Datasets:
module stringlengths 21 82.9k |
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module buffer_test();
localparam B = 1024;
reg CLOCK_50, rst;
reg [31:0] counter;
reg new_sample_val;
wire [31:0] pitch_shift_out;
wire pitch_shift_val;
// make reset
initial begin
CLOCK_50 = 1'b0;
rst = 1'b0;
counter = 32'b0;
new_sample_val = 1'b0;
... |
module EBABWrapper
(
/*AUTOARG*/
// Outputs
bus_byte_enable, bus_read, bus_write, bus_write_data, bus_addr,
// Inputs
clk, rst, out_sel, delta_mode_left, delta_mode_right, bus_ack,
bus_read_data, delta_left, delta_right, triangle_wave_max_left,
triangle_wave_max_right
);
input clk, rst, ou... |
module DE1_SoC_Computer
(
////////////////////////////////////
// FPGA Pins
////////////////////////////////////
// Clock pins
CLOCK_50,
CLOCK2_50,
CLOCK3_50,
CLOCK4_50,
// ADC
ADC_CS_N,
ADC_DIN,
ADC_DOUT,
ADC_SCLK,
// Audio
AUD_ADCDAT,
AUD_ADCLRCK,
AUD_BCLK,
A... |
module butter_test();
reg rst, CLOCK_50;
reg [31:0] counter;
reg audio_input_ready;
// DDS update signal for testing
reg [31:0] dds_accum;
// DDS LUT
reg [31:0] sine_out;
wire [31:0] my_out;
// make reset
initial begin
counter = 32'b0;
CLOCK_50 = 1'b0;
audio_inpu... |
module sync_rom (clock, address, sine);
input clock;
input [7:0] address;
output [15:0] sine;
reg signed [15:0] sine;
always@(posedge clock)
begin
case(address)
8'h00: sine = 16'h0000;
8'h01: sine = 16'h0192;
8'h02: sine = 16'h0323;
8'h03: sine = 16'h0... |
module RAM_512_18
#(parameter B = 1024)
(
output signed [31:0] q,
input signed [31:0] data,
input [($clog2(B)-1):0] wraddress, rdaddress,
input wren, rden, clock
);
reg [8:0] read_address_reg;
reg signed [31:0] mem [(B-1):0] /*synthesis rams... |
module buffer
#(parameter B=1024)
(
// inputs
clk,
rst,
delta,
new_sample_val,
new_sample_data,
out_sel,
delta_mode, // indicates whether to use fixed or varying delta
triangle_wave_max,
// outputs
pitch_shift_out,
pitch_shift_val
);
input clk, rst, new_sampl... |
module project_top();
reg rst, clk;
wire [31:0] bus_addr; // Avalon address
wire [3:0] bus_byte_enable; // four bit byte read/write mask
wire bus_read; // high when requesting data
wire bus_write; // high when writing data
wire [31:0] bus_write_data; // data... |
module delta_rom (clock, address, delta_out);
input clock;
input [9:0] address;
output [31:0] delta_out;
reg [31:0] delta_out;
always@(posedge clock)
begin
case(address)
10'd0: delta_out = 32'b00010000000000000000000000000000;
10'd1: delta_out = 32'b000100000010000... |
module IIR6_32bit_fixed (audio_out, audio_in,
scale,
b1, b2, b3, b4, b5, b6, b7,
a2, a3, a4, a5, a6, a7,
clk, data_val, rst, audio_out_val);
// The filter is a "Direct Form II Transposed"
//
// a(1)*y(n) = b... |
module signed_mult (out, a, b);
output [31:0] out;
input signed [31:0] a;
input signed [31:0] b;
wire signed [31:0] out;
wire signed [63:0] mult_out;
assign mult_out = a * b;
//assign out = mult_out[33:17];
assign out = {mult_out[63], mult_out[59:30]};
endmodule |
module cache(clk,
rst,
i_p_addr,
i_p_byte_en,
i_p_writedata,
i_p_read,
i_p_write,
o_p_readdata,
o_p_readdata_valid,
o_p_waitrequest,
o_m_addr,
o_m_byte_... |
module set(clk,
rst,
entry,
o_tag,
writedata,
byte_en,
write,
word_en,
readdata,
wb_addr,
hit,
modify,
miss,
valid,
read_miss);
parameter cache_entry = 14;
... |
module cache(clk,
rst,
i_p_addr,
i_p_byte_en,
i_p_writedata,
i_p_read,
i_p_write,
o_p_readdata,
o_p_readdata_valid,
o_p_waitrequest,
o_m_addr,
o_m_byte_... |
module set(clk,
rst,
entry,
o_tag,
writedata,
byte_en,
write,
word_en,
readdata,
wb_addr,
hit,
modify,
miss,
valid,
read_miss);
parameter cache_entry = 14;
... |
module cache(clk,
rst,
i_p_addr,
i_p_byte_en,
i_p_writedata,
i_p_read,
i_p_write,
o_p_readdata,
o_p_readdata_valid,
o_p_waitrequest,
o_m_addr,
o_m_byte_... |
module config_ctrl(clk,
rst,
entry,
o_tag,
writedata,
byte_en,
word_en,
write,
readdata0,
readdata1,
readdata2,
... |
module set(clk,
rst,
entry,
o_tag,
writedata,
byte_en,
write,
word_en,
readdata,
wb_addr,
hit,
miss,
dirty,
valid,
read_miss,
flash);
parameter cache... |
module simple_ram
#(parameter width = 1,
parameter widthad = 1
)
(
input clk,
input [widthad-1:0] wraddress,
input wren,
input [width-1:0] data,
input [widthad-1:0] rdaddress,
output reg [width-1:0] q
);
reg [width-1:0] mem [(2**widthad)-1:0]... |
module uart(
input clk, // The master clock for this module
input rst, // Synchronous reset.
input rx, // Incoming serial line
output tx, // Outgoing serial line
input transmit, // Signal to transmit
input [7:0] tx_byte, // Byte to transmit
output received, // Indicated that a byte has been ... |
module testbench;
reg clk = 1;
reg resetn = 0;
wire trap;
always #5 clk = ~clk;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
end
repeat (100) @(posedge clk);
resetn <= 1;
repeat (1000) @(posedge clk);
$finish;
end
wire mem_valid;
wire m... |
module testbench #(
parameter AXI_TEST = 0,
parameter VERBOSE = 0
);
reg clk = 1;
reg resetn = 0;
wire trap;
always #5 clk = ~clk;
initial begin
repeat (100) @(posedge clk);
resetn <= 1;
end
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
end... |
module picorv32_wrapper #(
parameter AXI_TEST = 0,
parameter VERBOSE = 0
) (
input clk,
input resetn,
output trap,
output trace_valid,
output [35:0] trace_data
);
wire tests_passed;
reg [31:0] irq = 0;
reg [15:0] count_cycle = 0;
always @(posedge clk) count_cycle <= resetn ? count_cycle + 1 : 0;
always @*... |
End of preview. Expand in Data Studio
Original dataset size: 21725 Number of duplicate clusters: 2951 Files in duplicate cluster: 8054 Unique files in duplicate cluster: 3781 Filtered dataset size: 17452 Time to deduplicate dataset: 7.37 Size of deduplicated dataset: 17452, old dataset size 21725
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