module stringlengths 21 82.9k |
|---|
module aibio_3bit_bin_to_therm
(
//--------Supply pins---------//
input vddcq,
input vss,
//-------Input pins----------//
input [2:0] b,
//-------Outptu pins---------//
output reg [6:0] t
);
always @(b)
case(b)
3'b000 : t = 7'b000_0000;
3'b001 : t = 7'b000_0001;
3'b010 : t = 7'b000_0011;... |
module aibio_bias_trim
(
//-------Supply pins---------//
input vddcq,
input vss,
//-------Input pins---------//
input [2:0]i_bias_trim,
input i_pbias,
input i_nbias,
//--------Output pins----------//
output [2:0]o_pbias_trim,
output [2:0]o_nbias_trim
);
//assign o_pbias_trim = ~(i_bias_trim);
... |
module aib_avmm_glue_logic(
// Inputs
input [23:0] i_waitreq_ch, // Wait request of each channel
input [23:0] i_rdatavld_ch, // Read data valid of each channel
input [31:0] o_rdata_ch_0, // Channel 0 read data bus
input [31:0] o_rdata_ch_1, // Channel 1 read data bus
input [31:0] o_rdata_ch_2, ... |
module aib_fifo_rdata_ored #(
parameter DWIDTH = 80, // FIFO Input data width
parameter DEPTH = 3 // FIFO Depth
)
(
// Output
output reg [DWIDTH-1:0] fifo_rdata,
// Input
input [DEPTH-1:0][DWIDTH-1:0] fifo_out_sel
);
integer n;
always @(*)
begin
fifo_rdata = {DWIDTH{1'b0}};
for(n = 0; n < DEPTH; n ... |
module aib_rxfifo_rd_dpath #(
parameter DWIDTH = 320,
parameter DEPTH = 16,
parameter DEPTH4 = DEPTH*4
)
(
output [DWIDTH-1:0] rdata_sync_ff, // Read data synchronized
input [DEPTH4-1:0] fifo_rd_en, // FIFO element selector
input [1:0] r_fifo_mode, // FIFO mode
input m_gen2_mode, /... |
module aib_txfifo_rd_dpath #(
parameter DINW = 320,
parameter DOUTW = 80,
parameter DEPTH = 16,
parameter DEPTH4 = DEPTH * 4
)
(
output [DOUTW-1:0] rdata_sync_ff, // Read data synchronized
input [DEPTH4-1:0] fifo_rd_en, // FIFO element selector
input [DEPTH-1:0][DINW-1:0] fifo_data_as... |
module aib_tx_bert #(
parameter [0:0] BERT_BUF_MODE_EN = 1 // Enables Buffer mode for BERT
)
(
input clk, // TX BERT clock
input rstn, // Active low asynchronous reset
input [ 3:0] tx_start_pulse, // Start pulse to enable LFSR and Pattern
input [ 3:0] tx_rst_pulse, ... |
module emib_ch_m2s2 (
inout [101:0] s_aib,
inout [101:0] m_aib
);
genvar i;
generate
for (i=0; i<102; i=i+1) begin: aib_io_conn
aliasv xaliasv95 (
.PLUS(m_aib[i]),
.MINUS(s_aib[101-i])
);
end
endgenerate
endmodule |
module emib_m2s2 # ( parameter ROTATE = 0) (
inout [101:0] s_ch0_aib,
inout [101:0] s_ch1_aib,
inout [101:0] s_ch2_aib,
inout [101:0] s_ch3_aib,
inout [101:0] s_ch4_aib,
inout [101:0] s_ch5_aib,
inout [101:0] s_ch6_aib,
inout [101:0] s_ch7_aib,
inout [101:0] s_ch8_aib,
inout [101:0] s_ch9_aib,
inout [... |
module emib_ch_m2s1 (
inout [95:0] s_aib,
inout [101:0] m_aib
);
wire tie_low = 1'b0;
aliasv xaliasv101 (
.PLUS(m_aib[101]),
.MINUS()
);
aliasv xaliasv100 (
.PLUS(m_aib[100]),
.MINUS()
);
aliasv xaliasv99 (
.PLUS(m_aib[99]),
.MINUS()
);
aliasv xaliasv98 (
.PLUS(m_aib[98]),
.MINUS()
);
... |
module emib_ch_m1s2 (
inout [95:0] m_aib,
inout [101:0] s_aib
);
wire tie_low = 1'b0;
wire tie_hi = 1'b1;
aliasv xaliasv101 (
.MINUS(s_aib[101]),
.PLUS()
);
aliasv xaliasv100 (
.MINUS(s_aib[100]),
.PLUS()
);
aliasv xaliasv99 (
.MINUS(s_aib[99]),
.PLUS()
);
aliasv xaliasv98 (
.MINUS(s_aib[... |
module emib_m1s2 # ( parameter ROTATE = 0) (
inout [101:0] s_ch0_aib,
inout [101:0] s_ch1_aib,
inout [101:0] s_ch2_aib,
inout [101:0] s_ch3_aib,
inout [101:0] s_ch4_aib,
inout [101:0] s_ch5_aib,
inout [101:0] s_ch6_aib,
inout [101:0] s_ch7_aib,
inout [101:0] s_ch8_aib,
inout [101:0] s_ch9_aib,
inout [... |
module emib_m2s1 (
inout [95:0] s_ch0_aib,
inout [95:0] s_ch1_aib,
inout [95:0] s_ch2_aib,
inout [95:0] s_ch3_aib,
inout [95:0] s_ch4_aib,
inout [95:0] s_ch5_aib,
inout [95:0] s_ch6_aib,
inout [95:0] s_ch7_aib,
inout [95:0] s_ch8_aib,
inout [95:0] s_ch9_aib,
inout [95:0] s_ch10_aib,
inout [95:... |
module lut_C
(
input [7:0] x,
output [7:0] x_max,
output reg [15:0] y
);
assign x_max = 182;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000010001100101;
2: y = 16'b0000100011001000;
3: y = 16'b0000110100101001;
4: y = 16'... |
module lut_Cs
(
input [7:0] x,
output [7:0] x_max,
output reg [15:0] y
);
assign x_max = 172;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000010010100110;
2: y = 16'b0000100101001010;
3: y = 16'b0000110111101011;
4: y = 16... |
module lut_D
(
input [7:0] x,
output [7:0] x_max,
output reg [15:0] y
);
assign x_max = 162;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000010011101111;
2: y = 16'b0000100111011100;
3: y = 16'b0000111011000101;
4: y = 16'... |
module lut_Ds
(
input [7:0] x,
output [7:0] x_max,
output reg [15:0] y
);
assign x_max = 153;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000010100111001;
2: y = 16'b0000101001101111;
3: y = 16'b0000111110100001;
4: y = 16... |
module lut_E
(
input [7:0] x,
output [7:0] x_max,
output reg [15:0] y
);
assign x_max = 144;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000010110001011;
2: y = 16'b0000101100010100;
3: y = 16'b0001000010011000;
4: y = 16'... |
module lut_F
(
input [7:0] x,
output [7:0] x_max,
output reg [15:0] y
);
assign x_max = 136;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000010111011110;
2: y = 16'b0000101110111001;
3: y = 16'b0001000110001110;
4: y = 16'... |
module lut_Fs
(
input [7:0] x,
output [7:0] x_max,
output reg [15:0] y
);
assign x_max = 128;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000011000111011;
2: y = 16'b0000110001110011;
3: y = 16'b0001001010100011;
4: y = 16... |
module lut_G
(
input [6:0] x,
output [6:0] x_max,
output reg [15:0] y
);
assign x_max = 121;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000011010010111;
2: y = 16'b0000110100101001;
3: y = 16'b0001001110110011;
4: y = 16'... |
module lut_Gs
(
input [6:0] x,
output [6:0] x_max,
output reg [15:0] y
);
assign x_max = 114;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000011011111101;
2: y = 16'b0000110111110101;
3: y = 16'b0001010011100011;
4: y = 16... |
module lut_A
(
input [6:0] x,
output [6:0] x_max,
output reg [15:0] y
);
assign x_max = 108;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000011101100000;
2: y = 16'b0000111010111001;
3: y = 16'b0001011000000110;
4: y = 16'... |
module lut_As
(
input [6:0] x,
output [6:0] x_max,
output reg [15:0] y
);
assign x_max = 101;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000011111100001;
2: y = 16'b0000111110111011;
3: y = 16'b0001011110000101;
4: y = 16... |
module lut_B
(
input [6:0] x,
output [6:0] x_max,
output reg [15:0] y
);
assign x_max = 96;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000100001001001;
2: y = 16'b0001000010001001;
3: y = 16'b0001100010110111;
4: y = 16'b... |
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