module stringlengths 21 82.9k |
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module buffer_test();
localparam B = 1024;
reg CLOCK_50, rst;
reg [31:0] counter;
reg new_sample_val;
wire [31:0] pitch_shift_out;
wire pitch_shift_val;
// make reset
initial begin
CLOCK_50 = 1'b0;
rst = 1'b0;
counter = 32'b0;
new_sample_val = 1'b0;
... |
module EBABWrapper
(
/*AUTOARG*/
// Outputs
bus_byte_enable, bus_read, bus_write, bus_write_data, bus_addr,
// Inputs
clk, rst, out_sel, delta_mode_left, delta_mode_right, bus_ack,
bus_read_data, delta_left, delta_right, triangle_wave_max_left,
triangle_wave_max_right
);
input clk, rst, ou... |
module DE1_SoC_Computer
(
////////////////////////////////////
// FPGA Pins
////////////////////////////////////
// Clock pins
CLOCK_50,
CLOCK2_50,
CLOCK3_50,
CLOCK4_50,
// ADC
ADC_CS_N,
ADC_DIN,
ADC_DOUT,
ADC_SCLK,
// Audio
AUD_ADCDAT,
AUD_ADCLRCK,
AUD_BCLK,
A... |
module butter_test();
reg rst, CLOCK_50;
reg [31:0] counter;
reg audio_input_ready;
// DDS update signal for testing
reg [31:0] dds_accum;
// DDS LUT
reg [31:0] sine_out;
wire [31:0] my_out;
// make reset
initial begin
counter = 32'b0;
CLOCK_50 = 1'b0;
audio_inpu... |
module sync_rom (clock, address, sine);
input clock;
input [7:0] address;
output [15:0] sine;
reg signed [15:0] sine;
always@(posedge clock)
begin
case(address)
8'h00: sine = 16'h0000;
8'h01: sine = 16'h0192;
8'h02: sine = 16'h0323;
8'h03: sine = 16'h0... |
module RAM_512_18
#(parameter B = 1024)
(
output signed [31:0] q,
input signed [31:0] data,
input [($clog2(B)-1):0] wraddress, rdaddress,
input wren, rden, clock
);
reg [8:0] read_address_reg;
reg signed [31:0] mem [(B-1):0] /*synthesis rams... |
module buffer
#(parameter B=1024)
(
// inputs
clk,
rst,
delta,
new_sample_val,
new_sample_data,
out_sel,
delta_mode, // indicates whether to use fixed or varying delta
triangle_wave_max,
// outputs
pitch_shift_out,
pitch_shift_val
);
input clk, rst, new_sampl... |
module project_top();
reg rst, clk;
wire [31:0] bus_addr; // Avalon address
wire [3:0] bus_byte_enable; // four bit byte read/write mask
wire bus_read; // high when requesting data
wire bus_write; // high when writing data
wire [31:0] bus_write_data; // data... |
module delta_rom (clock, address, delta_out);
input clock;
input [9:0] address;
output [31:0] delta_out;
reg [31:0] delta_out;
always@(posedge clock)
begin
case(address)
10'd0: delta_out = 32'b00010000000000000000000000000000;
10'd1: delta_out = 32'b000100000010000... |
module IIR6_32bit_fixed (audio_out, audio_in,
scale,
b1, b2, b3, b4, b5, b6, b7,
a2, a3, a4, a5, a6, a7,
clk, data_val, rst, audio_out_val);
// The filter is a "Direct Form II Transposed"
//
// a(1)*y(n) = b... |
module signed_mult (out, a, b);
output [31:0] out;
input signed [31:0] a;
input signed [31:0] b;
wire signed [31:0] out;
wire signed [63:0] mult_out;
assign mult_out = a * b;
//assign out = mult_out[33:17];
assign out = {mult_out[63], mult_out[59:30]};
endmodule |
module cache(clk,
rst,
i_p_addr,
i_p_byte_en,
i_p_writedata,
i_p_read,
i_p_write,
o_p_readdata,
o_p_readdata_valid,
o_p_waitrequest,
o_m_addr,
o_m_byte_... |
module set(clk,
rst,
entry,
o_tag,
writedata,
byte_en,
write,
word_en,
readdata,
wb_addr,
hit,
modify,
miss,
valid,
read_miss);
parameter cache_entry = 14;
... |
module cache(clk,
rst,
i_p_addr,
i_p_byte_en,
i_p_writedata,
i_p_read,
i_p_write,
o_p_readdata,
o_p_readdata_valid,
o_p_waitrequest,
o_m_addr,
o_m_byte_... |
module set(clk,
rst,
entry,
o_tag,
writedata,
byte_en,
write,
word_en,
readdata,
wb_addr,
hit,
modify,
miss,
valid,
read_miss);
parameter cache_entry = 14;
... |
module cache(clk,
rst,
i_p_addr,
i_p_byte_en,
i_p_writedata,
i_p_read,
i_p_write,
o_p_readdata,
o_p_readdata_valid,
o_p_waitrequest,
o_m_addr,
o_m_byte_... |
module config_ctrl(clk,
rst,
entry,
o_tag,
writedata,
byte_en,
word_en,
write,
readdata0,
readdata1,
readdata2,
... |
module set(clk,
rst,
entry,
o_tag,
writedata,
byte_en,
write,
word_en,
readdata,
wb_addr,
hit,
miss,
dirty,
valid,
read_miss,
flash);
parameter cache... |
module simple_ram
#(parameter width = 1,
parameter widthad = 1
)
(
input clk,
input [widthad-1:0] wraddress,
input wren,
input [width-1:0] data,
input [widthad-1:0] rdaddress,
output reg [width-1:0] q
);
reg [width-1:0] mem [(2**widthad)-1:0]... |
module uart(
input clk, // The master clock for this module
input rst, // Synchronous reset.
input rx, // Incoming serial line
output tx, // Outgoing serial line
input transmit, // Signal to transmit
input [7:0] tx_byte, // Byte to transmit
output received, // Indicated that a byte has been ... |
module testbench;
reg clk = 1;
reg resetn = 0;
wire trap;
always #5 clk = ~clk;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
end
repeat (100) @(posedge clk);
resetn <= 1;
repeat (1000) @(posedge clk);
$finish;
end
wire mem_valid;
wire m... |
module testbench #(
parameter AXI_TEST = 0,
parameter VERBOSE = 0
);
reg clk = 1;
reg resetn = 0;
wire trap;
always #5 clk = ~clk;
initial begin
repeat (100) @(posedge clk);
resetn <= 1;
end
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
end... |
module picorv32_wrapper #(
parameter AXI_TEST = 0,
parameter VERBOSE = 0
) (
input clk,
input resetn,
output trap,
output trace_valid,
output [35:0] trace_data
);
wire tests_passed;
reg [31:0] irq = 0;
reg [15:0] count_cycle = 0;
always @(posedge clk) count_cycle <= resetn ? count_cycle + 1 : 0;
always @*... |
module axi4_memory #(
parameter AXI_TEST = 0,
parameter VERBOSE = 0
) (
/* verilator lint_off MULTIDRIVEN */
input clk,
input mem_axi_awvalid,
output reg mem_axi_awready,
input [31:0] mem_axi_awaddr,
input [ 2:0] mem_axi_awprot,
input mem_axi_wvalid,
outp... |
module testbench #(
parameter VERBOSE = 0
);
reg clk = 1;
reg resetn = 1;
wire trap;
always #5 clk = ~clk;
initial begin
repeat (100) @(posedge clk);
resetn <= 0;
end
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
end
repeat (1000000) @(pos... |
module picorv32_wrapper #(
parameter VERBOSE = 0
) (
input wb_clk,
input wb_rst,
output trap,
output trace_valid,
output [35:0] trace_data
);
wire tests_passed;
reg [31:0] irq = 0;
wire mem_instr;
reg [15:0] count_cycle = 0;
always @(posedge wb_clk) count_cycle <= !wb_rst ? count_cycle + 1 : 0;
always @* ... |
module wb_ram #(
parameter depth = 256,
parameter memfile = "",
parameter VERBOSE = 0
) (
input wb_clk_i,
input wb_rst_i,
input [31:0] wb_adr_i,
input [31:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input wb_cyc_i,
input wb_stb_i,
output reg wb_ack_o,
output reg [31:0] wb_dat_o,
input mem_instr,
... |
module layer_0(
input clk,
input reset_n,
input [7:0] input_spike,
output [7:0] output_spike
);
parameter NUM_NEURONS = 8;
reg [NUM_NEURONS-1:0] spike_layer_0_potential_reg[NUM_NEURONS-1:0];
wire [NUM_NEURONS-1:0] spike_lay... |
module controller(
input clk,
input reset_n,
input [7:0] input_spike,
output [7:0] output_spike
);
wire [7:0] output_spike_layer_0;
layer_0 uut_layer_0 (
.clk(clk), .reset_n(reset_n),
.input_spike(input_spike),
.output_spike(output_... |
module layer_1(
input clk,
input reset_n,
input [7:0] input_spike,
output [7:0] output_spike
);
parameter NUM_NEURONS = 8;
reg [NUM_NEURONS-1:0] spike_layer_1_potential_reg[NUM_NEURONS-1:0];
wire [NUM_NEURONS-1:0] spike_lay... |
module tb_leaky_integrate_fire;
reg clk;
reg reset_n;
reg spike_in_0, spike_in_1, spike_in_2, spike_in_3, spike_in_4, spike_in_5, spike_in_6, spike_in_7;
reg [7:0] weight_0, weight_1, weight_2, weight_3, weight_4, weight_5, weight_6, weight_7;
reg [7:0] ... |
module leaky_integrate_fire(
input clk,
input reset_n,
input [7:0] spike_in,
input [63:0] weight_0,
input [63:0] weight_1,
input [63:0] weight_2,
input [63:0] weight_3,
input [63:0] weight_4,
input [63:... |
module tb_controller;
reg clk, reset_n;
reg [7:0] input_spike;
wire [7:0] output_spike;
parameter STEP = 10;
controller uut_controller (
.clk(clk), .reset_n(reset_n),
.input_spike(input_spike),
.output_spike(output_spike)
);... |
module cond ( nzcv, condition_code, will_this_be_executed);
input wire[3:0] nzcv;
input wire[3:0] condition_code;
output reg will_this_be_executed;
always @* begin
case(condition_code)
0: begin //EQ
if(nzcv[2] == 1) will_this_be_executed = 1;
else will_this_be_executed = 0;
end
1: begin //NE
if(nzcv[2] == 0... |
module bshift(instr_bit_25,imm_value, Rm, Rs, operand2, cin, c_to_alu, direct_data, use_shifter);
parameter n=32;
input [n-1:0] direct_data;
input use_shifter;
input instr_bit_25; // bit no. 25 in the instr
input [11:0] imm_value; // bits 11-0 in instr
input [n-1:0] Rm;
input [n-1:0] Rs;
output [n-1:0] operand2... |
module register_file(in_address1,in_address2,in_address3,in_address4,
out_data1,out_data2,out_data3,out_data4,
write_address,write_data,write_enable,
write_address2, write_data2, write_enable2,
pc, pc_update, pc_write,
cspr, cspr_write, cspr_update, clk );
parameter N = 32; //regist... |
module test;
reg clk;
DeepPipeline arm(clk);
initial
begin
clk = 1;
$dumpfile("test.vcd");
$dumpvars(0,test);
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
... |
module instr_cache(PC,instr,read_enable,clk);
parameter instr_size = 32;
parameter N = 32;
parameter addr_size = 8; //pc supplies address to instr_cache, so addr_size is same as addr_width here. We ignore msb bits from r15.
reg [instr_size-1:0] M [256-1:0]; //2^addr_size-1, 32 bit instructions
input read_enable;
input... |
module data_cache(data_address,in_data,out_data,read_enable,write_enable,clk,isByte);
parameter data_width = 8; //size of each data read, will be of width 16, i.e, half word by default.
parameter N =32;
parameter addr_width = 12; //It determines the number of data (half)words in memory
reg [data_width-1:0] M [2^addr_w... |
module register_test;
reg[3:0] read_address;
reg[3:0] write_address;
reg[31:0] write_data;
reg write_enable = 0;
reg[31:0] pc_update;
reg pc_write;
reg clk;
wire[31:0] out_data_1;
wire[31:0] cspr;
wire[31:0] pc;
register_file RegisterFile( //inputs
.in_address1(read_address),
.in_address2(),
... |
module alu(opcode, operand_1, operand_2, result, nzcv_old, nzcv, c_from_shifter, isWriteback);
parameter N = 32;
input[3:0] opcode; //opcode of operation
input wire [N-1:0] operand_1; //operands:
input wire [N-1:0] operand_2;
input wire[3:0] nzcv_old; //old nzcv
input wire c_from_shifter;//this is carry flag from sh... |
module SOC (
input wire CLK, // system clock
input wire RESET,// reset button
output reg [3:0] LEDS, // system LEDs
output wire TXD // UART transmit
);
wire clk;
wire resetn;
wire [31:0] IO_mem_addr;
wire [31:0] IO_mem_rdata;
wire [31:0] IO_mem_wdata;
wire ... |
module Clockworks
(
input wire CLK, // clock pin of the board
input wire RESET, // reset pin of the board
output wire clk, // (optionally divided) clock for the design.
// divided if SLOW is different from zero.
output wire resetn // (optionally timed) negative reset for the des... |
module Processor (
input wire clk,
input wire resetn,
output wire [31:0] IO_mem_addr, // IO memory address
input wire [31:0] IO_mem_rdata, // data read from IO memory
output wire [31:0] IO_mem_wdata, // data written to IO memory
output wire IO_mem_wr // IO write flag
... |
module OneShot(
input pulse,
input clk,
input rst,
output reg out
);
initial out = 0;
parameter waiting_l = 2'b00, on = 2'b01, waiting_h = 2'b10;
reg[1:0] next_state, current_state;
always @ (posedge clk or posedge rst) begin
if(rst) begin
current_state <= waiting_l;
end
else begin
current_s... |
module tx_test;
// Inputs
wire rx;
reg [10:0] address;
reg clk;
reg baud_clk;
reg rst;
reg [63:0] data;
reg send_data;
reg rxing;
// Outputs
wire tx;
// Instantiate the Unit Under Test (UUT)
tx_container uut (
.tx(tx),
.txing(txing),
.rx(rx),
.rxing(rxing),
.address(address),
.clk(clk),
... |
module shift_reg(
input rx,
output reg[(reg_length-1):0] shifted_bus,
output reg finished_rx,
input rst,
input baud_clk
);
parameter reg_length = 150;
initial finished_rx = 0;
parameter idle = 2'b00, reading = 2'b01, finished = 2'b10, finished_and_waiting = 2'b11;
reg[1:0] current_state, nex... |
module can_tx(
output reg tx,
output reg can_bitstuff,
output reg txing,
input rx,
input[10:0] address,
input clk,
input baud_clk,
input rst,
input [63:0] data,
input send_data,
input bitstuffed_output,
input clear_to_tx
);
assign rx_buf = rx;
parameter all_ones = 15'b111111111111111;
parameter idle... |
module CANIPCORETEST;
// Inputs
reg can_clk;
reg can_phy_rx;
reg bus2ip_reset;
reg bus2ip_rnw;
reg bus2ip_cs;
reg sys_clk;
reg [0:5] bus2ip_addr;
reg [0:31] bus2ip_data;
// Outputs
wire ip2bus_intrevent;
wire ip2bus_error;
wire ip2bus_ack;
wire can_phy_tx;
wire [0:31] ip2bus_data;
// Instantiate the ... |
module tx_container(
output reg tx,
output txing,
input rx,
input rxing,
input[10:0] address,
input clk,
input baud_clk,
input rst,
input [63:0] data,
input send_data
);
parameter init = 2'h0, ones = 2'h1, zeros = 2'h2;
assign clear_to_tx =1;
reg bit_stuffing = 0;
reg[1:0] c_state=0, n_state=0, p_... |
module BaudGen(clk,rst,baud_clk);
input clk,rst;
output reg baud_clk;
//EndCount is equal to clk frequency/baud frequency
// Therefore 400MHz/500kHz = 800
parameter EndCount = 10'd800;
reg[9:0] count = 0;
always@(posedge clk)begin
if(rst == 1) begin
count <=10'd0;
baud_clk <= 10'd0;
end
else if(count == EndCou... |
module Tx_test_internal;
// Inputs
reg [10:0] address;
reg clk;
reg baud_clk;
reg rst;
reg [63:0] data;
reg send_data;
reg clear_to_tx;
assign rx = tx;
assign bitstuffed_output = tx;
// Outputs
wire tx;
wire can_bitstuff;
wire txing;
// Instantiate the Unit Under Test (UUT)
can_tx uut (
.tx(tx),
... |
module Main(
output CAN_TX,
input CAN_RX,
input RESET,
input CLOCK_SIGNAL_IN,
input send_data,
input[7:0] transmit_data
);
wire[63:0] tx_data;
wire txing;
assign tx_data = {8{transmit_data}};
//Device address, arbitrarily chosen
parameter address = 11'h25, rxing = 1'b1;
//Clock Generator (100MHz in... |
module Main_test;
// Inputs
assign CAN_RX = CAN_TX;
reg RESET;
reg CLOCK_SIGNAL_IN;
reg send_data;
reg [7:0] transmit_data;
// Outputs
wire CAN_TX;
// Instantiate the Unit Under Test (UUT)
Main uut (
.CAN_TX(CAN_TX),
.CAN_RX(CAN_RX),
.RESET(RESET),
.CLOCK_SIGNAL_IN(CLOCK_SIGNAL_IN),
.send_data... |
module OneShotTest;
// Inputs
reg pulse;
reg clk;
reg rst;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
OneShot uut (
.pulse(pulse),
.clk(clk),
.rst(rst),
.out(out)
);
initial begin
// Initialize Inputs
pulse = 0;
clk = 0;
rst = 1;
// Wait 100 ns for global reset to ... |
module BitshiftTest;
// Inputs
reg rx;
reg rst;
reg baud_clk;
// Outputs
wire [149:0] shifted_bus;
// Instantiate the Unit Under Test (UUT)
shift_reg uut (
.rx(rx),
.shifted_bus(shifted_bus),
.finished_rx(finished_rx),
.rst(rst),
.baud_clk(baud_clk)
);
initial begin
// Initialize Inputs
rx... |
module top (
input clk,
input rst,
inout led,
inout [5:0] lcd
);
parameter EXCEPTION_HANDLING = 0;
// self-reset w/ self-detect logic
// self-reset just start w/ a value and decrement it until zero; at same time, sample the
// default external reset value at startup, supposing that y... |
module butterflyRadix4First(
input clk,
input en,
input[15:0] re_0,
input[15:0] re_1,
input[15:0] re_2,
input[15:0] re_3,
input[15:0] re_4,
input[15:0] re_5,
input[15:0] re_6,
input[15:0] re_7,
input[15:0] re_8... |
module dit
#(
// Length of FFT vector.
parameter N = 16,
// Base two log of N
parameter NLOG2 = 4,
// Number of bits in vector values (double this value for a complex number).
parameter X_WDTH = 8,
// Number of bits in twiddle factor values. (must be equal to X_WDTH at the moment)... |
module complexAddRadix_4(
input clk,
input [15:0] x1_re,
input [15:0] x1_im,
input [15:0] x2_re,
input [15:0] x2_im,
input [15:0] x3_re,
input [15:0] x3_im,
input [15:0] x4_re,
input [15:0] x4_im,
output [15:0] re_0,
... |
module butterflyRadix4Second(
input clk,
input[15:0] re_0,
input[15:0] re_1,
input[15:0] re_2,
input[15:0] re_3,
input[15:0] re_4,
input[15:0] re_5,
input[15:0] re_6,
input[15:0] re_7,
input[15:0] re_8,
... |
module butterfly
#(
// The width of m_in.
parameter M_WDTH = 0,
// The width of the input, output and twiddle factors.
parameter X_WDTH = 0
)
(
input wire clk,
input wire rst_n,
// m_in contains data that passes through this block with n... |
module Deserializer(
clk,
reset,
datain,
// first 16 is real last16 is imaginary
dataout0,
dataout1,
dataout2,
dataout3,
dataout4,
dataout5,
dataout6,
dataout7,
dataout8,
dataout9,
dataout10,
dataout11,... |
module FFT_top(
input clk,
input reset,
input [4:0] address,
output[15:0] out_re0,
output[15:0] out_re1,
output[15:0] out_re2,
output[15:0] out_re3,
output[15:0] out_re4,
output[15:0] out_re5,
output[15:0] out_re6,
output[15:0] out_re7,
... |
module FFT_top_tb;
// Inputs
reg clk;
reg reset;
reg [4:0] address;
reg [15:0] data_tmp11,data_tmp21,data_tmp31,data_tmp41,data_tmp51,data_tmp61,data_tmp71,data_tmp81,data_tmp91,data_tmp101,data_tmp111,data_tmp121,data_tmp131,data_tmp141,data_tmp151,data_tmp161;
reg [15:0] data_tmp12,data_tmp22,data_tmp32,data_t... |
module butterflyUnitRadix4(
input clk,
input[16:0] cos0,
input[16:0] sin0,
input[16:0] cos1,
input[16:0] sin1,
input[16:0] cos2,
input[16:0] sin2,
input[15:0] x1_re,
input[15:0] x1_im,
... |
module FFT16Radix4(
);
endmodule |
module layer_1(
input sys_clk ,
input sys_rst_n ,
input start_flag ,
output [32:0] data_out ,
output out_valid
);
wire [15:0] data_pic ;
wire pic_valid ;
pic_in... |
module vga(
input clk ,
input rst_n ,
input [23:0] data ,
output hs ,
output vs ,
output [ 9:0] x_pix ,
output [ 9:0] y_pix ,
output [23:0] color_rgb
);
parameter h_sync = 'd96 ;
p... |
module ann (
input clk ,
input rst_n ,
input signed [20:0] ina ,
input signed [20:0] inb ,
input signed [20:0] inc ,
input signed [20:0] ind ,
input valid_in,
output reg valid_out,
... |
module layer_2(
input sys_clk ,
input sys_rst_n ,
input start_flag ,
output [32:0] data_out ,
output out_valid
);
wire [32:0] data_max_out ;
wire data_max_valid ;... |
module pic_input(
input clk ,
input rst_n ,
input pic_start ,
output pic_out_valid ,
output [15:0] data_pic
);
wire [15:0] data_pic_out ;
reg [15:0] data_pic_reg ;
reg [ 9:0] ... |
module conv#(
/*parameter conv_w_0_0 = 16'd1 ,
parameter conv_w_0_1 = 16'd1 ,
parameter conv_w_0_2 = 16'd1 ,
parameter conv_w_0_3 = 16'd1 ,
parameter conv_w_0_4 = 16'd1 ,
parameter conv_w_1_0 = 16'd1 ,
parameter conv_w_1_1 = 16'd1 ,
parameter co... |
module maxpooling(
input clk ,
input rst_n ,
input valid_input ,
input [32:0] input_data ,
output out_valid ,
output [32:0] out_data
);
reg [ 9:0] count ;
r... |
module rainbow_generate(
input clk ,
input rst_n ,
input [ 9:0] x_pix ,
input [ 9:0] y_pix ,
output reg [23:0] data
);
parameter red = 24'hFF0000;
parameter green = 24'h00FF00;
parameter blue = 24'h0000FF;
parameter purple = 24'h9B30F... |
module relu(
input [32:0] A ,
output [32:0] B
);
assign B = A[32] == 1'b0 ? A : 33'b0;
endmodule |
module vga_top(
input sys_clk ,
input sys_rst_n ,
output hs ,
output vs ,
output clk_25MHz ,
output [23:0] color_rgb
);
wire [ 9:0] x_pix ;
wire [ 9:0] y_pix ;
wire [23:0] data ;
vga vga_inst(... |
module max_data_generate(
input clk ,
input rst_n ,
input data_start ,
output data_out_valid ,
output [32:0] data_out
);
wire [32:0] data_out_out ;
reg [32:0] data_out_reg ;
r... |
module top;
reg clk = 1;
reg tick_60hz = 0;
reg [15:0] keys = 0;
wire out;
cpu cpu0(.clk(clk),
.tick_60hz(tick_60hz),
.tick_next(1'b1),
.keys(keys),
.out(out),
.scr_busy(1'b0),
.scr_read(1'b0));
initial
forever #1 clk = ~clk;
initial... |
module cpu(input wire clk,
input wire tick_60hz,
input wire tick_next,
input wire [15:0] keys,
output wire out,
input wire scr_busy,
input wire scr_read,
input wire [7:0] scr_read_idx,
output reg [7:0] scr_read_byte,
outp... |
module gpu(input wire clk,
input wire draw,
input wire [11:0] addr,
input wire [3:0] lines,
input wire [5:0] x,
input wire [4:0] y,
output wire busy,
output reg collision,
output reg mem_read,
output reg [11:0] mem_read... |
module screen_bridge(input wire clk,
input wire tick_60hz,
input wire read,
input wire [5:0] row_idx,
input wire [6:0] column_idx,
output reg [7:0] data,
output reg ack,
ou... |
module top;
reg clk = 1;
reg draw = 0;
reg [11:0] addr;
reg [3:0] lines;
reg [5:0] x;
reg [4:0] y;
wire busy, collision;
wire mem_read;
wire [11:0] mem_read_idx;
wire [7:0] mem_read_byte;
wire mem_read_ack;
wire mem_write;
wire [11:0] mem_write_idx;
wire [7:0] mem_write_byte;
mem #(.de... |
module bcd(input wire [7:0] abc,
output wire [1:0] a,
output reg [3:0] b,
output reg [3:0] c);
assign a = abc >= 200 ? 2 : abc >= 100 ? 1 : 0;
wire [6:0] bc = abc - 100 * a;
// See Hacker's Delight, Integer division by constants:
// https://www.hackersdelight.org/divcMore.pdf
... |
module utils;
task assert_true;
input x;
begin
if (!x) begin
$error($time, " Assertion failed");
$finish_and_return(1);
end
end
endtask
task assert_equal;
input [31:0] x;
input [31:0] y;
begin
if (x != y) begin
$error($time, " %x != %x", x, y);
... |
module rng(input wire clk,
output wire [31:0] out,
input wire user_input);
reg [31:0] state = 42;
reg [31:0] next;
assign out = state;
always @(*) begin
next = state;
next = next ^ (next << 13);
next = next ^ (next >> 17);
next = next ^ (next << 5);
if (user_input) be... |
module mem(input wire clk,
input wire read,
input wire [11:0] read_idx,
output reg [7:0] read_byte,
output reg read_ack = 0,
input wire write,
input wire [11:0] write_idx,
input wire [7:0] write_byte);
parameter debug = 0;
reg [7:0] data... |
module top;
reg [7:0] abc = 0;
wire [1:0] a;
wire [3:0] b, c;
bcd bcd0(abc, a, b, c);
initial begin
$monitor($time, " %d -> %d %d %d", abc, a, b, c);
$dumpfile(`VCD_FILE);
$dumpvars;
repeat (256) begin
#1;
utils.assert_equal(abc, a * 100 + b * 10 + c);
utils.assert_true(a ... |
module ext18#(parameter DEPTH=18)(
input [DEPTH-1:0] a,
output reg [31:0] b
);
always@(a)
begin
if(a[DEPTH-1] == 1)//ÓзûºÅÀ©Õ¹
begin
b[31:0] = 32'hffffffff;
b[DEPTH-1:0] = a[DEPTH-1:0];
end
else
begin
b[... |
module cpu(
input clk,
input [31:0] inst,
input reset,
input [31:0] mrdata,
output [31:0] pc_out,
output [31:0] maddr,
output [31:0] mwdata,
output IM_R,
output DM_CS,
output DM_R,
output DM_W,
output [31:0]alu_r
);
wire RF_W,M1,M2,M3,M4,M5,M6,sign_ext,zero;
wire [2:0] ALUC;
wire[31:0] mux1_out,mux2_out,mux... |
module top_tb;
reg clk_in;
reg reset;
wire clk;
wire [31:0]pc;
wire [31:0]inst;
wire IM_R;
wire DM_CS;
wire DM_R;
wire DM_W;
wire [31:0]alu_r;
top uut(clk_in,reset,clk,pc,inst,addr,rdata,wdata,IM_R,DM_CS,DM_R,DM_W,alu_r);
// 不同的initial块是并行的，块内部顺序执行
initial
beg... |
module mux2x32#(parameter WIDTH=32)(
input [WIDTH-1:0] a,
input [WIDTH-1:0] b,
input select,
output reg [WIDTH-1:0] r
);
always @*
begin
case(select)
1'b0:
r=a;
1'b1:
r=b;
endcase
end
endmodule |
module imem(
input [31:0] a,
input IM_R,
output [31:0] rd
);
reg [31:0] RAM[2047:0];
initial
begin
$readmemh("imem.txt",RAM);
end
assign rd=(IM_R)?RAM[a[31:2]]:32'bx;
endmodule |
module decoder(
input [31:0] inst,
input clk,
input zero,
output IM_R,
output M3,
//output M4_0,
//output M4_1,
output M4,
output [2:0] ALUC,
output M2,
output RF_W,
//output RF_CLK,
output M5,
output M1,
output DM_CS,
output DM_R,
output DM_W,
output M6,
output sign_ext
);
wire [5:0] func=inst[5:0];
wire [5... |
module JOIN(
input [27:0] a,
input [3:0] b,
output [31:0] s
);
assign s[31:28]=b;
assign s[27:0]=a;
endmodule |
module ext16#(parameter DEPTH=16)(
input [DEPTH-1:0] a,
input sign_ext,
output reg [31:0] b
);
always@(a or sign_ext)
begin
if(sign_ext==1 && a[DEPTH-1]==1)
begin
b[31:0]=32'hffffffff;
b[DEPTH-1:0]=a[DEPTH-1:0];
end
else
begin
b[31:0]=32'h00000000;
b[DEPTH-1:0]=a[DEPTH-1:0];
end
end
en... |
module top(
input clk_in,
input reset,
output clk,
output [31:0]pc,
output [31:0]inst,
output [31:0]addr,
output [31:0]rdata,
output [31:0]wdata,
output IM_R,
output DM_CS,
output DM_R,
output DM_W,
output [31:0]alu_r
);
assign clk = clk_in;
cpu sccpu(clk_in,inst,reset,rdata,pc,addr,wdata,I... |
module ext5 #(parameter DEPTH=5)(
input [DEPTH-1:0] a,
output reg [31:0] b
);
always@(a)
begin
if(a[DEPTH-1]==1)
begin
b[31:0]=32'hffffffff;
b[DEPTH-1:0]=a[DEPTH-1:0];
end
else
begin
b[31:0]=32'h00000000;
b[DEPTH-1:0]=a[DEPTH-1:0];
end
end
endmodule |
module regfile(
input clk,
input rst,
input we,
input [4:0] raddr1,
input [4:0] raddr2,
input [4:0] waddr,
input [31:0] wdata,
output [31:0] rdata1,
output [31:0] rdata2
);
reg [31:0] array_reg[31:0];
integer i;
always@(posedge clk,posedge rst)
begin
if(rst)
begin
i=0;
while(i<32)
begin
array... |
module PC(
input clk,
input rst,
input [31:0] data_in,
output reg [31:0] data_out
);
always@(posedge clk,posedge rst)
begin
if(rst)
data_out<=32'b0;
else
data_out<=data_in;
end
endmodule |
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