module stringlengths 21 82.9k |
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module alu(
input [31:0] a,
input [31:0] b,
input [2:0] aluc,
output [31:0] r,
output zero
);
reg [31:0] r_1;
always@*
begin
case(aluc)
3'b000:
r_1=a+b;
3'b001:
r_1=a-b;
3'b010:
r_1=a|b;
3'b011:
r_1=b<<a[4:0];
default:;
endcase
end
assign r=r_1;
assign zero=r?1'b0:1'b1;
endmodule |
module dmem(
input clk,
input reset,
input CS,
input DM_W,
input DM_R,
input [31:0] addr,
input [31:0] wdata,
output [31:0] rdata
);
reg [31:0] ROM [2047:0];
initial
begin
$readmemh("D:/Downloads/CPU-master/rom.data",ROM);
end
assign rdata=(CS&DM_R)?ROM[addr[31:2]]:32'h0;
always @(posedge clk)
begin
if(... |
module testrotor();
reg [2:0] rotor_type_3 = 3'b010;
reg [2:0] rotor_type_2 = 3'b001;
reg [4:0] rotor_start_3 = 5'b00000;
reg [4:0] rotor_start_2 = 5'b00000;
reg [4:0] rotor_start_1 = 5'b00000;
reg [4:0] ring_position_3 = 5'b00000;
reg [4:0] ring_position_2 = 5'b00000;
reg [4:0] ring_position_1 = 5'b00000;
... |
module enigma_top
(input i_Clk, // Main Clock
input i_UART_RX, // UART RX Data
output o_UART_TX, // UART TX Data
output o_LED_1,
output o_LED_2,
output o_LED_3,
output o_LED_4,
// Segment1 is upper digit, Segment2 is lower digit
output o_Segment1_A,
output o_Segment1_B,
output... |
module test();
reg i_ready = 0;
reg [7:0] inputData;
reg r_Clock = 0;
wire o_ready;
wire [7:0] outputData;
integer i;
state_machine st(.i_clock(r_Clock),.i_ready(i_ready),.i_inputData(inputData),.o_ready(o_ready),.o_outputData(outputData));
always
#(5) r_Clock <= !r_Clock;
always @(posedge o_ready)
be... |
module rotorEncode #(parameter REVERSE = 0) (code, rotor_type, val);
input [4:0] code;
output reg [4:0] val;
input [2:0] rotor_type;
parameter MEM_INIT_FILE = "rotors.mem";
reg [4:0] rotor_data[0:415];
initial
if (MEM_INIT_FILE != "")
$readmemh(MEM_INIT_FILE, rotor_data);
always @*
val =... |
module hex_to_7seg
(
input i_Clk,
input [3:0] i_Value,
output o_Segment_A,
output o_Segment_B,
output o_Segment_C,
output o_Segment_D,
output o_Segment_E,
output o_Segment_F,
output o_Segment_G
);
reg [6:0] out = 7'b0000000;
always @... |
module decodeASCII(code, ascii);
input [4:0] code;
output [7:0] ascii;
assign ascii = 8'h41 + code;
endmodule |
module uart_rx
(
input i_Clock,
input i_Rx_Serial,
output o_Rx_DV,
output [7:0] o_Rx_Byte
);
parameter CLKS_PER_BIT = 87;
parameter s_IDLE = 3'b000;
parameter s_RX_START_BIT = 3'b001;
parameter s_RX_DATA_BITS = 3'b010;
parameter s_RX_STOP_BIT = 3'b011;
... |
module encodeASCII(ascii, code, valid);
input [7:0] ascii;
output [4:0] code;
output valid;
assign valid = ((ascii < 8'h41 || ascii > 8'h5A) && (ascii < 8'h61 || ascii > 8'h7A)) ? 0 : 1;
assign code = (ascii > 8'h5A) ? ascii - 8'h61 : ascii - 8'h41;
endmodule |
module rotor (
input clock,
output reg [4:0] rotor1,
output reg [4:0] rotor2,
output reg [4:0] rotor3,
input reset,
input rotate,
input [2:0] rotor_type_2,
input [2:0] rotor_type_3,
input [4:0] rotor_start_1,
input [4:0] rotor_start_2,
input [4:0] rotor_start_3
);
wire knock1;
wire knock2;
... |
module state_machine(
input i_clock,
input i_ready,
input [7:0] i_inputData,
output reg o_ready,
output reg [7:0] o_outputData,
output reg o_valid
);
reg [2:0] rotor_type_3 = 3'b010;
reg [2:0] rotor_type_2 = 3'b001;
reg [2:0] rotor_type_1 = 3'b000;
reg [4:0] rotor_start_3 = 5'b00000;
reg [4:0] rotor_star... |
module reflectorEncode (code, val, reflector_type);
input [4:0] code;
output reg [4:0] val;
input reflector_type;
always @*
begin
if (reflector_type == 1'b0)
begin
// Reflector B
case (code)
0 : val = "Y" - 8'h41;
1 : val = "R" - 8'h41;
2 : val = "U" - 8'h41;
3 : val = "H" - 8'h41... |
module plugboardEncode(input [4:0] code, output [4:0] val);
assign val = code;
endmodule |
module checkKnockpoints (position, knockpoint, rotor_type);
input [4:0] position;
output reg knockpoint;
input [2:0] rotor_type;
always @*
begin
knockpoint = 0;
case(rotor_type)
0 : if (position==16+1) knockpoint = 1;
1 : if (position== 4+1) knockpoint = 1;
2 : if (position==21+1) knockpoint = 1;
... |
module uart_tx
(
input i_Clock,
input i_Tx_DV,
input [7:0] i_Tx_Byte,
output o_Tx_Active,
output reg o_Tx_Serial,
output o_Tx_Done
);
parameter CLKS_PER_BIT = 87;
parameter s_IDLE = 3'b000;
parameter s_TX_START_BIT = 3'b001;
parameter s_TX_DATA_BITS... |
module calculate_val #(
parameter INPUT = 1
) (
input [4:0] value,
input [4:0] rotor,
output reg [4:0] out,
input [4:0] ring_position
);
reg signed [6:0] val = 7'b0000000;
always @*
begin
if (INPUT==1)
val = value - ring_position + rotor;
else
val = value + ring_position - rotor;
if (val < 0 ... |
module encode #(
parameter REVERSE = 0
) (
input [4:0] inputValue,
input [4:0] rotor,
output [4:0] outputValue,
input [2:0] rotor_type,
input [4:0] ring_position
);
wire [4:0] calculated_input;
wire [4:0] outval;
calculate_val #(.INPUT(1)) cinput(.value(inputValue),.rotor(rotor),.out(calculated_input),.ring_... |
module i2c_sender_verilog( input clk, inout siod, output sioc,
output taken, input send, input [7:0] id,
input [7:0] rega, input [7:0] value);
reg unsigned [7:0] divider = 8'b00000001;
reg [31:0] busy_sr = {32{1'b0}};
reg [... |
module debounce(input clk, input i, output o);
reg unsigned [23:0] c;
reg out_temp;
always @(posedge clk)begin
if(i == 1)begin
if(c==24'hFFFFFF)begin
out_temp <= 1'b1;
end
else begin
... |
module ov7670_registers_verilog(input clk, input resend, input advance, output [15:0] command, output finished);
reg [15:0] sreg;
reg finished_temp;
reg [7:0] address = {8{1'b0}};
assign command = sreg;
assign finished = finished_temp;
always@(sreg)
begin
if(sreg == 16'b1... |
module vga(input clk25,
output [3:0] vga_red,
output [3:0] vga_green,
output [3:0] vga_blue,
output vga_hsync,
output vga_vsync,
output [18:0] frame_addr,
input [11:0] frame_pixel);
parameter hRez = 640;
parameter hStartSync = 640+16;
para... |
module ov7670_controller_verilog(input clk, input resend, output config_finished, output sioc, inout siod, output reset, output pwdn, output xclk);
reg sys_clk = 0;
wire [15:0] command;
wire finished = 0;
wire taken = 0;
reg send;
reg [7:0] camera_address = 2'h42;
assign config_finishe... |
module ov7670_capture_verilog(input pclk,
input vsync,
input href,
input [7:0] d,
output [18:0] addr,
output [11:0] dout,
output we);
... |
module clocking_verilog(input clk_in, output clk_out);
wire clk_in;
reg clk_out;
always @ (posedge clk_in)
begin
clk_out <= !clk_out ;
end
endmodule |
module OV7670_top_verilog(input clk100, output OV7670_SIOC, inout OV7670_SIOD, output OV7670_RESET,
output OV7670_PWDN, input OV7670_VSYNC, input OV7670_HREF, input OV7670_PCLK,
output OV7670_XCLK, input [7:0] OV7670_D, output [7:0] LED, output [3:0] vga_red,
... |
module AXI4_Interconnect(clk, rst,
M1_ACLK, M1_ARESET, Master_1_Set, Master_1_Release,
M1_ARID, M1_ARADDR, M1_ARBURST, M1_ARVALID, M1_ARREADY, M1_ARLEN, M1_ARSIZE, // Read Address Channel
M1_RID, M1_RDATA, M1_RLAST, M1_RVALID, M1_RREADY, M1_RRE... |
module AXI4_BRAM_Controller(ACLK, ARESET,
ARID, ARADDR, ARBURST, ARVALID, ARREADY, ARLEN, ARSIZE, // Read Address Channel
RID, RDATA, RLAST, RVALID, RREADY, RRESP, // Read Data Channel
AWID, AWADDR, AWBURST, AWVALID, AWREADY, AWLEN, AWSIZE, // Write Address Channel
WID, WDATA, WLAST, W... |
module AXI4_Poly_Add(ACLK, ARESET, SET_ACCESS, RELEASE_ACCESS,
ARID, ARADDR, ARBURST, ARVALID, ARREADY, ARLEN, ARSIZE, // Read Address Channel
RID, RDATA, RLAST, RVALID, RREADY, RRESP, // Read Data Channel
AWID, AWADDR, AWBURST, AWVALID, AWREADY, AWLEN, AWSIZE, // Write Address Channel
... |
module AXI4_Write_BRAM(ACLK, ARESET, SET_ACCESS, RELEASE_ACCESS,
ARID, ARADDR, ARBURST, ARVALID, ARREADY, ARLEN, ARSIZE, // Read Address Channel
RID, RDATA, RLAST, RVALID, RREADY, RRESP, // Read Data Channel
AWID, AWADDR, AWBURST, AWVALID, AWREADY, AWLEN, AWSIZE, // Write Address Ch... |
module usbserial_tbx (
input pin_clk,
inout pin_usb_p,
inout pin_usb_n,
output pin_pu,
output pin_led,
output [3:0] debug
);
wire clk_48mhz;
wire clk_locked;
// Use an icepll generated pll
pll pll48( .clock_in(pin_clk), .clock_out(clk_48mhz), ... |
module MUXF7_L
(
input wire I0, I1,
input wire S,
output wire LO
);
assign LO = (S) ? I1 : I0;
endmodule |
module LUT6_D
#(
parameter [63:0] INIT = 64'h0000000000000000
)
(
input wire I0, I1, I2, I3, I4, I5,
output wire LO,
output wire O
);
wire [5:0] _w_idx = { I5, I4, I3, I2, I1, I0 };
assign LO = INIT[_w_idx];
assign O = INIT[_w_idx];
endmodule |
module SRLC16E
#(
parameter [15:0] INIT = 16'h0,
parameter [0:0] IS_CLK_INVERTED = 1'b0
)
(
// Clock
input wire CLK,
// Clock enable
input wire CE,
// Bit output position
input wire A0, A1, A2, A3,
// Data in
input wire D,
// Data out
output w... |
module FDCE
#(
parameter [0:0] IS_C_INVERTED = 1'b0,
parameter [0:0] IS_D_INVERTED = 1'b0,
parameter [0:0] IS_CLR_INVERTED = 1'b0,
parameter [0:0] INIT = 1'b0
)
(
// Clock
input wire C,
// Clock enable
input wire CE,
// Asynchronous clear
input wire CLR,
// ... |
module LUT2
#(
parameter [3:0] INIT = 4'b0000
)
(
input wire I0, I1,
output wire O
);
wire [1:0] _w_idx = { I1, I0 };
assign O = INIT[_w_idx];
endmodule |
module MUXF7
(
input wire I0, I1,
input wire S,
output wire O
);
assign O = (S) ? I1 : I0;
endmodule |
module RAM32X1S
#(
parameter [31:0] INIT = 32'h0,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)
(
// Write clock
input wire WCLK,
// Write enable
input wire WE,
// Read / Write address
input wire A0,
input wire A1,
input wire A2,
input wire ... |
module RAM64M
#(
parameter [63:0] INIT_A = 64'h0,
parameter [63:0] INIT_B = 64'h0,
parameter [63:0] INIT_C = 64'h0,
parameter [63:0] INIT_D = 64'h0,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)
(
// Write clock
input wire WCLK,
// Write e... |
module LUT1
#(
parameter [1:0] INIT = 2'b00
)
(
input wire I0,
output wire O
);
assign O = INIT[I0];
endmodule |
module RAM32X1D
#(
parameter [31:0] INIT = 32'h0,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)
(
// Write clock
input wire WCLK,
// Write enable
input wire WE,
// Read / Write address
input wire A0,
input wire A1,
input wire A2,
input wire ... |
module BUFG
(
input I,
output O /* verilator clocker */
);
assign O = I;
endmodule |
module RAM128X1D
#(
parameter [127:0] INIT = 128'h0,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)
(
// Write clock
input wire WCLK,
// Write enable
input wire WE,
// Read / Write address
input wire [6:0] A,
// Read address
input wire [6:0] DPRA,
// Data in
... |
module LUT4
#(
parameter [15:0] INIT = 16'h0000
)
(
input wire I0, I1, I2, I3,
output wire O
);
wire [3:0] _w_idx = { I3, I2, I1, I0 };
assign O = INIT[_w_idx];
endmodule |
module LUT6
#(
parameter [63:0] INIT = 64'h0000000000000000
)
(
input wire I0, I1, I2, I3, I4, I5,
output wire O
);
wire [5:0] _w_idx = { I5, I4, I3, I2, I1, I0 };
assign O = INIT[_w_idx];
endmodule |
module MUXF9
(
input wire I0, I1,
input wire S,
output wire O
);
assign O = (S) ? I1 : I0;
endmodule |
module RAM512X1S
#(
parameter [511:0] INIT = 512'h0,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)
(
// Write clock
input wire WCLK,
// Write enable
input wire WE,
// Read / Write address
input wire [8:0] A,
// Data in
input wire D,
// Data out
output ... |
module LUT6_2
#(
parameter [63:0] INIT = 64'h0000000000000000
)
(
input wire I0, I1, I2, I3, I4, I5,
output wire O5,
output wire O6
);
wire [5:0] _w_idx_5 = { 1'b0, I4, I3, I2, I1, I0 };
wire [5:0] _w_idx_6 = { I5, I4, I3, I2, I1, I0 };
assign O5 = INIT[_w_idx_5];
assign O6 = INI... |
module RAM64X1S
#(
parameter [63:0] INIT = 64'h0,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)
(
// Write clock
input wire WCLK,
// Write enable
input wire WE,
// Read / Write address
input wire A0,
input wire A1,
input wire A2,
input wire ... |
module RAM256X1S
#(
parameter [255:0] INIT = 256'h0,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)
(
// Write clock
input wire WCLK,
// Write enable
input wire WE,
// Read / Write address
input wire [7:0] A,
// Data in
input wire D,
// Data out
output ... |
module GND
(
output wire G
);
assign G = 1'b0;
endmodule |
module MUXF8_L
(
input wire I0, I1,
input wire S,
output wire LO
);
assign LO = (S) ? I1 : I0;
endmodule |
module RAM64X1D
#(
parameter [63:0] INIT = 64'h0,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)
(
// Write clock
input wire WCLK,
// Write enable
input wire WE,
// Read / Write address
input wire A0,
input wire A1,
input wire A2,
input wire ... |
module ODDRE1
#(
parameter [0:0] IS_C_INVERTED = 1'b0,
parameter [0:0] IS_D1_INVERTED = 1'b0,
parameter [0:0] IS_D2_INVERTED = 1'b0,
parameter SIM_DEVICE = "ULTRASCALE",
parameter [0:0] SRVAL = 1'b0
)
(
input C,
input D1,
input D2,
input SR,
output Q
);
... |
module LUT5_L
#(
parameter [31:0] INIT = 32'h00000000
)
(
input wire I0, I1, I2, I3, I4,
output wire LO
);
wire [4:0] _w_idx = { I4, I3, I2, I1, I0 };
assign LO = INIT[_w_idx];
endmodule |
module LDCE
#(
parameter INIT = 1'b0
)
(
// Asynchronous clear
input wire CLR,
// Latch
input wire G,
// Latch enable
input wire GE,
// Data in
input wire D,
// Data out
output wire Q
);
reg _r_Q;
initial begin : INIT_STATE
_r_Q = INIT[0];
end
... |
module RAM32M16
#(
parameter [63:0] INIT_A = 64'h0,
parameter [63:0] INIT_B = 64'h0,
parameter [63:0] INIT_C = 64'h0,
parameter [63:0] INIT_D = 64'h0,
parameter [63:0] INIT_E = 64'h0,
parameter [63:0] INIT_F = 64'h0,
parameter... |
module RAM32M
#(
parameter [63:0] INIT_A = 64'h0,
parameter [63:0] INIT_B = 64'h0,
parameter [63:0] INIT_C = 64'h0,
parameter [63:0] INIT_D = 64'h0,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)
(
// Write clock
input wire WCLK,
// Write e... |
module RAM256X1D
#(
parameter [255:0] INIT = 256'h0,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)
(
// Write clock
input wire WCLK,
// Write enable
input wire WE,
// Read / Write address
input wire [7:0] A,
// Read address
input wire [7:0] DPRA,
// Data in
... |
module LDPE
#(
parameter INIT = 1'b0
)
(
// Asynchronous preset
input wire PRE,
// Latch
input wire G,
// Latch enable
input wire GE,
// Data in
input wire D,
// Data out
output wire Q
);
reg _r_Q;
initial begin : INIT_STATE
_r_Q = INIT[0];
end
... |
module BUFGCE_DIV
#(
parameter integer BUFGCE_DIVIDE = 1,
parameter CE_TYPE = "SYNC",
parameter HARDSYNC_CLR = "FALSE",
parameter [0:0] IS_CE_INVERTED = 1'b0,
parameter [0:0] IS_CLR_INVERTED = 1'b0,
parameter [0:0] IS_I_INVERTED = 1'b0
)
(
input I,
... |
module MUXF7_D
(
input wire I0, I1,
input wire S,
output wire LO,
output wire O
);
assign LO = (S) ? I1 : I0;
assign O = (S) ? I1 : I0;
endmodule |
module IBUFDS_GTE3
#(
parameter [0:0] REFCLK_EN_TX_PATH = 1'b0,
parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00,
parameter [1:0] REFCLK_ICNTL_RX = 2'b00
)
(
// Clock input
input I,
input IB,
// Clock enable
input CEB,
// Clock outputs
output O /* verilator clock... |
module RAM128X1S
#(
parameter [127:0] INIT = 128'h0,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)
(
// Write clock
input wire WCLK,
// Write enable
input wire WE,
// Read / Write address
input wire A0,
input wire A1,
input wire A2,
input wir... |
module SRLC32E
#(
parameter [31:0] INIT = 32'h0,
parameter [0:0] IS_CLK_INVERTED = 1'b0
)
(
// Clock
input wire CLK,
// Clock enable
input wire CE,
// Bit output position
input wire [4:0] A,
// Data in
input wire D,
// Data out
output wire Q,
... |
module VCC
(
output wire P
);
assign P = 1'b1;
endmodule |
module RAM64M8
#(
parameter [63:0] INIT_A = 64'h0,
parameter [63:0] INIT_B = 64'h0,
parameter [63:0] INIT_C = 64'h0,
parameter [63:0] INIT_D = 64'h0,
parameter [63:0] INIT_E = 64'h0,
parameter [63:0] INIT_F = 64'h0,
parameter ... |
module SRL32E
#(
parameter [31:0] INIT = 32'h0,
parameter [0:0] IS_CLK_INVERTED = 1'b0
)
(
// Clock
input wire CLK,
// Clock enable
input wire CE,
// Bit output position
input wire [4:0] A,
// Data in
input wire D,
// Data out
output wire Q
);... |
module CFGLUT5
#(
parameter [31:0] INIT = 32'h00000000,
parameter [0:0] IS_CLK_INVERTED = 1'b0
)
(
// Clock
input wire CLK,
// Clock enable
input wire CE,
// LUT inputs
input wire I0, I1, I2, I3, I4,
// LUT configuration data input
input wire CDI,
// LUT confi... |
module MUXF8
(
input wire I0, I1,
input wire S,
output wire O
);
assign O = (S) ? I1 : I0;
endmodule |
module FDSE
#(
parameter [0:0] IS_C_INVERTED = 1'b0,
parameter [0:0] IS_D_INVERTED = 1'b0,
parameter [0:0] IS_S_INVERTED = 1'b0,
parameter [0:0] INIT = 1'b1
)
(
// Clock
input wire C,
// Clock enable
input wire CE,
// Synchronous set
input wire S,
// Data in
i... |
module MUXF8_D
(
input wire I0, I1,
input wire S,
output wire LO,
output wire O
);
assign LO = (S) ? I1 : I0;
assign O = (S) ? I1 : I0;
endmodule |
module LUT3
#(
parameter [7:0] INIT = 8'b00000000
)
(
input wire I0, I1, I2,
output wire O
);
wire [2:0] _w_idx = { I2, I1, I0 };
assign O = INIT[_w_idx];
endmodule |
module LUT6_L
#(
parameter [63:0] INIT = 64'h0000000000000000
)
(
input wire I0, I1, I2, I3, I4, I5,
output wire LO
);
wire [5:0] _w_idx = { I5, I4, I3, I2, I1, I0 };
assign LO = INIT[_w_idx];
endmodule |
module LUT5
#(
parameter [31:0] INIT = 32'h00000000
)
(
input wire I0, I1, I2, I3, I4,
output wire O
);
wire [4:0] _w_idx = { I4, I3, I2, I1, I0 };
assign O = INIT[_w_idx];
endmodule |
module BUFG_GT
(
input I,
input [2:0] DIV,
input CE,
input CEMASK,
input CLR,
input CLRMASK,
output O /* verilator clocker */
);
reg [1:0] r_CE_cdc;
wire w_CE_msk;
reg r_CE_msk;
reg [1:0] r_CLR_cdc;
wire w... |
module IBUFDS
#(
parameter CAPACITANCE = "DONT_CARE",
parameter DIFF_TERM = "FALSE",
parameter DQS_BIAS = "FALSE",
parameter IBUF_DELAY_VALUE = "0",
parameter IBUF_LOW_PWR = "TRUE",
parameter IFD_DELAY_VALUE = "AUTO",
parameter IOSTANDARD = "DEFAULT"
)
(
//... |
module CARRY8
#(
parameter CARRY_TYPE = "SINGLE_CY8" // "SINGLE_CY8", "DUAL_CY4"
)
(
// Carry cascade input
input wire CI,
// Second carry input (in DUAL_CY4 mode)
input wire CI_TOP,
// Carry MUX data input
input wire [7:0] DI,
// Carry MUX select line
input wire [7:0... |
module FDRE
#(
parameter [0:0] IS_C_INVERTED = 1'b0,
parameter [0:0] IS_D_INVERTED = 1'b0,
parameter [0:0] IS_R_INVERTED = 1'b0,
parameter [0:0] INIT = 1'b0
)
(
// Clock
input wire C,
// Clock enable
input wire CE,
// Synchronous reset
input wire R,
// Data in
... |
module FDPE
#(
parameter [0:0] IS_C_INVERTED = 1'b0,
parameter [0:0] IS_D_INVERTED = 1'b0,
parameter [0:0] IS_PRE_INVERTED = 1'b0,
parameter [0:0] INIT = 1'b0
)
(
// Clock
input wire C,
// Clock enable
input wire CE,
// Asynchronous preset
input wire PRE,
//... |
module SRL16E
#(
parameter [15:0] INIT = 16'h0,
parameter [0:0] IS_CLK_INVERTED = 1'b0
)
(
// Clock
input wire CLK,
// Clock enable
input wire CE,
// Bit output position
input wire A0, A1, A2, A3,
// Data in
input wire D,
// Data out
output wire Q
);
wire [... |
module LUT5_D
#(
parameter [31:0] INIT = 32'h00000000
)
(
input wire I0, I1, I2, I3, I4,
output wire LO,
output wire O
);
wire [4:0] _w_idx = { I4, I3, I2, I1, I0 };
assign LO = INIT[_w_idx];
assign O = INIT[_w_idx];
endmodule |
module CARRY4
(
// Carry cascade input
input wire CI,
//
input wire CYINIT,
// Carry MUX data input
input wire [3:0] DI,
// Carry MUX select line
input wire [3:0] S,
// Carry out of each stage of the chain
output wire [3:0] CO,
// Carry chain XOR general data... |
module mult_pipe2 #(
parameter SIZE = 16,
parameter LVL = 2
)
( a, b, clk, pdt) ;
/*
* parameter 'SIZE' is the width of multiplier/multiplicand;.Application Notes 10-5
* parameter '' is the intended number of stages of the
* pipelined multiplier;
* which is typically the smallest integer greater than or equal
* to ba... |
module psum_spad(clk, addr, we, data_port);
// 24 * 16bit
input clk;
input [4:0] addr;
input we; // write enable signal, 0: Read; 1: Write
inout [15:0] data_port;
reg [15:0] data_out;
reg [15:0] mem [23:0]; // 24 * 16bit
assign data_port = !we ? data_out : 16'bz;
always @ (posedge clk)
begin
if (we)
m... |
module dual_clock_fifo #(
parameter ADDR_WIDTH = 3,
parameter DATA_WIDTH = 16
)
(
input wire wr_rst_i,
input wire wr_clk_i,
input wire wr_en_i,
input wire [DATA_WIDTH-1:0] wr_data_i,
input wire rd_rst_i,
input wire rd_clk_i,
input wire rd_en_i,
output reg [DATA_WIDTH-1:0] rd_data_o,
outpu... |
module clacc_mem (ipf_valid, ipf_data, ipf_addr, clk);
input ipf_valid;
input [13:0] ipf_addr;
input [7:0] ipf_data;
input clk;
reg [7:0] ipf_M [0:16383];
integer i;
initial begin
for (i=0; i<=16383; i=i+1) ipf_M[i] = 0;
end
always@(negedge clk)
if (ipf_valid) ipf_M[ ipf_addr ] <= ipf_data;
endmodul... |
module counter_5to3(x, y);
input [4:0] x;
output [2:0] y;
assign y[2:0] = (x[4:0] == 5'b00000) ? 3'b000 :
( x[4:0] == 5'b00001) ? 3'b001 :
( x[4:0] == 5'b00010) ? 3'b001 :
( x[4:0] == 5'b00100) ? 3'b001 :
( x[4:0] == 5'b01000) ? 3'b001 :
( x[4:0] == 5'b10000) ? 3'b001 :
( x[4:0] == 5'b00011) ... |
module bs_mult_slice(clk, xy, pin, cin, rin, x, y, pout, cout, rout, lastbit);
input clk;
input xy, pin, cin, rin, x, y, lastbit;
output pout, cout, rout;
wire [2:0] cout_int;
reg cout;
reg rout;
wire a, b;
reg pin_delay;
reg x_delay;
reg y_delay;
reg cout1_delay;
assign a = x_delay & y;
assign b = x & y_d... |
module filter_spad(clk, addr, we, data_port);
// 224 * 16bit
input clk;
input [7:0] addr;
input we; // write enable signal, 0: Read; 1: Write
inout [15:0] data_port;
reg [15:0] data_out;
reg [15:0] mem [223:0]; // 12 * 16bit
assign data_port = !we ? data_out : 16'bz;
always @ (posedge clk)
begin
if (we)
... |
module ifmap_spad(clk, addr, we, data_port);
// 12 * 16bit
input clk;
input [3:0] addr;
input we; // write enable signal, 0: Read; 1: Write
inout [15:0] data_port;
reg [15:0] data_out;
reg [15:0] mem [11:0]; // 12 * 16bit
assign data_port = !we ? data_out : 16'bz;
always @ (posedge clk)
begin
if (we)
... |
module bs_adder(x, y, clk, z, rst);
input x, y, clk, rst;
output reg z;
reg cin_int;
wire sum_int;
fa I0(.x(x), .y(y), .cin(cin_int), .cout(cout_int), .sum(sum_int));
always @ (posedge clk)
begin
if(rst)
begin
cin_int <= 1'b0;
z <= 1'b0;
end
else
begin
cin_int <= cout_int;
z <= sum_int;... |
module bs_mult(clk, x, y, p, firstbit, lastbit);
input clk;
input x, y, firstbit, lastbit;
output p;
assign xy = x & y;
wire [29:0] pout;
wire [30:0] rout;
wire [30:0] cout;
bs_mult_slice I0(.clk(clk), .xy(xy), .pin(pout[0]), .cin(1'b0),
.rin(firstbit), .x(x), .y(y), .pout(p), .cout(cout[0]),
.rout(rout... |
module ha(x, y, cout, sum);
input x, y;
output cout, sum;
assign sum = x ^ y;
assign cout = x & y;
endmodule |
module fa(x, y, cin, cout, sum);
input x, y, cin;
output cout, sum;
wire cout_int, cout_int2;
wire sum_int;
ha I0(.x(x), .y(y), .cout(cout_int), .sum(sum_int));
ha I1(.x(sum_int), .y(cin), .cout(cout_int2), .sum(sum));
assign cout = cout_int | cout_int2;
endmodule |
module multiplier(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
out... |
module adder(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output ... |
module exponential (
input wire Clock,
input wire Reset,
input wire Str,
input wire [`DATALENGTH-1:0] Datain,
output reg Ack,
output reg [`DATALENGTH-1:0] DataOut
);
wire [`DATALENGTH-1:0] one, oversix, h... |
module adder_tb();
reg clk;
reg rst;
reg [31:0] input_a;
reg [31:0] input_b;
reg input_a_stb;
reg input_b_stb;
reg output_z_ack;
wire input_a_ack;
wire input_b_ack;
wire output_z_stb;
wire [31:0] output_z;
initial be... |
module exponential_tb ();
reg Clock;
reg Reset;
reg Str;
reg [`DATALENGTH-1:0] Datain;
wire [`DATALENGTH-1:0] DataOut;
wire Ack;
exponential DUT (Clock, Reset,Str, Datain ,Ack, DataOut);
initial begin
Clock = 0;
Reset = 1;
Str = 0;
#10
Reset = 0;
Str = 1;
Datain = 32'h3f800000;
... |
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