code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module mux #(
parameter WIDTH = 32
) (
input addr,
input [WIDTH-1:0] In0,
input [WIDTH-1:0] In1,
output reg [WIDTH-1:0] Out_dat
);
always @* begin
if (addr) Out_dat = In1;
else Out_dat = In0;
end
endmodule
| 8.575874 |
module control(rd, wr, ld_ir, ld_acc, ld_pc, inc_pc, halt, data_e, sel,
opcode, zero, clk, rst);
output rd, wr, ld_ir, ld_acc, ld_pc, inc_pc, halt, data_e, sel;
input [2:0] opcode;
input zero, clk, rst;
reg rd, wr, ld_ir, ld_acc, ld_pc, inc_pc, halt, data_e, sel;
reg ... | 6.500738 |
module Seg7 (
input [3:0] num,
output [7:0] seg
);
reg [7:0] tseg;
always @(num) begin
case (num)
4'b0000: tseg = 8'b11111100; // 0
4'b0001: tseg = 8'b01100000; // 1
4'b0010: tseg = 8'b01011010; // 2
4'b0011: tseg = 8'b11110010; // 3
4'b0100: tseg = 8'b01100110; // 4
... | 6.771186 |
module simple_function ();
function myfunction;
input a, b, c, d;
begin
myfunction = ((a + b) + (c - d));
end
endfunction
endmodule
| 6.540619 |
module function_calling (
a,
b,
c,
d,
e,
f
);
input a, b, c, d, e;
output f;
wire f;
`include "myfunction.v"
assign f = (myfunction(a, b, c, d)) ? e : 0;
endmodule
| 7.144021 |
module items> có thể bao gồm：
1. initial
2. always
3. assign
4. module
/*****************************************/
/*****************************************/
//Example01：
module A(out1, out2, in1, in2);
output out1;
output [3:0] out2;
input in1;
input [2:0] in2;
endmodule
| 6.689213 |
module my_module (
Clk,
D,
Q
);
parameter width = 2, delay = 10;
input [width - 1 : 0] D;
input Clk;
output [width : 0] Q;
assign #delay Q = D;
endmodule
| 7.052055 |
module nandgate (
output s,
input p,
input q
);
assign s = ~(p & q);
endmodule
| 7.298658 |
module top_module (
output one
);
// Insert your code here
assign one = 1'b1;
endmodule
| 7.203305 |
module fraserbc_simon (
io_in,
io_out
);
input wire [7:0] io_in;
output wire [7:0] io_out;
assign io_out[7:4] = 4'b0;
/* Instantiate main module */
simon simon0 (
.i_clk (io_in[0]),
.i_shift(io_in[1]),
.i_data (io_in[5:2]),
.o_data (io_out[3:0])
);
endmodule
| 7.617861 |
module lfsr_z0 (
i_clk,
i_rst,
o_data
);
input wire i_clk;
input wire i_rst;
output wire o_data;
reg [4:0] r_lfsr;
assign o_data = r_lfsr[0];
always @(posedge i_clk)
if (i_rst) r_lfsr <= 5'b00001;
else begin
r_lfsr[4] <= r_lfsr[3];
r_lfsr[3] <= r_lfsr[2];
r_lfsr[2] <... | 7.510878 |
module simon (
i_clk,
i_shift,
i_data,
o_data
);
input wire i_clk;
input wire i_shift;
input wire [3:0] i_data;
output wire [3:0] o_data;
assign o_data = r_round[3:0];
/* z0 Sequence */
wire w_z0;
lfsr_z0 lfsr0 (
.i_clk (i_clk),
.i_rst (i_shift),
.o_data(w_z0)
);
... | 7.119927 |
module top_module (
output one
);
// Insert your code here
wire x;
assign one = 1'b1;
endmodule
| 7.203305 |
module testnorgate;
// ------------------------- dados locais
reg a, b; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
norgate NOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
// atribuicao simultane... | 6.695863 |
module top_module (
output zero
); // Module body starts after semicolon
assign zero = 1'b0;
endmodule
| 7.203305 |
module tomkeddie_top_tto #(
parameter CLOCK_RATE = 1000
) (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire reset = io_in[1];
wire hour_inc = io_in[6];
wire min_inc = io_in[7];
wire lcd_en;
wire lcd_rs;
wire [3:0] lcd_data;
assign io... | 6.88019 |
module top_module (
output zero
); // Module body starts after semicolon
assign zero = 1'b0;
endmodule
| 7.203305 |
module xnorgate (
output s,
input p,
input q
);
assign s = (~p ^ q);
endmodule
| 6.74222 |
module testxnorgate;
// ------------------------- dados locais
reg a, b; // definir registrador
wire s; // definir conexao (fio)
// ------------------------- instancia
xnorgate XNOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 0; // valores bi... | 7.028584 |
module top_module (
input in,
output out
);
assign out = in;
endmodule
| 7.203305 |
module top_module (
input in,
output out
);
assign out = in;
endmodule
| 7.203305 |
module nandgate (
output s,
input p,
input q
);
assign s = ((~p) | (~q));
endmodule
| 7.298658 |
module top_module (
input a,
b,
c,
output w,
x,
y,
z
);
// input, output은 따로 지정하지 않는 한 자동으로 wire 선언됨
assign w = a;
assign x = b;
assign y = b;
assign z = c;
endmodule
| 7.203305 |
module top_module (
input a,
b,
c,
output w,
x,
y,
z
);
assign w = a;
assign x = b;
assign y = b;
assign z = c;
endmodule
| 7.203305 |
module testnorgate;
// ------------------------- dados locais
reg a, b; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
norgate NOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
// atribuicao simultane... | 6.695863 |
module top_module (
input in,
output out
);
assign out = ~in;
endmodule
| 7.203305 |
module top_module (
input in,
output out
);
assign out = ~in;
endmodule
| 7.203305 |
module migcorre_pwm (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0]; // clock input 12.5KHz
wire reset = io_in[1]; // reset active high
wire increase_duty_in = io_in[2]; // increase duty cycle by 10%
wire decrease_duty_in = io_in[3]; // decrease duty cycle by 10%
wire disable_de... | 6.944077 |
module xorgate (
output s,
input p,
input q
);
assign s = ((~p) & q) | (p & (~q));
endmodule
| 7.421731 |
module testxorgate;
// ------------------------- dados locais
reg a, b; // definir registrador
wire s; // definir conexao (fio)
// ------------------------- instancia
xorgate XOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 0; // valores binar... | 6.716539 |
module top_module (
input a,
input b,
output out
);
assign out = a & b;
endmodule
| 7.203305 |
module top_module (
input a,
input b,
output out
);
assign out = a & b;
endmodule
| 7.203305 |
module xnorgate (
output s,
input p,
input q
);
assign s = ((p & q) | ((~p) & (~q)));
endmodule
| 6.74222 |
module testxnorgate;
// ------------------------- dados locais
reg a, b; // definir registrador
wire s; // definir conexao (fio)
// ------------------------- instancia
xnorgate XNOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 0; // valores bi... | 7.028584 |
module alu_top (
input [7:0] io_in,
output [7:0] io_out
);
alu alu (
.A(io_in[7:6]),
.B(io_in[5:4]),
.ALU_Sel(io_in[3:0]),
.ALU_Out(io_out[6:0]),
.CarryOut(io_out[7])
);
endmodule
| 7.395278 |
module top_module (
input a,
input b,
output out
);
assign out = ~(a | b);
endmodule
| 7.203305 |
module top_module (
input a,
input b,
output out
);
assign out = ~(a | b);
endmodule
| 7.203305 |
module testandgate;
// ------------------------- dados locais
reg a, b, c; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
andgate AND1 (
s,
a,
b,
c
);
// ------------------------- preparacao
initial begin : start
// atribuic... | 6.553783 |
module for the McCoy microprocessor
*/
`default_nettype none
module aidan_McCoy(
input [7:0] io_in,
output [7:0] io_out);
// map i/o to proper labels
wire clk = io_in[0];
wire reset = io_in[1];
wire [5:0] instr = io_in[7:2];
// decode signals
wire bez;
wire ja;
//wire alu... | 7.59402 |
module top_module (
input a,
input b,
output out
);
assign out = ~(a ^ b);
endmodule
| 7.203305 |
module top_module (
input a,
input b,
output out
);
assign out = a ~^ b;
endmodule
| 7.203305 |
module and2gate (
output t,
input a,
input b,
input c
);
wirel x;
andgate AND1 (
x,
a,
b
);
andgate AND2 (
t,
x,
d
);
endmodule
| 8.613407 |
module testandgate;
// ------------------------- dados locais
reg a, b, c; // definir registradores
wire u, s, t; // definir conexao (fio)
// ------------------------- instancia
and2gate AND3 (
u,
a,
b,
c
);
// ------------------------- preparacao
initial begin : start
// ... | 6.553783 |
module azdle_binary_clock (
input [7:0] io_in,
output [7:0] io_out
);
wire rst;
wire clk;
wire pps; // Pulse per second input
wire [4:0] hours_init; // value for hours to load when coming out of reset
wire [7:0] opins;
assign clk = io_in[0];
assign rst = io_in[1];
assign pps = io_in[2];
as... | 7.186957 |
module rotor #(
parameter bits = 3,
parameter pattern = 6
) (
input rst,
input clk,
output reg [bits-1:0] val
);
always @(posedge clk)
if (rst) val <= pattern;
else val <= {val[bits-2:0], val[bits-1]};
endmodule
| 7.098426 |
module top_module (
input a,
input b,
input c,
input d,
output out,
output out_n
);
wire and_1, and_2;
assign and_1 = a & b;
assign and_2 = c & d;
assign out = and_1 | and_2;
assign out_n = !out;
endmodule
| 7.203305 |
module top_module (
input wire a,
input wire b,
input wire c,
input wire d,
output wire out,
output wire out_n
);
wire and_ab_1;
wire and_cd_1;
wire or_2;
assign and_ab_1 = a & b;
assign and_cd_1 = c & d;
assign or_2 = and_ab_1 | and_cd_1;
assign out = or_2;
assign out_n = ... | 7.203305 |
module Circuit_1 (
A,
B,
C,
F1,
F2
);
output F1, F2;
input A, B, C;
and G1 (T2, A, B, C);
or G2 (T1, A, B, C);
and G3 (T4, A, B);
and G4 (T5, A, C);
and G5 (T6, B, C);
or G6 (F2, T4, T5, T6);
not G7 (T7, F2);
and G8 (T3, T1, T7);
or G9 (F1, T2, T3);
endmodule
| 7.03116 |
module top_module (
output one
);
// Insert your code here
assign one = 1; //assign allows to drive an output continuously with a value
endmodule
| 7.203305 |
module top_module (
output one
);
// Insert your code here
assign one = 1'b1;
endmodule
| 7.203305 |
module top_module (
output zero
);
assign zero = 0;
endmodule
| 7.203305 |
module or3gate (
output s,
input p,
input q,
input r
);
wire x;
orgate OR0 (
x,
p,
q
);
orgate OR1 (
s,
r,
x
);
endmodule
| 7.416224 |
module testor3gate;
// ------------------------- dados locais
reg a, b, c; // definir registrador
wire s; // definir conexao (fio)
// ------------------------- instancia
or3gate OR1 (
s,
a,
b,
c
);
// ------------------------- preparacao
initial begin : start
a = 0; // va... | 7.48966 |
module nand2 (
output s,
input a,
input b
);
assign s = (~(a & b));
endmodule
| 8.000232 |
module nor2 (
output s,
input a,
input b
);
assign s = (~(a | b));
endmodule
| 7.808103 |
module xnor2 (
output s,
input a,
input b
);
assign s = (~(a ^ b));
endmodule
| 7.055481 |
module nand2 (
output s,
input a,
input b
);
assign s = ((~a) | (~b));
endmodule
| 8.000232 |
module nor2 (
output s,
input a,
input b
);
assign s = ((~a) & (~b));
endmodule
| 7.808103 |
module xor2 (
output s,
input a,
input b
);
assign s = ((~a) & b) | (a & (~b));
endmodule
| 9.200725 |
module xnor2 (
output s,
input a,
input b
);
assign s = (a & b) | ((~a) & (~b));
endmodule
| 7.055481 |
module and3 (
output s,
input a,
input b,
input c
);
assign s = a & b & c;
endmodule
| 7.858068 |
module and3 (
output s,
input a,
input b,
input c
);
and and1 (w1, a, b);
and and2 (s, w1, c);
endmodule
| 7.858068 |
module detector (
input in,
input clk,
output out
);
reg out;
reg [1:0] state;
reg [1:0] nextstate;
//initializing state
initial begin
state <= 0;
end
//always block for state alloc
always @(posedge clk) begin
state <= nextstate;
end
//always block for next state
always @(... | 6.593279 |
module top_module (
input p1a,
p1b,
p1c,
p1d,
p1e,
p1f,
output p1y,
input p2a,
p2b,
p2c,
p2d,
output p2y
);
wire p1_and1, p1_and2, p2_and1, p2_and2;
assign p1_and1 = p1a & p1b & p1c;
assign p1_and2 = p1d & p1e & p1f;
assign p2_and1 = p2a & p2b;
assign p2_and... | 7.203305 |
module top_module (
input p1a,
p1b,
p1c,
p1d,
p1e,
p1f,
output p1y,
input p2a,
p2b,
p2c,
p2d,
output p2y
);
assign p1y = (p1a & p1b & p1c) | (p1d & p1e & p1f);
assign p2y = (p2a & p2b) | (p2c & p2d);
endmodule
| 7.203305 |
module detector_tb;
/* input to the detector */
reg CLK;
reg in;
/* output from the detector */
wire out;
/* internal counter for test */
integer i;
integer Passed;
// Connect the detector to detector_tb
// Please follow name specified here.
detector UUT (
.clk(CLK),
.in (in),
... | 7.485789 |
module or3 (
output s,
input a,
input b,
input c
);
or or1 (w1, a, b);
or or2 (s, w1, c);
endmodule
| 8.195932 |
module jar_sram_top #(
parameter AW = 4, // address width
parameter DW = 8, // data width
parameter DEPTH = 16 // number of bytes
) (
input [DW-1:0] io_in,
output [DW-1:0] io_out
);
// Shared address and data input.
// When writing, low data bits first, then high bits, then address
wire ... | 7.064554 |
module top_module (
input wire [2:0] vec,
output wire [2:0] outv,
output wire o2,
output wire o1,
output wire o0
); // Module body starts after module declaration
assign outv = vec;
assign o0 = vec[0];
assign o1 = vec[1];
assign o2 = vec[2];
endmodule
| 7.203305 |
module top_module (
input wire [2:0] vec,
output wire [2:0] outv,
output wire o2,
output wire o1,
output wire o0
); // Module body starts after module declaration
assign outv = vec;
assign o2 = vec[2];
assign o1 = vec[1];
assign o0 = vec[0];
endmodule
| 7.203305 |
module top_module (
input wire [15:0] in,
output wire [ 7:0] out_hi,
output wire [ 7:0] out_lo
);
assign out_hi = in[15:8];
assign out_lo = in[7:0];
endmodule
| 7.203305 |
module top_module (
input wire [15:0] in,
output wire [ 7:0] out_hi,
output wire [ 7:0] out_lo
);
assign out_hi = in[15:8];
assign out_lo = in[7:0];
endmodule
| 7.203305 |
module top_module (
input [31:0] in,
output [31:0] out
); //
// assign out[31:24] = ...;
assign out = {in[7:0], in[15:8], in[23:16], in[31:24]};
endmodule
| 7.203305 |
module top_module (
input [31:0] in,
output [31:0] out
); //
// assign out[31:24] = ...;
assign out[31:24] = in[7:0];
assign out[23:16] = in[15:8];
assign out[15:8] = in[23:16];
assign out[7:0] = in[31:24];
endmodule
| 7.203305 |
module top_module (
input [2:0] a,
input [2:0] b,
output [2:0] out_or_bitwise,
output out_or_logical,
output [5:0] out_not
);
assign out_or_bitwise = a | b;
assign out_or_logical = a || b;
assign out_not = {~b, ~a};
endmodule
| 7.203305 |
module top_module (
input [2:0] a,
input [2:0] b,
output [2:0] out_or_bitwise,
output out_or_logical,
output [5:0] out_not
);
assign out_or_bitwise = a | b;
assign out_or_logical = a || b;
assign out_not[5:3] = ~b;
assign out_not[2:0] = ~a;
endmodule
| 7.203305 |
module top_module (
input [3:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and = ∈
assign out_or = |in;
assign out_xor = ^in;
endmodule
| 7.203305 |
module top_module (
input [3:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and = ∈
assign out_or = |in;
assign out_xor = ^in;
endmodule
| 7.203305 |
module tiny_fft (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire reset = io_in[1];
wire wrEn = io_in[2];
wire [3:0] data_in = io_in[7:4];
reg [1:0] wrIdx;
reg [2:0] rdIdx;
reg signed [3:0] input_reg[0:3];
assign io_out[0] = (rdIdx == 0) ? 1'b1 : 1'b0;
// Signal high ... | 7.212682 |
module top_module (
input [4:0] a,
b,
c,
d,
e,
f,
output [7:0] w,
x,
y,
z
); //
// assign { ... } = { ... };
assign {w, x, y, z} = {a, b, c, d, e, f, 2'b11};
endmodule
| 7.203305 |
module top_module (
input [4:0] a,
b,
c,
d,
e,
f,
output [7:0] w,
x,
y,
z
); //
// assign { ... } = { ... };
assign {w, x, y, z} = {a, b, c, d, e, f, 2'b11};
endmodule
| 7.203305 |
module top_module (
input [7:0] in,
output [7:0] out
);
assign out = {in[0], in[1], in[2], in[3], in[4], in[5], in[6], in[7]};
endmodule
| 7.203305 |
module top_module (
input [7:0] in,
output [7:0] out
);
assign out = {in[0], in[1], in[2], in[3], in[4], in[5], in[6], in[7]};
endmodule
| 7.203305 |
module top_module (
input [ 7:0] in,
output [31:0] out
); //
// assign out = { replicate-sign-bit , the-input };
assign out = {{24{in[7]}}, in};
endmodule
| 7.203305 |
module top_module (
input [ 7:0] in,
output [31:0] out
); //
// assign out = { replicate-sign-bit , the-input };
assign out = {{24{in[7]}}, in};
endmodule
| 7.203305 |
module top_module (
input a,
b,
c,
d,
e,
output [24:0] out
); //
// The output is XNOR of two vectors created by
// concatenating and replicating the five inputs.
// assign out = ~{ ... } ^ { ... };
assign out = ~{{5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}}} ^ {5{a, b, c, d, e}};
endmodu... | 7.203305 |
module top_module (
input a,
b,
c,
d,
e,
output [24:0] out
); //
// The output is XNOR of two vectors created by
// concatenating and replicating the five inputs.
// assign out = ~{ ... } ^ { ... };
wire [24:0] A;
wire [24:0] B;
assign A = {{5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}... | 7.203305 |
module top_module (
input clk,
input reset,
output [9:0] q
);
reg [9:0] o_q;
assign q = o_q;
always @(posedge clk) begin
if (reset) begin
o_q <= 10'b0;
end else begin
if (o_q == 999) begin
o_q <= 10'b0;
end else begin
o_q <= o_q + 1;
end
end
end
... | 7.203305 |
module my_fsm1always (
clk,
reset,
inA,
inB,
OutA,
OutB
);
input clk, reset, inA, inB;
output OutA, OutB;
reg OutA = 0, OutB = 0;
reg [1:0] estado_actual = 0; // No empleo estado anterior
parameter E0 = 0, E1 = 1, E2 = 2, E3 = 3; // 4 estados posibles
//************************... | 6.912463 |
module, the output port `b` is not driven; it isn't connected to any other wire.
// In general, all output ports of all modules should always be driven.
//
// In Verilog, one can connect two wires with the keyword `assign`.
// The following module implements a buffer (i.e. a circuit that copies its input to its outpu... | 7.714843 |
module my_moore1 (
clk,
reset,
inA,
inB,
OutA,
OutB
);
input clk, reset, inA, inB;
output OutA, OutB;
reg OutA = 0, OutB = 0;
reg [1:0] estado_actual = 0, estado_siguiente = 0;
parameter E0 = 0, E1 = 1, E2 = 2, E3 = 3; // 4 estados posibles
//********************************* Pa... | 7.179981 |
module top_module (
input clk,
input areset, // Asynchronous reset to state B
input in,
output out
); //
parameter A = 0, B = 1;
reg state, next_state;
always @(*) begin // This is a combinational always block
// State transition logic
case (state)
A: next_state = in ? A : ... | 7.203305 |
module sync_fifo_ver1 (
clk,
rst_n,
buf_in,
buf_out,
wr_en,
rd_en,
buf_empty,
buf_full,
fifo_cnt
);
input clk, rst_n;
input wr_en, rd_en;
input [7:0] buf_in;
output reg [7:0] buf_out;
output wire buf_empty, buf_full;
output reg [`buf_width-1:0] fifo_cnt;
reg [`buf_size... | 6.509696 |
module sync_fifo_ver1_tb ();
reg clk, rst_n;
reg wr_en, rd_en;
reg [7:0] buf_in; // data input to be pushed to buffer
wire [7:0] buf_out; // port to output the data using pop.
wire buf_empty, buf_full; // buffer empty and full indication
wire [`BUF_WIDTH-1:0] fifo_cnt; // number of data pushed in to b... | 6.509696 |
module Circuit_2 (
Out_1,
Out_2,
Out_3,
A,
B,
C,
D
);
output Out_1, Out_2, Out_3;
input A, B, C, D;
assign Out_1 = (A || (!B)) && (!C) && (C || D);
assign Out_2 = ((!C) && D || (B && C && D) || (C && (!D))) && ((!A) || B);
assign Out_3 = (A && B || C) && D || (!B) && C;
endmodule
... | 6.567869 |
module top_module (
output zero
); // Module body starts after semicolon
assign zero = 0;
endmodule
| 7.203305 |
module top_module (
output zero
); // Module body starts after semicolon
assign zero = 1'b0;
endmodule
| 7.203305 |
module top_module (
input a,
input b,
output out
);
assign out = a & b;
endmodule
| 7.203305 |
module top_module (
input a,
input b,
output out
);
mod_a u_mod_a (
.in1(a),
.in2(b),
.out(out)
);
endmodule
| 7.203305 |
module top_module (
input a,
input b,
output out
);
mod_a instance1 (
.in1(a),
.in2(b),
.out(out)
);
endmodule
| 7.203305 |
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