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module Demux_2 ( input io_en, input io_input_valid, input [15:0] io_input_data, input io_sel, output io_outputs_0_valid, output [15:0] io_outputs_0_data, output io_outputs_1_valid, output [15:0] io_outputs_1_data ); wire [15:0] _GEN_1; wire _GEN...
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module LockingRRArbiter_4 ( input clock, input reset, output io_in_0_ready, input io_in_0_valid, input io_in_0_bits_valid, input [15:0] io_in_0_bits_RouteID, input [15:0] io_in_0_bits_data, output io_in_1_ready, input io_in_1_va...
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module Demux_3 ( input io_en, input io_input_valid, input [15:0] io_input_RouteID, input [15:0] io_input_data, input io_sel, output io_outputs_0_valid, output [15:0] io_outputs_0_RouteID, output [15:0] io_outputs_0_data, output io_outputs_1_val...
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module type_detect #( parameter EXP_SIZE = `EXP_SIZE, parameter MANTIS_SIZE = `MANTIS_SIZE ) ( exp, mantis, type ); // Inputs input [EXP_SIZE -1:0] exp; // input exponent input [MANTIS_SIZE-1:0] mantis; // input mantissa // Outputs output reg [2:0] type; // output type parameter [2:0] ZER...
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module decoder3_8_test (); reg [2:0] A; reg g1, g2, g3; wire [7:0] y; decoder3_8 decoder3to8 ( A, g1, g2, g3, y ); initial begin A = 3'b000; g1 = 1; g2 = 0; g3 = 0; #10 A = 3'b000; #10 A = 3'b001; #10 A = 3'b010; #10 A = 3'b011; #10 A = 3'b1...
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module add16_t (); reg [15:0] A, B; reg CI; wire [15:0] Sum; wire CO, G, P; add16 a16 ( A, B, CI, Sum, CO, G, P ); integer i, j, k; parameter TWO_POW_16 = 65536; task doTest; input [15:0] a, b; input ci; begin A = a; B = b...
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