code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
mod_a mod_a_u1 (
out1,
out2,
a,
b,
c,
d
);
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
mod_a u_mod_a (
out1,
out2,
a,
b,
c,
d
);
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
mod_a mod_a_u1 (
.in1 (a),
.in2 (b),
.in3 (c),
.in4 (d),
.out1(out1),
.out2(out2)
);
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
mod_a u_mod_a (
.out1(out1),
.out2(out2),
.in1 (a),
.in2 (b),
.in3 (c),
.in4 (d)
);
endmodule
| 7.203305 |
module asic_multiplier_wrapper (
input [7:0] io_in,
output [7:0] io_out
);
// Instantiate the multiplier
asic_multiplier asic_multiplier_top (
.clk (io_in[0]),
.reset (io_in[1]),
.i_factor_a (io_in[4:2]),
.i_factor_b (io_in[7:5]),
.o_segments (io_out[6:0]),
... | 6.523357 |
module top_module (
input clk,
input d,
output q
);
wire q1;
wire q2;
my_dff u_my_dff_1 (
.clk(clk),
.d (d),
.q (q1)
);
my_dff u_my_dff_2 (
.clk(clk),
.d (q1),
.q (q2)
);
my_dff u_my_dff_3 (
.clk(clk),
.d (q2),
.q (q)
);
endm... | 7.203305 |
module top_module (
input clk,
input d,
output q
);
wire q1;
wire q2;
my_dff my_dff_u1 (
.clk(clk),
.d (d),
.q (q1)
);
my_dff my_dff_u2 (
.clk(clk),
.d (q1),
.q (q2)
);
my_dff my_dff_u3 (
.clk(clk),
.d (q2),
.q (q)
);
endmodule... | 7.203305 |
module top_module (
input clk,
input [7:0] d,
input [1:0] sel,
output [7:0] q
);
wire [7:0] q1, q2, q3;
my_dff8 my_dff8_u1 (
.clk(clk),
.d (d),
.q (q1)
);
my_dff8 my_dff8_u2 (
.clk(clk),
.d (q1),
.q (q2)
);
my_dff8 my_dff8_u3 (
.clk(clk),
... | 7.203305 |
module top_module (
input clk,
input [7:0] d,
input [1:0] sel,
output reg [7:0] q
);
wire [7:0] q1;
wire [7:0] q2;
wire [7:0] q3;
my_dff8 u_my_dff8_1 (
.clk(clk),
.d (d),
.q (q1)
);
my_dff8 u_my_dff8_2 (
.clk(clk),
.d (q1),
.q (q2)
);
my_dff8 u... | 7.203305 |
module top_module (
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
wire [16:0] a_lower = a[15:0];
wire [16:0] a_higher = a[31:16];
wire [16:0] b_lower = b[15:0];
wire [16:0] b_higher = b[31:16];
wire cout1;
wire cout2;
wire [15:0] sum_lower;
wire [15:0] sum_higher;
add16 add16_u... | 7.203305 |
module top_module (
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
wire cout_1;
wire cout_2;
add16 u_add16_1 (
.a(a[15:0]),
.b(b[15:0]),
.cin(1'b0),
.sum(sum[15:0]),
.cout(cout_1)
);
add16 u_add16_2 (
.a(a[31:16]),
.b(b[31:16]),
.cin(cout_1... | 7.203305 |
module tomkeddie_top_tto_a #(
parameter CLOCK_RATE = 1000
) (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire reset = io_in[1];
wire uart_tx_pin0;
wire uart_tx_pin1;
wire uart_tx_pin2;
assign io_out[0] = uart_tx_pin0;
assign io_out[1] = uart_tx_pin1;
assign io_out[2] =... | 6.88019 |
module top_module (
input [31:0] a,
input [31:0] b,
output [31:0] sum
); //
wire [16:0] a_lower = a[15:0];
wire [16:0] a_higher = a[31:16];
wire [16:0] b_lower = b[15:0];
wire [16:0] b_higher = b[31:16];
wire cout1;
wire cout2;
wire [15:0] sum_lower;
wire [15:0] sum_higher;
add16 add... | 7.203305 |
module add1 (
input a,
input b,
input cin,
output sum,
output cout
);
// Full adder module here
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule
| 6.640243 |
module mm21_SPIMaster (
input clock,
input reset,
output tx_ready,
input tx_valid,
input [7:0] tx_byte,
// whether or not to reset CS after sending data
input tx_clear_cs,
output sclk,
output mosi,
output n_cs
);
localparam STATE_IDLE = 2'd0, STATE_CS_ASSERT =... | 6.983741 |
module mm21_LEDColor (
input [2:0] row_idx,
input [2:0] col_idx,
input [5:0] pixel_offset,
output [7:0] pixel
);
wire [2:0] red;
wire [2:0] green;
wire [1:0] blue;
wire is_diagonal;
wire [5:0] green_sum;
wire [5:0] blue_sum;
assign green_sum = {3'd0, col_idx} + pixel_offset;
assign b... | 7.158683 |
module mm21_LEDMatrixDriver (
input clock,
input reset,
output sclk,
output mosi,
output n_cs
);
localparam STATE_RESET_FRAME_INDEX = 1'd0, STATE_SEND_PIXELS = 1'd1;
// command to reset frame index
localparam CMD_RESET_FRAME_INDEX = 8'h26;
localparam PIXEL_MAX = 6'h3f;
reg [0:0] state... | 6.718054 |
module mm21_SevenSeg (
input clock,
input reset,
output up,
output right,
output down,
output left
);
localparam COUNTER_MAX = 8'hff;
// counter to increment upon every clock
reg [7:0] counter;
// state to increment upon every counter wrap
reg [1:0] state;
// set outputs using c... | 6.82882 |
module mm21_LEDMatrixTop (
input [7:0] io_in,
output [7:0] io_out
);
wire clock;
wire reset_async;
wire reset_sync;
// LED matrix wires
wire sclk;
wire mosi;
wire n_cs;
// 7-seg wires
wire up;
wire right;
wire down;
wire left;
assign clock = io_in[0];
assign reset_async = io_in[... | 6.718054 |
module top_module (
input [31:0] a,
input [31:0] b,
output [31:0] sum
); //
wire cout_1;
wire cout_2;
add16 u_add16_1 (
.a(a[15:0]),
.b(b[15:0]),
.cin(1'b0),
.sum(sum[15:0]),
.cout(cout_1)
);
add16 u_add16_2 (
.a(a[31:16]),
.b(b[31:16]),
.cin(co... | 7.203305 |
module add1 (
input a,
input b,
input cin,
output sum,
output cout
);
// Full adder module heredasdsa
assign {cout, sum} = a + b + cin;
endmodule
| 6.640243 |
module top_module (
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
wire [16:0] a_lower = a[15:0];
wire [16:0] a_higher = a[31:16];
wire [16:0] b_lower = b[15:0];
wire [16:0] b_higher = b[31:16];
wire cout1, cout2, cout3;
wire [15:0] sum_lower;
wire [15:0] sum_higher_0;
wire [15:0]... | 7.203305 |
module top_module (
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
wire select_flag;
wire [15:0] sum_high_0;
wire [15:0] sum_high_1;
add16 u_add16_lo (
.a(a[15:0]),
.b(b[15:0]),
.cin(1'b0),
.sum(sum[15:0]),
.cout(select_flag)
);
add16 u_add16_hi0 (
... | 7.203305 |
module top_module (
input [31:0] a,
input [31:0] b,
input sub,
output [31:0] sum
);
wire cout1, cout2;
wire [31:0] exc_b;
assign exc_b = sub ? ~b : b; // XOR
add16 add16_u1 (
.a(a[15:0]),
.b(exc_b[15:0]),
.cin(sub),
.sum(sum[15:0]),
.cout(cout1)
);
add16 add... | 7.203305 |
module top_module (
input [31:0] a,
input [31:0] b,
input sub,
output [31:0] result
);
wire [31:0] c;
wire cout_1;
assign c = sub ? ~b : b;
add16 add16_1 (
.a(a[15:0]),
.b(c[15:0]),
.cin(sub),
.sum(result[15:0]),
.cout(cout_1)
);
add16 add16_2 (
.a (a[3... | 7.203305 |
module top_module (
input a,
input b,
output wire out_assign,
output reg out_alwaysblock
);
assign out_assign = a & b;
always @(*) out_alwaysblock = a & b;
endmodule
| 7.203305 |
module top_module (
input a,
input b,
output wire out_assign,
output reg out_alwaysblock
);
// assign
assign out_assign = a & b;
// always
always @(*) begin
out_alwaysblock = a & b;
end
endmodule
| 7.203305 |
module yubex_egg_timer (
input [7:0] io_in,
output reg [7:0] io_out
);
wire clk;
localparam clk_frequency = 14'd10000; // frequency in Hz
wire rst;
wire start;
assign clk = io_in[0];
assign rst = io_in[1];
assign start = io_in[2];
reg [1:0] state;
localparam idle = 2'b00;
localparam... | 7.569101 |
module top_module (
input clk,
input shift_ena,
input count_ena,
input data,
output [3:0] q
);
reg [3:0] o_q = 4'b0;
assign q = o_q;
always @(posedge clk) begin
if (shift_ena) begin
o_q <= {o_q[2:0], data};
end else if (count_ena) begin
o_q <= o_q - 1'b1;
end else beg... | 7.203305 |
module and_gate ( // This module implements a 2-input AND gate
a,
b,
c
);
input a;
input b;
output c;
assign c = a & b; // `c` is driven by `a & b`
endmodule
| 9.274676 |
module and3_gate ( // This module implements a 3-input AND gate
in1,
in2,
in3,
out
);
// input in1;
// input in2;
// input in3;
input in1, in2, in3;
output out;
assign out = in1 & in2 & in3;
endmodule
| 8.910591 |
module nand_gate ( // This module implements a 2-input NAND gate
a,
b,
c
);
input a;
input b;
output c;
assign c = ~(a & b);
endmodule
| 9.287559 |
module two_of_three ( // The output of this module is 1 iff 2 of its inputs are equal to 1.
a,
b,
c,
out
);
input a;
input b;
input c;
output out;
assign out = (a & (b ^ c)) | (~a & b & c);
endmodule
| 7.244658 |
module declaration syntax here:
module top_module(clk, reset, in, out);
input clk;
input reset; // Synchronous reset to state B
input in;
output out;//
reg out;
// Fill in state name declarations
parameter A = 0 ;
parameter B = 1 ;
reg present_state, next_state;
always @(... | 6.89453 |
module sync_fifo_ver2 (
clk,
rst_n,
wr,
rd,
din,
dout,
full,
empty
);
input clk, rst_n;
input wr, rd;
input [7:0] din;
output [7:0] dout;
reg [7:0] dout;
output full, empty;
reg full, empty;
reg [7:0] mem[15:0];
reg [3:0] wp, rp;
always @(posedge clk or negedge rst_... | 6.509696 |
module sync_fifo_ver2_tb ();
reg clk, rst_n, wr, rd;
reg [7:0] din;
wire [7:0] dout;
wire full, empty;
reg [7:0] temp = 0;
initial begin
clk = 0;
rst_n = 1;
wr = 0;
rd = 0;
#10 rst_n = 0;
#10 rst_n = 1;
push(1);
push(2);
push(3);
push(4);
push(5);
push(6);
... | 6.509696 |
module top_module (
input in,
output out
);
assign out = in;
endmodule
| 7.203305 |
module top_module (
input in,
output out
);
assign out = in;
endmodule
| 7.203305 |
module top_module (
input a,
input b,
output out
);
assign out = !(a || b);
endmodule
| 7.203305 |
module f4 (
output [3:0] s,
input [3:0] a,
input [3:0] b
);
and and1 (s[0], a[0], b[0]);
and and2 (s[1], a[1], b[1]);
and and3 (s[2], a[2], b[2]);
and and4 (s[3], a[3], b[3]);
endmodule
| 6.784298 |
module f4 (output [3:0] s,
input [3:0] chave, //definida apenas por 0000 ou 0001
input [3:0] a,
input [3:0] b);
wire [3:0] w1;
wire [3:0] w2;
wire [3:0] w3;
wire [3:0] w4;
wire [3:0] w5;
rand and1 (w1,a,b);
ror or1 (w2,a,b);
rnot not1 (w3,chave);
rand and2 (w4,w1,chave);
ran... | 6.842475 |
module f4 (output [3:0] s,
input [3:0] chave, //definida apenas por 0000 ou 0001
input [3:0] grupo, //definida da mesma forma que a chave
input [3:0] a,
input [3:0] b);
wire [3:0] w1;
wire [3:0] w2;
wire [3:0] w3;
wire [3:0] w4;
wire [3:0] w5;
wire [3:0] w6;
wire [3:0... | 6.842475 |
module circ (
output s,
input chave,
input grupo,
input a,
input b
);
xor xor1 (w1, a, b);
xnor xnor1 (w2, a, b);
or or1 (w3, a, b);
nor nor1 (w4, a, b);
not not1 (m1, chave);
//mux1
and and1 (m2, w1, m1);
and and2 (m3, w2, chave);
and and3 (m4, w3, m1);
and and5 (m5, w4, c... | 8.388756 |
module testcirc;
reg a, b, chave, grupo;
wire s;
circ circ1 (
s,
chave,
grupo,
a,
b
);
initial begin
a = 0;
b = 0;
chave = 0;
grupo = 0;
end
initial begin
$display("Eduardo Botelho de Andrade - 427395");
$display("Test LU's module");
$display("... | 8.149214 |
module top_module (
input clk,
input a,
input b,
output wire out_assign,
output reg out_always_comb,
output reg out_always_ff
);
assign out_assign = a ^ b;
always @(*) out_always_comb = a ^ b;
always @(posedge clk) out_always_ff <= a ^ b;
endmodule
| 7.203305 |
module top_module (
input clk,
input a,
input b,
output wire out_assign,
output reg out_always_comb,
output reg out_always_ff
);
// assign
assign out_assign = a ^ b;
// always @(*)
always @(*) begin
out_always_comb = a ^ b;
end
// always @(posedge clk)
always @(posedge clk) be... | 7.203305 |
module top_module (
input a,
input b,
input sel_b1,
input sel_b2,
output wire out_assign,
output reg out_always
);
// assign
assign out_assign = (sel_b1 & sel_b2) ? b : a;
// always
always @(*) begin
if (sel_b1 & sel_b2) out_always = b;
else out_always = a;
end
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input sel_b1,
input sel_b2,
output wire out_assign,
output reg out_always
);
assign out_assign = (sel_b1 & sel_b2) ? b : a;
always @(*) begin
if (sel_b1 & sel_b2) out_always = b;
else out_always = a;
end
endmodule
| 7.203305 |
module zoechip #(
parameter MAX_COUNT = 1000
) (
input [7:0] io_in,
output [7:0] io_out
);
wire A, B, C, D, F, G, M;
assign io_out = {1'b0, D, B, G, F, M, C, A};
wire Z = io_in[0];
wire O = io_in[1];
wire E = io_in[2];
wire f = io_in[3];
assign A = Z + O + E;
assign B = O + E + f;
assi... | 6.878561 |
module top_module (
input cpu_overheated,
output reg shut_off_computer,
input arrived,
input gas_tank_empty,
output reg keep_driving
); //
always @(*) begin
if (cpu_overheated) shut_off_computer = 1;
else shut_off_computer = 0;
end
always @(*) begin
if (~arrived) ... | 7.203305 |
module top_module (
input cpu_overheated,
output reg shut_off_computer,
input arrived,
input gas_tank_empty,
output reg keep_driving
); //
always @(*) begin
if (cpu_overheated) shut_off_computer = 1;
else shut_off_computer = 0;
end
always @(*) begin
if (arrived | ... | 7.203305 |
module top_module (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out
); //
always @(*) begin // This is a combinational circuit
case (sel)
3'b000: out = data0;
3'b... | 7.203305 |
module top_module (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out
); //
always @(*) begin // This is a combinational circuit
case (sel)
4'd0: out = data0;
4'd1: ... | 7.203305 |
module mbikovitsky_top #(
parameter CLOCK_HZ = 625,
parameter BAUD = 78,
parameter ROM_WORDS = 4
) (
input [7:0] io_in,
output [7:0] io_out
);
localparam LFSR_BITS = 5;
wire clk = io_in[0];
wire mode_cpu = reset_lfsr & reset_taps;
assign io_out = mode_cpu ? cpu_io_out[7:0] : segments;
... | 6.931629 |
module top_module (
input [3:0] in,
output reg [1:0] pos
);
always @(*) begin
case (in)
4'b0000, 4'b0001, 4'b0011, 4'b0101, 4'b0111, 4'b1001, 4'b1011, 4'b1101, 4'b1111: pos = 2'b00;
4'b0010, 4'b0110, 4'b1010, 4'b1110: pos = 2'b01;
4'b0100, 4'b1100: pos = 2'b10;
4'b1000: pos = 2'b... | 7.203305 |
module top_module (
input [3:0] in,
output reg [1:0] pos
);
always @(*) begin
if (in[0] == 1) pos = 2'd0;
else if (in[1] == 1) pos = 2'd1;
else if (in[2] == 1) pos = 2'd2;
else if (in[3] == 1) pos = 2'd3;
else pos = 2'd0;
end
endmodule
| 7.203305 |
module top_module (
// input [3:0] in,
// output reg [1:0] pos
// );
// always @(*) begin // Combinational always block
// case (in)
// 4'h0: pos = 2'h0; // I like hexadecimal because it saves typing.
// 4'h1: pos = 2'h0;
// 4'h2: pos = 2'h1;
// 4'h3: pos = 2'h0;
// 4'h4: pos = 2'h2;
// 4'h5: ... | 7.203305 |
module top_module (
input [7:0] in,
output reg [2:0] pos
);
always @(*) begin
casez (in)
8'b0000_0000, 8'b????_???1: pos = 3'b000;
8'b????_??10: pos = 3'b001;
8'b????_?100: pos = 3'b010;
8'b????_1000: pos = 3'b011;
8'b???1_0000: pos = 3'b100;
8'b??10_0000: pos = 3'b101... | 7.203305 |
module top_module (
input [7:0] in,
output reg [2:0] pos
);
always @(*) begin
casez (in)
8'bzzzz_zzz1: pos = 8'd0;
8'bzzzz_zz1z: pos = 8'd1;
8'bzzzz_z1zz: pos = 8'd2;
8'bzzzz_1zzz: pos = 8'd3;
8'bzzz1_zzzz: pos = 8'd4;
8'bzz1z_zzzz: pos = 8'd5;
8'bz1zz_zzzz: pos ... | 7.203305 |
module top_module (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up
);
// set default value before case statement
always @(*) begin
left = 1'b0;
down = 1'b0;
right = 1'b0;
up = 1'b0;
case (scancode)
16'he06b: left = 1'b1;
... | 7.203305 |
module top_module (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up
);
always @(*) begin
left = 0;
down = 0;
right = 0;
up = 0;
case (scancode)
16'he06b: left = 1;
16'he072: down = 1;
16'he074: right = 1;
16... | 7.203305 |
module top_module (
input [7:0] a,
b,
c,
d,
output [7:0] min
);
// assign intermediate_result1 = compare? true: false;
wire [7:0] min1;
wire [7:0] min2;
assign min1 = (a < b) ? a : b;
assign min2 = (c < d) ? c : d;
assign min = (min1 < min2) ? min1 : min2;
endmodule
| 7.203305 |
module top_module (
input [7:0] a,
b,
c,
d,
output reg [7:0] min
); //
// assign intermediate_result1 = compare? true: false;
reg [7:0] min_1;
reg [7:0] min_2;
always @(*) begin
min_1 = (a < b) ? a : b;
min_2 = (c < d) ? c : d;
min = (min_1 < min_2) ? min_1 : min_2;
end
e... | 7.203305 |
module top_module (
input [7:0] in,
output parity
);
assign parity = ^in;
endmodule
| 7.203305 |
module top_module (
input [7:0] in,
output parity
);
// even partity
assign parity = ^in;
endmodule
| 7.203305 |
module top_module (
input [99:0] in,
output out_and,
output out_or,
output out_xor
);
// reduction
assign out_and = ∈
assign out_or = |in;
assign out_xor = ^in;
endmodule
| 7.203305 |
module SPIController (
// System Interfaces
input wire clk,
input wire rst,
// SPI Bus Interfaces
output reg CS0,
output reg CS1,
output reg SPICLK,
output reg MOSI,
input wire MISO,
// Input Signals
input wire Addr15, // Sampled on Phase 01
input wire Read_notWri... | 7.271463 |
module top_module (
input [99:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and = ∈
assign out_or = |in;
assign out_xor = ^in;
endmodule
| 7.203305 |
module async_fifo_ver1 (
rst_n,
wr_clk,
wr_en,
din,
rd_clk,
rd_en,
dout,
empty,
full
);
input rst_n;
input wr_clk, wr_en;
input rd_clk, rd_en;
input [`data_width-1:0] din;
output full, empty;
wire full, empty;
output [`data_width-1:0] dout;
reg [`data_width-1:0] dout;... | 6.722882 |
module async_fifo_ver1_tb ();
reg rst_n, wr_clk, wr_en, rd_clk, rd_en;
reg [`data_width-1:0] din;
wire full, empty;
wire [`data_width-1:0] dout;
reg [`data_width-1:0] temp = 0;
initial begin
rst_n = 1;
wr_clk = 0;
wr_en = 0;
rd_clk = 0;
rd_en = 0;
#10 rst_n = 0;
#10 rst_n =... | 6.722882 |
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output start_shifting
);
parameter IDLE = 3'b000;
parameter S0 = 3'b001;
parameter S1 = 3'b010;
parameter S2 = 3'b011;
parameter S3 = 3'b100;
reg [2:0] cstate, nstate;
always @(posedge clk) begin
... | 7.203305 |
module top_module (
input clk,
input areset, // Asynchronous reset to OFF
input j,
input k,
output out
); //
parameter OFF = 0, ON = 1;
reg state, next_state;
always @(*) begin
// State transition logic
case (state)
OFF: next_state = j ? ON : OFF;
ON: next_state ... | 7.203305 |
module nand_with_wire (
a,
b,
c
);
input a;
input b;
output c;
wire tmp;
assign tmp = a & b;
assign c = ~tmp;
endmodule
| 6.611817 |
module delay_time (
clk,
rst_n,
in_data,
out_data
);
input clk, rst_n, in_data;
output out_data;
reg [2:0] cnt_ctrl; //打两拍
always @(posedge clk) begin
cnt_ctrl <= {cnt_ctrl[1:0], in_data};
end
/* always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
cnt_ctrl <= 3'b0;
end... | 6.676482 |
module BCD_Adder (
Sum,
Carry_out,
Addend,
Augend,
Carry_in
);
output [3:0] Sum;
output Carry_out;
input [3:0] Addend, Augend;
input Carry_in;
wire [3:0] z, z1;
wire k;
assign {k, z} = Addend + Augend + Carry_in;
assign Carry_out = (z[1] && z[3]) || (z[2] && z[3]) || k;
assign z1[... | 7.619207 |
module top_module (
input a,
b,
c,
output w,
x,
y,
z
);
assign w = a; //assign statements are executed in parallel
assign x = b;
assign y = b;
assign z = c;
endmodule
| 7.203305 |
module top_module (
input a,
b,
c,
output w,
x,
y,
z
);
assign w = a;
assign x = b;
assign y = b;
assign z = c;
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output out,
output out_n
);
wire w1 = a && b;
wire w2 = c && d;
assign out = w1 || w2;
assign out_n = !(w1 || w2);
endmodule
| 7.203305 |
module fa4bit (
output [2:0] s,
output carryout,
input [3:0] a,
input [3:0] b,
input carryin
);
or or1 (sinal, a[3], b[3]);
fa fa1 (
s[0],
w1,
a[0],
b[0],
sinal
);
fa fa2 (
s[1],
w2,
a[1],
b[1],
w1
);
fa fa3 (
s[2],
... | 7.14019 |
module fs4bit (
output [2:0] s,
output carryout,
input [3:0] a,
input [3:0] b,
input carryin
);
or or1 (sinal, a[3], b[3]);
fs fs1 (
s[0],
w1,
a[0],
b[0],
sinal
);
fs fs2 (
s[1],
w2,
a[1],
b[1],
w1
);
fs fs3 (
s[2],
... | 7.263759 |
module different (
output s,
input [3:0] a,
input [3:0] b
);
xor xor1 (w1, a[0], b[0]);
xor xor2 (w2, a[1], b[1]);
xor xor3 (w3, a[2], b[2]);
xor xor4 (w4, a[3], b[3]);
or or1 (s, w1, w2, w3, w4);
endmodule
| 6.956141 |
module top_module (
input [99:0] in,
output [99:0] out
);
reg [7:0] cnt;
always @(*) begin
for (cnt = 8'd0; cnt < 100; cnt = cnt + 1) begin
out[cnt] = in[99-cnt];
end
end
endmodule
| 7.203305 |
module top_module (
// input [99:0] in,
// output reg [99:0] out
// );
// always @(*) begin
// for (int i=0;i<$bits(out);i++) // $bits() is a system function that returns the width of a signal.
// out[i] = in[$bits(out)-i-1]; // $bits(out) is 100 because out is 100 bits wide.
// end
// endmodule
| 7.203305 |
module top_module (
input [99:0] in,
output reg [99:0] out
);
integer i;
always @(*) begin
for (i = 0; i <= 99; i = i + 1) begin
out[i] = in[99-i];
end
end
endmodule
| 7.203305 |
module mixer (
input clk,
input write_data,
input [5:0] data,
input voice0_out,
input voice1_out,
output [3:0] out
);
reg [5:0] voice_volumes;
always @(posedge clk) begin
if (write_data) voice_volumes <= data;
end
wire [2:0] voice0_volume = voice_volumes[2:0];
wire [2:0] voice1_... | 6.918526 |
module yupferris_bitslam (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire addr_data_sel = io_in[1];
wire write_addr = ~addr_data_sel;
wire write_data = addr_data_sel;
wire [5:0] addr_data = io_in[7:2];
wire [5:0] data = addr_data;
reg [2:0] addr;
always @(posedge clk) b... | 6.800173 |
module top_module (
input [254:0] in,
output [ 7:0] out
);
always @(*) begin
out = 0;
for (int i = 0; i < $bits(in); i = i + 1) begin
if (in[i] == 1) out = out + 1;
end
end
endmodule
| 7.203305 |
module top_module (
input [254:0] in,
output reg [7:0] out
);
integer count;
always @(*) begin : count_b
integer i;
count = 0;
for (i = 0; i <= 254; i = i + 1) begin
if (in[i]) count = count + 1;
end
out = {count[7:0]};
end
endmodule
| 7.203305 |
module top_module (
input [99:0] a,
b,
input cin,
output [99:0] cout,
output [99:0] sum
);
genvar i;
generate
begin
for (i = 0; i <= 99; i = i + 1) begin : adder_loop
if (i == 0)
adder1 u_adder1 (
.a(a[i]),
.b(b[i]),
.cin(ci... | 7.203305 |
module adder1 (
input a,
input b,
input cin,
output sum,
output cout
);
assign {cout, sum} = a + b + cin;
endmodule
| 7.322982 |
module top_module (
input [99:0] a,
b,
input cin,
output [99:0] cout,
output [99:0] sum
);
wire [99:0] new_cin;
assign new_cin = {cout[98:0], cin};
always @(*) begin
for (int i = 0; i < $bits(cout); i = i + 1) begin
sum[i] = a[i] ^ b[i] ^ new_cin[i];
cout[i] = (a[i] & b[i])... | 7.203305 |
module github_com_proppy_tt02_xls_popcount (
input wire [7:0] io_in,
output wire [7:0] io_out
);
user_module user_module0 (
io_in,
io_out
);
endmodule
| 7.341325 |
module top_module (
input [399:0] a,
b,
input cin,
output cout,
output [399:0] sum
);
genvar i;
wire [99:0] cout_temp;
// generate circular instance
generate
begin
for (i = 0; i <= 99; i = i + 1) begin : bcd_add_loop
if (i == 0)
bcd_fadd u_bcd_fadd (
... | 7.203305 |
module top_module (
input [399:0] a,
b,
input cin,
output cout,
output [399:0] sum
);
wire [99:0] fadd_cin;
wire [99:0] fadd_cout;
assign fadd_cin = {fadd_cout[98:0], cin};
generate
genvar i;
for (i = 0; i < 8'd100; i = i + 1) begin : BCD_loop
bcd_fadd bcd_fadd_u0 (
... | 7.203305 |
module top_module(
// input [399:0] a, b,
// input cin,
// output cout,
// output [399:0] sum );
// wire [99:0] fadd_cin;
// wire [99:0] fadd_cout;
// assign fadd_cin = {fadd_cout[98:0], cin};
// bcd_fadd bcd_fadd_u0 [99:0](
// .a(a),
// .b(b),
// .cin(fadd_c... | 6.631647 |
module rc5_top (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire reset = io_in[1];
wire ir = io_in[2];
wire [6:0] led_out;
assign io_out[6:0] = led_out;
wire valid;
wire [5:0] command;
wire control;
reg control_d;
localparam [5:0] RC5_INCR_VOLUME = 16;
localparam [5:... | 6.522639 |
module top_module (
input in,
output out
);
assign out = in;
endmodule
| 7.203305 |
module top_module (
output out
);
assign out = 1'b0;
endmodule
| 7.203305 |
module top_module (
input in1,
input in2,
output out
);
assign out = ~(in1 | in2);
endmodule
| 7.203305 |
module top_module (
input in1,
input in2,
output out
);
assign out = in1 & ~(in2);
endmodule
| 7.203305 |
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