repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand2/sky130_fd_sc_hd__nand2.functional.v | 1,270 | module MODULE1 (
VAR4,
VAR1,
VAR2
);
output VAR4;
input VAR1;
input VAR2;
wire VAR5;
nand VAR6 (VAR5, VAR2, VAR1 );
buf VAR3 (VAR4 , VAR5 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp.pp.blackbox.v | 1,321 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR2 ,
VAR5 ,
VAR9,
VAR7,
VAR3,
VAR6 ,
VAR8
);
output VAR4 ;
input VAR1 ;
input VAR2 ;
input VAR5 ;
input VAR9;
input VAR7;
input VAR3;
input VAR6 ;
input VAR8 ;
endmodule | apache-2.0 |
AndreaCorallo/KPU | rtl/kpu/ctrl.v | 4,057 | module MODULE2(
input wire VAR2, VAR13,
input wire [VAR4-1:0] VAR19, VAR20,
input wire [VAR4-1:0] VAR21,
input wire [VAR4-1:0] VAR14,
input wire [4:0] VAR15, VAR9,
input wire [4:0] VAR11,
input wire [4:0] VAR17,
output reg [VAR4-1:0] VAR10, VAR6
);
always @ begin
if (VAR11 == VAR9 &&
VAR2 == 1'b1)
VAR6 = VAR21;
end
els... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or2/sky130_fd_sc_hs__or2.functional.v | 1,663 | module MODULE1 (
VAR3,
VAR11,
VAR6 ,
VAR4 ,
VAR8
);
input VAR3;
input VAR11;
output VAR6 ;
input VAR4 ;
input VAR8 ;
wire VAR9 ;
wire VAR5;
or VAR10 (VAR9 , VAR8, VAR4 );
VAR2 VAR1 (VAR5, VAR9, VAR3, VAR11);
buf VAR7 (VAR6 , VAR5 );
endmodule | apache-2.0 |
theapi/de0-nano | rotary_encoder/quadrature_decode.v | 1,591 | module MODULE1(
reset,
VAR4,
VAR2,
VAR1
);
input reset, VAR4, VAR2;
output [7:0] VAR1;
reg [3:0] VAR6; reg [7:0] VAR3;
reg [2:0] VAR5;
always @ ( * )
begin
if (reset) begin
VAR6 = 4'b0000;
VAR3 = 0;
VAR5 = 0;
end
else begin
VAR6 = VAR6 << 2;
VAR6 = VAR6 | {VAR4, VAR2};
VAR5 = 0;
case (VAR6)
4'b0000 : VAR5 = 2'd0;
4'b00... | mit |
ehliar/schematic_gui | mux5.v | 1,285 | module MODULE1 #(parameter VAR4 = 1) (input wire [2:0] VAR6,
input wire [VAR4:0] VAR3, VAR8, VAR5,VAR2, VAR1,
output reg [VAR4:0] VAR7); | gpl-3.0 |
Jesus89/open-fpga-verilog-tutorial | tutorial/ICESTICK/T21-baud-tx/baudtx.v | 2,169 | module MODULE1(input wire clk, input wire VAR1, output wire VAR4 );
parameter VAR6 = VAR8;
reg [9:0] VAR5;
wire VAR11;
always @(posedge VAR11)
if (VAR1 == 0)
VAR5 <= {"VAR2",2'b01};
else
VAR5 <= {1'b1, VAR5[9:1]};
assign VAR4 = (VAR1) ? VAR5[0] : 1;
VAR7 #(VAR6)
VAR9 (
.VAR10(clk),
.VAR3(VAR11)
);
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and2/sky130_fd_sc_hdll__and2.behavioral.pp.v | 1,801 | module MODULE1 (
VAR13 ,
VAR12 ,
VAR3 ,
VAR8,
VAR5,
VAR9 ,
VAR1
);
output VAR13 ;
input VAR12 ;
input VAR3 ;
input VAR8;
input VAR5;
input VAR9 ;
input VAR1 ;
wire VAR6 ;
wire VAR7;
and VAR4 (VAR6 , VAR12, VAR3 );
VAR10 VAR2 (VAR7, VAR6, VAR8, VAR5);
buf VAR11 (VAR13 , VAR7 );
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/de/de_top.v | 27,888 | module MODULE1
(
input VAR29, input VAR173,
input VAR75, input VAR206, input [8:2] VAR123, input [13:2] VAR166, input [8:2] VAR170, input VAR32, input [3:0] VAR297, input [31:0] VAR33, input VAR53, input VAR194, input VAR152, input VAR153, input VAR54, VAR193, VAR226, input [53:0] VAR71, input VAR132, input VAR243, inp... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fahcon/sky130_fd_sc_lp__fahcon.functional.v | 1,733 | module MODULE1 (
VAR14,
VAR10 ,
VAR1 ,
VAR8 ,
VAR3
);
output VAR14;
output VAR10 ;
input VAR1 ;
input VAR8 ;
input VAR3 ;
wire VAR11 ;
wire VAR12 ;
wire VAR13 ;
wire VAR5 ;
wire VAR4;
xor VAR6 (VAR11 , VAR1, VAR8, VAR3 );
buf VAR7 (VAR10 , VAR11 );
nor VAR17 (VAR12 , VAR1, VAR8 );
nor VAR2 (VAR13 , VAR1, VAR3 );
nor VA... | apache-2.0 |
cafe-alpha/wascafe | v13/r07c_de10_20201010_abus3/wasca/synthesis/submodules/wasca_hex0.v | 2,094 | module MODULE1 (
address,
VAR9,
clk,
VAR7,
VAR4,
VAR1,
VAR5,
VAR6
)
;
output [ 6: 0] VAR5;
output [ 31: 0] VAR6;
input [ 1: 0] address;
input VAR9;
input clk;
input VAR7;
input VAR4;
input [ 31: 0] VAR1;
wire VAR3;
reg [ 6: 0] VAR2;
wire [ 6: 0] VAR5;
wire [ 6: 0] VAR8;
wire [ 31: 0] VAR6;
assign VAR3 = 1;
assign VAR8 ... | gpl-2.0 |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_crossbar_v2_1/hdl/verilog/axi_crossbar_v2_1_addr_decoder.v | 11,631 | module MODULE1 #
(
parameter VAR19 = "none",
parameter integer VAR34 = 2, parameter integer VAR51 = 1, parameter integer VAR20 = 1, parameter integer VAR2 = 32, parameter integer VAR15 = 0, parameter integer VAR53 = 1, parameter integer VAR25 = 0, parameter [VAR34*VAR20*64-1:0] VAR7 = {VAR34*VAR20*64{1'b1}},
parameter ... | gpl-3.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/system/synthesis/submodules/altera_reset_controller.v | 12,023 | module MODULE1
parameter VAR17 = 6,
parameter VAR23 = 0,
parameter VAR78 = 0,
parameter VAR6 = 0,
parameter VAR49 = 0,
parameter VAR58 = 0,
parameter VAR76 = 0,
parameter VAR66 = 0,
parameter VAR36 = 0,
parameter VAR12 = 0,
parameter VAR52 = 0,
parameter VAR61 = 0,
parameter VAR34 = 0,
parameter VAR9 = 0,
parameter VAR... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_1.behavioral.pp.v | 1,328 | module MODULE1( VAR5, VAR4, VAR9, VAR8, VAR3, VAR2 );
input VAR8, VAR9, VAR5;
inout VAR3, VAR2;
output VAR4;
VAR6 VAR1(.VAR5(VAR5),.VAR4(VAR4),.VAR9(VAR9),.VAR8(VAR8),.VAR3(VAR3),.VAR2(VAR2));
VAR6 VAR7(.VAR5(VAR5),.VAR4(VAR4),.VAR9(VAR9),.VAR8(VAR8),.VAR3(VAR3),.VAR2(VAR2)); | apache-2.0 |
timofonic/fpga_nes | hw/src/ppu/ppu.v | 9,305 | module MODULE1
(
input wire VAR106, input wire VAR91, input wire [ 2:0] VAR45, input wire VAR125, input wire VAR98, input wire [ 7:0] VAR79, input wire [ 7:0] VAR80, output wire VAR41, output wire VAR46, output wire [ 2:0] VAR115, output wire [ 2:0] VAR94, output wire [ 1:0] VAR76, output wire [ 7:0] VAR20, output wire... | bsd-2-clause |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_histogram/solution1/syn/verilog/doHist_CTRL_BUS_s_axi.v | 8,604 | module MODULE1
VAR20 = 4,
VAR47 = 32
)(
input wire VAR42,
input wire VAR12,
input wire VAR32,
input wire [VAR20-1:0] VAR31,
input wire VAR36,
output wire VAR23,
input wire [VAR47-1:0] VAR15,
input wire [VAR47/8-1:0] VAR11,
input wire VAR35,
output wire VAR40,
output wire [1:0] VAR41,
output wire VAR27,
input wire VAR24... | gpl-3.0 |
omicronns/studies-sys-rek | lab4/zlozony/src/zlozony.v | 2,939 | module MODULE1(
input clk,
input VAR25,
input [17:0] VAR15,
input [7:0] VAR11,
input [11:0] VAR32,
input [7:0] VAR8,
input [13:0] VAR20,
input [18:0] VAR6,
output [36:0] VAR23
);
wire [18:0] VAR33;
wire [11:0] VAR22;
wire [14:0] VAR21;
wire [14:0] VAR10;
wire [19:0] VAR19;
wire [30:0] VAR2;
wire [34:0] VAR13;
VAR26 VAR... | mit |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/ui_wr_data.v | 20,862 | module MODULE1 #
(
parameter VAR57 = 100,
parameter VAR67 = 256,
parameter VAR41 = 32,
parameter VAR98 = "VAR81",
parameter VAR56 = "VAR81",
parameter VAR51 = 5
)
(
VAR74, VAR101, VAR89, VAR42, VAR75,
VAR39,
rst, clk, VAR44, VAR58, VAR9, VAR104,
VAR70, VAR64, VAR1, VAR13, VAR11,
VAR86, VAR33
);
input rst;
input clk;
in... | mit |
theapi/de0-nano | vga/vga_800x480_buffered/ip_ram/ip_ram.v | 7,182 | module MODULE1 (
address,
VAR23,
VAR28,
VAR12,
VAR35);
input [14:0] address;
input VAR23;
input [15:0] VAR28;
input VAR12;
output [15:0] VAR35;
tri1 VAR23;
wire [15:0] VAR50;
wire [15:0] VAR35 = VAR50[15:0];
VAR26 VAR8 (
.VAR10 (address),
.VAR18 (VAR23),
.VAR7 (VAR28),
.VAR31 (VAR12),
.VAR22 (VAR50),
.VAR5 (1'b0),
.VAR... | mit |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.ip_user_files/ipstatic/axi_traffic_gen_v2_0_7/hdl/src/verilog/axi_traffic_gen_v2_0_systeminit_dmg.v | 7,086 | module MODULE1
parameter VAR12 = "VAR54" ,
parameter VAR10 = 4 , parameter VAR31 = 16 , parameter VAR11 = "VAR6.VAR45"
) (
input [VAR10-1 : 0] VAR26 ,
input clk ,
input VAR18 ,
output [31 : 0] VAR33
);
VAR51 #(
.VAR20 (VAR10 ),
.VAR2 ("0" ),
.VAR42 (VAR31),
.VAR12 (VAR12 ),
.VAR13 (1 ),
.VAR19 (0 ),
.VAR3 (0 ),
.VAR16 ... | gpl-3.0 |
migajv/mips_pipeline | verilog/cdb.v | 1,194 | module MODULE1 (
input clk,
input rst,
input VAR14,
input VAR11,
input [31:0] VAR16,
input [3:0] VAR8,
input [31:0] VAR9,
input [3:0] VAR13,
output VAR5,
output VAR10,
output reg [31:0] VAR18,
output reg [3:0] VAR15,
output reg VAR4
);
wire [1:0] VAR6;
VAR3 #(.VAR12(2)) VAR17 (
.req ({VAR14, VAR11}),
.clk (clk),
.rst (... | gpl-3.0 |
alexforencich/verilog-ethernet | rtl/eth_mac_1g_rgmii_fifo.v | 10,813 | module MODULE1 #
(
parameter VAR15 = "VAR82",
parameter VAR9 = "VAR55",
parameter VAR89 = "VAR84",
parameter VAR20 = "VAR78",
parameter VAR12 = 8,
parameter VAR115 = (VAR12>8),
parameter VAR38 = (VAR12/8),
parameter VAR134 = 1,
parameter VAR109 = 64,
parameter VAR76 = 4096,
parameter VAR25 = 1,
parameter VAR5 = 1,
para... | mit |
sh-chris110/chris | FPGA/chris.sdram.ok/db/ip/soc_design/submodules/soc_design_mm_interconnect_0_avalon_st_adapter_006.v | 6,176 | module MODULE1 #(
parameter VAR11 = 18,
parameter VAR16 = 0,
parameter VAR5 = 18,
parameter VAR6 = 0,
parameter VAR8 = 0,
parameter VAR9 = 0,
parameter VAR25 = 1,
parameter VAR7 = 1,
parameter VAR18 = 0,
parameter VAR13 = 18,
parameter VAR2 = 0,
parameter VAR10 = 1,
parameter VAR3 = 0,
parameter VAR17 = 1,
parameter VA... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/util_pmod_adc/util_pmod_adc.v | 10,893 | module MODULE1 (
clk,
reset,
VAR21,
VAR1,
VAR14,
VAR11,
VAR26,
VAR10,
VAR9,
VAR37
);
parameter VAR39 = 100; parameter VAR23 = 100; parameter VAR8 = 650; parameter VAR35 = 60; parameter VAR25 = 12;
parameter VAR7 = 3;
parameter VAR22 = 16;
localparam VAR15 = 0;
localparam VAR5 = 1;
localparam VAR4 = 2;
localparam VAR31 ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor3b/sky130_fd_sc_hs__nor3b.symbol.v | 1,305 | module MODULE1 (
input VAR2 ,
input VAR1 ,
input VAR5,
output VAR4
);
supply1 VAR3;
supply0 VAR6;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fah/sky130_fd_sc_lp__fah.symbol.v | 1,296 | module MODULE1 (
input VAR7 ,
input VAR8 ,
input VAR6 ,
output VAR3,
output VAR4
);
supply1 VAR2;
supply0 VAR5;
supply1 VAR1 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
sirchuckalot/zet-ng | rtl/zet.v | 3,129 | module MODULE1 (
input VAR5,
input VAR35,
input [15:0] VAR22,
output [19:1] VAR38,
output [ 1:0] VAR3,
output VAR26,
output VAR34,
input VAR43,
input [15:0] VAR32,
output [15:0] VAR17,
output [19:1] VAR8,
output VAR40,
output VAR4, output [ 1:0] VAR42,
output VAR24,
output VAR30,
input VAR21,
input VAR33, output VAR7, ... | gpl-3.0 |
James534/SubZero | SubZero/fpga/fpga_hw/top_level/DE0_Nano_SOPC/synthesis/submodules/altera_avalon_st_clock_crosser.v | 5,027 | module MODULE1(
VAR3,
VAR32,
VAR2,
VAR1,
VAR26,
VAR30,
VAR20,
VAR24,
VAR19,
VAR4
);
parameter VAR22 = 1;
parameter VAR21 = 8;
parameter VAR13 = 2;
parameter VAR12 = 2;
parameter VAR17 = 1;
localparam VAR25 = VAR22 * VAR21;
input VAR3;
input VAR32;
output VAR2;
input VAR1;
input [VAR25-1:0] VAR26;
input VAR30;
input VAR... | mit |
scalable-networks/ext | uhd/fpga/usrp2/fifo/fifo19_pad.v | 2,400 | module MODULE1
parameter VAR13=0)
(input clk, input reset, input VAR10,
input [18:0] VAR11,
input VAR2,
output VAR15,
output [18:0] VAR8,
output VAR16,
input VAR6);
reg [15:0] VAR4;
reg [1:0] VAR3;
localparam VAR12 = 0;
localparam VAR1 = 1;
localparam VAR5 = 2;
localparam VAR9 = 3;
always @(posedge clk)
if(reset | VAR1... | gpl-2.0 |
eda-globetrotter/MarcheProcessor | src/hazard_detect.v | 37,697 | module MODULE1(VAR4, VAR6, VAR2,
VAR3, VAR7, VAR1, VAR5);
input [0:31] VAR4, VAR6, VAR2;
output VAR3, VAR7, VAR1, VAR5;
reg VAR3, VAR7, VAR1, VAR5;
parameter VAR8 = 1'b0;
parameter VAR9 = 1'b1;
always @ (VAR4 or VAR2)
begin
if (VAR4[2] == 1'b1) begin
if (VAR2[2] == 1'b1) begin
VAR3 <= (VAR4[11:15]==VAR2[6:10])? VAR9 : ... | mit |
csail-csg/riscy-OOO | procs/asic/bluespec_verilog/ConfigRegUN.v | 1,842 | module MODULE1(VAR2, VAR3, VAR6, VAR1);
parameter VAR4 = 1;
input VAR2;
input VAR3;
input [VAR4 - 1 : 0] VAR6;
output [VAR4 - 1 : 0] VAR1;
reg [VAR4 - 1 : 0] VAR1;
VAR1 = {((VAR4 + 1)/2){2'b10}} ;
end
always@(posedge VAR2)
begin
if (VAR3)
VAR1 <= VAR5 VAR6;
end
endmodule | mit |
phisiart/tvm | verilog/tvm_vpi_mem_interface.v | 1,735 | module MODULE1
parameter VAR11 = 8,
parameter VAR8 = 8,
parameter VAR2 = 32,
parameter VAR5 = 32
)
(
input clk,
input rst,
input VAR16, output [VAR11-1:0] VAR3, output VAR14, input VAR1, input [VAR8-1:0] VAR18, output VAR13, input VAR12, input [VAR2-1:0] VAR19, input [VAR5-1:0] VAR4, input VAR6, input [VAR2-1:0] VAR17,... | apache-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_sprs.v | 16,814 | module MODULE1(
clk, rst,
VAR86, VAR1, flag, VAR85, VAR53, VAR61,
VAR14, VAR46, VAR19, VAR7, VAR27,
VAR11, VAR9, VAR24, VAR56,
VAR65, VAR72, VAR29, VAR10, VAR20, VAR50, VAR76, VAR71,
VAR73, VAR44, VAR33, VAR26, VAR45,
VAR59, VAR67, VAR21,
VAR57, VAR4, VAR15,
VAR38, VAR13, VAR5, VAR55,
VAR75, VAR54, VAR52,
VAR80, VAR23
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2bb2a/sky130_fd_sc_lp__o2bb2a.functional.pp.v | 2,171 | module MODULE1 (
VAR8 ,
VAR6,
VAR5,
VAR19 ,
VAR18 ,
VAR16,
VAR17,
VAR3 ,
VAR14
);
output VAR8 ;
input VAR6;
input VAR5;
input VAR19 ;
input VAR18 ;
input VAR16;
input VAR17;
input VAR3 ;
input VAR14 ;
wire VAR13 ;
wire VAR12 ;
wire VAR2 ;
wire VAR4;
nand VAR11 (VAR13 , VAR5, VAR6 );
or VAR9 (VAR12 , VAR18, VAR19 );
and... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/cores/axi_cfg_register_v1_0/src/axi_cfg_register.v | 5,253 | module MODULE1 #
(
parameter integer VAR56 = 1024,
parameter integer VAR43 = 32,
parameter integer VAR21 = 32,
parameter integer VAR42 = 0
)
(
input wire VAR5,
input wire VAR23,
output wire [VAR56-1:0] VAR38,
input wire [VAR21-1:0] VAR47, input wire VAR9, output wire VAR15, input wire [VAR43-1:0] VAR22, input wire [VAR... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_link/bsg_link_osdr_phy_phase_align.v | 2,357 | module MODULE1
(input VAR11
,input VAR1
,output VAR13
);
logic VAR5, VAR9;
VAR15 #(.VAR3(1)) VAR14
(.VAR16(VAR5),.VAR8(VAR9),. VAR2(VAR13));
VAR12 #(.VAR3(1),.VAR6(0)) VAR7
(.VAR11(VAR11),.VAR1(VAR1),.VAR10(~VAR5),.VAR17(VAR5));
VAR12 #(.VAR3(1),.VAR6(0)) VAR4
(.VAR11(~VAR11),.VAR1(VAR1),.VAR10(~VAR9),.VAR17(VAR9));
be... | bsd-3-clause |
civol/HDLRuby | lib/HDLRuby/v_samples/rom.v | 7,682 | module MODULE1(en,VAR2,addr,VAR1);
input[7:0] addr;
output reg [7:0] VAR1;
always @ (*)
begin
case(addr)
0: VAR1 <= 0;
1: VAR1 <= 1;
2: VAR1 <= 2;
3: VAR1 <= 3;
4: VAR1 <= 4;
5: VAR1 <= 5;
6: VAR1 <= 6;
7: VAR1 <= 7;
8: VAR1 <= 8;
9: VAR1 <= 9;
10: VAR1 <= 10;
11: VAR1 <= 11;
12: VAR1 <= 12;
13: VAR1 <= 13;
14: VAR1 <=... | mit |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/soc_system_system_pll.v | 2,149 | module MODULE1(
input wire VAR53,
input wire rst,
output wire VAR61,
output wire VAR65,
output wire VAR41
);
VAR18 #(
.VAR63("false"),
.VAR55("50.0 VAR45"),
.VAR36("VAR22"),
.VAR46(2),
.VAR23("125.000000 VAR45"),
.VAR56("0 VAR30"),
.VAR17(50),
.VAR57("25.000000 VAR45"),
.VAR3("0 VAR30"),
.VAR44(50),
.VAR26("0 VAR45"),
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_4.v | 2,477 | module MODULE2 (
VAR2 ,
VAR10,
VAR1,
VAR5 ,
VAR6 ,
VAR3,
VAR8,
VAR11 ,
VAR7
);
output VAR2 ;
input VAR10;
input VAR1;
input VAR5 ;
input VAR6 ;
input VAR3;
input VAR8;
input VAR11 ;
input VAR7 ;
VAR4 VAR9 (
.VAR2(VAR2),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR7... | apache-2.0 |
alexforencich/verilog-ethernet | example/NetFPGA_SUME/fpga/rtl/fpga.v | 19,231 | module MODULE1 (
input wire VAR61,
input wire VAR281,
input wire [1:0] VAR212,
output wire [1:0] VAR127,
output wire [1:0] VAR31,
output wire [1:0] VAR232,
output wire [1:0] VAR308,
output wire [1:0] VAR220,
inout wire VAR244,
inout wire VAR132,
output wire VAR224,
input wire VAR315,
input wire VAR25,
output wire VAR93... | mit |
google/skywater-pdk-libs-sky130_fd_io | cells/top_ground_hvc_wpad/sky130_fd_io__top_ground_hvc_wpad.symbol.v | 1,640 | module MODULE1 (
inout VAR1 ,
inout VAR7,
inout VAR2
);
supply1 VAR12 ;
supply1 VAR8 ;
supply0 VAR13;
supply0 VAR6 ;
supply1 VAR5 ;
supply1 VAR14 ;
supply1 VAR15 ;
supply1 VAR3 ;
supply1 VAR16 ;
supply1 VAR9 ;
supply0 VAR17 ;
supply0 VAR4 ;
supply0 VAR11 ;
supply0 VAR10 ;
endmodule | apache-2.0 |
AmeerAbdelhadi/Dynamic-Frequency-Phase-Sweeping | pll_cfg.v | 66,382 | module MODULE1
(
VAR222,
VAR31,
VAR37,
VAR211,
VAR72,
VAR136,
VAR160,
VAR162,
VAR77,
VAR26,
VAR111,
VAR81,
VAR216,
VAR33,
VAR25,
VAR79,
reset,
VAR89) ;
output VAR222;
input VAR31;
input [2:0] VAR37;
input [3:0] VAR211;
input [8:0] VAR72;
output [8:0] VAR136;
output VAR160;
input VAR162;
output VAR77;
output VAR26;
outp... | bsd-3-clause |
chipsalliance/Cores-SweRV-EL2 | design/dmi/dmi_wrapper.v | 4,005 | module MODULE1(
input VAR1, input VAR15, input VAR10, input VAR17, output VAR7, output VAR9,
input VAR5, input VAR18, input [31:1] VAR12, input [31:0] VAR11, output [31:0] VAR26, output [6:0] VAR13, output VAR16, output VAR27, output VAR19
);
wire VAR25;
wire VAR22;
wire VAR20;
VAR30 VAR29(
.VAR3(VAR1), .VAR15(VAR15), ... | apache-2.0 |
chiragsakhuja/gpu | frag_block_bb.v | 8,637 | module MODULE1 (
VAR8,
VAR4,
VAR6,
VAR5,
VAR7,
VAR9,
VAR1,
VAR3,
VAR2);
input [5:0] VAR8;
input [5:0] VAR4;
input VAR6;
input [15:0] VAR5;
input [15:0] VAR7;
input VAR9;
input VAR1;
output [15:0] VAR3;
output [15:0] VAR2;
tri1 VAR6;
tri0 VAR9;
tri0 VAR1;
endmodule | gpl-2.0 |
lvd2/zxevo | fpga/current/z80/zports.v | 23,331 | module MODULE1(
input wire VAR54, input wire VAR17, input wire VAR145,
input wire VAR132,
input wire VAR72,
input wire [ 7:0] din,
output reg [ 7:0] dout,
output wire VAR8,
input wire [15:0] VAR45,
input wire VAR161,
input wire VAR16,
input wire VAR136,
input wire VAR82,
input wire VAR66,
output reg VAR119, output reg ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/inv/sky130_fd_sc_hs__inv.functional.v | 1,637 | module MODULE1 (
VAR7,
VAR6,
VAR8 ,
VAR9
);
input VAR7;
input VAR6;
output VAR8 ;
input VAR9 ;
wire VAR1 ;
wire VAR2;
not VAR5 (VAR1 , VAR9 );
VAR3 VAR4 (VAR2, VAR1, VAR7, VAR6);
buf VAR10 (VAR8 , VAR2 );
endmodule | apache-2.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/sort_cell.v | 2,056 | module MODULE1 #(
parameter VAR3=32,
parameter VAR7=8,
parameter VAR14=0,
parameter VAR25=32
) (
input clk,
input reset,
input [VAR3-1:0] VAR17,
output [VAR3-1:0] VAR8,
input [VAR3-1:0] VAR11,
input VAR1,
input VAR23,
input VAR2,
input VAR4,
output VAR24
);
reg [VAR3-1:0] VAR22;
reg [VAR3-1:0] VAR21;
assign VAR8 = VAR2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fahcin/sky130_fd_sc_lp__fahcin.functional.v | 1,752 | module MODULE1 (
VAR15,
VAR8 ,
VAR17 ,
VAR12 ,
VAR10
);
output VAR15;
output VAR8 ;
input VAR17 ;
input VAR12 ;
input VAR10 ;
wire VAR16 ;
wire VAR6;
wire VAR5 ;
wire VAR9 ;
wire VAR7 ;
wire VAR1;
not VAR2 (VAR16 , VAR10 );
xor VAR4 (VAR6, VAR17, VAR12, VAR16 );
buf VAR19 (VAR8 , VAR6 );
and VAR11 (VAR5 , VAR17, VAR12 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl.behavioral.pp.v | 1,992 | module MODULE1 (
VAR8 ,
VAR10 ,
VAR2 ,
VAR7 ,
VAR1,
VAR12 ,
VAR4
);
output VAR8 ;
input VAR10 ;
input VAR2 ;
input VAR7 ;
input VAR1;
input VAR12 ;
input VAR4 ;
wire VAR9;
wire VAR11 ;
VAR13 VAR3 (VAR9, VAR10, VAR2, VAR7 );
buf VAR5 (VAR11 , VAR9 );
VAR13 VAR6 (VAR8 , VAR11, VAR1, VAR7);
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9467/axi_ad9467_if.v | 6,771 | module MODULE1 (
VAR8,
VAR9,
VAR27,
VAR28,
VAR42,
VAR30,
VAR44,
VAR31,
VAR25,
VAR40,
VAR34,
VAR43,
VAR32,
VAR35,
VAR14,
VAR48,
VAR15);
parameter VAR21 = 0;
parameter VAR4 = "VAR16";
input VAR8;
input VAR9;
input [ 7:0] VAR27;
input [ 7:0] VAR28;
input VAR42;
input VAR30;
output VAR44;
output [15:0] VAR31;
output VAR25;... | gpl-3.0 |
alexforencich/xfcp | lib/uart/example/Arty/fpga/rtl/fpga_core.v | 3,918 | module MODULE1 #
(
parameter VAR6 = "VAR28"
)
(
input wire clk,
input wire rst,
input wire [3:0] VAR26,
input wire [3:0] VAR12,
output wire VAR24,
output wire VAR39,
output wire VAR41,
output wire VAR42,
output wire VAR7,
output wire VAR15,
output wire VAR5,
output wire VAR19,
output wire VAR16,
output wire VAR9,
outpu... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/einvp/sky130_fd_sc_hd__einvp.functional.pp.v | 1,863 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR7 ,
VAR13,
VAR5,
VAR12 ,
VAR9
);
output VAR1 ;
input VAR4 ;
input VAR7 ;
input VAR13;
input VAR5;
input VAR12 ;
input VAR9 ;
wire VAR6 ;
wire VAR8;
VAR10 VAR3 (VAR6 , VAR4, VAR13, VAR5 );
VAR10 VAR11 (VAR8, VAR7, VAR13, VAR5 );
notif1 VAR2 (VAR1 , VAR6, VAR8);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o22a/sky130_fd_sc_lp__o22a_m.v | 2,336 | module MODULE2 (
VAR9 ,
VAR10 ,
VAR7 ,
VAR8 ,
VAR2 ,
VAR1,
VAR5,
VAR4 ,
VAR11
);
output VAR9 ;
input VAR10 ;
input VAR7 ;
input VAR8 ;
input VAR2 ;
input VAR1;
input VAR5;
input VAR4 ;
input VAR11 ;
VAR6 VAR3 (
.VAR9(VAR9),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR4(VAR4),
.VA... | apache-2.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_babasu/spw_babasu/synthesis/spw_babasu.v | 56,451 | module MODULE1 (
output wire VAR77, input wire VAR286, input wire [2:0] VAR348, output wire [8:0] VAR302, input wire [8:0] VAR296, input wire [10:0] VAR120, output wire VAR347, output wire VAR318, output wire VAR259, output wire VAR133, output wire VAR197, input wire VAR321, input wire VAR314, output wire VAR209, outpu... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4b/sky130_fd_sc_lp__or4b.behavioral.pp.v | 1,978 | module MODULE1 (
VAR12 ,
VAR13 ,
VAR3 ,
VAR14 ,
VAR6 ,
VAR10,
VAR8,
VAR16 ,
VAR5
);
output VAR12 ;
input VAR13 ;
input VAR3 ;
input VAR14 ;
input VAR6 ;
input VAR10;
input VAR8;
input VAR16 ;
input VAR5 ;
wire VAR17 ;
wire VAR7 ;
wire VAR4;
not VAR9 (VAR17 , VAR6 );
or VAR11 (VAR7 , VAR17, VAR14, VAR3, VAR13 );
VAR1 VA... | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_043.v | 1,602 | module MODULE1 (
VAR16,
VAR9
);
input [31:0] VAR16;
output [31:0]
VAR9;
wire [31:0]
VAR1,
VAR3,
VAR8,
VAR5,
VAR2,
VAR13,
VAR4,
VAR12,
VAR7,
VAR15,
VAR11;
assign VAR1 = VAR16;
assign VAR13 = VAR1 << 7;
assign VAR4 = VAR1 + VAR13;
assign VAR11 = VAR15 - VAR7;
assign VAR15 = VAR7 << 2;
assign VAR12 = VAR4 << 2;
assign VAR... | mit |
asicguy/gplgpu | hdl/vga/htaddmap.v | 30,941 | module MODULE1
(
input VAR117,
input VAR1,
input VAR101,
input VAR56,
input VAR172,
input VAR67,
input [31:0] VAR93,
input VAR14,
input VAR175,
input VAR9,
input VAR25,
input VAR85,
input [3:0] VAR7,
input VAR180,
input VAR168,
input VAR103,
input VAR55,
input VAR13,
input VAR87,
input VAR65,
input VAR28,
input VAR185,... | gpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/db/db_clip3_str.v | 1,271 | module MODULE1(VAR3,VAR1,VAR4,VAR2);
input [7:0] VAR1,VAR4;
input [8:0] VAR2 ;
output wire [7:0] VAR3;
assign VAR3 = (VAR2<VAR1) ? VAR1 : ((VAR2>VAR4) ? VAR4 : VAR2[7:0]);
endmodule | gpl-3.0 |
CMU-SAFARI/NOCulator | hring/hw/bless/brouter_3x3.v | 10,177 | module MODULE1(
input VAR54 VAR64,
input VAR54 VAR131,
input VAR54 VAR79,
input VAR54 VAR101,
input VAR54 VAR94,
input VAR54 VAR2,
input VAR54 VAR33,
input VAR54 VAR36,
input VAR54 VAR142,
input VAR51 VAR70,
input VAR51 VAR114,
input VAR51 VAR17,
input VAR51 VAR116,
input VAR51 VAR91,
input VAR51 VAR48,
input VAR51 VAR... | mit |
bigeagle/riffa | fpga/riffa_hdl/tx_hdr_fifo.v | 7,726 | module MODULE1(
parameter VAR41 = 128,
parameter VAR32 = 1,
parameter VAR57 = 1,
parameter VAR44 = "VAR42"
)
(
input VAR38,
input VAR9,
input VAR27,
input [(VAR41)-1:0] VAR49,
input [VAR17-1:0] VAR1,
input [VAR43-1:0] VAR54,
input [VAR2-1:0] VAR40,
input VAR58,
output VAR25,
output VAR39,
output [(VAR41)-1:0] VAR18,
ou... | bsd-3-clause |
ShepardSiegel/ocpi | coregen/ddr3_s4_amphy/alt_mem_ddrx_csr.v | 51,661 | module MODULE1 #
( parameter
VAR64 = 2,
VAR104 = 1,
VAR37 = 1,
VAR160 = 0,
VAR39 = 0,
VAR11 = 8,
VAR3 = 32,
VAR191 = 1,
VAR50 = 72,
VAR126 = 1, VAR115 = 13, VAR89 = 10, VAR132 = 3,
VAR42 = 1,
VAR13 = 1,
VAR157 = 0,
VAR92 = 4, VAR165 = 3, VAR78 = 4, VAR189 = 5, VAR159 = 4, VAR59 = 6, VAR170 = 8, VAR9 = 13, VAR107 = 4, V... | lgpl-3.0 |
mcoughli/root_of_trust | operational_os/hls/contact_discovery_hls_2017.1/solution1/syn/verilog/contact_discovery.v | 35,709 | module MODULE1 (
VAR139,
VAR26,
VAR129,
VAR131,
VAR161,
VAR98,
VAR49,
VAR36,
VAR53,
VAR27,
VAR134,
VAR72,
VAR96,
VAR110,
VAR145,
VAR13,
VAR105,
VAR113,
VAR89,
VAR41,
VAR7,
VAR62,
VAR45,
VAR86,
VAR8,
VAR55,
VAR17,
VAR31,
interrupt
);
parameter VAR85 = 15'd1;
parameter VAR1 = 15'd2;
parameter VAR83 = 15'd4;
parameter VAR... | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature_KOA/ecp/counter.v | 1,398 | module MODULE1 (clk, VAR2, VAR4);
input wire clk;
input wire VAR2;
output wire VAR4;
reg [7:0] VAR3;
assign VAR4 = |VAR3;
always @(posedge clk or negedge VAR2) begin
if(VAR2 == 1'b0)
VAR3 <= 8'VAR1;
end
else
VAR3 <= VAR3 - 1'b1;
end
endmodule | gpl-3.0 |
peteasa/parallella-fpga | AdiHDLLib/library/prcfg/qpsk/prcfg_dac.v | 5,280 | module MODULE1(
clk,
VAR3,
VAR14,
VAR9,
VAR12,
VAR1,
VAR7,
VAR19,
VAR11
);
parameter VAR20 = 0;
parameter VAR23 = 16;
localparam VAR22 = 2;
localparam VAR6 = 8'hA2;
input clk;
input [31:0] VAR3;
output [31:0] VAR14;
output VAR9;
input [(VAR23-1):0] VAR12;
output VAR1;
input VAR7;
output [(VAR23-1):0] VAR19;
input VAR11... | lgpl-3.0 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_AsyncResetRegVec_1.v | 3,507 | module MODULE1(
input VAR23,
input reset,
input [4:0] VAR25,
output [4:0] VAR37,
input VAR28
);
wire VAR30;
wire VAR40;
wire VAR33;
wire VAR20;
wire VAR26;
wire VAR14;
wire VAR7;
wire VAR17;
wire VAR3;
wire VAR2;
wire VAR5;
wire VAR39;
wire VAR36;
wire VAR34;
wire VAR46;
wire VAR13;
wire VAR31;
wire VAR18;
wire VAR19;
... | apache-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_iwb_biu.v | 18,193 | module MODULE1(
clk, rst, VAR36,
VAR14, VAR26, VAR31, VAR32, VAR10, VAR48,
VAR40, VAR24, VAR9, VAR3, VAR13, VAR22,
VAR29, VAR46, VAR15, VAR39, VAR44, VAR30, VAR12,
VAR2, VAR16, VAR47
);
parameter VAR6 = VAR37;
parameter VAR42 = VAR37;
input clk; input rst; input [1:0] VAR36;
input VAR14; input VAR26; input VAR31; input... | gpl-2.0 |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/AllignAdder.v | 2,124 | module MODULE1(
input VAR10,
input [35:0] VAR16,
input [35:0] VAR15,
input [31:0] VAR4,
input [7:0] VAR14,
input VAR9,
output reg VAR5,
output reg [35:0] VAR12,
output reg [35:0] VAR11,
output reg [31:0] VAR8
);
parameter VAR6 = 1'b01,
VAR18 = 1'b1;
wire VAR2;
wire [7:0] VAR1;
wire [26:0] VAR3;
wire VAR13;
wire [7:0] V... | apache-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_mm_bridge_0/synth/ghrd_10as066n2_mm_bridge_0.v | 4,523 | module MODULE1 #(
parameter VAR18 = 512,
parameter VAR14 = 8,
parameter VAR24 = 32,
parameter VAR15 = 5,
parameter VAR12 = 1,
parameter VAR16 = 1
) (
input wire clk, input wire VAR30, input wire [VAR18-1:0] VAR5, input wire VAR21, output wire [VAR15-1:0] VAR29, output wire [VAR18-1:0] VAR10, output wire [VAR24-1:0] VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputiso1p/sky130_fd_sc_hd__lpflow_inputiso1p.behavioral.pp.v | 1,769 | module MODULE1 (
VAR7 ,
VAR1 ,
VAR6,
VAR9 ,
VAR3 ,
VAR8 ,
VAR11
);
output VAR7 ;
input VAR1 ;
input VAR6;
input VAR9 ;
input VAR3 ;
input VAR8 ;
input VAR11 ;
wire VAR2;
or VAR5 (VAR2, VAR1, VAR6 );
VAR4 VAR10 (VAR7 , VAR2, VAR9, VAR3);
endmodule | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/hpdmc_ddr32/rtl/hpdmc_mgmt.v | 8,890 | module MODULE1 #(
parameter VAR2 = 26,
parameter VAR27 = 9
) (
input VAR34,
input VAR19,
input [2:0] VAR36,
input [2:0] VAR41,
input [10:0] VAR23,
input [3:0] VAR50,
input VAR33,
input VAR17,
input [VAR2-3-1:0] address,
output reg ack,
output reg read,
output reg write,
output [3:0] VAR24,
input VAR38,
input VAR31,
inp... | lgpl-3.0 |
gralco/click-clock-board | mojo_io_shield/work/verilog/elevator_1.v | 3,398 | module MODULE1 (
clk,
VAR6,
rst,
en,
VAR4,
VAR8,
VAR7,
VAR9
);
input clk;
input VAR6;
input rst;
input en;
output [7:0] VAR4;
reg [7:0] VAR4;
output [17:0] VAR8;
reg [17:0] VAR8;
output [7:0] VAR7;
wire [7:0] VAR7;
output [3:0] VAR9; wire [3:0] VAR9;
reg [3:0] VAR3 [0:6-1];
reg [1:0] VAR2, VAR1;
assign VAR7[0] = (((VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or4/sky130_fd_sc_hs__or4.blackbox.v | 1,233 | module MODULE1 (
VAR6,
VAR2,
VAR5,
VAR4,
VAR1
);
output VAR6;
input VAR2;
input VAR5;
input VAR4;
input VAR1;
supply1 VAR3;
supply0 VAR7;
endmodule | apache-2.0 |
amiq-consulting/amiq_blog | amiq_e_c_python_how_to_connect_e_with_python/amiq_mux2_1.v | 1,156 | module MODULE1(input clk, input sel, input VAR2, input VAR1, output reg out);
VAR3 out=0;
always@(posedge clk) begin
out<=sel?VAR1:VAR2;
end
endmodule | apache-2.0 |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/Cache/L1/Dirty_Ram.v | 1,259 | module MODULE1(
input VAR3,
input VAR7,
input [3:0] VAR12,
input VAR6,
input VAR2,
output VAR14,
input [7:0] VAR4,
output reg VAR8
);
VAR9 #(4,1,16) VAR13(
.VAR3 (VAR3),
.VAR10 ((VAR8) ? 1'b1 : VAR2),
.VAR11 ((VAR8) ? VAR4[3:0] : VAR12),
.VAR5 ((VAR8) ? 1'b0 : VAR6),
.VAR1 (VAR14)
);
always @ (posedge VAR3) begin
if (V... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or4b/sky130_fd_sc_ms__or4b.functional.pp.v | 1,978 | module MODULE1 (
VAR3 ,
VAR14 ,
VAR10 ,
VAR5 ,
VAR15 ,
VAR2,
VAR13,
VAR12 ,
VAR7
);
output VAR3 ;
input VAR14 ;
input VAR10 ;
input VAR5 ;
input VAR15 ;
input VAR2;
input VAR13;
input VAR12 ;
input VAR7 ;
wire VAR6 ;
wire VAR4 ;
wire VAR1;
not VAR17 (VAR6 , VAR15 );
or VAR9 (VAR4 , VAR6, VAR5, VAR10, VAR14 );
VAR11 VAR... | apache-2.0 |
merckhung/zet | cores/vga/rtl/vga_text_mode.v | 5,086 | module MODULE1 (
input clk,
input rst,
output reg [16:1] VAR41,
input [15:0] VAR33,
output VAR39,
input [9:0] VAR30,
input [9:0] VAR7,
input VAR1,
input VAR19,
output VAR31,
input [5:0] VAR9,
input [5:0] VAR22,
input [4:0] VAR2,
input [6:0] VAR3,
output reg [3:0] VAR28,
output VAR5
);
reg [ 6:0] VAR6;
reg [ 4:0] VAR38;... | gpl-3.0 |
kevintownsend/inara-hdl-libraries | scratch_pad_a/scratch_pad.v | 14,987 | module MODULE1(rst, clk, VAR8, VAR20, VAR51, VAR16, addr, VAR38, valid, VAR17);
parameter VAR54 = 8;
parameter VAR14 = 64;
parameter VAR2 = 512;
parameter VAR37 = 32;
parameter VAR11 = 32;
parameter VAR4 = VAR49(VAR37-1) + 1;
parameter VAR12 = VAR2 * VAR54;
parameter VAR18 = VAR49(VAR12-1);
parameter VAR32 = VAR49(VAR5... | apache-2.0 |
James534/Tempest | fpga/fpga_hw/top_level/DE0_Nano_SOPC/synthesis/submodules/DE0_Nano_SOPC_sdram.v | 23,219 | module MODULE1 (
clk,
rd,
VAR44,
wr,
VAR36,
VAR68,
VAR45,
VAR31,
VAR5,
VAR57
)
;
output VAR68;
output VAR45;
output VAR31;
output VAR5;
output [ 42: 0] VAR57;
input clk;
input rd;
input VAR44;
input wr;
input [ 42: 0] VAR36;
wire VAR68;
wire VAR45;
wire VAR31;
reg [ 1: 0] VAR32;
reg [ 42: 0] VAR28;
reg [ 42: 0] VAR59;
... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_4.functional.v | 1,585 | module MODULE1( VAR8, VAR1, VAR7, VAR16, VAR13 );
input VAR7, VAR1, VAR16, VAR13;
output VAR8;
wire VAR10;
not VAR12( VAR10, VAR7 );
wire VAR9;
not VAR18( VAR9, VAR16 );
wire VAR11;
not VAR3( VAR11, VAR13 );
wire VAR6;
and VAR5( VAR6, VAR10, VAR9, VAR11 );
wire VAR14;
not VAR15( VAR14, VAR1 );
wire VAR17;
and VAR4( VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o221a/sky130_fd_sc_hs__o221a.pp.blackbox.v | 1,375 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR3 ,
VAR6 ,
VAR8 ,
VAR5 ,
VAR7,
VAR2
);
output VAR4 ;
input VAR1 ;
input VAR3 ;
input VAR6 ;
input VAR8 ;
input VAR5 ;
input VAR7;
input VAR2;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or4bb/sky130_fd_sc_hdll__or4bb.behavioral.pp.v | 2,008 | module MODULE1 (
VAR7 ,
VAR2 ,
VAR5 ,
VAR12 ,
VAR8 ,
VAR16,
VAR17,
VAR1 ,
VAR15
);
output VAR7 ;
input VAR2 ;
input VAR5 ;
input VAR12 ;
input VAR8 ;
input VAR16;
input VAR17;
input VAR1 ;
input VAR15 ;
wire VAR3 ;
wire VAR4 ;
wire VAR14;
nand VAR10 (VAR3 , VAR8, VAR12 );
or VAR9 (VAR4 , VAR5, VAR2, VAR3 );
VAR13 VAR6 ... | apache-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/dbg_interface/dbg_registers.v | 11,103 | module MODULE1(VAR85, VAR5, VAR58, VAR90, VAR29, VAR55, VAR66, VAR52,
VAR77,
VAR62, VAR76, VAR72, VAR92,
VAR18, VAR47, VAR79, VAR21, VAR34, VAR31,
VAR64, VAR20, VAR60, VAR33,
VAR39, VAR73, VAR22, VAR11,
VAR36, VAR26, VAR82, VAR61,
VAR54, VAR50, VAR40, VAR12,
VAR7, VAR38, VAR28, VAR44, VAR75, VAR3, VAR8,
VAR63, VAR80,
V... | apache-2.0 |
sittner/lcnc-mdsio | vhdl/source/can/can_bsp.v | 62,946 | module MODULE1
(
clk,
rst,
VAR33,
VAR166,
VAR136,
VAR21,
VAR47,
addr,
VAR181,
VAR4,
VAR156,
VAR132,
VAR127,
VAR237,
VAR176,
VAR23,
VAR149,
VAR124,
VAR154,
VAR167,
VAR250,
VAR212,
VAR232,
VAR103,
VAR16,
VAR95,
VAR209,
VAR178,
VAR111,
VAR88,
VAR217,
VAR100,
VAR192,
VAR223,
VAR50,
VAR189,
VAR267,
VAR73,
VAR213,
VAR214,
VA... | gpl-3.0 |
alexforencich/verilog-ethernet | rtl/arp_eth_rx.v | 11,582 | module MODULE1 #
(
parameter VAR22 = 8,
parameter VAR31 = (VAR22>8),
parameter VAR24 = (VAR22/8)
)
(
input wire clk,
input wire rst,
input wire VAR13,
output wire VAR17,
input wire [47:0] VAR34,
input wire [47:0] VAR9,
input wire [15:0] VAR5,
input wire [VAR22-1:0] VAR30,
input wire [VAR24-1:0] VAR19,
input wire VAR16,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfxtp/sky130_fd_sc_hd__dfxtp.functional.pp.v | 1,644 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR11 ,
VAR7,
VAR1,
VAR9 ,
VAR10
);
output VAR2 ;
input VAR5 ;
input VAR11 ;
input VAR7;
input VAR1;
input VAR9 ;
input VAR10 ;
wire VAR6;
VAR3 VAR12 VAR8 (VAR6 , VAR11, VAR5, , VAR7, VAR1);
buf VAR4 (VAR2 , VAR6 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_1.behavioral.pp.v | 2,914 | module MODULE1( VAR15, VAR18, VAR9, VAR17, VAR1, VAR27 );
input VAR18, VAR15, VAR9;
inout VAR1, VAR27;
output VAR17;
reg VAR20;
VAR8 VAR3(.VAR15(VAR15),.VAR18(VAR18),.VAR9(VAR9),.VAR17(VAR17),.VAR1(VAR1),.VAR27(VAR27),.VAR20(VAR20));
VAR8 VAR16(.VAR15(VAR15),.VAR18(VAR18),.VAR9(VAR9),.VAR17(VAR17),.VAR1(VAR1),.VAR27(VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a211o/sky130_fd_sc_hd__a211o_4.v | 2,348 | module MODULE1 (
VAR10 ,
VAR1 ,
VAR5 ,
VAR2 ,
VAR6 ,
VAR3,
VAR4,
VAR7 ,
VAR11
);
output VAR10 ;
input VAR1 ;
input VAR5 ;
input VAR2 ;
input VAR6 ;
input VAR3;
input VAR4;
input VAR7 ;
input VAR11 ;
VAR9 VAR8 (
.VAR10(VAR10),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR7(VAR7),
.VA... | apache-2.0 |
hoangt/NOCulator | hring/hw/buffered/src/vcr_ip_ctrl_mac.v | 45,233 | module MODULE1
(clk, reset, VAR224, VAR214, VAR165, VAR74,
VAR161, VAR116, VAR244, VAR177, VAR49,
VAR10, VAR71, VAR110, VAR251,
VAR264, VAR171, VAR107, VAR120,
VAR64, VAR266, VAR231);
parameter VAR235 = 8;
localparam VAR227 = VAR12(VAR235);
parameter VAR113 = 4;
parameter VAR50 = 2;
parameter VAR95 = 2;
localparam VAR1... | mit |
ShepardSiegel/ocpi | coregen/dram_v6_mig39_2/mig_39_2/example_design/rtl/ui/ui_rd_data.v | 18,402 | module MODULE1 #
(
parameter VAR65 = 100,
parameter VAR69 = 256,
parameter VAR87 = "VAR54",
parameter VAR35 = "VAR68"
)
(
VAR83, VAR60, VAR70, VAR40,
VAR7, VAR48, VAR89, VAR91,
rst, clk, VAR66, VAR75, VAR10, VAR30,
VAR3, VAR28, VAR73
);
input rst;
input clk;
output wire VAR83;
output wire [3:0] VAR60;
reg [5:0] VAR6;
r... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor4/sky130_fd_sc_ls__nor4_2.v | 2,275 | module MODULE1 (
VAR7 ,
VAR5 ,
VAR2 ,
VAR10 ,
VAR6 ,
VAR1,
VAR9,
VAR4 ,
VAR8
);
output VAR7 ;
input VAR5 ;
input VAR2 ;
input VAR10 ;
input VAR6 ;
input VAR1;
input VAR9;
input VAR4 ;
input VAR8 ;
VAR11 VAR3 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xor2/sky130_fd_sc_hdll__xor2.blackbox.v | 1,272 | module MODULE1 (
VAR3,
VAR1,
VAR4
);
output VAR3;
input VAR1;
input VAR4;
supply1 VAR7;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
finnball/igloo | infra/hdl/ram.v | 6,044 | module MODULE4(
input clk,
input VAR3,
input [VAR31 - 1 : 0] VAR9,
input [VAR28 - 1 : 0] VAR33,
input VAR20,
input [VAR31 - 1 : 0] VAR18,
output [VAR28 - 1 : 0] VAR29
);
parameter VAR31 = 8;
parameter VAR28 = 16;
localparam VAR24 = 1 << VAR31;
reg [VAR28 - 1 : 0] VAR6 [VAR24 - 1 : 0];
reg [VAR28 - 1 : 0] VAR29 = 0;
ass... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and4b/sky130_fd_sc_hdll__and4b.pp.blackbox.v | 1,349 | module MODULE1 (
VAR8 ,
VAR4 ,
VAR1 ,
VAR2 ,
VAR3 ,
VAR9,
VAR6,
VAR5 ,
VAR7
);
output VAR8 ;
input VAR4 ;
input VAR1 ;
input VAR2 ;
input VAR3 ;
input VAR9;
input VAR6;
input VAR5 ;
input VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a31oi/sky130_fd_sc_hd__a31oi_2.v | 2,350 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR7 ,
VAR11 ,
VAR5 ,
VAR2,
VAR9,
VAR10 ,
VAR6
);
output VAR1 ;
input VAR3 ;
input VAR7 ;
input VAR11 ;
input VAR5 ;
input VAR2;
input VAR9;
input VAR10 ;
input VAR6 ;
VAR8 VAR4 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR10(VAR10),
.... | apache-2.0 |
ineganov/bare_system | hard/system.v | 6,415 | module MODULE1 ( input VAR81,
output VAR19,
output VAR85,
output VAR40,
input VAR44,
input [1:0] VAR42,
input [3:0] VAR43,
output [7:0] VAR67 );
wire VAR56, VAR58, VAR61, VAR18, VAR74, VAR87;
wire [31:0] VAR9, VAR52, VAR10, VAR1, VAR36,
VAR31, VAR70;
wire [29:0] VAR2, VAR84, VAR83, VAR14;
wire [3:0] VAR28, VAR29;
wire ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfrtp/sky130_fd_sc_lp__dfrtp.blackbox.v | 1,337 | module MODULE1 (
VAR8 ,
VAR6 ,
VAR5 ,
VAR3
);
output VAR8 ;
input VAR6 ;
input VAR5 ;
input VAR3;
supply1 VAR1;
supply0 VAR4;
supply1 VAR7 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
tmolteno/TART | hardware/FPGA/tart_spi/verilog/capture/fake_telescope.v | 5,010 | module MODULE1
parameter VAR13 = VAR3-1,
parameter VAR20 = 1, parameter VAR19 = 1, parameter VAR17 = 0, parameter VAR21 = 0, parameter VAR9 = 0,
parameter VAR15 = 3)
(
input VAR12, input VAR7,
input VAR10,
input VAR1, input VAR4,
output VAR14,
output [VAR13:0] VAR11
);
wire [31:0] VAR6;
reg [31:0] VAR26 = 32'h1;
reg [V... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21oi/sky130_fd_sc_hdll__a21oi.functional.v | 1,428 | module MODULE1 (
VAR1 ,
VAR7,
VAR5,
VAR9
);
output VAR1 ;
input VAR7;
input VAR5;
input VAR9;
wire VAR8 ;
wire VAR2;
and VAR4 (VAR8 , VAR7, VAR5 );
nor VAR6 (VAR2, VAR9, VAR8 );
buf VAR3 (VAR1 , VAR2 );
endmodule | apache-2.0 |
parallella/oh | spi/hdl/parallella_spi.v | 7,958 | module MODULE1(
VAR3, VAR56, VAR26, VAR17, VAR50,
VAR41, VAR36, VAR31, VAR64, VAR32,
VAR19, VAR67, VAR44, VAR33, VAR6,
VAR48,
VAR34, VAR21,
VAR43, VAR12, VAR9, VAR10, VAR52,
VAR22, VAR63, VAR61, VAR60,
VAR40, VAR11, VAR7, VAR8, VAR15,
VAR66, VAR47, VAR1, VAR69,
VAR42, VAR2, VAR55, VAR14, VAR30,
VAR38, VAR5, VAR39, VAR2... | mit |
fabianmcg/usbc_tcpc | src/Rx_Module.v | 5,306 | module MODULE1 (VAR16, reset, VAR15, VAR2, VAR23, VAR26, VAR19,
VAR29, VAR20, VAR5, VAR9, VAR12, VAR10,
VAR6, VAR14, VAR8, VAR28);
input wire VAR5, VAR9;
input wire VAR16;
input wire [7:0] VAR12;
input wire [15:0] VAR23; input wire [7:0] VAR19;
input wire [7:0] VAR26;
input wire [7:0] VAR2; input wire reset;
input wire... | mit |
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