repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a32o/sky130_fd_sc_lp__a32o_4.v | 2,469 | module MODULE2 (
VAR6 ,
VAR2 ,
VAR11 ,
VAR9 ,
VAR8 ,
VAR4 ,
VAR5,
VAR12,
VAR3 ,
VAR7
);
output VAR6 ;
input VAR2 ;
input VAR11 ;
input VAR9 ;
input VAR8 ;
input VAR4 ;
input VAR5;
input VAR12;
input VAR3 ;
input VAR7 ;
VAR10 VAR1 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR5(VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/maj3/sky130_fd_sc_ls__maj3.behavioral.v | 1,581 | module MODULE1 (
VAR1,
VAR6,
VAR5,
VAR13
);
output VAR1;
input VAR6;
input VAR5;
input VAR13;
supply1 VAR8;
supply0 VAR11;
supply1 VAR17 ;
supply0 VAR12 ;
wire VAR3 ;
wire VAR7 ;
wire VAR4 ;
wire VAR9;
or VAR10 (VAR3 , VAR5, VAR6 );
and VAR15 (VAR7 , VAR3, VAR13 );
and VAR16 (VAR4 , VAR6, VAR5 );
or VAR2 (VAR9, VAR4, V... | apache-2.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/median/ipi_proj/srcs/ip/xilinx_com_hls_image_filter_1_0/hdl/verilog/image_filter_AXIvideo2Mat.v | 29,950 | module MODULE1 (
VAR11,
VAR53,
VAR75,
VAR116,
VAR24,
VAR27,
VAR26,
VAR90,
VAR74,
VAR54,
VAR88,
VAR48,
VAR34,
VAR92,
VAR12,
VAR117,
VAR98,
VAR68,
VAR10,
VAR47,
VAR112,
VAR83,
VAR100,
VAR113,
VAR85,
VAR84,
VAR66
);
parameter VAR25 = 1'b1;
parameter VAR43 = 1'b0;
parameter VAR96 = 7'b1;
parameter VAR108 = 7'b10;
parameter... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/ipshared/xilinx.com/axi_crossbar_v2_1/da4c95fc/hdl/verilog/axi_crossbar_v2_1_addr_arbiter_sasd.v | 13,345 | module MODULE1 #
(
parameter VAR45 = "none",
parameter integer VAR9 = 1,
parameter integer VAR16 = 1,
parameter integer VAR37 = 1,
parameter VAR77 = 0,
parameter [VAR9*32-1:0] VAR41 = {VAR9{32'h00000000}}
)
(
input wire VAR2,
input wire VAR3,
input wire [VAR9*VAR37-1:0] VAR78,
input wire [VAR9*VAR37-1:0] VAR79,
input w... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfxtp/sky130_fd_sc_hs__sdfxtp.pp.symbol.v | 1,376 | module MODULE1 (
input VAR5 ,
output VAR3 ,
input VAR4 ,
input VAR6 ,
input VAR7 ,
input VAR1,
input VAR2
);
endmodule | apache-2.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/rtl/chip_top.v | 6,160 | module MODULE1 (
input wire VAR12,
input wire VAR9
,input wire VAR11
,output wire VAR7
,input wire [VAR2-1:0] VAR8
,output wire [VAR1-1:0] VAR6
,inout wire [VAR10-1:0] VAR4
);
wire clk ;
wire VAR14 ;
wire VAR13 ;
VAR5 VAR5 (
.VAR12 (VAR12 ),
.VAR9 (VAR9 ),
.clk (clk ),
.VAR14 (VAR14 ),
.VAR13 (VAR13 )
);
VAR3 VAR3 (
.c... | apache-2.0 |
anderson1008/PAB-NOC | RTL/loadTrack.v | 1,486 | module MODULE1 (reset, clk, valid, VAR7, VAR10, VAR15, VAR4, VAR6);
input clk, reset,VAR10;
input [3:0] valid;
input [3:0] VAR7;
input [4*VAR12-1:0] VAR15; output reg [VAR3-1:0] VAR4;
output reg [4*VAR11-1:0] VAR6;
wire [VAR12-1:0] VAR14 [3:0];
genvar VAR5;
generate
for (VAR5=0; VAR5<4; VAR5= VAR5+1) begin : VAR9
assig... | gpl-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/dbg_interface/dbg_sync_clk1_clk2.v | 4,979 | module MODULE1 (VAR4, VAR1, VAR2, VAR6, VAR14, VAR11);
parameter VAR10 = 1;
input VAR4;
input VAR1;
input VAR2;
input VAR6;
input VAR14;
output VAR11;
reg VAR13;
reg VAR7;
reg VAR5;
reg VAR8;
reg VAR3;
reg VAR9;
reg VAR11;
wire VAR12;
assign VAR12 = VAR14 | VAR13 & ~VAR9;
always @ (posedge VAR1 or posedge VAR6)
begin
i... | apache-2.0 |
ILoveSpeccy/Aeon-Lite | cores/korvet/src/cpu/k580wm80a.v | 11,211 | module MODULE1(
input clk,
input VAR26,
input reset,
input VAR37,
input [7:0] VAR5,
output reg [15:0] addr,
output reg sync,
output rd,
output reg wr,
output VAR17,
output reg [7:0] VAR83);
reg VAR13,VAR70,VAR21,VAR74,VAR43,VAR6,VAR31,VAR56,VAR78,VAR2,VAR64,VAR58,VAR76,VAR3,VAR45,VAR29,VAR55,VAR12;
reg[2:0] state;
wire... | gpl-3.0 |
alexforencich/verilog-ethernet | example/HXT100G/fpga/rtl/i2c_master.v | 29,804 | module MODULE1 (
input wire clk,
input wire rst,
input wire [6:0] VAR97,
input wire VAR51,
input wire VAR20,
input wire VAR38,
input wire VAR88,
input wire VAR98,
input wire VAR81,
output wire VAR113,
input wire [7:0] VAR28,
input wire VAR62,
output wire VAR33,
input wire VAR45,
output wire [7:0] VAR8,
output wire VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlxtn/sky130_fd_sc_hd__dlxtn_4.v | 2,204 | module MODULE2 (
VAR6 ,
VAR9 ,
VAR3,
VAR7 ,
VAR8 ,
VAR1 ,
VAR2
);
output VAR6 ;
input VAR9 ;
input VAR3;
input VAR7 ;
input VAR8 ;
input VAR1 ;
input VAR2 ;
VAR5 VAR4 (
.VAR6(VAR6),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR6 ,
VAR9 ,
VAR3
);
output VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_dff_nrs/sky130_fd_sc_ls__udp_dff_nrs.blackbox.v | 1,347 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR5,
VAR2,
VAR3
);
output VAR1 ;
input VAR4 ;
input VAR5;
input VAR2;
input VAR3 ;
endmodule | apache-2.0 |
fabianz66/cursos-tec | taller-digital/Lab4/lab_pong/FSM_Barra.v | 2,019 | module MODULE1(VAR4, reset, VAR3, VAR7,VAR6, VAR9);
input VAR4, reset, VAR3;
output VAR7;
output reg VAR6, VAR9;
reg [2:0] state;
parameter VAR8 = 0;
parameter VAR2 = 1;
parameter VAR1 = 2;
parameter VAR5 = 3;
begin
begin
begin
end
begin
begin
begin
begin | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/up_axi.v | 8,479 | module MODULE1 (
VAR21,
VAR7,
VAR18,
VAR35,
VAR34,
VAR23,
VAR27,
VAR6,
VAR36,
VAR5,
VAR8,
VAR3,
VAR12,
VAR14,
VAR22,
VAR32,
VAR25,
VAR24,
VAR17,
VAR19,
VAR30,
VAR13,
VAR26,
VAR20,
VAR31);
parameter VAR2 = 32'hffffffff;
parameter VAR10 = 32'h00000000;
input VAR21;
input VAR7;
input VAR18;
input [31:0] VAR35;
output VAR3... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_2.v | 2,262 | module MODULE2 (
VAR2,
VAR3 ,
VAR1,
VAR8 ,
VAR10,
VAR7,
VAR9 ,
VAR4
);
output VAR2;
input VAR3 ;
input VAR1;
input VAR8 ;
input VAR10;
input VAR7;
input VAR9 ;
input VAR4 ;
VAR6 VAR5 (
.VAR2(VAR2),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xnor3/sky130_fd_sc_ls__xnor3.blackbox.v | 1,269 | module MODULE1 (
VAR8,
VAR4,
VAR5,
VAR3
);
output VAR8;
input VAR4;
input VAR5;
input VAR3;
supply1 VAR7;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab02/lab02/Code/SSeg_map.v | 1,701 | module MODULE1(input[63:0]VAR2,
output[63:0]VAR1
);
assign VAR1 = {VAR2[0], VAR2[4], VAR2[16], VAR2[25], VAR2[17], VAR2[5], VAR2[12], VAR2[24],
VAR2[1], VAR2[6], VAR2[18], VAR2[27], VAR2[19], VAR2[7], VAR2[13], VAR2[26],
VAR2[2], VAR2[8], VAR2[20], VAR2[29], VAR2[21], VAR2[9], VAR2[14], VAR2[28],
VAR2[3], VAR2[10], VAR... | gpl-3.0 |
VectorBlox/PYNQ | Pynq-Z1/vivado/ip/pmod_io_switch_1.0/src/switch_bit.v | 3,787 | module MODULE1(
input wire [3:0] VAR18,
output wire [7:0] VAR8,
input wire [7:0] VAR15,
input wire [7:0] VAR31,
input wire VAR32,
output reg VAR13,
output reg VAR4,
output wire VAR27,
input wire VAR17,
input wire VAR1,
output wire VAR9,
input wire VAR28,
input wire VAR12,
output wire VAR19,
input wire VAR22,
input wire... | bsd-3-clause |
sam-falvo/remex | rtl/tx_DS_sel.v | 2,893 | module MODULE1(
input VAR3,
input VAR23,
input VAR26,
input VAR22,
input VAR11,
input VAR15,
input VAR4,
input [8:0] VAR10,
output VAR1,
output VAR19,
output VAR8,
output VAR6,
output VAR12,
output [8:0] VAR14
);
reg VAR24,
VAR17,
VAR9,
VAR13,
VAR18;
reg [5:0] VAR16;
reg VAR1, VAR19, VAR8, VAR6, VAR12;
wire VAR20 = |VA... | mpl-2.0 |
cpulabs/mist1032isa | src/dps/utim64/dps_utim64.v | 6,696 | module MODULE1(
input wire VAR10, input wire VAR19,
input wire VAR36,
input wire VAR6,
output wire VAR16,
input wire VAR35,
input wire [4:0] VAR38,
input wire [31:0] VAR17,
output wire VAR24,
output wire [31:0] VAR39,
output wire VAR7,
input wire VAR31
);
wire [3:0] VAR30;
wire [3:0] VAR29;
reg [1:0] VAR23;
reg [7:0] V... | bsd-2-clause |
takeshineshiro/fpga_linear_128 | BC_bb.v | 5,012 | module MODULE1 (
address,
VAR1,
VAR2);
input [0:0] address;
input VAR1;
output [15:0] VAR2;
endmodule | mit |
kielfriedt/ece472 | lab2/lookahead.v | 1,409 | module MODULE1(VAR5, VAR4, VAR6, VAR2, VAR1, VAR7, VAR3);
input [3:0] VAR2, VAR1;
input VAR5;
output [2:0] VAR6;
output VAR4;
output VAR7, VAR3;
assign VAR6[0] = VAR1[0] | (VAR2[0] & VAR5);
assign VAR6[1] = VAR1[1] | (VAR1[0] & VAR2[1]) | (VAR2[1] & VAR2[0] & VAR5);
assign VAR6[2] = VAR1[2] | (VAR1[1] & VAR2[2]) | (VAR... | gpl-3.0 |
Kipsora/MIPS-CPU | source/machine/cpu/stages/ex.v | 19,996 | module MODULE1(
input wire reset,
input wire[VAR41] VAR23,
input wire[VAR41] VAR5,
input wire VAR18,
input wire[VAR41] VAR8,
input wire[VAR41] VAR72,
input wire VAR17,
input wire[VAR41] VAR20,
input wire[VAR41] VAR67,
input wire[VAR9] VAR29,
input wire VAR27,
input wire[VAR60] VAR25,
input wire[VAR13] VAR12,
input wire... | mit |
Elphel/x353 | sensor/lens_flat.v | 16,679 | module MODULE1 (VAR21, VAR51, VAR78, VAR31, VAR13, VAR54, VAR18, VAR2,
VAR11, VAR53 );
input VAR21;
input VAR51;
input [15:0] VAR78;
input VAR31;
input VAR13;
input VAR54;
input VAR18;
input [1:0] VAR2;
input [15:0] VAR11;
output[15:0] VAR53;
reg [ 1:0] VAR48;
reg [23:0] VAR17;
reg [23:0] VAR23;
reg VAR7,VAR16,VAR33,VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfsbp/sky130_fd_sc_hs__sdfsbp.blackbox.v | 1,419 | module MODULE1 (
VAR9 ,
VAR8 ,
VAR1 ,
VAR3 ,
VAR7 ,
VAR4 ,
VAR2
);
input VAR9 ;
input VAR8 ;
output VAR1 ;
output VAR3 ;
input VAR7 ;
input VAR4 ;
input VAR2;
supply1 VAR6;
supply0 VAR5;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/phy/phy_rdlvl.v | 84,965 | module MODULE1 #
(
parameter VAR32 = 100, parameter VAR217 = 2, parameter VAR150 = 3333, parameter VAR209 = 300, parameter VAR164 = 64, parameter VAR197 = 3, parameter VAR187 = 8, parameter VAR69 = 8, parameter VAR225 = 10, parameter VAR188 = 5, parameter VAR137 = "VAR138", parameter VAR121 = "VAR94" )
(
input clk,
inp... | lgpl-3.0 |
alankarkotwal/lc-3b-processor | design/controller.v | 6,268 | module MODULE1(clk, VAR9, VAR11, VAR14, VAR15, VAR3, VAR23, VAR4, VAR21, VAR6, VAR18, VAR17, VAR8, VAR1, VAR12, VAR7, VAR2, VAR19, VAR16, VAR10, VAR5, VAR22);
input [15:0] VAR9;
input clk, VAR11, VAR14, VAR15;
output reg [3:0] VAR3;
output reg VAR23;
output reg [1:0] VAR4;
output reg [2:0] VAR21;
output reg [1:0] VAR6;... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o311ai/sky130_fd_sc_hd__o311ai.pp.symbol.v | 1,387 | module MODULE1 (
input VAR9 ,
input VAR1 ,
input VAR3 ,
input VAR10 ,
input VAR6 ,
output VAR2 ,
input VAR7 ,
input VAR5,
input VAR4,
input VAR8
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a41o/sky130_fd_sc_hs__a41o.behavioral.pp.v | 1,959 | module MODULE1 (
VAR7,
VAR8,
VAR16 ,
VAR11 ,
VAR15 ,
VAR13 ,
VAR5 ,
VAR14
);
input VAR7;
input VAR8;
output VAR16 ;
input VAR11 ;
input VAR15 ;
input VAR13 ;
input VAR5 ;
input VAR14 ;
wire VAR5 VAR9 ;
wire VAR2 ;
wire VAR3;
and VAR4 (VAR9 , VAR11, VAR15, VAR13, VAR5 );
or VAR10 (VAR2 , VAR9, VAR14 );
VAR12 VAR1 (VAR3,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21bo/sky130_fd_sc_hs__a21bo.blackbox.v | 1,347 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR5 ,
VAR4
);
output VAR1 ;
input VAR2 ;
input VAR5 ;
input VAR4;
supply1 VAR6;
supply0 VAR3;
endmodule | apache-2.0 |
mshaklunov/usb_devtrsac | rtl/usb_devtrsac.v | 9,996 | module MODULE1 (
input VAR40,
input VAR45,
input VAR24,
input VAR20,
input VAR74,
input VAR14,
output VAR61,
output VAR16,
output VAR36,
output[1:0] VAR33,
output[3:0] VAR79,
output[1:0] VAR27,
input[1:0] VAR55,
input VAR46,
output VAR30,
output[7:0] VAR31,
input VAR6,
output VAR15,
input[7:0] VAR21,
input[15:1] VAR77,... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_mout/rtl/jbi_jid_to_yid_pool.v | 18,290 | module MODULE1 (
VAR32, VAR53, VAR24, VAR28,
VAR41, VAR16, VAR30, VAR45, VAR22, VAR49, VAR21, clk,
VAR14
);
output VAR32; output [3:0] VAR53; input VAR41; input VAR16; input [3:0] VAR30; input VAR45; input [3:0] VAR22; input [3:0] VAR49; output VAR24; input [3:0] VAR21; output VAR28; input clk; input VAR14;
wire VAR20;... | gpl-2.0 |
andrewandrepowell/kernel-on-chip | hdl/projects/Nexys4/bd/ip/bd_mig_7series_0_0/bd_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v | 21,574 | module MODULE1 #
(parameter VAR126 = 3,
parameter VAR31 = 8,
parameter VAR19 = 4,
parameter VAR29 = 128,
parameter VAR41 = 100)
(
VAR86, VAR28, VAR123,
VAR103, VAR99, VAR46,
VAR83, VAR17, VAR81, VAR77, VAR34,
VAR23, VAR24, VAR53,
VAR52, VAR111, VAR72, VAR61,
VAR75, VAR62, VAR109,
clk, rst, VAR125, VAR133, VAR110,
VAR66... | mit |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/ip/hdl/verilog/FIFO_image_filter_mask_data_stream_0_V.v | 3,013 | module MODULE1 (
clk,
VAR18,
VAR7,
VAR1,
VAR4);
parameter VAR6 = 32'd8;
parameter VAR16 = 32'd1;
parameter VAR25 = 32'd2;
input clk;
input [VAR6-1:0] VAR18;
input VAR7;
input [VAR16-1:0] VAR1;
output [VAR6-1:0] VAR4;
reg[VAR6-1:0] VAR17 [0:VAR25-1];
integer VAR13;
always @ (posedge clk)
begin
if (VAR7)
begin
for (VAR13... | gpl-3.0 |
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