repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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|---|---|---|---|---|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_4.behavioral.v | 1,262 | module MODULE1( VAR6, VAR4, VAR7, VAR2 );
input VAR2, VAR6, VAR7;
output VAR4;
VAR3 VAR1(.VAR6(VAR6),.VAR4(VAR4),.VAR7(VAR7),.VAR2(VAR2));
VAR3 VAR5(.VAR6(VAR6),.VAR4(VAR4),.VAR7(VAR7),.VAR2(VAR2)); | apache-2.0 |
osecpu/fpga | preg.v | 1,821 | module MODULE1(clk,
VAR11, VAR10, VAR14,
VAR7, VAR12, VAR5,
VAR6, VAR3, VAR13,
VAR1, VAR8);
input clk, VAR1;
input [5:0] VAR11, VAR10, VAR14;
output reg [11:0] VAR7, VAR12;
input [11:0] VAR5;
output reg [15:0] VAR6, VAR3;
input [15:0] VAR13;
output VAR8;
reg [11:0] VAR4[63:0]; reg [15:0] VAR2[63:0];
wire [5:0] VAR9;
as... | mit |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | src/uart_comm.v | 6,261 | module MODULE1 (
input VAR57,
input VAR51,
input VAR12,
input [31:0] VAR35,
output reg VAR50 = 1'b0,
output reg [255:0] VAR5 = 256'd0,
output reg [95:0] VAR26 = 96'd0,
output reg [31:0] VAR20 = 32'd0,
output reg [31:0] VAR24 = 32'd0,
input VAR19,
input VAR25,
output VAR2
);
localparam VAR6 = 60;
localparam VAR21 = 256 ... | gpl-3.0 |
onchipuis/mriscv_vivado | mriscv_vivado.srcs/sources_1/ip/ddr_axi/ddr_axi/user_design/rtl/axi/mig_7series_v4_0_axi_mc_wrap_cmd.v | 11,271 | module MODULE1 #
(
parameter integer VAR26 = 32,
parameter integer VAR22 = 30,
parameter integer VAR23 = 1,
parameter integer VAR1 = 32,
parameter integer VAR4 = 2,
parameter integer VAR32 = 0
)
(
input wire clk ,
input wire reset ,
input wire [VAR26-1:0] VAR10 ,
input wire [7:0] VAR20 ,
input wire [2:0] VAR19 , input ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4b/sky130_fd_sc_lp__nor4b.blackbox.v | 1,322 | module MODULE1 (
VAR8 ,
VAR9 ,
VAR7 ,
VAR2 ,
VAR4
);
output VAR8 ;
input VAR9 ;
input VAR7 ;
input VAR2 ;
input VAR4;
supply1 VAR5;
supply0 VAR6;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/diode/sky130_fd_sc_hs__diode.blackbox.v | 1,214 | module MODULE1 (
VAR2
);
input VAR2;
supply1 VAR5;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
AloriumTechnology/XLR8SPI | extras/rtl/openxlr8.v | 16,846 | module MODULE1
parameter VAR1 = 1;
logic [VAR1-1:0][VAR6-1:0] VAR35;
logic [VAR1-1:0][VAR6-1:0] VAR53;
logic [VAR1-1:0][VAR6-1:0] VAR44;
logic [VAR1-1:0][VAR6-1:0] VAR7;
logic [7:0] VAR24;
logic VAR56;
logic VAR72, VAR33;
logic VAR5;
logic VAR11;
logic VAR15;
logic VAR42;
logic VAR20;
assign VAR20 = VAR46[7];
assign VA... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dlclkp/sky130_fd_sc_hvl__dlclkp.symbol.v | 1,280 | module MODULE1 (
input VAR6 ,
input VAR3,
output VAR5
);
supply1 VAR2;
supply0 VAR4;
supply1 VAR7 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fill/sky130_fd_sc_ls__fill.behavioral.pp.v | 1,147 | module MODULE1 (
VAR1,
VAR4,
VAR2 ,
VAR3
);
input VAR1;
input VAR4;
input VAR2 ;
input VAR3 ;
endmodule | apache-2.0 |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/verif/router/packet_source.v | 28,148 | module MODULE1
(clk, reset, VAR5, VAR28, VAR186, VAR109, VAR45, VAR6);
parameter VAR102 = 0;
parameter VAR148 = 1000;
parameter VAR185 = 25;
parameter VAR133 = 32;
parameter VAR65 = 0;
parameter VAR159 = VAR21;
parameter VAR124 = 32;
parameter VAR117 = 2;
parameter VAR84 = 2;
localparam VAR114 = VAR165(VAR84);
localpar... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor2/sky130_fd_sc_hs__nor2_2.v | 1,959 | module MODULE1 (
VAR7 ,
VAR1 ,
VAR5 ,
VAR2,
VAR4
);
output VAR7 ;
input VAR1 ;
input VAR5 ;
input VAR2;
input VAR4;
VAR3 VAR6 (
.VAR7(VAR7),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR7,
VAR1,
VAR5
);
output VAR7;
input VAR1;
input VAR5;
supply1 VAR2;
supply0 VAR4;
VAR3 VAR6 (
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkinv/sky130_fd_sc_hs__clkinv_2.v | 1,909 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR2,
VAR4
);
output VAR3 ;
input VAR5 ;
input VAR2;
input VAR4;
VAR6 VAR1 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR3,
VAR5
);
output VAR3;
input VAR5;
supply1 VAR2;
supply0 VAR4;
VAR6 VAR1 (
.VAR3(VAR3),
.VAR5(VAR5)
);
endmodule | apache-2.0 |
manu3193/GatoTDD | VGA_Controlador.v | 2,149 | module MODULE1(
input wire clk,
input wire reset,
output reg VAR15,
output reg VAR12,
output reg [10:0] VAR13,
output reg [10:0] VAR5,
output reg VAR4
);
parameter VAR10 = 11'd800;
parameter VAR1 = 11'd96;
parameter VAR9 = 11'd2;
parameter VAR3 = 11'd525;
parameter VAR11 = 11'd144 ;
parameter VAR6 = 11'd784 ;
parameter... | mit |
jameshegarty/rigel | platform/camera2.0/vsrc/MMIO_slave.v | 10,221 | module MODULE1(
input VAR121,
input VAR79,
output VAR59,
input [31:0] VAR107,
input [11:0] VAR125,
output VAR22,
input VAR41,
input [31:0] VAR40,
input [11:0] VAR89,
output VAR30,
input VAR65,
output [11:0] VAR94,
input VAR99,
output [1:0] VAR76,
output VAR26,
output [31:0] VAR84,
output [11:0] VAR66,
output VAR67,
inp... | mit |
olajep/oh | src/adi/hdl/library/common/ad_mem_asym.v | 5,153 | module MODULE1 #(
parameter VAR15 = 8,
parameter VAR20 = 256,
parameter VAR9 = 10,
parameter VAR6 = 64) (
input VAR1,
input VAR25,
input [VAR15-1:0] VAR3,
input [VAR20-1:0] VAR13,
input VAR2,
input VAR11,
input [VAR9-1:0] VAR27,
output reg [VAR6-1:0] VAR23);
function integer VAR18;
input integer VAR26;
begin
if (VAR26 ... | mit |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_processing_system7_0_0/hdl/processing_system7_bfm_v2_0_reg_map.v | 4,323 | module MODULE1();
parameter VAR27 = 32'h20000000; parameter VAR13 = 32'h10000000;
reg [VAR24-1:0] VAR6 [0:(VAR13/VAR10)-1]; reg [VAR24-1:0] VAR34 [0:(VAR13/VAR10)-1]; parameter VAR20 = 26;
reg [VAR24-1:0] VAR33 [0:(VAR27/VAR10)-1]; parameter VAR20 = 27;
task automatic VAR5;
input VAR22;
begin
end
endtask
task automatic... | bsd-2-clause |
Darkin47/Zynq-TX-UTT | Vivado_HLS/convolution_2D/solution1/impl/ip/hdl/verilog/doImgProc_CRTL_BUS_s_axi.v | 9,423 | module MODULE1
VAR26 = 5,
VAR37 = 32
)(
input wire VAR33,
input wire VAR46,
input wire VAR59,
input wire [VAR26-1:0] VAR57,
input wire VAR1,
output wire VAR11,
input wire [VAR37-1:0] VAR12,
input wire [VAR37/8-1:0] VAR13,
input wire VAR6,
output wire VAR35,
output wire [1:0] VAR8,
output wire VAR53,
input wire VAR9,
in... | gpl-3.0 |
Elphel/x353 | sensor/sensorpix353.v | 24,071 | module MODULE1( VAR84, VAR105, VAR2,
VAR23, VAR106, VAR41, VAR58, VAR28, en, VAR74, VAR16, VAR125,
VAR29,
VAR64, VAR27, VAR108, VAR116, do, VAR42, VAR111,
VAR91,
VAR46,
VAR117, VAR79);
input VAR84;
input VAR105;
input VAR2;
input VAR23;
input VAR106;
input [15:0] VAR28;
input en;
output VAR74;
output VAR16;
input [ 1:0... | gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_piano/zybo_petalinux_piano.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_r_channel.v | 6,152 | module MODULE1 #
(
parameter integer VAR6 = 4,
parameter integer VAR31 = 32
)
(
input wire clk ,
input wire reset ,
output wire [VAR6-1:0] VAR28 ,
output wire [VAR31-1:0] VAR47 ,
output wire [1:0] VAR7 ,
output wire VAR19 ,
output wire VAR21 ,
input wire VAR36 ,
input wire [VAR31-1:0] VAR41 ,
input wire [1:0] VAR29 ,
i... | gpl-3.0 |
secworks/aes | src/rtl/aes_sbox.v | 10,489 | module MODULE1(
input wire [31 : 0] VAR2,
output wire [31 : 0] VAR3
);
wire [7 : 0] VAR1 [0 : 255];
assign VAR3[31 : 24] = VAR1[VAR2[31 : 24]];
assign VAR3[23 : 16] = VAR1[VAR2[23 : 16]];
assign VAR3[15 : 08] = VAR1[VAR2[15 : 08]];
assign VAR3[07 : 00] = VAR1[VAR2[07 : 00]];
assign VAR1[8'h00] = 8'h63;
assign VAR1[8'h0... | bsd-2-clause |
duttondj/DigitalDesignI-P3 | counter16bit.v | 3,065 | module MODULE1(VAR6, enable, VAR1, VAR3, VAR8, VAR2, VAR4);
input VAR6, enable, VAR1, VAR3, VAR8;
input [3:0] VAR2;
output [15:0] VAR4;
reg [15:0] VAR7, VAR5;
always @(posedge VAR6 or negedge VAR1) begin
if (VAR1 == 0)
VAR7 <= 16'b0;
end
else
VAR7 <= VAR5;
end
always @(enable or VAR7) begin
VAR5 = VAR7;
if (!enable)
VA... | mit |
kactus2/ipxactexamplelib | tut.fi/communication.template/spi_master/1.0/spi_master.v | 3,610 | module MODULE1(
input VAR18,
output VAR8,
output reg VAR9,
output reg VAR15,
output reg VAR3,
output reg VAR5,
input VAR2, input VAR10 );
localparam VAR7 = 8; localparam VAR4 = VAR6(VAR7);
reg [VAR7-1:0] VAR1;
reg [VAR7-1:0] VAR17;
reg [VAR4-1:0] VAR16;
reg [VAR4-1:0] VAR13;
reg [1:0] state;
parameter [1:0]
VAR19 = 2'd... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21a/sky130_fd_sc_lp__o21a.functional.v | 1,412 | module MODULE1 (
VAR3 ,
VAR6,
VAR8,
VAR9
);
output VAR3 ;
input VAR6;
input VAR8;
input VAR9;
wire VAR2 ;
wire VAR5;
or VAR4 (VAR2 , VAR8, VAR6 );
and VAR1 (VAR5, VAR2, VAR9 );
buf VAR7 (VAR3 , VAR5 );
endmodule | apache-2.0 |
bigeagle/riffa | fpga/riffa_hdl/tx_port_monitor_32.v | 8,504 | module MODULE1 #(
parameter VAR26 = 9'd32,
parameter VAR12 = 512,
parameter VAR32 = (VAR12 - 4),
parameter VAR42 = VAR25((2**VAR25(VAR12))+1),
parameter VAR33 = 1
)
(
input VAR39,
input VAR27,
input [VAR26:0] VAR34, input VAR28, output VAR21,
output [VAR26-1:0] VAR9, output VAR38, input [VAR42-1:0] VAR7,
output VAR5, i... | bsd-3-clause |
SymbiFlow/yosys | techlibs/achronix/speedster22i/cells_map.v | 2,627 | module \VAR15 (input VAR18, output VAR22);
VAR8 VAR19 (.VAR5(VAR22), .VAR28(VAR18));
endmodule
module \VAR12 (input VAR18, output VAR22);
VAR26 VAR19 (.VAR5(VAR22), .VAR28(VAR18), .VAR16(1'b1));
endmodule
module MODULE4 (VAR2, VAR4);
parameter VAR10 = 0;
parameter VAR3 = 0;
input [VAR10-1:0] VAR2;
output VAR4;
generate... | isc |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/mux2i/sky130_fd_sc_hs__mux2i_4.v | 2,087 | module MODULE1 (
VAR5 ,
VAR8 ,
VAR6 ,
VAR4 ,
VAR7,
VAR2
);
output VAR5 ;
input VAR8 ;
input VAR6 ;
input VAR4 ;
input VAR7;
input VAR2;
VAR3 VAR1 (
.VAR5(VAR5),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR5 ,
VAR8,
VAR6,
VAR4
);
output VAR5 ;
input VAR8;
input VAR6;
... | apache-2.0 |
merckhung/zet | cores/vga/rtl/fml/vga_crtc_fml.v | 3,504 | module MODULE1 (
input clk, input rst,
input VAR6,
input [5:0] VAR15,
input [5:0] VAR10,
input [4:0] VAR7,
input [6:0] VAR5,
input [6:0] VAR9,
input [6:0] VAR11,
input [6:0] VAR2,
input [4:0] VAR16,
input [9:0] VAR21,
input [9:0] VAR3,
input [9:0] VAR22,
input [3:0] VAR25,
output reg [9:0] VAR24, output reg VAR12,
outp... | gpl-3.0 |
eda-globetrotter/PicenoDecoders | final/src/tosynth Folder/datamem.v | 2,673 | module MODULE1 (VAR2,VAR4,VAR3,clk,VAR1);
output [0:127] VAR2;
input [0:127] VAR4;
input [0:31] VAR3;
input clk;
input [0:1] VAR1;
reg [0:127] VAR2;
reg [127:0] MODULE1 [255:0];
begin
begin
begin
begin
begin
begin | mit |
dries007/Basys3 | VGA/VGA.srcs/sources_1/ip/v_ram/v_ram_stub.v | 1,329 | module MODULE1(VAR3, VAR1, VAR6, VAR4, VAR7, VAR2, VAR5)
;
input VAR3;
input [0:0]VAR1;
input [16:0]VAR6;
input [11:0]VAR4;
input VAR7;
input [16:0]VAR2;
output [11:0]VAR5;
endmodule | mit |
ncos/Xilinx-Verilog | ZOLED/src/toplevel.v | 1,872 | module MODULE1
(VAR25,
VAR23,
VAR5,
VAR18,
VAR15,
VAR6,
VAR36,
VAR32,
VAR33,
VAR13,
VAR19,
VAR39,
VAR8,
VAR20,
VAR17,
VAR22,
VAR4,
VAR29,
VAR16,
VAR34,
VAR1,
VAR10,
VAR12,
VAR30,
VAR40,
VAR31,
VAR35,
VAR21,
VAR38,
VAR2,
VAR11
);
output wire VAR36;
output wire VAR32;
output wire VAR33;
output wire VAR13;
output wire VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfsbp/sky130_fd_sc_ms__sdfsbp.functional.v | 2,061 | module MODULE1 (
VAR9 ,
VAR10 ,
VAR2 ,
VAR18 ,
VAR6 ,
VAR12 ,
VAR4
);
output VAR9 ;
output VAR10 ;
input VAR2 ;
input VAR18 ;
input VAR6 ;
input VAR12 ;
input VAR4;
wire VAR1 ;
wire VAR14 ;
wire VAR15;
not VAR3 (VAR14 , VAR4 );
VAR7 VAR17 (VAR15, VAR18, VAR6, VAR12 );
VAR8 VAR13 VAR16 (VAR1 , VAR15, VAR2, VAR14);
buf V... | apache-2.0 |
glennchid/font5-firmware | src/verilog/synthesis/antiDroopIIR_16.v | 2,138 | module MODULE1 (
input clk,
input VAR4,
input signed [15:0] din,
input signed [6:0] VAR18,
input VAR10,
output reg VAR14 = 1'd0,
output reg signed [15:0] dout = 16'VAR7);
parameter VAR13 = 15;
reg signed [15:0] VAR11 = 16'VAR7;
reg signed [47:0] VAR8 = 48'VAR7;
reg signed [22:0] VAR1 = 23'VAR7;
reg VAR12 = 1'b0, VAR15 ... | gpl-3.0 |
Separius/Custom-Single-Cycle-MIPS | Controller.v | 2,455 | module MODULE1(input clk,rst,output reg VAR6,VAR7,VAR9,VAR4,output reg[1:0] VAR2,VAR8,input VAR3,VAR1,input[5:0] VAR5);
always@(rst,VAR3,VAR1,VAR5)
begin
if((VAR5[5] == 1'b0) || (VAR5[5:3] == 3'b110)) begin
VAR6=1'b0;
VAR7=1'b1;
VAR9=1'b1;
VAR4=1'b0;
VAR2=2'b00;
VAR8=2'b00;
end
else if(VAR5[5:1] == 5'b10000) begin
VAR6... | gpl-3.0 |
niamster/hdl | spwm/spwm.v | 4,627 | module MODULE1
parameter VAR12=10)
(input clk,
input VAR4,
input [VAR15-1:0] VAR1,
input [VAR15-1:0] VAR26,
input [VAR15-1:0] VAR29,
input [VAR12-1:0] VAR34,
input VAR20,
input VAR30,
input VAR11,
output reg VAR28,
output VAR9);
reg [VAR12-1:0] VAR2;
wire [VAR12-1:0] VAR19;
wire [VAR15-1:0] VAR5;
reg [VAR15-1:0] d0;
wi... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9739a/axi_ad9739a_if.v | 6,679 | module MODULE1 (
VAR8,
VAR15,
VAR23,
VAR24,
VAR48,
VAR50,
VAR31,
VAR12,
VAR41,
VAR30,
VAR6,
VAR26,
VAR20,
VAR35,
VAR57,
VAR27,
VAR58,
VAR18,
VAR21,
VAR37,
VAR62,
VAR45,
VAR22,
VAR25,
VAR42,
VAR54,
VAR11,
VAR38);
parameter VAR52 = 0;
input VAR8;
input VAR15;
output VAR23;
output VAR24;
output [13:0] VAR48;
output [13:0]... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/nor3/sky130_fd_sc_hvl__nor3.behavioral.pp.v | 1,853 | module MODULE1 (
VAR1 ,
VAR10 ,
VAR2 ,
VAR9 ,
VAR6,
VAR14,
VAR11 ,
VAR8
);
output VAR1 ;
input VAR10 ;
input VAR2 ;
input VAR9 ;
input VAR6;
input VAR14;
input VAR11 ;
input VAR8 ;
wire VAR7 ;
wire VAR12;
nor VAR3 (VAR7 , VAR9, VAR10, VAR2 );
VAR13 VAR5 (VAR12, VAR7, VAR6, VAR14);
buf VAR4 (VAR1 , VAR12 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or3/sky130_fd_sc_lp__or3_0.v | 2,153 | module MODULE2 (
VAR9 ,
VAR7 ,
VAR1 ,
VAR6 ,
VAR10,
VAR8,
VAR3 ,
VAR4
);
output VAR9 ;
input VAR7 ;
input VAR1 ;
input VAR6 ;
input VAR10;
input VAR8;
input VAR3 ;
input VAR4 ;
VAR5 VAR2 (
.VAR9(VAR9),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR4(VAR4)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor3b/sky130_fd_sc_hs__nor3b.behavioral.pp.v | 1,924 | module MODULE1 (
VAR7,
VAR5,
VAR14 ,
VAR8 ,
VAR2 ,
VAR3
);
input VAR7;
input VAR5;
output VAR14 ;
input VAR8 ;
input VAR2 ;
input VAR3 ;
wire VAR11 ;
wire VAR6 ;
wire VAR4;
nor VAR12 (VAR11 , VAR8, VAR2 );
and VAR1 (VAR6 , VAR3, VAR11 );
VAR10 VAR9 (VAR4, VAR6, VAR7, VAR5);
buf VAR13 (VAR14 , VAR4 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a22oi/sky130_fd_sc_ms__a22oi_4.v | 2,352 | module MODULE2 (
VAR6 ,
VAR9 ,
VAR5 ,
VAR3 ,
VAR1 ,
VAR8,
VAR2,
VAR10 ,
VAR7
);
output VAR6 ;
input VAR9 ;
input VAR5 ;
input VAR3 ;
input VAR1 ;
input VAR8;
input VAR2;
input VAR10 ;
input VAR7 ;
VAR4 VAR11 (
.VAR6(VAR6),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR... | apache-2.0 |
aj-michael/Digital-Systems | Lab4-Part2-RAMwithHyperTerminalDisplay/uart_tx.v | 5,237 | module MODULE1 (
input [7:0] VAR16,
input VAR3,
input VAR17,
input VAR14,
output VAR11,
output VAR5,
output VAR8,
input clk);
wire [7:0] VAR9;
wire VAR19;
wire VAR1;
VAR10 VAR2 (
.VAR16 (VAR9),
.VAR18 (VAR19),
.VAR14 (VAR14),
.VAR11 (VAR11),
.VAR20 (VAR1),
.clk (clk));
VAR4 VAR6 (
.VAR16 (VAR16),
.VAR12 (VAR9),
.reset ... | mit |
monotone-RK/FACE | IEICE-Trans/data_compression/8-way_2-tree/src/riffa/rx_port_32.v | 15,824 | module MODULE1 #(
parameter VAR151 = 9'd32,
parameter VAR125 = 1024,
parameter VAR61 = 512,
parameter VAR145 = 2, parameter VAR51 = VAR84((VAR151/32)+1),
parameter VAR5 = VAR84((2**VAR84(VAR125))+1),
parameter VAR66 = VAR84((2**VAR84(VAR61))+1)
)
(
input VAR32,
input VAR118,
input [2:0] VAR25,
output VAR93, input [31:0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2111ai/sky130_fd_sc_lp__o2111ai.behavioral.v | 1,610 | module MODULE1 (
VAR15 ,
VAR5,
VAR9,
VAR10,
VAR14,
VAR13
);
output VAR15 ;
input VAR5;
input VAR9;
input VAR10;
input VAR14;
input VAR13;
supply1 VAR12;
supply0 VAR11;
supply1 VAR1 ;
supply0 VAR6 ;
wire VAR7 ;
wire VAR4;
or VAR8 (VAR7 , VAR9, VAR5 );
nand VAR2 (VAR4, VAR14, VAR10, VAR13, VAR7);
buf VAR3 (VAR15 , VAR4 )... | apache-2.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_incr_cmd.v | 4,487 | module MODULE1 #
(
parameter integer VAR12 = 32
)
(
input wire clk ,
input wire reset ,
input wire [VAR12-1:0] VAR17 ,
input wire [7:0] VAR16 ,
input wire [2:0] VAR10 ,
input wire VAR14 ,
output wire [VAR12-1:0] VAR8 ,
input wire VAR2 ,
output reg VAR4
);
reg VAR15;
reg [11:0] VAR3;
reg [8:0] VAR6;
reg VAR7;
wire [3:0]... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and3b/sky130_fd_sc_ls__and3b_4.v | 2,218 | module MODULE1 (
VAR8 ,
VAR10 ,
VAR5 ,
VAR1 ,
VAR4,
VAR7,
VAR2 ,
VAR6
);
output VAR8 ;
input VAR10 ;
input VAR5 ;
input VAR1 ;
input VAR4;
input VAR7;
input VAR2 ;
input VAR6 ;
VAR9 VAR3 (
.VAR8(VAR8),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR6(VAR6)
);
endmodule
module MODULE... | apache-2.0 |
thucoldwind/ucore_mips | CPU32/thinpad_top/thinpad_top.srcs/sources_1/new/registers.v | 2,664 | module MODULE1(
input wire clk,
input wire rst,
input wire[4:0] VAR7,
input wire VAR6,
output reg[31:0] VAR12,
input wire[4:0] VAR11,
input wire VAR4,
output reg[31:0] VAR10,
input wire[4:0] VAR2,
input wire[31:0] VAR8,
input wire VAR5
);
reg[31:0] VAR1[0:31];
always @ begin
if (VAR11 == 5'h0) begin
VAR10 = VAR3;
end e... | unlicense |
hwstar/Timestamper-FPGA | system.v | 15,078 | module MODULE1(VAR34, VAR62, VAR61, VAR81, VAR7, VAR27, VAR16,
VAR49, VAR50, VAR8, VAR74, VAR31, VAR25, VAR63, VAR75,
VAR73, VAR5, VAR51, VAR37, VAR1, VAR59, VAR55,
VAR80, VAR4, VAR10, VAR9, VAR23, VAR29, VAR44,VAR35, VAR19, VAR57);
input [2:0] VAR34;
input [1:0] VAR62;
input [1:0] VAR61;
input [2:0] VAR81;
input [7:0]... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o41a/sky130_fd_sc_hd__o41a.blackbox.v | 1,367 | module MODULE1 (
VAR6 ,
VAR8,
VAR9,
VAR5,
VAR4,
VAR2
);
output VAR6 ;
input VAR8;
input VAR9;
input VAR5;
input VAR4;
input VAR2;
supply1 VAR1;
supply0 VAR3;
supply1 VAR10 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
Apo45ty/ArquiCourseCPUVerilog | VerilogSource/CPU/controlunit3.v | 4,927 | module MODULE1 (output reg VAR11, VAR8, VAR20, VAR19, VAR14, VAR16, VAR3, VAR10,VAR13,VAR9,VAR15,VAR6,VAR5,output reg[4:0] VAR17, output reg[3:0] VAR1, input VAR12, VAR7,VAR2, input [31:0] VAR23,input [3:0] VAR18);
reg [4:0] VAR22, VAR4;
task VAR24;
input [17:0] VAR21;
fork
{VAR1,VAR11, VAR8, VAR20, VAR19,VAR17, VAR14,... | apache-2.0 |
hydai/Verilog-Practice | HardwareLab/Lab5/KeyBoard_ctrl.v | 3,033 | module MODULE1(VAR2, VAR15, VAR9, VAR7, VAR11, VAR6);
input VAR2;
input VAR15;
input [3:0] VAR7;
output [3:0] VAR9;
output [3:0] VAR6;
output [3:0] VAR11;
reg [3:0] VAR9;
reg [3:0] VAR1;
reg [3:0] VAR3;
reg [3:0] VAR6;
reg [3:0] VAR11;
reg [3:0] VAR5;
reg [7:0] VAR12;
reg [14:0] VAR13;
reg VAR4;
wire VAR14;
wire VAR16;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrtn/sky130_fd_sc_lp__sdfrtn.behavioral.pp.v | 2,993 | module MODULE1 (
VAR2 ,
VAR17 ,
VAR26 ,
VAR6 ,
VAR19 ,
VAR31,
VAR25 ,
VAR13 ,
VAR10 ,
VAR18
);
output VAR2 ;
input VAR17 ;
input VAR26 ;
input VAR6 ;
input VAR19 ;
input VAR31;
input VAR25 ;
input VAR13 ;
input VAR10 ;
input VAR18 ;
wire VAR29 ;
wire VAR5 ;
wire VAR30 ;
wire VAR16 ;
reg VAR9 ;
wire VAR21 ;
wire VAR14 ;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o41a/sky130_fd_sc_ms__o41a_4.v | 2,411 | module MODULE2 (
VAR9 ,
VAR10 ,
VAR8 ,
VAR2 ,
VAR6 ,
VAR11 ,
VAR5,
VAR4,
VAR1 ,
VAR12
);
output VAR9 ;
input VAR10 ;
input VAR8 ;
input VAR2 ;
input VAR6 ;
input VAR11 ;
input VAR5;
input VAR4;
input VAR1 ;
input VAR12 ;
VAR3 VAR7 (
.VAR9(VAR9),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR5... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/muxb4to1/sky130_fd_sc_hdll__muxb4to1_1.v | 2,219 | module MODULE1 (
VAR9 ,
VAR7 ,
VAR2 ,
VAR5,
VAR6,
VAR4 ,
VAR3
);
output VAR9 ;
input [3:0] VAR7 ;
input [3:0] VAR2 ;
input VAR5;
input VAR6;
input VAR4 ;
input VAR3 ;
VAR8 VAR1 (
.VAR9(VAR9),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR9,
VAR7,
VAR2
);
o... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a222oi/sky130_fd_sc_hdll__a222oi.pp.blackbox.v | 1,472 | module MODULE1 (
VAR10 ,
VAR9 ,
VAR8 ,
VAR11 ,
VAR3 ,
VAR4 ,
VAR6 ,
VAR1,
VAR2,
VAR5 ,
VAR7
);
output VAR10 ;
input VAR9 ;
input VAR8 ;
input VAR11 ;
input VAR3 ;
input VAR4 ;
input VAR6 ;
input VAR1;
input VAR2;
input VAR5 ;
input VAR7 ;
endmodule | apache-2.0 |
sam-falvo/kestrel | cores/KCP53K/cpu2/rtl/verilog/exec.v | 5,075 | module MODULE1(
input VAR11,
input VAR34,
input [63:0] VAR3,
input [63:0] VAR35,
input VAR36,
input VAR40,
input VAR10,
input VAR16,
input VAR9,
input VAR17,
input VAR14,
input VAR37,
input VAR44,
input [4:0] VAR12,
input VAR32,
input VAR51,
input VAR27,
input [63:0] VAR31,
input [2:0] VAR47,
input VAR8,
output [4:0] V... | mpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21bo/sky130_fd_sc_ls__a21bo.behavioral.pp.v | 2,043 | module MODULE1 (
VAR8 ,
VAR14 ,
VAR16 ,
VAR3,
VAR12,
VAR5,
VAR6 ,
VAR4
);
output VAR8 ;
input VAR14 ;
input VAR16 ;
input VAR3;
input VAR12;
input VAR5;
input VAR6 ;
input VAR4 ;
wire VAR2 ;
wire VAR13 ;
wire VAR11;
nand VAR7 (VAR2 , VAR16, VAR14 );
nand VAR15 (VAR13 , VAR3, VAR2 );
VAR10 VAR1 (VAR11, VAR13, VAR12, VAR... | apache-2.0 |
walkthetalk/fsref | ip/mm2s/src/include/MM2FIFO.v | 7,038 | module MODULE1 #
(
parameter integer VAR11 = 12,
parameter integer VAR17 = 12,
parameter integer VAR39 = 4,
parameter integer VAR48 = 12,
parameter integer VAR29 = 16,
parameter integer VAR32 = 32,
parameter integer VAR7 = 32
)
(
input wire VAR18,
output wire VAR21,
input wire [VAR11-1:0] VAR8,
input wire [VAR17-1:0] V... | gpl-3.0 |
audiocircuit/NCSU-Low-Power-RFID | rfid-verilog/tag/cmdparser.v | 3,544 | module MODULE1 (reset, VAR2, VAR10, VAR5, VAR11, VAR7,
VAR6, VAR4, VAR3);
input reset, VAR2, VAR10;
output VAR11, VAR7;
output [8:0] VAR5;
output [1:0] VAR6;
output VAR4, VAR3;
reg VAR11;
wire [8:0] VAR5;
wire VAR12, VAR7;
reg [7:0] VAR9;
wire [7:0] VAR8;
reg [5:0] VAR1;
reg [1:0] VAR6;
reg VAR4, VAR3;
always @ (posedg... | gpl-3.0 |
hydai/Verilog-Practice | HardwareLab/Lab4/display.v | 1,369 | module MODULE1(clk, VAR1, VAR3, out);
input clk;
input VAR1;
input [15:0]VAR3;
output [18:0]out;
wire clk, VAR1;
wire [15:0]VAR3;
reg [18:0]out;
reg [1:0]select;
reg [1:0]VAR4;
parameter d0=15'b000000111111111;
parameter d1=15'b111111111011011;
parameter d2=15'b011001011101111;
parameter d3=15'b011011011101101;
paramet... | mit |
eda-globetrotter/MarcheProcessor | processor/syn/src/prog_counter2.v | 1,202 | module MODULE1 (VAR1,rst,clk);
output [0:31] VAR1;
input clk;
input rst;
reg [0:31] VAR1;
always @(posedge clk)
begin
if(rst)
begin
VAR1<=32'd0;
end
else
begin
VAR1<=VAR1+32'd4;
end
end
endmodule | mit |
eda-globetrotter/MarcheProcessor | final/src/tosynth Folder/alu_mult.v | 52,026 | module MODULE1(VAR30,VAR5,VAR1,VAR16,VAR37);
output [0:127] VAR37;
input [0:127] VAR30;
input [0:127] VAR5;
input [0:1] VAR1;
input [0:4] VAR16;
parameter VAR23 = 128'hffffffffffffffffffffffffffffffff;
reg [0:127] VAR37;
reg [0:127] VAR4;
reg [0:15] VAR27;
reg [0:15] VAR20;
reg [0:15] VAR18;
reg [0:15] VAR29;
reg [0:15... | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_36.v | 24,362 | module MODULE2 (
clk,
reset,
VAR44,
VAR29,
VAR196,
VAR200,
VAR68
);
parameter VAR70 = 18;
parameter VAR183 = 36;
parameter VAR13 = 18;
localparam VAR76 = 37;
input clk;
input reset;
input VAR44;
input VAR29;
input [VAR70-1:0] VAR196; output VAR200;
output [VAR70-1:0] VAR68;
localparam VAR137 = 18; localparam VAR143 = 3... | mit |
bunnie/novena-sd-fpga | novena-sd.srcs/sources_1/ip/mig_v3_91_0/ddr3_if/user_design/rtl/infrastructure.v | 10,226 | module MODULE1 #
(
parameter VAR71 = 2500,
parameter VAR13 = 1,
parameter VAR111 = "VAR75",
parameter VAR115 = 1,
parameter VAR8 = 1,
parameter VAR1 = 16,
parameter VAR38 = 8,
parameter VAR6 = 2,
parameter VAR59 = 1
)
(
input VAR63,
input VAR47,
input VAR93,
input VAR110,
output VAR21,
output VAR45,
output VAR57,
outpu... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkinv/sky130_fd_sc_hs__clkinv_4.v | 1,909 | module MODULE2 (
VAR4 ,
VAR2 ,
VAR6,
VAR3
);
output VAR4 ;
input VAR2 ;
input VAR6;
input VAR3;
VAR5 VAR1 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR4,
VAR2
);
output VAR4;
input VAR2;
supply1 VAR6;
supply0 VAR3;
VAR5 VAR1 (
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and3b/sky130_fd_sc_hdll__and3b_4.v | 2,234 | module MODULE2 (
VAR10 ,
VAR7 ,
VAR6 ,
VAR2 ,
VAR1,
VAR3,
VAR4 ,
VAR9
);
output VAR10 ;
input VAR7 ;
input VAR6 ;
input VAR2 ;
input VAR1;
input VAR3;
input VAR4 ;
input VAR9 ;
VAR5 VAR8 (
.VAR10(VAR10),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR9(VAR9)
);
endmodule
module MODULE... | apache-2.0 |
Cognoscan/BoostDSP | verilog/src/math/CordicRectToPolar.v | 6,492 | module MODULE1 #(
parameter VAR5 = 1, parameter VAR2 = 16, parameter VAR27 = 16, parameter VAR16 = 0, parameter VAR19 = 16 )
(
input clk, input rst, input VAR9, input signed [VAR2-1:0] VAR7, input signed [VAR2-1:0] VAR15, output reg [VAR27-1:0] VAR26, output reg [VAR2:0] VAR11, output reg VAR25 );
parameter VAR28 = (VA... | apache-2.0 |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/IP/ADDSUBWIDE/ADDSUBWIDE.v | 4,728 | module MODULE1 (
VAR5,
VAR17,
VAR9,
VAR8);
input VAR5;
input [25:0] VAR17;
input [25:0] VAR9;
output [25:0] VAR8;
wire [25:0] VAR6;
wire [25:0] VAR8 = VAR6[25:0];
VAR19 VAR15 (
.VAR5 (VAR5),
.VAR17 (VAR17),
.VAR9 (VAR9),
.VAR8 (VAR6)
,
.VAR7 (),
.VAR13 (),
.VAR18 (),
.VAR1 (),
.VAR10 (),
.VAR11 ()
);
VAR15.VAR22 = "VA... | gpl-2.0 |
monotone-RK/FACE | IEICE-Trans/16-way/src/riffa/tx_port_channel_gate_64.v | 7,022 | module MODULE1 #(
parameter VAR30 = 9'd64,
parameter VAR7 = 8,
parameter VAR16 = VAR30+1
)
(
input VAR20,
input VAR25, output [VAR16-1:0] VAR29, output VAR10, input VAR14,
input VAR24, input VAR28, output VAR26, input VAR27, input [31:0] VAR9, input [30:0] VAR17, input [VAR30-1:0] VAR11, input VAR18, output VAR12 );
re... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9122/axi_ad9122_if.v | 7,457 | module MODULE1 (
VAR21,
VAR44,
VAR71,
VAR38,
VAR64,
VAR24,
VAR34,
VAR54,
VAR26,
VAR46,
VAR32,
VAR1,
VAR20,
VAR23,
VAR36,
VAR66,
VAR62,
VAR60,
VAR22,
VAR39,
VAR50,
VAR53,
VAR58,
VAR55,
VAR10,
VAR45,
VAR13,
VAR28,
VAR70,
VAR51,
VAR11,
VAR63,
VAR7,
VAR31,
VAR41,
VAR56,
VAR6,
VAR72);
parameter VAR69 = 0;
parameter VAR37 = ... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_1.functional.v | 3,002 | module MODULE1( VAR26, VAR36, VAR1, VAR19, VAR21, VAR7, VAR8 );
input VAR8, VAR7, VAR1, VAR21, VAR36, VAR26;
output VAR19;
wire VAR32;
not VAR10( VAR32, VAR8 );
wire VAR3;
not VAR16( VAR3, VAR1 );
wire VAR27;
not VAR9( VAR27, VAR36 );
wire VAR4;
and VAR5( VAR4, VAR32, VAR3, VAR27 );
wire VAR18;
not VAR17( VAR18, VAR26 ... | apache-2.0 |
ECE492-Team5/Platform | soc-platform-quartusii/soc_system/synthesis/submodules/soc_system_jtag_uart.v | 16,904 | module MODULE2 (
clk,
VAR20,
VAR10,
VAR30,
VAR49,
VAR11,
VAR57
)
;
output VAR30;
output [ 7: 0] VAR49;
output VAR11;
output [ 5: 0] VAR57;
input clk;
input [ 7: 0] VAR20;
input VAR10;
wire VAR30;
wire [ 7: 0] VAR49;
wire VAR11;
wire [ 5: 0] VAR57;
always @(posedge clk)
begin
if (VAR10)
("%VAR43", VAR20);
end
assign VAR... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_4.behavioral.pp.v | 1,402 | module MODULE1( VAR10, VAR1, VAR4, VAR6, VAR2, VAR7, VAR5 );
input VAR2, VAR6, VAR10, VAR4;
inout VAR7, VAR5;
output VAR1;
VAR8 VAR3(.VAR10(VAR10),.VAR1(VAR1),.VAR4(VAR4),.VAR6(VAR6),.VAR2(VAR2),.VAR7(VAR7),.VAR5(VAR5));
VAR8 VAR9(.VAR10(VAR10),.VAR1(VAR1),.VAR4(VAR4),.VAR6(VAR6),.VAR2(VAR2),.VAR7(VAR7),.VAR5(VAR5)); | apache-2.0 |
chadharrington/all_spark_cube | fpga/usb_controller.v | 5,445 | module MODULE1
(
input clk,
input VAR37,
input [15:0] VAR43,
input VAR4,
input VAR24,
input [7:0] VAR5,
output [7:0] VAR44,
output VAR14,
output VAR12,
output VAR28,
output [31:0] VAR22,
output [3:0] VAR36,
output VAR2,
output [3:0] VAR29,
output [1:0] VAR38,
output [4:0] VAR3,
output VAR30
);
wire VAR18, VAR42;
wire V... | mit |
karatekid/ultrasonic-fountain | hardware/src/spi_slave.v | 2,021 | module MODULE1(
input clk,
input rst,
input VAR15,
input VAR24,
output VAR14,
input VAR23,
output VAR8,
input [7:0] din,
output [7:0] dout,
output reg VAR16,
output reg VAR13
);
reg VAR11, VAR20;
reg VAR22, VAR19;
reg VAR21, VAR3;
reg VAR27, VAR1;
reg [7:0] VAR6, VAR9;
reg VAR2, VAR5;
reg [2:0] VAR12, VAR18;
reg [7:0] ... | gpl-3.0 |
timtian090/Playground | UVM/UVMPlayground/Lab4/Lab4-Project/TF_BCD_Binary_Encoder.v | 4,777 | module MODULE1();
localparam VAR5 = 17;
localparam VAR1 = 5;
reg [VAR5-1:0] VAR6;
localparam VAR4 = 500000000; localparam VAR3 = ((1.0 / VAR4) * 1000000000.0) / 2.0;
reg VAR2;
begin
begin
begin
begin
end
begin | mit |
TokiSeven/schoolMIPS | board/marsohod_3/marsohod_3.v | 1,297 | module MODULE1(
input VAR20,
input VAR16,
input VAR19,
output [7:0] VAR18,
output [12:1] VAR14
);
wire clk;
wire VAR8 = VAR20;
wire VAR10 = VAR16;
wire VAR7 = ~VAR19;
wire [ 31:0 ] VAR13;
VAR2 VAR2
(
.VAR8 ( VAR8 ),
.VAR10 ( VAR10 ),
.VAR17 ( 4'b1000 ),
.VAR7 ( VAR7 ),
.clk ( clk ),
.VAR5 ( 4'b0010 ),
.VAR13 ( VAR13 )
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxtn/sky130_fd_sc_ms__dlxtn.functional.pp.v | 1,777 | module MODULE1 (
VAR3 ,
VAR13 ,
VAR10,
VAR1 ,
VAR7 ,
VAR9 ,
VAR4
);
output VAR3 ;
input VAR13 ;
input VAR10;
input VAR1 ;
input VAR7 ;
input VAR9 ;
input VAR4 ;
wire VAR2 ;
wire VAR5;
not VAR8 (VAR2 , VAR10 );
VAR6 VAR11 (VAR5 , VAR13, VAR2, , VAR1, VAR7);
buf VAR12 (VAR3 , VAR5 );
endmodule | apache-2.0 |
keith-epidev/VHDL-lib | top/lab_7/part_3/ip/xfft/xfft_stub.v | 2,436 | module MODULE1(VAR15, VAR1, VAR4, VAR19, VAR17, VAR16, VAR9, VAR5, VAR10, VAR14, VAR11, VAR7, VAR12, VAR6, VAR18, VAR3, VAR13, VAR8, VAR2)
;
input VAR15;
input [7:0]VAR1;
input VAR4;
output VAR19;
input [31:0]VAR17;
input VAR16;
output VAR9;
input VAR5;
output [63:0]VAR10;
output [15:0]VAR14;
output VAR11;
input VAR7;
... | gpl-2.0 |
JeremySavonet/Eurobot-2017-Moon-Village | software/custom_leds/fpga/soc_system/synthesis/submodules/altera_jtag_streaming.v | 26,252 | module MODULE1 #(
parameter VAR34 = 0,
parameter VAR38 = 0,
parameter VAR65 = 0,
parameter VAR52 = -1
) (
input wire VAR33,
input wire VAR109,
output reg VAR94,
input wire [2:0] VAR24,
input wire VAR103,
input wire VAR30,
input wire VAR49,
input wire VAR70,
output wire [7:0] VAR71,
output wire VAR92,
input wire [7:0] V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and4b/sky130_fd_sc_hs__and4b.symbol.v | 1,287 | module MODULE1 (
input VAR7,
input VAR1 ,
input VAR4 ,
input VAR2 ,
output VAR3
);
supply1 VAR5;
supply0 VAR6;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkinv/sky130_fd_sc_lp__clkinv_8.v | 2,036 | module MODULE2 (
VAR5 ,
VAR1 ,
VAR3,
VAR2,
VAR6 ,
VAR8
);
output VAR5 ;
input VAR1 ;
input VAR3;
input VAR2;
input VAR6 ;
input VAR8 ;
VAR7 VAR4 (
.VAR5(VAR5),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR5,
VAR1
);
output VAR5;
input VAR1;
supply1 VAR3;
supply0 VAR2;... | apache-2.0 |
ptracton/wb_soc_template | rtl/ZIP/rtl/pfcache.v | 9,666 | module MODULE1(VAR33, VAR12, VAR27, VAR13,
VAR53, VAR51, VAR34, VAR26, VAR11,
VAR7, VAR52, VAR35, VAR19, VAR56,
VAR18, VAR23, VAR44, VAR31,
VAR43);
parameter VAR15 = 8, VAR6=24,
VAR4=5; localparam VAR49=(1<<VAR15); localparam VAR20=VAR15; localparam VAR39=VAR15-VAR4; localparam VAR55 = 32; localparam VAR22=VAR6; input ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlygate4sd3/sky130_fd_sc_ms__dlygate4sd3.functional.v | 1,309 | module MODULE1 (
VAR1,
VAR2
);
output VAR1;
input VAR2;
wire VAR5;
buf VAR4 (VAR5, VAR2 );
buf VAR3 (VAR1 , VAR5 );
endmodule | apache-2.0 |
mindrobots/P8X32A_Emulation | P8X32A_Nexys4/src/cog_vid.v | 5,096 | module MODULE1
(
input VAR29,
input VAR11,
input VAR10,
input VAR1,
input VAR15,
input [31:0] VAR18,
input [31:0] VAR34,
input [31:0] VAR27,
input [7:0] VAR17,
input VAR8,
output ack,
output [31:0] VAR32
);
reg [31:0] VAR31;
reg [31:0] VAR30;
always @(posedge VAR29 or negedge VAR10)
if (!VAR10)
VAR31 <= 32'b0;
else if ... | gpl-3.0 |
neale/CS-program | 474-VLSI/Lab_ADC/ADC_ROM.v | 6,400 | module MODULE1 (
address,
VAR44,
VAR50);
input [10:0] address;
input VAR44;
output [11:0] VAR50;
tri1 VAR44;
wire [11:0] VAR2;
wire [11:0] VAR50 = VAR2[11:0];
VAR33 VAR3 (
.VAR41 (address),
.VAR22 (VAR44),
.VAR38 (VAR2),
.VAR53 (1'b0),
.VAR49 (1'b0),
.VAR14 (1'b1),
.VAR24 (1'b0),
.VAR43 (1'b0),
.VAR28 (1'b1),
.VAR36 (1... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.v | 2,334 | module MODULE2 (
VAR4,
VAR5 ,
VAR6 ,
VAR9 ,
VAR3 ,
VAR1 ,
VAR8
);
input VAR4;
input VAR5 ;
input VAR6 ;
output VAR9 ;
output VAR3 ;
input VAR1 ;
input VAR8 ;
VAR2 VAR7 (
.VAR4(VAR4),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR4,
VAR5 ,
VAR6 ,
VAR9 ,
VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfstp/sky130_fd_sc_hdll__sdfstp.symbol.v | 1,506 | module MODULE1 (
input VAR9 ,
output VAR1 ,
input VAR7,
input VAR2 ,
input VAR8 ,
input VAR10
);
supply1 VAR5;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
merckhung/zet | cores/vdu/rtl/vdu_ram_2k_attr.v | 1,248 | module MODULE1 (
input clk,
input rst,
input VAR3,
input [10:0] addr,
output [ 7:0] VAR4,
input [ 7:0] VAR5
);
reg [ 7:0] VAR1[0:2047];
reg [10:0] VAR2;
always @(posedge clk)
begin
if (VAR3) VAR1[addr] <= VAR5;
VAR2 <= addr;
end
assign VAR4 = VAR1[VAR2]; | gpl-3.0 |
borti4938/sd2snes | verilog/sd2snes_gsu/dcm.v | 3,266 | module MODULE1 (
input VAR8,
output VAR33,
output VAR39,
input VAR41,
output[7:0] VAR6
);
VAR30 #(
.VAR21("VAR17"), .VAR1(2.0), .VAR4(7), .VAR25(25), .VAR18("VAR40"), .VAR22(41.667), .VAR7("VAR2"), .VAR23("VAR2"), .VAR19("VAR37"), .VAR11("VAR32"), .VAR10("VAR32"), .VAR14("VAR26"), .VAR36(16'hFFFF), .VAR15(0), .VAR34("V... | gpl-2.0 |
ZenoFuturista/fpga-shovel-and-pickaxe | verilog/sha_miner/hmac.v | 29,461 | module MODULE2(input clk, input VAR55, input [7:0] VAR15, input [7:0] in[0:79], input [31:0] VAR63, output reg[7:0] VAR82[0:127], output reg[31:0] VAR54, output reg[31:0] VAR61, output reg[31:0] VAR88[0:7], output reg VAR77);
parameter VAR7 = 64;
wire [31:0] VAR50 [0:7];
assign VAR50 = '{32'h6a09e667, 32'hbb67ae85, 32'... | apache-2.0 |
dbousias/RoachSweeper | Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/Mem/Mem_stub.v | 1,331 | module MODULE1(VAR5, VAR4, VAR6, clk, VAR3, VAR1, VAR2)
;
input [8:0]VAR5;
input [4:0]VAR4;
input [8:0]VAR6;
input clk;
input VAR3;
output [4:0]VAR1;
output [4:0]VAR2;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi.functional.v | 1,626 | module MODULE1 (
VAR7 ,
VAR1,
VAR8,
VAR6 ,
VAR2
);
output VAR7 ;
input VAR1;
input VAR8;
input VAR6 ;
input VAR2 ;
wire VAR9 ;
wire VAR10 ;
wire VAR5;
and VAR4 (VAR9 , VAR6, VAR2 );
nor VAR12 (VAR10 , VAR1, VAR8 );
nor VAR3 (VAR5, VAR10, VAR9);
buf VAR11 (VAR7 , VAR5 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.v | 2,334 | module MODULE1 (
VAR9 ,
VAR7 ,
VAR10 ,
VAR3 ,
VAR4 ,
VAR5 ,
VAR8,
VAR1
);
output VAR9 ;
input VAR7 ;
input VAR10 ;
input VAR3 ;
input VAR4 ;
input VAR5 ;
input VAR8;
input VAR1;
VAR2 VAR6 (
.VAR9(VAR9),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR1(VAR1)
);
endmodule
module MODUL... | apache-2.0 |
loonquawl/fermiac | fifo/fifo.v | 1,415 | module MODULE1
parameter VAR4=32,
parameter VAR13=32,
parameter VAR5=1
)
(
input [VAR4-1:0] VAR7 ,
output [VAR4-1:0] VAR10 ,
input clk ,
input VAR6 ,
input VAR3 ,
input VAR1 ,
output VAR11 ,
output VAR8
);
reg [VAR4-1:0] VAR9[VAR13];
reg [9:0] VAR12=0;
assign VAR10=VAR9[0];
assign VAR11=VAR12==VAR13;
assign VAR8=VAR12=... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/buflp/sky130_fd_sc_lp__buflp.pp.symbol.v | 1,257 | module MODULE1 (
input VAR6 ,
output VAR4 ,
input VAR1 ,
input VAR2,
input VAR5,
input VAR3
);
endmodule | apache-2.0 |
buserror/xc3sprog | bscan_spi/bscan_s6_spi_isf_ext.v | 1,239 | module MODULE1
(
output wire VAR45,
output wire VAR8,
output wire VAR34,
input VAR18
);
wire VAR36;
wire VAR12;
wire VAR24;
wire VAR7;
reg [47:0] VAR10;
reg [15:0] VAR25;
reg VAR19 = 0;
assign VAR45 = VAR24 ;
wire VAR16;
wire VAR1;
wire VAR21;
reg VAR29 = 0;
reg VAR15 = 0;
reg VAR28 = 0;
reg VAR30 = 0;
reg [13:0] VAR37... | gpl-2.0 |
monotone-RK/FACE | IEICE-Trans/data_compression/4-way_2-tree/src/ip_pcie/PCIeGen2x8If128_stub.v | 7,253 | module MODULE1(VAR17, VAR57, VAR11, VAR24, VAR18, VAR47, VAR40, VAR16, VAR41, VAR79, VAR28, VAR65, VAR59, VAR63, VAR49, VAR42, VAR61, VAR12, VAR33, VAR85, VAR84, VAR32, VAR23, VAR3, VAR50, VAR39, VAR52, VAR72, VAR81, VAR6, VAR43, VAR9, VAR86, VAR66, VAR58, VAR25, VAR35, VAR73, VAR76, VAR8, VAR64, VAR30, VAR70, VAR62, V... | mit |
zhijian-liu/mips-cpu | src/sopc.v | 1,728 | module MODULE1(
input VAR12,
input reset
);
wire VAR13 ;
wire [31:0] VAR14;
wire [31:0] VAR26 ;
wire VAR3 ;
wire VAR2 ;
wire [31:0] VAR20 ;
wire [31:0] VAR22 ;
wire VAR6 ;
wire [31:0] VAR10;
wire [ 3:0] VAR11 ;
wire [31:0] VAR4 ;
VAR7 VAR7(
.VAR12 (VAR12 ),
.reset (reset ),
.VAR14 (VAR14 ),
.VAR26 (VAR26 ),
.VAR2 (VAR2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/ebufn/sky130_fd_sc_lp__ebufn.functional.v | 1,216 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR4
);
output VAR3 ;
input VAR1 ;
input VAR4;
bufif0 VAR2 (VAR3 , VAR1, VAR4 );
endmodule | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_du.v | 45,489 | module MODULE1(
clk, rst,
VAR173, VAR4, VAR7, VAR2,
VAR186, VAR147,
VAR114, VAR191, VAR165, VAR1,
VAR193, VAR192,
VAR217, VAR90, VAR40, VAR125, VAR150,
VAR76, VAR92, VAR162, VAR101,
VAR97, VAR179, VAR102, VAR127, VAR154,
VAR151, VAR66, VAR25, VAR99, VAR42, VAR197,
VAR78, VAR188, VAR140, VAR113, VAR163, VAR135
);
parame... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/yf32/reg_bank.v | 6,725 | module MODULE1 (clk, reset, VAR13, VAR5, VAR14, VAR20,
VAR4, VAR27, VAR6, VAR25);
input clk;
input reset;
input VAR13;
input [ 5:0] VAR5;
input [ 5:0] VAR14;
input [ 5:0] VAR20;
input [31:0] VAR6;
output [31:0] VAR4;
output [31:0] VAR27;
output VAR25;
reg [31:0] VAR27;
reg [31:0] VAR4;
reg VAR21;
wire VAR25 = VAR21 ;
r... | mit |
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