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Datasets:
OvertureMMXXI
/
HDL-RepoBench-Sample
like
0
Tasks:
Text Generation
Languages:
code
Size:
1K<n<10K
Tags:
hardware
verilog
systemverilog
vhdl
chisel
hls
+ 1
License:
other
Dataset card
Data Studio
Files
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xet
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main
HDL-RepoBench-Sample
228 MB
1 contributor
History:
2 commits
OvertureMMXXI
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d6720f3
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1 day ago
chisel
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hls
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original_repo
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systemverilog
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vhdl
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.gitattributes
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README.md
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897 Bytes
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sample_manifest.json
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source_readme
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