Datasets:
Upload HDL-RepoBench sample
Browse files- .gitattributes +2 -1
- README.md +35 -0
- chisel/test.jsonl +0 -0
- chisel/test_content_classfied.jsonl +0 -0
- chisel/train.jsonl +0 -0
- chisel/train_content.jsonl +0 -0
- chisel/valid.jsonl +119 -0
- chisel/valid_content.jsonl +0 -0
- hls/test.jsonl +3 -0
- hls/test_content_classfied.jsonl +3 -0
- hls/train.jsonl +0 -0
- hls/train_content.jsonl +0 -0
- hls/valid.jsonl +123 -0
- hls/valid_content.jsonl +3 -0
- original_repo/README.md +3 -0
- sample_manifest.json +190 -0
- source_readme +1 -0
- systemverilog/test.jsonl +0 -0
- systemverilog/test_content_classfied.jsonl +3 -0
- systemverilog/train.jsonl +0 -0
- systemverilog/train_content.jsonl +0 -0
- systemverilog/valid.jsonl +107 -0
- systemverilog/valid_content.jsonl +0 -0
- vhdl/test.jsonl +0 -0
- vhdl/test_content_classfied.jsonl +3 -0
- vhdl/train.jsonl +0 -0
- vhdl/train_content.jsonl +3 -0
- vhdl/valid.jsonl +104 -0
- vhdl/valid_content.jsonl +0 -0
.gitattributes
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*.7z filter=lfs diff=lfs merge=lfs -text
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*.arrow filter=lfs diff=lfs merge=lfs -text
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-
*.avro filter=lfs diff=lfs merge=lfs -text
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*.bin filter=lfs diff=lfs merge=lfs -text
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*.bz2 filter=lfs diff=lfs merge=lfs -text
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*.ckpt filter=lfs diff=lfs merge=lfs -text
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# Video files - compressed
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*.mp4 filter=lfs diff=lfs merge=lfs -text
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*.webm filter=lfs diff=lfs merge=lfs -text
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*.7z filter=lfs diff=lfs merge=lfs -text
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*.arrow filter=lfs diff=lfs merge=lfs -text
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*.bin filter=lfs diff=lfs merge=lfs -text
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*.bz2 filter=lfs diff=lfs merge=lfs -text
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*.ckpt filter=lfs diff=lfs merge=lfs -text
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# Video files - compressed
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*.mp4 filter=lfs diff=lfs merge=lfs -text
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*.webm filter=lfs diff=lfs merge=lfs -text
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*.jsonl filter=lfs diff=lfs merge=lfs -text
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.gz filter=lfs diff=lfs merge=lfs -text
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README.md
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---
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license: other
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task_categories:
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- text-generation
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language:
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- code
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tags:
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- hardware
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- verilog
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- systemverilog
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- vhdl
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- chisel
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- hls
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- code-completion
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size_categories:
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- 1K<n<10K
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---
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# HDL-RepoBench Sample
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This is a compact, deterministic sample of MHRC-Bench for lightweight
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inspection and upload tests. It preserves the original language directories and
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JSONL file names while keeping the output below 2 GB.
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Sampling policy:
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- Languages: chisel, hls, systemverilog, vhdl.
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- Validation and test splits: copied in full by default.
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- Training split: repository-stratified deterministic sample.
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- Raw repository archive: omitted because `original_repo/collected_repos.tar.gz`
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is about 33 GB in the source dataset.
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This generated sample contains 6,537 JSONL records and occupies
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217.0 MiB on disk. See `sample_manifest.json` for exact
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per-file counts, byte sizes, and generation arguments.
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chisel/test.jsonl
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chisel/test_content_classfied.jsonl
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chisel/train.jsonl
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chisel/train_content.jsonl
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chisel/valid.jsonl
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{"file": "CGRAs/src/main/scala/Alu.scala", "target_type": "function_definition", "cursor_line": 43, "target_nlines": 1, "node_depth": 2, "node_path": ["compilation_unit", "block", "function_definition"], "target": " def AND = 6.U // And \n"}
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{"file": "CGRAs/src/main/scala/CellProcessing.scala", "target_type": "class_definition", "cursor_line": 149, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " joinDin2Valid := eb2.io.doutValid\n"}
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{"file": "CGRAs/src/main/scala/ConfMux.scala", "target_type": "object_definition", "cursor_line": 69, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object ConfMuxMain extends App {\n println(\"Generating the hardware\")\n (new chisel3.stage.ChiselStage).emitVerilog(new ConfMux(2, 1), Array(\"--target-dir\", \"generated\"))\n}\n"}
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{"file": "CGRAs/src/main/scala/DEb.scala", "target_type": "class_definition", "cursor_line": 79, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " io.dout := regDin1\n"}
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{"file": "CGRAs/src/main/scala/DFifo.scala", "target_type": "class_definition", "cursor_line": 37, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class DFifo\n"}
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{"file": "CGRAs/src/main/scala/DFifoImp.scala", "target_type": "class_definition", "cursor_line": 43, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " extends BlackBox(Map(\"dataWidth\" -> dataWidth, \"fifoDepth\" -> fifoDepth)) with HasBlackBoxResource{ \n val io = IO(new Bundle {\n"}
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{"file": "CGRAs/src/main/scala/DReg.scala", "target_type": "block", "cursor_line": 56, "target_nlines": 4, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when (io.doutReady === true.B) {\n data := io.din\n valid := io.dinValid\n } \n"}
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{"file": "CGRAs/src/main/scala/Fr.scala", "target_type": "class_definition", "cursor_line": 36, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class Fr \n"}
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{"file": "CGRAs/src/main/scala/Fs.scala", "target_type": "object_definition", "cursor_line": 70, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object FsMain extends App {\n println(\"Generating the hardware\")\n (new chisel3.stage.ChiselStage).emitVerilog(new Fs(5), Array(\"--target-dir\", \"generated\"))\n} \n"}
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{"file": "CGRAs/src/main/scala/Fu.scala", "target_type": "function_definition", "cursor_line": 44, "target_nlines": 1, "node_depth": 2, "node_path": ["compilation_unit", "block", "function_definition"], "target": " def STATE_0 = 0.U(2.W) // 00\n"}
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{"file": "CGRAs/src/main/scala/Join.scala", "target_type": "object_definition", "cursor_line": 71, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object JoinMain extends App {\n println(\"Generating the hardware\")\n (new chisel3.stage.ChiselStage).emitVerilog(new Join(32), Array(\"--target-dir\", \"generated\"))\n}\n"}
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{"file": "CGRAs/src/main/scala/OverlayRocc.scala", "target_type": "block", "cursor_line": 97, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when (io.cellConfig(191) === 1.U){\n catchConfig(unsignedCellConfig) := 1.B \n }\n"}
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{"file": "CGRAs/src/main/scala/ProcessingElement.scala", "target_type": "class_definition", "cursor_line": 36, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class ProcessingElement \n"}
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| 14 |
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{"file": "CGRAs/src/test/scala/AluTest.scala", "target_type": "block", "cursor_line": 144, "target_nlines": 5, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block", "lambda_expression", "indented_block", "for_expression", "block"], "target": " for (i <- 1 until numOfTests) {\n dut.io.din1.poke((-(i*2)).S)\n dut.io.din2.poke(i.S)\n dut.clock.step(1)\n }\n"}
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| 15 |
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{"file": "CGRAs/src/test/scala/CellProcessingTest.scala", "target_type": "class_definition", "cursor_line": 70, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " dut.io.eastDinValid.poke(eastDinValid)\n\n dut.io.southDin.poke(southDin)\n dut.io.southDinValid.poke(southDinValid)\n"}
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| 16 |
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{"file": "CGRAs/src/test/scala/ConfMuxTest.scala", "target_type": "block", "cursor_line": 51, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " dut.clock.step(1)\n selector = 2\n muxInput = 53\n"}
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| 17 |
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{"file": "CGRAs/src/test/scala/DEbTest.scala", "target_type": "block", "cursor_line": 123, "target_nlines": 5, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block"], "target": " println(\"An: \" + dut.io.doutReady.peek().toString)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.io.dinValid.poke(false.B)\n dut.clock.step(1)\n"}
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| 18 |
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{"file": "CGRAs/src/test/scala/DFifoTest.scala", "target_type": "block", "cursor_line": 49, "target_nlines": 2, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block", "lambda_expression", "indented_block", "for_expression", "block"], "target": " dut.io.din.poke(i.S) \n dut.io.dinValid.poke(true.B)\n"}
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| 19 |
+
{"file": "CGRAs/src/test/scala/DRegTest.scala", "target_type": "block", "cursor_line": 41, "target_nlines": 2, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " var doutReady = false.B\n var dinValid = false.B \n"}
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| 20 |
+
{"file": "CGRAs/src/test/scala/FrTest.scala", "target_type": "block", "cursor_line": 40, "target_nlines": 5, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block"], "target": " \n var validIn = \"b11011\".U \n var readyOut = \"b11011\".U \n var validMuxSel = \"b10\".U \n var forkMask = \"b11011\".U \n"}
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| 21 |
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{"file": "CGRAs/src/test/scala/FsTest.scala", "target_type": "block", "cursor_line": 40, "target_nlines": 3, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block"], "target": " \n dut.io.readyOut.poke(\"b00000\".U)\n dut.io.forkMask.poke(\"b00000\".U)\n"}
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| 22 |
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{"file": "CGRAs/src/test/scala/FuTest.scala", "target_type": "identifier", "cursor_line": 268, "target_nlines": 1, "node_depth": 13, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block", "lambda_expression", "indented_block", "call_expression", "field_expression", "field_expression", "field_expression", "identifier"], "target": " dut.io.dinValid.poke(dinValid)\n"}
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| 23 |
+
{"file": "CGRAs/src/test/scala/JoinTest.scala", "target_type": "block", "cursor_line": 79, "target_nlines": 5, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block"], "target": " println(\"*************************************\")\n println(\"Test 1: Vin1: true, Vin2: false, Aout: false\")\n println(\"*************************************\")\n din1Valid = true.B\n din2Valid = false.B \n"}
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| 24 |
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{"file": "CGRAs/src/test/scala/OverlayRoccTestACC.scala", "target_type": "class_definition", "cursor_line": 49, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " dut.io.dataOutReady.poke(dataOutReady)\n dut.clock.step(1)\n\n var cellConfig: UInt = 0.U \n \n"}
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| 25 |
+
{"file": "CGRAs/src/test/scala/OverlayRoccTestCAP.scala", "target_type": "block", "cursor_line": 116, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " dut.io.dataInValid.poke(\"b100001\".U)\n"}
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| 26 |
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{"file": "CGRAs/src/test/scala/OverlayRoccTestMAC.scala", "target_type": "class_definition", "cursor_line": 90, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " for (i <- 1 to 101) {\n // ------------------------------------------------------------------------------------------------\n"}
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| 27 |
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{"file": "CGRAs/src/test/scala/OverlayRoccTestMAC2.scala", "target_type": "block", "cursor_line": 91, "target_nlines": 5, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block", "lambda_expression", "indented_block", "for_expression", "block"], "target": " for (i <- 1 to 16) {\n // ------------------------------------------------------------------------------------------------\n // | | C5 | C4 | C3 | C2 | C1 | C0 |\n // ------------------------------------------------------------------------------------------------\n // ------------------------------------------------------------------------------------------------\n"}
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| 28 |
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{"file": "CGRAs/src/test/scala/OverlayRoccTestSUM.scala", "target_type": "block", "cursor_line": 124, "target_nlines": 3, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block", "lambda_expression", "indented_block", "for_expression", "block"], "target": " for( i <- 0 to 10){\n dut.clock.step(1)\n } \n"}
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| 29 |
+
{"file": "CGRAs/src/test/scala/ProcessingElementTest.scala", "target_type": "function_definition", "cursor_line": 40, "target_nlines": 1, "node_depth": 2, "node_path": ["compilation_unit", "block", "function_definition"], "target": " def FIFO_DEPTH = 32 \n"}
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| 30 |
+
{"file": "tywaves-chisel/example/detect2ones.test.scala", "target_type": "block", "cursor_line": 37, "target_nlines": 1, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "call_expression", "field_expression", "call_expression", "block"], "target": " when(isOne) { state := State.sTwo1s }.otherwise { state := State.sNone } \n"}
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| 31 |
+
{"file": "tywaves-chisel/example/gcd.test.scala", "target_type": "block", "cursor_line": 43, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when(io.loadValues) { x := io.a; y := io.b }\n"}
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| 32 |
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{"file": "tywaves-chisel/example/myfsm.test.scala", "target_type": "block", "cursor_line": 90, "target_nlines": 3, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "call_expression", "block"], "target": " fsm.clock.step(10)\n fsm.io.inputState.poke(MyFSMStates.StateA)\n fsm.clock.step(10)\n"}
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| 33 |
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{"file": "tywaves-chisel/example/tydi-example-meaningfulnames.test.scala", "target_type": "class_definition", "cursor_line": 82, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class Generated_0_7_d3p7qsW3_29 extends BitsEl(64.W)\n"}
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| 34 |
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{"file": "tywaves-chisel/example/tydi-example.test.scala", "target_type": "function_definition", "cursor_line": 25, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition"], "target": " def generated_0_7_Tc5SbYQz_27 = UInt(64.W)\n"}
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| 35 |
+
{"file": "tywaves-chisel/src/main/scala/tywaves/circuitmapper/TypedConverter.scala", "target_type": "function_definition", "cursor_line": 83, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition"], "target": " def getTopModuleName: Option[String] = topModuleName.name\n"}
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| 36 |
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{"file": "tywaves-chisel/src/main/scala/tywaves/simulator/ParametricSimulator.scala", "target_type": "function_definition", "cursor_line": 63, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " def getFirtoolArgs: Seq[String] = _firtoolArgs\n"}
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| 37 |
+
{"file": "tywaves-chisel/src/main/scala/tywaves/simulator/ParametricSimulatorInterface.scala", "target_type": "function_definition", "cursor_line": 14, "target_nlines": 5, "node_depth": 3, "node_path": ["compilation_unit", "trait_definition", "template_body", "function_definition"], "target": " settings: Seq[SimulatorSettings] = Seq(),\n simName: String = \"defaultSimulation\",\n )(body: T => Unit): Unit = {\n if (_resetSimulationBeforeRun)\n reset()\n"}
|
| 38 |
+
{"file": "tywaves-chisel/src/main/scala/tywaves/simulator/SimulatorSettings.scala", "target_type": "class_definition", "cursor_line": 38, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "private[simulator] case class FirtoolArgs(args: Seq[String]) extends SimulatorSettings\n"}
|
| 39 |
+
{"file": "tywaves-chisel/src/main/scala/tywaves/simulator/TywavesInterface.scala", "target_type": "block", "cursor_line": 21, "target_nlines": 3, "node_depth": 5, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition", "block", "block"], "target": " if (exitCode != 0)\n throw new Exception(s\"$program not found on the PATH! Please install it running: make all\\n\")\n }\n"}
|
| 40 |
+
{"file": "tywaves-chisel/src/main/scala/tywaves/simulator/TywavesSimulator.scala", "target_type": "class_definition", "cursor_line": 10, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "class_definition"], "target": " private[simulator] case class Tywaves(runWaves: Boolean, waitFor: Boolean) extends SimulatorSettings\n"}
|
| 41 |
+
{"file": "tywaves-chisel/src/main/scala/tywaves/utils/UniqueHashMap.scala", "target_type": "block", "cursor_line": 40, "target_nlines": 5, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block"], "target": " this.foreach { case (key, value) =>\n bw.write(s\"$key: $value\\n\")\n }\n bw.close()\n }\n"}
|
| 42 |
+
{"file": "tywaves-chisel/src/test/scala/GetNameTest.scala", "target_type": "class_definition", "cursor_line": 5, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class MyBundle extends Bundle\n"}
|
| 43 |
+
{"file": "tywaves-chisel/src/test/scala/bar/Bar.scala", "target_type": "class_definition", "cursor_line": 29, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "\n val cable =\n Wire(Bool()) // do not use reserved verilog words as val names (val wire) -> tywaves-demo does not work for them yet\n cable := io.a & io.b\n\n"}
|
| 44 |
+
{"file": "tywaves-chisel/src/test/scala/bar/BarTest.scala", "target_type": "block", "cursor_line": 48, "target_nlines": 2, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block"], "target": " c.io.out.expect(true.B)\n\n"}
|
| 45 |
+
{"file": "tywaves-chisel/src/test/scala/foo/Foo.scala", "target_type": "class_definition", "cursor_line": 6, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class Simple extends Bundle\n"}
|
| 46 |
+
{"file": "tywaves-chisel/src/test/scala/foo/FooTest.scala", "target_type": "block", "cursor_line": 34, "target_nlines": 4, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " simulate(new Foo, Seq(VcdTraceWithUnderscore), simName = \"trace_with_underscore\") {\n println(\"Running test: \" + it)\n RunFoo(_)\n }\n"}
|
| 47 |
+
{"file": "tywaves-chisel/src/test/scala/gcd/GCD.scala", "target_type": "block", "cursor_line": 20, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when(io.loadValues) { x := io.a; y := io.b }\n"}
|
| 48 |
+
{"file": "tywaves-chisel/src/test/scala/gcd/GCDTest.scala", "target_type": "block", "cursor_line": 15, "target_nlines": 2, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "call_expression", "block"], "target": " gcd.io.a.poke(24.U)\n gcd.io.b.poke(36.U)\n"}
|
| 49 |
+
{"file": "tywaves-chisel/src/test/scala/hierarchicalmodules/Blink.scala", "target_type": "class_definition", "cursor_line": 16, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " when(io.enable) {\n when(cnt.inc() && cnt.value === (period - 1).U) {\n ledReg := ~ledReg\n }\n }\n"}
|
| 50 |
+
{"file": "tywaves-chisel/src/test/scala/hierarchicalmodules/BlinkTest.scala", "target_type": "block", "cursor_line": 56, "target_nlines": 4, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " simName = \"blink_with_tywaves_sim_should_work\",\n ) { dut =>\n blinkTb(dut)\n }\n"}
|
| 51 |
+
{"file": "tywaves-chisel/src/test/scala/hierarchicalmodules/MultiBlink.scala", "target_type": "object_definition", "cursor_line": 52, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": " ChiselStage.emitSystemVerilog(\n new AMultiBlink,\n firtoolOpts = Array(\n \"-O=debug\",\n \"-g\",\n"}
|
| 52 |
+
{"file": "tywaves-chisel/src/test/scala/hierarchicalmodules/MultiBlinkTest.scala", "target_type": "class_definition", "cursor_line": 21, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " dut.clock.step() // 5\n dut.clock.step() // 6\n dut.clock.step()\n"}
|
| 53 |
+
{"file": "tywaves-chisel/src/test/scala/hierarchicalmodules/UseCounter.scala", "target_type": "function_definition", "cursor_line": 14, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "class_definition", "template_body", "class_definition", "template_body", "function_definition"], "target": " def apply: UInt = value\n"}
|
| 54 |
+
{"file": "tywaves-chisel/src/test/scala/memories/BlockMem.scala", "target_type": "class_definition", "cursor_line": 12, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val wrAddr = Input(UInt(log2Ceil(depth).W))\n}\n"}
|
| 55 |
+
{"file": "tywaves-chisel/src/test/scala/memories/BlockMemTest.scala", "target_type": "object_definition", "cursor_line": 76, "target_nlines": 1, "node_depth": 7, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "object_definition"], "target": " object SelType extends ChiselEnum { val A, B, C = Value }\n"}
|
| 56 |
+
{"file": "tywaves-chisel/src/test/scala/tywaves/simulator/ImportSimulatorReverseOrder.scala", "target_type": "class_definition", "cursor_line": 8, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " describe(\"Issue 27\") {\n it(\"Should import chisel before tywaves\") {\n import chisel3._\n import tywaves.simulator.TywavesSimulator._\n"}
|
| 57 |
+
{"file": "tywaves-chisel/src/test/scala/tywaves/simulator/ParametricSimulatorSpec.scala", "target_type": "block", "cursor_line": 73, "target_nlines": 4, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block"], "target": " it(\"save the workdir with a name\") {\n simulate(new GCD(), Seq(VcdTrace, SaveWorkdirFile(\"myWorkdir\")))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/ParametricSimulator/defaultSimulation/myWorkdir\")))\n }\n"}
|
| 58 |
+
{"file": "tywaves-chisel/src/test/scala/tywaves/simulator/TywavesSimulatorSpec.scala", "target_type": "block", "cursor_line": 107, "target_nlines": 4, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block"], "target": " simulate(new GCD(), Seq(VcdTrace, NameTrace(\"gcdTb1\")), simName = \"use_a_name_for_the_simulation\")(gcd =>\n gcdTb(gcd)\n )\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/TywavesSimulator/use_a_name_for_the_simulation/gcdTb1.vcd\")))\n"}
|
| 59 |
+
{"file": "an-ethernet-controller/src/main/scala/ethcontroller/design/EthRxController.scala", "target_type": "block", "cursor_line": 128, "target_nlines": 2, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "for_expression", "block"], "target": " ramMasterRegs(ramId).Cmd := RegNext(Mux(ramId.U === wrRamIdReg && ocpSelRam, OcpCmd.WR, Mux(ocpRamRdEn, OcpCmd.RD, OcpCmd.IDLE)))\n ramMasterRegs(ramId).Data := RegNext(ethByteReg)\n"}
|
| 60 |
+
{"file": "an-ethernet-controller/src/main/scala/ethcontroller/design/EthTxController.scala", "target_type": "block", "cursor_line": 201, "target_nlines": 3, "node_depth": 25, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "field_expression", "call_expression", "call_expression", "field_expression", "call_expression", "block", "call_expression", "call_expression", "field_expression", "call_expression", "call_expression", "field_expression", "call_expression", "call_expression", "field_expression", "call_expression", "call_expression", "field_expression", "call_expression", "block"], "target": " }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"fifoEmpty\")(\"Addr\")) {\n ocpDataReg := ethTxCtrlRegMap(\"fifoEmpty\")(\"Reg\")\n }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"fifoFull\")(\"Addr\")) {\n"}
|
| 61 |
+
{"file": "an-ethernet-controller/src/main/scala/ethcontroller/design/MIIRx.scala", "target_type": "class_definition", "cursor_line": 79, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " eofReg := true.B\n"}
|
| 62 |
+
{"file": "an-ethernet-controller/src/main/scala/ethcontroller/design/MIITx.scala", "target_type": "block", "cursor_line": 48, "target_nlines": 3, "node_depth": 7, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "call_expression", "field_expression", "call_expression", "block"], "target": " when(~transmittingReg && serializeByteToNibble.io.dv) {\n transmittingReg := true.B\n }.elsewhen(~serializeByteToNibble.io.dv && serializeByteToNibble.io.done) {\n"}
|
| 63 |
+
{"file": "an-ethernet-controller/src/main/scala/ethcontroller/interfaces/MIIChannel.scala", "target_type": "class_definition", "cursor_line": 9, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val clk = Bool(INPUT)\n /** Received data valid */\n"}
|
| 64 |
+
{"file": "an-ethernet-controller/src/main/scala/ethcontroller/interfaces/PHYChannel.scala", "target_type": "class_definition", "cursor_line": 12, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " /** Management input data */\n val mdi = Bool(INPUT)\n"}
|
| 65 |
+
{"file": "an-ethernet-controller/src/main/scala/ethcontroller/protocols/EthernetConstants.scala", "target_type": "object_definition", "cursor_line": 13, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": " val constVLANt1 = Bits(\"h8100\", width = 16)\n"}
|
| 66 |
+
{"file": "an-ethernet-controller/src/main/scala/ethcontroller/protocols/EthernetFrame.scala", "target_type": "function_definition", "cursor_line": 38, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " def ethTypeNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(ethType, msbFirst = false)\n"}
|
| 67 |
+
{"file": "an-ethernet-controller/src/main/scala/ethcontroller/protocols/EthernetUtils.scala", "target_type": "function_definition", "cursor_line": 49, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition"], "target": " def toBytes(xs: Int*) = xs.map(_.toByte).toArray\n"}
|
| 68 |
+
{"file": "an-ethernet-controller/src/main/scala/ethcontroller/utils/Deserializer.scala", "target_type": "block", "cursor_line": 32, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " } else {\n shiftReg(outputWidth - inputWidth - 1, 0) := shiftReg(outputWidth - 1, inputWidth)\n shiftReg(outputWidth - 1, outputWidth - inputWidth) := io.shiftIn\n"}
|
| 69 |
+
{"file": "an-ethernet-controller/src/main/scala/ethcontroller/utils/ExtClockSampler.scala", "target_type": "class_definition", "cursor_line": 24, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "\n if (sampleRisingEdge) {\n extClkEdge := extClkSyncedReg & ~extClkSyncedOldReg //check for a rising edge\n } else {\n extClkEdge := ~extClkSyncedReg & extClkSyncedOldReg //or check for a falling edge\n"}
|
| 70 |
+
{"file": "an-ethernet-controller/src/main/scala/ethcontroller/utils/Serializer.scala", "target_type": "block", "cursor_line": 42, "target_nlines": 5, "node_depth": 7, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "call_expression", "field_expression", "call_expression", "block"], "target": " }.otherwise {\n countReg := countReg - 1.U\n doneReg := false.B\n }\n }.elsewhen(doneReg) {\n"}
|
| 71 |
+
{"file": "an-ethernet-controller/src/main/scala/ocp/Arbiter.scala", "target_type": "block", "cursor_line": 47, "target_nlines": 2, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "field_expression", "call_expression", "block"], "target": " stateReg := sWrite\n burstCntReg := UInt(0)\n"}
|
| 72 |
+
{"file": "an-ethernet-controller/src/main/scala/ocp/NodeTdmArbiter.scala", "target_type": "function_definition", "cursor_line": 60, "target_nlines": 3, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " def slotTable(i: Int): UInt = {\n (cntReg === UInt(i * slotLen)).toUInt\n }\n"}
|
| 73 |
+
{"file": "an-ethernet-controller/src/main/scala/ocp/Ocp.scala", "target_type": "object_definition", "cursor_line": 14, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object OcpCmd {\n"}
|
| 74 |
+
{"file": "an-ethernet-controller/src/main/scala/ocp/OcpBurst.scala", "target_type": "block", "cursor_line": 255, "target_nlines": 5, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " for (i <- 0 until master.burstLength - 1) {\n MBuffer(i) := MBuffer(i + 1)\n }\n MBuffer(master.burstLength - 1) := master.M\n }\n"}
|
| 75 |
+
{"file": "an-ethernet-controller/src/main/scala/ocp/OcpCache.scala", "target_type": "class_definition", "cursor_line": 38, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class OcpCacheSlavePort(addrWidth: Int, dataWidth: Int) extends Bundle() {\n // Clk is implicit in Chisel\n val M = new OcpCacheMasterSignals(addrWidth, dataWidth).asInput\n val S = new OcpSlaveSignals(dataWidth).asOutput\n}\n"}
|
| 76 |
+
{"file": "an-ethernet-controller/src/main/scala/ocp/OcpCore.scala", "target_type": "class_definition", "cursor_line": 28, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "\n // This does not really clone, but Data.clone doesn't either\n override def clone() = {\n val res = new OcpCoreMasterPort(addrWidth, dataWidth)\n res.asInstanceOf[this.type]\n"}
|
| 77 |
+
{"file": "an-ethernet-controller/src/main/scala/ocp/OcpIO.scala", "target_type": "block", "cursor_line": 54, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when(masterReg.Cmd === OcpCmd.IDLE || slave.S.CmdAccept === Bits(1)) {\n masterReg := master.M\n }\n"}
|
| 78 |
+
{"file": "an-ethernet-controller/src/main/scala/ocp/OcpNI.scala", "target_type": "class_definition", "cursor_line": 17, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "\n // This does not really clone, but Data.clone doesn't either\n override def clone() = {\n val res = new OcpNISlaveSignals(dataWidth)\n"}
|
| 79 |
+
{"file": "an-ethernet-controller/src/main/scala/ocp/OcpTest.scala", "target_type": "block", "cursor_line": 44, "target_nlines": 4, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when(cnt =/= UInt(0)) {\n cnt := cnt - UInt(1)\n io.S.Resp := OcpResp.DVA\n }\n"}
|
| 80 |
+
{"file": "an-ethernet-controller/src/main/scala/ocp/TdmArbiter.scala", "target_type": "block", "cursor_line": 101, "target_nlines": 3, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "for_expression", "block", "call_expression", "block", "call_expression", "block"], "target": " when(io.slave.S.Resp === OcpResp.DVA) {\n stateReg(i) := sIdle\n }\n"}
|
| 81 |
+
{"file": "an-ethernet-controller/src/main/scala/ocp/TdmArbiterWrapper.scala", "target_type": "block", "cursor_line": 22, "target_nlines": 3, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "arguments", "instance_expression", "template_body", "val_definition", "call_expression", "block"], "target": " val master = Vec.fill(cnt) {\n new OcpBurstSlavePort(addrWidth, dataWidth, burstLen)\n }\n"}
|
| 82 |
+
{"file": "an-ethernet-controller/src/test/scala/ethcontroller/design/EthRxControllerTester.scala", "target_type": "block", "cursor_line": 59, "target_nlines": 4, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "for_expression", "block"], "target": " for (nibble <- frame.dstMacNibbles ++ frame.srcMacNibbles ++ frame.ethTypeNibbles) {\n txPHY2MIIData(nibble, 6)\n peekEthRxStatus()\n }\n"}
|
| 83 |
+
{"file": "an-ethernet-controller/src/test/scala/ethcontroller/design/EthTxControllerTester.scala", "target_type": "block", "cursor_line": 65, "target_nlines": 4, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "for_expression", "block", "if_expression", "block"], "target": " if (byteCnt == 8) {\n byteCnt = 1\n ocpAddr += 0x1\n } else {\n"}
|
| 84 |
+
{"file": "an-ethernet-controller/src/test/scala/ethcontroller/design/MIIRxTester.scala", "target_type": "class_definition", "cursor_line": 39, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " poke(dut.io.miiChannel.dv, 0)\n step(3)\n"}
|
| 85 |
+
{"file": "an-ethernet-controller/src/test/scala/ethcontroller/design/MIITxTester.scala", "target_type": "block", "cursor_line": 62, "target_nlines": 4, "node_depth": 4, "node_path": ["compilation_unit", "object_definition", "template_body", "try_expression", "block"], "target": " () => Module(new MIITx())) {\n dut => new MIITxTester(dut, EthernetTesting.mockupPTPEthFrameOverIpUDP)\n }\n } finally {\n"}
|
| 86 |
+
{"file": "an-ethernet-controller/src/test/scala/ethcontroller/protocols/EthernetTesting.scala", "target_type": "object_definition", "cursor_line": 82, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": " override val ptpSuffix: Array[Byte] = Array.emptyByteArray\n override val fcs: Array[Byte] = Array.emptyByteArray\n override val igp: Array[Byte] = Array.emptyByteArray\n"}
|
| 87 |
+
{"file": "an-ethernet-controller/src/test/scala/ethcontroller/utils/DeserializerTester.scala", "target_type": "block", "cursor_line": 16, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "for_expression", "block"], "target": " peek(dut.io.shiftOut)\n peek(dut.io.done)\n step(1)\n"}
|
| 88 |
+
{"file": "an-ethernet-controller/src/test/scala/ethcontroller/utils/SerializerTester.scala", "target_type": "block", "cursor_line": 41, "target_nlines": 3, "node_depth": 6, "node_path": ["compilation_unit", "object_definition", "template_body", "try_expression", "block", "call_expression", "block"], "target": " () => Module(new Serializer(false, 8, 4))) {\n dut => new SerializerTester(dut, EthernetTesting.mockupPTPEthFrameOverIpUDP)\n }\n"}
|
| 89 |
+
{"file": "chiselv/chiselv/src/ALU.scala", "target_type": "if_expression", "cursor_line": 18, "target_nlines": 1, "node_depth": 7, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "infix_expression", "parenthesized_expression", "if_expression", "if_expression"], "target": " val shamt = (if (bitWidth == 32) 5 else if (bitWidth == 64) 6 else 0) - 1\n"}
|
| 90 |
+
{"file": "chiselv/chiselv/src/Blink.scala", "target_type": "block", "cursor_line": 26, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when(counterWrap) {\n led := ~led\n }\n"}
|
| 91 |
+
{"file": "chiselv/chiselv/src/CPUSingleCycle.scala", "target_type": "block", "cursor_line": 190, "target_nlines": 4, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block"], "target": " when(decoder.io.inst === LW) {\n dataSize := 3.U\n dataOut := memoryIOManager.io.MemoryIOPort.readData\n }\n"}
|
| 92 |
+
{"file": "chiselv/chiselv/src/Constants.scala", "target_type": "object_definition", "cursor_line": 23, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object InstructionType extends ChiselEnum {\n val IN_ERR, INST_R, INST_I, INST_S, INST_B, INST_U, INST_J, INST_Z = Value\n}\n"}
|
| 93 |
+
{"file": "chiselv/chiselv/src/DataMemory.scala", "target_type": "if_expression", "cursor_line": 40, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "class_definition", "template_body", "if_expression", "block", "if_expression"], "target": " if (debugMsg) println(s\" Load memory file: \" + memoryFile)\n"}
|
| 94 |
+
{"file": "chiselv/chiselv/src/Decoder.scala", "target_type": "function_definition", "cursor_line": 147, "target_nlines": 4, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " case INST_R => 0.S\n case INST_I => Cat(Fill(20, inst(31)), inst(31, 20)).asSInt\n case INST_S => Cat(Fill(20, inst(31)), inst(31, 25), inst(11, 7)).asSInt\n case INST_B => Cat(Fill(19, inst(31)), inst(31), inst(7), inst(30, 25), inst(11, 8), 0.U(1.W)).asSInt\n"}
|
| 95 |
+
{"file": "chiselv/chiselv/src/GPIO.scala", "target_type": "block", "cursor_line": 68, "target_nlines": 1, "node_depth": 9, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "arguments", "field_expression", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " | output [${numGPIO - 1}:0] dataOut,\n"}
|
| 96 |
+
{"file": "chiselv/chiselv/src/InstructionMemory.scala", "target_type": "if_expression", "cursor_line": 24, "target_nlines": 3, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "if_expression"], "target": " if (memoryFile.trim().nonEmpty) {\n loadMemoryFromFileInline(mem, memoryFile)\n }\n"}
|
| 97 |
+
{"file": "chiselv/chiselv/src/MemoryIOManager.scala", "target_type": "block", "cursor_line": 213, "target_nlines": 5, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "call_expression", "block"], "target": " }\n is(2.U) { // Write halfword\n switch(io.DataMemPort.writeAddress(1).asUInt) {\n is(1.U) { // Write half word 1\n dataToWrite := Cat(io.MemoryIOPort.writeData(15, 0).asUInt, Fill(16, 0.U))\n"}
|
| 98 |
+
{"file": "chiselv/chiselv/src/PLLBlackBox.scala", "target_type": "class_definition", "cursor_line": 12, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val lock = Output(Clock())\n })\n\n val filename = \"pll_\" + board + \".v\"\n val verilog = Source.fromResource(filename).getLines().mkString(\"\\n\")\n"}
|
| 99 |
+
{"file": "chiselv/chiselv/src/ProgramCounter.scala", "target_type": "class_definition", "cursor_line": 7, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val PC = Output(UInt(bitWidth.W))\n val PC4 = Output(UInt(bitWidth.W))\n"}
|
| 100 |
+
{"file": "chiselv/chiselv/src/RVFI_Wrapper.scala", "target_type": "class_definition", "cursor_line": 72, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " rvfi.insn := decoder.io.op\n\n"}
|
| 101 |
+
{"file": "chiselv/chiselv/src/RegisterBank.scala", "target_type": "class_definition", "cursor_line": 11, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val regwr_addr = Input(UInt(log2Ceil(bitWidth).W))\n val regwr_data = Input(UInt(bitWidth.W))\n"}
|
| 102 |
+
{"file": "chiselv/chiselv/src/SOC.scala", "target_type": "block", "cursor_line": 58, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "if_expression", "block"], "target": " if (numGPIO > 0) {\n core.io.GPIO0External <> io.GPIO0External\n }\n"}
|
| 103 |
+
{"file": "chiselv/chiselv/src/Syscon.scala", "target_type": "class_definition", "cursor_line": 6, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class SysconPort(val bitWidth: Int) extends Bundle {\n val Address = Input(UInt(12.W))\n val DataOut = Output(UInt(bitWidth.W))\n}\n"}
|
| 104 |
+
{"file": "chiselv/chiselv/src/Timer.scala", "target_type": "block", "cursor_line": 23, "target_nlines": 3, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block"], "target": " when(counterWrap) {\n counter := counter + 1.U\n }\n"}
|
| 105 |
+
{"file": "chiselv/chiselv/src/Toplevel.scala", "target_type": "if_expression", "cursor_line": 24, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "if_expression"], "target": " val customReset = if (invReset) ~reset.asBool else reset\n"}
|
| 106 |
+
{"file": "chiselv/chiselv/src/Uart.scala", "target_type": "block", "cursor_line": 181, "target_nlines": 5, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "call_expression", "block", "call_expression", "block"], "target": " when(rx === 1.U) {\n /* We might overflow the queue if we can't keep up */\n rxQueue.io.enq.bits := rxByte.reverse.reduce(_ ## _)\n rxQueue.io.enq.valid := true.B\n rxState := sRxIdle\n"}
|
| 107 |
+
{"file": "chiselv/chiselv/test/src/ALUSpec.scala", "target_type": "if_expression", "cursor_line": 110, "target_nlines": 1, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "indented_block", "match_expression", "case_block", "case_clause", "if_expression"], "target": " case GTE => if (a.toInt >= b.toInt) 1 else 0\n"}
|
| 108 |
+
{"file": "chiselv/chiselv/test/src/CPUDemoAppsSpec.scala", "target_type": "block", "cursor_line": 76, "target_nlines": 4, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block"], "target": " defaultDut(filename) { c =>\n c.clock.setTimeout(3000)\n c.clock.step(2000)\n }\n"}
|
| 109 |
+
{"file": "chiselv/chiselv/test/src/CPUSingleCycleAppsSpec.scala", "target_type": "block", "cursor_line": 84, "target_nlines": 2, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " c.clock.step(1 + writeLatency) // sw\n // Check Memory read at address 0x80000000\n"}
|
| 110 |
+
{"file": "chiselv/chiselv/test/src/CPUSingleCycleIOSpec.scala", "target_type": "block", "cursor_line": 134, "target_nlines": 5, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " c.registers(3).peekInt() should be(0)\n c.clock.step(1) // bne\n c.clock.step(2 * ms) // wait 2ms\n c.timerCounter.peekInt() should be(2)\n c.registers(3).peekInt() should be(2)\n"}
|
| 111 |
+
{"file": "chiselv/chiselv/test/src/CPUSingleCycleInstructionSpec.scala", "target_type": "block", "cursor_line": 120, "target_nlines": 5, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " jal x1, +8\n nop\n jalr x2, x1, +2044\n \"\"\"\n defaultDut(prog) { c =>\n"}
|
| 112 |
+
{"file": "chiselv/chiselv/test/src/DecoderSpec.scala", "target_type": "block", "cursor_line": 251, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"lbu x1, 16(x2)\"))\n c.clock.step()\n"}
|
| 113 |
+
{"file": "chiselv/chiselv/test/src/GPIOSpec.scala", "target_type": "function_definition", "cursor_line": 22, "target_nlines": 3, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " )\n\n it should \"read GPIO output and direction as 0 when initialized\" in {\n"}
|
| 114 |
+
{"file": "chiselv/chiselv/test/src/MemorySpec.scala", "target_type": "block", "cursor_line": 42, "target_nlines": 5, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block", "lambda_expression", "indented_block", "call_expression", "block"], "target": " addresses.foreach { address =>\n values.foreach { value =>\n c.io.writeEnable.poke(true)\n c.io.writeAddress.poke(addressOffset + address)\n c.io.readAddress.poke(addressOffset + address)\n"}
|
| 115 |
+
{"file": "chiselv/chiselv/test/src/ProgramCounterSpec.scala", "target_type": "block", "cursor_line": 28, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " c.clock.step()\n"}
|
| 116 |
+
{"file": "chiselv/chiselv/test/src/RegisterBankSpec.scala", "target_type": "block", "cursor_line": 14, "target_nlines": 4, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block"], "target": " test(new RegisterBank) { c =>\n c.io.rs1_addr.poke(0.U)\n c.io.rs1.expect(0.U)\n }\n"}
|
| 117 |
+
{"file": "chiselv/chiselv/test/src/SysconSpec.scala", "target_type": "block", "cursor_line": 35, "target_nlines": 4, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " c.clock.step()\n c.io.DataOut.peekInt() should be(1)\n }\n }\n"}
|
| 118 |
+
{"file": "chiselv/chiselv/test/src/TimerSpec.scala", "target_type": "block", "cursor_line": 28, "target_nlines": 4, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " c.io.dataOut.peekInt() should be(0)\n c.obs_counter.peekInt() should be(0)\n c.clock.step(ms)\n c.io.dataOut.peekInt() should be(1)\n"}
|
| 119 |
+
{"file": "chiselv/chiselv/test/src/UartSpec.scala", "target_type": "function_definition", "cursor_line": 21, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " def clockSerial(clk: Clock) = clk.step(fpgaClock / baudRate)\n"}
|
chisel/valid_content.jsonl
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hls/test.jsonl
ADDED
|
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+
version https://git-lfs.github.com/spec/v1
|
| 2 |
+
oid sha256:3b8f723e337530a48fa787aeb821b22f3f6d686b159d457e148173c8cda3322c
|
| 3 |
+
size 34348033
|
hls/test_content_classfied.jsonl
ADDED
|
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| 1 |
+
version https://git-lfs.github.com/spec/v1
|
| 2 |
+
oid sha256:f1200bb1dec805ed8ef04ff0b4fa435608ff8424233dc10f1e24d008e773b7a2
|
| 3 |
+
size 90250832
|
hls/train.jsonl
ADDED
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hls/train_content.jsonl
ADDED
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hls/valid.jsonl
ADDED
|
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|
| 1 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/qam_dem.h", "target_type": "function_definition", "cursor_line": 21, "target_nlines": 3, "node_depth": 2, "node_path": ["translation_unit", "preproc_ifdef", "function_definition"], "target": " cphase_t ph_xy;\n qam_t \t\tqam;\n\n"}
|
| 2 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/.autopilot/db/hls_design_meta.h", "target_type": "preproc_ifdef", "cursor_line": 4, "target_nlines": 4, "node_depth": 1, "node_path": ["translation_unit", "preproc_ifdef"], "target": "\nstruct HLS_Design_Meta {\n// port data: name, bitwidth, direction (enumerator: hls_in, hls_out, hls_inout), group.\nstatic const Port_Property port_props[21];\n"}
|
| 3 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/sim/fastsim/hls_design.h", "target_type": "compound_statement", "cursor_line": 318, "target_nlines": 3, "node_depth": 1, "node_path": ["ERROR", "compound_statement"], "target": " {\r\n return mStartTime;\r\n }\r\n"}
|
| 4 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/sim/fastsim/hls_design_meta.h", "target_type": "field_declaration", "cursor_line": 11, "target_nlines": 1, "node_depth": 4, "node_path": ["translation_unit", "preproc_ifdef", "struct_specifier", "field_declaration_list", "field_declaration"], "target": "static bool is_vld_port(HLS_UINT32);\n"}
|
| 5 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/sim/fastsim/hls_util.h", "target_type": "if_statement", "cursor_line": 57, "target_nlines": 2, "node_depth": 7, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement", "compound_statement", "for_statement", "compound_statement", "if_statement"], "target": " if (i >= numWord) \n return tmp;\n"}
|
| 6 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/sim/fastsim/stdafx.h", "target_type": "preproc_ifdef", "cursor_line": 6, "target_nlines": 5, "node_depth": 1, "node_path": ["translation_unit", "preproc_ifdef"], "target": "#pragma once\r\n\r\n#include \"targetver.h\"\r\n\r\n#define WIN32_LEAN_AND_MEAN // Exclude rarely-used stuff from Windows headers\r\n"}
|
| 7 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/sim/fastsim/targetver.h", "target_type": "preproc_ifdef", "cursor_line": 2, "target_nlines": 1, "node_depth": 1, "node_path": ["translation_unit", "preproc_ifdef"], "target": "#pragma once\r\n"}
|
| 8 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/sim/fastsim/vhls_sim.h", "target_type": "declaration", "cursor_line": 172, "target_nlines": 1, "node_depth": 6, "node_path": ["translation_unit", "preproc_ifdef", "preproc_ifdef", "linkage_specification", "declaration_list", "preproc_ifdef", "declaration"], "target": " HLS_DLLESPEC hlsHandle hls_open(p_hls_setup_info setup_info); \n"}
|
| 9 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/syn/systemc/AESL_pkg.h", "target_type": "if_statement", "cursor_line": 170, "target_nlines": 1, "node_depth": 5, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement", "compound_statement", "if_statement"], "target": " if (!i0.is_01()) return sc_lv<T>();\n"}
|
| 10 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/syn/systemc/qam_dem_top.h", "target_type": "compound_statement", "cursor_line": 76, "target_nlines": 4, "node_depth": 5, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement", "function_definition", "compound_statement"], "target": " sc_signal< sc_lv<1> > qam_dem_top_mounstrito_U0_control_reg_clr;\n sc_signal< sc_lv<28> > qam_dem_top_mounstrito_U0_control_reg_init_V;\n sc_signal< sc_logic > ap_sig_hs_continue;\n sc_signal< sc_logic > ap_reg_procdone_qam_dem_top_mounstrito_U0;\n"}
|
| 11 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/syn/systemc/qam_dem_top_mounstrito.h", "target_type": "declaration", "cursor_line": 339, "target_nlines": 1, "node_depth": 6, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement", "function_definition", "compound_statement", "declaration"], "target": " static const sc_lv<32> ap_const_lv32_E;\n"}
|
| 12 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/syn/systemc/qam_dem_top_mounstrito_cos_lut.h", "target_type": "compound_statement", "cursor_line": 45, "target_nlines": 3, "node_depth": 7, "node_path": ["translation_unit", "preproc_ifdef", "labeled_statement", "compound_statement", "function_definition", "compound_statement", "for_statement", "compound_statement"], "target": " for (unsigned i = 0; i < 7 ; i = i + 1) {\n ram[i] = \"0b111111111111111\";\n }\n"}
|
| 13 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/syn/systemc/qam_dem_top_mul_16s_12s_27_2.h", "target_type": "declaration", "cursor_line": 20, "target_nlines": 1, "node_depth": 4, "node_path": ["translation_unit", "preproc_ifdef", "compound_statement", "labeled_statement", "declaration"], "target": " sc_core::sc_in_clk clk;\n"}
|
| 14 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/synt_types.h", "target_type": "expression_statement", "cursor_line": 32, "target_nlines": 1, "node_depth": 2, "node_path": ["translation_unit", "preproc_ifdef", "expression_statement"], "target": "typedef ap_fixed<14,2,AP_TRN,AP_SAT> phase_t; // phase in radian\n"}
|
| 15 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/qam_dem.cpp", "target_type": "function_definition", "cursor_line": 6, "target_nlines": 2, "node_depth": 1, "node_path": ["translation_unit", "function_definition"], "target": "\tstatic QAMDEM qam; //Accesible for all the functions\n\n"}
|
| 16 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/qam_dem_defs.cpp", "target_type": "declaration", "cursor_line": 219, "target_nlines": 1, "node_depth": 3, "node_path": ["translation_unit", "function_definition", "compound_statement", "declaration"], "target": " cphase_t t_ph_out;\n"}
|
| 17 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/.autopilot/db/hls_design_meta.cpp", "target_type": "declaration", "cursor_line": 9, "target_nlines": 2, "node_depth": 1, "node_path": ["translation_unit", "declaration"], "target": "\tPort_Property(\"ph_out_i_V\", 12, hls_out, 6, \"ap_none\", \"out_data\", 1),\n\tPort_Property(\"ph_out_q_V\", 12, hls_out, 7, \"ap_none\", \"out_data\", 1),\n"}
|
| 18 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/.autopilot/db/qam_dem.pp.0.cpp", "target_type": "function_definition", "cursor_line": 39630, "target_nlines": 1, "node_depth": 2, "node_path": ["translation_unit", "template_declaration", "function_definition"], "target": "template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,false>::template RType<64,false>::plus operator + ( const ap_range_ref<_AP_W,_AP_S> &op, unsigned long op2) { return (ap_int_base<_AP_W, false>(op)) + (ap_int_base<64,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<64,false>::template RType<_AP_W,false>::plus operator + ( unsigned long op2, const ap_range_ref<_AP_W,_AP_S> &op) { return ap_int_base<64,false>(op2) + (ap_int_base<_AP_W, false>(op)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,false>::template RType<64,false>::minus operator - ( const ap_range_ref<_AP_W,_AP_S> &op, unsigned long op2) { return (ap_int_base<_AP_W, false>(op)) - (ap_int_base<64,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<64,false>::template RType<_AP_W,false>::minus operator - ( unsigned long op2, const ap_range_ref<_AP_W,_AP_S> &op) { return ap_int_base<64,false>(op2) - (ap_int_base<_AP_W, false>(op)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,false>::template RType<64,false>::mult operator * ( const ap_range_ref<_AP_W,_AP_S> &op, unsigned long op2) { return (ap_int_base<_AP_W, false>(op)) * (ap_int_base<64,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<64,false>::template RType<_AP_W,false>::mult operator * ( unsigned long op2, const ap_range_ref<_AP_W,_AP_S> &op) { return ap_int_base<64,false>(op2) * (ap_int_base<_AP_W, false>(op)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,false>::template RType<64,false>::div operator / ( const ap_range_ref<_AP_W,_AP_S> &op, unsigned long op2) { return (ap_int_base<_AP_W, false>(op)) / (ap_int_base<64,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<64,false>::template RType<_AP_W,false>::div operator / ( unsigned long op2, const ap_range_ref<_AP_W,_AP_S> &op) { return ap_int_base<64,false>(op2) / (ap_int_base<_AP_W, false>(op)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,false>::template RType<64,false>::mod operator % ( const ap_range_ref<_AP_W,_AP_S> &op, unsigned long op2) { return (ap_int_base<_AP_W, false>(op)) % (ap_int_base<64,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<64,false>::template RType<_AP_W,false>::mod operator % ( unsigned long op2, const ap_range_ref<_AP_W,_AP_S> &op) { return ap_int_base<64,false>(op2) % (ap_int_base<_AP_W, false>(op)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,false>::template RType<64,false>::arg1 operator >> ( const ap_range_ref<_AP_W,_AP_S> &op, unsigned long op2) { return (ap_int_base<_AP_W, false>(op)) >> (ap_int_base<64,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<64,false>::template RType<_AP_W,false>::arg1 operator >> ( unsigned long op2, const ap_range_ref<_AP_W,_AP_S> &op) { return ap_int_base<64,false>(op2) >> (ap_int_base<_AP_W, false>(op)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,false>::template RType<64,false>::arg1 operator << ( const ap_range_ref<_AP_W,_AP_S> &op, unsigned long op2) { return (ap_int_base<_AP_W, false>(op)) << (ap_int_base<64,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<64,false>::template RType<_AP_W,false>::arg1 operator << ( unsigned long op2, const ap_range_ref<_AP_W,_AP_S> &op) { return ap_int_base<64,false>(op2) << (ap_int_base<_AP_W, false>(op)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,false>::template RType<64,false>::logic operator & ( const ap_range_ref<_AP_W,_AP_S> &op, unsigned long op2) { return (ap_int_base<_AP_W, false>(op)) & (ap_int_base<64,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<64,false>::template RType<_AP_W,false>::logic operator & ( unsigned long op2, const ap_range_ref<_AP_W,_AP_S> &op) { return ap_int_base<64,false>(op2) & (ap_int_base<_AP_W, false>(op)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,false>::template RType<64,false>::logic operator | ( const ap_range_ref<_AP_W,_AP_S> &op, unsigned long op2) { return (ap_int_base<_AP_W, false>(op)) | (ap_int_base<64,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<64,false>::template RType<_AP_W,false>::logic operator | ( unsigned long op2, const ap_range_ref<_AP_W,_AP_S> &op) { return ap_int_base<64,false>(op2) | (ap_int_base<_AP_W, false>(op)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,false>::template RType<64,false>::logic operator ^ ( const ap_range_ref<_AP_W,_AP_S> &op, unsigned long op2) { return (ap_int_base<_AP_W, false>(op)) ^ (ap_int_base<64,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<64,false>::template RType<_AP_W,false>::logic operator ^ ( unsigned long op2, const ap_range_ref<_AP_W,_AP_S> &op) { return ap_int_base<64,false>(op2) ^ (ap_int_base<_AP_W, false>(op)); }\n"}
|
| 19 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/.autopilot/db/qam_dem.pp.0.cpp.ap-cdt.cpp", "target_type": "compound_statement", "cursor_line": 35853, "target_nlines": 1, "node_depth": 5, "node_path": ["translation_unit", "template_declaration", "struct_specifier", "field_declaration_list", "function_definition", "compound_statement"], "target": "template<> struct ssdm_int<15 + 1024 * 0,true> { int V __attribute__ ((bitwidth(15 + 1024 * 0))); inline __attribute__((always_inline)) ssdm_int<15 + 1024 * 0 ,true>() { }; }; template<> struct ssdm_int<15 + 1024 * 0, false> { unsigned int V __attribute__ ((bitwidth(15 + 1024 * 0))); inline __attribute__((always_inline)) ssdm_int<15 + 1024 * 0 , false>() { }; };\n"}
|
| 20 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/.autopilot/db/qam_dem.pp.0.cpp.ap-line.cpp", "target_type": "function_definition", "cursor_line": 37744, "target_nlines": 3, "node_depth": 5, "node_path": ["translation_unit", "template_declaration", "struct_specifier", "field_declaration_list", "template_declaration", "function_definition"], "target": " inline __attribute__((always_inline)) ap_int_base(const ap_fixed_base<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& op) {\n Base::V = op.to_ap_int_base().V;\n }\n"}
|
| 21 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/.autopilot/db/qam_dem.pragma.0.cpp", "target_type": "compound_statement", "cursor_line": 39551, "target_nlines": 1, "node_depth": 3, "node_path": ["translation_unit", "template_declaration", "function_definition", "compound_statement"], "target": "template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<64,false>::mult operator * (unsigned long i_op, const ap_int_base<_AP_W,_AP_S, false> &op) { return ap_int_base<64,false>(i_op) * (op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<64,false>::mult operator * ( const ap_int_base<_AP_W,_AP_S, false> &op, unsigned long i_op) { return op * ap_int_base<64,false>(i_op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<64,false>::plus operator + (unsigned long i_op, const ap_int_base<_AP_W,_AP_S, false> &op) { return ap_int_base<64,false>(i_op) + (op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<64,false>::plus operator + ( const ap_int_base<_AP_W,_AP_S, false> &op, unsigned long i_op) { return op + ap_int_base<64,false>(i_op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<64,false>::minus operator - (unsigned long i_op, const ap_int_base<_AP_W,_AP_S, false> &op) { return ap_int_base<64,false>(i_op) - (op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<64,false>::minus operator - ( const ap_int_base<_AP_W,_AP_S, false> &op, unsigned long i_op) { return op - ap_int_base<64,false>(i_op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<64,false>::div operator / (unsigned long i_op, const ap_int_base<_AP_W,_AP_S, false> &op) { return ap_int_base<64,false>(i_op) / (op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<64,false>::div operator / ( const ap_int_base<_AP_W,_AP_S, false> &op, unsigned long i_op) { return op / ap_int_base<64,false>(i_op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<64,false>::mod operator % (unsigned long i_op, const ap_int_base<_AP_W,_AP_S, false> &op) { return ap_int_base<64,false>(i_op) % (op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<64,false>::mod operator % ( const ap_int_base<_AP_W,_AP_S, false> &op, unsigned long i_op) { return op % ap_int_base<64,false>(i_op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<64,false>::logic operator & (unsigned long i_op, const ap_int_base<_AP_W,_AP_S, false> &op) { return ap_int_base<64,false>(i_op) & (op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<64,false>::logic operator & ( const ap_int_base<_AP_W,_AP_S, false> &op, unsigned long i_op) { return op & ap_int_base<64,false>(i_op); } template <int _AP_W, bool _AP_S> inline __attribute__((always_inline)) ap_int_base<_AP_W, _AP_S> operator << (const ap_int_base<_AP_W, _AP_S>& op, unsigned long op2) { ap_int_base<_AP_W, _AP_S> r; if (false) r.V = op2 >= 0 ? (op.V << op2) : (op.V >> (-op2)); else r.V = op.V << op2; return r; } template <int _AP_W, bool _AP_S> inline __attribute__((always_inline)) ap_int_base<_AP_W, _AP_S> operator >> (const ap_int_base<_AP_W, _AP_S>& op, unsigned long op2) { ap_int_base<_AP_W, _AP_S> r; if (false) r.V = op2 >= 0 ? (op.V >> op2) : (op.V << (-op2)); else r.V = op.V >> op2; return r; } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<64,false>::logic operator | (unsigned long i_op, const ap_int_base<_AP_W,_AP_S, false> &op) { return ap_int_base<64,false>(i_op) | (op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<64,false>::logic operator | ( const ap_int_base<_AP_W,_AP_S, false> &op, unsigned long i_op) { return op | ap_int_base<64,false>(i_op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<64,false>::logic operator ^ (unsigned long i_op, const ap_int_base<_AP_W,_AP_S, false> &op) { return ap_int_base<64,false>(i_op) ^ (op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<64,false>::logic operator ^ ( const ap_int_base<_AP_W,_AP_S, false> &op, unsigned long i_op) { return op ^ ap_int_base<64,false>(i_op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) bool operator == ( unsigned long i_op, const ap_int_base<_AP_W,_AP_S, false> &op) { return ap_int_base<64,false>(i_op).operator == (op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) bool operator == ( const ap_int_base<_AP_W,_AP_S> &op, unsigned long op2) { return op.operator == (ap_int_base<64,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) bool operator != ( unsigned long i_op, const ap_int_base<_AP_W,_AP_S, false> &op) { return ap_int_base<64,false>(i_op).operator != (op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) bool operator != ( const ap_int_base<_AP_W,_AP_S> &op, unsigned long op2) { return op.operator != (ap_int_base<64,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) bool operator > ( unsigned long i_op, const ap_int_base<_AP_W,_AP_S, false> &op) { return ap_int_base<64,false>(i_op).operator > (op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) bool operator > ( const ap_int_base<_AP_W,_AP_S> &op, unsigned long op2) { return op.operator > (ap_int_base<64,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) bool operator >= ( unsigned long i_op, const ap_int_base<_AP_W,_AP_S, false> &op) { return ap_int_base<64,false>(i_op).operator >= (op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) bool operator >= ( const ap_int_base<_AP_W,_AP_S> &op, unsigned long op2) { return op.operator >= (ap_int_base<64,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) bool operator < ( unsigned long i_op, const ap_int_base<_AP_W,_AP_S, false> &op) { return ap_int_base<64,false>(i_op).operator < (op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) bool operator < ( const ap_int_base<_AP_W,_AP_S> &op, unsigned long op2) { return op.operator < (ap_int_base<64,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) bool operator <= ( unsigned long i_op, const ap_int_base<_AP_W,_AP_S, false> &op) { return ap_int_base<64,false>(i_op).operator <= (op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) bool operator <= ( const ap_int_base<_AP_W,_AP_S> &op, unsigned long op2) { return op.operator <= (ap_int_base<64,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) ap_int_base<_AP_W,_AP_S> &operator += ( ap_int_base<_AP_W,_AP_S> &op, unsigned long op2) { return op.operator += (ap_int_base<64,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) ap_int_base<_AP_W,_AP_S> &operator -= ( ap_int_base<_AP_W,_AP_S> &op, unsigned long op2) { return op.operator -= (ap_int_base<64,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) ap_int_base<_AP_W,_AP_S> &operator *= ( ap_int_base<_AP_W,_AP_S> &op, unsigned long op2) { return op.operator *= (ap_int_base<64,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) ap_int_base<_AP_W,_AP_S> &operator /= ( ap_int_base<_AP_W,_AP_S> &op, unsigned long op2) { return op.operator /= (ap_int_base<64,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) ap_int_base<_AP_W,_AP_S> &operator %= ( ap_int_base<_AP_W,_AP_S> &op, unsigned long op2) { return op.operator %= (ap_int_base<64,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) ap_int_base<_AP_W,_AP_S> &operator >>= ( ap_int_base<_AP_W,_AP_S> &op, unsigned long op2) { return op.operator >>= (ap_int_base<64,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) ap_int_base<_AP_W,_AP_S> &operator <<= ( ap_int_base<_AP_W,_AP_S> &op, unsigned long op2) { return op.operator <<= (ap_int_base<64,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) ap_int_base<_AP_W,_AP_S> &operator &= ( ap_int_base<_AP_W,_AP_S> &op, unsigned long op2) { return op.operator &= (ap_int_base<64,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) ap_int_base<_AP_W,_AP_S> &operator |= ( ap_int_base<_AP_W,_AP_S> &op, unsigned long op2) { return op.operator |= (ap_int_base<64,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) ap_int_base<_AP_W,_AP_S> &operator ^= ( ap_int_base<_AP_W,_AP_S> &op, unsigned long op2) { return op.operator ^= (ap_int_base<64,false>(op2)); }\n"}
|
| 22 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/.autopilot/db/qam_dem.pragma.1.cpp", "target_type": "function_definition", "cursor_line": 37078, "target_nlines": 5, "node_depth": 5, "node_path": ["translation_unit", "template_declaration", "struct_specifier", "field_declaration_list", "template_declaration", "function_definition"], "target": " inline __attribute__((always_inline)) ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, ap_range_ref<_AP_W3, _AP_S3> >\n operator, (const ap_range_ref<_AP_W3, _AP_S3>& a2) {\n return ap_concat_ref<_AP_WR, ap_concat_ref,\n _AP_W3, ap_range_ref<_AP_W3, _AP_S3> >(*this,\n const_cast<ap_range_ref<_AP_W3, _AP_S3>& >(a2));\n"}
|
| 23 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/.autopilot/db/qam_dem.pragma.2.cpp", "target_type": "compound_statement", "cursor_line": 39541, "target_nlines": 1, "node_depth": 3, "node_path": ["translation_unit", "template_declaration", "function_definition", "compound_statement"], "target": "template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<1,false>::mult operator * (bool i_op, const ap_int_base<_AP_W,_AP_S, false> &op) { return ap_int_base<1,false>(i_op) * (op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<1,false>::mult operator * ( const ap_int_base<_AP_W,_AP_S, false> &op, bool i_op) { return op * ap_int_base<1,false>(i_op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<1,false>::plus operator + (bool i_op, const ap_int_base<_AP_W,_AP_S, false> &op) { return ap_int_base<1,false>(i_op) + (op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<1,false>::plus operator + ( const ap_int_base<_AP_W,_AP_S, false> &op, bool i_op) { return op + ap_int_base<1,false>(i_op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<1,false>::minus operator - (bool i_op, const ap_int_base<_AP_W,_AP_S, false> &op) { return ap_int_base<1,false>(i_op) - (op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<1,false>::minus operator - ( const ap_int_base<_AP_W,_AP_S, false> &op, bool i_op) { return op - ap_int_base<1,false>(i_op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<1,false>::div operator / (bool i_op, const ap_int_base<_AP_W,_AP_S, false> &op) { return ap_int_base<1,false>(i_op) / (op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<1,false>::div operator / ( const ap_int_base<_AP_W,_AP_S, false> &op, bool i_op) { return op / ap_int_base<1,false>(i_op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<1,false>::mod operator % (bool i_op, const ap_int_base<_AP_W,_AP_S, false> &op) { return ap_int_base<1,false>(i_op) % (op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<1,false>::mod operator % ( const ap_int_base<_AP_W,_AP_S, false> &op, bool i_op) { return op % ap_int_base<1,false>(i_op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<1,false>::logic operator & (bool i_op, const ap_int_base<_AP_W,_AP_S, false> &op) { return ap_int_base<1,false>(i_op) & (op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<1,false>::logic operator & ( const ap_int_base<_AP_W,_AP_S, false> &op, bool i_op) { return op & ap_int_base<1,false>(i_op); } template <int _AP_W, bool _AP_S> inline __attribute__((always_inline)) ap_int_base<_AP_W, _AP_S> operator << (const ap_int_base<_AP_W, _AP_S>& op, bool op2) { ap_int_base<_AP_W, _AP_S> r; if (false) r.V = op2 >= 0 ? (op.V << op2) : (op.V >> (-op2)); else r.V = op.V << op2; return r; } template <int _AP_W, bool _AP_S> inline __attribute__((always_inline)) ap_int_base<_AP_W, _AP_S> operator >> (const ap_int_base<_AP_W, _AP_S>& op, bool op2) { ap_int_base<_AP_W, _AP_S> r; if (false) r.V = op2 >= 0 ? (op.V >> op2) : (op.V << (-op2)); else r.V = op.V >> op2; return r; } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<1,false>::logic operator | (bool i_op, const ap_int_base<_AP_W,_AP_S, false> &op) { return ap_int_base<1,false>(i_op) | (op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<1,false>::logic operator | ( const ap_int_base<_AP_W,_AP_S, false> &op, bool i_op) { return op | ap_int_base<1,false>(i_op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<1,false>::logic operator ^ (bool i_op, const ap_int_base<_AP_W,_AP_S, false> &op) { return ap_int_base<1,false>(i_op) ^ (op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) typename ap_int_base<_AP_W,_AP_S>::template RType<1,false>::logic operator ^ ( const ap_int_base<_AP_W,_AP_S, false> &op, bool i_op) { return op ^ ap_int_base<1,false>(i_op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) bool operator == ( bool i_op, const ap_int_base<_AP_W,_AP_S, false> &op) { return ap_int_base<1,false>(i_op).operator == (op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) bool operator == ( const ap_int_base<_AP_W,_AP_S> &op, bool op2) { return op.operator == (ap_int_base<1,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) bool operator != ( bool i_op, const ap_int_base<_AP_W,_AP_S, false> &op) { return ap_int_base<1,false>(i_op).operator != (op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) bool operator != ( const ap_int_base<_AP_W,_AP_S> &op, bool op2) { return op.operator != (ap_int_base<1,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) bool operator > ( bool i_op, const ap_int_base<_AP_W,_AP_S, false> &op) { return ap_int_base<1,false>(i_op).operator > (op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) bool operator > ( const ap_int_base<_AP_W,_AP_S> &op, bool op2) { return op.operator > (ap_int_base<1,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) bool operator >= ( bool i_op, const ap_int_base<_AP_W,_AP_S, false> &op) { return ap_int_base<1,false>(i_op).operator >= (op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) bool operator >= ( const ap_int_base<_AP_W,_AP_S> &op, bool op2) { return op.operator >= (ap_int_base<1,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) bool operator < ( bool i_op, const ap_int_base<_AP_W,_AP_S, false> &op) { return ap_int_base<1,false>(i_op).operator < (op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) bool operator < ( const ap_int_base<_AP_W,_AP_S> &op, bool op2) { return op.operator < (ap_int_base<1,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) bool operator <= ( bool i_op, const ap_int_base<_AP_W,_AP_S, false> &op) { return ap_int_base<1,false>(i_op).operator <= (op); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) bool operator <= ( const ap_int_base<_AP_W,_AP_S> &op, bool op2) { return op.operator <= (ap_int_base<1,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) ap_int_base<_AP_W,_AP_S> &operator += ( ap_int_base<_AP_W,_AP_S> &op, bool op2) { return op.operator += (ap_int_base<1,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) ap_int_base<_AP_W,_AP_S> &operator -= ( ap_int_base<_AP_W,_AP_S> &op, bool op2) { return op.operator -= (ap_int_base<1,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) ap_int_base<_AP_W,_AP_S> &operator *= ( ap_int_base<_AP_W,_AP_S> &op, bool op2) { return op.operator *= (ap_int_base<1,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) ap_int_base<_AP_W,_AP_S> &operator /= ( ap_int_base<_AP_W,_AP_S> &op, bool op2) { return op.operator /= (ap_int_base<1,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) ap_int_base<_AP_W,_AP_S> &operator %= ( ap_int_base<_AP_W,_AP_S> &op, bool op2) { return op.operator %= (ap_int_base<1,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) ap_int_base<_AP_W,_AP_S> &operator >>= ( ap_int_base<_AP_W,_AP_S> &op, bool op2) { return op.operator >>= (ap_int_base<1,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) ap_int_base<_AP_W,_AP_S> &operator <<= ( ap_int_base<_AP_W,_AP_S> &op, bool op2) { return op.operator <<= (ap_int_base<1,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) ap_int_base<_AP_W,_AP_S> &operator &= ( ap_int_base<_AP_W,_AP_S> &op, bool op2) { return op.operator &= (ap_int_base<1,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) ap_int_base<_AP_W,_AP_S> &operator |= ( ap_int_base<_AP_W,_AP_S> &op, bool op2) { return op.operator |= (ap_int_base<1,false>(op2)); } template<int _AP_W, bool _AP_S> inline __attribute__((always_inline)) ap_int_base<_AP_W,_AP_S> &operator ^= ( ap_int_base<_AP_W,_AP_S> &op, bool op2) { return op.operator ^= (ap_int_base<1,false>(op2)); }\n"}
|
| 24 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/sim/autowrap/testbench/qam_dem.cpp_pre.cpp", "target_type": "declaration", "cursor_line": 21288, "target_nlines": 1, "node_depth": 9, "node_path": ["translation_unit", "template_declaration", "function_definition", "compound_statement", "if_statement", "compound_statement", "if_statement", "else_clause", "compound_statement", "declaration"], "target": " off_type __file_off = _M_file.seekoff(0, ios_base::cur);\n"}
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| 25 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/sim/autowrap/testbench/qam_dem.cpp_pre.cpp.line.cpp", "target_type": "if_statement", "cursor_line": 28721, "target_nlines": 5, "node_depth": 4, "node_path": ["translation_unit", "template_declaration", "function_definition", "compound_statement", "if_statement"], "target": "#pragma empty_line\n#pragma empty_line\n tmp.flip();\n tmp++;\n result = \"-\";\n"}
|
| 26 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/sim/autowrap/testbench/qam_dem.cpp_pre.cpp.tb.cpp", "target_type": "compound_statement", "cursor_line": 8245, "target_nlines": 1, "node_depth": 5, "node_path": ["translation_unit", "template_declaration", "struct_specifier", "field_declaration_list", "function_definition", "compound_statement"], "target": " { return !__x; }\n"}
|
| 27 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/sim/autowrap/testbench/tb_qam_dem.cpp_pre.cpp", "target_type": "function_definition", "cursor_line": 34812, "target_nlines": 3, "node_depth": 2, "node_path": ["translation_unit", "template_declaration", "function_definition"], "target": "inline bool operator >= ( double op1, const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op2) {\n return op2.operator <= (op1);\n}\n"}
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| 28 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/sim/autowrap/testbench/tb_qam_dem.cpp_pre.cpp.line.cpp", "target_type": "declaration", "cursor_line": 32352, "target_nlines": 1, "node_depth": 4, "node_path": ["translation_unit", "template_declaration", "function_definition", "compound_statement", "declaration"], "target": "template<int _AP_W, bool _AP_S> inline ap_private< _AP_W + 1, false > operator, (const ap_private<_AP_W, _AP_S> &op1, bool op2) { ap_private<1 + _AP_W, false> val(op2); ap_private<1 + _AP_W, false> ret(op1); ret <<= 1; if (false) { val <<= _AP_W; val >>= _AP_W; } ret |= val; return ret;} template<int _AP_W, bool _AP_S> inline ap_private< _AP_W + 1, false > operator, (bool op1, const ap_private<_AP_W, _AP_S>& op2) { ap_private<1 + _AP_W, false> val(op1); ap_private<1 + _AP_W, false> ret(op2); if (_AP_S) { ret <<= 1; ret >>= 1; } ret |= val << _AP_W; return ret; } template<int _AP_W, bool _AP_S> inline ap_private< _AP_W + 1, false > operator, (const ap_range_ref<_AP_W, _AP_S> &op1, bool op2) { ap_private<1 + _AP_W, false> val(op2); ap_private<1 + _AP_W, false> ret(op1); ret <<= 1; if (false) { val <<= _AP_W; val >>= _AP_W; } ret |= val; return ret; } template<int _AP_W, bool _AP_S> inline ap_private< _AP_W + 1, false > operator, (bool op1, const ap_range_ref<_AP_W, _AP_S> &op2) { ap_private<1 + _AP_W, false> val(op1); ap_private<1 + _AP_W, false> ret(op2); int len = op2.length(); val <<= len; ret |= val; return ret; } template<int _AP_W, bool _AP_S> inline ap_private<1 + 1, false > operator, (const ap_bit_ref<_AP_W, _AP_S> &op1, bool op2) { ap_private<1 + 1, false> val(op2); val[1] = op1; return val; } template<int _AP_W, bool _AP_S> inline ap_private<1 + 1, false > operator, (bool op1, const ap_bit_ref<_AP_W, _AP_S> &op2) { ap_private<1 + 1, false> val(op1); val <<= 1; val[0] = op2; return val; } template<int _AP_W, typename _AP_T, int _AP_W2, typename _AP_T2> inline ap_private<_AP_W + _AP_W2 + 1, false > operator, (const ap_concat_ref<_AP_W, _AP_T, _AP_W2, _AP_T2> &op1, bool op2) { ap_private<1 + _AP_W + _AP_W2, false> val(op2); ap_private<1 + _AP_W + _AP_W2, false> ret(op1); if (false) { val <<= _AP_W + _AP_W2; val >>= _AP_W + _AP_W2; } ret <<= 1; ret |= val; return ret; }template<int _AP_W, typename _AP_T, int _AP_W2, typename _AP_T2> inline ap_private<_AP_W + _AP_W2 + 1, false > operator, (bool op1, const ap_concat_ref<_AP_W, _AP_T, _AP_W2, _AP_T2> &op2) { ap_private<1 + _AP_W + _AP_W2, false> val(op1); ap_private<1 + _AP_W + _AP_W2, false> ret(op2); int len = op2.length(); val <<= len; ret |= val; return ret; }template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N > inline ap_private< _AP_W + 1, false > operator, (const af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op1, bool op2) { ap_private<1 + _AP_W, false> val(op2); ap_private<1 + _AP_W, false> ret(op1); if (false) { val <<= _AP_W; val >>= _AP_W; } ret <<= 1; ret |= val; return ret; } template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N > inline ap_private< _AP_W + 1, false > operator, (bool op1, const af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op2) { ap_private<1 + _AP_W, false> val(op1); ap_private<1 + _AP_W, false> ret(op2); int len = op2.length(); val <<= len; ret |= val; return ret; } template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N > inline ap_private< 1 + 1, false> operator, (const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op1, bool op2) { ap_private<1 + 1, false> val(op2); val[1] = op1; return val; } template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N > inline ap_private< 1 + 1, false> operator, (bool op1, const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op2) { ap_private<1 + 1, false> val(op1); val <<= 1; val[0] = op2; return val; }\n"}
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| 29 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/sim/autowrap/testbench/tb_qam_dem.cpp_pre.cpp.tb.cpp", "target_type": "compound_statement", "cursor_line": 32237, "target_nlines": 1, "node_depth": 3, "node_path": ["translation_unit", "template_declaration", "function_definition", "compound_statement"], "target": "template<int _AP_W, bool _AP_S> inline typename ap_private<8,true>::template RType<_AP_W,_AP_S>::mult operator * ( char i_op, const ap_private<_AP_W,_AP_S, false> &op) { return ap_private<8,true>(i_op).operator * (op); } template<int _AP_W, bool _AP_S> inline typename ap_private<_AP_W,_AP_S>::template RType<8,true>::mult operator * ( const ap_private<_AP_W,_AP_S, false> &op, char i_op) { return op.operator * (ap_private<8,true>(i_op)); } template<int _AP_W, bool _AP_S> inline typename ap_private<8,true>::template RType<_AP_W,_AP_S>::plus operator + ( char i_op, const ap_private<_AP_W,_AP_S, false> &op) { return ap_private<8,true>(i_op).operator + (op); } template<int _AP_W, bool _AP_S> inline typename ap_private<_AP_W,_AP_S>::template RType<8,true>::plus operator + ( const ap_private<_AP_W,_AP_S, false> &op, char i_op) { return op.operator + (ap_private<8,true>(i_op)); } template<int _AP_W, bool _AP_S> inline typename ap_private<8,true>::template RType<_AP_W,_AP_S>::minus operator - ( char i_op, const ap_private<_AP_W,_AP_S, false> &op) { return ap_private<8,true>(i_op).operator - (op); } template<int _AP_W, bool _AP_S> inline typename ap_private<_AP_W,_AP_S>::template RType<8,true>::minus operator - ( const ap_private<_AP_W,_AP_S, false> &op, char i_op) { return op.operator - (ap_private<8,true>(i_op)); } template<int _AP_W, bool _AP_S> inline typename ap_private<8,true>::template RType<_AP_W,_AP_S>::div operator / ( char i_op, const ap_private<_AP_W,_AP_S, false> &op) { return ap_private<8,true>(i_op).operator / (op); } template<int _AP_W, bool _AP_S> inline typename ap_private<_AP_W,_AP_S>::template RType<8,true>::div operator / ( const ap_private<_AP_W,_AP_S, false> &op, char i_op) { return op.operator / (ap_private<8,true>(i_op)); } template<int _AP_W, bool _AP_S> inline typename ap_private<8,true>::template RType<_AP_W,_AP_S>::mod operator % ( char i_op, const ap_private<_AP_W,_AP_S, false> &op) { return ap_private<8,true>(i_op).operator % (op); } template<int _AP_W, bool _AP_S> inline typename ap_private<_AP_W,_AP_S>::template RType<8,true>::mod operator % ( const ap_private<_AP_W,_AP_S, false> &op, char i_op) { return op.operator % (ap_private<8,true>(i_op)); } template<int _AP_W, bool _AP_S> inline typename ap_private<8,true>::template RType<_AP_W,_AP_S>::logic operator & ( char i_op, const ap_private<_AP_W,_AP_S, false> &op) { return ap_private<8,true>(i_op).operator & (op); } template<int _AP_W, bool _AP_S> inline typename ap_private<_AP_W,_AP_S>::template RType<8,true>::logic operator & ( const ap_private<_AP_W,_AP_S, false> &op, char i_op) { return op.operator & (ap_private<8,true>(i_op)); } template<int _AP_W, bool _AP_S> inline typename ap_private<8,true>::template RType<_AP_W,_AP_S>::logic operator | ( char i_op, const ap_private<_AP_W,_AP_S, false> &op) { return ap_private<8,true>(i_op).operator | (op); } template<int _AP_W, bool _AP_S> inline typename ap_private<_AP_W,_AP_S>::template RType<8,true>::logic operator | ( const ap_private<_AP_W,_AP_S, false> &op, char i_op) { return op.operator | (ap_private<8,true>(i_op)); } template<int _AP_W, bool _AP_S> inline typename ap_private<8,true>::template RType<_AP_W,_AP_S>::logic operator ^ ( char i_op, const ap_private<_AP_W,_AP_S, false> &op) { return ap_private<8,true>(i_op).operator ^ (op); } template<int _AP_W, bool _AP_S> inline typename ap_private<_AP_W,_AP_S>::template RType<8,true>::logic operator ^ ( const ap_private<_AP_W,_AP_S, false> &op, char i_op) { return op.operator ^ (ap_private<8,true>(i_op)); } template<int _AP_W, bool _AP_S> char operator >> ( char i_op, const ap_private<_AP_W,_AP_S, false> &op) { return i_op >> (op.get_VAL()); } template<int _AP_W, bool _AP_S> inline typename ap_private<_AP_W,_AP_S>::template RType<8,true>::arg1 operator >> ( const ap_private<_AP_W,_AP_S> &op, char i_op) { return op.operator >> (i_op); } template<int _AP_W, bool _AP_S> char operator << ( char i_op, const ap_private<_AP_W,_AP_S, false> &op) { return i_op << (op.get_VAL()); } template<int _AP_W, bool _AP_S> inline typename ap_private<_AP_W,_AP_S>::template RType<8,true>::arg1 operator << ( const ap_private<_AP_W,_AP_S> &op, char i_op) { return op.operator << (i_op); } template<int _AP_W, bool _AP_S> inline bool operator == ( const ap_private<_AP_W,_AP_S> &op, char op2) { return op.operator == (ap_private<8, true>(op2)); } template<int _AP_W, bool _AP_S> inline bool operator == ( char op2, const ap_private<_AP_W,_AP_S, false> &op) { return ap_private<8,true>(op2).operator == (op); } template<int _AP_W, bool _AP_S> inline bool operator != ( const ap_private<_AP_W,_AP_S> &op, char op2) { return op.operator != (ap_private<8, true>(op2)); } template<int _AP_W, bool _AP_S> inline bool operator != ( char op2, const ap_private<_AP_W,_AP_S, false> &op) { return ap_private<8,true>(op2).operator != (op); } template<int _AP_W, bool _AP_S> inline bool operator > ( const ap_private<_AP_W,_AP_S> &op, char op2) { return op.operator > (ap_private<8, true>(op2)); } template<int _AP_W, bool _AP_S> inline bool operator > ( char op2, const ap_private<_AP_W,_AP_S, false> &op) { return ap_private<8,true>(op2).operator > (op); } template<int _AP_W, bool _AP_S> inline bool operator >= ( const ap_private<_AP_W,_AP_S> &op, char op2) { return op.operator >= (ap_private<8, true>(op2)); } template<int _AP_W, bool _AP_S> inline bool operator >= ( char op2, const ap_private<_AP_W,_AP_S, false> &op) { return ap_private<8,true>(op2).operator >= (op); } template<int _AP_W, bool _AP_S> inline bool operator < ( const ap_private<_AP_W,_AP_S> &op, char op2) { return op.operator < (ap_private<8, true>(op2)); } template<int _AP_W, bool _AP_S> inline bool operator < ( char op2, const ap_private<_AP_W,_AP_S, false> &op) { return ap_private<8,true>(op2).operator < (op); } template<int _AP_W, bool _AP_S> inline bool operator <= ( const ap_private<_AP_W,_AP_S> &op, char op2) { return op.operator <= (ap_private<8, true>(op2)); } template<int _AP_W, bool _AP_S> inline bool operator <= ( char op2, const ap_private<_AP_W,_AP_S, false> &op) { return ap_private<8,true>(op2).operator <= (op); } template<int _AP_W, bool _AP_S> inline ap_private<_AP_W,_AP_S> &operator += ( ap_private<_AP_W,_AP_S> &op, char op2) { return op.operator += (ap_private<8,true>(op2)); } template<int _AP_W, bool _AP_S> inline ap_private<_AP_W,_AP_S> &operator -= ( ap_private<_AP_W,_AP_S> &op, char op2) { return op.operator -= (ap_private<8,true>(op2)); } template<int _AP_W, bool _AP_S> inline ap_private<_AP_W,_AP_S> &operator *= ( ap_private<_AP_W,_AP_S> &op, char op2) { return op.operator *= (ap_private<8,true>(op2)); } template<int _AP_W, bool _AP_S> inline ap_private<_AP_W,_AP_S> &operator /= ( ap_private<_AP_W,_AP_S> &op, char op2) { return op.operator /= (ap_private<8,true>(op2)); } template<int _AP_W, bool _AP_S> inline ap_private<_AP_W,_AP_S> &operator %= ( ap_private<_AP_W,_AP_S> &op, char op2) { return op.operator %= (ap_private<8,true>(op2)); } template<int _AP_W, bool _AP_S> inline ap_private<_AP_W,_AP_S> &operator &= ( ap_private<_AP_W,_AP_S> &op, char op2) { return op.operator &= (ap_private<8,true>(op2)); } template<int _AP_W, bool _AP_S> inline ap_private<_AP_W,_AP_S> &operator |= ( ap_private<_AP_W,_AP_S> &op, char op2) { return op.operator |= (ap_private<8,true>(op2)); } template<int _AP_W, bool _AP_S> inline ap_private<_AP_W,_AP_S> &operator ^= ( ap_private<_AP_W,_AP_S> &op, char op2) { return op.operator ^= (ap_private<8,true>(op2)); } template<int _AP_W, bool _AP_S> inline ap_private<_AP_W,_AP_S> &operator >>= ( ap_private<_AP_W,_AP_S> &op, char op2) { op = op.operator >> (op2); return op; } template<int _AP_W, bool _AP_S> inline ap_private<_AP_W,_AP_S> &operator <<= ( ap_private<_AP_W,_AP_S> &op, char op2) { op = op.operator << (op2); return op; }\n"}
|
| 30 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/sim/fastsim/hls_design.cpp", "target_type": "if_statement", "cursor_line": 693, "target_nlines": 4, "node_depth": 3, "node_path": ["translation_unit", "function_definition", "compound_statement", "if_statement"], "target": " if (ready_time < get_current_time()) {\n ready_time = get_current_time();\n DEBUG(mLogFile << \"@I: delayed ready time from \" << old_ready_time << \" to \" << ready_time << std::endl);\n }\n"}
|
| 31 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/sim/fastsim/hls_design_dut.cpp", "target_type": "declaration", "cursor_line": 57, "target_nlines": 1, "node_depth": 3, "node_path": ["translation_unit", "function_definition", "compound_statement", "declaration"], "target": " ctl_crec_t control;\n"}
|
| 32 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/sim/fastsim/hls_design_meta.cpp", "target_type": "declaration", "cursor_line": 5, "target_nlines": 4, "node_depth": 1, "node_path": ["translation_unit", "declaration"], "target": "\tPort_Property(\"dout_mix_i_V\", 16, hls_out, 2, \"ap_none\", \"out_data\", 1),\n\tPort_Property(\"dout_mix_q_V\", 16, hls_out, 3, \"ap_none\", \"out_data\", 1),\n\tPort_Property(\"ph_in_i_V\", 12, hls_in, 4, \"ap_none\", \"in_data\", 1),\n\tPort_Property(\"ph_in_q_V\", 12, hls_in, 5, \"ap_none\", \"in_data\", 1),\n"}
|
| 33 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/sim/fastsim/qam_dem.cpp_pre.cpp.tb.cpp", "target_type": "function_definition", "cursor_line": 32358, "target_nlines": 1, "node_depth": 2, "node_path": ["translation_unit", "template_declaration", "function_definition"], "target": "template<int _AP_W, bool _AP_S> inline ap_private< _AP_W + 1, false > operator, (const ap_private<_AP_W, _AP_S> &op1, bool op2) { ap_private<1 + _AP_W, false> val(op2); ap_private<1 + _AP_W, false> ret(op1); ret <<= 1; if (false) { val <<= _AP_W; val >>= _AP_W; } ret |= val; return ret;} template<int _AP_W, bool _AP_S> inline ap_private< _AP_W + 1, false > operator, (bool op1, const ap_private<_AP_W, _AP_S>& op2) { ap_private<1 + _AP_W, false> val(op1); ap_private<1 + _AP_W, false> ret(op2); if (_AP_S) { ret <<= 1; ret >>= 1; } ret |= val << _AP_W; return ret; } template<int _AP_W, bool _AP_S> inline ap_private< _AP_W + 1, false > operator, (const ap_range_ref<_AP_W, _AP_S> &op1, bool op2) { ap_private<1 + _AP_W, false> val(op2); ap_private<1 + _AP_W, false> ret(op1); ret <<= 1; if (false) { val <<= _AP_W; val >>= _AP_W; } ret |= val; return ret; } template<int _AP_W, bool _AP_S> inline ap_private< _AP_W + 1, false > operator, (bool op1, const ap_range_ref<_AP_W, _AP_S> &op2) { ap_private<1 + _AP_W, false> val(op1); ap_private<1 + _AP_W, false> ret(op2); int len = op2.length(); val <<= len; ret |= val; return ret; } template<int _AP_W, bool _AP_S> inline ap_private<1 + 1, false > operator, (const ap_bit_ref<_AP_W, _AP_S> &op1, bool op2) { ap_private<1 + 1, false> val(op2); val[1] = op1; return val; } template<int _AP_W, bool _AP_S> inline ap_private<1 + 1, false > operator, (bool op1, const ap_bit_ref<_AP_W, _AP_S> &op2) { ap_private<1 + 1, false> val(op1); val <<= 1; val[0] = op2; return val; } template<int _AP_W, typename _AP_T, int _AP_W2, typename _AP_T2> inline ap_private<_AP_W + _AP_W2 + 1, false > operator, (const ap_concat_ref<_AP_W, _AP_T, _AP_W2, _AP_T2> &op1, bool op2) { ap_private<1 + _AP_W + _AP_W2, false> val(op2); ap_private<1 + _AP_W + _AP_W2, false> ret(op1); if (false) { val <<= _AP_W + _AP_W2; val >>= _AP_W + _AP_W2; } ret <<= 1; ret |= val; return ret; }template<int _AP_W, typename _AP_T, int _AP_W2, typename _AP_T2> inline ap_private<_AP_W + _AP_W2 + 1, false > operator, (bool op1, const ap_concat_ref<_AP_W, _AP_T, _AP_W2, _AP_T2> &op2) { ap_private<1 + _AP_W + _AP_W2, false> val(op1); ap_private<1 + _AP_W + _AP_W2, false> ret(op2); int len = op2.length(); val <<= len; ret |= val; return ret; }template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N > inline ap_private< _AP_W + 1, false > operator, (const af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op1, bool op2) { ap_private<1 + _AP_W, false> val(op2); ap_private<1 + _AP_W, false> ret(op1); if (false) { val <<= _AP_W; val >>= _AP_W; } ret <<= 1; ret |= val; return ret; } template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N > inline ap_private< _AP_W + 1, false > operator, (bool op1, const af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op2) { ap_private<1 + _AP_W, false> val(op1); ap_private<1 + _AP_W, false> ret(op2); int len = op2.length(); val <<= len; ret |= val; return ret; } template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N > inline ap_private< 1 + 1, false> operator, (const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op1, bool op2) { ap_private<1 + 1, false> val(op2); val[1] = op1; return val; } template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N > inline ap_private< 1 + 1, false> operator, (bool op1, const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op2) { ap_private<1 + 1, false> val(op1); val <<= 1; val[0] = op2; return val; }\n"}
|
| 34 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/sim/fastsim/tb_qam_dem.cpp_pre.cpp.tb.cpp", "target_type": "declaration", "cursor_line": 35501, "target_nlines": 1, "node_depth": 3, "node_path": ["translation_unit", "function_definition", "compound_statement", "declaration"], "target": "ap_fixed<28,2,AP_TRN,AP_WRAP> tmp_sum;\n"}
|
| 35 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/sim/fastsim/vhls_sim.cpp", "target_type": "function_definition", "cursor_line": 67, "target_nlines": 4, "node_depth": 3, "node_path": ["translation_unit", "linkage_specification", "declaration_list", "function_definition"], "target": " HLS_DLLESPEC void hls_restart(hlsHandle design_handle)\r\n {\r\n static_cast<HLS_Design*>(design_handle)->restart();\r\n }\r\n"}
|
| 36 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/syn/systemc/qam_dem_top.cpp", "target_type": "declaration", "cursor_line": 20, "target_nlines": 1, "node_depth": 3, "node_path": ["translation_unit", "namespace_definition", "declaration_list", "declaration"], "target": "const sc_logic qam_dem_top::ap_const_logic_0 = sc_dt::Log_0;\n"}
|
| 37 |
+
{"file": "VivadoHLS-QAM-SP605/QAMDemodulator/src/solution1/syn/systemc/qam_dem_top_mounstrito.cpp", "target_type": "function_definition", "cursor_line": 1312, "target_nlines": 3, "node_depth": 3, "node_path": ["translation_unit", "namespace_definition", "declaration_list", "function_definition"], "target": "void qam_dem_top_mounstrito::thread_OP2_V_i_cast_fu_325_p1() {\n OP2_V_i_cast_fu_325_p1 = esl_sext<27,12>(ph_in_i_V.read());\n}\n"}
|
| 38 |
+
{"file": "DRIM4HLS/caches/src/decode.h", "target_type": "if_statement", "cursor_line": 224, "target_nlines": 3, "node_depth": 9, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement", "labeled_statement", "while_statement", "compound_statement", "if_statement", "compound_statement", "if_statement"], "target": " if (feedinput_tmp.pc == load_pc && load_instruction) {\n load_instruction = false;\n }\n"}
|
| 39 |
+
{"file": "DRIM4HLS/caches/src/drim4hls.h", "target_type": "compound_statement", "cursor_line": 116, "target_nlines": 4, "node_depth": 3, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement"], "target": "\n // MEM\n wb.clk(clk);\n wb.rst(rst);\n"}
|
| 40 |
+
{"file": "DRIM4HLS/caches/src/drim4hls_datatypes.h", "target_type": "if_statement", "cursor_line": 284, "target_nlines": 2, "node_depth": 5, "node_path": ["translation_unit", "preproc_ifdef", "preproc_ifdef", "function_definition", "compound_statement", "if_statement"], "target": " if (!(rs2 == other.rs2))\n return false;\n"}
|
| 41 |
+
{"file": "DRIM4HLS/caches/src/execute.h", "target_type": "compound_statement", "cursor_line": 235, "target_nlines": 4, "node_depth": 2, "node_path": ["ERROR", "if_statement", "compound_statement"], "target": " #ifndef __SYNTHESIS__\n debug_exe_out_t.alu_src = \"ALUSRC_RS2\";\n #endif\n\n"}
|
| 42 |
+
{"file": "DRIM4HLS/caches/src/fetch.h", "target_type": "for_statement", "cursor_line": 178, "target_nlines": 5, "node_depth": 9, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement", "function_definition", "compound_statement", "labeled_statement", "while_statement", "compound_statement", "for_statement"], "target": "\t\t\t\tfor (m = 0; m < ICACHE_WAYS; m++) {\n\t\t\t\t\ticache_buffer_addr[k][m] = icache_buffer_addr[k-1][m];\n\t\t\t\t\ticache_buffer_instr[k][m] = icache_buffer_instr[k-1][m]; \n\t\t\t\t} \n\t\t\t}\n"}
|
| 43 |
+
{"file": "DRIM4HLS/caches/src/writeback.h", "target_type": "compound_statement", "cursor_line": 200, "target_nlines": 3, "node_depth": 16, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement", "function_definition", "compound_statement", "labeled_statement", "while_statement", "compound_statement", "if_statement", "compound_statement", "switch_statement", "compound_statement", "if_statement", "compound_statement", "if_statement", "compound_statement"], "target": " if (DCACHE_OFFSET_WIDTH) {\n\t\t\t\t\t\t\tdmem_dout.write_addr = 0;\n\t\t\t\t\t\t}\n"}
|
| 44 |
+
{"file": "DRIM4HLS/core/examples/binary_search/notmain.c", "target_type": "if_statement", "cursor_line": 23, "target_nlines": 4, "node_depth": 5, "node_path": ["translation_unit", "function_definition", "compound_statement", "while_statement", "compound_statement", "if_statement"], "target": " break;\n }\n else\n last = middle - 1;\n"}
|
| 45 |
+
{"file": "DRIM4HLS/core/examples/bubblesort/notmain.c", "target_type": "if_statement", "cursor_line": 31, "target_nlines": 3, "node_depth": 5, "node_path": ["translation_unit", "function_definition", "compound_statement", "for_statement", "compound_statement", "if_statement"], "target": " if(swapped==0) {\n break;\n }\n"}
|
| 46 |
+
{"file": "DRIM4HLS/core/examples/consecutive_branches/custom.c", "target_type": "declaration", "cursor_line": 5, "target_nlines": 1, "node_depth": 1, "node_path": ["translation_unit", "declaration"], "target": "void *custom();\n"}
|
| 47 |
+
{"file": "DRIM4HLS/core/examples/crc/crc.c", "target_type": "for_statement", "cursor_line": 14, "target_nlines": 4, "node_depth": 3, "node_path": ["translation_unit", "function_definition", "compound_statement", "for_statement"], "target": "\n //If the uppermost bit is a 1...\n if (remainder & 0x00000080) \n remainder ^= POLYNOMIAL;\n"}
|
| 48 |
+
{"file": "DRIM4HLS/core/examples/fibonacci/fibonacci.c", "target_type": "declaration", "cursor_line": 4, "target_nlines": 1, "node_depth": 1, "node_path": ["translation_unit", "declaration"], "target": "int x;\n"}
|
| 49 |
+
{"file": "DRIM4HLS/core/examples/insertion_sort/notmain.c", "target_type": "declaration", "cursor_line": 36, "target_nlines": 1, "node_depth": 3, "node_path": ["translation_unit", "function_definition", "compound_statement", "declaration"], "target": " int n = sizeof(array) / sizeof(array[0]);\n"}
|
| 50 |
+
{"file": "DRIM4HLS/core/examples/load_branch/custom.c", "target_type": "compound_statement", "cursor_line": 9, "target_nlines": 5, "node_depth": 2, "node_path": ["translation_unit", "function_definition", "compound_statement"], "target": "\t\n\tcustom();\n\t\n\treturn 0;\n}\n"}
|
| 51 |
+
{"file": "DRIM4HLS/core/examples/loads_stores/custom.c", "target_type": "declaration", "cursor_line": 5, "target_nlines": 1, "node_depth": 1, "node_path": ["translation_unit", "declaration"], "target": "void *custom();\n"}
|
| 52 |
+
{"file": "DRIM4HLS/core/examples/matrix_div/notmain.c", "target_type": "compound_statement", "cursor_line": 14, "target_nlines": 4, "node_depth": 4, "node_path": ["translation_unit", "function_definition", "compound_statement", "for_statement", "compound_statement"], "target": "\tfor (i = 1; i < DATA_SIZE; i++) {\n\t\n\t\tarray[i] = array[i] / array[i-1];\n\t}\n"}
|
| 53 |
+
{"file": "DRIM4HLS/core/examples/matrix_transpose/matrix_transpose.c", "target_type": "declaration", "cursor_line": 22, "target_nlines": 1, "node_depth": 5, "node_path": ["translation_unit", "function_definition", "compound_statement", "for_statement", "for_statement", "declaration"], "target": "\t\tfor (int j=0; j < N; j++)\n"}
|
| 54 |
+
{"file": "DRIM4HLS/core/examples/poly_eval/poly_eval.c", "target_type": "declaration", "cursor_line": 5, "target_nlines": 1, "node_depth": 1, "node_path": ["translation_unit", "declaration"], "target": "int result;\n"}
|
| 55 |
+
{"file": "DRIM4HLS/core/examples/shortest_path/shortest_path.c", "target_type": "compound_statement", "cursor_line": 21, "target_nlines": 4, "node_depth": 2, "node_path": ["translation_unit", "function_definition", "compound_statement"], "target": "\t\t\tmin = dist[v]; \n\t\t\tmin_index = v;\n\t\t}\n\treturn min_index;\n"}
|
| 56 |
+
{"file": "DRIM4HLS/core/src/decode.h", "target_type": "declaration", "cursor_line": 105, "target_nlines": 1, "node_depth": 4, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement", "declaration"], "target": "\tbool flush_tmp;\n"}
|
| 57 |
+
{"file": "DRIM4HLS/core/src/drim4hls.h", "target_type": "compound_statement", "cursor_line": 57, "target_nlines": 3, "node_depth": 3, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement"], "target": " Connections::Out < imem_in_t > CCS_INIT_S1(fe2imem_data);\n\n Connections::In < dmem_out_t > CCS_INIT_S1(dmem2wb_data);\n"}
|
| 58 |
+
{"file": "DRIM4HLS/core/src/drim4hls_datatypes.h", "target_type": "declaration", "cursor_line": 290, "target_nlines": 1, "node_depth": 3, "node_path": ["translation_unit", "preproc_ifdef", "preproc_ifdef", "declaration"], "target": " inline de_out_t & operator = (const de_out_t & other) {\n"}
|
| 59 |
+
{"file": "DRIM4HLS/core/src/execute.h", "target_type": "declaration", "cursor_line": 80, "target_nlines": 1, "node_depth": 1, "node_path": ["ERROR", "declaration"], "target": " de_out_t data_in;\n"}
|
| 60 |
+
{"file": "DRIM4HLS/core/src/fetch.h", "target_type": "function_definition", "cursor_line": 61, "target_nlines": 3, "node_depth": 2, "node_path": ["translation_unit", "preproc_ifdef", "function_definition"], "target": "\tsc_uint < PC_LEN > redirect_addr_tmp;\n\t\n bool freeze;\n"}
|
| 61 |
+
{"file": "DRIM4HLS/core/src/writeback.h", "target_type": "declaration", "cursor_line": 116, "target_nlines": 1, "node_depth": 9, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement", "function_definition", "compound_statement", "labeled_statement", "while_statement", "compound_statement", "declaration"], "target": " unsigned int aligned_address = input.alu_res.to_uint();\n"}
|
| 62 |
+
{"file": "DRIM4HLS/floating_point/src/decode.h", "target_type": "if_statement", "cursor_line": 417, "target_nlines": 4, "node_depth": 11, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement", "labeled_statement", "while_statement", "compound_statement", "if_statement", "else_clause", "if_statement", "compound_statement", "if_statement"], "target": " if (insn[31] == 0)\n extended = 0;\n else\n extended = 4294967295;\n"}
|
| 63 |
+
{"file": "DRIM4HLS/floating_point/src/drim4hls.h", "target_type": "declaration", "cursor_line": 73, "target_nlines": 1, "node_depth": 4, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement", "declaration"], "target": " writeback CCS_INIT_S1(wb);\n"}
|
| 64 |
+
{"file": "DRIM4HLS/floating_point/src/drim4hls_datatypes.h", "target_type": "declaration", "cursor_line": 1531, "target_nlines": 1, "node_depth": 3, "node_path": ["translation_unit", "preproc_ifdef", "preproc_ifdef", "declaration"], "target": " inline dcache_tag_t & operator = (const dcache_tag_t &other) {\n"}
|
| 65 |
+
{"file": "DRIM4HLS/floating_point/src/execute.h", "target_type": "compound_statement", "cursor_line": 125, "target_nlines": 3, "node_depth": 2, "node_path": ["ERROR", "function_definition", "compound_statement"], "target": "\n return u_div_res;\n }\n"}
|
| 66 |
+
{"file": "DRIM4HLS/floating_point/src/execute_fp.h", "target_type": "declaration", "cursor_line": 75, "target_nlines": 1, "node_depth": 1, "node_path": ["ERROR", "declaration"], "target": " exe_out_t output;\n"}
|
| 67 |
+
{"file": "DRIM4HLS/floating_point/src/fast_float.h", "target_type": "if_statement", "cursor_line": 727, "target_nlines": 3, "node_depth": 6, "node_path": ["translation_unit", "preproc_ifdef", "compound_statement", "compound_statement", "if_statement", "else_clause", "if_statement"], "target": " Far_large_is_mul = 0;\n\n }\n"}
|
| 68 |
+
{"file": "DRIM4HLS/floating_point/src/fetch.h", "target_type": "declaration", "cursor_line": 176, "target_nlines": 1, "node_depth": 9, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement", "function_definition", "compound_statement", "labeled_statement", "while_statement", "compound_statement", "declaration"], "target": "\t\t\tint n = 0;\n"}
|
| 69 |
+
{"file": "DRIM4HLS/floating_point/src/writeback.h", "target_type": "declaration", "cursor_line": 459, "target_nlines": 1, "node_depth": 6, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement", "function_definition", "compound_statement", "declaration"], "target": "\t\tint i = 0;\n"}
|
| 70 |
+
{"file": "DRIM4HLS/prediction/src/decode.h", "target_type": "compound_statement", "cursor_line": 680, "target_nlines": 3, "node_depth": 9, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement", "labeled_statement", "while_statement", "compound_statement", "case_statement", "if_statement", "compound_statement"], "target": " debug_dout_t.alu_op = \"ALUOP_SRAI\";\n debug_dout_t.alu_src = \"ALUSRC_IMM_U\";\n #endif\n"}
|
| 71 |
+
{"file": "DRIM4HLS/prediction/src/drim4hls.h", "target_type": "declaration", "cursor_line": 66, "target_nlines": 1, "node_depth": 4, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement", "declaration"], "target": " decode CCS_INIT_S1(dec);\n"}
|
| 72 |
+
{"file": "DRIM4HLS/prediction/src/drim4hls_datatypes.h", "target_type": "compound_statement", "cursor_line": 673, "target_nlines": 5, "node_depth": 4, "node_path": ["translation_unit", "preproc_ifdef", "preproc_ifdef", "function_definition", "compound_statement"], "target": " if (!(regfile_data == other.regfile_data))\n return false;\n if (!(ldst == other.ldst))\n return false;\n if (!(sync_fewb == other.sync_fewb))\n"}
|
| 73 |
+
{"file": "DRIM4HLS/prediction/src/execute.h", "target_type": "declaration", "cursor_line": 132, "target_nlines": 1, "node_depth": 1, "node_path": ["ERROR", "declaration"], "target": " div_res_t div_res;\n"}
|
| 74 |
+
{"file": "DRIM4HLS/prediction/src/fetch.h", "target_type": "declaration", "cursor_line": 136, "target_nlines": 1, "node_depth": 8, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement", "function_definition", "compound_statement", "labeled_statement", "compound_statement", "declaration"], "target": " int l = 0;\n"}
|
| 75 |
+
{"file": "DRIM4HLS/prediction/src/writeback.h", "target_type": "if_statement", "cursor_line": 199, "target_nlines": 3, "node_depth": 15, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement", "function_definition", "compound_statement", "labeled_statement", "while_statement", "compound_statement", "if_statement", "compound_statement", "switch_statement", "compound_statement", "if_statement", "compound_statement", "if_statement"], "target": " if (DCACHE_OFFSET_WIDTH) {\n\t\t\t\t\t\t\tdmem_dout.write_addr = 0;\n\t\t\t\t\t\t}\n"}
|
| 76 |
+
{"file": "DRIM4HLS/caches/src/top.cpp", "target_type": "compound_statement", "cursor_line": 93, "target_nlines": 2, "node_depth": 6, "node_path": ["translation_unit", "class_specifier", "field_declaration_list", "function_definition", "compound_statement", "labeled_statement", "compound_statement"], "target": " imem2de_ch.ResetWrite();\n fe2imem_ch.ResetRead();\n"}
|
| 77 |
+
{"file": "DRIM4HLS/core/src/top.cpp", "target_type": "declaration", "cursor_line": 56, "target_nlines": 1, "node_depth": 3, "node_path": ["translation_unit", "class_specifier", "field_declaration_list", "declaration"], "target": " SC_CTOR(Top);\n"}
|
| 78 |
+
{"file": "DRIM4HLS/floating_point/src/top.cpp", "target_type": "function_definition", "cursor_line": 97, "target_nlines": 4, "node_depth": 3, "node_path": ["translation_unit", "class_specifier", "field_declaration_list", "function_definition"], "target": " imem2de_ch.ResetWrite();\n fe2imem_ch.ResetRead();\n\n wait();\n"}
|
| 79 |
+
{"file": "DRIM4HLS/prediction/src/top.cpp", "target_type": "declaration", "cursor_line": 186, "target_nlines": 1, "node_depth": 5, "node_path": ["translation_unit", "class_specifier", "field_declaration_list", "function_definition", "compound_statement", "declaration"], "target": " unsigned address;\n"}
|
| 80 |
+
{"file": "Potholes/examples/image_access.c", "target_type": "compound_statement", "cursor_line": 110, "target_nlines": 4, "node_depth": 4, "node_path": ["translation_unit", "function_definition", "compound_statement", "if_statement", "compound_statement"], "target": " if(d==NULL) {\n printf(\"Cannot open display\\n\");\n exit(1);\n }\n"}
|
| 81 |
+
{"file": "Potholes/examples/image_access.h", "target_type": "declaration", "cursor_line": 4, "target_nlines": 1, "node_depth": 1, "node_path": ["translation_unit", "declaration"], "target": "void save_image(char * outputname);\n"}
|
| 82 |
+
{"file": "Potholes/examples/sob.c", "target_type": "compound_statement", "cursor_line": 12, "target_nlines": 3, "node_depth": 2, "node_path": ["translation_unit", "function_definition", "compound_statement"], "target": " assert(argv == 3);\n\n load_image(argc[1]); // load a png file from arg\n"}
|
| 83 |
+
{"file": "Potholes/src/include/options.h", "target_type": "field_declaration", "cursor_line": 29, "target_nlines": 1, "node_depth": 7, "node_path": ["translation_unit", "preproc_ifdef", "preproc_if", "linkage_specification", "declaration_list", "struct_specifier", "field_declaration_list", "field_declaration"], "target": "\tconst char **defines;\n"}
|
| 84 |
+
{"file": "Potholes/src/include/potholes/Initialization.h", "target_type": "declaration", "cursor_line": 15, "target_nlines": 1, "node_depth": 4, "node_path": ["translation_unit", "preproc_ifdef", "linkage_specification", "declaration_list", "declaration"], "target": " int Potholes_Unload(Tcl_Interp *);\n"}
|
| 85 |
+
{"file": "Potholes/src/include/potholes/affine.h", "target_type": "declaration", "cursor_line": 17, "target_nlines": 1, "node_depth": 2, "node_path": ["translation_unit", "preproc_ifdef", "declaration"], "target": "isl_ast_expr * pth_generate_access_expr(pth_ast_build * build, pth_scop * scop, pth_stmt * stmt, pth_expr * expr );\n"}
|
| 86 |
+
{"file": "Potholes/src/include/potholes/analysis.h", "target_type": "function_definition", "cursor_line": 36, "target_nlines": 3, "node_depth": 2, "node_path": ["translation_unit", "preproc_ifdef", "function_definition"], "target": " isl_ctx * ctx;\n potholes::ExtractScop::ScopMap sm;\n potholes::ExtractScop::Locations ld;\n"}
|
| 87 |
+
{"file": "Potholes/src/include/potholes/ast.h", "target_type": "declaration", "cursor_line": 115, "target_nlines": 2, "node_depth": 2, "node_path": ["translation_unit", "preproc_ifdef", "declaration"], "target": "__isl_give pth_ast_expr *pth_ast_expr_alloc_op(isl_ctx *ctx,\n\tenum isl_ast_op_type op, int n_arg);\n"}
|
| 88 |
+
{"file": "Potholes/src/include/potholes/consumer.h", "target_type": "declaration", "cursor_line": 34, "target_nlines": 1, "node_depth": 6, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement", "function_definition", "compound_statement", "declaration"], "target": " virtual bool HandleTopLevelDecl(clang::DeclGroupRef) = 0;\n"}
|
| 89 |
+
{"file": "Potholes/src/include/potholes/extract.h", "target_type": "declaration", "cursor_line": 84, "target_nlines": 1, "node_depth": 6, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement", "function_definition", "compound_statement", "declaration"], "target": " void operator() (std::string filename);\n"}
|
| 90 |
+
{"file": "Potholes/src/include/potholes/function.h", "target_type": "function_definition", "cursor_line": 17, "target_nlines": 2, "node_depth": 5, "node_path": ["translation_unit", "preproc_ifdef", "preproc_ifdef", "linkage_specification", "declaration_list", "function_definition"], "target": " struct pth_ast_node_param { \n pth_ast_node_param_type type;\n"}
|
| 91 |
+
{"file": "Potholes/src/include/potholes/generate.h", "target_type": "declaration", "cursor_line": 55, "target_nlines": 1, "node_depth": 2, "node_path": ["translation_unit", "preproc_ifdef", "declaration"], "target": "isl_ast_expr * pth_generate_ast_expr_access(pth_ast_build*, pth_scop*, pth_stmt*, pth_expr*);\n"}
|
| 92 |
+
{"file": "Potholes/src/include/potholes/options.h", "target_type": "declaration", "cursor_line": 15, "target_nlines": 1, "node_depth": 5, "node_path": ["translation_unit", "preproc_ifdef", "preproc_ifdef", "linkage_specification", "declaration_list", "declaration"], "target": "isl_ctx * build_options(int n_paths, const char ** paths);\n"}
|
| 93 |
+
{"file": "Potholes/src/include/potholes/parallel.h", "target_type": "declaration", "cursor_line": 21, "target_nlines": 1, "node_depth": 2, "node_path": ["translation_unit", "preproc_ifdef", "declaration"], "target": "bool pth_loop_is_parallel(pth_ast_build *, pth_scop *);\n"}
|
| 94 |
+
{"file": "Potholes/src/include/potholes/parameters.h", "target_type": "compound_statement", "cursor_line": 33, "target_nlines": 4, "node_depth": 3, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement"], "target": " static int Compile(ClientData, Tcl_Interp * , int, const char * argv[]);\n static int Get(ClientData, Tcl_Interp * , int, const char * argv[]);\n \n};\n"}
|
| 95 |
+
{"file": "Potholes/src/include/potholes/process.h", "target_type": "declaration", "cursor_line": 15, "target_nlines": 1, "node_depth": 2, "node_path": ["translation_unit", "preproc_ifdef", "declaration"], "target": "void compile_source_file(isl_ctx * ctx, int, const char **);\n"}
|
| 96 |
+
{"file": "Potholes/src/include/potholes/project.h", "target_type": "function_definition", "cursor_line": 28, "target_nlines": 3, "node_depth": 4, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement", "function_definition"], "target": " ~Project();\n potholes::Analysis * getAnalysis();\n static int Compile(ClientData, Tcl_Interp * , int, const char * argv[]);\n"}
|
| 97 |
+
{"file": "Potholes/src/include/potholes/region.h", "target_type": "compound_statement", "cursor_line": 44, "target_nlines": 5, "node_depth": 3, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement"], "target": " class FileRegion : public BufferedRegion { \n public :\n \n // does depth first traversal of buffers calling decompose\n \n"}
|
| 98 |
+
{"file": "Potholes/src/include/potholes/register.h", "target_type": "function_definition", "cursor_line": 18, "target_nlines": 3, "node_depth": 4, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement", "function_definition"], "target": "template<typename T> std::string Register(std::string name) {\n potholes::Analysis::Registry * reg = potholes::Analysis::Registry::instance();\n TransformFactory<T> * factory = new TransformFactory<T>();\n"}
|
| 99 |
+
{"file": "Potholes/src/include/potholes/relation.h", "target_type": "function_definition", "cursor_line": 13, "target_nlines": 5, "node_depth": 4, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement", "function_definition"], "target": " class Relation {\n public:\n typedef enum {\n Parent, Child, Equivalent, Replacement, Insertion, Next\n } Type;\n"}
|
| 100 |
+
{"file": "Potholes/src/include/potholes/rewrite.h", "target_type": "declaration", "cursor_line": 30, "target_nlines": 1, "node_depth": 7, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement", "function_definition", "compound_statement", "labeled_statement", "declaration"], "target": " Analysis::Files transformed_files;\n"}
|
| 101 |
+
{"file": "Potholes/src/include/potholes/scop.h", "target_type": "declaration", "cursor_line": 23, "target_nlines": 1, "node_depth": 7, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement", "compound_statement", "labeled_statement", "labeled_statement", "declaration"], "target": " std::string filename;\n"}
|
| 102 |
+
{"file": "Potholes/src/include/potholes/statement.h", "target_type": "declaration", "cursor_line": 22, "target_nlines": 1, "node_depth": 2, "node_path": ["translation_unit", "preproc_ifdef", "declaration"], "target": "isl_id * pth_memory_space_id();\n"}
|
| 103 |
+
{"file": "Potholes/src/include/potholes/tclBackedObject.h", "target_type": "declaration", "cursor_line": 30, "target_nlines": 1, "node_depth": 7, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement", "compound_statement", "function_definition", "compound_statement", "declaration"], "target": " T * obj = new T(argc, argv);\n"}
|
| 104 |
+
{"file": "Potholes/src/include/potholes/transform.h", "target_type": "declaration", "cursor_line": 25, "target_nlines": 1, "node_depth": 5, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement", "compound_statement", "declaration"], "target": " virtual void Initialize(clang::ASTContext& Context) = 0;\n"}
|
| 105 |
+
{"file": "Potholes/src/include/potholes/visitor.h", "target_type": "function_definition", "cursor_line": 17, "target_nlines": 3, "node_depth": 4, "node_path": ["translation_unit", "preproc_ifdef", "function_definition", "compound_statement", "function_definition"], "target": " class Visitor : public clang::RecursiveASTVisitor<Potholes::Visitor>{ \n \n };\n"}
|
| 106 |
+
{"file": "Potholes/src/options.c", "target_type": "declaration", "cursor_line": 32, "target_nlines": 1, "node_depth": 3, "node_path": ["translation_unit", "function_definition", "compound_statement", "declaration"], "target": " isl_ctx * pet_ctx = isl_ctx_alloc_with_options(&options_args, options);\n"}
|
| 107 |
+
{"file": "Potholes/src/affine.cxx", "target_type": "declaration", "cursor_line": 60, "target_nlines": 1, "node_depth": 3, "node_path": ["translation_unit", "function_definition", "compound_statement", "declaration"], "target": " isl_aff * aff = isl_aff_zero_on_domain(isl_local_space_from_space(bounded_space));\n"}
|
| 108 |
+
{"file": "Potholes/src/analysis.cxx", "target_type": "compound_statement", "cursor_line": 124, "target_nlines": 4, "node_depth": 2, "node_path": ["translation_unit", "function_definition", "compound_statement"], "target": " potholes::PromoteScop * transform = new potholes::PromoteScop(*analysis);\n\t analysis->registerTransform(transform);\n } else { \n std::cerr << \"Can't find Scop\" << std::endl;\n"}
|
| 109 |
+
{"file": "Potholes/src/ast.cxx", "target_type": "declaration", "cursor_line": 199, "target_nlines": 1, "node_depth": 3, "node_path": ["translation_unit", "function_definition", "compound_statement", "declaration"], "target": " pth_scop * scop = (pth_scop *)(malloc(sizeof(pet_scop)));\n"}
|
| 110 |
+
{"file": "Potholes/src/consumer.cxx", "target_type": "declaration", "cursor_line": 49, "target_nlines": 1, "node_depth": 5, "node_path": ["translation_unit", "function_definition", "compound_statement", "for_statement", "compound_statement", "declaration"], "target": " potholes::Transform * transform = *cit;\n"}
|
| 111 |
+
{"file": "Potholes/src/extract.cxx", "target_type": "compound_statement", "cursor_line": 90, "target_nlines": 3, "node_depth": 10, "node_path": ["translation_unit", "function_definition", "compound_statement", "if_statement", "compound_statement", "for_statement", "compound_statement", "if_statement", "compound_statement", "if_statement", "compound_statement"], "target": " if (candidate_offset == 0) { \n candidate_location = sm.getLocForStartOfFile(sm.getFileID(*slit));\n }\n"}
|
| 112 |
+
{"file": "Potholes/src/generate.cxx", "target_type": "declaration", "cursor_line": 132, "target_nlines": 1, "node_depth": 3, "node_path": ["translation_unit", "function_definition", "compound_statement", "declaration"], "target": " isl_id * mem = pth_memory_space_id();\n"}
|
| 113 |
+
{"file": "Potholes/src/parallel.cxx", "target_type": "function_definition", "cursor_line": 106, "target_nlines": 4, "node_depth": 1, "node_path": ["translation_unit", "function_definition"], "target": " \n assert(success == 0);\n return scop;\n}\n"}
|
| 114 |
+
{"file": "Potholes/src/potholes-promote-functions.cxx", "target_type": "declaration", "cursor_line": 45, "target_nlines": 1, "node_depth": 3, "node_path": ["translation_unit", "function_definition", "compound_statement", "declaration"], "target": " isl_ctx * ctx = isl_ctx_alloc();\n"}
|
| 115 |
+
{"file": "Potholes/src/potholes.cxx", "target_type": "compound_statement", "cursor_line": 61, "target_nlines": 3, "node_depth": 4, "node_path": ["translation_unit", "function_definition", "compound_statement", "if_statement", "compound_statement"], "target": " if (Itcl_RegisterC(interp, \"project_initialize\", Project::Create, 0, 0) != TCL_OK) { \n return TCL_ERROR;\n }\n"}
|
| 116 |
+
{"file": "Potholes/src/process.cxx", "target_type": "declaration", "cursor_line": 84, "target_nlines": 1, "node_depth": 3, "node_path": ["translation_unit", "function_definition", "compound_statement", "declaration"], "target": " ct::CommonOptionsParser OptionsParser(argc, argv);\n"}
|
| 117 |
+
{"file": "Potholes/src/project.cxx", "target_type": "declaration", "cursor_line": 96, "target_nlines": 1, "node_depth": 7, "node_path": ["translation_unit", "function_definition", "compound_statement", "if_statement", "else_clause", "if_statement", "compound_statement", "declaration"], "target": "\tTcl_Obj ** objects = (Tcl_Obj **)(malloc(sizeof(Tcl_Obj *) * flags.size()));\n"}
|
| 118 |
+
{"file": "Potholes/src/promote.cxx", "target_type": "for_statement", "cursor_line": 78, "target_nlines": 3, "node_depth": 3, "node_path": ["translation_unit", "function_definition", "compound_statement", "for_statement"], "target": "\n clang::SourceManager & sm = rewriter.getSourceMgr();\n clang::SourceManager::fileinfo_iterator fit;\n"}
|
| 119 |
+
{"file": "Potholes/src/region.cxx", "target_type": "compound_statement", "cursor_line": 11, "target_nlines": 3, "node_depth": 2, "node_path": ["translation_unit", "function_definition", "compound_statement"], "target": " \n Return rewritten buffer from rewriter\n \n"}
|
| 120 |
+
{"file": "Potholes/src/rewrite.cxx", "target_type": "declaration", "cursor_line": 106, "target_nlines": 1, "node_depth": 5, "node_path": ["translation_unit", "function_definition", "compound_statement", "for_statement", "compound_statement", "declaration"], "target": " potholes::Transform * transform = *cit;\n"}
|
| 121 |
+
{"file": "Potholes/src/scop.cxx", "target_type": "declaration", "cursor_line": 15, "target_nlines": 1, "node_depth": 3, "node_path": ["translation_unit", "function_definition", "compound_statement", "declaration"], "target": " Tcl_Obj * filename_obj = Tcl_NewStringObj(string.c_str(), -1);\n"}
|
| 122 |
+
{"file": "Potholes/src/statement.cxx", "target_type": "declaration", "cursor_line": 184, "target_nlines": 1, "node_depth": 3, "node_path": ["translation_unit", "function_definition", "compound_statement", "declaration"], "target": " isl_space * space = isl_pw_aff_get_space(pa);\n"}
|
| 123 |
+
{"file": "Potholes/src/transform.cxx", "target_type": "compound_statement", "cursor_line": 4, "target_nlines": 5, "node_depth": 2, "node_path": ["translation_unit", "function_definition", "compound_statement"], "target": " potholes::Transform::Transform(Analysis& analysis) :analysis(analysis) {\n \n \n \n }"}
|
hls/valid_content.jsonl
ADDED
|
@@ -0,0 +1,3 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
version https://git-lfs.github.com/spec/v1
|
| 2 |
+
oid sha256:208da91fea9c54778727eb5561342050dff1322a8b74cbe284218a485a08916d
|
| 3 |
+
size 29491805
|
original_repo/README.md
ADDED
|
@@ -0,0 +1,3 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# Original repository archive
|
| 2 |
+
|
| 3 |
+
The full MHRC-Bench `original_repo/collected_repos.tar.gz` file is not included in this compact sample because it is about 33 GB by itself. The JSONL content files include the completion contexts needed for sample inspection and lightweight experiments.
|
sample_manifest.json
ADDED
|
@@ -0,0 +1,190 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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source_readme
ADDED
|
@@ -0,0 +1 @@
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|
| 1 |
+
readme
|
systemverilog/test.jsonl
ADDED
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The diff for this file is too large to render.
See raw diff
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systemverilog/test_content_classfied.jsonl
ADDED
|
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| 1 |
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version https://git-lfs.github.com/spec/v1
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| 2 |
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oid sha256:ba05f46cb85fb8ee3671c78902da98950a24966f199147d7ee163337915bc2e8
|
| 3 |
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size 18923574
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systemverilog/train.jsonl
ADDED
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|
systemverilog/train_content.jsonl
ADDED
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systemverilog/valid.jsonl
ADDED
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@@ -0,0 +1,107 @@
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|
| 1 |
+
{"file": "tiny-tpu-old/src/accumulator.sv", "target_type": "module_declaration", "cursor_line": 23, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " for (i = 0; i < 2; i = i + 1) begin\n"}
|
| 2 |
+
{"file": "tiny-tpu-old/src/control_unit.sv", "target_type": "case_statement", "cursor_line": 105, "target_nlines": 1, "node_depth": 31, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement", "case_item", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " state <= FETCH;\n"}
|
| 3 |
+
{"file": "tiny-tpu-old/src/dma.sv", "target_type": "module_declaration", "cursor_line": 14, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " output wire [3:0] dma_address\n);\n\n // Combinational logic for outputs\n"}
|
| 4 |
+
{"file": "tiny-tpu-old/src/input_setup.sv", "target_type": "module_declaration", "cursor_line": 32, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " counter <= 3'b0;\n a_in1 <= 8'b0;\n a_in2 <= 8'b0;\n state <= IDLE; \n"}
|
| 5 |
+
{"file": "tiny-tpu-old/src/mmu.sv", "target_type": "module_declaration", "cursor_line": 30, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " .load_weight(load_weight),\n .valid(valid),\n .a_in(a_in1),\n"}
|
| 6 |
+
{"file": "tiny-tpu-old/src/processing_element.sv", "target_type": "module_declaration", "cursor_line": 13, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n output reg [7:0] a_out, // Output A to right neighbor\n output reg [7:0] acc_out // Accumulated value to the PE below\n);\n"}
|
| 7 |
+
{"file": "tiny-tpu-old/src/tpu.sv", "target_type": "module_declaration", "cursor_line": 151, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " .reset(reset),\n"}
|
| 8 |
+
{"file": "tiny-tpu-old/src/tt_um_tpu.sv", "target_type": "module_declaration", "cursor_line": 17, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input wire reset // rst_n - low to reset --> // TODO: rename back to rst_n!\n"}
|
| 9 |
+
{"file": "tiny-tpu-old/src/unified_buffer.sv", "target_type": "module_declaration", "cursor_line": 18, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input wire store, // flag for storing data from accumulators to unified buffer\n input wire ext, // flag for output to host computer\n\n input wire [7:0] acc1_mem_0,\n"}
|
| 10 |
+
{"file": "tiny-tpu-old/src/weight_memory.sv", "target_type": "module_declaration", "cursor_line": 29, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " weight4 <= 8'b0;\n\n end else if (fetch_w) begin // READ data into weight memory \n memory[dma_address] <= ui_in;\n"}
|
| 11 |
+
{"file": "tiny-tpu-old/test/dump_acc.sv", "target_type": "module_declaration", "cursor_line": 1, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "module dump();\n initial begin\n $dumpfile (\"acc.vcd\");\n $dumpvars (0, accumulator);\n"}
|
| 12 |
+
{"file": "tiny-tpu-old/test/dump_dma.sv", "target_type": "module_declaration", "cursor_line": 8, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " $dumpvars(0, dma.test_storage[2]);\n $dumpvars(0, dma.test_storage[3]);\n\n $dumpvars(0, dma.test_storage[4]);\n"}
|
| 13 |
+
{"file": "tiny-tpu-old/test/dump_is.sv", "target_type": "module_declaration", "cursor_line": 5, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " #1;\n end\nendmodule\n"}
|
| 14 |
+
{"file": "tiny-tpu-old/test/dump_mmu.sv", "target_type": "module_declaration", "cursor_line": 1, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "module dump();\n initial begin\n $dumpfile (\"mmu.vcd\");\n"}
|
| 15 |
+
{"file": "tiny-tpu-old/test/dump_tpu.sv", "target_type": "module_declaration", "cursor_line": 4, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " $dumpvars (0, tpu);\n #1;\n end\nendmodule\n"}
|
| 16 |
+
{"file": "tiny-tpu-old/test/dump_tt_um_tpu.sv", "target_type": "module_declaration", "cursor_line": 2, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " initial begin\n $dumpfile (\"tt_um_tpu.vcd\");\n $dumpvars (0, tt_um_tpu);\n #1;\n end\n"}
|
| 17 |
+
{"file": "tiny-tpu-old/test/dump_weight_memory.sv", "target_type": "module_declaration", "cursor_line": 10, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " $dumpvars (0, weight_memory.memory[3]);\n"}
|
| 18 |
+
{"file": "usb20dev/rtl/usb.sv", "target_type": "module_declaration", "cursor_line": 33, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "endmodule : usb\n"}
|
| 19 |
+
{"file": "usb20dev/rtl/usb_crc16.sv", "target_type": "module_declaration", "cursor_line": 74, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\nalways_ff @(posedge clk or posedge rst)\nbegin\n"}
|
| 20 |
+
{"file": "usb20dev/rtl/usb_crc5.sv", "target_type": "module_declaration", "cursor_line": 26, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "//-----------------------------------------------------------------------------\n// Data serializer\n//-----------------------------------------------------------------------------\nbus8_t dbyte;\nlogic dbit;\n"}
|
| 21 |
+
{"file": "usb20dev/rtl/usb_fe_if.sv", "target_type": "simple_identifier", "cursor_line": 22, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "interface_declaration", "interface_item", "modport_declaration", "modport_item", "modport_ports_declaration", "modport_simple_ports_declaration", "modport_simple_port", "port_identifier", "simple_identifier"], "target": " output tx_oen,\n"}
|
| 22 |
+
{"file": "usb20dev/rtl/usb_pkg.sv", "target_type": "primary_literal", "cursor_line": 15, "target_nlines": 1, "node_depth": 10, "node_path": ["source_file", "package_declaration", "package_or_generate_item_declaration", "data_declaration", "type_declaration", "data_type", "packed_dimension", "constant_range", "constant_expression", "constant_primary", "primary_literal"], "target": "typedef logic [31:0] bus32_t;\n"}
|
| 23 |
+
{"file": "usb20dev/rtl/usb_sie.sv", "target_type": "module_declaration", "cursor_line": 44, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " .bus_reset (sie_bus.reset) // o: Bus reset active\n);\n"}
|
| 24 |
+
{"file": "usb20dev/rtl/usb_sie_if.sv", "target_type": "simple_identifier", "cursor_line": 72, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "interface_declaration", "interface_item", "modport_declaration", "modport_item", "modport_ports_declaration", "modport_simple_ports_declaration", "modport_simple_port", "port_identifier", "simple_identifier"], "target": " output rx_error\n"}
|
| 25 |
+
{"file": "usb20dev/rtl/usb_sie_rx.sv", "target_type": "case_statement", "cursor_line": 298, "target_nlines": 3, "node_depth": 22, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "\n STRIP_EOP_S : begin\n data_valid = 'b0;\n"}
|
| 26 |
+
{"file": "usb20dev/rtl/usb_sie_tx.sv", "target_type": "module_declaration", "cursor_line": 41, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " TX_DATA_WAIT_S,\n XXX_S = 'x\n"}
|
| 27 |
+
{"file": "usb20dev/verif/helpers/usb_host_beh.sv", "target_type": "module_declaration", "cursor_line": 18, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "// USB FS 12.000 Mb/s +-0.25% (+-208ps)\nlocalparam USB_PERIOD = 83333; // ps\nlocalparam USB_JIT = 100; // ps\n`define USB_PERIOD_DEL ((USB_PERIOD + ($urandom_range(0, USB_JIT*2) - USB_JIT))/1000.0)\n"}
|
| 28 |
+
{"file": "usb20dev/verif/helpers/usb_sie_vip.sv", "target_type": "module_declaration", "cursor_line": 41, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " sie_bus.tx_data = data[i];\n sie_bus.tx_valid = 1'b1;\n"}
|
| 29 |
+
{"file": "usb20dev/verif/testbenches/crc/tb.sv", "target_type": "simple_identifier", "cursor_line": 22, "target_nlines": 1, "node_depth": 4, "node_path": ["source_file", "package_or_generate_item_declaration", "net_declaration", "ERROR", "simple_identifier"], "target": " .clk (tb_clk),\n"}
|
| 30 |
+
{"file": "usb20dev/verif/testbenches/example/tb.sv", "target_type": "simple_identifier", "cursor_line": 37, "target_nlines": 1, "node_depth": 1, "node_path": ["ERROR", "simple_identifier"], "target": "`include \"../testbenches/tb_footer.svh\"\n"}
|
| 31 |
+
{"file": "usb20dev/verif/testbenches/sie/tb.sv", "target_type": "function_statement", "cursor_line": 78, "target_nlines": 1, "node_depth": 8, "node_path": ["ERROR", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement"], "target": " is_data_eq = 1;\n"}
|
| 32 |
+
{"file": "usb20dev/verif/testbenches/tb_dut_usb.svh", "target_type": "simple_identifier", "cursor_line": 6, "target_nlines": 1, "node_depth": 3, "node_path": ["source_file", "package_or_generate_item_declaration", "net_declaration", "simple_identifier"], "target": "usb dut (\n"}
|
| 33 |
+
{"file": "usb20dev/verif/testbenches/tb_footer.svh", "target_type": "simple_identifier", "cursor_line": 34, "target_nlines": 1, "node_depth": 11, "node_path": ["source_file", "package_or_generate_item_declaration", "data_declaration", "ERROR", "delay_control", "mintypmax_expression", "expression", "primary", "primary_literal", "simple_text_macro_usage", "text_macro_identifier", "simple_identifier"], "target": " #(`STOP_TIME);\n"}
|
| 34 |
+
{"file": "usb20dev/verif/testbenches/tb_header.svh", "target_type": "simple_identifier", "cursor_line": 26, "target_nlines": 1, "node_depth": 6, "node_path": ["ERROR", "module_or_generate_item", "package_or_generate_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "simple_identifier"], "target": "logic tb_clk = 0;\n"}
|
| 35 |
+
{"file": "UVM_Verification/rcc_agent.sv", "target_type": "simple_identifier", "cursor_line": 8, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_property", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "simple_identifier"], "target": "\tuvm_analysis_port #(rcc_transaction) mon2ref;\n"}
|
| 36 |
+
{"file": "UVM_Verification/rcc_assertions.sv", "target_type": "module_declaration", "cursor_line": 31, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " disable iff (intf.reset) $rose(intf.rcc_clk) |=> !$isunknown(intf.din);\n endproperty\n\n"}
|
| 37 |
+
{"file": "UVM_Verification/rcc_config.sv", "target_type": "primary", "cursor_line": 5, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "class_constructor_declaration", "list_of_arguments_parent", "expression", "primary"], "target": "\t\tsuper.new(name);\n"}
|
| 38 |
+
{"file": "UVM_Verification/rcc_driver.sv", "target_type": "primary", "cursor_line": 36, "target_nlines": 1, "node_depth": 4, "node_path": ["ERROR", "ERROR", "mintypmax_expression", "expression", "primary"], "target": "\t\t if(!uvm_config_db#(virtual rcc_if)::get(this, \"\", \"vif\", vif))\n"}
|
| 39 |
+
{"file": "UVM_Verification/rcc_environment.sv", "target_type": "simple_identifier", "cursor_line": 20, "target_nlines": 1, "node_depth": 17, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "blocking_assignment", "operator_assignment", "expression", "primary", "let_expression", "let_list_of_arguments", "simple_identifier"], "target": " rcc_cov = rcc_in_coverage::type_id::create(.name(\"rcc_cov\"), .parent(this));\n"}
|
| 40 |
+
{"file": "UVM_Verification/rcc_if.sv", "target_type": "simple_identifier", "cursor_line": 12, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "interface_declaration", "interface_or_generate_item", "package_or_generate_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "simple_identifier"], "target": " logic [15:0] din;\n"}
|
| 41 |
+
{"file": "UVM_Verification/rcc_in_coverage.sv", "target_type": "simple_identifier", "cursor_line": 10, "target_nlines": 1, "node_depth": 8, "node_path": ["ERROR", "class_item", "class_property", "data_declaration", "data_type_or_implicit1", "data_type", "class_type", "class_identifier", "simple_identifier"], "target": " uvm_tlm_analysis_fifo #(rcc_transaction) cov_addr_fifo;\n"}
|
| 42 |
+
{"file": "UVM_Verification/rcc_monitor.sv", "target_type": "primary", "cursor_line": 28, "target_nlines": 1, "node_depth": 2, "node_path": ["ERROR", "ERROR", "primary"], "target": " `uvm_fatal(\"No Vif\", {\"virtual interface must be set for: \", get_full_name(), \".vif\"});\n"}
|
| 43 |
+
{"file": "UVM_Verification/rcc_out_coverage.sv", "target_type": "simple_identifier", "cursor_line": 98, "target_nlines": 1, "node_depth": 6, "node_path": ["ERROR", "class_item", "class_property", "data_declaration", "data_type_or_implicit1", "data_type", "simple_identifier"], "target": " bins out_ref_pound = {35};\n"}
|
| 44 |
+
{"file": "UVM_Verification/rcc_pkg.sv", "target_type": "simple_identifier", "cursor_line": 1, "target_nlines": 1, "node_depth": 3, "node_path": ["source_file", "package_declaration", "package_identifier", "simple_identifier"], "target": "package rcc_pkg;\n"}
|
| 45 |
+
{"file": "UVM_Verification/rcc_scoreboard.sv", "target_type": "simple_identifier", "cursor_line": 11, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_property", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "simple_identifier"], "target": " uvm_analysis_export #(rcc_transaction) out_ref;\n"}
|
| 46 |
+
{"file": "UVM_Verification/rcc_sequencer.sv", "target_type": "data_type", "cursor_line": 39, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "class_constructor_declaration", "tf_port_list", "tf_port_item1", "data_type_or_implicit1", "data_type"], "target": "\tfunction new(string name = \"\");\n"}
|
| 47 |
+
{"file": "UVM_Verification/rcc_tb_top.sv", "target_type": "module_declaration", "cursor_line": 23, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " // coverage instance for coverage result display\n rcc_in_coverage cov_in;\n"}
|
| 48 |
+
{"file": "UVM_Verification/rcc_test.sv", "target_type": "data_type", "cursor_line": 25, "target_nlines": 1, "node_depth": 10, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "task_declaration", "task_body_declaration", "tf_port_list", "tf_port_item1", "data_type_or_implicit1", "data_type"], "target": "\ttask run_phase(uvm_phase phase);\n"}
|
| 49 |
+
{"file": "UVM_Verification/ref_pred.sv", "target_type": "data_type", "cursor_line": 17, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_property", "data_declaration", "data_type_or_implicit1", "data_type"], "target": " integer ref_out;\n"}
|
| 50 |
+
{"file": "UVM_Verification/results_conv.v", "target_type": "case_statement", "cursor_line": 364, "target_nlines": 4, "node_depth": 22, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " end\n else\n state <= `IDLE ;\n end\n"}
|
| 51 |
+
{"file": "UVM_Verification/results_conv_test.sv", "target_type": "module_declaration", "cursor_line": 62, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " g_din[15:0] = 16'b0000000000000000;\n\n rcc_clk = 1'b0;\n test_mode = 1'b0;\n"}
|
| 52 |
+
{"file": "UVM_Verification/results_conv_test.v", "target_type": "module_declaration", "cursor_line": 118, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "always @(posedge digit_clk)\nbegin\n"}
|
| 53 |
+
{"file": "easyUVM/adder.sv", "target_type": "module_declaration", "cursor_line": 12, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " INITIAL: begin\n inter.ready <= 1;\n state <= WAIT;\n"}
|
| 54 |
+
{"file": "easyUVM/agent.sv", "target_type": "simple_identifier", "cursor_line": 19, "target_nlines": 1, "node_depth": 18, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "blocking_assignment", "operator_assignment", "expression", "primary", "function_subroutine_call", "subroutine_call", "tf_call", "simple_identifier"], "target": " drv = driver::type_id::create(\"drv\", this);\n"}
|
| 55 |
+
{"file": "easyUVM/agent_out.sv", "target_type": "simple_identifier", "cursor_line": 9, "target_nlines": 1, "node_depth": 10, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "class_constructor_declaration", "tf_port_list", "tf_port_item1", "data_type_or_implicit1", "data_type", "simple_identifier"], "target": " function new(string name = \"agent_out\", uvm_component parent = null);\n"}
|
| 56 |
+
{"file": "easyUVM/comparator.sv", "target_type": "primary", "cursor_line": 61, "target_nlines": 1, "node_depth": 13, "node_path": ["ERROR", "function_statement_or_null", "function_statement", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "checker_instantiation", "event_expression", "event_expression", "expression", "primary"], "target": " uvm_report_fatal(\"No expect transaction to compare with\", \"\");\n"}
|
| 57 |
+
{"file": "easyUVM/driver.sv", "target_type": "primary", "cursor_line": 14, "target_nlines": 1, "node_depth": 2, "node_path": ["ERROR", "ERROR", "primary"], "target": " assert(uvm_config_db#(input_vif)::get(this, \"\", \"vif\", vif));\n"}
|
| 58 |
+
{"file": "easyUVM/driver_out.sv", "target_type": "simple_identifier", "cursor_line": 13, "target_nlines": 1, "node_depth": 4, "node_path": ["ERROR", "ERROR", "class_type", "class_identifier", "simple_identifier"], "target": " assert(uvm_config_db#(output_vif)::get(this, \"\", \"vif\", vif));\n"}
|
| 59 |
+
{"file": "easyUVM/env.sv", "target_type": "simple_identifier", "cursor_line": 29, "target_nlines": 1, "node_depth": 10, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "function_declaration", "function_body_declaration", "ERROR", "clockvar_expression", "clockvar", "simple_identifier"], "target": " rfm.in.connect(to_refmod.get_export);\n"}
|
| 60 |
+
{"file": "easyUVM/input_if.sv", "target_type": "simple_identifier", "cursor_line": 5, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "interface_declaration", "modport_declaration", "modport_item", "modport_ports_declaration", "modport_simple_ports_declaration", "modport_simple_port", "port_identifier", "simple_identifier"], "target": " modport port(input clk, rst, A, B, valid, output ready);\n"}
|
| 61 |
+
{"file": "easyUVM/monitor.sv", "target_type": "simple_identifier", "cursor_line": 8, "target_nlines": 1, "node_depth": 8, "node_path": ["ERROR", "class_item", "class_method", "class_constructor_declaration", "tf_port_list", "tf_port_item1", "data_type_or_implicit1", "data_type", "simple_identifier"], "target": " function new(string name, uvm_component parent);\n"}
|
| 62 |
+
{"file": "easyUVM/monitor_out.sv", "target_type": "simple_identifier", "cursor_line": 3, "target_nlines": 1, "node_depth": 6, "node_path": ["ERROR", "class_item", "class_property", "data_declaration", "data_type_or_implicit1", "data_type", "simple_identifier"], "target": " output_vif vif;\n"}
|
| 63 |
+
{"file": "easyUVM/output_if.sv", "target_type": "simple_identifier", "cursor_line": 1, "target_nlines": 1, "node_depth": 6, "node_path": ["source_file", "interface_declaration", "interface_ansi_header", "list_of_port_declarations", "ansi_port_declaration", "port_identifier", "simple_identifier"], "target": "interface output_if(input clk, rst);\n"}
|
| 64 |
+
{"file": "easyUVM/packet_in.sv", "target_type": "simple_identifier", "cursor_line": 7, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "text_macro_usage", "list_of_actual_arguments", "expression", "expression", "primary", "simple_identifier"], "target": " `uvm_field_int(B, UVM_ALL_ON|UVM_HEX)\n"}
|
| 65 |
+
{"file": "easyUVM/packet_out.sv", "target_type": "simple_identifier", "cursor_line": 8, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "class_constructor_declaration", "tf_port_list", "tf_port_item1", "port_identifier", "simple_identifier"], "target": " function new(string name=\"packet_out\");\n"}
|
| 66 |
+
{"file": "easyUVM/refmod.sv", "target_type": "primary_literal", "cursor_line": 20, "target_nlines": 1, "node_depth": 21, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "blocking_assignment", "operator_assignment", "expression", "primary", "function_subroutine_call", "subroutine_call", "tf_call", "list_of_arguments_parent", "expression", "primary", "primary_literal"], "target": " tr_out = packet_out::type_id::create(\"tr_out\", this);\n"}
|
| 67 |
+
{"file": "easyUVM/sequence_in.sv", "target_type": "primary", "cursor_line": 14, "target_nlines": 1, "node_depth": 20, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "task_declaration", "task_body_declaration", "statement_or_null", "statement", "statement_item", "loop_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "simple_immediate_assert_statement", "expression", "primary"], "target": " assert(tx.randomize());\n"}
|
| 68 |
+
{"file": "easyUVM/sequencer.sv", "target_type": "simple_identifier", "cursor_line": 1, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_type", "parameter_value_assignment", "list_of_parameter_assignments", "ordered_parameter_assignment", "_ordered_parameter_assignment", "data_type", "simple_identifier"], "target": "class sequencer extends uvm_sequencer #(packet_in);\n"}
|
| 69 |
+
{"file": "easyUVM/simple_test.sv", "target_type": "simple_identifier", "cursor_line": 3, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_property", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "simple_identifier"], "target": " sequence_in seq;\n"}
|
| 70 |
+
{"file": "easyUVM/top.sv", "target_type": "module_declaration", "cursor_line": 34, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " \n logic [1:0] state;\n"}
|
| 71 |
+
{"file": "svreal/svreal/svreal.sv", "target_type": "module_declaration", "cursor_line": 1343, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " `MAKE_REAL(fract_as_float, in_width+1);\n"}
|
| 72 |
+
{"file": "svreal/tests/test_arith.sv", "target_type": "module_declaration", "cursor_line": 14, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " output real mul_o,\n"}
|
| 73 |
+
{"file": "svreal/tests/test_clog2.sv", "target_type": "module_declaration", "cursor_line": 7, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " output signed [31:0] out\n);\n assign out = clog2_math(in_);\nendmodule\n"}
|
| 74 |
+
{"file": "svreal/tests/test_comp.sv", "target_type": "module_declaration", "cursor_line": 30, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " `EQ_INTO_REAL(a_int, b_int, eq_o);\n `NE_INTO_REAL(a_int, b_int, ne_o);\nendmodule"}
|
| 75 |
+
{"file": "svreal/tests/test_compress_uint.sv", "target_type": "module_declaration", "cursor_line": 12, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": ");\n `COMPRESS_UINT(in_, (`WIDTH), val);\n assign out = `TO_REAL(val);\nendmodule\n"}
|
| 76 |
+
{"file": "svreal/tests/test_const.sv", "target_type": "module_declaration", "cursor_line": 15, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": ");\n // produce a_o output\n `MAKE_CONST_REAL(a_const, a_const_int);\n assign a_o = `TO_REAL(a_const_int);\n\n"}
|
| 77 |
+
{"file": "svreal/tests/test_conv.sv", "target_type": "module_declaration", "cursor_line": 15, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " assign `FORCE_REAL(r2i_i, r2i_int);\n\n"}
|
| 78 |
+
{"file": "svreal/tests/test_dff.sv", "target_type": "module_declaration", "cursor_line": 5, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "module test_dff #(\n parameter real init=0.0\n) (\n"}
|
| 79 |
+
{"file": "svreal/tests/test_float.sv", "target_type": "primary", "cursor_line": 32, "target_nlines": 1, "node_depth": 14, "node_path": ["source_file", "ERROR", "module_or_generate_item", "package_or_generate_item_declaration", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "conditional_statement", "cond_predicate", "expression", "expression", "primary"], "target": " if ((data[62:52] == 11'h7ff) && (data[51:0] != 0)) begin\n"}
|
| 80 |
+
{"file": "svreal/tests/test_hier.sv", "target_type": "primary", "cursor_line": 28, "target_nlines": 1, "node_depth": 4, "node_path": ["source_file", "text_macro_usage", "list_of_actual_arguments", "expression", "primary"], "target": " `PASS_REAL(b, b),\n"}
|
| 81 |
+
{"file": "svreal/tests/test_iface.sv", "target_type": "module_declaration", "cursor_line": 17, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n // create c_int interface\n svreal #(`REAL_INTF_PARAMS(value, 18, -10)) c_int ();\n"}
|
| 82 |
+
{"file": "svreal/tests/test_iface_core.sv", "target_type": "module_declaration", "cursor_line": 58, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "module level1 (svreal.in a, svreal.in b, svreal.out c);\n level2 inner(.a(a), .b(b), .c(c));\nendmodule\n"}
|
| 83 |
+
{"file": "svreal/tests/test_iface_synth.sv", "target_type": "module_declaration", "cursor_line": 13, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n assign a.value = a_value;\n assign b.value = b_value;\n assign c_value = c.value;\n"}
|
| 84 |
+
{"file": "svreal/tests/test_ite.sv", "target_type": "module_declaration", "cursor_line": 8, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input real b_i,\n // if-then-else\n input cond_i,\n"}
|
| 85 |
+
{"file": "svreal/tests/test_meas_width.sv", "target_type": "module_declaration", "cursor_line": 6, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input [7:0] in_,\n output [7:0] out\n);\n `MEAS_UINT_WIDTH_INTO(in_, 8, out, 8);\n"}
|
| 86 |
+
{"file": "svreal/tests/test_sync_ram.sv", "target_type": "module_declaration", "cursor_line": 9, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input clk,\n"}
|
| 87 |
+
{"file": "svreal/tests/test_sync_rom.sv", "target_type": "module_declaration", "cursor_line": 5, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "module test_sync_rom (\n input [1:0] addr,\n output real out,\n input clk,\n"}
|
| 88 |
+
{"file": "svreal/tests/test_synth.sv", "target_type": "module_declaration", "cursor_line": 12, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input wire logic signed [`A_WIDTH-1:0] a_ext,\n input wire logic signed [`B_WIDTH-1:0] b_ext,\n // unary op I/O\n output wire logic signed [`A_WIDTH-1:0] neg_ext,\n output wire logic signed [`A_WIDTH-1:0] abs_ext,\n"}
|
| 89 |
+
{"file": "ava-core/rtl/accelerator_pkg.sv", "target_type": "primary_literal", "cursor_line": 36, "target_nlines": 1, "node_depth": 11, "node_path": ["source_file", "package_declaration", "package_or_generate_item_declaration", "data_declaration", "type_declaration", "data_type", "enum_base_type", "packed_dimension", "constant_range", "constant_expression", "constant_primary", "primary_literal"], "target": "typedef enum logic [1:0] {\n"}
|
| 90 |
+
{"file": "ava-core/rtl/accelerator_top.sv", "target_type": "case_statement", "cursor_line": 174, "target_nlines": 5, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " vd_data = vlsu_wdata;\n VREG_WB_SRC_ARITH:\n vd_data = arith_output;\n VREG_WB_SRC_SCALAR:\n vd_data = replicated_scalar;\n"}
|
| 91 |
+
{"file": "ava-core/rtl/address_unit.sv", "target_type": "expression", "cursor_line": 135, "target_nlines": 1, "node_depth": 16, "node_path": ["ERROR", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "blocking_assignment", "operator_assignment", "expression", "expression", "expression", "expression", "primary", "concatenation", "expression"], "target": " cycle_bytes = {5'd0, be_gen[3]} + {5'd0, be_gen[2]} + {5'd0, be_gen[1]} + {5'd0, be_gen[0]};\n"}
|
| 92 |
+
{"file": "ava-core/rtl/arith_stage.sv", "target_type": "case_statement", "cursor_line": 152, "target_nlines": 4, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " PE_OPERAND_IMMEDIATE:\n begin\n if (unsigned_immediate)\n begin\n"}
|
| 93 |
+
{"file": "ava-core/rtl/bit_ext.sv", "target_type": "module_declaration", "cursor_line": 17, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " (input logic signed [W_IN-1:0] a_in, \n output logic signed [W_OUT-1:0] a_out);\n"}
|
| 94 |
+
{"file": "ava-core/rtl/mapping_unit.sv", "target_type": "module_declaration", "cursor_line": 39, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " vd_data[15:0]\n"}
|
| 95 |
+
{"file": "ava-core/rtl/pe_32b.sv", "target_type": "case_statement", "cursor_line": 225, "target_nlines": 5, "node_depth": 14, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " 2'd0: // 8b -> 16b\n sat_result = {'0, sat16_result};\n 2'd1: // 16b -> 32b\n sat_result = sat32_result;\n endcase\n"}
|
| 96 |
+
{"file": "ava-core/rtl/relu_bound.sv", "target_type": "module_declaration", "cursor_line": 23, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " ar = 0;\n else if (a > N)\n ar = N[6:0];\n else\n ar = a[6:0];\n"}
|
| 97 |
+
{"file": "ava-core/rtl/sat_unit.sv", "target_type": "module_declaration", "cursor_line": 23, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " logic signed [W_OUT-1:0] min_out = {1'b1,{(W_OUT-1){1'b0}}};\n\n assign a_out = a_in < min_in ? min_out : (a_in > max_in) ? max_out : a_in[W_OUT-1:0];\n\n //initial $display(\"%d, %d, %d, %d\", max_in, min_in, max_out, min_out);\n"}
|
| 98 |
+
{"file": "ava-core/rtl/scalar_replicate.sv", "target_type": "case_statement", "cursor_line": 65, "target_nlines": 5, "node_depth": 6, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "case_statement"], "target": " else\n replicated_out = {\n {16{scalar_in[15]}},\n scalar_in[15:0],\n {16{scalar_in[15]}},\n"}
|
| 99 |
+
{"file": "ava-core/rtl/tb/tb_bit_ext.sv", "target_type": "primary", "cursor_line": 32, "target_nlines": 1, "node_depth": 9, "node_path": ["ERROR", "module_or_generate_item", "loop_generate_construct", "generate_block", "module_or_generate_item", "udp_instantiation", "udp_instance", "input_terminal", "expression", "primary"], "target": " #1ns $display(\"%d, %d\", in, out);\n"}
|
| 100 |
+
{"file": "ava-core/rtl/tb/tb_relu_bound.sv", "target_type": "primary", "cursor_line": 34, "target_nlines": 1, "node_depth": 9, "node_path": ["ERROR", "module_or_generate_item", "loop_generate_construct", "generate_block", "module_or_generate_item", "udp_instantiation", "udp_instance", "input_terminal", "expression", "primary"], "target": " #10ns $display(\"%d, %d\", in, out);\n"}
|
| 101 |
+
{"file": "ava-core/rtl/tb/tb_sat_unit.sv", "target_type": "primary", "cursor_line": 23, "target_nlines": 1, "node_depth": 7, "node_path": ["ERROR", "module_or_generate_item", "module_instantiation", "hierarchical_instance", "list_of_port_connections", "ordered_port_connection", "expression", "primary"], "target": "sat_unit #(.W_IN(13), .W_OUT(8)) satu(in, out);\n"}
|
| 102 |
+
{"file": "ava-core/rtl/temporary_reg.sv", "target_type": "case_statement", "cursor_line": 84, "target_nlines": 5, "node_depth": 18, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " packed_set[1] = 1'b1;\n memory_read_packed[1] = memory_read_bytes[2];\n end\n 4'bzz11 : begin\n packed_set[2] = 1'b1;\n"}
|
| 103 |
+
{"file": "ava-core/rtl/vector_csrs.sv", "target_type": "module_declaration", "cursor_line": 83, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " vl_next = max_vl;\n else\n vl_next = avl_in[4:0];\n\nend\n"}
|
| 104 |
+
{"file": "ava-core/rtl/vector_decoder.sv", "target_type": "case_statement", "cursor_line": 141, "target_nlines": 1, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " else\n"}
|
| 105 |
+
{"file": "ava-core/rtl/vector_lsu.sv", "target_type": "case_statement", "cursor_line": 88, "target_nlines": 5, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " case(vs3_addr_o[0])\n 1'd0 : data_wdata_o = {vs_rdata_i[47:32], vs_rdata_i[15:0]};\n 1'd1 : data_wdata_o = {vs_rdata_i[111:96], vs_rdata_i[79:64]};\n endcase\n end\n"}
|
| 106 |
+
{"file": "ava-core/rtl/vector_registers.sv", "target_type": "case_statement", "cursor_line": 290, "target_nlines": 4, "node_depth": 27, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement", "case_item", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " end\n // 2'd1: // Not needed, just wr_en0 = '1\n 2'd2:\n begin\n"}
|
| 107 |
+
{"file": "ava-core/rtl/vw_sign_ext.sv", "target_type": "case_statement", "cursor_line": 36, "target_nlines": 3, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " 2'd0: // 8b\n begin\n sign_ext_a = {{24{a[7]}}, a[7:0]};\n"}
|
systemverilog/valid_content.jsonl
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|
vhdl/test.jsonl
ADDED
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vhdl/test_content_classfied.jsonl
ADDED
|
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+
version https://git-lfs.github.com/spec/v1
|
| 2 |
+
oid sha256:cf12c03927a7999bd5a7e35c75c7d3bfb3ece86af984053e189a2736e61a645e
|
| 3 |
+
size 17089233
|
vhdl/train.jsonl
ADDED
|
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vhdl/train_content.jsonl
ADDED
|
@@ -0,0 +1,3 @@
|
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|
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| 1 |
+
version https://git-lfs.github.com/spec/v1
|
| 2 |
+
oid sha256:d03ed5e26475bbde121075cbdd28349b77e8d4b615be1d472c0d723522a6fbe7
|
| 3 |
+
size 21719820
|
vhdl/valid.jsonl
ADDED
|
@@ -0,0 +1,104 @@
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|
| 1 |
+
{"file": "gbaHD/hdl/borderGen.vhd", "target_type": "entity_declaration", "cursor_line": 9, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " generic(\n xMin : integer;\n"}
|
| 2 |
+
{"file": "gbaHD/hdl/captureGBA.vhd", "target_type": "process_statement", "cursor_line": 112, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " process( clk ) is\n begin\n if rising_edge( clk ) then\n if ( colorMode = '1' ) then\n redPxlOut <= redGBACol;\n"}
|
| 3 |
+
{"file": "gbaHD/hdl/commTransceiver.vhd", "target_type": "process_statement", "cursor_line": 179, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " elsif ( curPacket( packetBits - 1 downto packetBits - prefixLen ) = osdState_prefix ) then\n osdActive <= curPacket( 0 );\n osdState( 6 downto 0 ) <= curPacket( 7 downto 1 );\n"}
|
| 4 |
+
{"file": "gbaHD/hdl/drp.vhd", "target_type": "process_statement", "cursor_line": 623, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " process( clk ) is\n begin\n if ( rising_edge( clk ) ) then\n if ( fsmSingleValCur = applyMask ) then\n maskedVal <= ( nextMask and doSig ) or ( nextVal and not( nextMask ) ) ;\n"}
|
| 5 |
+
{"file": "gbaHD/hdl/font5x7.vhd", "target_type": "architecture_body", "cursor_line": 91, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " ind := offset + x;\n \n charPxl <= font( char )( ind );\n end if;\n end if;\n"}
|
| 6 |
+
{"file": "gbaHD/hdl/fracDiv.vhd", "target_type": "process_statement", "cursor_line": 38, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " end if;\n \n cnt <= tmpCnt;\n end if;\n"}
|
| 7 |
+
{"file": "gbaHD/hdl/gbaShaderApprox.vhd", "target_type": "architecture_body", "cursor_line": 56, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " case gbaRed is \n when \"00000\" => baseRed <= \"00000000\";\n when \"00001\" => baseRed <= \"00000001\";\n when \"00010\" => baseRed <= \"00000101\";\n when \"00011\" => baseRed <= \"00001000\";\n"}
|
| 8 |
+
{"file": "gbaHD/hdl/gbaShader_new.vhd", "target_type": "entity_declaration", "cursor_line": 10, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity gbaColorCorrNew is\n port(\n gbaRed : in std_logic_vector( 4 downto 0 );\n gbaGreen : in std_logic_vector( 4 downto 0 );\n"}
|
| 9 |
+
{"file": "gbaHD/hdl/lineBuffer.vhd", "target_type": "process_statement", "cursor_line": 95, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " readSel( i ) <= '0';\n end if;\n end loop;\n end process;\n"}
|
| 10 |
+
{"file": "gbaHD/hdl/lineCache.vhd", "target_type": "entity_declaration", "cursor_line": 14, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " rst : in std_logic;\n"}
|
| 11 |
+
{"file": "gbaHD/hdl/osd.vhd", "target_type": "process_statement", "cursor_line": 171, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " mainMenu( SMOOTHFIELDY )( SMOOTHFIELDX + 2 ) <= 6;\n end if;\n \n if ( pixelGrid_int = '1' ) then\n if ( bgrid_int = '1' ) then\n"}
|
| 12 |
+
{"file": "gbaHD/hdl/padOverlay.vhd", "target_type": "architecture_body", "cursor_line": 71, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\nsignal butUp, butDown, butLeft, butRight, butA, butB, butL, butR,\n butStart, butSelect : std_logic;\n\n"}
|
| 13 |
+
{"file": "gbaHD/hdl/singeLineBuffer.vhd", "target_type": "entity_declaration", "cursor_line": 20, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " redDataIn : in std_logic_vector( 7 downto 0 );\n blueDataIn : in std_logic_vector( 7 downto 0 );\n greenDataIn : in std_logic_vector( 7 downto 0 );\n \n"}
|
| 14 |
+
{"file": "gbaHD/hdl/smooth.vhd", "target_type": "case_statement", "cursor_line": 316, "target_nlines": 2, "node_depth": 12, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "else", "sequence_of_statements", "case_statement", "case_statement_alternative", "sequence_of_statements", "case_statement"], "target": " rOut <= smoothOut( 0 )( 3 )( 0 );\n gOut <= smoothOut( 0 )( 3 )( 1 );\n"}
|
| 15 |
+
{"file": "HD-64/development/firmware/vicii/bad_line_detect.vhdl", "target_type": "architecture_body", "cursor_line": 64, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\n\tp_detect : process(clk) is\n\t\tvariable v_enable : std_wire;\n"}
|
| 16 |
+
{"file": "HD-64/development/firmware/vicii/border.vhdl", "target_type": "entity_declaration", "cursor_line": 46, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\typos : in t_ppos;\n\treg : in t_regs;\n\n\to_vbrd : out std_wire;\n"}
|
| 17 |
+
{"file": "HD-64/development/firmware/vicii/bus_latch.vhdl", "target_type": "entity_declaration", "cursor_line": 42, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "(\n\tclk : in std_wire; -- must be twice the video clock (16 times ph0)\n\trst : in std_wire;\n\n"}
|
| 18 |
+
{"file": "HD-64/development/firmware/vicii/bus_logger.vhdl", "target_type": "architecture_body", "cursor_line": 81, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\tsignal data_in : std_word(c_bit_width - 1 downto 0);\n\tsignal push_in : std_wire;\n"}
|
| 19 |
+
{"file": "HD-64/development/firmware/vicii/dot_clock.vhdl", "target_type": "process_statement", "cursor_line": 144, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\t\to_clk <= '0';\n\t\t\tend if;\n\t\tend if;\n"}
|
| 20 |
+
{"file": "HD-64/development/firmware/vicii/graphics_gen.vhdl", "target_type": "case_statement", "cursor_line": 340, "target_nlines": 3, "node_depth": 15, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "case_statement"], "target": "\t\t\t\t\t\twhen MODE_STD_TEXT =>\n\t\t\t\t\t\t\to_colr <= x\"0\"; -- BLACK\n\t\t\t\t\t\twhen MODE_MCL_TEXT =>\n"}
|
| 21 |
+
{"file": "HD-64/development/firmware/vicii/graphics_mux.vhdl", "target_type": "entity_declaration", "cursor_line": 62, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\ti_sprt_prio : in std_wire;\n\ti_sprt_colr : in t_colr;\n"}
|
| 22 |
+
{"file": "HD-64/development/firmware/vicii/registers.vhdl", "target_type": "architecture_body", "cursor_line": 191, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\t\tend if;\n\t\tend if;\n\tend process;\n\nend architecture;\n"}
|
| 23 |
+
{"file": "HD-64/development/firmware/vicii/sprites.vhdl", "target_type": "entity_declaration", "cursor_line": 54, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\n\ti_data : in std_word(7 downto 0);\n\to_prio : out std_wire;\n\to_actv : out std_wire;\n\to_colr : out t_colr\n"}
|
| 24 |
+
{"file": "HD-64/development/firmware/vicii/strobe.vhdl", "target_type": "entity_declaration", "cursor_line": 50, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "port\n(\n\tclk : in std_wire;\n"}
|
| 25 |
+
{"file": "HD-64/development/firmware/vicii/sync_flex.vhdl", "target_type": "process_statement", "cursor_line": 147, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\typos <= h65_ypos;\n\t\t\tspecs <= c_vic_h65_specs;\n\n"}
|
| 26 |
+
{"file": "HD-64/development/firmware/vicii/vic_passive.vhdl", "target_type": "entity_declaration", "cursor_line": 59, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t-- vic detection\n\tvic_type : out t_vic_type;\n"}
|
| 27 |
+
{"file": "HD-64/development/firmware/vicii/vic_pkg.vhdl", "target_type": "constant_declaration", "cursor_line": 44, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "constant_declaration"], "target": "\tconstant c_xpos_bits : positive := bits_for_range(c_max_xlen);\n"}
|
| 28 |
+
{"file": "HD-64/development/firmware/vicii/video_matrix.vhdl", "target_type": "process_statement", "cursor_line": 191, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\n\t\t\trst_1r <= rst;\n\t\t\tif rst_1r then\n"}
|
| 29 |
+
{"file": "HD-64/development/firmware/vicii/xy_sync.vhdl", "target_type": "case_statement", "cursor_line": 160, "target_nlines": 1, "node_depth": 15, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "case_statement"], "target": "\t\t\t\t\t\t\tend if;\n"}
|
| 30 |
+
{"file": "RPU/tests/rpu_core_tb.vhd", "target_type": "process_statement", "cursor_line": 544, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "begin\nif rising_edge(cEng_core) then\n count12MHz_stable <= count12MHz;\nend if;\nend process;\n"}
|
| 31 |
+
{"file": "RPU/tests/tb_alu_int32_div.vhd", "target_type": "entity_declaration", "cursor_line": 37, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity alu_int32_div_tb is\n-- Port ( );\nend alu_int32_div_tb;\n"}
|
| 32 |
+
{"file": "RPU/tests/tb_unit_alu_RV32I_01.vhd", "target_type": "process_statement", "cursor_line": 130, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " wait for I_clk_period*2;\n\n I_dataA <= X\"00000001\";\n\t\tI_dataB <= X\"00000006\";\n"}
|
| 33 |
+
{"file": "RPU/tests/tb_unit_decoder_RV32_01.vhd", "target_type": "process_statement", "cursor_line": 96, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " begin\n\t\tI_clk <= '0';\n\t\twait for I_clk_period/2;\n\t\tI_clk <= '1';\n\t\twait for I_clk_period/2;\n"}
|
| 34 |
+
{"file": "RPU/vhdl/alu_int32_div.vhd", "target_type": "architecture_body", "cursor_line": 56, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " constant STATE_IDLE : integer := 0;\n constant STATE_INFLIGHTU : integer := 1;\n constant STATE_COMPLETE : integer := 2;\n\n"}
|
| 35 |
+
{"file": "RPU/vhdl/constants.vhd", "target_type": "constant_declaration", "cursor_line": 226, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "constant_declaration"], "target": "constant EXCEPTION_STORE_AMO_PAGE_FAULT: std_logic_vector(XLEN32M1 downto 0):= X\"0000000f\";\n"}
|
| 36 |
+
{"file": "RPU/vhdl/control_unit.vhd", "target_type": "process_statement", "cursor_line": 114, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " interrupt_was_inactive <= '0';\n interrupt_state <= \"001\";\n next_s_state <= \"0000001\"; --F\n"}
|
| 37 |
+
{"file": "RPU/vhdl/core.vhd", "target_type": "entity_declaration", "cursor_line": 36, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " I_int_data : in STD_LOGIC_VECTOR(31 downto 0);\n I_int : in STD_LOGIC;\n O_int_ack : out STD_LOGIC;\n\n -- memory interface\n"}
|
| 38 |
+
{"file": "RPU/vhdl/csr_unit.vhd", "target_type": "process_statement", "cursor_line": 155, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " csr_instret <= std_logic_vector(unsigned(csr_instret) + 1);\n end if;\n"}
|
| 39 |
+
{"file": "RPU/vhdl/lint_unit.vhd", "target_type": "process_statement", "cursor_line": 101, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " actual_int <= '1';\n actual_int_data <= I_int_data1;\n int1_ack <= '1';\n elsif I_enMask(2) = '1' and I_int2 = '1' and int2_ack = '0' then\n actual_int <= '1';\n"}
|
| 40 |
+
{"file": "RPU/vhdl/mem_controller.vhd", "target_type": "architecture_body", "cursor_line": 109, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " end if;\n elsif state = 2 then\n cmd <= '0';\n state <= 0;\n"}
|
| 41 |
+
{"file": "RPU/vhdl/pc_unit.vhd", "target_type": "process_statement", "cursor_line": 45, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\tbegin\n\t\tif rising_edge(I_clk) then\n\t\t\tcase I_nPCop is\n"}
|
| 42 |
+
{"file": "RPU/vhdl/register_set.vhd", "target_type": "entity_declaration", "cursor_line": 36, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " O_dataA : out STD_LOGIC_VECTOR (XLENM1 downto 0);-- regRS1 data out\n O_dataB : out STD_LOGIC_VECTOR (XLENM1 downto 0) -- regRS2 data out\n"}
|
| 43 |
+
{"file": "RPU/vhdl/unit_alu_RV32_I.vhd", "target_type": "case_statement", "cursor_line": 142, "target_nlines": 1, "node_depth": 15, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "if_statement", "elsif", "sequence_of_statements", "case_statement", "case_statement_alternative", "sequence_of_statements", "case_statement"], "target": " when F3_OPIMM_SLTIU =>\n"}
|
| 44 |
+
{"file": "RPU/vhdl/unit_decoder_RV32I.vhd", "target_type": "entity_declaration", "cursor_line": 39, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " O_memOp : out STD_LOGIC_VECTOR(4 downto 0); -- Memory operation \n O_csrOP : out STD_LOGIC_VECTOR(4 downto 0); -- CSR operations\n O_csrAddr : out STD_LOGIC_VECTOR(11 downto 0); -- CSR address\n O_trapExit : out STD_LOGIC; -- request to exit trap handler\n"}
|
| 45 |
+
{"file": "T13x/klessydra-t1-3th/PKG_RiscV_Klessydra.vhd", "target_type": "constant_declaration", "cursor_line": 383, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "constant_declaration"], "target": " constant SYSTEM : std_logic_vector(6 downto 0) := \"1110011\";\r\n"}
|
| 46 |
+
{"file": "T13x/klessydra-t1-3th/RTL-Accumulator.vhd", "target_type": "process_statement", "cursor_line": 141, "target_nlines": 2, "node_depth": 9, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "for_generate_statement", "generate_statement_body", "if_generate_statement", "if_generate", "generate_statement_body", "process_statement"], "target": " dsp_out_accum_results(f) <= std_logic_vector(unsigned(accum_partial_results_stg_1(f)(15 downto 0)) + \n unsigned(accum_partial_results_stg_1(f)(31 downto 16)) +\n"}
|
| 47 |
+
{"file": "T13x/klessydra-t1-3th/RTL-CSR_Unit.vhd", "target_type": "case_statement", "cursor_line": 832, "target_nlines": 5, "node_depth": 23, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "for_generate_statement", "generate_statement_body", "process_statement", "sequence_of_statements", "if_statement", "elsif", "sequence_of_statements", "if_statement", "elsif", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "case_statement", "case_statement_alternative", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "case_statement"], "target": " if(rs1(instr_word_IE) /= 0) then\r\n MHPMCOUNTER9(h) <= (MHPMCOUNTER9(h) or csr_wdata_i);\r\n end if;\r\n when CSRRC|CSRRCI =>\r\n csr_rdata_o_replicated(h) <= MHPMCOUNTER9(h);\r\n"}
|
| 48 |
+
{"file": "T13x/klessydra-t1-3th/RTL-DSP_Unit.vhd", "target_type": "process_statement", "cursor_line": 1802, "target_nlines": 5, "node_depth": 6, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "for_generate_statement", "generate_statement_body", "process_statement"], "target": " h := g; -- set the spm rd/wr ports equal to the \"for-loop\"\n elsif multithreaded_accl_en = 0 then\n h := f; -- set the spm rd/wr ports equal to the \"for-generate\" \n end if;\n -- Addition in SIMD Virtual Parallelism is executed here, if the carries are blocked, we will have a chain of 8-bit or 16-bit adders, else we have 32-bit adders\n"}
|
| 49 |
+
{"file": "T13x/klessydra-t1-3th/RTL-Debug_Unit.vhd", "target_type": "process_statement", "cursor_line": 165, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " end if;\r\n when others =>\r\n null;\r\n"}
|
| 50 |
+
{"file": "T13x/klessydra-t1-3th/RTL-ID_STAGE.vhd", "target_type": "case_statement", "cursor_line": 253, "target_nlines": 3, "node_depth": 18, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "elsif", "sequence_of_statements", "if_statement", "else", "sequence_of_statements", "case_statement", "case_statement_alternative", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "case_statement"], "target": " case FUNCT3_wires is\n when ADD => --ADD instruction\n decoded_instruction_IE <= ADD7_pattern;\n"}
|
| 51 |
+
{"file": "T13x/klessydra-t1-3th/RTL-IE_STAGE.vhd", "target_type": "process_statement", "cursor_line": 1043, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " pass_BLTU <= '1';\n else\n pass_BGEU <= '1';\n end if;\n end if;\n"}
|
| 52 |
+
{"file": "T13x/klessydra-t1-3th/RTL-IF_STAGE.vhd", "target_type": "process_statement", "cursor_line": 68, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " begin\n if busy_ID = '0' then\n instr_req_o <= '1';\n else\n instr_req_o <= '0';\n"}
|
| 53 |
+
{"file": "T13x/klessydra-t1-3th/RTL-Load_Store_Unit.vhd", "target_type": "case_statement", "cursor_line": 265, "target_nlines": 2, "node_depth": 12, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "elsif", "sequence_of_statements", "if_statement", "elsif", "sequence_of_statements", "case_statement"], "target": " misaligned_err <= '1';\n elsif load_err = '1' then -- AAA move to data_valid_waiting stage\n"}
|
| 54 |
+
{"file": "T13x/klessydra-t1-3th/RTL-Processing_Pipeline.vhd", "target_type": "case_statement", "cursor_line": 1690, "target_nlines": 4, "node_depth": 15, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "if_generate_statement", "if_generate", "generate_statement_body", "process_statement", "sequence_of_statements", "if_statement", "elsif", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "case_statement"], "target": " if decoded_instruction_LS(KMEMLD_bit_position) = '1' then\r\n write(row0, string'(\" kmemld x\"));\r\n end if;\r\n\r\n"}
|
| 55 |
+
{"file": "T13x/klessydra-t1-3th/RTL-Program_Counter_unit.vhd", "target_type": "entity_declaration", "cursor_line": 64, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " mepc_incremented_pc : out array_2D(THREAD_POOL_SIZE - 1 downto 0)(31 downto 0);\r\n mepc_interrupt_pc : out array_2D(THREAD_POOL_SIZE - 1 downto 0)(31 downto 0);\r\n irq_pending : out std_logic_vector(THREAD_POOL_SIZE - 1 downto 0);\r\n clk_i : in std_logic;\r\n"}
|
| 56 |
+
{"file": "T13x/klessydra-t1-3th/RTL-Registerfile.vhd", "target_type": "entity_declaration", "cursor_line": 57, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\tMUL_WB : in std_logic_vector(31 downto 0);\n\tLS_WB : in std_logic_vector(31 downto 0);\n\tinstr_word_LS_WB : in std_logic_vector(31 downto 0);\n\tinstr_word_IE_WB : in std_logic_vector(31 downto 0);\n\tharc_LS_WB : in integer range THREAD_POOL_SIZE-1 downto 0;\n"}
|
| 57 |
+
{"file": "T13x/klessydra-t1-3th/RTL-Scratchpad_Memory.vhd", "target_type": "entity_declaration", "cursor_line": 29, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " Addr_Width : natural;\n SIMD : natural;\n --------------------------------\n ACCL_NUM : natural;\n"}
|
| 58 |
+
{"file": "T13x/klessydra-t1-3th/RTL-Scratchpad_Memory_Interface.vhd", "target_type": "process_statement", "cursor_line": 206, "target_nlines": 4, "node_depth": 6, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "for_generate_statement", "generate_statement_body", "process_statement"], "target": " sc_addr_wr(h)(l) <= (others => '0');\n sc_data_wr(h)(l) <= (others => '0');\n end loop;\n rd_offset(h) <= (others => (others => '0'));\n"}
|
| 59 |
+
{"file": "T13x/klessydra-t1-3th/STR-Klessydra_top.vhd", "target_type": "process_statement", "cursor_line": 548, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " begin\r\n if rst_ni = '0' then\r\n elsif rising_edge(clk_i) then\r\n pc_except_value <= pc_except_value_wire; -- AAA verify if it is working for DSP and LSU (not verified yet)\r\n"}
|
| 60 |
+
{"file": "deniser/hdl/denise.vhdl", "target_type": "case_statement", "cursor_line": 395, "target_nlines": 2, "node_depth": 6, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "case_statement"], "target": " when \"000\" => v.d.bplen := \"000000\";\n when \"001\" => v.d.bplen := \"000001\";\n"}
|
| 61 |
+
{"file": "deniser/hdl/joyquad.vhdl", "target_type": "architecture_body", "cursor_line": 36, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "architecture rtl of joyquad is\n type reg_t is record\n d : unsigned(7 downto 0);\n v : std_ulogic;\n vq : std_ulogic;\n"}
|
| 62 |
+
{"file": "deniser/hdl/ocs.vhdl", "target_type": "constant_declaration", "cursor_line": 33, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "constant_declaration"], "target": " constant RGA_DIWSTRT : addr_t := x\"08E\";\n"}
|
| 63 |
+
{"file": "deniser/hdl/portable/inferred/oddr.vhdl", "target_type": "entity_declaration", "cursor_line": 21, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity oddr is\n port (\n"}
|
| 64 |
+
{"file": "deniser/hdl/portable/machxo3d/oddr.vhdl", "target_type": "entity_declaration", "cursor_line": 27, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " d1 : in std_ulogic;\n q : out std_ulogic\n );\nend;\n"}
|
| 65 |
+
{"file": "deniser/hdl/priv.vhdl", "target_type": "case_statement", "cursor_line": 163, "target_nlines": 1, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "sequence_of_statements", "case_statement"], "target": " when x\"156\" => s.spr(2).datb:= '1';\n"}
|
| 66 |
+
{"file": "deniser/hdl/sim/rga_bfm.vhdl", "target_type": "if_statement", "cursor_line": 80, "target_nlines": 1, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "procedure_body", "sequence_of_statements", "if_statement"], "target": " if cmd.log < LOG_DEBUG then return; end if;\n"}
|
| 67 |
+
{"file": "deniser/hdl/sim/rga_bfm_impl.vhdl", "target_type": "case_statement", "cursor_line": 72, "target_nlines": 3, "node_depth": 8, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "loop_statement", "sequence_of_statements", "case_statement"], "target": " deni.drd <= (others => 'Z') after 20 ns;\n else\n rgacmd.rdata <= deno.drd;\n"}
|
| 68 |
+
{"file": "deniser/hdl/sim/tb.vhdl", "target_type": "entity_declaration", "cursor_line": 25, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity tb is\nend;\n"}
|
| 69 |
+
{"file": "deniser/hdl/sim/tbtest.vhdl", "target_type": "entity_declaration", "cursor_line": 32, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity test is\nend;\n"}
|
| 70 |
+
{"file": "deniser/hdl/sim/text.vhdl", "target_type": "variable_declaration", "cursor_line": 27, "target_nlines": 1, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "procedure_body", "declarative_part", "variable_declaration"], "target": " variable l : line;\n"}
|
| 71 |
+
{"file": "deniser/hdl/syncer.vhdl", "target_type": "entity_declaration", "cursor_line": 28, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " q : out std_ulogic\n"}
|
| 72 |
+
{"file": "deniser/hdl/test/joy0.vhdl", "target_type": "process_statement", "cursor_line": 9, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " rga_write(rgacmd, RGA_DIWSTRT, x\"2c81\");\n"}
|
| 73 |
+
{"file": "deniser/hdl/test/wb0.vhdl", "target_type": "architecture_body", "cursor_line": 13, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\n rga_write(rgacmd, RGA_COLOR00, x\"0000\");\n rga_write(rgacmd, RGA_COLOR01, x\"0111\");\n rga_write(rgacmd, RGA_COLOR02, x\"0222\");\n"}
|
| 74 |
+
{"file": "deniser/hdl/top.vhdl", "target_type": "entity_declaration", "cursor_line": 35, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " m0v : in std_ulogic;\n m0h : in std_ulogic;\n"}
|
| 75 |
+
{"file": "fphdl/env_c.vhdl", "target_type": "package_body", "cursor_line": 14, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "package_body"], "target": " begin\n report \"Procedure STOP called with status: \" & INTEGER'image(STATUS)\n severity failure;\n"}
|
| 76 |
+
{"file": "fphdl/fixed_float_types_c.vhdl", "target_type": "package_declaration", "cursor_line": 29, "target_nlines": 1, "node_depth": 1, "node_path": ["design_file", "package_declaration"], "target": " type round_type is (round_nearest, -- Default, nearest LSB '0'\n"}
|
| 77 |
+
{"file": "fphdl/fixed_noresize.vhdl", "target_type": "variable_declaration", "cursor_line": 4064, "target_nlines": 1, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "procedure_body", "declarative_part", "variable_declaration"], "target": " variable result : ufixed (VALUE'range);\n"}
|
| 78 |
+
{"file": "fphdl/fixed_pkg_c.vhdl", "target_type": "case_statement", "cursor_line": 6935, "target_nlines": 3, "node_depth": 6, "node_path": ["design_file", "design_unit", "package_body", "declarative_part", "procedure_body", "sequence_of_statements", "case_statement"], "target": " when '9' => result := x\"9\"; good := true;\n when 'A' | 'a' => result := x\"A\"; good := true;\n when 'B' | 'b' => result := x\"B\"; good := true;\n"}
|
| 79 |
+
{"file": "fphdl/fixed_synth.vhdl", "target_type": "process_statement", "cursor_line": 110, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " variable outarray : cry_type; -- array for output\n variable in1array, in2array : cry_type; -- array for input\n"}
|
| 80 |
+
{"file": "fphdl/float_noround_pkg.vhdl", "target_type": "case_statement", "cursor_line": 2946, "target_nlines": 3, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "sequence_of_statements", "case_statement"], "target": " fpresult := neg_zerofp (fraction_width => fraction_width-guard,\n exponent_width => exponent_width);\n when others =>\n"}
|
| 81 |
+
{"file": "fphdl/float_pkg_c.vhdl", "target_type": "case_statement", "cursor_line": 1513, "target_nlines": 5, "node_depth": 8, "node_path": ["design_file", "package_body", "declarative_part", "procedure_body", "sequence_of_statements", "if_statement", "else", "sequence_of_statements", "case_statement"], "target": " when round_inf =>\n round := remainder(2) and not isign;\n when round_neginf =>\n round := remainder(2) and isign;\n when others =>\n"}
|
| 82 |
+
{"file": "fphdl/float_synth.vhdl", "target_type": "process_statement", "cursor_line": 545, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " outarray(0) := not (in1reg3);\n when \"001\" =>\n outarray(0) := in1reg3 and in2reg3;\n when \"010\" =>\n"}
|
| 83 |
+
{"file": "fphdl/numeric_std_additions.vhdl", "target_type": "case_statement", "cursor_line": 2147, "target_nlines": 2, "node_depth": 10, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "sequence_of_statements", "if_statement", "else", "sequence_of_statements", "loop_statement", "sequence_of_statements", "case_statement"], "target": " when x\"5\" => result(i+1) := '5';\n when x\"6\" => result(i+1) := '6';\n"}
|
| 84 |
+
{"file": "fphdl/numeric_std_unsigned_c.vhdl", "target_type": "function_body", "cursor_line": 1482, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_body", "declarative_part", "function_body"], "target": " function \\?<\\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is\r\n begin\r\n return \\?<\\ (UNSIGNED(L), UNSIGNED(R));\r\n end function \\?<\\;\r\n"}
|
| 85 |
+
{"file": "fphdl/standard_additions_c.vhdl", "target_type": "case_statement", "cursor_line": 1996, "target_nlines": 5, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "sequence_of_statements", "case_statement"], "target": " and (tvar < roundvar and tvar > -roundvar) then\n-- and ((bvalue-roundvar) = real(frcptr)) then\n write (L, frcptr); -- Just a short integer, write it.\n elsif (exp >= dwidth) or (exp < -4) then\n -- in \"e\" format (modified)\n"}
|
| 86 |
+
{"file": "fphdl/standard_textio_additions_c.vhdl", "target_type": "case_statement", "cursor_line": 122, "target_nlines": 5, "node_depth": 6, "node_path": ["design_file", "design_unit", "package_body", "declarative_part", "procedure_body", "sequence_of_statements", "case_statement"], "target": " when '6' => result := x\"6\"; good := true;\n when '7' => result := x\"7\"; good := true;\n when '8' => result := x\"8\"; good := true;\n when '9' => result := x\"9\"; good := true;\n when 'A' | 'a' => result := x\"A\"; good := true;\n"}
|
| 87 |
+
{"file": "fphdl/std_logic_1164_additions.vhdl", "target_type": "case_statement", "cursor_line": 1456, "target_nlines": 4, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "procedure_body", "sequence_of_statements", "case_statement"], "target": " when '0' => result := o\"0\"; good := true;\n when '1' => result := o\"1\"; good := true;\n when '2' => result := o\"2\"; good := true;\n when '3' => result := o\"3\"; good := true;\n"}
|
| 88 |
+
{"file": "fphdl/test_fixed_synth.vhdl", "target_type": "entity_declaration", "cursor_line": 9, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity test_fixed_synth is\n generic (\n quiet : boolean := false); -- make the simulation quiet\nend entity test_fixed_synth;\n"}
|
| 89 |
+
{"file": "fphdl/test_float_synth.vhdl", "target_type": "process_statement", "cursor_line": 132, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " if (not stop_clock) then\n"}
|
| 90 |
+
{"file": "haddoc2/lib/hdl/ConvLayer.vhd", "target_type": "architecture_body", "cursor_line": 123, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " generic map (\n BITWIDTH => BITWIDTH,\n IMAGE_WIDTH => IMAGE_WIDTH,\n KERNEL_SIZE => KERNEL_SIZE,\n NB_IN_FLOWS => NB_IN_FLOWS\n"}
|
| 91 |
+
{"file": "haddoc2/lib/hdl/DisplayLayer.vhd", "target_type": "architecture_body", "cursor_line": 40, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "begin\n out_data <= in_data(to_integer(unsigned(sel)));\n out_dv <= in_dv;\n out_fv <= in_fv;\n"}
|
| 92 |
+
{"file": "haddoc2/lib/hdl/DotProduct.vhd", "target_type": "architecture_body", "cursor_line": 101, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " out_valid => s_out_valid\n );\n out_dv <= s_out_valid;\n out_fv <= s_out_valid;\n\n"}
|
| 93 |
+
{"file": "haddoc2/lib/hdl/InputLayer.vhd", "target_type": "process_statement", "cursor_line": 45, "target_nlines": 1, "node_depth": 7, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "if_generate_statement", "if_generate", "generate_statement_body", "process_statement"], "target": " out_fv <= in_fv;\n"}
|
| 94 |
+
{"file": "haddoc2/lib/hdl/MCM.vhd", "target_type": "process_statement", "cursor_line": 51, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " if (in_valid = '1') then\n mcm_loop : for i in 0 to DOT_PRODUCT_SIZE - 1 loop\n out_data(i) <= KERNEL_VALUE(i) * in_data(i);\n"}
|
| 95 |
+
{"file": "haddoc2/lib/hdl/MOA.vhd", "target_type": "architecture_body", "cursor_line": 80, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\n elsif(rising_edge(clk)) then\n if (enable = '1') then\n"}
|
| 96 |
+
{"file": "haddoc2/lib/hdl/NeighExtractor.vhd", "target_type": "entity_declaration", "cursor_line": 70, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " enable : in std_logic;\n in_data : in std_logic_vector((BITWIDTH-1) downto 0);\n in_dv : in std_logic;\n"}
|
| 97 |
+
{"file": "haddoc2/lib/hdl/PoolLayer.vhd", "target_type": "architecture_body", "cursor_line": 92, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " in_data => in_data(i),\n"}
|
| 98 |
+
{"file": "haddoc2/lib/hdl/TanhLayer.vhd", "target_type": "entity_declaration", "cursor_line": 11, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " SUM_WIDTH : integer\n );\n port(\n in_data : in std_logic_vector (SUM_WIDTH-1 downto 0);\n"}
|
| 99 |
+
{"file": "haddoc2/lib/hdl/Taps.vhd", "target_type": "entity_declaration", "cursor_line": 39, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\n port (\n clk : in std_logic;\n"}
|
| 100 |
+
{"file": "haddoc2/lib/hdl/TensorExtractor.vhd", "target_type": "architecture_body", "cursor_line": 70, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " port map (\n"}
|
| 101 |
+
{"file": "haddoc2/lib/hdl/cnn_types.vhd", "target_type": "constant_declaration", "cursor_line": 35, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "constant_declaration"], "target": " constant V2 : integer := SCALE_FACTOR - 10;\n"}
|
| 102 |
+
{"file": "haddoc2/lib/hdl/maxPool.vhd", "target_type": "entity_declaration", "cursor_line": 23, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity maxPool is\n generic(\n BITWIDTH : integer;\n IMAGE_WIDTH : integer;\n"}
|
| 103 |
+
{"file": "haddoc2/lib/hdl/poolH.vhd", "target_type": "entity_declaration", "cursor_line": 16, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " enable : in std_logic;\n"}
|
| 104 |
+
{"file": "haddoc2/lib/hdl/poolV.vhd", "target_type": "process_statement", "cursor_line": 96, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " end if;\n"}
|
vhdl/valid_content.jsonl
ADDED
|
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|
|