| {"file": "vboard/vga/board/tinyfpgabx/TinyFPGABX_PLL_config_pkg.vhd", "target_type": "constant_declaration", "cursor_line": 35, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "constant_declaration"], "target": " 22 => ( 0, 0 ), -- 102.100\n 23 => ( 0, 0 ), -- 106.470\n 24 => ( 0, 0 ), -- 108.000\n"} |
| {"file": "vproc/bfm/test/testapb.vhd", "target_type": "entity_declaration", "cursor_line": 37, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " CLKPERIOD : time := 10 ns;\n STOPCOUNT : integer := 200\n);\nend entity;\n"} |
| {"file": "Answers-for-My-LZU-UG-Courses/Principles of Computer Organization/2021春季学期/Cache设计/Cache_SA4/Cache_SA4.gen/sources_1/ip/blk_mem_gen_0/misc/blk_mem_gen_v8_4.vhd", "target_type": "architecture_body", "cursor_line": 147, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "architecture xilinx of blk_mem_gen_v8_4_4 is\n begin\n end \narchitecture xilinx;\n"} |
| {"file": "Simon_Speck_Ciphers/VHDL/SIMON_CIPHER_TB.vhd", "target_type": "entity_declaration", "cursor_line": 40, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "ENTITY SIMON_CIPHER_TB IS\nEND SIMON_CIPHER_TB;\n"} |
| {"file": "SpaceInvadersFpgaGame/space_invaders/space_invaders.cache/ip/70c61db667320b22/blk_mem_gen_5_stub.vhdl", "target_type": "architecture_body", "cursor_line": 27, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is\nattribute syn_black_box : boolean;\n"} |
| {"file": "greta/hdl/aspic/aspic_regs.vhdl", "target_type": "variable_declaration", "cursor_line": 114, "target_nlines": 1, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "declarative_part", "variable_declaration"], "target": " variable rec : rxdata_reg;\n"} |
| {"file": "Clavier/FPGA/LedController.vhd", "target_type": "case_statement", "cursor_line": 92, "target_nlines": 5, "node_depth": 14, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "loop_statement", "sequence_of_statements", "case_statement"], "target": " when done =>\n -- Normal mode, fixed brightness\n if LED_STATES(i) = '1' then\n led_values(i) <= BRIGHTNESS;\n end if;\n"} |
| {"file": "jpeg_open/model/xilinx/ku/pll/pll_main_250/pll_main_sim_netlist.vhdl", "target_type": "entity_declaration", "cursor_line": 23, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " );\n attribute ORIG_REF_NAME : string;\n attribute ORIG_REF_NAME of pll_main_pll_main_clk_wiz : entity is \"pll_main_clk_wiz\";\n"} |
| {"file": "leros/vhdl/core/leros_decode.vhd", "target_type": "process_statement", "cursor_line": 52, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "begin\n\t-- some defaults\n\tdec.op <= op_ld;\n"} |
| {"file": "MIPI_CSI2_TX/hdl/i2c/i2c_mux.vhd", "target_type": "case_statement", "cursor_line": 388, "target_nlines": 3, "node_depth": 6, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "case_statement"], "target": " elsif (unsigned(DATA_OUT_OV(7 downto 0)) = x\"00\" ) then\r\n start_activated_by_i2c_next <= '0';\r\n end if;\r\n"} |
| {"file": "bladeRF-adsb/vhdl/adsb_crc.vhd", "target_type": "entity_declaration", "cursor_line": 16, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " crc_good : out std_logic ;\n crc_valid : out std_logic\n"} |
| {"file": "RedPitaya-FPGA/prj/Examples/Vga_image/rtl/vga_vhdl.vhd", "target_type": "architecture_body", "cursor_line": 52, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\n--signals to synhronize the screen\nhsync <= '1' when hst_sig >= Hf and hst_sig < Hf + Hs else '0';\n"} |
| {"file": "catapult-v3-smartnic-re/Projects/Network/SuperliteII_V4_QSFP/core/superliteii_txrx_module.vhd", "target_type": "process_statement", "cursor_line": 390, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "process(DataClock,Reset_Tx)\n"} |
| {"file": "jTDC/modules/register/rw_register.vhdl", "target_type": "entity_declaration", "cursor_line": 41, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\t\t readsignal : in std_logic;\n CLK : in STD_LOGIC;\n registerbits : out STD_LOGIC_VECTOR (31 downto 0) := (others => '0')\n\t);\nend rw_register;\n"} |
| {"file": "openfpga-pcengine/rtl/pce/HUC6280/HUC6280_ALU.vhd", "target_type": "process_statement", "cursor_line": 53, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\t\tCR <= L(7);\n\t\t\t\tIntL <= L(6 downto 0) & CI;\n"} |
| {"file": "space-invaders-vhdl/lib/io/ps2_iobase.vhd", "target_type": "architecture_body", "cursor_line": 104, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\tend if;\r\n\tend process;\r\n\r\n\todata_rdy <= en and parchecked;\r\n\r\n"} |
| {"file": "TPU/vhdl/core/reg16_8.vhd", "target_type": "process_statement", "cursor_line": 33, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\tO_dataA <= regs(to_integer(unsigned(I_selA)));\n\t\t\tO_dataB <= regs(to_integer(unsigned(I_selB)));\n\t\t\tif (I_we = '1') then\n\t\t\t\tregs(to_integer(unsigned(I_selD))) <= I_dataD;\n"} |
| {"file": "openfpga-pcengine-cd/src/fpga/core/rtl/CEGen.vhd", "target_type": "entity_declaration", "cursor_line": 8, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\tRST_N : in STD_LOGIC;\r\n"} |
| {"file": "SneakySnake/Snake-on-Chip/Hardware_Accelerator/Snake-on-Chip.srcs/sources_1/ip/shd_pe_fifo/sim/shd_pe_fifo.vhd", "target_type": "entity_declaration", "cursor_line": 68, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " full : OUT STD_LOGIC;\n empty : OUT STD_LOGIC\n );\nEND shd_pe_fifo;\n"} |
| {"file": "1bitSDR/impl1/reveal_workspace/rev15i/top_la0_comp.vhd", "target_type": "package_declaration", "cursor_line": 17, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "package_declaration"], "target": " jtck:\t\tIN std_logic;\n"} |
| {"file": "I99T/i99t/b04/b04.vhd", "target_type": "process_statement", "cursor_line": 74, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\t \t\tDATA_OUT <= REG4;\n\t\t\t\t else\t\t\t\t \n\t\t\t\t\t\t REGD := (DATA_IN+REG4) mod 128;\n\t\t\t\t\t\t temp := DATA_IN+REG4;\n"} |
| {"file": "ODriveFPGA/altera_nios_custom_instr_floating_point_2_NOSQRT/altera_nios_custom_instr_floating_point_2_multi/fpoint2_multi.vhd", "target_type": "case_statement", "cursor_line": 95, "target_nlines": 2, "node_depth": 6, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "case_statement"], "target": " when \"010\" => load_data <= FLOATIS_LAT; \n when \"011\" => load_data <= FSQRTS_LAT; \n"} |
| {"file": "TurboGrafx16_MiSTer/rtl/HUC6280/HUC6280.vhd", "target_type": "case_statement", "cursor_line": 226, "target_nlines": 2, "node_depth": 15, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "elsif", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "case_statement"], "target": "\t\t\t\t\t\twhen \"10\" =>\r\n\t\t\t\t\t\t\tINT_MASK_PRE <= CPU_DO(2 downto 0);\r\n"} |
| {"file": "UETRV-PCore/FPGA_Target/Nexys-A7/PCore_FPGA.cache/ip/2019.1/7efb766302388b7c/nexys_shell_proc_sys_reset_0_0_sim_netlist.vhdl", "target_type": "entity_declaration", "cursor_line": 123, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " port (\n"} |
| {"file": "hardh264/tests/cavlc_test.vhd", "target_type": "process_statement", "cursor_line": 164, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\twait until rising_edge(clk2); vin <= CONV_STD_LOGIC_VECTOR(data(index)(8),12);\r\n\t\twait until rising_edge(clk2); vin <= CONV_STD_LOGIC_VECTOR(data(index)(4),12);\r\n"} |
| {"file": "Digital-Design-Lab/Chapter_12/Digital_camera/digital_camera.srcs/sources_1/ip/ram_read_0/ram_read_0_funcsim.vhdl", "target_type": "entity_declaration", "cursor_line": 24, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " vga_v_cnt : in STD_LOGIC_VECTOR ( 7 downto 0 )\n );\n attribute ORIG_REF_NAME : string;\n attribute ORIG_REF_NAME of ram_read_0_ram_read : entity is \"ram_read\";\n"} |
| {"file": "PYNQ-DL/resize/ip/hdl/vhdl/axis2xfMat.vhd", "target_type": "process_statement", "cursor_line": 418, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " src_TDATA_blk_n_assign_proc : process(src_data_V_0_state, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, exitcond_reg_151)\n begin\n if (((exitcond_reg_151 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then \n src_TDATA_blk_n <= src_data_V_0_state(0);\n"} |
| {"file": "freezing-spice/src/id.vhd", "target_type": "case_statement", "cursor_line": 208, "target_nlines": 4, "node_depth": 9, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "case_statement", "case_statement_alternative", "sequence_of_statements", "case_statement"], "target": " decoded.alu_func <= ALU_SRL;\n end if;\n when \"110\" => decoded.alu_func <= ALU_OR;\n when \"111\" => decoded.alu_func <= ALU_AND;\n"} |
| {"file": "syfala/source/rtl/i2s/i2s_standard.vhd", "target_type": "entity_declaration", "cursor_line": 78, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " sd_#L_#R_rx : in std_logic; -- serial data receive\n sd_#L_#R_tx : out std_logic; -- serial data transmit\n from_faust_#L : in std_logic_vector(d_width-1 downto 0); -- left channel data to transmit bit by bit\n from_faust_#R : in std_logic_vector(d_width-1 downto 0); -- right channel data to transmit bit by bit\n"} |
| {"file": "Time-Card/FPGA/Open-Source/Package/TimeCard_Package.vhd", "target_type": "variable_declaration", "cursor_line": 191, "target_nlines": 1, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "procedure_body", "declarative_part", "variable_declaration"], "target": " variable TempReg : std_logic_vector((Axi_DataSize_Con-1) downto 0);\n"} |
| {"file": "Motion-Detection-System-Based-On-Background-Reconstruction/IP/image_process_1.0/src/fifo/fifo_sim_netlist.vhdl", "target_type": "architecture_body", "cursor_line": 1223, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " srst => srst\n );\n"} |
| {"file": "cryptocores/des/rtl/vhdl/des.vhd", "target_type": "process_statement", "cursor_line": 551, "target_nlines": 2, "node_depth": 7, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "if_generate_statement", "if_generate", "generate_statement_body", "process_statement"], "target": " when 13 =>\n if (v_mode = '0') then\n"} |
| {"file": "BIT-CS-UnderGraduate/大四上/计算机组成原理课程设计/cpu/cpu.cache/ip/2019.2/0a58b89f66623201/inst_sram_sim_netlist.vhdl", "target_type": "architecture_body", "cursor_line": 3609, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " dpo(21) <= \\<const0>\\;\n dpo(20) <= \\<const0>\\;\n dpo(19) <= \\<const0>\\;\n dpo(18) <= \\<const0>\\;\n dpo(17) <= \\<const0>\\;\n"} |
| {"file": "fpga-vt/components/T80_RegX.vhd", "target_type": "architecture_body", "cursor_line": 81, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\t\tSPO\t\t: out std_ulogic;\n\t\t\tA0\t\t: in std_ulogic;\n"} |
| {"file": "fpu/vhdl/src/lzc/lzc_8.vhd", "target_type": "entity_declaration", "cursor_line": 9, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\tport(\n\t\tA : in std_logic_vector(7 downto 0);\n\t\tZ : out std_logic_vector(2 downto 0);\n\t\tV : out std_logic\n\t);\n"} |
| {"file": "Apple-II_MiSTer/rtl/t65/T65.vhd", "target_type": "case_statement", "cursor_line": 489, "target_nlines": 1, "node_depth": 18, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "elsif", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "case_statement"], "target": " when \"011\" =>--0x78(sei)\r\n"} |
| {"file": "VHDL/ieee-754-multiplier/tb_add_16.vhd", "target_type": "architecture_body", "cursor_line": 52, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " wait for 100 ns;\n X_A_VAL <= X\"0055\"; X_B_VAL <= X\"00AA\"; X_CIN_H <= '1';\n wait for 100 ns;\n X_A_VAL <= X\"0355\"; X_B_VAL <= X\"01AA\"; X_CIN_H <= '1';\n"} |
| {"file": "AES-VHDL/AES-DEC/RTL/key_schedule.vhd", "target_type": "entity_declaration", "cursor_line": 25, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\tround_const : in std_logic_vector(7 downto 0);\r\n"} |
| {"file": "FPGA-Notes-for-Scientists/ip/Redpitaya-125-14-clk/src/clk_bd.vhd", "target_type": "entity_declaration", "cursor_line": 23, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " );\n attribute CORE_GENERATION_INFO : string;\n"} |
| {"file": "Rudi-RV32I/src/cpu/program_counter.vhd", "target_type": "process_statement", "cursor_line": 101, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " when PC_JMP_REG_RELATIVE => add_LHS := unsigned(a);\n when others => add_LHS := unsigned(RESET_VECTOR);\n end case;\n\n"} |
| {"file": "fpga-multi-effect/ip_repo/VL_user_clk_slow_1.0/sources_1/new/clk_slow.vhd", "target_type": "process_statement", "cursor_line": 36, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "begin\n if rising_edge(clk_in) then\n clk_cntr <= std_logic_vector(unsigned(clk_cntr)+1); \n end if;\nend process;\n"} |
| {"file": "zynq_timestamping/ip/ADI_timestamping/RTL_code/adc_dmac_xlength_sniffer.vhd", "target_type": "architecture_body", "cursor_line": 164, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " src_clk => s_axi_aclk,\n src_data => dma_x_length_int_32b,\n src_data_valid => dma_x_length_int_valid,\n dst_clk => ADCxN_clk,\n"} |
| {"file": "A-VideoBoard/quartus/PLL_14_625.vhd", "target_type": "architecture_body", "cursor_line": 96, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\tport_scandata\t\t: STRING;\n\t\tport_scandataout\t\t: STRING;\n\t\tport_scandone\t\t: STRING;\n\t\tport_scanread\t\t: STRING;\n\t\tport_scanwrite\t\t: STRING;\n"} |
| {"file": "Artix-7-HDMI-processing/src/conversion_to_RGB.vhd", "target_type": "process_statement", "cursor_line": 217, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " s1_W <= '0' & in_W;\r\n end if; \r\n"} |
| {"file": "FPGA-radio/demo/bsp_components/test_bench/pwm_tb.vhd", "target_type": "process_statement", "cursor_line": 35, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " process\n begin\n while True loop\n CLK <= '0';\n"} |
| {"file": "arcade-galaga/modules/T80/T80as.vhd", "target_type": "process_statement", "cursor_line": 227, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\tbegin\n\t\tif Reset_s = '0' then\n"} |
| {"file": "fp23fftk/src/fastconv/fp23_sfunc_dbl.vhd", "target_type": "process_statement", "cursor_line": 174, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " if rising_edge(clk_dsp) then\r\n if (reset = '1') then\r\n cnt_rdy <= (0 => '1', others => '0');\r\n rd_mx <= '0';\r\n addrb <= (others => '0');\r\n"} |
| {"file": "fpga-dns-adtm/hw/dns-anomaly-arty-a7/dns-anomaly-arty-a7.srcs/sim_1/new/test_dns_pkts.vhd", "target_type": "procedure_body", "cursor_line": 417, "target_nlines": 3, "node_depth": 3, "node_path": ["design_file", "package_body", "declarative_part", "procedure_body"], "target": " SIGNAL E_RXD : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)) IS\n BEGIN\n E_RX_DV <= '1';\n"} |
| {"file": "my-discrete-fpga/vhdl/mux_8_1/tb_mux_74xx151.vhd", "target_type": "entity_declaration", "cursor_line": 23, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity tb_mux_74xx151 is\r\n\r\nend tb_mux_74xx151;\r\n"} |
| {"file": "FPGA_SDR/m2radio/my_fir/mfir_sim/dspba_library.vhd", "target_type": "process_statement", "cursor_line": 48, "target_nlines": 3, "node_depth": 9, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "if_generate_statement", "if_generate", "generate_statement_body", "for_generate_statement", "generate_statement_body", "process_statement"], "target": " delay_signals(i) <= delay_signals(i + 1);\n end if;\n end if;\n"} |
| {"file": "VHDL_Lib/pwm.vhd", "target_type": "process_statement", "cursor_line": 154, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " lockout_o <= HI;\n lockoutCnt_v := lockoutCnt_v - 1;\n else\n"} |
| {"file": "ethernet_mac/xilinx/tx_fifo.vhd", "target_type": "entity_declaration", "cursor_line": 18, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\tdata_i : in t_ethernet_data;\n"} |
| {"file": "fpga-spectrum/spectrum_de1.vhd", "target_type": "entity_declaration", "cursor_line": 71, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t--ROM_OFFSET\t\t\t:\tstd_logic_vector(7 downto 0) := \"00000010\";\r\n\t-- +3\r\n\tROM_OFFSET\t\t\t:\tstd_logic_vector(7 downto 0) := \"00000100\";\r\n\t\r\n\t-- ROM offset for ZXMMC+ external Flash banks\r\n"} |
| {"file": "yafc/vhdl/tb/stack_tb.vhd", "target_type": "architecture_body", "cursor_line": 168, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " write( l, integer'image( i ) );\r\n"} |
| {"file": "getting-started-with-fpgas/chapter08/Turnstile_Example_TB.vhd", "target_type": "entity_declaration", "cursor_line": 5, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity Turnstile_Example_TB is\nend entity Turnstile_Example_TB;\n"} |
| {"file": "neo430/rtl/core/neo430_pwm.vhd", "target_type": "process_statement", "cursor_line": 118, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " if rising_edge(clk_i) then\n"} |
| {"file": "FPGA_ADC/VHDL/calibrationTDCLength/calibrationTDCLength_tb.vhd", "target_type": "process_statement", "cursor_line": 205, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\tstimuli_clk2 : process\n"} |
| {"file": "Hastlayer-SDK/test/Hast.Transformer.Vhdl.Tests/VerificationTests/VerificationSources/CatapultSamplesVerificationTests.Posit32SampleWithInliningMatchesApproved.approved.vhdl", "target_type": "case_statement", "cursor_line": 74104, "target_nlines": 1, "node_depth": 12, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "if_statement", "else", "sequence_of_statements", "case_statement"], "target": " \\Hast::InternalInvocationProxy().Posit32::AssemblePositBitsWithRounding(Boolean,Int32,UInt32,UInt32).targetAvailableIndicator\\(2) := false;\n"} |
| {"file": "HomebrewGPU/HomebrewGPU.ip_user_files/ip/mig/mig_stub.vhdl", "target_type": "architecture_body", "cursor_line": 58, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "attribute syn_black_box : boolean;\nattribute black_box_pad_pin : string;\n"} |
| {"file": "vna2/fpga/vna/vna.srcs/sources_1/new/comm.vhd", "target_type": "entity_declaration", "cursor_line": 48, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " si_wu : out STD_LOGIC;\n last_byte : in STD_LOGIC);\n"} |
| {"file": "xpm_vhdl/src/xpm/xpm_cdc/hdl/xpm_cdc_low_latency_handshake.vhd", "target_type": "process_statement", "cursor_line": 170, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " src_count_ff <= src_count_nxt;\n src_ready_ext_ff <= src_ready_nxt;\n end if;\n end process;\n"} |
| {"file": "CSI2Rx/vhdl_rx/ov-cam-control/ov_i2c_control.vhd", "target_type": "process_statement", "cursor_line": 53, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " begin\n if start_xfer = '1' then\n state_cntr <= \"00000000\";\n else\n"} |
| {"file": "neorv32-setups/osflow/board_tops/neorv32_OrangeCrab_BoardTop_MinimalBoot.vhd", "target_type": "entity_declaration", "cursor_line": 51, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " -- UART0\n OrangeCrab_GPIO_0 : in std_logic;\n"} |
| {"file": "mc1/src/rtl/ram_true_dual_port_vhdl93.vhd", "target_type": "entity_declaration", "cursor_line": 46, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " i_clk_b : in std_logic;\n"} |
| {"file": "FlowBlaze/NetFPGA-SUME-FB/FlowBlaze.src/pipealu.vhd", "target_type": "architecture_body", "cursor_line": 208, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "sh2_7: entity work.shreg generic map (2,3) port map (clk,command(162 downto 160),Op2cx);\nsh2_8: entity work.shreg generic map (2,3) port map (clk,command(165 downto 163),Op2cy);\nsh2_9: entity work.shreg generic map (2,8) port map (clk,command(175 downto 168),Op2cc);\n \n"} |
| {"file": "dsi-shield/hdl/ip_cores/local/generic_dpram.vhd", "target_type": "architecture_body", "cursor_line": 110, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " port (\n rst_n_i : in std_logic := '1';\n clka_i : in std_logic;\n"} |
| {"file": "RFToolSDR/fpga/projects/rx_tx_gen/rx_tx_gen.sim/sim_1/impl/func/ft60x_fifo_if_func_impl.vhd", "target_type": "entity_declaration", "cursor_line": 49329, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " \\G_1PIPE_IFACE.s_daddr_r_reg[4]\\ : in STD_LOGIC;\n \\xsdb_reg_reg[1]\\ : in STD_LOGIC;\n basic_trigger : in STD_LOGIC;\n"} |
| {"file": "intfftk/src/vhdl/math/mults/mlt61x18_dsp48e2.vhd", "target_type": "architecture_body", "cursor_line": 193, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " -- Data: input / output data ports\n A => dspA_M2, -- 30-bit input: A data input\n B => dspB_12, -- 18-bit input: B data input\n C => (others=>'0'),\n D => (others=>'0'),\n"} |
| {"file": "HyperRAM/src/Example_Design/MEGA65/hdmi/serialiser_10to1_selectio.vhd", "target_type": "entity_declaration", "cursor_line": 34, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "end entity serialiser_10to1_selectio;\n"} |
| {"file": "WishboneAXI/cores/Wishbone2AXI/hdl/general-cores/genrams/memory_loader_pkg.vhd", "target_type": "case_statement", "cursor_line": 51, "target_nlines": 5, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "sequence_of_statements", "case_statement"], "target": " when 'd' => t := x\"d\";\n when 'D' => t := x\"d\";\n when 'e' => t := x\"e\";\n when 'E' => t := x\"e\";\n when 'f' => t := x\"f\";\n"} |
| {"file": "potato/testbenches/tb_soc_uart.vhd", "target_type": "architecture_body", "cursor_line": 42, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\t\ttxd => txd,\n"} |
| {"file": "RANC/hardware/Projects/Streaming/src/blockdesign/streaming/ip/streaming_AXIStreamPacketBuffer_0_1/streaming_AXIStreamPacketBuffer_0_1_stub.vhdl", "target_type": "entity_declaration", "cursor_line": 22, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " buffer_overflow_error : out STD_LOGIC;\n buffer_to_stream_error : out STD_LOGIC;\n m00_axis_aclk : in STD_LOGIC;\n m00_axis_aresetn : in STD_LOGIC;\n m00_axis_tvalid : out STD_LOGIC;\n"} |
| {"file": "SMS_MiSTer/rtl/VM2413/attacktable.vhd", "target_type": "architecture_body", "cursor_line": 53, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\n w_mul <= ('0' & i0) * i1;\n"} |
| {"file": "tinyTPU/src/vhdl/Instruction_FIFO/INSTRUCTION_FIFO.vhdl", "target_type": "entity_declaration", "cursor_line": 42, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " UPPER_WORD : in HALFWORD_TYPE; --!< The upper halfword (16 Bit) of the instruction.\n WRITE_EN : in std_logic_vector(0 to 2); --!< Write enable flags for each word.\n \n"} |
| {"file": "vhdl-tutorial/ram/init/ram_sdp_init_array.vhd", "target_type": "process_statement", "cursor_line": 78, "target_nlines": 3, "node_depth": 7, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "if_generate_statement", "if_generate", "generate_statement_body", "process_statement"], "target": " process (clk)\n begin\n if (rising_edge(clk)) then\n"} |
| {"file": "ZJU_computer_architecture/myExp5/Exp5.cache/ip/2018.2/1d5d55521972c550/divider_stub.vhdl", "target_type": "architecture_body", "cursor_line": 31, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "attribute syn_black_box of stub : architecture is true;\r\nattribute black_box_pad_pin of stub : architecture is \"aclk,s_axis_divisor_tvalid,s_axis_divisor_tdata[31:0],s_axis_dividend_tvalid,s_axis_dividend_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[63:0]\";\r\nattribute x_core_info : string;\r\nattribute x_core_info of stub : architecture is \"div_gen_v5_1_13,Vivado 2018.2\";\r\n"} |
| {"file": "scaffold/fpga-arch/system.vhd", "target_type": "process_statement", "cursor_line": 780, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " mtxr_in_spi_sck,\n mtxr_in_spi_mosi,\n mtxr_in_spi_ss,\n mtxr_in_spi_trigger,\n"} |
| {"file": "LumaCode/cabletester/diamond/PLL_28_tmpl.vhd", "target_type": "design_file", "cursor_line": 8, "target_nlines": 2, "node_depth": 0, "node_path": ["design_file"], "target": " CLKOS: out std_logic);\nend component;\n"} |
| {"file": "Vivado-KMeans/lloyds_algorithm_RTL/source/vhdl/madd.vhd", "target_type": "process_statement", "cursor_line": 113, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " \t\telse\n \t\t\tdelay_line(0) <= nd;\n \t\t\tdelay_line(1 to MUL_LATENCY+1-1) <= delay_line(0 to MUL_LATENCY+1-2);\n"} |
| {"file": "gb-research/mbc1b/hdl/cells/odrv.vhd", "target_type": "process_statement", "cursor_line": 21, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " PIN <= '0';\n"} |
| {"file": "tangyRiscVSOC/src/tangyRiscVSOCTop.vhd", "target_type": "entity_declaration", "cursor_line": 34, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " buttonUser: in std_logic; -- high active\n\t\n --leds\n leds: out std_logic_vector( 5 downto 0 );\n"} |
| {"file": "vpcie/src/ebone/src/ebs_bram/src/ebs_bram_pkg.vhd", "target_type": "package_declaration", "cursor_line": 26, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "package_declaration"], "target": "generic (\n EBS_AD_RNGE : natural := 16; -- adressing range\n EBS_AD_BASE : natural := 2; -- usual memory segment\n EBS_AD_SIZE : natural := 512; -- size in segment\n EBS_AD_OFST : natural := 0; -- offset in segment\n"} |
| {"file": "IPECC/hdl/common/ecc_shuffle_pkg.vhd", "target_type": "subtype_declaration", "cursor_line": 27, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "subtype_declaration"], "target": "\tsubtype phys_addr is std_logic_vector(vp_addr_width - 1 downto 0);\n"} |
| {"file": "dvb_fpga/third_party/bch_generated/bch_168x8.vhd", "target_type": "entity_declaration", "cursor_line": 37, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "port (\n\tclk : in std_ulogic;\n\treset : in std_ulogic;\n\tfd : in std_ulogic; -- First data. 1: SEED is used (initialise and calculate), 0: Previous CRC is used (continue and calculate)\n\tnd : in std_ulogic; -- New Data. d input has a valid data. Calculate new CRC\n"} |
| {"file": "VHDL-100-Projects/Stage 1 - Combinational Basics/23_Ripple_Carry_Adder_4_Bit/RCA4Bit_tb.vhd", "target_type": "entity_declaration", "cursor_line": 5, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "ENTITY RCA4Bit_tb IS\nEND RCA4Bit_tb;\n"} |
| {"file": "jcore-cpu/cache/cache_config_sim.vhd", "target_type": "design_file", "cursor_line": 5, "target_nlines": 4, "node_depth": 0, "node_path": ["design_file"], "target": " use configuration work.ram_1rw_sim;\n end for;\n for ram\n for all : ram_2rw\n"} |
| {"file": "img_process_vhdl/integer_div/dsfsa/op_sub.vhd", "target_type": "entity_declaration", "cursor_line": 6, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity op_sub is\ngeneric (\n\t\t\tconstant data_width : integer := 8;\n\t\t\tconstant addr_cnt\t:integer := 20\n"} |
| {"file": "img_process_vhdl/line_buffer/shift_tab_2_2.vhd", "target_type": "process_statement", "cursor_line": 147, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\t\t\t\n\t\t\t\t\tfifo_en_count <= fifo_en_count + 1;\n\t\t\t\t\t-- alt_tap = img_width - (window_size - 1)\n"} |
| {"file": "FmcPGA/ips/txt_idx_map_rom/synth/txt_idx_map_rom.vhd", "target_type": "entity_declaration", "cursor_line": 63, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);\n douta : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)\n );\nEND txt_idx_map_rom;\n"} |
| {"file": "openfpga-SNES/rtl/chip/GSU/GSU.vhd", "target_type": "process_statement", "cursor_line": 752, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\t\tend if;\n\t\t\telsif CPU_EN = '1' then\n"} |
| {"file": "openfpga-SNES/rtl/chip/SPC7110/SPC7110.vhd", "target_type": "process_statement", "cursor_line": 523, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\t\t\t\t\tFIFO_WR <= '1';\n\t\t\t\t\t\t\tDEC_ADDR <= std_logic_vector( unsigned(DEC_ADDR) + 1 );\n\t\t\t\t\t\t\tDROM_READ <= '0';\n\t\t\t\t\t\t\tWS <= WS_LOAD_FIFO3;\n\t\t\t\t\t\tend if;\n"} |
| {"file": "Event-Driven-Spiking-Neural-Network-Accelerator-for-FPGA/hardware/ip_repo/snn_top_hls/hdl/vhdl/snn_top_hls_snn_top_hls_Pipeline_VITIS_LOOP_529_14.vhd", "target_type": "process_statement", "cursor_line": 507, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " else \n p_ZL13weight_memory_7_ce0_local <= ap_const_logic_0;\n"} |
| {"file": "Event-Driven-Spiking-Neural-Network-Accelerator-for-FPGA/hardware/ip_repo/snn_top_hls/hdl/vhdl/snn_top_hls_snn_top_hls_Pipeline_VITIS_LOOP_529_18.vhd", "target_type": "process_statement", "cursor_line": 506, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " p_ZL13weight_memory_7_ce0_local <= ap_const_logic_1;\n else \n p_ZL13weight_memory_7_ce0_local <= ap_const_logic_0;\n end if; \n end process;\n"} |
| {"file": "FPGA_Webserver/hdl/icmp/icmp_handler.vhd", "target_type": "entity_declaration", "cursor_line": 46, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " packet_out_request : out std_logic := '0';\n packet_out_granted : in std_logic := '0';\n packet_out_valid : out std_logic := '0'; \n"} |
| {"file": "FPGA_Webserver/testbenches/tb_defragment_and_check_crc.vhd", "target_type": "entity_declaration", "cursor_line": 31, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity tb_defragment_and_check_crc is\r\n Port ( a : in STD_LOGIC);\r\nend tb_defragment_and_check_crc;\r\n"} |
| {"file": "FPGA_DisplayPort/src/top_level.vhd", "target_type": "architecture_body", "cursor_line": 194, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " signal tx_swing_0p4 : STD_LOGIC := '1';\r\n signal tx_swing_0p6 : STD_LOGIC := '0';\r\n signal tx_swing_0p8 : STD_LOGIC := '0';\r\n"} |
| {"file": "FPGA_DisplayPort/test_benches/tb_aux_test.vhd", "target_type": "architecture_body", "cursor_line": 79, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\r\nuut: aux_test PORT MAP (\r\n"} |
| {"file": "OSVVM/OsvvmTypesPkg.vhd", "target_type": "package_declaration", "cursor_line": 46, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "package_declaration"], "target": "package OsvvmTypesPkg is\n\n type slv_vector is array (integer range <>) of std_logic_vector ; \n type uv_vector is array (integer range <>) of unsigned ; \n type sv_vector is array (integer range <>) of signed ; \n"} |
| {"file": "OSVVM/demo/AlertLog_Demo_Global.vhd", "target_type": "entity_declaration", "cursor_line": 59, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity AlertLog_Demo_Global is\nend AlertLog_Demo_Global ;\n"} |
| {"file": "C64Nano/src/c1541/c1541_sd.vhd", "target_type": "architecture_body", "cursor_line": 321, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\t\t\tend if;\t\n\t\t\tend if;\n\t\t\t\t\n\t\t\t-- save track state machine\n\t\t\tcase save_track_stage is\n"} |
| {"file": "C64Nano/src/gowin_pll/gowin_pll_ntsc.vhd", "target_type": "architecture_body", "cursor_line": 159, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " PLLA_inst: PLLA\r\n generic map (\r\n FCLKIN => \"50\",\r\n IDIV_SEL => 1,\r\n"} |
| {"file": "Digital-IDE/resources/dide-lsp/static/vhdl_std_lib/ieee/numeric_bit.vhdl", "target_type": "constant_declaration", "cursor_line": 60, "target_nlines": 2, "node_depth": 3, "node_path": ["design_file", "package_declaration", "declarative_part", "constant_declaration"], "target": " constant CopyRightNotice : STRING\n := \"Copyright 2008 IEEE. All rights reserved.\";\n"} |
| {"file": "Digital-IDE/resources/dide-lsp/static/vhdl_std_lib/unimacro/unimacro_VCOMP.vhd", "target_type": "case_statement", "cursor_line": 782, "target_nlines": 4, "node_depth": 11, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "case_statement"], "target": " when 10 to 18 => func_width := 10;\n when 19 to 36 => func_width := 9;\n when others => func_width := 12;\n end case;\n"} |
| {"file": "MSX_MiSTer/rtl/CPU/t80pa.vhd", "target_type": "architecture_body", "cursor_line": 198, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\t\t\t\tif TState = \"100\" then\n\t\t\t\t\t\tMREQ_n <= '1';\n"} |
| {"file": "MSX_MiSTer/rtl/VIDEO/vdp_package.vhd", "target_type": "constant_declaration", "cursor_line": 115, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "constant_declaration"], "target": " CONSTANT CLOCKS_PER_LINE : INTEGER := 1368; -- 342*4\r\n"} |
| {"file": "SNES_MiSTer/rtl/chip/DSP/DSPn.vhd", "target_type": "case_statement", "cursor_line": 677, "target_nlines": 2, "node_depth": 12, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "if_statement", "else", "sequence_of_statements", "case_statement"], "target": "\t\t\t\t\twhen x\"21\" => SS_DO <= \"00000\" & STACK_RAM(0)(10 downto 8);\r\n\t\t\t\t\twhen x\"22\" => SS_DO <= STACK_RAM(1)(7 downto 0);\r\n"} |
| {"file": "SNES_MiSTer/rtl/chip/SDD1/InputMgr.vhd", "target_type": "entity_declaration", "cursor_line": 9, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\tCLK\t\t\t: in std_logic;\r\n\t\tENABLE\t\t: in std_logic;\r\n\t\t\r\n\t\tINIT_ADDR\t: in std_logic_vector(23 downto 0);\r\n\t\t\r\n"} |
| {"file": "q27/src/vhdl/PoC/common/strings.vhdl", "target_type": "case_statement", "cursor_line": 195, "target_nlines": 3, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "sequence_of_statements", "case_statement"], "target": "\t\t\twhen 'H' =>\t\t\treturn 'H';\n\t\t\twhen '-' =>\t\t\treturn '-';\n\t\t\twhen others =>\treturn 'X';\n"} |
| {"file": "q27/src/vhdl/top/xilinx/sdrc4_queens_uart.vhdl", "target_type": "entity_declaration", "cursor_line": 49, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " rts : out std_logic\n );\nend sdrc4_queens_uart;\n"} |
| {"file": "Atari800_MiSTer/rtl/common/a8core/atari5200core.vhd", "target_type": "entity_declaration", "cursor_line": 37, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\tVIDEO_G : OUT STD_LOGIC_VECTOR(video_bits-1 DOWNTO 0);\n\t\tVIDEO_R : OUT STD_LOGIC_VECTOR(video_bits-1 DOWNTO 0);\n\t\tVIDEO_BLANK : out std_logic;\n"} |
| {"file": "Atari800_MiSTer/rtl/common/a8core/pbi_rom.vhdl", "target_type": "entity_declaration", "cursor_line": 37, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\tpbi_rom_address: out std_logic_vector(12 downto 0);\n\t\tpbi_rom_address_enable: out std_logic;\n\t\tdata_out: out std_logic_vector(7 downto 0);\n\t\tcache_data_out: out std_logic_vector(7 downto 0);\n\t\tdata_out_enable: out std_logic\n"} |
| {"file": "Arduino-Soft-Core/sources/JTAG_OCD_Prg/JTAGCompPack.vhd", "target_type": "component_declaration", "cursor_line": 87, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "component_declaration"], "target": "\t TCK : in std_logic;\r\n"} |
| {"file": "Arduino-Soft-Core/sources/uC/Papilio_AVR8.vhd", "target_type": "entity_declaration", "cursor_line": 40, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t portc : inout std_logic_vector(7 downto 0);\n\t portd : inout std_logic_vector(7 downto 0);\n\t porte : inout std_logic_vector(7 downto 0);\n"} |
| {"file": "axiom-firmware/peripherals/soc_main/pixel_remap.vhd", "target_type": "process_statement", "cursor_line": 580, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\tif rising_edge(clk) then\n\t if dv_par = '1' then\n\t\tif lval_in = '0' and fval_in = '1' then\n\t\t read_sync <= '1';\n"} |
| {"file": "axiom-firmware/peripherals/soc_main/sync_delay.vhd", "target_type": "process_statement", "cursor_line": 59, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\tend if;\n\n\tdata_out <= sync_v;\n\n"} |
| {"file": "neorv32/rtl/core/neorv32_gptmr.vhd", "target_type": "process_statement", "cursor_line": 104, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " elsif rising_edge(clk_i) then\n clken <= clkgen_i(to_integer(unsigned(clkprsc)));\n"} |
| {"file": "neorv32/rtl/core/neorv32_onewire.vhd", "target_type": "process_statement", "cursor_line": 230, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " irq_o <= '0';\n elsif rising_edge(clk_i) then\n irq_o <= ctrl.enable and (not fifo.tx_avail) and (not serial.busy);\n end if;\n"} |
| {"file": "GBA_MiSTer/rtl/gba_gpioRTCSolarGyro.vhd", "target_type": "case_statement", "cursor_line": 334, "target_nlines": 3, "node_depth": 27, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "if_statement", "elsif", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "case_statement", "case_statement_alternative", "sequence_of_statements", "if_statement", "elsif", "sequence_of_statements", "case_statement", "case_statement_alternative", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "case_statement"], "target": " when x\"67\" => \n dataLen <= to_unsigned(3, dataLen'length);\n data(0) <= \"00\" & buf_tm_hour;\n"} |
| {"file": "GBA_MiSTer/rtl/gba_gpu.vhd", "target_type": "entity_declaration", "cursor_line": 66, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " VRAM_Hi_be : in std_logic_vector(3 downto 0);\n vram_blocked : out std_logic;\n"} |
| {"file": "Gauntlet_FPGA/MiSTer/rtl/gauntlet/CRAMS.vhd", "target_type": "entity_declaration", "cursor_line": 21, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\tI_UDSn\t\t\t\t: in\tstd_logic;\n\t\tI_LDSn\t\t\t\t: in\tstd_logic;\n\t\tI_CRAMn\t\t\t\t: in\tstd_logic;\n\t\tI_BR_Wn\t\t\t\t: in\tstd_logic;\n"} |
| {"file": "Gauntlet_FPGA/MiSTer/rtl/lib/POKEY.vhd", "target_type": "process_statement", "cursor_line": 331, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\tend if;\n"} |
| {"file": "psl_with_ghdl/src/psl_onehot0.vhd", "target_type": "architecture_body", "cursor_line": 31, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\n -- This assertion fails at cycle 15\n ONEHOT0_1_a : assert always onehot0(b);\n\n"} |
| {"file": "psl_with_ghdl/src/psl_prev.vhd", "target_type": "process_statement", "cursor_line": 51, "target_nlines": 1, "node_depth": 6, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "block_statement", "concurrent_statement_part", "process_statement"], "target": " if rising_edge(clk) then\n"} |
| {"file": "XFBAPE/FPGA/filter_lr12_mono.vhd", "target_type": "entity_declaration", "cursor_line": 30, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\ta0 \t\t:\tin signed(coeff_bits - 1 downto 0);\n\ta1 \t\t:\tin signed(coeff_bits - 1 downto 0);\n\ta2 \t\t:\tin signed(coeff_bits - 1 downto 0);\n\n"} |
| {"file": "XFBAPE/FPGA/uart_tx.vhd", "target_type": "process_statement", "cursor_line": 120, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " o_TX_Active <= '0';\n r_TX_Done <= '1';\n r_SM_Main <= s_Idle;\n \n"} |
| {"file": "gcvideo/HDL/gcvideo_dvi/src/dvienc_defs.vhd", "target_type": "constant_declaration", "cursor_line": 83, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "constant_declaration"], "target": " constant UCode_Addr_TMDS : natural := 384;\n"} |
| {"file": "gcvideo/HDL/gcvideo_lite_n64/gcvlite_n64/source/delayline_bool.vhd", "target_type": "process_statement", "cursor_line": 55, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " delayline(delayline'high downto 1) <= delayline(delayline'high - 1 downto 0);\n"} |
| {"file": "SonicSurface/Firmware/FPGA primary/src/UARTSender.vhd", "target_type": "entity_declaration", "cursor_line": 15, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\t out_wire : out STD_LOGIC\r\n"} |
| {"file": "SonicSurface/Firmware/FPGA tactile modulation/src/SwapField.vhd", "target_type": "process_statement", "cursor_line": 43, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\t\t\t\t\tsCounter <= PERIODS_A;\r\n\t\t\t\t\t\tend if;\r\n"} |
| {"file": "SwiftTron/MatMul/MAC_32x8_8_bias_32/bias_sum_32_32.vhd", "target_type": "entity_declaration", "cursor_line": 14, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\toutput_row_20, output_row_21, output_row_22, output_row_23, output_row_24, output_row_25, output_row_26, output_row_27, output_row_28, output_row_29, \n"} |
| {"file": "SwiftTron/NonLinear/I_EXP.vhd", "target_type": "process_statement", "cursor_line": 49, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\tshifter: process(q_l, z)\n"} |
| {"file": "zpu/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top.vhd", "target_type": "entity_declaration", "cursor_line": 67, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " vga_green : out std_logic_vector(7 downto 5);\n"} |
| {"file": "zpu/zpu/hdl/zpu4/src/timer.vhd", "target_type": "architecture_body", "cursor_line": 33, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " cnt <= (others => '0');\n cnt_smp <= (others => '0');\n elsif rising_edge(clk) then\n"} |
| {"file": "SRAI_HW_ACCEL_WINDOWS10_PCIe/hw/Z11_PCIe_gen3x16/IP/shell/PCIe_Bridge_ICAP_complex/ip/PCIe_Bridge_ICAP_complex_clk_wiz_1_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/PCIe_Bridge_ICAP_complex_clk_wiz_1_0_address_decoder.vhd", "target_type": "process_statement", "cursor_line": 491, "target_nlines": 2, "node_depth": 6, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "for_generate_statement", "generate_statement_body", "process_statement"], "target": " end if; \n end process BKEND_RDCE_REG; \n"} |
| {"file": "SRAI_HW_ACCEL_WINDOWS10_PCIe/hw/Z11_PCIe_gen3x16/IP/shell/PCIe_Bridge_ICAP_complex/ip/PCIe_Bridge_ICAP_complex_system_management_wiz_0_0/proc_common_v3_00_a/hdl/src/vhdl/PCIe_Bridge_ICAP_complex_system_management_wiz_0_0_conv_funs_pkg.vhd", "target_type": "case_statement", "cursor_line": 214, "target_nlines": 3, "node_depth": 7, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "sequence_of_statements", "loop_statement", "sequence_of_statements", "case_statement"], "target": "-- when '-' => return_vector(char_ptr-2 to char_ptr) := \"---\";\n-- but synplicity does\n when '_' => char_ptr := char_ptr + 3;\n"} |
| {"file": "Vivado-Design-Tutorials/General/Revision_Control/Manage_IP/sources/manage_ip_prj/axis_vio_pl_master_to_ps/axis_vio_pl_master_to_ps_sim_netlist.vhdl", "target_type": "architecture_body", "cursor_line": 80, "target_nlines": 1, "node_depth": 2, "node_path": ["ERROR", "design_unit", "architecture_body"], "target": " attribute dont_touch of s_axis_tready : signal is \"true\";\n"} |
| {"file": "Vivado-Design-Tutorials/Versal/IO_Design/Multi_bank_source_synchronous_design/Design/Prbs_Any.vhd", "target_type": "entity_declaration", "cursor_line": 116, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " CHK_MODE: boolean := false; \n"} |
| {"file": "fpgagen/CtrlModule/RTL/MergeROM.vhd", "target_type": "process_statement", "cursor_line": 48, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\tif rising_edge(clk) then\n\t\tromsel_a<=from_zpu.memAAddr(maxAddrBitBRAM);\n\t\tromsel_b<=from_zpu.memBAddr(maxAddrBitBRAM);\n\tend if;\nend process;\n"} |
| {"file": "fpgagen/CtrlModule/RTL/OSD_Overlay.vhd", "target_type": "entity_declaration", "cursor_line": 15, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\tred_out : out std_logic_vector(7 downto 0);\n"} |
| {"file": "FPGA-Oscilloscope/FPGA/Test/NIOS/synthesis/NIOS.vhd", "target_type": "entity_declaration", "cursor_line": 9, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity NIOS is\n\tport (\n\t\tclk_clk : in std_logic := '0' -- clk.clk\n\t);\nend entity NIOS;\n"} |
| {"file": "FPGA-Oscilloscope/osc/lpm_compare3.vhd", "target_type": "architecture_body", "cursor_line": 60, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\tGENERIC (\n\t\tlpm_hint\t\t: STRING;\n\t\tlpm_representation\t\t: STRING;\n"} |
| {"file": "patmos/hardware/vhdl/argo/com_spm_wrapper.vhd", "target_type": "architecture_body", "cursor_line": 99, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " n_clk => clk,\n reset => reset,\n ocp_core_m.MCmd => ocp_M_Cmd,\n"} |
| {"file": "patmos/hardware/vivado/netfpga/patmos_netfpga.srcs/sources_1/bd/design_1/ip/design_1_axi_ethernetlite_0_0/sim/design_1_axi_ethernetlite_0_0.vhd", "target_type": "architecture_body", "cursor_line": 172, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " ATTRIBUTE X_INTERFACE_INFO OF phy_rx_data: SIGNAL IS \"xilinx.com:interface:mii:1.0 MII RXD\";\n ATTRIBUTE X_INTERFACE_INFO OF phy_dv: SIGNAL IS \"xilinx.com:interface:mii:1.0 MII RX_DV\";\n ATTRIBUTE X_INTERFACE_INFO OF phy_crs: SIGNAL IS \"xilinx.com:interface:mii:1.0 MII CRS\";\n ATTRIBUTE X_INTERFACE_INFO OF phy_rx_clk: SIGNAL IS \"xilinx.com:interface:mii:1.0 MII RX_CLK\";\n"} |
| {"file": "N64_MiSTer/rtl/VI_outProcess.vhd", "target_type": "process_statement", "cursor_line": 310, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " process (all)\n"} |
| {"file": "N64_MiSTer/rtl/VI_sqrt.vhd", "target_type": "process_statement", "cursor_line": 92, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " process (clk)\n"} |
| {"file": "vhdl-extras/rtl/extras/parity_ops.vhdl", "target_type": "variable_declaration", "cursor_line": 73, "target_nlines": 1, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "declarative_part", "variable_declaration"], "target": " variable xr : std_ulogic;\n"} |
| {"file": "vhdl-extras/rtl/test/test_dual_port_ram.vhdl", "target_type": "process_statement", "cursor_line": 47, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " wr_log(i) := std_ulogic_vector(to_stdlogicvector(random(word'length)));\n end loop;\n\n wait until falling_edge(clock);\n\n"} |
| {"file": "DRAM-Bender/projects/U200/U200.ip_user_files/ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd", "target_type": "process_statement", "cursor_line": 392, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then\n if (Lpf_reset='1' --or \n --System_Reset_Req_d3='1' or\n --Chip_Reset_Req_d3='1' or \n\t --ris_edge = '1'\n"} |
| {"file": "FPGA-proj/CNN_minist/CNN_minist.runs/picture_784_synth_1/picture_784_sim_netlist.vhdl", "target_type": "architecture_body", "cursor_line": 245, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_2_synth is\nbegin\n\\gnbram.gnativebmg.native_blk_mem_gen\\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top\n"} |
| {"file": "FPGA-proj/CNN_minist/CNN_minist.srcs/sources_1/ip/B_conv1/B_conv1_stub.vhdl", "target_type": "entity_declaration", "cursor_line": 19, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " addra : in STD_LOGIC_VECTOR ( 2 downto 0 );\n douta : out STD_LOGIC_VECTOR ( 16 downto 0 )\n"} |
| {"file": "fpga-fft/generated/fft1024_wide/fft1024_wide_wrapper2.vhd", "target_type": "architecture_body", "cursor_line": 35, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\tcore: entity fft1024_wide generic map(dataBits=>dataBits, twBits=>twBits)\n\t\tport map(clk=>clk, phase=>core_phase(10-1 downto 0), din=>core_din, dout=>core_dout);\n\t\n"} |
| {"file": "fpga-fft/twiddle_multiplier.vhd", "target_type": "entity_declaration", "cursor_line": 17, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\tgeneric(dataBits: integer := 18;\n\t\t\ttwiddleBits: integer := 12;\n\t\t\tsubOrder1,subOrder2: integer := 4;\n\t\t\ttwiddleDelay: integer := 7;\n"} |
| {"file": "CoPro6502/src/T80/DebugSystemXR.vhd", "target_type": "process_statement", "cursor_line": 95, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\tend if;\n"} |
| {"file": "CoPro6502/src/T80/SSRAM.vhd", "target_type": "entity_declaration", "cursor_line": 56, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\tAddrWidth\t: integer := 11;\n\t\tDataWidth\t: integer := 8\n\t);\n\tport(\n\t\tClk\t\t\t: in std_logic;\n"} |
| {"file": "AtomBusMon/src/AVR8/JTAG_OCD_Prg/JTAGCompPack.vhd", "target_type": "design_file", "cursor_line": 77, "target_nlines": 4, "node_depth": 0, "node_path": ["design_file"], "target": "\r\ncomponent Resync1b_cp2 is port(\t \r\n\t cp2 : in std_logic;\r\n\t\t\t\t\t\t\tDIn : in std_logic;\r\n"} |
| {"file": "AtomBusMon/src/AVR8/uC/BusMastCompPack.vhd", "target_type": "component_declaration", "cursor_line": 82, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "component_declaration"], "target": "\t\t\t\t\t mack : in std_logic;\r\n \t\t\t\t -- Interrupt support\r\n\t\t\t aes_irq : out std_logic;\r\n"} |
| {"file": "PSX_MiSTer/rtl/cd_xa.vhd", "target_type": "process_statement", "cursor_line": 506, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " end if;\n \n when RESAMPLE_CLAMP =>\n if (resampleSum < -32768) then clamp := x\"8000\";\n"} |
| {"file": "PSX_MiSTer/sim/system/src/rs232/tbrs232_transmitter.vhd", "target_type": "entity_declaration", "cursor_line": 7, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " port \n (\n"} |
| {"file": "fletcher/hardware/arrays/ArrayConfig_pkg.vhd", "target_type": "constant_declaration", "cursor_line": 222, "target_nlines": 1, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "declarative_part", "constant_declaration"], "target": " constant cmd : string := parse_command(cfg);\n"} |
| {"file": "fletcher/hardware/arrays/ArrayReaderList.vhd", "target_type": "entity_declaration", "cursor_line": 79, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " bcd_clk : in std_logic;\n"} |
| {"file": "FpgasNowWhat/Chapters/FirstFpgaDownload/FPGA/XuLA/blinker/blinkerTestBench.vhd", "target_type": "architecture_body", "cursor_line": 43, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " PORT(\n clk_i : IN std_logic;\n blinker_o : OUT std_logic\n"} |
| {"file": "FpgasNowWhat/Chapters/Rams/FPGA/XuLA2/SdramSPInst/SdramCntl.vhd", "target_type": "entity_declaration", "cursor_line": 246, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " clk_i : in std_logic; -- Master clock.\n lock_i : in std_logic := YES; -- True if clock is stable.\n"} |
| {"file": "gplgpu/hdl/sim_lib/220model.vhd", "target_type": "entity_declaration", "cursor_line": 2051, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " lpm_width : natural; \n -- Specifies the number of clock cycles of latency associated with the\n -- alb, aeb, agb, ageb, aleb or aneb output.\n lpm_pipeline : natural := 0;\n"} |
| {"file": "gplgpu/hdl/sim_lib/arriaii_atoms.vhd", "target_type": "process_statement", "cursor_line": 9687, "target_nlines": 4, "node_depth": 8, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "block_statement", "concurrent_statement_part", "for_generate_statement", "generate_statement_body", "process_statement"], "target": " VitalPathDelay01 (\n OutSignal => dataout(i),\n OutSignalName => \"dataout\",\n OutTemp => dataout_tmp(i),\n"} |
| {"file": "bladeRF-wiphy/fpga/vhdl/wlan_correlator.vhd", "target_type": "process_statement", "cursor_line": 79, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " accum(i).i <= resize(shift_right(preamble(i).i*sample.i + preamble(i).q*sample.q, 14),16);\n accum(i).q <= resize(shift_right(- preamble(i).q*sample.i + preamble(i).i*sample.q, 14),16);\n"} |
| {"file": "bladeRF-wiphy/fpga/vhdl/wlan_phase_correction.vhd", "target_type": "case_statement", "cursor_line": 324, "target_nlines": 3, "node_depth": 6, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "case_statement"], "target": " when READ_SAMPLES =>\n if( fifo_empty = '0' ) then\n future.rindex <= current.rindex + 1 ;\n"} |
| {"file": "HDMI2USB-numato-opsis-sample-code/comms/ulpi/vr5-ulpi2utmi/ulpi_port.vhdl", "target_type": "entity_declaration", "cursor_line": 19, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\tulpi_nxt : in std_logic;\n"} |
| {"file": "HDMI2USB-numato-opsis-sample-code/video/displayport/output/src/test_streams/test_source.vhd", "target_type": "entity_declaration", "cursor_line": 55, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " Port ( clk : in STD_LOGIC;\r\n stream_channel_count : out std_logic_vector(2 downto 0);\r\n ready : out STD_LOGIC;\r\n"} |
| {"file": "BIT-CS-Learning/大四/组成原理+汇编小学期/团队设计提交/接口控制器设计源代码/pipelinecpu/pipelinecpu.cache/ip/2019.2/61ae6898a8c27183/inst_rom_sim_netlist.vhdl", "target_type": "entity_declaration", "cursor_line": 310, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " port (\n a : in STD_LOGIC_VECTOR ( 9 downto 0 );\n d : in STD_LOGIC_VECTOR ( 31 downto 0 );\n dpra : in STD_LOGIC_VECTOR ( 9 downto 0 );\n clk : in STD_LOGIC;\n"} |
| {"file": "BIT-CS-Learning/大四/组成原理+汇编小学期/团队设计提交/流水线CPU源代码/pipelinecpu_origin/pipelinecpu_origin.cache/ip/2019.2/e77f6459d38ac1e5/inst_rom_sim_netlist.vhdl", "target_type": "entity_declaration", "cursor_line": 468, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " attribute C_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dist_mem_gen_v8_0_13 : entity is 1024;\n attribute C_ELABORATION_DIR : string;\n"} |
| {"file": "FPGAandGames/TETRIS/fpgatetris_xilinx/tetris/fpgatetris.cache/ip/2018.3/c364994f323bb313/string_rom_gameover_stub.vhdl", "target_type": "architecture_body", "cursor_line": 24, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is\nattribute syn_black_box : boolean;\nattribute black_box_pad_pin : string;\nattribute syn_black_box of stub : architecture is true;\n"} |
| {"file": "FPGAandGames/TETRIS/fpgatetris_xilinx/tetris/fpgatetris.srcs/sources_1/ip/string_rom_gameover/string_rom_gameover_stub.vhdl", "target_type": "architecture_body", "cursor_line": 27, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "attribute syn_black_box of stub : architecture is true;\nattribute black_box_pad_pin of stub : architecture is \"clka,addra[8:0],douta[38:0]\";\nattribute x_core_info : string;\nattribute x_core_info of stub : architecture is \"blk_mem_gen_v8_4_2,Vivado 2018.3\";\n"} |
| {"file": "Open-Source-FPGA-Bitcoin-Miner/projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/rd_dc_as.vhd", "target_type": "design_file", "cursor_line": 134, "target_nlines": 4, "node_depth": 0, "node_path": ["design_file"], "target": "jlOOACDwafr3KbdqWTewATnsEoyZxYKv0dKTg84D14qn09VeqUZ8ClgdHoQSSTn0qopR/N0dpDUg\nD1REjWolaWI9PctH6n1risUccQKnTwOApk/U9BOfkEgaRysYwMaNCzM+Xg+Sk3QDiapfOoU32xf9\nOhyOrHRyqjQdY4xNF3jqaAMTIZYNCaWjAeGCS6APWS+c/QzTfHTTT10XK2t0jcP9CVr9X/VxtkwP\nb0EOs85i1fxZP+Ak1khftCxiRwZ3GaOIEGHqtLf7oupKbOybo5txLnRVRw0uEgwnKit76v2CxaUT\n"} |
| {"file": "Open-Source-FPGA-Bitcoin-Miner/projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/wr_pf_sshft.vhd", "target_type": "design_file", "cursor_line": 91, "target_nlines": 4, "node_depth": 0, "node_path": ["design_file"], "target": "jA+1hDdR/LJ8ipmhswB/2IyDy6Uup0Irga7idX3BNLc5O9iNTIT5mdapmQCVtI63bt7xVIBHhjW7\n8UwpC6tu8kD13txt3vy8/kUwIFYrI0cNWml2V8zKRhP3ADGcwBP4+IUHEBzSHjP19OkKCW4NtbTi\nsj7aTaVczCaiJ0XSXoraVvaCEj//aB6Y2L5hB9Gy4/Ex4Vl/Xj/wfX63yJJYI9JitKE5zjxzVvj7\naJ8VubiZQjbHnuqMGIl5yIlruc8LfTSa9lSgkUPYyOMmH6jWzbB0qhrKp40VPT7FBpTbHpzjiz4m\n"} |
| {"file": "apis_anatolia/VHDL_ile_FPGA_PROGRAMLAMA/ders28/ADT7420.vhd", "target_type": "architecture_body", "cursor_line": 110, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": ");\n\ncntr250msEn\t<= '1';\n\n--------------------------------------------------------------------------------------------------------------------------------\n"} |
| {"file": "apis_anatolia/website/using_fifo_for_cdc_uart_ex/sim/tb_high_speed_uart.vhd", "target_type": "entity_declaration", "cursor_line": 17, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity tb_high_speed_uart is\nend tb_high_speed_uart;\n"} |
| {"file": "dynamatic/data/vhdl/arith/xori.vhd", "target_type": "architecture_body", "cursor_line": 39, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\n result <= lhs xor rhs;\n"} |
| {"file": "dynamatic/data/vhdl/handshake/one_slot_break_dvr.vhd", "target_type": "architecture_body", "cursor_line": 25, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "begin\n\n control : entity work.one_slot_break_dvr_dataless\n"} |
| {"file": "msx1fpga/src/peripheral/tb_keyboard/ps2_iobase.vhd", "target_type": "architecture_body", "cursor_line": 52, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\tend loop;\n\tend procedure;\n"} |
| {"file": "msx1fpga/src/syn-de2/pll2.vhd", "target_type": "entity_declaration", "cursor_line": 45, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\tinclk0\t\t: IN STD_LOGIC := '0';\n\t\tc0\t\t: OUT STD_LOGIC ;\n\t\tc1\t\t: OUT STD_LOGIC \n\t);\nEND pll2;\n"} |
| {"file": "Papilio-Arcade/A2601/scripts/cart_rom_ram.vhd", "target_type": "case_statement", "cursor_line": 38, "target_nlines": 2, "node_depth": 8, "node_path": ["design_file", "design_unit", "architecture_body", "declarative_part", "function_body", "sequence_of_statements", "loop_statement", "sequence_of_statements", "case_statement"], "target": " when 'D' => result(i*4+3 downto i*4) := x\"D\";\n when 'E' => result(i*4+3 downto i*4) := x\"E\";\n"} |
| {"file": "Papilio-Arcade/scramble_rel001_papilio/source/scramble_ram.vhd", "target_type": "architecture_body", "cursor_line": 85, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " we <= I_CS and (not I_RW_L);\r\n end process;\r\n"} |
| {"file": "cps2_digiav/board/cps1/rtl/fir_2ch_audio/auk_dspip_math_pkg_hpfir.vhd", "target_type": "variable_declaration", "cursor_line": 168, "target_nlines": 1, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "declarative_part", "variable_declaration"], "target": " variable res : integer;\n"} |
| {"file": "cps2_digiav/board/cps1/rtl/fir_2ch_audio_sim/dspba_library.vhd", "target_type": "process_statement", "cursor_line": 286, "target_nlines": 1, "node_depth": 10, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "if_generate_statement", "if_generate", "generate_statement_body", "if_generate_statement", "if_generate", "generate_statement_body", "process_statement"], "target": " counter <= (others => '0');\n"} |
| {"file": "ocm-pld-dev/esemsx3/src/video/vdp_wait_control.vhd", "target_type": "process_statement", "cursor_line": 243, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " BEGIN\n IF( CLK21M'EVENT AND CLK21M = '1' )THEN\n WAIT_ROM_Q <= WAIT_ROM(COMBINED_ADDR_REG);\n END IF;\n END PROCESS;\n"} |
| {"file": "ocm-pld-dev/ocm_sm/init_smx/src_addons/top.vhd", "target_type": "entity_declaration", "cursor_line": 61, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " sdram_clk_o : out std_logic;\n sdram_cs_o : out std_logic;\n sdram_we_o : out std_logic;\n\n -- PS/2\n"} |
| {"file": "ghdl-yosys-plugin/examples/icestick/leds/blink.vhdl", "target_type": "architecture_body", "cursor_line": 10, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " counter := x\"000000\";\n clk_4hz <= not clk_4hz;\n else\n"} |
| {"file": "ghdl-yosys-plugin/testsuite/issues/issue4/counter8.vhdl", "target_type": "architecture_body", "cursor_line": 14, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " process (clk)\n"} |
| {"file": "scopy-fpga/logic/logic.cache/ip/2019.2/1d9cd87141295ff0/clk_wiz_1_idelay_refclk_sim_netlist.vhdl", "target_type": "architecture_body", "cursor_line": 153, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),\n DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,\n"} |
| {"file": "scopy-fpga/logic/logic.ip_user_files/bd/design_1/ip/design_1_clk_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/design_1_clk_wiz_0_0_address_decoder.vhd", "target_type": "entity_declaration", "cursor_line": 144, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " ( \n X\"0000_0000_1000_0000\", -- IP user0 base address \n X\"0000_0000_1000_01FF\", -- IP user0 high address \n X\"0000_0000_1000_0200\", -- IP user1 base address \n"} |
| {"file": "FPGAandUSB3.0/FPGASource/StreamerIN/streamin.cache/ip/2018.3/b8e013e808cdffcc/dbg_hub_sim_netlist.vhdl", "target_type": "entity_declaration", "cursor_line": 9230, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " );\nend decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbm_v3_0_0_ctl_reg;\n"} |
| {"file": "FPGAandUSB3.0/FPGASource/UVC_OV5640/uvc_ov5640/uvc_ov5640.srcs/sources_1/ip/fifo_generator_3/fifo_generator_3_stub.vhdl", "target_type": "entity_declaration", "cursor_line": 18, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " wr_clk : in STD_LOGIC;\n rd_clk : in STD_LOGIC;\n din : in STD_LOGIC_VECTOR ( 15 downto 0 );\n wr_en : in STD_LOGIC;\n"} |
| {"file": "DirectNVM/rtl_proj/bd/design_1/ip/design_1_auto_ds_7/design_1_auto_ds_7_sim_netlist.vhdl", "target_type": "architecture_body", "cursor_line": 8459, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " I0 => '0',\n O => ram_afull_i\n );\ni_1: unisim.vcomponents.LUT1\n"} |
| {"file": "DirectNVM/rtl_proj/bd/design_1/ip/design_1_ref_clk_0_buf_0/sim/design_1_ref_clk_0_buf_0.vhd", "target_type": "entity_declaration", "cursor_line": 61, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " IBUF_DS_ODIV2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)\n"} |
| {"file": "Cosmos-plus-OpenSSD/project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_Tiger4NSC_1_0/src/DPBSCFIFO80x64WC/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd", "target_type": "design_file", "cursor_line": 204, "target_nlines": 4, "node_depth": 0, "node_path": ["design_file"], "target": "obq1EFFvP3+STnuRi4JZjmoxVCIBnidcHN0hq6lNDdEbrv1BJ9HxN6ppWUJHRsydw4RZT3ZXpXj7\n5M235BkgZUyU0XUqfv0mjBIx5dd0p6NHmkQ2xo+op1W7dJRzfcRw0+sZWEwFC6mwPc13v2alCppr\nyml4wNPJ4rT+lfKt7vZrKM3d4zPFLqxUTAnP2f3BSm+j2aItYzm+Vybw73ITBU1IaLS/zgJ5nIm2\nrbIUyJHdfedhzJ46x+Xv3jcs5Nu+oXZ4I8Qy0Myoyh7G6gAvU5rA2WwB7cR7uG+4Ib/quG/oAc+b\n"} |
| {"file": "Cosmos-plus-OpenSSD/project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_V2NFC100DDR_1_0/src/SDPRAM_9A16x9B16/synth/SDPRAM_9A16x9B16.vhd", "target_type": "architecture_body", "cursor_line": 324, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),\n s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),\n s_axi_wlast => '0',\n"} |
| {"file": "hard-cv/hw/rtl/primitive/SAC16.vhd", "target_type": "architecture_body", "cursor_line": 78, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\t\t\n\n\t absB <= abs(B);\n\t\t\t\t\n\t sel\t<= \"00\" when absB = 1 else -- selecting shift\n"} |
| {"file": "hard-cv/hw/rtl/primitive/ram_8x64.vhd", "target_type": "entity_declaration", "cursor_line": 8, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\tport(\n \t\tclk : in std_logic; \n \t\twe, en : in std_logic; \n \t\tdo : out std_logic_vector(7 downto 0 ); \n \t\tdi : in std_logic_vector(7 downto 0 ); \n"} |
| {"file": "rfsoc_qpsk/boards/ip/iprepo/rx/rx_decimation/sysgen/xlclockdriver_rd.vhd", "target_type": "process_statement", "cursor_line": 232, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " end if;\n end if;\n"} |
| {"file": "rfsoc_qpsk/boards/ip/iprepo/tx/ip_catalog/axi_qpsk_tx.srcs/sources_1/bd/axi_qpsk_tx_bd/synth/axi_qpsk_tx_bd.vhd", "target_type": "architecture_body", "cursor_line": 728, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " signal microblaze_1_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC;\n signal microblaze_1_axi_periph_to_s00_couplers_BREADY : STD_LOGIC;\n signal microblaze_1_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );\n signal microblaze_1_axi_periph_to_s00_couplers_BVALID : STD_LOGIC;\n"} |
| {"file": "RISC-V_SoC/vivado/soc/soc.cache/ip/2018.3/f99c0fd9519aeb9d/soc_processing_system7_0_0_sim_netlist.vhdl", "target_type": "entity_declaration", "cursor_line": 3416, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );\n S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );\n"} |
| {"file": "RISC-V_SoC/vivado/soc/soc.srcs/sources_1/bd/soc/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd", "target_type": "entity_declaration", "cursor_line": 97, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " (C_VECTOR_WIDTH - 1 downto 0) --\n\n );\n"} |
| {"file": "vscode-terosHDL/tests/formatter/helpers/expected/case_0.vhd", "target_type": "entity_declaration", "cursor_line": 4, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity my_ent_generic_port is\n generic (\n PORT_COUNT : natural;\n port_COUNT : natural;\n generic_COUNT : natural;\n"} |
| {"file": "vscode-terosHDL/tests_impr/documenter/auto/vhdl/sample_1.vhd", "target_type": "entity_declaration", "cursor_line": 42, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " s_axi_rready : in std_logic; --! @end\n\n --! @virtualbus video_in_axi_stream @dir in A slave axi stream interface for video in\n --! axis data bus, transfers two pixels per clock with pixel width of 12 bits in mono color\n"} |
| {"file": "X68000_MiSTer/rtl/memory/cachecont.vhd", "target_type": "process_statement", "cursor_line": 1197, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\telsif rising_edge(sclk) then\r\n\t\t\tif (sys_ce = '1') then\r\n\t\t\t\tcase rmw_state is\r\n\t\t\t\twhen rmw_IDLE =>\r\n"} |
| {"file": "X68000_MiSTer/rtl/pwrcont.vhd", "target_type": "entity_declaration", "cursor_line": 18, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\tsrstn\t:in std_logic;\r\n\tpclk\t:in std_logic;\r\n\tmpu_ce :in std_logic := '1';\r\n\tprstn\t:in std_logic\r\n"} |
| {"file": "NVMeCHA/hw/NVMe_Controller/NVMe_Controller.srcs/sources_1/bd/ps_subsystem/ip/ps_subsystem_clk_wiz_1_0/ps_subsystem_clk_wiz_1_0_sim_netlist.vhdl", "target_type": "architecture_body", "cursor_line": 61, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " attribute XILINX_LEGACY_PRIM of clkout1_buf : label is \"BUFG\";\n attribute BOX_TYPE of mmcme3_adv_inst : label is \"PRIMITIVE\";\n attribute OPT_MODIFIED : string;\n attribute OPT_MODIFIED of mmcme3_adv_inst : label is \"MLO\";\nbegin\n"} |
| {"file": "NVMeCHA/hw/NVMe_Controller/NVMe_Controller.srcs/sources_1/ip/pl_asq_bram/pl_asq_bram_stub.vhdl", "target_type": "entity_declaration", "cursor_line": 22, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " clkb : in STD_LOGIC;\n enb : in STD_LOGIC;\n addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );\n"} |
| {"file": "ztachip/tools/ghdl/ghdl/lib/ghdl/src/ieee2008/numeric_std-body.vhdl", "target_type": "constant_declaration", "cursor_line": 3961, "target_nlines": 1, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "procedure_body", "declarative_part", "constant_declaration"], "target": " constant ne : INTEGER := (VALUE'length+2)/3;\n"} |
| {"file": "ztachip/tools/ghdl/ghdl/lib/ghdl/src/std/v87/textio-body.vhdl", "target_type": "case_statement", "cursor_line": 219, "target_nlines": 3, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "sequence_of_statements", "case_statement"], "target": " when '1' =>\n return '1';\n end case;\n"} |
| {"file": "ZYNQ_ADC_DMA_LWIP/Vivado_proj/Data_Acq_1.cache/ip/2020.1/24700b9d1bdfc876/design_1_clk_wiz_0_0_stub.vhdl", "target_type": "architecture_body", "cursor_line": 27, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "attribute syn_black_box : boolean;\nattribute black_box_pad_pin : string;\nattribute syn_black_box of stub : architecture is true;\nattribute black_box_pad_pin of stub : architecture is \"clk_80M,clk_10M,clk_160M,clk_in1_p,clk_in1_n\";\nbegin\n"} |
| {"file": "ZYNQ_ADC_DMA_LWIP/Vivado_proj/Data_Acq_1.cache/ip/2020.1/6f27797cac6b44fa/design_1_fifo_generator_0_0_stub.vhdl", "target_type": "architecture_body", "cursor_line": 32, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "attribute syn_black_box of stub : architecture is true;\nattribute black_box_pad_pin of stub : architecture is \"wr_clk,rd_clk,din[15:0],wr_en,rd_en,dout[15:0],full,empty\";\nattribute x_core_info : string;\nattribute x_core_info of stub : architecture is \"fifo_generator_v13_2_5,Vivado 2020.1\";\n"} |
| {"file": "BeebFpga/src/common/hdmi/hdmi.vhd", "target_type": "process_statement", "cursor_line": 236, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " state <= videoDataPreamble;\n ctl0 <= '1';\n ctl1 <= '0';\n ctl2 <= '0';\n"} |
| {"file": "BeebFpga/src/common/music5000/Ram2K.vhd", "target_type": "architecture_body", "cursor_line": 30, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\n process (clka)\n begin\n if rising_edge(clka) then\n"} |
| {"file": "MSX-Development/FPGA/ocm-pld v3.9x/esemsx3/src/sound/filter/tb/tb_filter.vhd", "target_type": "process_statement", "cursor_line": 56, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " begin\r\n if( tb_end = '1' )then\r\n wait;\r\n"} |
| {"file": "MSX-Development/FPGA/ocm-pld v3.9x/ocm_sm/init_smxhb/src_addons/top.vhd", "target_type": "process_statement", "cursor_line": 433, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " variable port_a_disc_time : std_logic_vector( 20 downto 0 ) := \"000000000000000000000\";\n"} |
| {"file": "open-logic/src/fix/vhdl/olo_fix_mult.vhd", "target_type": "entity_declaration", "cursor_line": 55, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " In_A : in std_logic_vector(fixFmtWidthFromString(AFmt_g) - 1 downto 0);\n In_B : in std_logic_vector(fixFmtWidthFromString(BFmt_g) - 1 downto 0);\n -- Output\n"} |
| {"file": "open-logic/test/base/olo_base_crc_append/olo_base_crc_append_tb.vhd", "target_type": "case_statement", "cursor_line": 45, "target_nlines": 5, "node_depth": 6, "node_path": ["design_file", "design_unit", "architecture_body", "declarative_part", "function_body", "sequence_of_statements", "case_statement"], "target": " case crcWidth is\n when 8 => return x\"D5\";\n when 16 => return x\"0589\";\n when others => report \"Error: unuspoorted CrcWdith_g\" severity error;\n end case;\n"} |
| {"file": "parallella-examples/rpi-camera/parallella_7020_headless_gpiose_elink2/parallella_7020_headless_gpiose_elink2.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_sg_intrpt.vhd", "target_type": "process_statement", "cursor_line": 563, "target_nlines": 5, "node_depth": 10, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "if_generate_statement", "if_generate", "generate_statement_body", "if_generate_statement", "if_generate", "generate_statement_body", "process_statement"], "target": " ch2_dly_irq_set_i <= '0';\r\n elsif(ch2_dly_fast_incr = '1' and ch2_delay_tc = '1')then\r\n ch2_delay_count <= (others => '0');\r\n ch2_dly_irq_set_i <= '1';\r\n elsif(ch2_dly_fast_incr = '1')then\r\n"} |
| {"file": "parallella-examples/rpi-camera/parallella_7020_headless_gpiose_elink2/parallella_7020_headless_gpiose_elink2.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_vdma_mngr.vhd", "target_type": "process_statement", "cursor_line": 1799, "target_nlines": 5, "node_depth": 10, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "if_generate_statement", "if_generate", "generate_statement_body", "if_generate_statement", "if_generate", "generate_statement_body", "process_statement"], "target": "\t\t flag_to_repeat_after_fsize_less_err <= '0';\n\t\t elsif(fsize_mismatch_err_i = '1')then\n\t\t flag_to_repeat_after_fsize_less_err <= '1';\n\t\t end if;\n\t\t end if;\n"} |
| {"file": "FPGA-robotics/phys_fpga/xilinx_nexys4/ov7670_rgb_yuv_80x60/vhd/pkg_ov7670.vhd", "target_type": "constant_declaration", "cursor_line": 55, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "constant_declaration"], "target": " constant c_nb_line_pxls : natural := log2i(c_img_cols-1) + 1;\n"} |
| {"file": "FPGA-robotics/phys_fpga/xilinx_nexys4/ov7670x2_colorcentroid_160x120/pkg_fun.vhd", "target_type": "case_statement", "cursor_line": 108, "target_nlines": 2, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "sequence_of_statements", "case_statement"], "target": " when 6 => return \"6\";\n when 7 => return \"7\";\n"} |
| {"file": "hdl-modules/modules/common/test/tb_assign_last.vhd", "target_type": "entity_declaration", "cursor_line": 30, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity tb_assign_last is\n generic (\n runner_cfg : string\n );\nend entity;\n"} |
| {"file": "hdl-modules/modules/sine_generator/src/sine_calculator.vhd", "target_type": "entity_declaration", "cursor_line": 191, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " input_phase : in u_unsigned(\n get_phase_width(\n"} |
| {"file": "FGPU/RTL/old/floating_point_2016.2/xbip_pipe_v3_0_2/hdl/xbip_pipe_v3_0.vhd", "target_type": "design_file", "cursor_line": 44, "target_nlines": 1, "node_depth": 0, "node_path": ["design_file"], "target": "`protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n"} |
| {"file": "FGPU/bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_LMEM_4_CACHE_WORDS.vhd", "target_type": "constant_declaration", "cursor_line": 147, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "constant_declaration"], "target": " constant PHASE_LEN : natural := 2**PHASE_W;\r\n"} |
| {"file": "Digital-Hardware-Modelling/vhdl/filter/fir_picoblaze/ssg_display_shared_package.vhdl", "target_type": "subtype_declaration", "cursor_line": 45, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "subtype_declaration"], "target": "\tsubtype FSM_STATE_T is std_logic_vector(DIGIT_CNT-1 downto 0);\r\n"} |
| {"file": "Digital-Hardware-Modelling/xilinx-vivado-hls/pointer_basic/proj_pointer_basic/solution2/syn/vhdl/pointer_basic_pointer_basic_io_s_axi.vhd", "target_type": "process_statement", "cursor_line": 171, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " waddr_proc : process (ACLK)\r\n"} |
| {"file": "HDMI2USB-jahanzeb-firmware/ipcore_dir/bytefifoFPGA/simulation/bytefifoFPGA_pctrl.vhd", "target_type": "process_statement", "cursor_line": 226, "target_nlines": 2, "node_depth": 7, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "if_generate_statement", "if_generate", "generate_statement_body", "process_statement"], "target": " IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN\n sim_stop_cntr <= sim_stop_cntr - \"1\";\n"} |
| {"file": "HDMI2USB-jahanzeb-firmware/ipcore_dir/rgbfifo.vhd", "target_type": "architecture_body", "cursor_line": 195, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " c_prog_empty_thresh_assert_val_wrch => 1022,\n"} |
| {"file": "Open-GPGPU-FlexGrip-/FlexGripPlus_4.4/RTL/SMP/Pipeline/Execution/RRO/Components/fp_leading_zeros_and_shift.vhd", "target_type": "process_statement", "cursor_line": 65, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " for i in PLOG downto 0 loop\n if (leadZerosBin(i) = '1') then\n dtemp := (others => '0');\n"} |
| {"file": "Open-GPGPU-FlexGrip-/FlexGripPlus_4.4/RTL/dp_ram.vhd", "target_type": "architecture_body", "cursor_line": 44, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\n\ttype mem_type is array (0 to RAM_SIZE - 1) of std_logic_vector(RAM_D_WIDTH - 1 downto 0);\n\n\t--impure function init_mem(mif_file_name : in string) return mem_type is\n"} |
| {"file": "ipbus-firmware/components/ipbus_core/firmware/hdl/trans_arb.vhd", "target_type": "entity_declaration", "cursor_line": 49, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " trans_in: in ipbus_trans_out;\n pkt: out std_logic_vector(NSRC - 1 downto 0)\n );\n\nend trans_arb;\n"} |
| {"file": "ipbus-firmware/components/ipbus_util/firmware/hdl/ipbus_sysmon_us_int_ref/ipbus_decode_ipbus_sysmon_us.vhd", "target_type": "constant_declaration", "cursor_line": 18, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "constant_declaration"], "target": " constant IPBUS_SEL_WIDTH: positive := 1;\n"} |
| {"file": "zynq_cam_isp_demo/zynq_cam_isp_demo.gen/sources_1/bd/base/ip/base_axi_vdma_0_0/base_axi_vdma_0_0_stub.vhdl", "target_type": "entity_declaration", "cursor_line": 45, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " m_axi_mm2s_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );\n m_axi_mm2s_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );\n m_axi_mm2s_arvalid : out STD_LOGIC;\n"} |
| {"file": "zynq_cam_isp_demo/zynq_cam_isp_demo.gen/sources_1/bd/base/ipshared/0513/hdl/lib_pkg_v1_0_rfs.vhd", "target_type": "variable_declaration", "cursor_line": 390, "target_nlines": 1, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "declarative_part", "variable_declaration"], "target": " variable Result : integer := 0;\n"} |
| {"file": "cpu86/papilio1/kcuart_tx.vhd", "target_type": "entity_declaration", "cursor_line": 60, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " clk : in std_logic);\r\n"} |
| {"file": "cpu86/papilio2_lcd/ipcore_dir/blk_mem_40K.vhd", "target_type": "entity_declaration", "cursor_line": 48, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);\n douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);\n clkb : IN STD_LOGIC;\n web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);\n addrb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);\n"} |
| {"file": "Pynq-CV-OV5640/boards/src/ip/xilinx_com_hls_xf_dilation_accel_1_0/hdl/vhdl/xfExtractPixels.vhd", "target_type": "architecture_body", "cursor_line": 21, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " constant ap_const_logic_1 : STD_LOGIC := '1';\n constant ap_const_boolean_1 : BOOLEAN := true;\n constant ap_const_logic_0 : STD_LOGIC := '0';\n\n"} |
| {"file": "Pynq-CV-OV5640/boards/src/ip/xilinx_com_hls_xf_erosion_accel_1_0/hdl/vhdl/xf_erosion_accel_bkb.vhd", "target_type": "architecture_body", "cursor_line": 58, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\n-- Generate level 3 logic\nmux_3_0 <= mux_2_0 when sel(2) = '0' else mux_2_1;\n\n-- output logic\n"} |
| {"file": "TJCS-Undergraduate-Courses/计算机系统实验-郭玉臣/1853790_庄镇华_郭玉臣老师班_第三次实验/源代码/MucOS/MucOS.srcs/sources_1/bd/design_1/ip/design_1_mdm_1_3/design_1_mdm_1_3_sim_netlist.vhdl", "target_type": "entity_declaration", "cursor_line": 34, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " tdo : in STD_LOGIC;\n Scan_En : in STD_LOGIC;\n Scan_Reset : in STD_LOGIC;\n Scan_Reset_Sel : in STD_LOGIC;\n"} |
| {"file": "TJCS-Undergraduate-Courses/计算机系统实验-郭玉臣/1853790_庄镇华_郭玉臣老师班_第二次实验/源代码/MucOS/MucOS.srcs/sources_1/bd/design_1/ip/design_1_axi_intc_0_2/synth/design_1_axi_intc_0_2.vhd", "target_type": "entity_declaration", "cursor_line": 72, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " s_axi_bready : IN STD_LOGIC;\n s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);\n"} |
| {"file": "yolov3tiny-ZYNQ7000/YOLOV3TINY-ZYNQ/IP/rgb2dvi_v1_2/src/DVI_Constants.vhd", "target_type": "constant_declaration", "cursor_line": 59, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "constant_declaration"], "target": " constant kCtlTkn0 : std_logic_vector(9 downto 0) := \"1101010100\";\n"} |
| {"file": "yolov3tiny-ZYNQ7000/YOLOV3TINY-ZYNQ/VideoDetectionProject/VideoDetectionProject.cache/ip/2021.1/6733417043ac2f13/design_1_Accel_Conv_0_2_stub.vhdl", "target_type": "entity_declaration", "cursor_line": 37, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " S_AXI_LITE_CTRL_rvalid : out STD_LOGIC;\n S_AXI_LITE_CTRL_rready : in STD_LOGIC;\n"} |
| {"file": "AXI4/Axi4/TestCases/TbAxi4_MemoryBurst2.vhd", "target_type": "process_statement", "cursor_line": 65, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " wait for 0 ns ; wait for 0 ns ;\n TranscriptOpen ;\n SetTranscriptMirror(TRUE) ; \n"} |
| {"file": "AXI4/common/src/Axi4OptionsPkg.vhd", "target_type": "case_statement", "cursor_line": 925, "target_nlines": 2, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "sequence_of_statements", "case_statement"], "target": " when AWQOS => return to_integer(AxiBus.WriteAddress.QOS ) ;\n when AWREGION => return to_integer(AxiBus.WriteAddress.Region) ;\n"} |
| {"file": "hdl4fpga/library/sdram/phy_iofifo.vhd", "target_type": "process_statement", "cursor_line": 51, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\tcntr := (others => '0');\n\t\telsif rising_edge(in_clk) then\n\t\t\tif in_rst='1' then\n"} |
| {"file": "hdl4fpga/library/testbench/uart_rx.vhd", "target_type": "architecture_body", "cursor_line": 102, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\t\t\tdata := data ror 8;\n\t\t\tend loop;\n"} |
| {"file": "mega65-core/src/_unused2/dual_stream_blend.vhd", "target_type": "architecture_body", "cursor_line": 165, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " CEP => one, \n CEM => one, \n CECTRL => one, \n CECARRYIN => one, \n\t CECINSUB => one, \n"} |
| {"file": "mega65-core/src/vhdl/i2c_slave.vhdl", "target_type": "case_statement", "cursor_line": 243, "target_nlines": 2, "node_depth": 9, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "case_statement"], "target": " state_reg <= answer_ack_start;\n bits_processed_reg <= 0;\n"} |
| {"file": "rfsoc_ofdm/boards/ip/iprepo/ofdm_interpolator/hdl/ofdm_interpolator_v1_0.vhd", "target_type": "entity_declaration", "cursor_line": 9, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\ts_axis_tdata\t: in std_logic_vector(31 downto 0);\n\t\ts_axis_tready : out std_logic;\n\t\ts_axis_tvalid\t: in std_logic;\n"} |
| {"file": "rfsoc_ofdm/boards/ip/iprepo/ofdm_rx_v0_4/hdl/vhdl/ofdm_rx_src_MoveAvg.vhd", "target_type": "architecture_body", "cursor_line": 129, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " END IF;\n END IF;\n END PROCESS PipelineRegister_process;\n\n"} |
| {"file": "UVVM/uvvm_vvc_framework/src/ti_uvvm_engine.vhd", "target_type": "architecture_body", "cursor_line": 47, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " shared_uvvm_state := INIT_COMPLETED;\n wait;\n end process p_initialize_uvvm;\n"} |
| {"file": "UVVM/uvvm_vvc_framework/tb/maintenance_tb/vvc_tb.vhd", "target_type": "process_statement", "cursor_line": 1202, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\n -- send x\"AA\" from sbi interface to UART 2\n log(ID_LOG_HDR, \"Check simple transmit\", C_SCOPE_J2);\n sbi_write(SBI_VVCT, 2, C_ADDR_TX_DATA, x\"AA\", \"TX_DATA\", C_SCOPE_J2);\n"} |
| {"file": "PoC/src/net/arp/arp_Wrapper.vhdl", "target_type": "process_statement", "cursor_line": 673, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\tif (FSMCache_ARPReq_TimeoutCounter_rst = '1') then\n\t\t\t\tARPReq_TimeoutCounter_s\t\t<= to_signed(ARPREQ_TIMEOUTCOUNTER_MAX, ARPReq_TimeoutCounter_s'length);\n\t\t\telse\n\t\t\t\tARPReq_TimeoutCounter_s\t\t<= ARPReq_TimeoutCounter_s - 1;\n"} |
| {"file": "PoC/src/sim/sim_simulation.v93.vhdl", "target_type": "if_statement", "cursor_line": 77, "target_nlines": 1, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "procedure_body", "sequence_of_statements", "if_statement"], "target": "\t\tif C_SIM_VERBOSE then\t\treport \"simInitialize:\" severity NOTE;\t\t\tend if;\n"} |
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