| {"file": "SystemVerilogAssertions/examples/clock_delay_eg/clock_delay_op.sv", "target_type": "module_declaration", "cursor_line": 31, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\t// Generate Clock here\n\tinitial\n\tbegin\n\t\tclock = 0;\n"} |
| {"file": "SystemVerilogAssertions/examples/clock_delay_eg/clock_delay_range.sv", "target_type": "module_declaration", "cursor_line": 69, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\t\ty = 0;\n\n\t\t#100 $finish;\n"} |
| {"file": "SystemVerilogAssertions/examples/first_match_eg/sequence_first_match.sv", "target_type": "module_declaration", "cursor_line": 46, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " frame=1'b0; irdy=1'b0;\n $display(\"time=%t frame=%0d irdy=%0d\", $time, frame, irdy);\n repeat (5) @(posedge clk);\nendtask\n\n"} |
| {"file": "SystemVerilogAssertions/examples/immediate_assertions/sva_imm_rr.sv", "target_type": "module_declaration", "cursor_line": 1, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "module sva_imm_test;\n\nendmodule\n"} |
| {"file": "SystemVerilogAssertions/projects/round_robin_arb/rr_arb_sva.sv", "target_type": "data_type", "cursor_line": 19, "target_nlines": 1, "node_depth": 5, "node_path": ["ERROR", "interface_or_generate_item", "package_or_generate_item_declaration", "data_declaration", "data_type_or_implicit1", "data_type"], "target": "logic gnt3;\n"} |
| {"file": "custom_uvm_report_server/consumer.sv", "target_type": "variable_decl_assignment", "cursor_line": 24, "target_nlines": 1, "node_depth": 6, "node_path": ["source_file", "ERROR", "class_item", "class_property", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment"], "target": " uvm_blocking_put_imp #(T,consumer #(T)) in;\n"} |
| {"file": "custom_uvm_report_server/custom_report_server.sv", "target_type": "expression", "cursor_line": 429, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "package_or_generate_item_declaration", "net_declaration", "list_of_net_decl_assignments", "net_decl_assignment", "expression", "primary", "concatenation", "expression"], "target": " tracebackinfo_str = {\"\\n\", indentation_str, report_object_name, \",\",\n"} |
| {"file": "custom_uvm_report_server/hello_world.sv", "target_type": "module_declaration", "cursor_line": 33, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " top mytop;\n\n"} |
| {"file": "custom_uvm_report_server/packet.sv", "target_type": "primary", "cursor_line": 33, "target_nlines": 1, "node_depth": 12, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "constraint_declaration", "constraint_block", "constraint_block_item", "constraint_expression", "expression_or_dist", "expression", "expression", "expression", "primary"], "target": " constraint c { addr >= 0 && addr < 'h100; }\n"} |
| {"file": "custom_uvm_report_server/producer.sv", "target_type": "expression", "cursor_line": 67, "target_nlines": 1, "node_depth": 5, "node_path": ["source_file", "ERROR", "class_item", "text_macro_usage", "list_of_actual_arguments", "expression"], "target": " `uvm_info(\"producer\", $sformatf(\"Sending %s\",p.get_name()), UVM_MEDIUM)\n"} |
| {"file": "custom_uvm_report_server/top.sv", "target_type": "operator_assignment", "cursor_line": 66, "target_nlines": 1, "node_depth": 14, "node_path": ["ERROR", "class_item", "class_method", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "blocking_assignment", "operator_assignment"], "target": " super.build_phase(phase);\n"} |
| {"file": "virtio/rtl/virtio/available_ring/handler/virtio_available_ring_handler.sv", "target_type": "simple_identifier", "cursor_line": 102, "target_nlines": 1, "node_depth": 4, "node_path": ["source_file", "package_or_generate_item_declaration", "net_declaration", "ERROR", "simple_identifier"], "target": " always_ff @(posedge aclk or negedge areset_n) begin\n"} |
| {"file": "virtio/rtl/virtio/available_ring/handler/virtio_available_ring_handler_top.sv", "target_type": "module_declaration", "cursor_line": 92, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " );\n\n `LOGIC_AXI4_STREAM_IF_TX_ASSIGN(tx, tx);\n"} |
| {"file": "virtio/rtl/virtio/available_ring/monitor/virtio_available_ring_monitor.sv", "target_type": "expression", "cursor_line": 79, "target_nlines": 1, "node_depth": 5, "node_path": ["source_file", "package_or_generate_item_declaration", "net_declaration", "list_of_net_decl_assignments", "net_decl_assignment", "expression"], "target": " rx.tready = tx.tready && !almost_full;\n"} |
| {"file": "virtio/rtl/virtio/available_ring/monitor/virtio_available_ring_monitor_top.sv", "target_type": "module_declaration", "cursor_line": 86, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " );\n\n `LOGIC_AXI4_STREAM_IF_TX_ASSIGN(tx, tx);\nendmodule\n"} |
| {"file": "virtio/rtl/virtio/packages/virtio_available_ring_pkg.sv", "target_type": "data_type", "cursor_line": 64, "target_nlines": 1, "node_depth": 5, "node_path": ["source_file", "package_declaration", "package_or_generate_item_declaration", "data_declaration", "type_declaration", "data_type"], "target": " typedef request_type_t response_type_t;\n"} |
| {"file": "virtio/tests/virtio/available_ring/handler/virtio_available_ring_handler_unit_test.sv", "target_type": "module_declaration", "cursor_line": 20, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " import virtio_available_ring_pkg::*;\n"} |
| {"file": "AXI-SDCard-High-Speed-Controller/rtl/sd_controller.sv", "target_type": "packed_dimension", "cursor_line": 33, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "module_declaration", "module_ansi_header", "list_of_port_declarations", "ansi_port_declaration", "variable_port_header", "data_type", "packed_dimension"], "target": " input logic[2:0] axilite_arprot,\n"} |
| {"file": "AXI-SDCard-High-Speed-Controller/rtl/sd_controller_axi_writer.sv", "target_type": "case_statement", "cursor_line": 78, "target_nlines": 4, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " next_addr_state = SETUP;\n end\n end\n\n"} |
| {"file": "AXI-SDCard-High-Speed-Controller/rtl/sd_controller_ping_pong_buffer.sv", "target_type": "module_declaration", "cursor_line": 79, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " prop_buffer[write_ptr] <= wprop;\n end\n"} |
| {"file": "AXI-SDCard-High-Speed-Controller/rtl/sd_controller_regfile.sv", "target_type": "case_statement", "cursor_line": 79, "target_nlines": 4, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " RESPONSE: begin\n if(axilite_rready) begin\n next_read_state = IDLE;\n end\n"} |
| {"file": "AXI-SDCard-High-Speed-Controller/rtl/sd_controller_wrapper.v", "target_type": "module_declaration", "cursor_line": 118, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " .R(1'b0), // 1-bit reset\n .S(1'b0) // 1-bit set\n );\n\n always @(posedge sdclk_bufg) begin\n"} |
| {"file": "AXI-SDCard-High-Speed-Controller/rtl/sd_reader.sv", "target_type": "case_statement", "cursor_line": 444, "target_nlines": 4, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " if(ridx >= 17 - 1) begin//crc16 and a stop bit\n next_sddat_state = READY_TO_SUSPEND;\n end\n end\n"} |
| {"file": "AXI-SDCard-High-Speed-Controller/rtl/sdcmd_ctrl.sv", "target_type": "module_declaration", "cursor_line": 66, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " assign resparg = response.arg;\r\n\r\n always_ff @(posedge clk) begin\r\n"} |
| {"file": "clarvi/bram.sv", "target_type": "module_declaration", "cursor_line": 72, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " memory[avs_b_address][i] <= avs_b_writedata[i];\n if (avs_b_read)\n avs_b_readdata <= memory[avs_b_address];\n"} |
| {"file": "clarvi/bram_altsyncram.sv", "target_type": "module_declaration", "cursor_line": 89, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " .clock1 (1'b1),\n .clocken0 (1'b1),\n .clocken1 (1'b1),\n .clocken2 (1'b1),\n"} |
| {"file": "clarvi/clarvi.sv", "target_type": "case_statement", "cursor_line": 547, "target_nlines": 5, "node_depth": 15, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "package_or_generate_item_declaration", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "case_statement", "case_item", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " F3_SLTU: return SLTU;\n F3_XOR: return XOR;\n F3_OR: return OR;\n F3_AND: return AND;\n // for immediate shifts we check the 6th bit in the shift amount is 0\n"} |
| {"file": "clarvi/clarvi_avalon.sv", "target_type": "module_declaration", "cursor_line": 43, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " output logic avm_main_read,\n"} |
| {"file": "clarvi/clarvi_debug.sv", "target_type": "simple_identifier", "cursor_line": 65, "target_nlines": 1, "node_depth": 3, "node_path": ["source_file", "package_or_generate_item_declaration", "net_declaration", "simple_identifier"], "target": " db_rs2_value <= de_ex_rs2_value;\n"} |
| {"file": "clarvi/riscv.svh", "target_type": "variable_decl_assignment", "cursor_line": 131, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "package_or_generate_item_declaration", "data_declaration", "type_declaration", "data_type", "struct_union_member", "list_of_variable_decl_assignments", "variable_decl_assignment"], "target": " logic memory_read;\n"} |
| {"file": "clarvi/sim.sv", "target_type": "module_declaration", "cursor_line": 75, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " memory_debug #(\n .ADDR_WIDTH(ADDR_WIDTH)\n ) main_mem_debug (\n .clock,\n .address(main_address),\n"} |
| {"file": "coolgirl-famicom-multicart/CoolGirl_config.vh", "target_type": "simple_identifier", "cursor_line": 5, "target_nlines": 1, "node_depth": 5, "node_path": ["source_file", "package_or_generate_item_declaration", "parameter_declaration", "list_of_param_assignments", "ERROR", "simple_identifier"], "target": "parameter ENABLE_MAPPER_021_022_023_025 = 1, // mappers #021, #022, #023, #025 - VRC2, VRC4\n"} |
| {"file": "coolgirl-famicom-multicart/CoolGirl_mappers.vh", "target_type": "primary_literal", "cursor_line": 551, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "package_or_generate_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "unpacked_dimension", "constant_range", "constant_expression", "constant_primary", "primary_literal"], "target": " prg_bank_a[7:6] <= cpu_data_in[1:0];\n"} |
| {"file": "coolgirl-famicom-multicart/CoolGirl_rev2.x/CoolGirl.v", "target_type": "simple_identifier", "cursor_line": 20, "target_nlines": 1, "node_depth": 5, "node_path": ["source_file", "package_or_generate_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "ERROR", "simple_identifier"], "target": " output sram_we,\n"} |
| {"file": "coolgirl-famicom-multicart/CoolGirl_rev3.x/CoolGirl.v", "target_type": "simple_identifier", "cursor_line": 47, "target_nlines": 1, "node_depth": 5, "node_path": ["source_file", "package_or_generate_item_declaration", "net_declaration", "list_of_net_decl_assignments", "net_decl_assignment", "simple_identifier"], "target": " assign ppu_addr_out[18:10] = ext_ntram_access\n"} |
| {"file": "coolgirl-famicom-multicart/CoolGirl_rev4.x/CoolGirl.v", "target_type": "simple_identifier", "cursor_line": 70, "target_nlines": 1, "node_depth": 3, "node_path": ["source_file", "package_or_generate_item_declaration", "net_declaration", "simple_identifier"], "target": " assign ppu_data_in = 8'bZZZZZZZZ;\n"} |
| {"file": "coolgirl-famicom-multicart/CoolGirl_rev5.x/CoolGirl.v", "target_type": "primary_literal", "cursor_line": 44, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "package_or_generate_item_declaration", "net_declaration", "list_of_net_decl_assignments", "net_decl_assignment", "unpacked_dimension", "constant_range", "constant_expression", "constant_primary", "primary_literal"], "target": " assign cpu_addr_out[26:13] = {prg_base[26:14] | (prg_addr_mapped[20:14] & ~prg_mask[20:14]), prg_addr_mapped[13]};\n"} |
| {"file": "coolgirl-famicom-multicart/CoolGirl_rev6.x/CoolGirl.v", "target_type": "simple_identifier", "cursor_line": 56, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "package_or_generate_item_declaration", "net_declaration", "list_of_net_decl_assignments", "net_decl_assignment", "expression", "expression", "primary", "simple_identifier"], "target": " assign sram_ce = sram_ce_w | cpu_data_out_enabled;\n"} |
| {"file": "SNN-FPGA/SNN.srcs/sim_1/new/neuron_sim.sv", "target_type": "module_declaration", "cursor_line": 34, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " \n logic spike_out;\n neuron dut(clk, rst, en, potent_in, spike_out);\n \n"} |
| {"file": "SNN-FPGA/SNN.srcs/sim_1/new/snn_sim.sv", "target_type": "module_declaration", "cursor_line": 5, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " logic clk, rst, en;\n always begin clk <= 1'b1; #5; clk <= 1'b0; #5; end\n initial begin rst = 1'b1; #18; rst = 1'b0; end\n"} |
| {"file": "SNN-FPGA/SNN.srcs/sources_1/new/comparer_recursivenode.sv", "target_type": "module_declaration", "cursor_line": 30, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " .DATA_WIDTH(DATA_WIDTH), .TAG_WIDTH(TAG_WIDTH)\n ) rch(\n"} |
| {"file": "SNN-FPGA/SNN.srcs/sources_1/new/counter.sv", "target_type": "module_declaration", "cursor_line": 10, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input logic signal, // signal to be counted\n \n output logic [CNT_WIDTH - 1 : 0] cnt\n);\n\n"} |
| {"file": "SNN-FPGA/SNN.srcs/sources_1/new/hidden_layer.sv", "target_type": "module_declaration", "cursor_line": 39, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " .spike_in(prev_layer_spike),\n .spike_out(curr_layer_spike[k])\n );\n"} |
| {"file": "SNN-FPGA/SNN.srcs/sources_1/new/max_comparer.sv", "target_type": "module_declaration", "cursor_line": 11, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " comparer_recursivenode #(\n .LEFT(0), .RIGHT(ITEM_CNT-1),\n"} |
| {"file": "SNN-FPGA/SNN.srcs/sources_1/new/neuron.sv", "target_type": "module_declaration", "cursor_line": 49, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " sum_potent_in = sum_potent_in + potent_in[i];\n"} |
| {"file": "SNN-FPGA/SNN.srcs/sources_1/new/snn.sv", "target_type": "module_declaration", "cursor_line": 24, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " logic init_ren, init_wen, init_done;\n always_ff @(posedge clk)\n begin\n if (rst) init_timer <= 1'b0;\n"} |
| {"file": "SystemVerilogSHA256/miner.sv", "target_type": "module_declaration", "cursor_line": 27, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\tassign hashed = {secnd_hash[7:0], secnd_hash[15:8], secnd_hash[23:16], secnd_hash[31:24], secnd_hash[39:32], secnd_hash[47:40], secnd_hash[55:48], secnd_hash[63:56], secnd_hash[71:64], secnd_hash[79:72], secnd_hash[87:80], secnd_hash[95:88], secnd_hash[103:96], secnd_hash[111:104], secnd_hash[119:112], secnd_hash[127:120], secnd_hash[135:128], secnd_hash[143:136], secnd_hash[151:144], secnd_hash[159:152], secnd_hash[167:160], secnd_hash[175:168], secnd_hash[183:176], secnd_hash[191:184], secnd_hash[199:192], secnd_hash[207:200], secnd_hash[215:208], secnd_hash[223:216], secnd_hash[231:224], secnd_hash[239:232], secnd_hash[247:240], secnd_hash[255:248]};\n\nendmodule"} |
| {"file": "SystemVerilogSHA256/miner_tb.sv", "target_type": "module_declaration", "cursor_line": 23, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " \t$display(\"Hash: %h\", hashed);\n \t$finish;\n\tend\nendmodule"} |
| {"file": "SystemVerilogSHA256/sha_256.sv", "target_type": "module_declaration", "cursor_line": 5, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\t\t\t\tparameter PADDED_SIZE = 512)\n"} |
| {"file": "SystemVerilogSHA256/sha_256_tb.sv", "target_type": "module_declaration", "cursor_line": 23, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " \tassign rst = 0;\n \twhile(done !== 1'b1) begin\n"} |
| {"file": "SystemVerilogSHA256/sha_mainloop.sv", "target_type": "module_declaration", "cursor_line": 28, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\tfunction automatic [31:0] rho1;\n\t\tinput [31:0] x;\n\t\tif(^x === 1'bX) rho1 = 32'h888;\n\t\telse rho1 = {x[16:0],x[31:17]} ^ {x[18:0],x[31:19]} ^ (x >> 10);\n\tendfunction\n"} |
| {"file": "SystemVerilogSHA256/sha_mainloop_tb.sv", "target_type": "module_declaration", "cursor_line": 7, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n\tsha_mainloop uut(.padded(padded), .clk(clk), .rst(rst));\n"} |
| {"file": "SystemVerilogSHA256/sha_padder.sv", "target_type": "module_declaration", "cursor_line": 12, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\tassign padded = {message, 1'b1, {zero_width{1'b0}}, {back_0_width{1'b0}}, MSG_SIZE};\n"} |
| {"file": "SystemVerilogSHA256/sha_padder_tb.sv", "target_type": "module_declaration", "cursor_line": 4, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "module sha_padder_tb;\n\tlogic [511:0] padded;\n\tlogic [23:0] message;\n\n"} |
| {"file": "fpga-flight-controller/src/i2c_master.sv", "target_type": "module_declaration", "cursor_line": 187, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\t\t\tdefault: state = STATE_BUSY;\n\t\tendcase\n\t\t\n\t\tcase (state_reg)\n\t\t\tREADY, MISSED_ACK, PRE_WRITE: scl_o = 0;\n"} |
| {"file": "fpga-flight-controller/src/lpf.sv", "target_type": "module_declaration", "cursor_line": 4, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\tinput logic data_ready,\n\tinput logic signed[15:0] value,\n\toutput logic signed[15:0] filtered\n"} |
| {"file": "fpga-flight-controller/src/main.sv", "target_type": "module_declaration", "cursor_line": 9, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\toutput logic[2:0] LEDS\n);\n\tlocalparam signed MOTOR_MIN = 190;\n\tlocalparam signed MOTOR_MAX = 600;\n"} |
| {"file": "fpga-flight-controller/src/mpu6050_driver.sv", "target_type": "module_declaration", "cursor_line": 40, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\tlocalparam REG_GYRO_CONFIG = 8'd27;\n"} |
| {"file": "fpga-flight-controller/src/pid.sv", "target_type": "module_declaration", "cursor_line": 17, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\t\n\twire signed[60:0] scaled_gyro = gyro * FS; // 15 bits to right of binary point\n\twire signed[63:0] scaled_gyro_aligned = {scaled_gyro, {3{1'b0}}}; // 18 bits to right of binary point\n\t\n"} |
| {"file": "fpga-flight-controller/src/pid_test.sv", "target_type": "module_declaration", "cursor_line": 5, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": ");\n\n\tpid(.gyro, .stick, .power);\n\t\n"} |
| {"file": "fpga-flight-controller/src/ppm_decoder.sv", "target_type": "module_declaration", "cursor_line": 33, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\tend else begin\n\t\tlast_ppm <= ppm;\n\t\t//ch_out <= '{ch[0], ch[1], ch[2], ch[3], ch[4], ch[5]};\n\t\tif(ppm & ~last_ppm) begin\n"} |
| {"file": "fpga-flight-controller/src/pwm_encoder.sv", "target_type": "module_declaration", "cursor_line": 5, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "input logic [11:0] val [0:3];\noutput logic [3:0] pwm = 4'b0;\n\n"} |
| {"file": "labs-with-cva6/labs/caching/part2/starter/tb/assert.svh", "target_type": "simple_identifier", "cursor_line": 9, "target_nlines": 1, "node_depth": 4, "node_path": ["source_file", "text_macro_definition", "text_macro_name", "text_macro_identifier", "simple_identifier"], "target": "`define ASSERT(CONDITION, MESSAGE) if ((CONDITION)==1'b1); else begin $display($sformatf(\"Error: %s\", $sformatf MESSAGE)); ERROR = 1; end\n"} |
| {"file": "labs-with-cva6/labs/caching/part2/starter/tb/victim_cache_tb.sv", "target_type": "primary", "cursor_line": 52, "target_nlines": 1, "node_depth": 14, "node_path": ["ERROR", "module_or_generate_item", "initial_construct", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "procedural_timing_control_statement", "event_control", "event_expression", "expression", "primary"], "target": "@(negedge clk_i);\n"} |
| {"file": "labs-with-cva6/labs/caching/part2/starter/ucsbece154b_victim_cache.sv", "target_type": "module_declaration", "cursor_line": 120, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " MEM_d[lru_d].data = 0; // TODO\n MEM_d[lru_d].tag = 0; // TODO\n MEM_d[lru_d].valid = 0; // TODO\n lru_d = 0; // TODO\n"} |
| {"file": "labs-with-cva6/labs/caching/part2/starter/unread.sv", "target_type": "module_declaration", "cursor_line": 16, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "module unread (\n input logic d_i\n);\n\nendmodule\n"} |
| {"file": "labs-with-cva6/labs/caching/part2/ucsbece154b_icache.sv", "target_type": "case_statement", "cursor_line": 346, "target_nlines": 4, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " // value is being written to victim cache\n // then we need need to do memory request write to icache sram\n VICTIM_MISS: begin\n cmp_en_d = 1'b0;\n"} |
| {"file": "labs-with-cva6/labs/sv/starter/tb/assert.svh", "target_type": "simple_identifier", "cursor_line": 9, "target_nlines": 1, "node_depth": 4, "node_path": ["source_file", "text_macro_definition", "text_macro_name", "text_macro_identifier", "simple_identifier"], "target": "`define ASSERT(CONDITION, MESSAGE) if ((CONDITION)==1'b1); else begin $display($sformatf(\"Error: %s\", $sformatf MESSAGE)); ERROR = 1; end\n"} |
| {"file": "labs-with-cva6/labs/sv/starter/tb/fifo_tb.sv", "target_type": "primary", "cursor_line": 13, "target_nlines": 1, "node_depth": 7, "node_path": ["ERROR", "module_or_generate_item", "package_or_generate_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "expression", "primary"], "target": "logic clk_i = 0;\n"} |
| {"file": "labs-with-cva6/labs/sv/starter/ucsbece154b_fifo.sv", "target_type": "module_declaration", "cursor_line": 12, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n output logic [DATA_WIDTH-1:0] data_o,\n"} |
| {"file": "mipi-csi-2/src/camera.sv", "target_type": "primary_literal", "cursor_line": 55, "target_nlines": 1, "node_depth": 11, "node_path": ["ERROR", "module_or_generate_item", "continuous_assign", "list_of_net_assignments", "net_assignment", "expression", "primary", "select1", "bit_select1", "expression", "primary", "primary_literal"], "target": "assign data_type = packet_header[0][5:0];\n"} |
| {"file": "mipi-csi-2/src/d_phy_receiver.sv", "target_type": "primary", "cursor_line": 52, "target_nlines": 1, "node_depth": 24, "node_path": ["ERROR", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "nonblocking_assignment", "expression", "expression", "primary"], "target": " zero_accumulator <= zero_accumulator + 1'd1;\n"} |
| {"file": "mipi-csi-2/src/decoders/raw8.sv", "target_type": "module_declaration", "cursor_line": 1, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "module raw8 (\n input logic [7:0] image_data [3:0],\n input logic image_data_enable,\n"} |
| {"file": "mipi-csi-2/src/decoders/rgb565.sv", "target_type": "module_declaration", "cursor_line": 6, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": ");\n\nlogic [31:0] unpacked_image_data;\nassign unpacked_image_data = {image_data[3], image_data[2], image_data[1], image_data[0]};\n\n"} |
| {"file": "mipi-csi-2/src/decoders/rgb888.sv", "target_type": "module_declaration", "cursor_line": 28, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "begin\n if (image_data_enable)\n begin\n"} |
| {"file": "mipi-csi-2/src/decoders/yuv422_8bit.sv", "target_type": "module_declaration", "cursor_line": 1, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "module yuv422_8bit (\n input logic [7:0] image_data [3:0],\n input logic image_data_enable,\n output logic [23:0] yuv [1:0],\n output logic yuv_enable\n"} |
| {"file": "mipi-csi-2/test/camera_tb.sv", "target_type": "case_statement", "cursor_line": 68, "target_nlines": 5, "node_depth": 13, "node_path": ["source_file", "ERROR", "statement_or_null", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " assert (word_count == {TEST1[4], TEST1[3]}) else $fatal(1, \"Expected word count '%h%h' but was %h\", TEST1[4], TEST1[3], word_count);\n assert (image_data_type == TEST1[2]) else $fatal(1, \"Expected data type %h but was %h\", TEST1[2], image_data_type);\n $display(\"Test 1 complete\");\n current_test <= 1;\n test_index <= 1'd0;\n"} |
| {"file": "mipi-csi-2/test/d_phy_receiver_tb.sv", "target_type": "module_declaration", "cursor_line": 71, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " begin\n assert(d_phy_receiver.state == 2'd0) else $fatal(1, \"receiver is in %d but should've returned to UNKNOWN\", d_phy_receiver.state);\n $finish;\n end\n"} |
| {"file": "parallella-riscv/ip/RISCV_Rocket_Core_RV64_1.0/example_designs/bfm_design/RISCV_Rocket_Core_RV64_v1_0_tb.v", "target_type": "module_declaration", "cursor_line": 217, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\t\twait(tb_ARESETn === 0) @(posedge tb_ACLK);\n\t\twait(tb_ARESETn === 1) @(posedge tb_ACLK);\n"} |
| {"file": "parallella-riscv/ip/RISCV_Rocket_Core_RV64_1.0/src/AsyncResetReg.v", "target_type": "expression", "cursor_line": 52, "target_nlines": 1, "node_depth": 9, "node_path": ["ERROR", "module_or_generate_item", "package_or_generate_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "expression", "primary", "multiple_concatenation", "expression"], "target": " _RAND = {1{$random}};\n"} |
| {"file": "parallella-riscv/ip/RISCV_Rocket_Core_RV64_1.0/src/RISCV_Rocket_Core_RV64.v", "target_type": "module_declaration", "cursor_line": 187, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " .S_AXI_BRESP (s_axi_bresp),\n .S_AXI_BVALID (s_axi_bvalid),\n .S_AXI_BREADY (s_axi_bready),\n .S_AXI_ARID (s_axi_arid),\n .S_AXI_ARADDR (s_axi_araddr),\n"} |
| {"file": "parallella-riscv/ip/RISCV_Rocket_Core_RV64_1.0/src/RISCV_Rocket_Core_RV64_AXI.v", "target_type": "primary_literal", "cursor_line": 309, "target_nlines": 1, "node_depth": 20, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "package_or_generate_item_declaration", "data_declaration", "ERROR", "expression", "primary", "function_subroutine_call", "subroutine_call", "tf_call", "list_of_arguments_parent", "expression", "primary", "function_subroutine_call", "subroutine_call", "tf_call", "list_of_arguments_parent", "expression", "primary", "primary_literal"], "target": " .io_ps_axi_slave_aw_bits_cache (4'b0),\n"} |
| {"file": "parallella-riscv/ip/RISCV_Rocket_Core_RV64_1.0/src/RV64IMAFD.Core.vh", "target_type": "module_declaration", "cursor_line": 1, "target_nlines": 3, "node_depth": 1, "node_path": ["ERROR", "module_declaration"], "target": "module IntXbar( // @[:Top.ZynqFPGAConfig.fir@3.2]\n input auto_int_in_1_0, // @[:Top.ZynqFPGAConfig.fir@6.4]\n output auto_int_out_2 // @[:Top.ZynqFPGAConfig.fir@6.4]\n"} |
| {"file": "parallella-riscv/ip/RISCV_Rocket_Core_RV64_1.0/src/plusarg_reader.v", "target_type": "module_declaration", "cursor_line": 19, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "end\n`endif\n"} |
| {"file": "parallella-riscv/ip/RISCV_Rocket_Core_RV64_1.0/src/settings.vh", "target_type": "simple_identifier", "cursor_line": 18, "target_nlines": 1, "node_depth": 4, "node_path": ["source_file", "text_macro_definition", "text_macro_name", "text_macro_identifier", "simple_identifier"], "target": "`define RISCV_DRAM_BASE 3'd1\n"} |
| {"file": "parallella-riscv/parallella/dv/dut_riscv_rv64g.v", "target_type": "primary", "cursor_line": 216, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "module_instantiation", "hierarchical_instance", "list_of_port_connections", "named_port_connection", "expression", "primary"], "target": "\t\t .s_axi_wdata\t(s_axi_wdata[31:0]),\n"} |
| {"file": "Convolutional-Neural-Network-using-SystemVerilog/2D_filter/conv.sv", "target_type": "simple_identifier", "cursor_line": 142, "target_nlines": 1, "node_depth": 35, "node_path": ["ERROR", "cond_predicate", "expression", "conditional_expression", "cond_predicate", "expression", "conditional_expression", "cond_predicate", "expression", "expression", "primary", "function_subroutine_call", "subroutine_call", "system_tf_call", "expression", "expression", "conditional_expression", "cond_predicate", "expression", "expression", "expression", "primary", "function_subroutine_call", "subroutine_call", "tf_call", "ERROR", "constant_bit_select1", "constant_expression", "constant_expression", "constant_expression", "constant_primary", "constant_mintypmax_expression", "constant_expression", "constant_primary", "parameter_identifier", "simple_identifier"], "target": " logic signed [$clog2(KERNEL_DIMENSION)+$size(mult_sum_1dim,2)-1:0]mult_sum_out;\n"} |
| {"file": "Convolutional-Neural-Network-using-SystemVerilog/CNN_TB.sv", "target_type": "expression", "cursor_line": 310, "target_nlines": 1, "node_depth": 18, "node_path": ["ERROR", "module_or_generate_item", "initial_construct", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "loop_statement", "statement", "statement_item", "seq_block", "ERROR", "clockvar_expression", "select1", "bit_select1", "expression"], "target": " weights_mem_in_kernel_wr[0] = 1'b0;\n"} |
| {"file": "Convolutional-Neural-Network-using-SystemVerilog/Fully connected layer/flat.sv", "target_type": "module_declaration", "cursor_line": 53, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " o_valid <= 1'd0;\n\n o_ready <= 1'b1;\n"} |
| {"file": "Convolutional-Neural-Network-using-SystemVerilog/Fully connected layer/fully_connected_layer.sv", "target_type": "module_declaration", "cursor_line": 207, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n reg [DATA_WIDTH-1:0] \tmem [2**ADDR_WIDTH];\n\n"} |
| {"file": "Convolutional-Neural-Network-using-SystemVerilog/activation_func/relu.sv", "target_type": "module_declaration", "cursor_line": 8, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\toutput logic [DIMENSION-1:0][PIX_WIDTH-1:0] o_data \n);\n\n"} |
| {"file": "Convolutional-Neural-Network-using-SystemVerilog/blocks/conv_block.sv", "target_type": "simple_identifier", "cursor_line": 79, "target_nlines": 1, "node_depth": 4, "node_path": ["ERROR", "named_port_connection", "expression", "primary", "simple_identifier"], "target": " .i_valid (i_valid ),\n"} |
| {"file": "Convolutional-Neural-Network-using-SystemVerilog/blocks/max_pooling_block.sv", "target_type": "module_declaration", "cursor_line": 58, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " .cols_cntr( ),\n .rows_cntr( )\n );\n"} |
| {"file": "Convolutional-Neural-Network-using-SystemVerilog/pooling/maxpooling.sv", "target_type": "simple_identifier", "cursor_line": 116, "target_nlines": 1, "node_depth": 7, "node_path": ["ERROR", "statement_or_null", "statement", "statement_item", "loop_statement", "for_initialization", "for_variable_declaration", "simple_identifier"], "target": " for (int i = 1; i < POOL_DIMENSION; i++) begin\n"} |
| {"file": "Convolutional-Neural-Network-using-SystemVerilog/top/CNN.sv", "target_type": "module_declaration", "cursor_line": 179, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " .IN_DIMENSION (FLAT_DIMENSION[numb] ),\n .OUT_DIMENSION (FLAT_DIMENSION[numb+1] )\n ) inst_fully_connected_layer1 (\n .clk (clk ),\n"} |
| {"file": "Convolutional-Neural-Network-using-SystemVerilog/top/CNN.svh", "target_type": "primary_literal", "cursor_line": 1901, "target_nlines": 1, "node_depth": 15, "node_path": ["source_file", "package_or_generate_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "expression", "primary", "assignment_pattern_expression", "assignment_pattern", "expression", "primary", "assignment_pattern_expression", "assignment_pattern", "expression", "primary", "primary_literal"], "target": " 6.7064e-02, -8.3180e-02, 1.3578e-01, 1.7633e-02, -1.0262e-01,\n"} |
| {"file": "LUMOS/Arithmetic_Logic_Unit.v", "target_type": "case_statement", "cursor_line": 31, "target_nlines": 4, "node_depth": 14, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " `ALU_OR : result = operand_1 | operand_2; \n `ALU_XOR : result = operand_1 ^ operand_2; \n\n `ALU_SLT : result = $signed(operand_1) < $signed(operand_2) ? 1 : 0; \n"} |
| {"file": "LUMOS/Defines.vh", "target_type": "simple_identifier", "cursor_line": 55, "target_nlines": 1, "node_depth": 4, "node_path": ["source_file", "text_macro_definition", "text_macro_name", "text_macro_identifier", "simple_identifier"], "target": " `define XORI 3'b100\n"} |
| {"file": "LUMOS/Fixed_Point_Unit.v", "target_type": "module_declaration", "cursor_line": 214, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "module Multiplier_16bit \n(\n input wire [15 : 0] operand_1, \n input wire [15 : 0] operand_2, \n"} |
| {"file": "LUMOS/Fixed_Point_Unit_Testbench.v", "target_type": "module_declaration", "cursor_line": 53, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " operand_1 = 32'b0000_0011_1010_0000_00;\n operand_2 = 32'b0000_0100_0001_0000_00;\n operation = `FPU_ADD;\n\n"} |
| {"file": "LUMOS/Immediate_Generator.v", "target_type": "case_statement", "cursor_line": 22, "target_nlines": 5, "node_depth": 14, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " case (instruction_type)\n `I_TYPE : immediate = { {21{instruction[31]}}, instruction[30 : 20] };\n `S_TYPE : immediate = { {21{instruction[31]}}, instruction[30 : 25], instruction[11 : 7] };\n `B_TYPE : immediate = { {20{instruction[31]}}, instruction[7], instruction[30 : 25], instruction[11 : 8], 1'b0 };\n `U_TYPE : immediate = { instruction[31 : 12], {12{1'b0}} };\n"} |
| {"file": "LUMOS/LUMOS.v", "target_type": "case_statement", "cursor_line": 354, "target_nlines": 5, "node_depth": 23, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement", "case_item", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " begin\n aluOperation <= `ALU_SUB;\n end\n\n `BLT : \n"} |
| {"file": "LUMOS/LUMOS_Testbench.v", "target_type": "module_declaration", "cursor_line": 191, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " // Memory //\n ////////////\n\n reg [31 : 0] Memory [0 : 4 * 1024 - 1];\n initial $readmemh(`FIRMWARE, Memory);\n"} |
| {"file": "LUMOS/Register_File.v", "target_type": "module_declaration", "cursor_line": 28, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input wire [WIDTH - 1 : 0] write_data,\n\n output reg [WIDTH - 1 : 0] read_data_1,\n"} |
| {"file": "LUMOS/Synthesis/LUMOS.v", "target_type": "case_statement", "cursor_line": 1184, "target_nlines": 5, "node_depth": 14, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " `FPU_ADD : begin result = operand_1 + operand_2; ready = 1; end\n `FPU_SUB : begin result = operand_1 - operand_2; ready = 1; end\n `FPU_MUL : begin result = product[WIDTH + FBITS - 1 : FBITS]; ready = product_ready; end\n `FPU_SQRT : begin result = root; ready = root_ready; end\n default : begin result = 'bz; ready = 0; end\n"} |
| {"file": "LUMOS/Synthesis/LUMOS.vh", "target_type": "module_declaration", "cursor_line": 158, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " TBUFX2 \\read_data_2_tri[2] ( .A(1'b1), .EN(1'b0), .Y(read_data_2[2]) );\n TBUFX2 \\read_data_2_tri[1] ( .A(1'b1), .EN(1'b0), .Y(read_data_2[1]) );\n"} |
| {"file": "axi_vip_demo/src/axi_ram/axi_ram.v", "target_type": "case_statement", "cursor_line": 239, "target_nlines": 1, "node_depth": 14, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " s_axi_bvalid_next = 1'b1;\n"} |
| {"file": "axi_vip_demo/src/axi_vip_master/axi_vip_master.sv", "target_type": "module_declaration", "cursor_line": 60, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " m_axi_awlen,\n m_axi_awsize,\n m_axi_awburst,\n m_axi_awlock,\n m_axi_awcache,\n"} |
| {"file": "axi_vip_demo/src/axi_vip_master/axi_vip_master_pkg.sv", "target_type": "data_type", "cursor_line": 53, "target_nlines": 1, "node_depth": 11, "node_path": ["source_file", "package_declaration", "package_or_generate_item_declaration", "data_declaration", "type_declaration", "data_type", "class_type", "parameter_value_assignment", "list_of_parameter_assignments", "ordered_parameter_assignment", "_ordered_parameter_assignment", "data_type"], "target": " axi_vip_master_VIP_HAS_WSTRB,\n"} |
| {"file": "axi_vip_demo/src/axi_vip_master/axi_vip_v1_1_vl_rfs.sv", "target_type": "primary", "cursor_line": 270, "target_nlines": 1, "node_depth": 12, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "continuous_assign", "list_of_variable_assignments", "variable_assignment", "expression", "conditional_expression", "expression", "primary", "multiple_concatenation", "expression", "primary"], "target": " assign IF.WSTRB = slave_mode? s_axi_wstrb : {(C_AXI_WDATA_WIDTH/8){1'bz}};\n"} |
| {"file": "axi_vip_demo/src/tb/tb.sv", "target_type": "module_declaration", "cursor_line": 81, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "axi_strb_t axi_wstrb;\nlogic axi_wlast;\n"} |
| {"file": "axi_vip_demo/src/xilinx_vip/axi_vip_axi4pc.sv", "target_type": "expression", "cursor_line": 808, "target_nlines": 1, "node_depth": 14, "node_path": ["source_file", "interface_declaration", "interface_or_generate_item", "package_or_generate_item_declaration", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "jump_statement", "expression", "primary", "mintypmax_expression", "expression"], "target": " return(max_b_wait_cycles);\n"} |
| {"file": "axi_vip_demo/src/xilinx_vip/axi_vip_if.sv", "target_type": "primary", "cursor_line": 209, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "ERROR", "interface_or_generate_item", "package_or_generate_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "expression", "primary"], "target": " logic intf_is_master = 0;\n"} |
| {"file": "axi_vip_demo/src/xilinx_vip/axi_vip_pkg.sv", "target_type": "simple_identifier", "cursor_line": 3843, "target_nlines": 1, "node_depth": 1, "node_path": ["ERROR", "simple_identifier"], "target": " this.report_errors_number = updated;\n"} |
| {"file": "axi_vip_demo/src/xilinx_vip/xil_common_vip_macros.svh", "target_type": "simple_identifier", "cursor_line": 50, "target_nlines": 1, "node_depth": 4, "node_path": ["source_file", "text_macro_definition", "text_macro_name", "text_macro_identifier", "simple_identifier"], "target": "`define xil_info(TAG, MSG, LEVEL) \\\n"} |
| {"file": "axi_vip_demo/src/xilinx_vip/xil_common_vip_pkg.sv", "target_type": "simple_identifier", "cursor_line": 235, "target_nlines": 1, "node_depth": 9, "node_path": ["ERROR", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "class_constructor_declaration", "list_of_arguments_parent", "expression", "primary", "simple_identifier"], "target": " super.new(name);\n"} |
| {"file": "cdc/sim/data_bus_synchro_unit_test.sv", "target_type": "module_declaration", "cursor_line": 98, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " `UNIT_TESTS_END\n\nendmodule\n"} |
| {"file": "cdc/sim/debouncer_unit_test.sv", "target_type": "module_declaration", "cursor_line": 21, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " aclk,\n arstn,\n button,\n button_debounced\n"} |
| {"file": "cdc/sim/ffd_synchro_unit_test.sv", "target_type": "module_declaration", "cursor_line": 11, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " `SVUT_SETUP\n\n"} |
| {"file": "cdc/sim/hsk_pulse_synchro_unit_test.sv", "target_type": "module_declaration", "cursor_line": 70, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " - `FAIL_IF_NOT();\n - `FAIL_IF_EQUAL();\n - `FAIL_IF_NOT_EQUAL();\n */\n"} |
| {"file": "cdc/sim/pulse_synchro_unit_test.sv", "target_type": "module_declaration", "cursor_line": 52, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " arstn_i = 1'b1;\n arstn_o = 1'b1;\n end\n endtask\n\n"} |
| {"file": "cdc/src/data_bus_synchro.v", "target_type": "module_declaration", "cursor_line": 35, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " output reg [BUS_WIDTH-1:0] tdata_o\n );\n\n"} |
| {"file": "cdc/src/debouncer.v", "target_type": "module_declaration", "cursor_line": 34, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n\n reg [1:0] button_2ffd;\n"} |
| {"file": "cdc/src/ffd_synchro.v", "target_type": "module_declaration", "cursor_line": 37, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " synchro <= {synchro[0], tvalid_i};\n end\n"} |
| {"file": "cdc/src/hsk_pulse_synchro.v", "target_type": "module_declaration", "cursor_line": 37, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n reg pulse_mux;\n"} |
| {"file": "cdc/src/pulse_synchro.v", "target_type": "module_declaration", "cursor_line": 32, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input wire arstn_o,\n"} |
| {"file": "common_verification/src/clk_rst_gen.sv", "target_type": "module_declaration", "cursor_line": 12, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "module clk_rst_gen #(\n parameter realtime ClkPeriod = 0ps, // minimum: 2ps\n parameter int unsigned RstClkCycles = 0\n) (\n output logic clk_o,\n"} |
| {"file": "common_verification/src/rand_id_queue.sv", "target_type": "primary_literal", "cursor_line": 42, "target_nlines": 1, "node_depth": 19, "node_path": ["source_file", "package_declaration", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "jump_statement", "expression", "primary", "mintypmax_expression", "expression", "expression", "primary", "primary_literal"], "target": " return (size == 0);\n"} |
| {"file": "common_verification/src/rand_stream_mst.sv", "target_type": "module_declaration", "cursor_line": 71, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " if (rand_wait_cycles == 0) begin\n"} |
| {"file": "common_verification/src/rand_stream_slv.sv", "target_type": "module_declaration", "cursor_line": 60, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " assert (AcqDelay > 0ps)\n else $fatal(\"The acquisition delay must be greater than 0!\");\n assert (AcqDelay > ApplDelay)\n"} |
| {"file": "common_verification/src/rand_synch_driver.sv", "target_type": "module_declaration", "cursor_line": 21, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input logic clk_i,\n input logic rst_ni,\n\n output data_t data_o\n"} |
| {"file": "common_verification/src/rand_synch_holdable_driver.sv", "target_type": "module_declaration", "cursor_line": 32, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " @(posedge clk_i);\n forever begin\n rand_success = std::randomize(rand_delay) with {\n rand_delay >= MinWaitCycles;\n rand_delay <= MaxWaitCycles;\n"} |
| {"file": "common_verification/src/rand_verif_pkg.sv", "target_type": "expression", "cursor_line": 22, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "package_declaration", "package_or_generate_item_declaration", "task_declaration", "task_body_declaration", "statement_or_null", "statement", "statement_item", "simple_immediate_assert_statement", "expression"], "target": " assert (rand_success) else $error(\"Failed to randomize wait cycles!\");\n"} |
| {"file": "common_verification/src/signal_highlighter.sv", "target_type": "module_declaration", "cursor_line": 19, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input logic valid_i,\n input T data_i\n);\n\n T in_wave;\n"} |
| {"file": "common_verification/src/sim_timeout.sv", "target_type": "module_declaration", "cursor_line": 19, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " end\n\n `ifndef VERILATOR\n"} |
| {"file": "common_verification/src/stream_watchdog.sv", "target_type": "module_declaration", "cursor_line": 36, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " end\n @(posedge clk_i);\n"} |
| {"file": "common_verification/test/tb_clk_rst_gen.sv", "target_type": "module_declaration", "cursor_line": 17, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n // DUT\n clk_rst_gen #(\n"} |
| {"file": "fplib/examples/interp_fplib.sv", "target_type": "module_declaration", "cursor_line": 53, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " $display(\"y (float) = %f\", y.fval);\n $finish();\n end\n\n"} |
| {"file": "fplib/examples/interp_no_fplib.sv", "target_type": "module_declaration", "cursor_line": 79, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " .IW_Y(IW_Y), .QW_Y(QW_Y)\n ) u_interp (.m(m), .x(x), .b(b), .y(y));\n\n initial begin\n"} |
| {"file": "fplib/rtl/clip.sv", "target_type": "module_declaration", "cursor_line": 37, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " // clipped value\n assign out = positiveclip ? maxval :\n negativeclip ? minval : in[outw-1:0];\n\n"} |
| {"file": "fplib/rtl/fp_convert.sv", "target_type": "module_declaration", "cursor_line": 22, "target_nlines": 5, "node_depth": 1, "node_path": ["ERROR", "module_declaration"], "target": ");\n localparam int out_wl = `fp_wl(fp);\n localparam longint ival = longint'(float * (2.0 ** `fp_qw(fp))); // rounds to nearest integer\n localparam longint top = 2 ** (out_wl - 1) - 1;\n localparam longint bot = -(2 ** (out_wl - 1));\n"} |
| {"file": "fplib/rtl/fp_if.sv", "target_type": "primary", "cursor_line": 88, "target_nlines": 1, "node_depth": 6, "node_path": ["source_file", "package_or_generate_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "expression", "primary"], "target": " fval[i] = `fp_to_float(val[i], qw);\n"} |
| {"file": "fplib/rtl/fp_macros.svh", "target_type": "simple_identifier", "cursor_line": 31, "target_nlines": 1, "node_depth": 4, "node_path": ["source_file", "text_macro_definition", "text_macro_name", "text_macro_identifier", "simple_identifier"], "target": " `define sub_iw(fp1, fp2) `add_iw(fp1, fp2)\n"} |
| {"file": "fplib/rtl/fp_op.sv", "target_type": "module_declaration", "cursor_line": 34, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " sfp.in in1, in2, // input sfp signal\n sfp.out out, // output sfp signal (= in1 + in2)\n output clipping // clipping indicator (active-high)\n);\n"} |
| {"file": "fplib/rtl/fp_op_full.sv", "target_type": "module_declaration", "cursor_line": 77, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " if ((`fp_iw(out) != iw_aligned + 1) || (`fp_qw(out) != qw_aligned))\n $error({\"%m: Incorrect output word length for a full-width subtract!\",\n \"Make sure out.iw = max(in1.iw, in2.iw) + 1 and out.qw = max(in1.qw, in2.qw)!\"});\n\n // resize in1 and in2 to have the same word length with an aligned binary point\n"} |
| {"file": "fplib/rtl/fp_resize.sv", "target_type": "module_declaration", "cursor_line": 163, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " sfp.in in, // input sfp signal\n sfp.out out // output sfp signal\n);\n\n sfp_resize_ind #(.clip(clip)) u_resize_ind (.in(in), .out(out), .clipping());\n"} |
| {"file": "fplib/tests/test_fplib.sv", "target_type": "expression", "cursor_line": 77, "target_nlines": 1, "node_depth": 16, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "loop_generate_construct", "generate_block", "module_or_generate_item", "interface_instantiation", "parameter_value_assignment", "list_of_parameter_assignments", "ordered_parameter_assignment", "_ordered_parameter_assignment", "mintypmax_expression", "expression", "primary", "select1", "bit_select1", "expression"], "target": " sfp #(iw_r[i], qw_r[i]) s_from_real();\n"} |
| {"file": "fplib/tests/test_fplib_pkg.sv", "target_type": "simple_identifier", "cursor_line": 19, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "package_declaration", "package_or_generate_item_declaration", "local_parameter_declaration", "list_of_param_assignments", "param_assignment", "parameter_identifier", "simple_identifier"], "target": " localparam bit [63:0] ureals[n_reals] = '{64'h4041928790000000, 64'h4018400000000000, 64'h3f35464000000000, 64'h3fa8c80000000000, 64'h3e99b17c00000000, 64'h3f296e4a00000000, 64'h4016000000000000, 64'h3e5c5d25d8000000, 64'h3f98460000000000, 64'h400c000000000000, 64'h3fe0000000000000, 64'h4153b873fc000000, 64'h4091dc4000000000, 64'h3f61c94000000000, 64'h40fab5e000000000, 64'h3fdc000000000000, 64'h40ddc21800000000, 64'h3fc4800000000000, 64'h3ff1aa7000000000, 64'h3dea1a9100000000, 64'h408f522e00000000, 64'h3f9f64e006000000, 64'h3eb8fe3200000000, 64'h40112fa000000000, 64'h3f04070000000000, 64'h40f9563c00000000, 64'h4022380000000000, 64'h3f84040000000000, 64'h408f765800000000, 64'h404801ea00000000, 64'h3f70800000000000, 64'h3fb8838000000000, 64'h3ece780000000000, 64'h3fe4000000000000, 64'h4063700000000000, 64'h3fc8000000000000, 64'h3f34412a00000000, 64'h40f4828400000000, 64'h3e2d39d800000000, 64'h414b7765c0000000, 64'h4059407800000000, 64'h408c210000000000, 64'h40b67ab000000000, 64'h3e849a778a000000, 64'h40585e3000000000, 64'h400a0b7e00000000, 64'h3fdd9c0000000000, 64'h3fd8000000000000, 64'h3f42000000000000, 64'h3f82d24000000000, 64'h3ff8000000000000, 64'h3fe3510000000000, 64'h3ff9000000000000, 64'h403aa80000000000, 64'h3f80000000000000, 64'h3fe2200000000000, 64'h406879c800000000, 64'h3f0a669000000000, 64'h4111d15c10000000, 64'h40640e5e80000000, 64'h3f8ae00000000000, 64'h4004dcf7f0000000, 64'h4090bdc000000000, 64'h3f8ce00000000000, 64'h3f79000000000000, 64'h3fe0000000000000, 64'h3ff7800000000000, 64'h3eef9b5f50000000, 64'h4028000000000000, 64'h4111854d00000000, 64'h3fd8000000000000, 64'h408fa2bbe0000000, 64'h3ffa2a2800000000, 64'h3fba000000000000, 64'h3e68562f00000000, 64'h3f2e94cd00000000, 64'h3fd8000000000000, 64'h3f60000000000000, 64'h3f4e28f000000000, 64'h404ee00000000000, 64'h3fac000000000000, 64'h40453dba80000000, 64'h3ee87e7000000000, 64'h3f0bfbf000000000, 64'h407c3db000000000, 64'h404993b3d8000000, 64'h3f8a000000000000, 64'h4006f78000000000, 64'h3fd9c50000000000, 64'h40bda90000000000, 64'h3f71800000000000, 64'h408fad7400000000, 64'h3fcb200000000000, 64'h4010c00000000000, 64'h3e70dc6480000000, 64'h3ff0000000000000, 64'h3fc0000000000000, 64'h4021d00000000000, 64'h3fd8000000000000, 64'h4002c99408000000};\n"} |
| {"file": "plic/bench/verilog/ahb3lite_bfm.sv", "target_type": "case_statement", "cursor_line": 243, "target_nlines": 3, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "package_or_generate_item_declaration", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "case_statement"], "target": " HSIZE_B64 : get_bytes_per_beat = 8;\n HSIZE_B128 : get_bytes_per_beat = 16;\n HSIZE_B256 : get_bytes_per_beat = 32;\n"} |
| {"file": "plic/bench/verilog/test.sv", "target_type": "case_statement", "cursor_line": 419, "target_nlines": 1, "node_depth": 4, "node_path": ["ERROR", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " hburst = (HDATA_SIZE == 64) ? HBURST_INCR4 : HBURST_SINGLE;\n"} |
| {"file": "plic/bench/verilog/testbench_top.sv", "target_type": "module_declaration", "cursor_line": 42, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " parameter HADDR_SIZE = 16;\n parameter HDATA_SIZE = 32;\n\n\n /////////////////////////////////////////////////////////\n"} |
| {"file": "plic/rtl/verilog/ahb3lite/ahb3lite_plic_top.sv", "target_type": "case_statement", "cursor_line": 180, "target_nlines": 5, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "package_or_generate_item_declaration", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "case_statement"], "target": " 512: address_offset = 7'b011_1111;\n 256: address_offset = 7'b001_1111;\n 128: address_offset = 7'b000_1111;\n 64: address_offset = 7'b000_0111;\n 32: address_offset = 7'b000_0011;\n"} |
| {"file": "plic/rtl/verilog/apb4/apb4_plic_top.sv", "target_type": "module_declaration", "cursor_line": 198, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " .ip ( ip ), //Interrupt Pending\n\n .ie ( ie ), //Interrupt Enable\n"} |
| {"file": "plic/rtl/verilog/core/plic_cell.sv", "target_type": "module_declaration", "cursor_line": 95, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " always @(posedge clk_i,negedge rst_ni)\n if (!rst_ni ) priority_o <= 0;\n else if ( ip_i && ie_i) priority_o <= priority_i;\n"} |
| {"file": "plic/rtl/verilog/core/plic_core.sv", "target_type": "packed_dimension", "cursor_line": 85, "target_nlines": 1, "node_depth": 8, "node_path": ["ERROR", "module_ansi_header", "list_of_port_declarations", "ansi_port_declaration", "net_port_header1", "net_port_type1", "data_type_or_implicit1", "implicit_data_type1", "packed_dimension"], "target": " output [SOURCES -1:0] ip, //Interrupt Pending for each source\n"} |
| {"file": "plic/rtl/verilog/core/plic_dynamic_registers.sv", "target_type": "case_statement", "cursor_line": 580, "target_nlines": 4, "node_depth": 18, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " case (register_function(write_register))\n ID : ; //A write to ID generates a strobe signal\n default: registers[write_register] <= gen_wval( registers[write_register], wdata, be);\n endcase\n"} |
| {"file": "plic/rtl/verilog/core/plic_gateway.sv", "target_type": "case_statement", "cursor_line": 135, "target_nlines": 4, "node_depth": 6, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "case_statement"], "target": " else\n nxt_pending_cnt = pending_cnt;\n 2'b11: nxt_pending_cnt = pending_cnt; //do nothing\n endcase\n"} |
| {"file": "plic/rtl/verilog/core/plic_priority_index.sv", "target_type": "module_declaration", "cursor_line": 70, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " parameter PRIORITIES = 7,\n parameter HI = 16,\n parameter LO = 0,\n\n //These should be localparams, but that's not supported by all tools yet\n"} |
| {"file": "plic/rtl/verilog/core/plic_target.sv", "target_type": "primary_literal", "cursor_line": 97, "target_nlines": 1, "node_depth": 10, "node_path": ["source_file", "package_or_generate_item_declaration", "data_declaration", "data_type_or_implicit1", "data_type", "packed_dimension", "constant_range", "constant_expression", "constant_expression", "constant_primary", "primary_literal"], "target": " logic [SOURCES_BITS -1:0] id;\n"} |
| {"file": "AXI4_Interconnect/RTL/AXI_Arbiter_R.sv", "target_type": "case_statement", "cursor_line": 111, "target_nlines": 4, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " else\n next_state = AXI_MASTER_0;\n end\n AXI_MASTER_2: begin //2号主机占用总线状态，响应请求优先级为：2>3>0>1\n"} |
| {"file": "AXI4_Interconnect/RTL/AXI_Arbiter_W.sv", "target_type": "case_statement", "cursor_line": 132, "target_nlines": 1, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " next_state = AXI_MASTER_2;\n"} |
| {"file": "AXI4_Interconnect/RTL/AXI_Interconnect.sv", "target_type": "simple_identifier", "cursor_line": 392, "target_nlines": 1, "node_depth": 15, "node_path": ["source_file", "module_declaration", "module_ansi_header", "list_of_port_declarations", "ansi_port_declaration", "net_port_header1", "net_port_type1", "data_type_or_implicit1", "implicit_data_type1", "packed_dimension", "constant_range", "constant_expression", "constant_expression", "constant_primary", "parameter_identifier", "simple_identifier"], "target": "\tinput\t [USER_WIDTH-1:0]\ts6_RUSER,\n"} |
| {"file": "AXI4_Interconnect/RTL/AXI_Interface.sv", "target_type": "simple_identifier", "cursor_line": 153, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "interface_declaration", "modport_declaration", "modport_item", "modport_ports_declaration", "modport_simple_ports_declaration", "modport_simple_port", "port_identifier", "simple_identifier"], "target": "\t\tinput\t \t\tAWBURST,\n"} |
| {"file": "AXI4_Interconnect/RTL/AXI_Master_Mux_R.sv", "target_type": "case_statement", "cursor_line": 255, "target_nlines": 1, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " default: begin\n"} |
| {"file": "AXI4_Interconnect/RTL/AXI_Master_Mux_W.sv", "target_type": "case_statement", "cursor_line": 201, "target_nlines": 4, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " s_AWREGION = m0_AWREGION;\n s_AWUSER = m0_AWUSER;\n s_AWVALID = m0_AWVALID;\n s_WID = m0_WID;\n"} |
| {"file": "AXI4_Interconnect/RTL/AXI_Slave_Mux_R.sv", "target_type": "case_statement", "cursor_line": 450, "target_nlines": 2, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " s0_RREADY = '0;\n s1_RREADY = '0;\n"} |
| {"file": "AXI4_Interconnect/RTL/AXI_Slave_Mux_W.sv", "target_type": "case_statement", "cursor_line": 234, "target_nlines": 1, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " m_AWREADY = s5_AWREADY;\n"} |
| {"file": "AXI4_Interconnect/Simulation/AXI_Interconnect_TB/AXI_Interconnect_TB.sv", "target_type": "simple_identifier", "cursor_line": 184, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "module_instantiation", "hierarchical_instance", "list_of_port_connections", "named_port_connection", "expression", "primary", "simple_identifier"], "target": " .ARADDR (m1_ARADDR),\n"} |
| {"file": "AXI4_Interconnect/Simulation/AXI_M_S_TB/AXI_M_S_TB.sv", "target_type": "module_declaration", "cursor_line": 73, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\t//写数据通道\t\n\tlogic\t[31:0]\t\tWID;\n\tlogic\t[1023:0]\tWDATA;\n\tlogic\t[127:0]\t\tWSTRB;\n\tlogic\t \t\t\tWLAST;\n"} |
| {"file": "AXI4_Interconnect/Simulation/AXI_Master.sv", "target_type": "module_declaration", "cursor_line": 74, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " else\n AWVALID <= #TCO AWVALID;\n end\n\n always_ff@(posedge ACLK, negedge ARESETn)begin\n"} |
| {"file": "AXI4_Interconnect/Simulation/AXI_Slave.sv", "target_type": "module_declaration", "cursor_line": 105, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " logic [7:0] cnt_addr_w;\n\n"} |
| {"file": "LM-RISCV-DV/integration_files/SweRV_EH1/google_riscv_dv/src/riscv_asm_program_gen.sv", "target_type": "simple_identifier", "cursor_line": 1081, "target_nlines": 1, "node_depth": 1, "node_path": ["ERROR", "simple_identifier"], "target": " instr = {instr, $sformatf(\"csrr x%0d, 0x%0x # %0s\", cfg.gpr[0], status, status.name())};\n"} |
| {"file": "LM-RISCV-DV/integration_files/SweRV_EH1/google_riscv_dv/src/riscv_instr_gen_config.sv", "target_type": "expression", "cursor_line": 442, "target_nlines": 1, "node_depth": 9, "node_path": ["ERROR", "class_item", "constraint_declaration", "constraint_block", "constraint_block_item", "constraint_expression", "constraint_set", "constraint_expression", "expression_or_dist", "expression"], "target": " virtual_addr_translation_on == 1'b1;\n"} |
| {"file": "LM-RISCV-DV/integration_files/SweRV_EH1/riscv_dv_extension/riscv_core_setting.sv", "target_type": "primary", "cursor_line": 28, "target_nlines": 1, "node_depth": 6, "node_path": ["source_file", "package_or_generate_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "expression", "primary"], "target": "privileged_mode_t supported_privileged_mode[] = {MACHINE_MODE};\n"} |
| {"file": "LM-RISCV-DV/integration_files/SweRV_EH1/snapshots/default/common_defines.vh", "target_type": "simple_identifier", "cursor_line": 170, "target_nlines": 1, "node_depth": 4, "node_path": ["source_file", "text_macro_definition", "text_macro_name", "text_macro_identifier", "simple_identifier"], "target": "`define RV_DATA_ACCESS_ENABLE3 1'h0\n"} |
| {"file": "LM-RISCV-DV/integration_files/SweRV_EH1/snapshots/default/common_defines_verilator.vh", "target_type": "simple_identifier", "cursor_line": 73, "target_nlines": 1, "node_depth": 4, "node_path": ["source_file", "text_macro_definition", "text_macro_name", "text_macro_identifier", "simple_identifier"], "target": "`define RV_UNUSED_REGION5 'h50000000\n"} |
| {"file": "LM-RISCV-DV/integration_files/SweRV_EH1/snapshots/default/pd_defines.vh", "target_type": "include_compiler_directive", "cursor_line": 7, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "include_compiler_directive"], "target": "`include \"common_defines.vh\"\n"} |
| {"file": "LM-RISCV-DV/integration_files/SweRV_EH1/snapshots/default/pic_ctrl_verilator_unroll.sv", "target_type": "expression", "cursor_line": 9, "target_nlines": 1, "node_depth": 11, "node_path": ["source_file", "package_or_generate_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "ERROR", "net_decl_assignment", "expression", "primary", "select1", "bit_select1", "expression"], "target": " assign level_intpend_w_prior_en_1[m+1] = '0 ;\n"} |
| {"file": "LM-RISCV-DV/integration_files/SweRV_EH1/testbench/ahb_sif.sv", "target_type": "module_declaration", "cursor_line": 121, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " mem[{addr[31:3],3'd2}],\n mem[{addr[31:3],3'd1}],\n mem[{addr[31:3],3'd0}]};\n strb_lat <= strb;\n"} |
| {"file": "LM-RISCV-DV/integration_files/SweRV_EH1/testbench/pkg.sv", "target_type": "simple_identifier", "cursor_line": 389, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "package_declaration", "package_or_generate_item_declaration", "data_declaration", "type_declaration", "data_type", "enum_name_declaration", "enum_identifier", "simple_identifier"], "target": " CSR_MCYCLEH = 12'hB80,\n"} |
| {"file": "LM-RISCV-DV/integration_files/SweRV_EH1/testbench/tb_top.sv", "target_type": "primary", "cursor_line": 674, "target_nlines": 1, "node_depth": 8, "node_path": ["ERROR", "module_declaration", "module_or_generate_item", "program_instantiation", "hierarchical_instance", "list_of_port_connections", "named_port_connection", "expression", "primary"], "target": " .debug_brkpt_status (debug_brkpt_status),\n"} |
| {"file": "LM-RISCV-DV/integration_files/SweRV_EH1/testbench/tracer.sv", "target_type": "case_statement", "cursor_line": 721, "target_nlines": 5, "node_depth": 10, "node_path": ["source_file", "ERROR", "module_or_generate_item", "package_or_generate_item_declaration", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "case_statement"], "target": " 2'b00: mnemonic = \"sb\";\n 2'b01: mnemonic = \"sh\";\n 2'b10: mnemonic = \"sw\";\n default: begin\n decode_mnemonic(\"INVALID\");\n"} |
| {"file": "LM-RISCV-DV/integration_files/SweRV_EH1/testbench/tracer_pkg.sv", "target_type": "packed_dimension", "cursor_line": 119, "target_nlines": 1, "node_depth": 6, "node_path": ["source_file", "package_declaration", "package_or_generate_item_declaration", "parameter_declaration", "data_type_or_implicit1", "data_type", "packed_dimension"], "target": "parameter logic [31:0] INSN_FENCE = { 17'b?, 3'b000, 5'b?, {OPCODE_MISC_MEM} };\n"} |
| {"file": "axi_dma/csr_out/csr_dma.sv", "target_type": "expression", "cursor_line": 68, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "module_instantiation", "hierarchical_instance", "list_of_port_connections", "named_port_connection", "expression"], "target": " .register_if (register_if)\n"} |
| {"file": "axi_dma/csr_out/csr_dma.v", "target_type": "expression", "cursor_line": 565, "target_nlines": 1, "node_depth": 18, "node_path": ["source_file", "module_declaration", "generate_region", "interface_or_generate_item", "if_generate_construct", "generate_block", "loop_generate_construct", "generate_block", "interface_or_generate_item", "interface_instantiation", "hierarchical_instance", "list_of_port_connections", "named_port_connection", "expression", "primary", "select1", "indexed_range", "expression", "expression"], "target": " .o_register_read_data (w_register_read_data[64*(4+i)+:64]),\n"} |
| {"file": "axi_dma/csr_out/csr_dma_ral_pkg.sv", "target_type": "expression", "cursor_line": 50, "target_nlines": 1, "node_depth": 4, "node_path": ["ERROR", "class_item", "text_macro_usage", "list_of_actual_arguments", "expression"], "target": " `rggen_ral_create_field(error_src, 1, 1, \"RO\", 1, 1'h0, 1, -1, \"\")\n"} |
| {"file": "axi_dma/rtl/dma_axi_if.sv", "target_type": "simple_identifier", "cursor_line": 284, "target_nlines": 1, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "ERROR", "clockvar_expression", "clockvar", "simple_identifier"], "target": " dma_mosi_o.awprot = AXI_NONSECURE;\n"} |
| {"file": "axi_dma/rtl/dma_axi_wrapper.sv", "target_type": "module_declaration", "cursor_line": 50, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " dma_desc[i].src_addr = dma_desc_src_vec[i*`DMA_ADDR_WIDTH +: `DMA_ADDR_WIDTH];\n dma_desc[i].dst_addr = dma_desc_dst_vec[i*`DMA_ADDR_WIDTH +: `DMA_ADDR_WIDTH];\n dma_desc[i].num_bytes = dma_desc_byt_vec[i*`DMA_ADDR_WIDTH +: `DMA_ADDR_WIDTH];\n dma_desc[i].wr_mode = dma_mode_t'(dma_desc_wr_mod[i]);\n dma_desc[i].rd_mode = dma_mode_t'(dma_desc_rd_mod[i]);\n"} |
| {"file": "axi_dma/rtl/dma_fifo.sv", "target_type": "module_declaration", "cursor_line": 21, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " output logic [WIDTH-1:0] data_o,\n"} |
| {"file": "axi_dma/rtl/dma_fsm.sv", "target_type": "module_declaration", "cursor_line": 113, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " always_comb begin : wr_streamer\n dma_stream_wr_o = s_dma_str_in_t'('0);\n"} |
| {"file": "axi_dma/rtl/dma_func_wrapper.sv", "target_type": "module_declaration", "cursor_line": 67, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " .dma_abort_i (dma_ctrl_i.abort_req),\n .dma_maxb_i (dma_ctrl_i.max_burst),\n"} |
| {"file": "axi_dma/rtl/dma_streamer.sv", "target_type": "case_statement", "cursor_line": 64, "target_nlines": 5, "node_depth": 18, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "package_or_generate_item_declaration", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " 'd2: strobe = 'b0011;\n 'd3: strobe = 'b0111;\n 'd4: strobe = 'b1111;\n default: strobe = '0;\n endcase\n"} |
| {"file": "axi_dma/rtl/inc/dma_pkg.svh", "target_type": "simple_identifier", "cursor_line": 41, "target_nlines": 1, "node_depth": 3, "node_path": ["source_file", "id_directive", "text_macro_identifier", "simple_identifier"], "target": " `ifndef DMA_MAX_BEAT_BURST\n"} |
| {"file": "axi_dma/rtl/inc/dma_utils_pkg.sv", "target_type": "simple_identifier", "cursor_line": 1, "target_nlines": 1, "node_depth": 3, "node_path": ["source_file", "id_directive", "text_macro_identifier", "simple_identifier"], "target": "`ifndef _DMA_UTILS_PKG_\n"} |
| {"file": "axi_dma/rtl/tb_axi_dma.sv", "target_type": "module_declaration", "cursor_line": 64, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " output logic [3:0] dma_m_awregion,\n output axi_user_req_t dma_m_awuser,\n"} |
| {"file": "tiny-gpu/src/alu.sv", "target_type": "module_declaration", "cursor_line": 22, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": ");\n localparam ADD = 2'b00,\n SUB = 2'b01,\n MUL = 2'b10,\n"} |
| {"file": "tiny-gpu/src/controller.sv", "target_type": "module_declaration", "cursor_line": 74, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " channel_serving_consumer[j] = 1;\n current_consumer[i] <= j;\n"} |
| {"file": "tiny-gpu/src/core.sv", "target_type": "module_declaration", "cursor_line": 171, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " registers #(\n"} |
| {"file": "tiny-gpu/src/dcr.sv", "target_type": "module_declaration", "cursor_line": 12, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input wire [7:0] device_control_data,\n"} |
| {"file": "tiny-gpu/src/decoder.sv", "target_type": "case_statement", "cursor_line": 124, "target_nlines": 3, "node_depth": 30, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " decoded_reg_write_enable <= 1;\n decoded_reg_input_mux <= 2'b10;\n end\n"} |
| {"file": "tiny-gpu/src/dispatch.sv", "target_type": "module_declaration", "cursor_line": 40, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " done <= 0;\n blocks_dispatched = 0;\n blocks_done = 0;\n"} |
| {"file": "tiny-gpu/src/fetcher.sv", "target_type": "case_statement", "cursor_line": 56, "target_nlines": 4, "node_depth": 22, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " FETCHED: begin\n // Reset when core_state = DECODE\n if (core_state == 3'b010) begin \n fetcher_state <= IDLE;\n"} |
| {"file": "tiny-gpu/src/gpu.sv", "target_type": "module_declaration", "cursor_line": 172, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " always @(posedge clk) begin \n lsu_read_valid[lsu_index] <= core_lsu_read_valid[j];\n lsu_read_address[lsu_index] <= core_lsu_read_address[j];\n\n"} |
| {"file": "tiny-gpu/src/lsu.sv", "target_type": "case_statement", "cursor_line": 67, "target_nlines": 1, "node_depth": 34, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " lsu_out <= mem_read_data;\n"} |
| {"file": "tiny-gpu/src/pc.sv", "target_type": "module_declaration", "cursor_line": 11, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " parameter DATA_MEM_DATA_BITS = 8,\n parameter PROGRAM_MEM_ADDR_BITS = 8\n) (\n input wire clk,\n"} |
| {"file": "tiny-gpu/src/registers.sv", "target_type": "case_statement", "cursor_line": 90, "target_nlines": 2, "node_depth": 42, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " // LDR\n registers[decoded_rd_address] <= lsu_out;\n"} |
| {"file": "tiny-gpu/src/scheduler.sv", "target_type": "module_declaration", "cursor_line": 72, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " end\n REQUEST: begin \n"} |
| {"file": "uvm_gen/templates/uvm_agent.sv", "target_type": "data_type", "cursor_line": 87, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "package_or_generate_item_declaration", "function_declaration", "function_body_declaration", "tf_port_list", "tf_port_item1", "data_type_or_implicit1", "data_type"], "target": "function void {:NAME:}Agent::build_phase (uvm_phase phase);\r\n"} |
| {"file": "uvm_gen/templates/uvm_config.sv", "target_type": "primary", "cursor_line": 22, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_property", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "expression", "primary"], "target": " bit has_functional_coverage = 0;\n"} |
| {"file": "uvm_gen/templates/uvm_driver.sv", "target_type": "expression", "cursor_line": 11, "target_nlines": 1, "node_depth": 6, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "text_macro_usage", "list_of_actual_arguments", "expression"], "target": " `uvm_object_utils_begin({:NAME:}DriverConfig)\r\n"} |
| {"file": "uvm_gen/templates/uvm_env.sv", "target_type": "expression", "cursor_line": 115, "target_nlines": 1, "node_depth": 3, "node_path": ["source_file", "text_macro_usage", "list_of_actual_arguments", "expression"], "target": " `uvm_info(tID, $sformatf(\"build_phase begin ...\"), UVM_HIGH)\r\n"} |
| {"file": "uvm_gen/templates/uvm_interface.sv", "target_type": "simple_identifier", "cursor_line": 14, "target_nlines": 1, "node_depth": 15, "node_path": ["source_file", "interface_declaration", "interface_item", "interface_or_generate_item", "package_or_generate_item_declaration", "task_declaration", "task_body_declaration", "statement_or_null", "statement", "statement_item", "procedural_timing_control_statement", "event_control", "event_expression", "expression", "primary", "simple_identifier"], "target": " @(posedge clk);\r\n"} |
| {"file": "uvm_gen/templates/uvm_monitor.sv", "target_type": "primary", "cursor_line": 69, "target_nlines": 1, "node_depth": 16, "node_path": ["source_file", "package_or_generate_item_declaration", "class_constructor_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "blocking_assignment", "operator_assignment", "expression", "primary", "function_subroutine_call", "subroutine_call", "tf_call", "list_of_arguments_parent", "expression", "primary"], "target": " this.ap = new(\"ap\", this);\r\n"} |
| {"file": "uvm_gen/templates/uvm_pkg.sv", "target_type": "simple_identifier", "cursor_line": 24, "target_nlines": 1, "node_depth": 5, "node_path": ["source_file", "package_or_generate_item_declaration", "net_declaration", "list_of_net_decl_assignments", "net_decl_assignment", "simple_identifier"], "target": "endpackage: {:NAME:}Pkg\r\n"} |
| {"file": "uvm_gen/templates/uvm_scoreboard.sv", "target_type": "simple_identifier", "cursor_line": 22, "target_nlines": 1, "node_depth": 4, "node_path": ["source_file", "ERROR", "class_type", "ERROR", "simple_identifier"], "target": "function {:NAME:}Scoreboard::new (string name=\"{:NAME:}Scoreboard\", uvm_component parent=null);\n"} |
| {"file": "uvm_gen/templates/uvm_sequence.sv", "target_type": "expression", "cursor_line": 12, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "class_constructor_prototype", "tf_port_list", "tf_port_item1", "expression"], "target": " extern function new (string name=\"{:NAME:}Sequence\");\n"} |
| {"file": "uvm_gen/templates/uvm_test.sv", "target_type": "primary_literal", "cursor_line": 56, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "package_or_generate_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "expression", "primary", "primary_literal"], "target": " mEnvCfg = {:ENV_NAME:}EnvConfig::type_id::create(\"mEnvCfg\");\n"} |
| {"file": "uvm_gen/templates/uvm_test_top.sv", "target_type": "module_declaration", "cursor_line": 3, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "module {:NAME:}_test_top;\n\n import uvm_pkg::*;\n import {:NAME:}_test_pkg::*;\n"} |
| {"file": "uvm_gen/templates/uvm_transaction.sv", "target_type": "data_type", "cursor_line": 33, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "function_prototype", "tf_port_list", "tf_port_item1", "data_type_or_implicit1", "data_type"], "target": " extern function void do_copy (uvm_object rhs);\n"} |
| {"file": "Toolbox/ip_repo/axis_gpio_1_0/src/axis_gpio.sv", "target_type": "module_declaration", "cursor_line": 31, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " ( \n input\t\t clk,\n"} |
| {"file": "Toolbox/ip_repo/axis_gpio_1_0/src/axis_gpio_v1_0.v", "target_type": "module_declaration", "cursor_line": 69, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " axis_gpio \n #(\n .BYTE_START(BYTE_START),\n"} |
| {"file": "Toolbox/ip_repo/axis_gpio_1_0/src/debounce.sv", "target_type": "expression", "cursor_line": 75, "target_nlines": 1, "node_depth": 6, "node_path": ["ERROR", "expression", "expression", "ERROR", "primary", "mintypmax_expression", "expression"], "target": " if ((gpio_in_q[i] == 0) && (gpio_out_i[i] == 1)) begin\n"} |
| {"file": "Toolbox/ip_repo/axis_gpio_1_0/src/sw_axis.sv", "target_type": "case_statement", "cursor_line": 192, "target_nlines": 3, "node_depth": 14, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " // No prefix, skip to data\n next_state = DATA;\n \n"} |
| {"file": "Toolbox/ip_repo/axis_snoop_debug_1_0/src/axis_snoop_debug.sv", "target_type": "case_statement", "cursor_line": 179, "target_nlines": 4, "node_depth": 14, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " next_state = current_state;\n\n end\n end\n"} |
| {"file": "Toolbox/ip_repo/axis_snoop_debug_1_0/src/axis_snoop_fifo.sv", "target_type": "module_declaration", "cursor_line": 13, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input wire\t\t\t S_AXIS_TREADY,\n"} |
| {"file": "Toolbox/ip_repo/axis_uart_1_0/src/uart.sv", "target_type": "module_declaration", "cursor_line": 37, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " // input slave axis interface\n input [WORD_LENGTH-1:0] s_axis_data,\n input\t\t s_axis_valid,\n input\t\t s_axis_last,\n output\t\t s_axis_ready,\n"} |
| {"file": "Toolbox/ip_repo/axis_uart_1_0/src/uart_tx.sv", "target_type": "case_statement", "cursor_line": 305, "target_nlines": 3, "node_depth": 14, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "\t DATA: begin\n\t assert(uart_data_counter < WORD_LENGTH);\n\t assert(UART_TX == fv_data[uart_data_counter]);\n"} |
| {"file": "Toolbox/ip_repo/rmii_axis_1_0/src/crc_gen.sv", "target_type": "module_declaration", "cursor_line": 69, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " assign lfsr_c[9] = (data_in[1] ^ lfsr_q[1] ^ lfsr_q[11]);\n assign lfsr_c[10] = lfsr_q[12];\n assign lfsr_c[11] = lfsr_q[13];\n"} |
| {"file": "Toolbox/ip_repo/rmii_axis_1_0/src/eth_header_gen.sv", "target_type": "module_declaration", "cursor_line": 111, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " assign header.ipv4.time_to_live = {<<8{TIME_TO_LIVE}};\n assign header.ipv4.protocol = {<<8{PROTOCOL}};\n assign header.ipv4.header_checksum = {<<8{HEADER_CHECKSUM}};\n"} |
| {"file": "Toolbox/ip_repo/rmii_axis_1_0/src/packet_gen.sv", "target_type": "case_statement", "cursor_line": 391, "target_nlines": 5, "node_depth": 14, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " end\n DATA :\n begin\n tx_valid = 1;\n tx_data = data_buffer[MII_WIDTH-1:0];\n"} |
| {"file": "Toolbox/ip_repo/rmii_axis_1_0/src/packet_recv.sv", "target_type": "module_declaration", "cursor_line": 63, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\t end\n\tend\n end // always @ (posedge clk)\n \n typedef struct packed {\n"} |
| {"file": "Toolbox/ip_repo/rmii_axis_1_0/src/rmii_axis_v1_0.v", "target_type": "module_declaration", "cursor_line": 30, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " output [1:0]\tETH_TXD,\n \n // Ports of Axi Master Bus Interface M00_AXIS\n input wire\t\tm00_axis_aclk,\n input wire\t\tm00_axis_aresetn,\n"} |
| {"file": "DDR4MemoryController/C2MInterface.sv", "target_type": "simple_identifier", "cursor_line": 60, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "interface_declaration", "modport_declaration", "modport_item", "modport_ports_declaration", "modport_simple_ports_declaration", "modport_simple_port", "port_identifier", "simple_identifier"], "target": "\t\t\t\t\t\toutput \tack_tran,tag_tran,full\n"} |
| {"file": "DDR4MemoryController/CalcMax.sv", "target_type": "module_declaration", "cursor_line": 28, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "Compare c4(Counters[max[0]],Counters[max[1]],max[0],max[1],max[4]);\n"} |
| {"file": "DDR4MemoryController/Controller_FSM.sv", "target_type": "simple_identifier", "cursor_line": 41, "target_nlines": 1, "node_depth": 5, "node_path": ["source_file", "package_or_generate_item_declaration", "net_declaration", "list_of_net_decl_assignments", "ERROR", "simple_identifier"], "target": "ShiftRegMC ShiftRead (.clock, .reset, .ShiftInput(ShiftInputRd), .ShiftOutput(ShiftOutputRd));\r\n"} |
| {"file": "DDR4MemoryController/DDR4Interface.sv", "target_type": "expression", "cursor_line": 251, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "package_or_generate_item_declaration", "property_declaration", "property_spec", "property_expr", "sequence_expr", "sequence_expr", "expression_or_dist", "expression"], "target": "\t ((cs_n === LOW) && (cke === `HIGH) && $fell(act_n))|-> ##TRCD ($fell(`CAS) || $rose(act_n));\n"} |
| {"file": "DDR4MemoryController/Memory.sv", "target_type": "case_statement", "cursor_line": 218, "target_nlines": 4, "node_depth": 8, "node_path": ["source_file", "package_or_generate_item_declaration", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "case_statement"], "target": "\t\t\t5'b10000: next = write;\t\n\t\t\t5'b01000: next = read;\t\n\t\t\t5'b00100: next = writeA;\t\n\t\t\t5'b00010: next = readA;\t\n"} |
| {"file": "DDR4MemoryController/MemoryController.sv", "target_type": "simple_identifier", "cursor_line": 71, "target_nlines": 1, "node_depth": 5, "node_path": ["source_file", "package_or_generate_item_declaration", "net_declaration", "list_of_net_decl_assignments", "ERROR", "simple_identifier"], "target": "\t\t.DataOut(Data_sf), .AddrOut(Address_sf),\n"} |
| {"file": "DDR4MemoryController/ReadWrite.sv", "target_type": "module_declaration", "cursor_line": 58, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\tinput write,\n\toutput [63:0] DataBus,\n\tinput [7:0][63:0] DataHost,\n\toutput logic DQS_t,\n\toutput logic DQS_c);\n"} |
| {"file": "DDR4MemoryController/Read_data_comm.sv", "target_type": "module_declaration", "cursor_line": 25, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "assign read_valid = IF.valid_data;\r\n\r\nendmodule\r\n"} |
| {"file": "DDR4MemoryController/Receive_command.sv", "target_type": "module_declaration", "cursor_line": 35, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\tstate<=next_state;\r\n\tend\r\nend\r\n\r\n"} |
| {"file": "DDR4MemoryController/Scheduler.sv", "target_type": "simple_identifier", "cursor_line": 11, "target_nlines": 1, "node_depth": 11, "node_path": ["source_file", "package_or_generate_item_declaration", "parameter_declaration", "data_type_or_implicit1", "data_type", "packed_dimension", "constant_range", "constant_expression", "constant_expression", "constant_primary", "parameter_identifier", "simple_identifier"], "target": "\tinput logic [DATAWIDTH-1:0] DataIn,\n"} |
| {"file": "DDR4MemoryController/Send_command.sv", "target_type": "case_statement", "cursor_line": 40, "target_nlines": 1, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "\t\t\t\tnext_state=send;\r\n"} |
| {"file": "DDR4MemoryController/ShiftReg.sv", "target_type": "simple_identifier", "cursor_line": 9, "target_nlines": 1, "node_depth": 5, "node_path": ["source_file", "package_or_generate_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "simple_identifier"], "target": "\tinput [SHIFTBITS:0]ShiftInput,\n"} |
| {"file": "DDR4MemoryController/Timer.sv", "target_type": "module_declaration", "cursor_line": 6, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "module CountdownTimer(clock, Reset, HitZero,Load);\ninput clock;\ninput Reset;\ninput logic [31:0] Load;\n"} |
| {"file": "DDR4MemoryController/Top.sv", "target_type": "module_declaration", "cursor_line": 52, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\trepeat (5) @(negedge clock);\n\t$display ($time, \"\\tReset is now off\");\n\tReset = 1'b0;\n\tWrite(32'b000000000000001_00_0000000_00_000_000);\n"} |
| {"file": "SPI-Interface/interface.sv", "target_type": "primary", "cursor_line": 30, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "interface_declaration", "interface_or_generate_item", "clocking_declaration", "clocking_event", "event_expression", "expression", "primary"], "target": " clocking monitor_cb @(posedge mclk);\n"} |
| {"file": "SPI-Interface/spi/spi_interface.sv", "target_type": "simple_identifier", "cursor_line": 26, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "interface_declaration", "interface_or_generate_item", "clocking_declaration", "clocking_item", "list_of_clocking_decl_assign", "clocking_decl_assign", "simple_identifier"], "target": " input data_out_master;\n"} |
| {"file": "SPI-Interface/spi_agent.sv", "target_type": "primary", "cursor_line": 40, "target_nlines": 1, "node_depth": 8, "node_path": ["ERROR", "function_statement_or_null", "function_statement", "statement", "statement_item", "blocking_assignment", "operator_assignment", "expression", "primary"], "target": " mon=spi_monitor::type_id::create(\"mon\",this);\n"} |
| {"file": "SPI-Interface/spi_driver.sv", "target_type": "function_statement", "cursor_line": 23, "target_nlines": 1, "node_depth": 2, "node_path": ["ERROR", "function_statement_or_null", "function_statement"], "target": " super.build_phase(phase);\n"} |
| {"file": "SPI-Interface/spi_environment.sv", "target_type": "simple_identifier", "cursor_line": 30, "target_nlines": 1, "node_depth": 9, "node_path": ["ERROR", "ERROR", "class_type", "parameter_value_assignment", "list_of_parameter_assignments", "ordered_parameter_assignment", "_ordered_parameter_assignment", "data_type", "interface_identifier", "simple_identifier"], "target": " uvm_config_db#(virtual spi_interface)::set(this, \"agt\", \"vif\", vif);\n"} |
| {"file": "SPI-Interface/spi_master.v", "target_type": "module_declaration", "cursor_line": 32, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " data_out_reg<=shift_reg;\n else if(count<8)begin\n"} |
| {"file": "SPI-Interface/spi_monitor.sv", "target_type": "simple_identifier", "cursor_line": 11, "target_nlines": 1, "node_depth": 3, "node_path": ["ERROR", "class_type", "class_identifier", "simple_identifier"], "target": "class spi_monitor extends uvm_monitor;\n"} |
| {"file": "SPI-Interface/spi_scoreboard.sv", "target_type": "expression", "cursor_line": 40, "target_nlines": 1, "node_depth": 6, "node_path": ["source_file", "ERROR", "ERROR", "class_item", "text_macro_usage", "list_of_actual_arguments", "expression"], "target": " `uvm_info(\"\",$sformatf(\"data_out_master:%0h data_out_slave:%0h\",trans.data_out_master,trans.data_out_slave),UVM_LOW)\n"} |
| {"file": "SPI-Interface/spi_sequence.sv", "target_type": "simple_identifier", "cursor_line": 21, "target_nlines": 1, "node_depth": 21, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "task_declaration", "task_body_declaration", "statement_or_null", "statement", "statement_item", "loop_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "blocking_assignment", "operator_assignment", "variable_lvalue", "simple_identifier"], "target": " seq=new();\n"} |
| {"file": "SPI-Interface/spi_sequence_item.sv", "target_type": "data_type", "cursor_line": 13, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_property", "data_declaration", "data_type_or_implicit1", "data_type"], "target": " rand bit [7:0]data_in_slave;\n"} |
| {"file": "SPI-Interface/spi_sequencer.sv", "target_type": "primary", "cursor_line": 12, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "class_constructor_declaration", "list_of_arguments_parent", "expression", "primary"], "target": " super.new(name, parent);\n"} |
| {"file": "SPI-Interface/spi_slave.v", "target_type": "module_declaration", "cursor_line": 14, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " \n assign data_out=read?data_out_reg:8'h00;\n \n always@(posedge sclk)\n if(load) begin\n"} |
| {"file": "SPI-Interface/spi_test.sv", "target_type": "port_identifier", "cursor_line": 22, "target_nlines": 1, "node_depth": 3, "node_path": ["ERROR", "tf_port_list", "tf_port_item1", "port_identifier"], "target": " function void build_phase(uvm_phase phase);\n"} |
| {"file": "SPI-Interface/spi_top_dut.v", "target_type": "module_declaration", "cursor_line": 22, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " property p2;\n @(posedge mclk)\n disable iff(!reset)\n load_slave|->!read_slave;\n"} |
| {"file": "Shuhai/hw/rtl/u280_ddr/hbm_bench.vh", "target_type": "blocking_assignment", "cursor_line": 133, "target_nlines": 1, "node_depth": 10, "node_path": ["source_file", "interface_declaration", "interface_item", "interface_or_generate_item", "package_or_generate_item_declaration", "task_declaration", "task_body_declaration", "statement_or_null", "statement", "statement_item", "blocking_assignment"], "target": " wready = 1'b0;\r\n"} |
| {"file": "Shuhai/hw/rtl/u280_ddr/hbm_benchmark.sv", "target_type": "primary", "cursor_line": 2110, "target_nlines": 1, "node_depth": 7, "node_path": ["ERROR", "interface_or_generate_item", "interface_instantiation", "hierarchical_instance", "list_of_port_connections", "named_port_connection", "expression", "primary"], "target": " .m_axi_wlast (m_axi_wlast),\n"} |
| {"file": "Shuhai/hw/rtl/u280_ddr/lt_engine.sv", "target_type": "module_declaration", "cursor_line": 124, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n if ( ld_params_rd_reg & (lt_params[(PARAMS_BITS+225)+:5]==ENGINE_ID) )// (lt_params[233:226] == ENGINE_ID))\n"} |
| {"file": "Shuhai/hw/rtl/u280_ddr/rd_engine.sv", "target_type": "module_declaration", "cursor_line": 221, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " state <= RD_END; \n else\n"} |
| {"file": "Shuhai/hw/rtl/u280_ddr/wr_engine.sv", "target_type": "module_declaration", "cursor_line": 60, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " reg [31:0] work_group_size;\n reg [31:0] stride ;\n reg isRdLatencyTest;\n reg [63:0] mem_op_index ;\n reg [ADDR_WIDTH - 1:0] offset_addr ;\n"} |
| {"file": "Shuhai/hw/rtl/u280_ddr/xdma_app.v", "target_type": "module_declaration", "cursor_line": 179, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n xdma_control #(\n .N_MEM_INTF (N_MEM_INTF),\n .N_ULTRARAM_INTF (N_ULTRARAM_INTF)\n"} |
| {"file": "Shuhai/hw/rtl/u280_ddr/xdma_control.sv", "target_type": "case_statement", "cursor_line": 240, "target_nlines": 4, "node_depth": 14, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " end\n else\n r_nstate = RIDLE;\n end\n"} |
| {"file": "Shuhai/hw/rtl/u280_hbm/hbm_bench.vh", "target_type": "data_type", "cursor_line": 35, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "interface_declaration", "interface_item", "interface_or_generate_item", "package_or_generate_item_declaration", "data_declaration", "data_type_or_implicit1", "data_type"], "target": "logic[LEN_WIDTH-1:0] arlen;\r\n"} |
| {"file": "Shuhai/hw/rtl/u280_hbm/hbm_benchmark.sv", "target_type": "simple_identifier", "cursor_line": 1375, "target_nlines": 1, "node_depth": 1, "node_path": ["ERROR", "simple_identifier"], "target": " .AXI_17_ARESET_N (hbm_axi[17].arstn ), //resetn\n"} |
| {"file": "Shuhai/hw/rtl/u280_hbm/lt_engine.sv", "target_type": "module_declaration", "cursor_line": 41, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " output [15:0] lat_timer ,\n"} |
| {"file": "Shuhai/hw/rtl/u280_hbm/rd_engine.sv", "target_type": "case_statement", "cursor_line": 249, "target_nlines": 5, "node_depth": 22, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " state <= RD_END; \n end\n end\n\n RD_END: \n"} |
| {"file": "Shuhai/hw/rtl/u280_hbm/wr_engine.sv", "target_type": "case_statement", "cursor_line": 249, "target_nlines": 2, "node_depth": 22, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " \n default:\n"} |
| {"file": "Shuhai/hw/rtl/u280_hbm/xdma_app.v", "target_type": "module_declaration", "cursor_line": 127, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input wire user_clk,\n"} |
| {"file": "Shuhai/hw/rtl/u280_hbm/xdma_control.sv", "target_type": "case_statement", "cursor_line": 239, "target_nlines": 3, "node_depth": 14, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " else\n r_nstate = RIDLE;\n end\n"} |
| {"file": "analogue-pocket-utils/ip/data_loader.sv", "target_type": "module_declaration", "cursor_line": 181, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " READ_WRITE: begin\n // Read data is available\n"} |
| {"file": "analogue-pocket-utils/ip/data_unloader.sv", "target_type": "module_declaration", "cursor_line": 216, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " reg [5:0] data_read_state = 0;\n\n localparam READ_ADDRESS_DELAY = 1;\n"} |
| {"file": "analogue-pocket-utils/ip/debug_key.v", "target_type": "module_declaration", "cursor_line": 66, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " synch_3 rx_synch (\n cart_tran_pin31,\n"} |
| {"file": "analogue-pocket-utils/ip/hex_loader.v", "target_type": "case_statement", "cursor_line": 101, "target_nlines": 2, "node_depth": 30, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " begin\n addr[15:12] <= digit;\n"} |
| {"file": "analogue-pocket-utils/ip/mem/psram.sv", "target_type": "case_statement", "cursor_line": 303, "target_nlines": 1, "node_depth": 14, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " cram_a <= addr[21:16];\n"} |
| {"file": "analogue-pocket-utils/ip/mem/test/psram_tb.sv", "target_type": "module_declaration", "cursor_line": 117, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " $error(\"ce0 rose too early\");\n\n"} |
| {"file": "analogue-pocket-utils/ip/sound_i2s.sv", "target_type": "module_declaration", "cursor_line": 66, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " end\n\n prev_audio_mclk <= audio_mclk;\n end\n\n"} |
| {"file": "analogue-pocket-utils/ip/sync_fifo.sv", "target_type": "case_statement", "cursor_line": 82, "target_nlines": 3, "node_depth": 14, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " READ_DELAY: begin\n read_state <= READ_WRITE;\n end\n"} |
| {"file": "analogue-pocket-utils/ip/test/common.v", "target_type": "module_declaration", "cursor_line": 67, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": ");\n\n reg [WIDTH-1:0] stage_1;\n reg [WIDTH-1:0] stage_2;\n"} |
| {"file": "analogue-pocket-utils/ip/test/data_loader_16_tb.sv", "target_type": "module_declaration", "cursor_line": 61, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " end\n\n always begin\n #half_period_mem clk_memory = ~clk_memory;\n end\n"} |
| {"file": "analogue-pocket-utils/ip/test/data_loader_8_tb.sv", "target_type": "module_declaration", "cursor_line": 34, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " .write_data(write_data)\n"} |
| {"file": "analogue-pocket-utils/ip/test/data_unloader_16_tb.sv", "target_type": "module_declaration", "cursor_line": 125, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " else $error(\"read_en changed\");\n\n #(8 * period_mem);\n"} |
| {"file": "analogue-pocket-utils/ip/test/data_unloader_8_tb.sv", "target_type": "module_declaration", "cursor_line": 83, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n bridge_rd = 0;\n"} |
| {"file": "analogue-pocket-utils/ip/test/sync_fifo_tb.sv", "target_type": "module_declaration", "cursor_line": 6, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n localparam period = 20;\n localparam half_period = period / 2;\n\n localparam period_read = 10;\n"} |
| {"file": "reDIP-CIA/gateware/bcd_add.sv", "target_type": "module_declaration", "cursor_line": 25, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " output logic [WID-1:0] dout,\n"} |
| {"file": "reDIP-CIA/gateware/bcd_update.sv", "target_type": "module_declaration", "cursor_line": 24, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input logic [WID-1:0] win, // Write data\n input logic [WID-1:0] din, // Current value\n input logic cin, // Carry in\n output logic [WID-1:0] dout, // New value\n"} |
| {"file": "reDIP-CIA/gateware/cia_control.sv", "target_type": "module_declaration", "cursor_line": 64, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " ta_ctrl.toggle = ctrl.cra.outmode;\n tb_ctrl.toggle = ctrl.crb.outmode;\n\n // Contrary to what's stated in the datasheet, the control register\n // LOAD bit is actually stored, and is ANDed with the control register\n"} |
| {"file": "reDIP-CIA/gateware/cia_core.sv", "target_type": "module_declaration", "cursor_line": 207, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " .phi2_dn (phi2_dn),\n .res (res),\n"} |
| {"file": "reDIP-CIA/gateware/cia_edgedet.sv", "target_type": "module_declaration", "cursor_line": 23, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input logic phi2_dn,\n input logic pad_i,\n output logic posedge_o\n"} |
| {"file": "reDIP-CIA/gateware/cia_interrupt.sv", "target_type": "case_statement", "cursor_line": 70, "target_nlines": 4, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " 2'b01: { ir_n, irq } = 2'b01;\n 2'b10: { ir_n, irq } = 2'b10;\n 2'b11: { ir_n, irq } = 2'b00;\n endcase\n"} |
| {"file": "reDIP-CIA/gateware/cia_io.sv", "target_type": "expression", "cursor_line": 81, "target_nlines": 1, "node_depth": 12, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "blocking_assignment", "operator_assignment", "expression"], "target": " phi1_io = ~phi2_io;\n"} |
| {"file": "reDIP-CIA/gateware/cia_pkg.sv", "target_type": "simple_identifier", "cursor_line": 97, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "package_declaration", "package_or_generate_item_declaration", "data_declaration", "type_declaration", "data_type", "struct_union_member", "list_of_variable_decl_assignments", "variable_decl_assignment", "simple_identifier"], "target": " logic pbon;\n"} |
| {"file": "reDIP-CIA/gateware/cia_ports.sv", "target_type": "module_declaration", "cursor_line": 24, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input logic rd,\n input logic we,\n input cia::reg4_t addr,\n"} |
| {"file": "reDIP-CIA/gateware/cia_serial.sv", "target_type": "module_declaration", "cursor_line": 155, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " tx_sp_next <= sr[7];\n end\n end\n"} |
| {"file": "reDIP-CIA/gateware/cia_timer.sv", "target_type": "module_declaration", "cursor_line": 46, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " always_comb begin\n prescaler_next = { hi_w ? data : prescaler[15:8], lo_w ? data : prescaler[7:0] };\n"} |
| {"file": "reDIP-CIA/gateware/cia_tod.sv", "target_type": "case_statement", "cursor_line": 122, "target_nlines": 4, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " 2'b01: { tod_sample, tod_hold } = 2'b01;\n 2'b10: { tod_sample, tod_hold } = 2'b10;\n 2'b11: { tod_sample, tod_hold } = 2'b00;\n endcase\n"} |
| {"file": "reDIP-CIA/gateware/ice40_init.sv", "target_type": "module_declaration", "cursor_line": 49, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " // Reset is asserted from the very beginning.\n always_comb begin\n rst_24 = !(bram_cnt == 8'hff);\n"} |
| {"file": "reDIP-CIA/gateware/redip_cia.sv", "target_type": "module_declaration", "cursor_line": 55, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " inout logic PB0,\n inout logic PB1,\n"} |
| {"file": "sigma_delta_converters/rtl/cic_comb.sv", "target_type": "module_declaration", "cursor_line": 27, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " if(rst) begin\n data_out <= 0;\n"} |
| {"file": "sigma_delta_converters/rtl/cic_integrator.sv", "target_type": "module_declaration", "cursor_line": 18, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " output bit [WIDTH-1:0] data_out\n"} |
| {"file": "sigma_delta_converters/rtl/dc_blocker.sv", "target_type": "module_declaration", "cursor_line": 25, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " output bit [WIDTH-1:0] data_out\n);\n"} |
| {"file": "sigma_delta_converters/rtl/fir_compensator.sv", "target_type": "primary", "cursor_line": 61, "target_nlines": 1, "node_depth": 5, "node_path": ["ERROR", "for_step", "operator_assignment", "expression", "expression", "primary"], "target": " for(i = 0; i < 2; i = i + 1) begin\n"} |
| {"file": "sigma_delta_converters/rtl/hw_test/pll/pll.v", "target_type": "module_declaration", "cursor_line": 144, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\t\taltpll_component.port_extclk2 = \"PORT_UNUSED\",\n\t\taltpll_component.port_extclk3 = \"PORT_UNUSED\",\n\t\taltpll_component.width_clock = 5;\n\n\n"} |
| {"file": "sigma_delta_converters/rtl/hw_test/pll/pll_inst.v", "target_type": "simple_identifier", "cursor_line": 3, "target_nlines": 1, "node_depth": 5, "node_path": ["source_file", "package_or_generate_item_declaration", "net_declaration", "list_of_net_decl_assignments", "net_decl_assignment", "simple_identifier"], "target": "\t.c0 ( c0_sig )\n"} |
| {"file": "sigma_delta_converters/rtl/hw_test/shifter.sv", "target_type": "module_declaration", "cursor_line": 60, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " ram_pong[ram_wr_addr] <= i_data;\n end\n ram_wr_addr <= ram_wr_addr + 1;\n if(ram_wr_addr == ram_cmp) begin\n ram_select <= ~ram_select;\n"} |
| {"file": "sigma_delta_converters/rtl/hw_test/top.sv", "target_type": "case_statement", "cursor_line": 210, "target_nlines": 5, "node_depth": 22, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " case(nibble_idx)\n 0: nibble_to_send = sample_out[23:20];\n 1: nibble_to_send = sample_out[19:16];\n 2: nibble_to_send = sample_out[15:12];\n 3: nibble_to_send = sample_out[11:8];\n"} |
| {"file": "sigma_delta_converters/rtl/hw_test/uart.sv", "target_type": "module_declaration", "cursor_line": 142, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " tx_baud_en <= 0;\n end\n if(rst) begin\n"} |
| {"file": "sigma_delta_converters/rtl/sigma_delta_adc.sv", "target_type": "module_declaration", "cursor_line": 6, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " parameter int OVERSAMPLE_RATE = 256,\n"} |
| {"file": "sigma_delta_converters/rtl/sigma_delta_dac.sv", "target_type": "module_declaration", "cursor_line": 15, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n bit [DAC_BITLEN:0] acc1 = 0;\n always_ff @(posedge clk) begin\n acc1 <= acc1[DAC_BITLEN-1:0] + dac_input;\n"} |
| {"file": "sigma_delta_converters/tb/adc/sigma_delta_adc_tb.sv", "target_type": "module_declaration", "cursor_line": 67, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " sample_in = sample_in + 1;\n //write to file\n $fdisplay(fd, \"%f\", adc_input);\n //wait for clock\n"} |
| {"file": "sigma_delta_converters/tb/dac/sigma_delta_dac_tb.sv", "target_type": "module_declaration", "cursor_line": 150, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " wait(rst == 0);\n fd = $fopen(OUTPUT_FILE, \"w\");\n repeat(50) @(posedge clk);\n"} |
| {"file": "sigma_delta_converters/tb/shifter/shifter_tb.sv", "target_type": "module_declaration", "cursor_line": 7, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " bit sim_done = 0;\n initial begin\n $dumpfile(\"dump.vcd\");\n $dumpvars;\n wait(sim_done == 1);\n"} |
| {"file": "AMBA_AXI3/AXI_Protocol/Design and Verification/AXI_Interface.sv", "target_type": "port_identifier", "cursor_line": 126, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "interface_declaration", "modport_declaration", "modport_item", "modport_ports_declaration", "modport_simple_ports_declaration", "modport_simple_port", "port_identifier"], "target": "\tinput\tARBURST,\n"} |
| {"file": "AMBA_AXI3/AXI_Protocol/Design and Verification/AXI_master.sv", "target_type": "case_statement", "cursor_line": 198, "target_nlines": 4, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "\t\t\t axim.BREADY = '0;\n\t\t\t BNext_state_M = B_START_M;\n\t\t\tend\t\t\n \n"} |
| {"file": "AMBA_AXI3/AXI_Protocol/Design and Verification/AXI_slave.sv", "target_type": "case_statement", "cursor_line": 948, "target_nlines": 5, "node_depth": 45, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement", "case_item", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement", "case_item", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement", "case_item", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " wrap_boundary2 = 16 * 1;\n end\n \n 3'b001:begin\n wrap_boundary2 = 16 * 2;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n"} |
| {"file": "AMBA_AXI3/AXI_Protocol/Design and Verification/AXI_top_design.sv", "target_type": "module_declaration", "cursor_line": 53, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\t\t\t.arburst(arburst)\n);\n\n"} |
| {"file": "AMBA_AXI3/AXI_Protocol/Design and Verification/axi_Assertions.sv", "target_type": "module_declaration", "cursor_line": 132, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "// After WLAST is asserted, slave should initiate response\nproperty AXI_WLAST_BVALID_p;\n@(posedge clk)\n"} |
| {"file": "AMBA_AXI3/AXI_Protocol/Design and Verification/axi_driver.sv", "target_type": "simple_identifier", "cursor_line": 249, "target_nlines": 1, "node_depth": 76, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "task_declaration", "task_body_declaration", "statement_or_null", "statement", "statement_item", "loop_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "loop_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "loop_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "loop_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "loop_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "wait_statement", "statement_or_null", "statement", "statement_item", "checker_instantiation", "checker_identifier", "simple_identifier"], "target": "\t\t\t\t\t\t\t\t\tstimulus(rand_awid,rand_awaddr_valid,rand_awaddr_invalid,rand_awaddr_readonly,rand_wdata,rand_araddr_valid,rand_araddr_invalid,rand_arid);\n"} |
| {"file": "AMBA_AXI3/AXI_Protocol/Design and Verification/axi_env.sv", "target_type": "include_compiler_directive", "cursor_line": 1, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "include_compiler_directive"], "target": "`include\"//khensu/Home06/anurag/Desktop/SV_AXI_finlly_final/axi_driver.sv\"\n"} |
| {"file": "AMBA_AXI3/AXI_Protocol/Design and Verification/axi_monitor.sv", "target_type": "simple_identifier", "cursor_line": 13, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "class_constructor_declaration", "tf_port_list", "tf_port_item1", "port_identifier", "simple_identifier"], "target": " function new(virtual axi intf); \n"} |
| {"file": "AMBA_AXI3/AXI_Protocol/Design and Verification/axi_scoreboard_update.sv", "target_type": "primary_literal", "cursor_line": 141, "target_nlines": 1, "node_depth": 53, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "task_declaration", "task_body_declaration", "statement_or_null", "statement", "statement_item", "loop_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "loop_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "ERROR", "clockvar_expression", "select1", "constant_range", "constant_expression", "constant_primary", "primary_literal"], "target": "\t\t\t\t\t\t\t\t\t\t\t\t\tdata_received[31:24] = top.slave_mem[address_read+3];\n"} |
| {"file": "AMBA_AXI3/AXI_Protocol/Design and Verification/axi_testcase.sv", "target_type": "simple_identifier", "cursor_line": 35, "target_nlines": 1, "node_depth": 12, "node_path": ["source_file", "program_declaration", "non_port_program_item", "initial_construct", "statement_or_null", "statement", "statement_item", "seq_block", "ERROR", "clockvar_expression", "select1", "member_identifier", "simple_identifier"], "target": "\tenv.drvr.read_size_invalid(rand_awid, rand_awaddr_valid, rand_awaddr_invalid, rand_awaddr_readonly, rand_wdata, rand_araddr_valid, rand_araddr_invalid, rand_arid );\n"} |
| {"file": "AMBA_AXI3/AXI_Protocol/Design and Verification/axi_top.sv", "target_type": "module_declaration", "cursor_line": 65, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\t\t\t\t.arburst(arburst),\n\t\t\t\t .intf(intf)\n"} |
| {"file": "AMBA_AXI3/AXI_Protocol/Emulation/AXI_Interface.sv", "target_type": "port_identifier", "cursor_line": 120, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "interface_declaration", "modport_declaration", "modport_item", "modport_ports_declaration", "modport_simple_ports_declaration", "modport_simple_port", "port_identifier"], "target": "\tinput\tARLEN,\n"} |
| {"file": "AMBA_AXI3/AXI_Protocol/Emulation/AXI_master.sv", "target_type": "case_statement", "cursor_line": 501, "target_nlines": 3, "node_depth": 19, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement", "case_item", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " address_slave_reg = address_slave_temp;\n \n read_mem[address_slave_reg] = axim.RDATA[15:8];\n"} |
| {"file": "AMBA_AXI3/AXI_Protocol/Emulation/AXI_slave.sv", "target_type": "case_statement", "cursor_line": 967, "target_nlines": 4, "node_depth": 45, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement", "case_item", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement", "case_item", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement", "case_item", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " end\n \n 3'b010:begin\n wrap_boundary2 = 4 * 4;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n"} |
| {"file": "AMBA_AXI3/AXI_Protocol/Emulation/AXI_top_design.sv", "target_type": "module_declaration", "cursor_line": 64, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "logic\t[1:0]\tAWBURST;\nlogic\t[2:0]\tAWSIZE;\n"} |
| {"file": "axi_riscv_atomics/src/axi_res_tbl.sv", "target_type": "module_declaration", "cursor_line": 60, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " if (check_clr_req_i) begin\n check_clr_gnt_o = 1'b1;\n"} |
| {"file": "axi_riscv_atomics/src/axi_riscv_amos.sv", "target_type": "case_statement", "cursor_line": 428, "target_nlines": 5, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " end else begin\n aw_state_d = SEND_AW;\n end\n // Remember outstanding W beats before injected request\n if (aw_state_q == WAIT_RESULT_AW) begin\n"} |
| {"file": "axi_riscv_atomics/src/axi_riscv_amos_alu.sv", "target_type": "module_declaration", "cursor_line": 70, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "`ifndef VERILATOR\n initial begin: validate_params\n assert (DATA_WIDTH > 0)\n"} |
| {"file": "axi_riscv_atomics/src/axi_riscv_amos_wrap.sv", "target_type": "module_declaration", "cursor_line": 105, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " .mst_aw_user_o ( mst.aw_user ),\n"} |
| {"file": "axi_riscv_atomics/src/axi_riscv_atomics.sv", "target_type": "simple_identifier", "cursor_line": 188, "target_nlines": 1, "node_depth": 5, "node_path": ["source_file", "package_or_generate_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "simple_identifier"], "target": " logic [2:0] int_axi_ar_size;\n"} |
| {"file": "axi_riscv_atomics/src/axi_riscv_atomics_structs.sv", "target_type": "module_declaration", "cursor_line": 81, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " .CUT_OUP_POP_INP_GNT ( CutOupPopInpGnt )\n"} |
| {"file": "axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv", "target_type": "module_declaration", "cursor_line": 60, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " .AXI_MAX_READ_TXNS (AXI_MAX_READ_TXNS),\n .AXI_MAX_WRITE_TXNS (AXI_MAX_WRITE_TXNS),\n .AXI_USER_AS_ID (AXI_USER_AS_ID),\n .AXI_USER_ID_MSB (AXI_USER_ID_MSB),\n .AXI_USER_ID_LSB (AXI_USER_ID_LSB),\n"} |
| {"file": "axi_riscv_atomics/src/axi_riscv_lrsc.sv", "target_type": "case_statement", "cursor_line": 815, "target_nlines": 2, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " if (!(slv_ar_valid_i && slv_ar_lock_i &&\n slv_ar_addr_i[AXI_ADDR_WIDTH-1:AXI_ADDR_LSB] == clr_addr_q)) begin\n"} |
| {"file": "axi_riscv_atomics/src/axi_riscv_lrsc_wrap.sv", "target_type": "module_declaration", "cursor_line": 43, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input logic rst_ni,\n AXI_BUS.Master mst,\n AXI_BUS.Slave slv\n"} |
| {"file": "axi_riscv_atomics/test/axi_riscv_atomics_synth.v", "target_type": "module_declaration", "cursor_line": 162, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " .slv_aw_valid_i(slv_aw_valid_i),\n\n .slv_ar_addr_i(slv_ar_addr_i),\n .slv_ar_prot_i(slv_ar_prot_i),\n .slv_ar_region_i(slv_ar_region_i),\n"} |
| {"file": "axi_riscv_atomics/test/axi_riscv_atomics_tb.sv", "target_type": "variable_decl_assignment", "cursor_line": 331, "target_nlines": 1, "node_depth": 4, "node_path": ["ERROR", "block_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment"], "target": " automatic logic [2:0] size;\n"} |
| {"file": "axi_riscv_atomics/test/axi_riscv_lrsc_synth.v", "target_type": "module_declaration", "cursor_line": 122, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input [AXI_USER_WIDTH-1:0] mst_r_user_i,\n"} |
| {"file": "axi_riscv_atomics/test/axi_riscv_lrsc_tb.sv", "target_type": "primary", "cursor_line": 658, "target_nlines": 1, "node_depth": 29, "node_path": ["source_file", "ERROR", "statement_or_null", "statement", "statement_item", "loop_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "cond_predicate", "expression", "expression", "primary", "select1", "bit_select1", "expression", "primary"], "target": " if (act_beat.b_resp[1] == 1'b0) begin\n"} |
| {"file": "axi_riscv_atomics/test/golden_memory.sv", "target_type": "case_statement", "cursor_line": 296, "target_nlines": 3, "node_depth": 31, "node_path": ["source_file", "package_declaration", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "task_declaration", "task_body_declaration", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " end\n default: begin\n w_data = data_uo;\n"} |
| {"file": "axi_riscv_atomics/test/tb_axi_pkg.sv", "target_type": "simple_identifier", "cursor_line": 146, "target_nlines": 1, "node_depth": 12, "node_path": ["source_file", "package_declaration", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "task_declaration", "task_body_declaration", "block_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "simple_identifier"], "target": " automatic ax_beat_t ax_beat = new;\n"} |
| {"file": "AXI/axi_config_objs.svh", "target_type": "primary", "cursor_line": 17, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "class_constructor_declaration", "list_of_arguments_parent", "expression", "primary"], "target": " super.new(name);\r\n"} |
| {"file": "AXI/axi_env.sv", "target_type": "primary", "cursor_line": 30, "target_nlines": 1, "node_depth": 11, "node_path": ["source_file", "package_or_generate_item_declaration", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "blocking_assignment", "operator_assignment", "expression", "primary"], "target": " slave = axi_slave::type_id::create(\"slave\", this);\r\n"} |
| {"file": "AXI/axi_interface.sv", "target_type": "simple_identifier", "cursor_line": 46, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "interface_declaration", "interface_or_generate_item", "clocking_declaration", "clocking_item", "list_of_clocking_decl_assign", "clocking_decl_assign", "simple_identifier"], "target": " input AWID, AWADDR, AWLEN, AWSIZE, AWBURST,AWVALID, WID, WDATA, WSTRB, WLAST, WVALID, \r\n"} |
| {"file": "AXI/axi_m_driver.sv", "target_type": "simple_identifier", "cursor_line": 144, "target_nlines": 1, "node_depth": 6, "node_path": ["source_file", "ERROR", "ERROR", "expression", "primary", "let_expression", "simple_identifier"], "target": "task axi_m_driver::send_read_address();\r\n"} |
| {"file": "AXI/axi_m_monitor.sv", "target_type": "simple_identifier", "cursor_line": 91, "target_nlines": 1, "node_depth": 25, "node_path": ["ERROR", "ERROR", "primary", "function_subroutine_call", "subroutine_call", "method_call", "primary", "function_subroutine_call", "subroutine_call", "method_call", "primary", "function_subroutine_call", "subroutine_call", "method_call", "primary", "function_subroutine_call", "subroutine_call", "method_call", "primary", "function_subroutine_call", "subroutine_call", "method_call", "ERROR", "method_identifier", "method_identifier", "simple_identifier"], "target": " r_trans.b_size = vif.mon_cb.ARSIZE;\r\n"} |
| {"file": "AXI/axi_master.sv", "target_type": "data_type", "cursor_line": 5, "target_nlines": 1, "node_depth": 19, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_property", "data_declaration", "data_type_or_implicit1", "data_type", "class_type", "parameter_value_assignment", "list_of_parameter_assignments", "ordered_parameter_assignment", "_ordered_parameter_assignment", "data_type", "class_type", "parameter_value_assignment", "list_of_parameter_assignments", "ordered_parameter_assignment", "_ordered_parameter_assignment", "data_type"], "target": " uvm_sequencer#(axi_transaction#(D_WIDTH, A_WIDTH)) w_seqr;\r\n"} |
| {"file": "AXI/axi_package.svh", "target_type": "include_compiler_directive", "cursor_line": 11, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "include_compiler_directive"], "target": "`include \"axi_s_monitor.sv\"\r\n"} |
| {"file": "AXI/axi_read_seq.sv", "target_type": "primary", "cursor_line": 15, "target_nlines": 1, "node_depth": 17, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "class_constructor_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "conditional_statement", "cond_predicate", "expression", "primary", "ERROR", "mintypmax_expression", "expression", "primary"], "target": " if(!uvm_config_db#(test_config)::get(null, \"uvm_test_top.seq\", \"config\", test_cfg)) \r\n"} |
| {"file": "AXI/axi_s_driver.sv", "target_type": "simple_identifier", "cursor_line": 208, "target_nlines": 1, "node_depth": 3, "node_path": ["source_file", "package_or_generate_item_declaration", "net_declaration", "simple_identifier"], "target": " s_rtrans.b_type = B_TYPE'(vif.s_drv_cb.ARBURST);\r\n"} |
| {"file": "AXI/axi_s_monitor.sv", "target_type": "simple_identifier", "cursor_line": 6, "target_nlines": 1, "node_depth": 13, "node_path": ["ERROR", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_property", "data_declaration", "data_type_or_implicit1", "data_type", "parameter_value_assignment", "list_of_parameter_assignments", "named_parameter_assignment", "param_expression", "data_type", "simple_identifier"], "target": " virtual axi_intf#(.D_WIDTH(D_WIDTH), .A_WIDTH(A_WIDTH)).SMON vif;\r\n"} |
| {"file": "AXI/axi_scoreboard.sv", "target_type": "operator_assignment", "cursor_line": 83, "target_nlines": 1, "node_depth": 5, "node_path": ["ERROR", "statement_or_null", "statement", "statement_item", "blocking_assignment", "operator_assignment"], "target": " m_ap_imp = new(\"m_ap_imp\", this);\r\n"} |
| {"file": "AXI/axi_slave.sv", "target_type": "simple_identifier", "cursor_line": 13, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "class_constructor_declaration", "list_of_arguments_parent", "expression", "primary", "simple_identifier"], "target": " super.new(name, parent);\r\n"} |
| {"file": "AXI/axi_tb_top.sv", "target_type": "module_declaration", "cursor_line": 23, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " env_cfg.intf = intf;\r\n uvm_config_db#(env_config)::set(null, \"uvm_test_top\", \"config\", env_cfg);\r\n uvm_config_db#(env_config)::set(null, \"uvm_test_top.env.master\", \"config\", env_cfg);\r\n"} |
| {"file": "AXI/axi_test.sv", "target_type": "primary", "cursor_line": 36, "target_nlines": 1, "node_depth": 17, "node_path": ["source_file", "package_or_generate_item_declaration", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "blocking_assignment", "operator_assignment", "expression", "primary", "function_subroutine_call", "subroutine_call", "tf_call", "list_of_arguments_parent", "expression", "primary"], "target": " wr_seq = new(\"wr_seq\");\r\n"} |
| {"file": "AXI/axi_transaction.sv", "target_type": "simple_identifier", "cursor_line": 33, "target_nlines": 1, "node_depth": 15, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "constraint_declaration", "constraint_block", "constraint_block_item", "constraint_expression", "constraint_set", "constraint_expression", "expression_or_dist", "expression", "expression", "expression", "primary", "simple_identifier"], "target": " data[i].size() == 2**b_size;\r\n"} |
| {"file": "AXI/axi_write_seq.sv", "target_type": "data_type", "cursor_line": 4, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "ERROR", "class_type", "parameter_value_assignment", "list_of_parameter_assignments", "ordered_parameter_assignment", "_ordered_parameter_assignment", "data_type"], "target": " `uvm_object_param_utils(axi_write_seq#(D_WIDTH, A_WIDTH));\r\n"} |
| {"file": "FPGA-SATA-HBA/RTL/IP/clk_wiz_0/clk_wiz_0.v", "target_type": "module_declaration", "cursor_line": 91, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " .clk_in1_n(clk_in1_n)\n"} |
| {"file": "FPGA-SATA-HBA/RTL/IP/clk_wiz_0/clk_wiz_0_clk_wiz.v", "target_type": "module_declaration", "cursor_line": 105, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n wire [15:0] do_unused;\n"} |
| {"file": "FPGA-SATA-HBA/RTL/IP/clk_wiz_0/clk_wiz_0_sim_netlist.v", "target_type": "module_declaration", "cursor_line": 129, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " .CLKOUT5_DUTY_CYCLE(0.500000),\n"} |
| {"file": "FPGA-SATA-HBA/RTL/IP/clk_wiz_0/clk_wiz_0_stub.v", "target_type": "module_declaration", "cursor_line": 19, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input reset;\r\n output locked;\r\n input clk_in1_p;\r\n"} |
| {"file": "FPGA-SATA-HBA/RTL/IP/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh", "target_type": "primary_literal", "cursor_line": 380, "target_nlines": 1, "node_depth": 16, "node_path": ["source_file", "ERROR", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "blocking_assignment", "operator_assignment", "expression", "primary", "concatenation", "expression", "primary", "primary_literal"], "target": " 10'b0010_0010_00,\r\n"} |
| {"file": "FPGA-SATA-HBA/RTL/IP/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh", "target_type": "expression", "cursor_line": 72, "target_nlines": 1, "node_depth": 17, "node_path": ["source_file", "package_or_generate_item_declaration", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "checker_instantiation", "property_expr", "sequence_expr", "expression_or_dist", "expression", "expression"], "target": " if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin\r\n"} |
| {"file": "FPGA-SATA-HBA/RTL/IP/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh", "target_type": "primary_literal", "cursor_line": 280, "target_nlines": 1, "node_depth": 12, "node_path": ["source_file", "ERROR", "statement_or_null", "statement", "statement_item", "blocking_assignment", "operator_assignment", "expression", "primary", "concatenation", "expression", "primary", "primary_literal"], "target": " 40'b11111_11111_0011111010_1111101001_0000000001,\r\n"} |
| {"file": "FPGA-SATA-HBA/RTL/IP/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh", "target_type": "blocking_assignment", "cursor_line": 203, "target_nlines": 1, "node_depth": 16, "node_path": ["source_file", "package_or_generate_item_declaration", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "blocking_assignment"], "target": " phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;\n"} |
| {"file": "FPGA-SATA-HBA/RTL/IP/clk_wiz_0/mmcm_pll_drp_func_us_plus_mmcm.vh", "target_type": "expression", "cursor_line": 815, "target_nlines": 1, "node_depth": 12, "node_path": ["source_file", "ERROR", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "blocking_assignment", "operator_assignment", "expression", "expression"], "target": "\teven_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);\r\n"} |
| {"file": "FPGA-SATA-HBA/RTL/IP/clk_wiz_0/mmcm_pll_drp_func_us_plus_pll.vh", "target_type": "primary", "cursor_line": 205, "target_nlines": 1, "node_depth": 20, "node_path": ["source_file", "package_or_generate_item_declaration", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "blocking_assignment", "operator_assignment", "expression", "expression", "primary"], "target": " phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;\n"} |
| {"file": "FPGA-SATA-HBA/RTL/fpga_uart_sata_example/fpga_uart_sata_example_top.sv", "target_type": "module_declaration", "cursor_line": 78, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " .gt_rxn ( SATA0_B_N ),\r\n .gt_txp ( SATA0_A_P ),\r\n .gt_txn ( SATA0_A_N ),\r\n // user clock output\r\n .clk ( clk ),\r\n"} |
| {"file": "FPGA-SATA-HBA/RTL/fpga_uart_sata_example/uart_rx.sv", "target_type": "case_statement", "cursor_line": 79, "target_nlines": 5, "node_depth": 26, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " end\r\n S_DATA: begin\r\n cnt <= cnt + 5'd1;\r\n if(cnt[1:0] == '1) rx_data <= {rbit, rx_data[7:1]};\r\n if(cnt == '1) stat <= (PARITY==\"NONE\") ? S_OKAY : S_PARI;\r\n"} |
| {"file": "FPGA-SATA-HBA/RTL/fpga_uart_sata_example/uart_tx.sv", "target_type": "module_declaration", "cursor_line": 159, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " txdata <= '1;\r\n fifo_rptr <= '0;\r\n fifo_rd_en <= '0;\r\n {send_data, send_last} <= '0;\r\n"} |
| {"file": "FPGA-SATA-HBA/RTL/sata_hba/sata_gth.sv", "target_type": "case_statement", "cursor_line": 152, "target_nlines": 3, "node_depth": 18, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " end\r\n WAIT_RD_DATA : begin\r\n gtrxreset_o <= 1'b1;\r\n"} |
| {"file": "FPGA-SATA-HBA/RTL/sata_hba/sata_hba_top.sv", "target_type": "module_declaration", "cursor_line": 64, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "wire gt_txoutclk;\r\nwire drp_clk;\r\n\r\n"} |
| {"file": "FPGA-SATA-HBA/RTL/sata_hba/sata_link_transport.sv", "target_type": "case_statement", "cursor_line": 256, "target_nlines": 1, "node_depth": 34, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " PRIM_R_ERR : begin rx_dword_en <= 1'b1; end\r\n"} |
| {"file": "NAND-Flash-Memory-Controller-verification/Flash controller/ACounter.v", "target_type": "module_declaration", "cursor_line": 65, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input clk;\n input Res;\n"} |
| {"file": "NAND-Flash-Memory-Controller-verification/Flash controller/ErrLoc.v", "target_type": "module_declaration", "cursor_line": 85, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "always@(posedge clk)\n if (Res)\n ECC_status <= 1'h0;\n else\n"} |
| {"file": "NAND-Flash-Memory-Controller-verification/Flash controller/H_gen.v", "target_type": "module_declaration", "cursor_line": 78, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "assign ecc[7]=1'b0;\nassign ecc[6]=rp1;\nassign ecc[5]=rp2;\nassign ecc[4]=Din[3];\n"} |
| {"file": "NAND-Flash-Memory-Controller-verification/Flash controller/MFSM.v", "target_type": "expression", "cursor_line": 457, "target_nlines": 1, "node_depth": 28, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement", "case_item", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "nonblocking_assignment", "expression"], "target": " t_start <= 1;\n"} |
| {"file": "NAND-Flash-Memory-Controller-verification/Flash controller/TFSM.v", "target_type": "case_statement", "cursor_line": 268, "target_nlines": 2, "node_depth": 18, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " S_RE:begin\n CE_n <= 0;\n"} |
| {"file": "NAND-Flash-Memory-Controller-verification/Flash controller/checker.sv", "target_type": "simple_identifier", "cursor_line": 100, "target_nlines": 1, "node_depth": 20, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "task_declaration", "task_body_declaration", "statement_or_null", "statement", "statement_item", "conditional_statement", "cond_predicate", "expression", "expression", "primary", "concatenation", "expression", "primary", "select1", "member_identifier", "simple_identifier"], "target": "\tif(command[2] != {bfm.CE_n,bfm.CLE,bfm.ALE,bfm.RE_n,bfm.WE_n}) begin\n"} |
| {"file": "NAND-Flash-Memory-Controller-verification/Flash controller/coverage.sv", "target_type": "primary", "cursor_line": 62, "target_nlines": 1, "node_depth": 8, "node_path": ["ERROR", "ERROR", "expression", "primary", "concatenation", "ERROR", "expression", "expression", "primary"], "target": "\t\tbins SysReset_and_Write\t\t= binsof(Commands) intersect {program_page} && (binsof(SystemReset.SysReset));\t\t\t\t// System reset and write command active at the same time \n"} |
| {"file": "NAND-Flash-Memory-Controller-verification/Flash controller/flash_bfm.sv", "target_type": "case_statement", "cursor_line": 115, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "interface_declaration", "interface_or_generate_item", "package_or_generate_item_declaration", "task_declaration", "task_body_declaration", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "\t\tread_page :\tbegin\n"} |
| {"file": "NAND-Flash-Memory-Controller-verification/Flash controller/flash_interface.sv", "target_type": "module_declaration", "cursor_line": 171, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " row1<= DIO;\n row2<= row1;\n"} |
| {"file": "NAND-Flash-Memory-Controller-verification/Flash controller/flash_pkg.sv", "target_type": "simple_identifier", "cursor_line": 17, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "package_declaration", "package_or_generate_item_declaration", "parameter_declaration", "list_of_param_assignments", "param_assignment", "parameter_identifier", "simple_identifier"], "target": "parameter TRUE = 1'b1;\n"} |
| {"file": "NAND-Flash-Memory-Controller-verification/Flash controller/mybuf.sv", "target_type": "module_declaration", "cursor_line": 19, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " output wire [7:0] QB\n\t \n"} |
| {"file": "NAND-Flash-Memory-Controller-verification/Flash controller/nfcm_top.v", "target_type": "case_statement", "cursor_line": 326, "target_nlines": 4, "node_depth": 14, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " 2'b10 : addr_data <= rad_1;\n 2'b01 : addr_data <= cad_2;\n default: addr_data <= cad_1;\n endcase\n"} |
| {"file": "NAND-Flash-Memory-Controller-verification/Flash controller/scoreboard.sv", "target_type": "primary_literal", "cursor_line": 268, "target_nlines": 1, "node_depth": 6, "node_path": ["ERROR", "constant_range", "ERROR", "constant_expression", "constant_expression", "constant_primary", "primary_literal"], "target": "\t\t\t\tCMD_State = CMD_State+ 32'd1;\n"} |
| {"file": "NAND-Flash-Memory-Controller-verification/Flash controller/testbench.sv", "target_type": "blocking_assignment", "cursor_line": 15, "target_nlines": 1, "node_depth": 10, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "class_constructor_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "blocking_assignment"], "target": "\t\tbfm = b;\n"} |
| {"file": "NAND-Flash-Memory-Controller-verification/Flash controller/tester.sv", "target_type": "case_statement", "cursor_line": 91, "target_nlines": 4, "node_depth": 8, "node_path": ["ERROR", "class_item", "class_method", "task_declaration", "task_body_declaration", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "\tcase(random_cmd)\n\t\tprogram_page:\twrite_cycle(Addr);\n\t\t\t\n\t\tread_page:\tread_cycle(Addr);\n"} |
| {"file": "NAND-Flash-Memory-Controller-verification/Flash controller/top.sv", "target_type": "module_declaration", "cursor_line": 13, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "flash_bfm bfm();\t\t\t\t\t\t\t\t\t\n"} |
| {"file": "altera-pcie/apps/bench/cvgt/top_level.sv", "target_type": "module_declaration", "cursor_line": 79, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " .txReady_in (txReady)\n"} |
| {"file": "altera-pcie/apps/bench/defs.vh", "target_type": "simple_identifier", "cursor_line": 14, "target_nlines": 1, "node_depth": 14, "node_path": ["source_file", "package_or_generate_item_declaration", "local_parameter_declaration", "list_of_param_assignments", "param_assignment", "constant_param_expression", "constant_mintypmax_expression", "constant_expression", "constant_primary", "constant_mintypmax_expression", "constant_expression", "constant_expression", "constant_primary", "parameter_identifier", "simple_identifier"], "target": "localparam int MTR_BASE = (PRV_BASE + 2); // metrics base address\n"} |
| {"file": "altera-pcie/apps/bench/pcie_app.sv", "target_type": "case_statement", "cursor_line": 217, "target_nlines": 5, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " state_next = S_AWAIT_REGS;\n end\n end else if (csValid == 0) begin\n // CPU is responding with a write to the CPU->FPGA queue\n state_next = S_AWAIT_CONSUME_END;\n"} |
| {"file": "altera-pcie/apps/bench/pcie_app_pkg.sv", "target_type": "simple_identifier", "cursor_line": 20, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "package_declaration", "package_or_generate_item_declaration", "local_parameter_declaration", "list_of_param_assignments", "param_assignment", "parameter_identifier", "simple_identifier"], "target": " localparam int BENCHMARK_TIMER = makestuff_tlp_xcvr_pkg::CTL_BASE - 1;\n"} |
| {"file": "altera-pcie/apps/bench/svgx/top_level.sv", "target_type": "module_declaration", "cursor_line": 50, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n .rxData_out (rxData), // Host->FPGA pipe\n .rxSOP_out (rxSOP),\n .rxEOP_out (rxEOP),\n .rxValid_out (rxValid),\n"} |
| {"file": "altera-pcie/apps/bench/tb-sys/altpcietb_bfm_driver_chaining.sv", "target_type": "port_identifier", "cursor_line": 87, "target_nlines": 1, "node_depth": 7, "node_path": ["ERROR", "module_or_generate_item", "package_or_generate_item_declaration", "function_declaration", "function_body_declaration", "tf_port_list", "tf_port_item1", "port_identifier"], "target": " function uint64 hostRead64(int addr);\n"} |
| {"file": "altera-pcie/apps/bench/tb-sys/pcie_cv_tb.sv", "target_type": "port_identifier", "cursor_line": 267, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "module_instantiation", "hierarchical_instance", "list_of_port_connections", "named_port_connection", "port_identifier"], "target": " .txdetectrx4 (1'b0), // (terminated)\n"} |
| {"file": "altera-pcie/apps/bench/tb-sys/pcie_sv_tb.sv", "target_type": "port_identifier", "cursor_line": 313, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "module_instantiation", "hierarchical_instance", "list_of_port_connections", "named_port_connection", "port_identifier"], "target": " .rx_in6 (), // (terminated)\n"} |
| {"file": "altera-pcie/apps/demo/cvgt/top_level.sv", "target_type": "module_declaration", "cursor_line": 39, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " logic txReady;\n\n pcie_cv pcie_inst(\n"} |
| {"file": "altera-pcie/apps/demo/defs.vh", "target_type": "data_type", "cursor_line": 17, "target_nlines": 1, "node_depth": 4, "node_path": ["source_file", "package_or_generate_item_declaration", "local_parameter_declaration", "data_type_or_implicit1", "data_type"], "target": "localparam int REG_BAR = (0);\n"} |
| {"file": "altera-pcie/apps/demo/pcie_app.sv", "target_type": "module_declaration", "cursor_line": 128, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " .c2fWrData_out (c2fWrData),\n .c2fRdPtr_out (c2fRdPtr),\n .c2fDTAck_in (c2fDTAck)\n );\n\n"} |
| {"file": "altera-pcie/apps/demo/pcie_app_pkg.sv", "target_type": "simple_identifier", "cursor_line": 20, "target_nlines": 1, "node_depth": 13, "node_path": ["source_file", "package_declaration", "package_or_generate_item_declaration", "local_parameter_declaration", "list_of_param_assignments", "param_assignment", "constant_param_expression", "constant_mintypmax_expression", "constant_expression", "constant_expression", "constant_primary", "package_scope", "package_identifier", "simple_identifier"], "target": " localparam int CHECKSUM_MSW = makestuff_tlp_xcvr_pkg::CTL_BASE - 1;\n"} |
| {"file": "altera-pcie/apps/demo/svgx/top_level.sv", "target_type": "module_declaration", "cursor_line": 37, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " logic txEOP;\n logic txValid;\n logic txReady;\n\n pcie_sv pcie_inst(\n"} |
| {"file": "altera-pcie/apps/demo/tb-sys/altpcietb_bfm_driver_chaining.sv", "target_type": "primary", "cursor_line": 185, "target_nlines": 1, "node_depth": 28, "node_path": ["source_file", "ERROR", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "loop_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "loop_statement", "for_step", "function_subroutine_call", "subroutine_call", "tf_call", "list_of_arguments_parent", "expression", "primary"], "target": " 1, // display EP config space after setup\n"} |
| {"file": "altera-pcie/apps/demo/tb-sys/pcie_cv_tb.sv", "target_type": "expression", "cursor_line": 423, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "module_instantiation", "hierarchical_instance", "list_of_port_connections", "named_port_connection", "expression"], "target": " .dut_hip_pipe_rxvalid3 (dut_pcie_tb_hip_pipe_rxvalid3) // .rxvalid3\n"} |
| {"file": "altera-pcie/apps/demo/tb-sys/pcie_sv_tb.sv", "target_type": "primary_literal", "cursor_line": 250, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "module_instantiation", "hierarchical_instance", "list_of_port_connections", "named_port_connection", "expression", "primary", "primary_literal"], "target": " .powerdown5 (2'b00), // (terminated)\n"} |
| {"file": "amba3-vip/pkg_amba3.sv", "target_type": "include_compiler_directive", "cursor_line": 66, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "include_compiler_directive"], "target": " `include \"pkg_amba3_axi_tx_wrap.svh\"\n"} |
| {"file": "amba3-vip/pkg_amba3_apb_if.sv", "target_type": "port_identifier", "cursor_line": 80, "target_nlines": 1, "node_depth": 6, "node_path": ["ERROR", "modport_declaration", "modport_item", "modport_ports_declaration", "modport_simple_ports_declaration", "modport_simple_port", "port_identifier"], "target": " import monitor_clear, monitor_write, monitor_read\n"} |
| {"file": "amba3-vip/pkg_amba3_apb_master.svh", "target_type": "simple_identifier", "cursor_line": 64, "target_nlines": 1, "node_depth": 10, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "task_declaration", "task_body_declaration", "tf_port_list", "tf_port_item1", "port_identifier", "simple_identifier"], "target": " apb.master_read(addr, data);\n"} |
| {"file": "amba3-vip/pkg_amba3_apb_monitor.svh", "target_type": "primary", "cursor_line": 154, "target_nlines": 1, "node_depth": 15, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "task_declaration", "task_body_declaration", "statement_or_null", "statement", "statement_item", "conditional_statement", "cond_predicate", "expression", "expression", "expression", "primary"], "target": " if (now.psel == 1'b1 && now.penable == 1'b1 && now.pready == 1'b1)\n"} |
| {"file": "amba3-vip/pkg_amba3_apb_slave.svh", "target_type": "data_type", "cursor_line": 39, "target_nlines": 1, "node_depth": 5, "node_path": ["ERROR", "class_item", "class_property", "data_declaration", "type_declaration", "data_type"], "target": " typedef logic [DATA_BITS - 1:0] data_t;\n"} |
| {"file": "amba3-vip/pkg_amba3_axi_if.sv", "target_type": "data_type", "cursor_line": 43, "target_nlines": 1, "node_depth": 6, "node_path": ["source_file", "interface_declaration", "interface_or_generate_item", "package_or_generate_item_declaration", "data_declaration", "type_declaration", "data_type"], "target": " typedef logic [DATA_BITS - 1:0] data_t;\n"} |
| {"file": "amba3-vip/pkg_amba3_axi_master.svh", "target_type": "simple_identifier", "cursor_line": 154, "target_nlines": 1, "node_depth": 28, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "task_declaration", "task_body_declaration", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "simple_immediate_assert_statement", "expression", "expression", "primary", "function_subroutine_call", "subroutine_call", "method_call", "method_call_body", "method_identifier", "method_identifier", "simple_identifier"], "target": " assert (rx.data[0].last == (tx.data.size == tx.addr.len));\n"} |
| {"file": "amba3-vip/pkg_amba3_axi_monitor.svh", "target_type": "primary", "cursor_line": 351, "target_nlines": 1, "node_depth": 16, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "task_declaration", "task_body_declaration", "block_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "expression", "primary", "assignment_pattern_expression", "assignment_pattern", "expression", "primary"], "target": " wready: axi.monitor_cb.wready\n"} |
| {"file": "amba3-vip/pkg_amba3_axi_probe.svh", "target_type": "expression", "cursor_line": 143, "target_nlines": 1, "node_depth": 9, "node_path": ["ERROR", "ERROR", "expression", "primary", "function_subroutine_call", "subroutine_call", "method_call", "method_call_body", "list_of_arguments_parent", "expression"], "target": " raddr_q.put(tx);\n"} |
| {"file": "amba3-vip/pkg_amba3_axi_slave.svh", "target_type": "primary", "cursor_line": 114, "target_nlines": 1, "node_depth": 9, "node_path": ["ERROR", "ERROR", "expression", "primary", "function_subroutine_call", "subroutine_call", "tf_call", "list_of_arguments_parent", "expression", "primary"], "target": " fill_q(wdata_q, waddr_q);\n"} |
| {"file": "amba3-vip/pkg_amba3_axi_tx.svh", "target_type": "function_statement", "cursor_line": 102, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement"], "target": " upper_byte_lane += (number_bytes - 1);\n"} |
| {"file": "amba3-vip/pkg_amba3_axi_tx_fixed.svh", "target_type": "primary", "cursor_line": 59, "target_nlines": 1, "node_depth": 17, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "class_constructor_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "blocking_assignment", "operator_assignment", "expression", "primary", "assignment_pattern_expression", "assignment_pattern", "expression", "primary"], "target": " lock : NORMAL,\n"} |
| {"file": "amba3-vip/pkg_amba3_axi_tx_incr.svh", "target_type": "expression", "cursor_line": 52, "target_nlines": 1, "node_depth": 12, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "class_constructor_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "blocking_assignment", "operator_assignment", "expression"], "target": " this.txid = $urandom_range(0, (1 << TXID_BITS) - 1);\n"} |
| {"file": "amba3-vip/pkg_amba3_axi_tx_wrap.svh", "target_type": "expression", "cursor_line": 52, "target_nlines": 1, "node_depth": 24, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "class_constructor_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "simple_immediate_assert_statement", "expression", "expression", "primary", "mintypmax_expression", "expression", "expression", "primary", "mintypmax_expression", "expression", "expression", "primary", "mintypmax_expression", "expression", "expression"], "target": " assert ((addr & ((1 << BEAT_BASE) - 1)) == '0);\n"} |
| {"file": "amba3-vip/tb_amba3_apb.sv", "target_type": "simple_identifier", "cursor_line": 112, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "ERROR", "module_or_generate_item", "package_or_generate_item_declaration", "task_declaration", "task_body_declaration", "ERROR", "clockvar_expression", "clockvar", "simple_identifier"], "target": " master.ticks(random_delay());\n"} |
| {"file": "amba3-vip/tb_amba3_axi.sv", "target_type": "primary_literal", "cursor_line": 186, "target_nlines": 1, "node_depth": 20, "node_path": ["ERROR", "module_or_generate_item", "package_or_generate_item_declaration", "task_declaration", "task_body_declaration", "statement_or_null", "statement", "statement_item", "simple_immediate_assert_statement", "expression", "expression", "primary", "function_subroutine_call", "subroutine_call", "method_call", "primary", "select1", "bit_select1", "expression", "primary", "primary_literal"], "target": " assert (fixed_1b.data[2].strb == 16'h0040);\n"} |
| {"file": "axi_vip_master/agent/axi_m_agent.sv", "target_type": "data_type", "cursor_line": 17, "target_nlines": 1, "node_depth": 10, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "ERROR", "ERROR", "class_type", "parameter_value_assignment", "list_of_parameter_assignments", "ordered_parameter_assignment", "_ordered_parameter_assignment", "data_type"], "target": " axi_m_driver #(WIDTH, SIZE) drv;\n"} |
| {"file": "axi_vip_master/agent/axi_m_drv.sv", "target_type": "data_type", "cursor_line": 17, "target_nlines": 1, "node_depth": 10, "node_path": ["ERROR", "class_item", "class_property", "data_declaration", "data_type_or_implicit1", "data_type", "parameter_value_assignment", "list_of_parameter_assignments", "ordered_parameter_assignment", "_ordered_parameter_assignment", "data_type"], "target": " virtual interface axi_intf #(WIDTH, SIZE) intf;\n"} |
| {"file": "axi_vip_master/agent/axi_m_mon.sv", "target_type": "expression", "cursor_line": 19, "target_nlines": 1, "node_depth": 16, "node_path": ["ERROR", "class_item", "class_method", "class_constructor_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "blocking_assignment", "operator_assignment", "expression", "primary", "function_subroutine_call", "subroutine_call", "tf_call", "list_of_arguments_parent", "expression"], "target": " mon2sb_port = new(\"mon2sb_port\",this);\n"} |
| {"file": "axi_vip_master/agent/axi_m_seq.sv", "target_type": "data_type", "cursor_line": 13, "target_nlines": 1, "node_depth": 12, "node_path": ["ERROR", "class_type", "parameter_value_assignment", "list_of_parameter_assignments", "ordered_parameter_assignment", "_ordered_parameter_assignment", "data_type", "class_type", "parameter_value_assignment", "list_of_parameter_assignments", "ordered_parameter_assignment", "_ordered_parameter_assignment", "data_type"], "target": ") extends uvm_sequence#(axi_m_Sequence_Item#(WIDTH, SIZE));\n"} |
| {"file": "axi_vip_master/agent/axi_s_agent.sv", "target_type": "operator_assignment", "cursor_line": 21, "target_nlines": 1, "node_depth": 12, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "blocking_assignment", "operator_assignment"], "target": " drv = axi_s_driver#(WIDTH, SIZE)::type_id::create(\"drv\", this);\n"} |
| {"file": "axi_vip_master/agent/axi_s_drv.sv", "target_type": "port_identifier", "cursor_line": 21, "target_nlines": 1, "node_depth": 6, "node_path": ["ERROR", "class_item", "class_method", "class_constructor_declaration", "tf_port_list", "tf_port_item1", "port_identifier"], "target": " function new(string name=\"axi_s_driver\",uvm_component parent);\n"} |
| {"file": "axi_vip_master/agent/my_seq_item.sv", "target_type": "variable_decl_assignment", "cursor_line": 40, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_property", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment"], "target": " rand logic [(WIDTH/8)-1:0] ARID;\n"} |
| {"file": "axi_vip_master/agent/my_sqncr.sv", "target_type": "simple_identifier", "cursor_line": 6, "target_nlines": 1, "node_depth": 6, "node_path": ["source_file", "package_or_generate_item_declaration", "data_declaration", "package_import_declaration", "package_import_item", "package_identifier", "simple_identifier"], "target": "import uvm_pkg::*;\n"} |
| {"file": "axi_vip_master/env/axi_env.sv", "target_type": "data_type", "cursor_line": 11, "target_nlines": 1, "node_depth": 10, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "ERROR", "ERROR", "class_type", "parameter_value_assignment", "list_of_parameter_assignments", "ordered_parameter_assignment", "_ordered_parameter_assignment", "data_type"], "target": " `uvm_component_param_utils(axi_Environment#(WIDTH, SIZE))\n"} |
| {"file": "axi_vip_master/env/axi_sb.sv", "target_type": "operator_assignment", "cursor_line": 56, "target_nlines": 1, "node_depth": 12, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "blocking_assignment", "operator_assignment"], "target": " drv2sb_export_drv = new(\"drv2sb_export_drv\", this);\n"} |
| {"file": "axi_vip_master/env/axi_subscriber.sv", "target_type": "primary_literal", "cursor_line": 62, "target_nlines": 1, "node_depth": 10, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "ERROR", "ERROR", "variable_lvalue", "select1", "bit_select1", "expression", "primary", "primary_literal"], "target": " bins arlen[3] = {[0:$]};\n"} |
| {"file": "axi_vip_master/interface/my_interface.sv", "target_type": "packed_dimension", "cursor_line": 52, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "interface_declaration", "interface_or_generate_item", "package_or_generate_item_declaration", "data_declaration", "data_type_or_implicit1", "data_type", "packed_dimension"], "target": " logic [WIDTH-1:0] RDATA;\n"} |
| {"file": "axi_vip_master/rtl/axi_slave_dut.sv", "target_type": "case_statement", "cursor_line": 280, "target_nlines": 4, "node_depth": 14, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " read_burst_next = s_axi_arburst;\n\n s_axi_arready_next = 1'b0;\n read_state_next = READ_STATE_BURST;\n"} |
| {"file": "axi_vip_master/top/axi_test.sv", "target_type": "simple_identifier", "cursor_line": 32, "target_nlines": 1, "node_depth": 19, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_property", "data_declaration", "data_type_or_implicit1", "data_type", "class_type", "parameter_value_assignment", "list_of_parameter_assignments", "ordered_parameter_assignment", "_ordered_parameter_assignment", "mintypmax_expression", "expression", "primary", "primary_literal", "simple_text_macro_usage", "text_macro_identifier", "simple_identifier"], "target": " axi_Environment #(`WIDTH, `SIZE) env;\n"} |
| {"file": "axi_vip_master/top/axi_top.sv", "target_type": "module_declaration", "cursor_line": 27, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " .clk (intf.clk),\n .s_axi_wdata (intf.WDATA),\n .s_axi_wstrb (intf.WSTRB),\n .s_axi_wvalid (intf.WVALID),\n"} |
| {"file": "axi_vip_master/top/tb_top.sv", "target_type": "simple_identifier", "cursor_line": 22, "target_nlines": 1, "node_depth": 6, "node_path": ["source_file", "package_or_generate_item_declaration", "data_declaration", "package_import_declaration", "package_import_item", "package_identifier", "simple_identifier"], "target": "import uvm_pkg::*;\n"} |
| {"file": "hdmi/src/audio_clock_regeneration_packet.sv", "target_type": "module_declaration", "cursor_line": 12, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input logic clk_audio,\n"} |
| {"file": "hdmi/src/audio_info_frame.sv", "target_type": "module_declaration", "cursor_line": 6, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "#(\n parameter bit [2:0] AUDIO_CHANNEL_COUNT = 3'd1, // 2 channels. See CEA-861-D table 17 for details.\n parameter bit [7:0] CHANNEL_ALLOCATION = 8'h00, // Channel 0 = Front Left, Channel 1 = Front Right (0-indexed)\n parameter bit DOWN_MIX_INHIBITED = 1'b0, // Permitted or no information about any assertion of this. The DM_INH field is to be set only for DVD-Audio applications.\n"} |
| {"file": "hdmi/src/audio_sample_packet.sv", "target_type": "module_declaration", "cursor_line": 86, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " aligned_frame_counter[i] = 8'(frame_counter + i - CHANNEL_STATUS_LENGTH);\n else\n aligned_frame_counter[i] = 8'(frame_counter + i);\n end\n assign header[23 - (3-i)] = aligned_frame_counter[i] == 8'd0 && audio_sample_word_present[i];\n"} |
| {"file": "hdmi/src/auxiliary_video_information_info_frame.sv", "target_type": "module_declaration", "cursor_line": 12, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " parameter bit [1:0] PICTURE_ASPECT_RATIO = 2'b00, // No data, See CEA-CEB16 for more information about Active Format Description processing.\n parameter bit [3:0] ACTIVE_FORMAT_ASPECT_RATIO = 4'b1000, // Not valid unless ACTIVE_FORMAT_INFO_PRESENT = 1'b1, then Same as picture aspect ratio\n"} |
| {"file": "hdmi/src/hdmi.sv", "target_type": "expression", "cursor_line": 253, "target_nlines": 1, "node_depth": 26, "node_path": ["source_file", "module_declaration", "generate_region", "module_or_generate_item", "if_generate_construct", "generate_block", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "nonblocking_assignment", "expression"], "target": " video_preamble <= 0;\n"} |
| {"file": "hdmi/src/packet_assembler.sv", "target_type": "module_declaration", "cursor_line": 6, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input logic reset,\n input logic data_island_period,\n input logic [23:0] header, // See Table 5-8 Packet Types\n input logic [55:0] sub [3:0],\n"} |
| {"file": "hdmi/src/packet_picker.sv", "target_type": "module_declaration", "cursor_line": 156, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " if (reset || video_field_end)\n begin\n audio_info_frame_sent <= 1'b0;\n"} |
| {"file": "hdmi/src/serializer.sv", "target_type": "primary_literal", "cursor_line": 146, "target_nlines": 1, "node_depth": 8, "node_path": ["ERROR", "event_expression", "expression", "primary", "select1", "bit_select1", "expression", "primary", "primary_literal"], "target": " .Q( tmds[ 2 ] ),\n"} |
| {"file": "hdmi/src/source_product_description_info_frame.sv", "target_type": "module_declaration", "cursor_line": 60, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " assign sub[i] = {packet_bytes[6 + i*7], packet_bytes[5 + i*7], packet_bytes[4 + i*7], packet_bytes[3 + i*7], packet_bytes[2 + i*7], packet_bytes[1 + i*7], packet_bytes[0 + i*7]};\n end\nendgenerate\n\nendmodule\n"} |
| {"file": "hdmi/src/tmds_channel.sv", "target_type": "case_statement", "cursor_line": 126, "target_nlines": 4, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " 4'b1001 : terc4_coding = 10'b0100111001;\n 4'b1010 : terc4_coding = 10'b0110011100;\n 4'b1011 : terc4_coding = 10'b1011000110;\n 4'b1100 : terc4_coding = 10'b1010001110;\n"} |
| {"file": "hdmi/test/audio_clock_tb/audio_clock_tb.sv", "target_type": "module_declaration", "cursor_line": 23, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " $finish;\nend\n"} |
| {"file": "hdmi/test/audio_param_tb/audio_param_tb.sv", "target_type": "module_declaration", "cursor_line": 1, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "module audio_param_tb ();\n"} |
| {"file": "hdmi/test/spd_tb/spd_tb.sv", "target_type": "module_declaration", "cursor_line": 3, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "module spd_tb();\n\nlogic [55:0] sub [3:0];\n\nsource_product_description_info_frame #(\n"} |
| {"file": "hdmi/test/top_tb/pll.sv", "target_type": "module_declaration", "cursor_line": 21, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "end\n\nalways\nbegin\n\t#20833333ps c2 = 1;\n"} |
| {"file": "hdmi/test/top_tb/top_tb.sv", "target_type": "primary_literal", "cursor_line": 42, "target_nlines": 1, "node_depth": 31, "node_path": ["ERROR", "generate_region", "interface_or_generate_item", "loop_generate_construct", "generate_block", "continuous_assign", "list_of_net_assignments", "net_assignment", "expression", "conditional_expression", "cond_predicate", "expression", "conditional_expression", "cond_predicate", "expression", "conditional_expression", "cond_predicate", "expression", "conditional_expression", "cond_predicate", "expression", "conditional_expression", "cond_predicate", "expression", "conditional_expression", "cond_predicate", "expression", "conditional_expression", "expression", "expression", "primary", "primary_literal"], "target": " : tmds_values[j] == 10'b0110011100 ? 4'b1010\n"} |
| {"file": "hdmi/top/top.sv", "target_type": "module_declaration", "cursor_line": 36, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " .screen_width(screen_width),\n"} |
| {"file": "nerv/axi_cache/axi_ram.v", "target_type": "case_statement", "cursor_line": 300, "target_nlines": 3, "node_depth": 14, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " s_axi_arready_next = 1'b1;\n\n if (s_axi_arready && s_axi_arvalid) begin\n"} |
| {"file": "nerv/axi_cache/nerv_axi_cache.sv", "target_type": "case_statement", "cursor_line": 792, "target_nlines": 3, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " axi_arlen = (LINE_WIDTH / AXI_DATA_WIDTH) - 1;\n read_state = R_DFETCH;\n end else begin\n"} |
| {"file": "nerv/axi_cache/nerv_axi_cache_dcache.sv", "target_type": "module_declaration", "cursor_line": 120, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " addr_t stable_addr, stable_addr_q;\n logic [DATA_WIDTH/8-1:0] stable_wstrb;\n logic [DATA_WIDTH/8-1:0] stable_wstrb_q;\n logic [DATA_WIDTH-1:0] stable_wdata;\n"} |
| {"file": "nerv/axi_cache/nerv_axi_cache_icache.sv", "target_type": "module_declaration", "cursor_line": 46, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " output var imem_fault,\n\n output var [ADDRESS_WIDTH-1:0] req_addr,\n output var req_valid,\n\n"} |
| {"file": "nerv/axi_cache/testbench_axi.sv", "target_type": "primary", "cursor_line": 326, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "program_instantiation", "hierarchical_instance", "list_of_port_connections", "named_port_connection", "expression", "primary"], "target": "\t.imem_addr(imem_addr),\n"} |
| {"file": "nerv/axi_cache/testbench_internal.sv", "target_type": "expression", "cursor_line": 59, "target_nlines": 1, "node_depth": 11, "node_path": ["source_file", "ERROR", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "nonblocking_assignment", "expression", "expression"], "target": "\t\tstall_counter <= stall_counter + 1;\n"} |
| {"file": "nerv/axi_cache/verify_axi.sv", "target_type": "module_declaration", "cursor_line": 3, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "module resetgen(input wire clock, input wire reset, input wire axi_arvalid, input wire axi_arready);\n initial assume(reset);\nendmodule\n"} |
| {"file": "nerv/axi_cache/wrapper_axi.sv", "target_type": "primary", "cursor_line": 158, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "module_instantiation", "hierarchical_instance", "list_of_port_connections", "named_port_connection", "expression", "primary"], "target": "\t\t.dmem_wdata(dmem_wdata),\n"} |
| {"file": "nerv/axi_cache/wrapper_internal.sv", "target_type": "module_declaration", "cursor_line": 190, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\t(* keep *) `rvformal_rand_reg next_dmem_res_r_valid;\n\t(* keep *) `rvformal_rand_reg next_dmem_res_r_fault;\n"} |
| {"file": "nerv/examples/icebreaker/testbench.sv", "target_type": "module_declaration", "cursor_line": 40, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "initial begin\n\tif ($test$plusargs(\"vcd\")) begin\n\t\t$dumpfile(\"testbench.vcd\");\n\t\t$dumpvars(0, testbench);\n"} |
| {"file": "nerv/examples/icebreaker/top.v", "target_type": "module_declaration", "cursor_line": 29, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": ");\n\n// Create reset signal 16 clocks long\nreg reset = 1'b1;\n"} |
| {"file": "nerv/imemcheck.sv", "target_type": "module_declaration", "cursor_line": 35, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\t(* keep *) wire [31:0] dmem_addr;\n\t(* keep *) wire [ 3:0] dmem_wstrb;\n\t(* keep *) wire [31:0] dmem_wdata;\n\n\twire [31:0] check_imem_addr;\n"} |
| {"file": "nerv/nerv.sv", "target_type": "primary", "cursor_line": 975, "target_nlines": 1, "node_depth": 6, "node_path": ["source_file", "package_or_generate_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "expression", "primary"], "target": "\t\t\t\t\t10'b 0000100_001 /* ZIP */: begin next_wr = insn[24:20] == 5'b 01111; illinsn = !next_wr; next_rd = 0; for (int i=0; i<16; i=i+1) begin next_rd[2*i] = rs1_value[i]; next_rd[2*i+1] = rs1_value[i+16]; end end\n"} |
| {"file": "nerv/nervsoc.sv", "target_type": "module_declaration", "cursor_line": 66, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\t\t.reset (reset ),\n\t\t.stall (stall ),\n"} |
| {"file": "nerv/testbench.sv", "target_type": "primary", "cursor_line": 39, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "ERROR", "module_or_generate_item", "package_or_generate_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "expression", "primary"], "target": "reg [31:0] irq = 'b0;\n"} |
| {"file": "nerv/wrapper.sv", "target_type": "simple_identifier", "cursor_line": 122, "target_nlines": 1, "node_depth": 6, "node_path": ["ERROR", "statement_or_null", "statement", "statement_item", "clocking_drive", "ERROR", "simple_identifier"], "target": "`ifdef NERV_FAULT\n"} |
| {"file": "axi4-interface/axi-interconnect/axi_lite_interconnect.sv", "target_type": "case_statement", "cursor_line": 152, "target_nlines": 2, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "\t\t\tREAD : next_state = (axibus_s[sel_s].r.valid && axibus_m[sel_m].r.ready) ? IDLE : READ;\n\t\t\tWRITE : next_state = (axibus_s[sel_s].b.valid && axibus_m[sel_m].b.ready) ? IDLE : WRITE;\n"} |
| {"file": "axi4-interface/axi4/axi_if.sv", "target_type": "port_identifier", "cursor_line": 50, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "interface_declaration", "modport_declaration", "modport_item", "modport_ports_declaration", "modport_simple_ports_declaration", "modport_simple_port", "port_identifier"], "target": "\t\tinput araddr, arvalid, output arready, input arlen, arsize, arburst,\n"} |
| {"file": "axi4-interface/axi4/axi_master.sv", "target_type": "case_statement", "cursor_line": 78, "target_nlines": 3, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "\t\t\tIDLE : next_state = (start_read_delay) ? RADDR : ((start_write_delay) ? WADDR : IDLE);\n\t\t\tRADDR : if (m_axi.arvalid && m_axi.arready) next_state = RDATA;\n\t\t\tRDATA : if (m_axi.rvalid && m_axi.rready && m_axi.rlast) next_state = IDLE;\n"} |
| {"file": "axi4-interface/axi4/axi_pkg.sv", "target_type": "data_type", "cursor_line": 29, "target_nlines": 1, "node_depth": 5, "node_path": ["source_file", "package_declaration", "package_or_generate_item_declaration", "data_declaration", "type_declaration", "data_type"], "target": "\ttypedef logic [2 : 0] size_t;\n"} |
| {"file": "axi4-interface/axi4/axi_slave.sv", "target_type": "case_statement", "cursor_line": 50, "target_nlines": 4, "node_depth": 22, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "\t\t\t\t\taddr <= s_axi.araddr;\n\t\t\t\t\tlen <= s_axi.arlen;\n\t\t\t\t\tsize <= s_axi.arsize;\n\t\t\t\t\tburst <= s_axi.arburst;\n"} |
| {"file": "axi4-interface/axi4-lite/axi_lite_if.sv", "target_type": "simple_identifier", "cursor_line": 6, "target_nlines": 1, "node_depth": 5, "node_path": ["source_file", "interface_declaration", "interface_or_generate_item", "package_or_generate_item_declaration", "net_declaration", "simple_identifier"], "target": "\taddr_t araddr;\n"} |
| {"file": "axi4-interface/axi4-lite/axi_lite_master.sv", "target_type": "module_declaration", "cursor_line": 52, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\t\tend else begin\n\t\t\tstart_read_delay <= start_read;\n\t\t\tstart_write_delay <= start_write;\n\t\tend\n"} |
| {"file": "axi4-interface/axi4-lite/axi_lite_pkg.sv", "target_type": "data_type", "cursor_line": 14, "target_nlines": 1, "node_depth": 5, "node_path": ["source_file", "package_declaration", "package_or_generate_item_declaration", "data_declaration", "type_declaration", "data_type"], "target": "\ttypedef logic [STRB_WIDTH - 1 : 0] strb_t;\n"} |
| {"file": "axi4-interface/axi4-lite/axi_lite_slave.sv", "target_type": "case_statement", "cursor_line": 58, "target_nlines": 5, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "\t\t\tIDLE : next_state = (s_axi_lite.arvalid) ? RADDR : (s_axi_lite.awvalid) ? WADDR : IDLE;\n\t\t\tRADDR : if (s_axi_lite.arvalid && s_axi_lite.arready) next_state = RDATA;\n\t\t\tRDATA : if (s_axi_lite.rvalid && s_axi_lite.rready ) next_state = IDLE;\n\t\t\tWADDR : if (s_axi_lite.awvalid && s_axi_lite.awready) next_state = WDATA;\n\t\t\tWDATA : if (s_axi_lite.wvalid && s_axi_lite.wready ) next_state = WRESP;\n"} |
| {"file": "axi4-interface/axi4-stream/axi_stream_if.sv", "target_type": "variable_decl_assignment", "cursor_line": 5, "target_nlines": 1, "node_depth": 6, "node_path": ["source_file", "interface_declaration", "interface_or_generate_item", "package_or_generate_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment"], "target": "\tlogic tvalid;\n"} |
| {"file": "axi4-interface/axi4-stream/axi_stream_master.sv", "target_type": "case_statement", "cursor_line": 40, "target_nlines": 5, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "\t\tcase (state)\n\t\t\tIDLE : if (start_delay) next_state = SEND;\n\t\t\tSEND : if (m_axi_stream.tlast) next_state = IDLE;\n\t\t\tdefault : next_state = IDLE;\n\t\tendcase\n"} |
| {"file": "axi4-interface/axi4-stream/axi_stream_pkg.sv", "target_type": "simple_identifier", "cursor_line": 5, "target_nlines": 1, "node_depth": 12, "node_path": ["source_file", "package_declaration", "package_or_generate_item_declaration", "data_declaration", "type_declaration", "data_type", "packed_dimension", "constant_range", "constant_expression", "constant_expression", "constant_primary", "parameter_identifier", "simple_identifier"], "target": "\ttypedef logic [DATA_WIDTH - 1 : 0] data_t;\n"} |
| {"file": "axi4-interface/axi4-stream/axi_stream_slave.sv", "target_type": "case_statement", "cursor_line": 29, "target_nlines": 5, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "\t\tcase (state)\n\t\t\tIDLE : next_state = RECV;\n\t\t\tRECV : next_state = RECV;\n\t\t\tdefault : next_state = IDLE;\n\t\tendcase\n"} |
| {"file": "axi4-interface/test/tb_axi.sv", "target_type": "module_declaration", "cursor_line": 44, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\t\t$finish;\n\tend\n\n"} |
| {"file": "axi4-interface/test/tb_axi_lite.sv", "target_type": "module_declaration", "cursor_line": 41, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\t\ttest_write();\n\t\ttest_read();\n"} |
| {"file": "axi4-interface/test/tb_axi_lite_interconnect.sv", "target_type": "module_declaration", "cursor_line": 90, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\tendtask : test_read\n\n"} |
| {"file": "axi4-interface/test/tb_axi_stream.sv", "target_type": "module_declaration", "cursor_line": 38, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\t\t$finish;\n\tend\n\n\n"} |
| {"file": "tech_cells_generic/src/deprecated/cluster_clk_cells.sv", "target_type": "module_declaration", "cursor_line": 26, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input logic clk_i,\n output logic clk_o\n);\n\n tc_clk_buffer i_tc_clk_buffer (\n"} |
| {"file": "tech_cells_generic/src/deprecated/cluster_pwr_cells.sv", "target_type": "module_declaration", "cursor_line": 46, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n assign out_o = in_i;\n\n"} |
| {"file": "tech_cells_generic/src/deprecated/generic_memory.sv", "target_type": "module_declaration", "cursor_line": 41, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " assign M[i*8+j] = BEN[i];\n end\n end\n endgenerate\n\n"} |
| {"file": "tech_cells_generic/src/deprecated/generic_rom.sv", "target_type": "module_declaration", "cursor_line": 20, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input logic [ADDR_WIDTH-1:0] A,\n output logic [DATA_WIDTH-1:0] Q\n"} |
| {"file": "tech_cells_generic/src/deprecated/pad_functional.sv", "target_type": "module_declaration", "cursor_line": 33, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " 1 0/1 1 0/1 | - 1\n"} |
| {"file": "tech_cells_generic/src/deprecated/pulp_buffer.sv", "target_type": "module_declaration", "cursor_line": 15, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": ");\n\n assign out_o = in_i;\n\n"} |
| {"file": "tech_cells_generic/src/deprecated/pulp_clk_cells.sv", "target_type": "module_declaration", "cursor_line": 67, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input logic clk0_i,\n input logic clk1_i,\n input logic clk_sel_i,\n output logic clk_o\n);\n"} |
| {"file": "tech_cells_generic/src/deprecated/pulp_clock_gating_async.sv", "target_type": "module_declaration", "cursor_line": 36, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n pulp_clock_gating i_clk_gate (\n .clk_i,\n .en_i ( r_reg[STAGES-1] ),\n .test_en_i,\n"} |
| {"file": "tech_cells_generic/src/deprecated/pulp_pwr_cells.sv", "target_type": "module_declaration", "cursor_line": 63, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " output logic sleepout_o\n);\n\n assign sleepout_o = sleep_i;\n"} |
| {"file": "tech_cells_generic/src/fpga/pad_functional_xilinx.sv", "target_type": "module_declaration", "cursor_line": 39, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n (* PULLUP = \"YES\" *)\n"} |
| {"file": "tech_cells_generic/src/fpga/tc_clk_xilinx.sv", "target_type": "module_declaration", "cursor_line": 47, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " assign clk_o = clk_i;\n"} |
| {"file": "tech_cells_generic/src/fpga/tc_sram_xilinx.sv", "target_type": "module_declaration", "cursor_line": 216, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " end\n\n`endif\n`endif\n// pragma translate_on\n"} |
| {"file": "tech_cells_generic/src/rtl/tc_clk.sv", "target_type": "module_declaration", "cursor_line": 16, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n assign clk_o = clk0_i & clk1_i;\n\nendmodule\n"} |
| {"file": "tech_cells_generic/src/rtl/tc_sram.sv", "target_type": "case_statement", "cursor_line": 95, "target_nlines": 5, "node_depth": 18, "node_path": ["ERROR", "module_or_generate_item", "initial_construct", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "loop_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " \"zeros\": init_val[i] = {DataWidth{1'b0}};\n \"ones\": init_val[i] = {DataWidth{1'b1}};\n \"random\": init_val[i] = {DataWidth{$urandom()}};\n default: init_val[i] = {DataWidth{1'bx}};\n endcase\n"} |
| {"file": "tech_cells_generic/src/rtl/tc_sram_impl.sv", "target_type": "module_declaration", "cursor_line": 47, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input logic rst_ni, // Asynchronous reset active low\n // implementation-related IO\n"} |
| {"file": "tech_cells_generic/src/tc_pwr.sv", "target_type": "module_declaration", "cursor_line": 84, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input logic ena_i,\n output logic data_o\n);\n\n assign data_o = ena_i ? data_i : 1'b0;\n"} |
| {"file": "tech_cells_generic/test/tb_tc_sram.sv", "target_type": "simple_identifier", "cursor_line": 96, "target_nlines": 1, "node_depth": 24, "node_path": ["ERROR", "module_or_generate_item", "loop_generate_construct", "generate_block", "interface_or_generate_item", "initial_construct", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "loop_statement", "statement_or_null", "statement", "statement_item", "seq_block", "ERROR", "clockvar_expression", "select1", "bit_select1", "expression", "primary", "simple_identifier"], "target": " addr[i] <= #ApplTime stim_addr;\n"} |
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