Datasets:

OvertureMMXXI
/

HDL-RepoBench-Sample

	{"task_id": "CGRAs", "path": "CGRAs/src/main/scala/Alu.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ****************************************/\nimport chisel3._\n\nobject operations\n{\n def SUM = 0.U // Summation \n def MUL = 1.U // Multiplication\n def SUB = 2.U // Subtraction\n def SLL = 3.U // Shift Left Logical\n def SRA = 4.U // Shift Right Arithmetic\n def SRL = 5.U // Shift Right Logical\n", "right_context": " def OR = 7.U // Or\n def XOR = 8.U // Xor \n def DIV = 9.U // Div (NOT IMPLEMENTED)\n def MIN = 10.U // Minimum (NOT IMPLEMENTED)\n def MAX = 11.U // Maximum (NOT IMPLEMENTED)\n}\n \nimport operations._\n \nclass Alu \n (\n dataWidth: Int, \n opWidth: Int\n )\n extends Module {\n val io = IO(new Bundle {\n val din1 = Input(SInt(dataWidth.W))\n val din2 = Input(SInt(dataWidth.W))\n val dout = Output(SInt(dataWidth.W))\n val opConfig = Input(UInt(opWidth.W))\n })\n // Result \n val outAux = Wire(SInt((dataWidth).W))\n\n when (io.opConfig === SUM) { // SUM\n outAux := io.din1 + io.din2 \n }\n .elsewhen (io.opConfig === MUL) { // MUL\n outAux := io.din1 io.din2 \n } \n .elsewhen (io.opConfig === SUB) { // SUB\n outAux := io.din1 - io.din2 \n }\n .elsewhen (io.opConfig === SLL) { // SLL\n outAux := io.din1 << (io.din2(18, 0)).asUInt\n } \n .elsewhen (io.opConfig === SRA) { // SRA\n outAux := io.din1 >> io.din2.asUInt\n } \n .elsewhen (io.opConfig === SRL) { // SRL\n outAux := (io.din1.asUInt >> io.din2.asUInt).asSInt \n }\n .elsewhen (io.opConfig === AND) { // AND\n outAux := io.din1 & io.din2 \n } \n .elsewhen (io.opConfig === OR) { // OR\n outAux := io.din1 \| io.din2 \n } \n .elsewhen (io.opConfig === XOR) { // XOR\n outAux := io.din1 ^ io.din2 \n } \n .otherwise { \n outAux := 0.S // Default \n }\n \n io.dout := outAux\n}\n\n// Generate the Verilog code\nobject AluMain extends App {\n println(\"Generating the hardware\")\n (new chisel3.stage.ChiselStage).emitVerilog(new Alu(32, 5), Array(\"--target-dir\", \"generated\"))\n}", "groundtruth": " def AND = 6.U // And \n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/main/scala/CellProcessing.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n *****************************************/\nimport chisel3._\nimport chisel3.util._\n\nclass CellProcessing \n (\n dataWidth: Int\n ) \n extends Module {\n val io = IO(new Bundle {\n val northDin = Input(SInt(dataWidth.W))\n val northDinValid = Input(Bool())\n val eastDin = Input(SInt(dataWidth.W))\n val eastDinValid = Input(Bool())\n val southDin = Input(SInt(dataWidth.W))\n val southDinValid = Input(Bool())\n val westDin = Input(SInt(dataWidth.W))\n val westDinValid = Input(Bool())\n val fuDin1Ready = Output(Bool()) \n val fuDin2Ready = Output(Bool()) \n val dout = Output(SInt(dataWidth.W))\n val doutValid = Output(Bool()) \n val northDoutReady = Input(Bool())\n val eastDoutReady = Input(Bool())\n val southDoutReady = Input(Bool())\n val westDoutReady = Input(Bool())\n val configBits = Input(UInt(182.W))\n })\n // Config signals\n val selectorMux1 = Wire(UInt(3.W))\n val selectorMux2 = Wire(UInt(3.W))\n val forkReceiverMask1 = Wire(UInt(4.W))\n val forkReceiverMask2 = Wire(UInt(4.W))\n val opConfig = Wire(UInt(5.W))\n val forkSenderMask = Wire(UInt(5.W))\n val I1CONST = Wire(UInt(dataWidth.W))\n val initialVaueLoad = Wire(UInt(dataWidth.W))\n val iterationsResetLoad = Wire(UInt(16.W))\n val fifoLengthLoad = Wire(UInt(16.W))\n val loadInitialValue = Wire(UInt(2.W))\n val fuDout = Wire(SInt(dataWidth.W))\n val ebDin1 = Wire(SInt(dataWidth.W))\n val ebDin2 = Wire(SInt(dataWidth.W))\n val joinDin1 = Wire(SInt(dataWidth.W))\n val joindin2 = Wire(SInt(dataWidth.W))\n val joinDout1 = Wire(SInt(dataWidth.W))\n val joinDout2 = Wire(SInt(dataWidth.W))\n val fuDoutValid = Wire(Bool())\n val fuDoutReady = Wire(Bool())\n val ebDin1Valid = Wire(Bool())\n val ebDin2Valid = Wire(Bool())\n val joinDin1Valid = Wire(Bool())\n val joinDin1Ready = Wire(Bool())\n val joinDin2Valid = Wire(Bool())\n val joinDin2Ready = Wire(Bool())\n val joinDoutValid = Wire(Bool())\n val joinDoutReady = Wire(Bool())\n val forkedDoutReady = Wire(Bool())\n\n // Configuration bits arrangement\n selectorMux1 := io.configBits(2, 0) \n selectorMux2 := io.configBits(5, 3)\n forkReceiverMask1 := io.configBits(17, 14)\n // 2 fill bits (19 , 18)\n forkReceiverMask2 := io.configBits(23, 20)\n // structure conf\n opConfig := io.configBits(48, 44)\n // 3 fill bits (50 , 48)\n forkSenderMask := io.configBits(56, 52)\n // structure conf\n I1CONST := io.configBits(115, 84)\n initialVaueLoad := io.configBits(147, 116) \n fifoLengthLoad := io.configBits(163, 148)\n iterationsResetLoad := io.configBits(179, 164)\n loadInitialValue := io.configBits(181, 180)\n\n val fr1 = Module (new Fr(6, 4))\n val readyfr1 = Cat(io.northDoutReady, io.eastDoutReady, io.southDoutReady, io.westDoutReady) \n val validInfr1 = Cat(fuDoutValid.asUInt, \"b1\".U, io.westDinValid, io.southDinValid, io.eastDinValid, io.northDinValid) \n fr1.io.readyOut := readyfr1\n fr1.io.validIn := validInfr1\n fr1.io.validMuxSel := selectorMux1\n fr1.io.forkMask := forkReceiverMask1 \n ebDin1Valid := fr1.io.validOut \n\n val mux1 = Module (new ConfMux(6, dataWidth))\n mux1.io.selector := selectorMux1\n mux1.io.muxInput := (Cat(fuDout, I1CONST, io.westDin, io.southDin, io.eastDin, io.northDin)).asSInt\n ebDin1 := mux1.io.muxOutput\n\n val eb1 = Module (new DEb(dataWidth))\n eb1.io.din := ebDin1\n eb1.io.dinValid := ebDin1Valid\n io.fuDin1Ready := eb1.io.dinReady \n joinDin1 := eb1.io.dout \n joinDin1Valid := eb1.io.doutValid \n eb1.io.doutReady := joinDin1Ready\n\n val fr2 = Module (new Fr(6, 4))\n val ready_fr2 = Cat(io.northDoutReady, io.eastDoutReady, io.southDoutReady, io.westDoutReady) \n val validIn_fr2 = Cat(fuDoutValid.asUInt, \"b1\".U, io.westDinValid, io.southDinValid, io.eastDinValid, io.northDinValid) \n fr2.io.readyOut := ready_fr2\n fr2.io.validIn := validIn_fr2\n fr2.io.validMuxSel := selectorMux2\n fr2.io.forkMask := forkReceiverMask2 \n ebDin2Valid := fr2.io.validOut \n\n val mux2 = Module (new ConfMux(6, dataWidth))\n mux2.io.selector := selectorMux2\n mux2.io.muxInput := (Cat(fuDout, I1CONST, io.westDin, io.southDin, io.eastDin, io.northDin)).asSInt \n ebDin2 := mux2.io.muxOutput\n\n val eb2 = Module (new DEb(dataWidth))\n eb2.io.din := ebDin2\n eb2.io.dinValid := ebDin2Valid\n io.fuDin2Ready := eb2.io.dinReady \n joindin2 := eb2.io.dout \n", "right_context": " eb2.io.doutReady := joinDin2Ready \n\n val joinInst = Module (new Join(dataWidth))\n joinInst.io.din1 := joinDin1\n joinInst.io.din2 := joindin2 \n joinInst.io.doutReady := joinDoutReady\n joinInst.io.din1Valid := joinDin1Valid\n joinInst.io.din2Valid := joinDin2Valid\n\n joinDoutValid := joinInst.io.doutValid \n joinDin1Ready := joinInst.io.din1Ready \n joinDin2Ready := joinInst.io.din2Ready \n joinDout1 := joinInst.io.dout1\n joinDout2 := joinInst.io.dout2\n\n val fuInst = Module (new Fu(dataWidth, 5))\n fuInst.io.din1 := joinDout1\n fuInst.io.din2 := joinDout2\n fuInst.io.dinValid := joinDoutValid\n joinDoutReady := fuInst.io.dinReady \n fuInst.io.loopSource := loadInitialValue\n fuInst.io.iterationsReset := iterationsResetLoad \n fuInst.io.opConfig := opConfig \n fuDout := fuInst.io.dout \n fuDoutValid := fuInst.io.doutValid\n \n fuInst.io.doutReady := fuDoutReady\n\n val ebOut = Module (new DEb(dataWidth))\n ebOut.io.din := fuDout\n ebOut.io.dinValid := fuDoutValid\n ebOut.io.din := fuInst.io.dout \n ebOut.io.dinValid := fuInst.io.doutValid\n\n fuDoutReady := ebOut.io.dinReady\n io.dout := ebOut.io.dout \n io.doutValid := ebOut.io.doutValid \n ebOut.io.doutReady := forkedDoutReady\n\n val fs = Module (new Fs(5))\n val readyOutFs = Cat(\"b1\".U, io.northDoutReady, io.eastDoutReady, io.southDoutReady, io.westDoutReady) \n fs.io.readyOut := readyOutFs\n forkedDoutReady := fs.io.readyIn\n fs.io.forkMask := forkSenderMask\n}\n\n// Generate the Verilog code\nobject CellProcessingMain extends App {\n println(\"Generating the hardware\")\n (new chisel3.stage.ChiselStage).emitVerilog(new CellProcessing(32), Array(\"--target-dir\", \"generated\"))\n}", "groundtruth": " joinDin2Valid := eb2.io.doutValid\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/main/scala/ConfMux.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ***************************************/\n\n/\n * Multiplexer module that separates a series of input data based on the provided parameters.\n * numInput: The number of inputs to the multiplexer.\n * muxInput: The input data to be separated. Each input is assumed to be of equal size.\n * selector: The index to select the output from the separated input data.\n * muxOutput: The selected output based on the provided selector.\n * Example:\n * If `numInput` is 2 and each input data is 8 bits the multiplexer separates it \n * into 2 separate data, each containing 4 bits. If `selector` is 0, it returns the first 4 bits.\n */\n\nimport chisel3._\nimport chisel3.util._\n\nclass ConfMux \n (\n numInputs: Int = 2, \n dataWidth: Int = 1\n )\n extends Module {\n val io = IO(new Bundle { \n val selector = Input(UInt(log2Ceil(numInputs).W))\n val muxInput = Input(SInt((numInputsdataWidth).W))\n val muxOutput = Output(SInt(dataWidth.W))\n })\n \n val inputs = Wire(Vec(numInputs, SInt(dataWidth.W))) \n\n for (i <- 0 until numInputs) {\n inputs(i) := (io.muxInput((i+1)dataWidth-1,idataWidth)).asSInt\n }\n io.muxOutput := inputs(io.selector)\n}\n\n// Generate the Verilog code\n", "right_context": "", "groundtruth": "object ConfMuxMain extends App {\n println(\"Generating the hardware\")\n (new chisel3.stage.ChiselStage).emitVerilog(new ConfMux(2, 1), Array(\"--target-dir\", \"generated\"))\n}\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/main/scala/DEb.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ***************************************/\n\n/\n * The Elastic Buffer operates as a 2-slot FIFO, utilizing latches or flip-flops for implementation. \n * When EBs are adjacent, they synchronize data transfer (D) through a set of control signals: \n * a forward data-presence valid signal (V) indicating the presence of data or emptiness within the EB, \n * and a back-propagating stall/accept (A) signal, indicating if the EB is stalled or ready to receive new data. \n * A generalized EB extends this concept to an N-slot FIFO, typically realized through RAM implementation.\n **/\n\nimport chisel3._\nimport chisel3.util._\n\nclass DEb \n (\n dataWidth: Int\n )\n extends Module {\n val io = IO(new Bundle {\n val din = Input(SInt(dataWidth.W))\n val dinValid = Input(Bool())\n val dinReady = Output(Bool())\n val dout = Output(SInt(dataWidth.W))\n val doutValid = Output(Bool())\n val doutReady = Input(Bool()) \n })\n\n val regDin1 = RegInit(0.S(dataWidth.W))\n val regDin2 = RegInit(0.S(dataWidth.W))\n val regDinValid1 = RegInit(0.B)\n val regDinValid2 = RegInit(0.B)\n val regAreg = RegInit(0.B)\n\n when(regAreg) {\n regDin1 := io.din\n regDin2 := regDin1\n \n regDinValid1 := io.dinValid\n regDinValid2 := regDinValid1\n }\n\n regAreg := ~io.doutValid \| io.doutReady\n\n // Combinational assignments\n io.dinReady := regAreg\n\n when(regAreg) {\n", "right_context": " io.doutValid := regDinValid1\n }.otherwise {\n io.dout := regDin2\n io.doutValid := regDinValid2\n }\n}\n \n// Generate the Verilog code\nobject DEbMain extends App {\n println(\"Generating the hardware\")\n (new chisel3.stage.ChiselStage).emitVerilog(new DEb(32), Array(\"--target-dir\", \"generated\"))\n}\n", "groundtruth": " io.dout := regDin1\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/main/scala/DFifo.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n *****************************************/\nimport chisel3._\nimport chisel3.util._\nimport chisel3.stage.PrintFullStackTraceAnnotation\n\n", "right_context": " (\n dataWidth: Int, \n fifoDepth: Int\n ) \n extends Module {\n val io = IO(new Bundle {\n val din = Input(SInt(dataWidth.W)) \n val dinValid = Input(Bool())\n val doutReady = Input(Bool())\n val dinReady = Output(Bool())\n val dout = Output(SInt(dataWidth.W)) \n val doutValid = Output(Bool()) \n })\n\n val fifo = Module(new DFifoImp(dataWidth, fifoDepth))\n fifo.io.clock := clock\n fifo.io.reset := reset.asBool \n fifo.io.din := io.din \n fifo.io.dinValid := io.dinValid\n fifo.io.doutReady := io.doutReady\n io.dinReady := fifo.io.dinReady\n io.dout := fifo.io.dout \n io.doutValid := fifo.io.doutValid \n}\n\n// Generate the Verilog code\nobject DFifoMain extends App {\n println(\"Generating the hardware\")\n (new chisel3.stage.ChiselStage).emitVerilog(new DFifo(32, 32), Array(\"--target-dir\", \"generated\"))\n}", "groundtruth": "class DFifo\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/main/scala/DFifoImp.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n *****************************************/\nimport chisel3._\nimport chisel3.util._\nimport chisel3.util.HasBlackBoxResource\nimport chisel3.experimental.{IntParam, BaseModule}\n\nclass DFifoImp\n (\n dataWidth: Int, \n fifoDepth: Int\n ) \n", "right_context": " val reset = Input(Bool())\n val din = Input(SInt(dataWidth.W)) \n val dinValid = Input(Bool())\n val doutReady = Input(Bool())\n val dinReady = Output(Bool())\n val dout = Output(SInt(dataWidth.W)) \n val doutValid = Output(Bool()) \n })\n\n addResource(\"vsrc/DFifoImp.v\")\n}", "groundtruth": " extends BlackBox(Map(\"dataWidth\" -> dataWidth, \"fifoDepth\" -> fifoDepth)) with HasBlackBoxResource{ \n val io = IO(new Bundle {\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/main/scala/DReg.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n *****************************************/\nimport chisel3._\nimport chisel3.util._\n\nclass DReg\n (\n dataWidth: Int\n )\n extends Module {\n val io = IO(new Bundle {\n val din = Input(SInt(dataWidth.W))\n val dinValid = Input(Bool())\n val doutReady = Input(Bool())\n val dout = Output(SInt(dataWidth.W))\n val doutValid = Output(Bool())\n val dinReady = Output(Bool()) \n })\n\n val data = RegInit(0.S(dataWidth.W))\n val valid = RegInit(0.B)\n\n data := 0.S \n valid := false.B \n \n", "right_context": "}\n\n// Generate the Verilog code\nobject DRegMain extends App {\n println(\"Generating the hardware\")\n (new chisel3.stage.ChiselStage).emitVerilog(new DReg(8), Array(\"--target-dir\", \"generated\"))\n}", "groundtruth": " when (io.doutReady === true.B) {\n data := io.din\n valid := io.dinValid\n } \n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/main/scala/Fr.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n *****************************************/\nimport chisel3._\nimport chisel3.util._\n\n", "right_context": " (\n numberOfValids: Int, \n numberOfReadys: Int\n ) \n extends Module {\n val io = IO(new Bundle {\n val validIn = Input(UInt(numberOfValids.W))\n val readyOut = Input(UInt(numberOfReadys.W))\n val validMuxSel = Input(UInt((log2Ceil(numberOfValids).W)))\n val forkMask = Input(UInt(numberOfReadys.W))\n val validOut = Output(Bool()) \n })\n // All wires \n val aux = Wire(Vec(numberOfReadys+1, Bool()))\n val temp = Wire(Vec(numberOfReadys+1, Bool()))\n val vaux = Wire(SInt(1.W))\n\n for (i <- 0 until numberOfReadys) {\n aux(i) := ((~io.forkMask(i)) \| io.readyOut(i)).asBool\n }\n val confMux = Module (new ConfMux(numberOfValids, 1))\n confMux.io.selector := io.validMuxSel\n confMux.io.muxInput := (io.validIn).asSInt \n vaux := confMux.io.muxOutput\n\n aux(numberOfReadys) := vaux(0).asBool \n temp(0) := aux(0)\n\n for (i <- 1 until numberOfReadys+1) {\n temp(i) := temp(i-1) & aux(i)\n }\n io.validOut := temp(numberOfReadys) \n}\n\n// Generate the Verilog code\nobject FrMain extends App {\n println(\"Generating the hardware\")\n (new chisel3.stage.ChiselStage).emitVerilog(new Fr(5, 5), Array(\"--target-dir\", \"generated\"))\n}", "groundtruth": "class Fr \n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/main/scala/Fs.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ***************************************/\n\n/\n * The Fork Sender's responsibility is to verify the readiness of all potential destinations \n * for the input data. The AND gate in this block ensures that the valid signal is asserted only \n * when the Fork Sender confirms that all receivers are available.\n **/\n\nimport chisel3._\nimport chisel3.util._\n\nclass Fs \n (\n numberOfReadys: Int\n )\n extends Module {\n val io = IO(new Bundle {\n val readyOut = Input(UInt(numberOfReadys.W))\n val forkMask = Input(UInt(numberOfReadys.W))\n val readyIn = Output(Bool()) \n })\n \n val aux = Wire(Vec(numberOfReadys, Bool()))\n val temp = Wire(Vec(numberOfReadys, Bool()))\n\n for (i <- 0 until numberOfReadys) {\n aux(i) := ((~io.forkMask(i)) \| io.readyOut(i)).asBool\n }\n\n temp(0) := aux(0) \n\n for (i <- 1 until numberOfReadys) {\n temp(i) := temp(i-1) & aux(i)\n }\n io.readyIn := temp(numberOfReadys - 1).asBool \n}\n\n// Generate the Verilog code\n", "right_context": "", "groundtruth": "object FsMain extends App {\n println(\"Generating the hardware\")\n (new chisel3.stage.ChiselStage).emitVerilog(new Fs(5), Array(\"--target-dir\", \"generated\"))\n} \n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/main/scala/Fu.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ***************************************/\n\n/\n * An FU is a circuit that executes the operation of a data flow graph node. \n * The FU executes an operation only when its inputs are ready and when its output is free.\n **/\n\nimport chisel3._\nimport chisel3.util._\n\nobject states\n{\n", "right_context": " def STATE_1 = 1.U(2.W) // 01\n def STATE_2 = 2.U(2.W) // 10\n def STATE_3 = 3.U(2.W) // 11\n}\n\nimport states._\n\nclass Fu\n (\n dataWidth: Int, \n opWidth: Int\n )\n extends Module {\n val io = IO(new Bundle {\n val din1 = Input(SInt(dataWidth.W))\n val din2 = Input(SInt(dataWidth.W))\n val dinValid = Input(Bool())\n val doutReady = Input(Bool())\n val loopSource = Input(UInt(2.W))\n val iterationsReset = Input(UInt(16.W))\n val opConfig = Input(UInt(opWidth.W))\n val dinReady = Output(Bool())\n val dout = Output(SInt(dataWidth.W))\n val doutValid = Output(Bool()) \n })\n\n val aluDin1 = Wire(SInt(dataWidth.W))\n val aluDin2 = Wire(SInt(dataWidth.W))\n \n val aluDout = Wire(SInt(dataWidth.W))\n\n val doutReg = RegInit(0.S(dataWidth.W))\n val count = RegInit(0.U(16.W))\n val loaded = RegInit(0.U(1.W))\n\n //val valid = RegInit(0.U(1.W))\n val valid = Wire(Bool()) \n\n val alu = Module (new Alu(dataWidth, opWidth))\n alu.io.din1 := aluDin1\n alu.io.din2 := aluDin2\n aluDout := alu.io.dout \n alu.io.opConfig := io.opConfig\n \n when (io.loopSource === STATE_0) {\n aluDin1 := io.din1\n aluDin2 := io.din2 \n }\n .elsewhen (io.loopSource === STATE_1) {\n when (loaded === 0.U) {\n aluDin1 := io.din1\n aluDin2 := io.din2 \n } \n .otherwise {\n aluDin1 := doutReg\n aluDin2 := io.din2 \n } \n } \n .elsewhen (io.loopSource === STATE_2) {\n when (loaded === 0.U) {\n aluDin1 := io.din1\n aluDin2 := io.din2 \n } \n .otherwise {\n aluDin1 := io.din1\n aluDin2 := doutReg \n } \n } \n .otherwise { \n aluDin1 := (dataWidth - 1).S\n aluDin2 := (dataWidth - 1).S\n }\n \n when (io.doutReady === 1.U) {\n valid := 0.U \n }.otherwise{\n valid := 1.U \n }\n \n when (io.dinValid === 1.U && io.doutReady === 1.U && \n (io.loopSource === STATE_1 \|\| io.loopSource === STATE_2)) {\n loaded := 1.U\n count := count + 1.U \n }\n \n when (count === io.iterationsReset && \n (io.loopSource === STATE_1 \|\| io.loopSource === STATE_2) && \n io.doutReady === 1.U){\n count := 0.U\n loaded := 0.U\n valid := 1.U \n doutReg := aluDout\n } \n .elsewhen ((io.loopSource === STATE_1 \|\| io.loopSource === STATE_2) && \n io.dinValid === 1.U && io.doutReady === 1.U){\n doutReg := aluDout\n } \n\n io.dinReady := io.doutReady\n\n when (io.loopSource === STATE_0){\n io.dout := aluDout\n io.doutValid := io.dinValid \n }\n .otherwise{\n io.dout := doutReg\n io.doutValid := valid \n } \n}\n\n// Generate the Verilog code\nobject FuMain extends App {\n println(\"Generating the hardware\")\n (new chisel3.stage.ChiselStage).emitVerilog(new Fu(32, 5), Array(\"--target-dir\", \"generated\"))\n}\n", "groundtruth": " def STATE_0 = 0.U(2.W) // 00\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/main/scala/Join.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ***************************************/\n\n/\n * This block stops both din1 and din2 until they have data. \n * So din1 and din2 shouldn't signal a stop when they're empty. \n * If they do, it will hold up the movement of data in the earlier \n * pipeline stages and stop din1 and din2 from getting valid data \n * during the stalled state.\n **/\n\nimport chisel3._\nimport chisel3.util._\n\nclass Join \n (\n dataWidth: Int\n )\n extends Module {\n val io = IO(new Bundle {\n val din1 = Input(SInt(dataWidth.W))\n val din2 = Input(SInt(dataWidth.W))\n val doutReady = Input(Bool())\n val din1Valid = Input(Bool())\n val din2Valid = Input(Bool())\n val doutValid = Output(Bool())\n val din1Ready = Output(Bool())\n val din2Ready = Output(Bool())\n val dout1 = Output(SInt(dataWidth.W))\n val dout2 = Output(SInt(dataWidth.W))\n })\n\n io.dout1 := io.din1\n io.dout2 := io.din2 \n io.doutValid := io.din1Valid & io.din2Valid\n io.din1Ready := io.doutReady & io.din2Valid \n io.din2Ready := io.doutReady & io.din1Valid \n}\n\n// Generate the Verilog code\n", "right_context": "", "groundtruth": "object JoinMain extends App {\n println(\"Generating the hardware\")\n (new chisel3.stage.ChiselStage).emitVerilog(new Join(32), Array(\"--target-dir\", \"generated\"))\n}\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/main/scala/OverlayRocc.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ****************************************/\nimport chisel3._\nimport chisel3.util._\n\nclass OverlayRocc \n (\n dataWidth: Int = 32, \n inputNodes: Int = 6, \n outputNodes: Int = 6, \n fifoDepth: Int = 32\n ) \n extends Module { val io = IO(new Bundle {\n val dataIn = Input(SInt((dataWidthinputNodes).W))\n val dataInValid = Input(UInt(inputNodes.W))\n val dataInReady = Output(UInt(inputNodes.W))\n val dataOut = Output(UInt((dataWidthinputNodes).W))\n val dataOutValid = Output(UInt(inputNodes.W))\n val dataOutReady = Input(UInt(inputNodes.W))\n val cellConfig = Input(UInt(192.W))\n })\n \n val northDin = Wire(Vec(inputNodes, SInt(dataWidth.W)))\n val northDinValid = Wire(Vec(inputNodes, Bool()))\n\n val vecDataInReady = Wire(Vec(inputNodes, Bool()))\n\n val vecDataOutValid = Wire(Vec(inputNodes, Bool()))\n val northDinReady = Wire(Vec(inputNodes, Bool()))\n\n val eastDout = Wire(Vec(outputNodes, SInt(dataWidth.W)))\n val eastDoutValid = Wire(Vec(outputNodes, Bool()))\n val eastDoutReady = Wire(Vec(outputNodes, Bool()))\n \n\n val intercDataWE = VecInit.fill(inputNodes -1, outputNodes)(0.asSInt(dataWidth.W)) \n val intercDataEW = VecInit.fill(inputNodes -1, outputNodes)(0.asSInt(dataWidth.W)) \n\n val intercValidWE = VecInit.fill(inputNodes -1, outputNodes)(0.asUInt(1.W)) \n val intercValidEW = VecInit.fill(inputNodes -1, outputNodes)(0.asUInt(1.W)) \n\n val intercReadyWE = VecInit.fill(inputNodes -1, outputNodes)(0.asUInt(1.W)) \n val intercReadyEW = VecInit.fill(inputNodes -1, outputNodes)(0.asUInt(1.W)) \n\n\n val intercDataNS = VecInit.fill(inputNodes, outputNodes - 1)(0.asSInt(dataWidth.W)) \n val intercDataSN = VecInit.fill(inputNodes, outputNodes - 1)(0.asSInt(dataWidth.W)) \n\n val intercValidNS = VecInit.fill(inputNodes, outputNodes -1)(0.asUInt(1.W))\n val intercValidSN = VecInit.fill(inputNodes, outputNodes -1)(0.asUInt(1.W))\n\n val intercReadyNS = VecInit.fill(inputNodes, outputNodes -1)(0.asUInt(1.W))\n val intercReadySN = VecInit.fill(inputNodes, outputNodes -1)(0.asUInt(1.W))\n\n val configBits = Wire(UInt(182.W))\n val catchConfig = Wire(Vec(inputNodesoutputNodes, Bool()))\n\n \n // ***************************************************************** Needs test\n val unsignedCellConfig = io.cellConfig(190,185).asUInt\n configBits := io.cellConfig(181,0)\n\n for( i <- 0 to inputNodesoutputNodes - 1){\n catchConfig(i) := 0.B \n }\n\n", "right_context": " northDin(i) := (io.dataIn(dataWidth(i+1) - 1, dataWidthi)).asSInt\n northDinValid(i) := io.dataInValid(i) \n vecDataInReady(i) := northDinReady(i)\n \n }\n\n io.dataInReady := vecDataInReady.asUInt \n val vecDataOut = Wire(Vec(outputNodes, SInt(dataWidth.W)))\n\n val I = RegInit(0.U(log2Ceil(inputNodes).W))\n val J = RegInit(0.U(log2Ceil(outputNodes).W))\n\n for (I <- 0 until inputNodes) \n { \n for (J <- 0 until outputNodes) \n {\n // WEST_OV \n if (I == 0) \n {\n if (J == 0) \n {\n val northWestOv = Module(new ProcessingElement(dataWidth, fifoDepth))\n\n // ****** North\n northWestOv.io.northDin := northDin(I)\n northWestOv.io.northDinValid := northDinValid(I)\n northDinReady(I) := northWestOv.io.northDinReady.asBool \n\n // ***** East\n northWestOv.io.eastDin := intercDataWE(I)(J)\n northWestOv.io.eastDinValid := intercValidWE(I)(J)\n intercReadyWE(I)(J) := northWestOv.io.eastDinReady \n\n // ***** South \n northWestOv.io.southDin := intercDataNS(I)(J)\n northWestOv.io.southDinValid := intercValidNS(I)(J)\n intercReadyNS(I)(J) := northWestOv.io.southDinReady \n\n // ***** West\n northWestOv.io.westDin := 0.S \n northWestOv.io.westDinValid := 0.U \n // westDinReady = open \n\n // ***** North\n // northDout = open\n // northDoutValid = open\n northWestOv.io.northDoutReady := 0.U \n\n // ***** East\n intercDataEW(I)(J) := northWestOv.io.eastDout \n intercValidEW(I)(J) := northWestOv.io.eastDoutValid \n northWestOv.io.eastDoutReady := intercReadyEW(I)(J)\n\n // ***** South\n intercDataSN(I)(J) := northWestOv.io.southDout \n intercValidSN(I)(J) := northWestOv.io.southDoutValid \n northWestOv.io.southDoutReady := intercReadySN(I)(J)\n\n // ***** West\n // westDout = open\n // westDoutValid = open\n northWestOv.io.westDoutReady := 0.U \n\n // ******* Config\n northWestOv.io.configBits := configBits\n northWestOv.io.catchConfig := catchConfig(I+inputNodesJ) \n }\n\n if (J != 0 & J != outputNodes - 1) \n {\n val midWestOv = Module(new ProcessingElement(dataWidth, fifoDepth))\n\n // ****** North\n midWestOv.io.northDin := intercDataSN(I)(J-1) \n midWestOv.io.northDinValid := intercValidSN(I)(J-1) \n intercReadySN(I)(J-1) := midWestOv.io.northDinReady \n\n // ***** East\n midWestOv.io.eastDin := intercDataWE(I)(J) \n midWestOv.io.eastDinValid := intercValidWE(I)(J) \n intercReadyWE(I)(J) := midWestOv.io.eastDinReady \n\n // ***** South\n midWestOv.io.southDin := intercDataNS(I)(J) \n midWestOv.io.southDinValid := intercValidNS(I)(J) \n intercReadyNS(I)(J) := midWestOv.io.southDinReady \n\n // ***** West\n midWestOv.io.westDin := 0.S \n midWestOv.io.westDinValid := 0.U\n //westDinReady = open \n\n // ***** North\n intercDataNS(I)(J-1) := midWestOv.io.northDout \n intercValidNS(I)(J-1) := midWestOv.io.northDoutValid \n midWestOv.io.northDoutReady := intercReadyNS(I)(J-1) \n\n // ***** East\n intercDataEW(I)(J) := midWestOv.io.eastDout \n intercValidEW(I)(J) := midWestOv.io.eastDoutValid \n midWestOv.io.eastDoutReady := intercReadyEW(I)(J) \n\n // ***** South\n intercDataSN(I)(J) := midWestOv.io.southDout \n intercValidSN(I)(J) := midWestOv.io.southDoutValid \n midWestOv.io.southDoutReady := intercReadySN(I)(J) \n\n // ***** West\n //westDout = open \n //westDoutValid = open \n midWestOv.io.westDoutReady := 0.U \n\n // ******* Config\n midWestOv.io.configBits := configBits\n midWestOv.io.catchConfig := catchConfig(I+inputNodesJ) \n }\n\n if (J == outputNodes - 1) \n {\n val southWestOv = Module(new ProcessingElement(dataWidth, fifoDepth))\n\n // ****** North\n southWestOv.io.northDin := intercDataSN(I)(J-1) \n southWestOv.io.northDinValid := intercValidSN(I)(J-1) \n intercReadySN(I)(J-1) := southWestOv.io.northDinReady \n\n // ***** East\n southWestOv.io.eastDin := intercDataWE(I)(J) \n southWestOv.io.eastDinValid := intercValidWE(I)(J) \n intercReadyWE(I)(J) := southWestOv.io.eastDinReady \n\n // ***** South\n southWestOv.io.southDin := 0.S \n southWestOv.io.southDinValid := 0.U \n // southDinReady = open\n\n // ***** West\n southWestOv.io.westDin := 0.S \n southWestOv.io.westDinValid := 0.U \n // westDinReady = open \n\n // ***** North\n intercDataNS(I)(J-1) := southWestOv.io.northDout \n intercValidNS(I)(J-1) := southWestOv.io.northDoutValid \n southWestOv.io.northDoutReady := intercReadyNS(I)(J-1) \n\n // ***** East\n intercDataEW(I)(J) := southWestOv.io.eastDout\n intercValidEW(I)(J) := southWestOv.io.eastDoutValid\n southWestOv.io.eastDoutReady := intercReadyEW(I)(J) \n\n // ***** South\n // southDout = open \n // southDoutValid = open \n southWestOv.io.southDoutReady := 0.U \n\n // ***** West\n // westDout = open \n // westDoutValid = open \n southWestOv.io.westDoutReady := 0.U \n\n // ******* Config\n southWestOv.io.configBits := configBits\n southWestOv.io.catchConfig := catchConfig(I+inputNodesJ) \n }\n } \n //////////////////////////////////////////////////// \n // MIDDLE_OV \n if (I != 0 & I != inputNodes - 1) \n {\n if (J == 0)\n {\n val middleNorthOv = Module(new ProcessingElement(dataWidth, fifoDepth))\n\n // ****** North\n middleNorthOv.io.northDin := northDin(I) \n middleNorthOv.io.northDinValid := northDinValid(I) \n northDinReady(I) := middleNorthOv.io.northDinReady \n\n // ***** East\n middleNorthOv.io.eastDin:= intercDataWE(I)(J) \n middleNorthOv.io.eastDinValid := intercValidWE(I)(J) \n intercReadyWE(I)(J) := middleNorthOv.io.eastDinReady \n\n // ***** South\n middleNorthOv.io.southDin := intercDataNS(I)(J) \n middleNorthOv.io.southDinValid := intercValidNS(I)(J) \n intercReadyNS(I)(J) := middleNorthOv.io.southDinReady \n\n // ***** West\n middleNorthOv.io.westDin:= intercDataEW(I-1)(J) \n middleNorthOv.io.westDinValid := intercValidEW(I-1)(J) \n intercReadyEW(I-1)(J) := middleNorthOv.io.westDinReady \n \n // ***** North\n // northDout = open \n // northDoutValid = open \n middleNorthOv.io.northDoutReady := 0.U\n\n // ***** East \n intercDataEW(I)(J) := middleNorthOv.io.eastDout \n intercValidEW(I)(J) := middleNorthOv.io.eastDoutValid \n middleNorthOv.io.eastDoutReady := intercReadyEW(I)(J)\n\n // ***** South\n intercDataSN(I)(J) := middleNorthOv.io.southDout \n intercValidSN(I)(J) := middleNorthOv.io.southDoutValid\n middleNorthOv.io.southDoutReady := intercReadySN(I)(J)\n\n // ***** West\n intercDataWE(I-1)(J) := middleNorthOv.io.westDout \n intercValidWE(I-1)(J) := middleNorthOv.io.westDoutValid \n middleNorthOv.io.westDoutReady := intercReadyWE(I-1)(J)\n\n // ******* Config\n middleNorthOv.io.configBits := configBits \n middleNorthOv.io.catchConfig := catchConfig(I+inputNodesJ) \n }\n\n if(J != 0 & J != outputNodes - 1)\n {\n val middleMiddleOv = Module(new ProcessingElement(dataWidth, fifoDepth))\n\n // ****** North\n middleMiddleOv.io.northDin := intercDataSN(I)(J-1) \n middleMiddleOv.io.northDinValid := intercValidSN(I)(J-1) \n intercReadySN(I)(J-1) := middleMiddleOv.io.northDinReady \n\n // ***** East\n middleMiddleOv.io.eastDin := intercDataWE(I)(J) \n middleMiddleOv.io.eastDinValid := intercValidWE(I)(J) \n intercReadyWE(I)(J) := middleMiddleOv.io.eastDinReady \n\n // ***** South\n middleMiddleOv.io.southDin := intercDataNS(I)(J) \n middleMiddleOv.io.southDinValid := intercValidNS(I)(J) \n intercReadyNS(I)(J) := middleMiddleOv.io.southDinReady \n\n // ***** West\n middleMiddleOv.io.westDin := intercDataEW(I-1)(J) \n middleMiddleOv.io.westDinValid := intercValidEW(I-1)(J)\n intercReadyEW(I-1)(J) := middleMiddleOv.io.westDinReady \n\n // ***** North\n intercDataNS(I)(J-1) := middleMiddleOv.io.northDout \n intercValidNS(I)(J-1) := middleMiddleOv.io.northDoutValid\n middleMiddleOv.io.northDoutReady := intercReadyNS(I)(J-1)\n\n // ***** East\n intercDataEW(I)(J) := middleMiddleOv.io.eastDout\n intercValidEW(I)(J) := middleMiddleOv.io.eastDoutValid \n middleMiddleOv.io.eastDoutReady := intercReadyEW(I)(J)\n\n // ***** South\n intercDataSN(I)(J) := middleMiddleOv.io.southDout \n intercValidSN(I)(J) := middleMiddleOv.io.southDoutValid\n middleMiddleOv.io.southDoutReady := intercReadySN(I)(J) \n\n // ***** West\n intercDataWE(I-1)(J) := middleMiddleOv.io.westDout \n intercValidWE(I-1)(J) := middleMiddleOv.io.westDoutValid \n middleMiddleOv.io.westDoutReady := intercReadyWE(I-1)(J) \n\n // ******* Config\n middleMiddleOv.io.configBits := configBits\n middleMiddleOv.io.catchConfig:= catchConfig(I+inputNodesJ) \n } \n\n if (J == outputNodes - 1)\n {\n val middleSouthOv = Module(new ProcessingElement(dataWidth, fifoDepth))\n\n // ****** North\n middleSouthOv.io.northDin := intercDataSN(I)(J-1) \n middleSouthOv.io.northDinValid := intercValidSN(I)(J-1)\n intercReadySN(I)(J-1) := middleSouthOv.io.northDinReady \n\n // ***** East\n middleSouthOv.io.eastDin := intercDataWE(I)(J) \n middleSouthOv.io.eastDinValid := intercValidWE(I)(J) \n intercReadyWE(I)(J) := middleSouthOv.io.eastDinReady \n\n // ***** South\n middleSouthOv.io.southDin := 0.S \n middleSouthOv.io.southDinValid := 0.U \n // southDinReady = open \n\n // ***** West\n middleSouthOv.io.westDin := intercDataEW(I-1)(J) \n middleSouthOv.io.westDinValid := intercValidEW(I-1)(J) \n intercReadyEW(I-1)(J) := middleSouthOv.io.westDinReady \n \n // ***** North\n intercDataNS(I)(J-1) := middleSouthOv.io.northDout \n intercValidNS(I)(J-1) := middleSouthOv.io.northDoutValid \n middleSouthOv.io.northDoutReady := intercReadyNS(I)(J-1) \n\n // ***** East\n intercDataEW(I)(J) := middleSouthOv.io.eastDout \n intercValidEW(I)(J) := middleSouthOv.io.eastDoutValid \n middleSouthOv.io.eastDoutReady := intercReadyEW(I)(J)\n\n // ***** South\n // southDout = open \n // southDoutValid = open \n middleSouthOv.io.southDoutReady := 0.U\n\n // ***** West\n intercDataWE(I-1)(J) := middleSouthOv.io.westDout \n intercValidWE(I-1)(J) := middleSouthOv.io.westDoutValid \n middleSouthOv.io.westDoutReady := intercReadyWE(I-1)(J) \n\n // ******* Config\n middleSouthOv.io.configBits := configBits\n middleSouthOv.io.catchConfig := catchConfig(I+inputNodesJ) \n } \n }\n \n // EAST_OV \n if (I == inputNodes - 1)\n {\n if (J == 0)\n {\n val northEastOv = Module(new ProcessingElement(dataWidth, fifoDepth))\n\n // ****** North\n northEastOv.io.northDin := northDin(I) \n northEastOv.io.northDinValid := northDinValid(I) \n northDinReady(I) := northEastOv.io.northDinReady \n\n // ***** East\n northEastOv.io.eastDin := 0.S \n northEastOv.io.eastDinValid := 0.U \n // eastDinReady = open \n\n // ***** South\n northEastOv.io.southDin := intercDataNS(I)(J) \n northEastOv.io.southDinValid := intercValidNS(I)(J) \n intercReadyNS(I)(J) := northEastOv.io.southDinReady \n\n // ***** West\n northEastOv.io.westDin := intercDataEW(I-1)(J) \n northEastOv.io.westDinValid := intercValidEW(I-1)(J) \n intercReadyEW(I-1)(J) := northEastOv.io.westDinReady \n\n // ***** North\n // northDout = open \n // northDoutValid = open \n northEastOv.io.northDoutReady := 0.U \n\n // ***** East\n eastDout(J) := northEastOv.io.eastDout \n eastDoutValid(J) := northEastOv.io.eastDoutValid \n northEastOv.io.eastDoutReady := eastDoutReady(J) \n\n // ***** South\n intercDataSN(I)(J) := northEastOv.io.southDout \n intercValidSN(I)(J) := northEastOv.io.southDoutValid \n northEastOv.io.southDoutReady := intercReadySN(I)(J) \n\n // ***** West\n intercDataWE(I-1)(J) := northEastOv.io.westDout \n intercValidWE(I-1)(J) := northEastOv.io.westDoutValid \n northEastOv.io.westDoutReady := intercReadyWE(I-1)(J)\n\n // ******* Config\n northEastOv.io.configBits := configBits\n northEastOv.io.catchConfig := catchConfig(I+inputNodesJ) \n }\n\n if (J != 0 & J != outputNodes - 1)\n {\n val middleEastOv = Module(new ProcessingElement(dataWidth,fifoDepth))\n\n // ****** North\n middleEastOv.io.northDin := intercDataSN(I)(J-1) \n middleEastOv.io.northDinValid := intercValidSN(I)(J-1)\n intercReadySN(I)(J-1) := middleEastOv.io.northDinReady \n \n // ***** East\n middleEastOv.io.eastDin := 0.S \n middleEastOv.io.eastDinValid := 0.U \n // io.eastDinReady = open \n\n // ***** South\n middleEastOv.io.southDin := intercDataNS(I)(J)\n middleEastOv.io.southDinValid:= intercValidNS(I)(J)\n intercReadyNS(I)(J) := middleEastOv.io.southDinReady \n\n // ***** West\n middleEastOv.io.westDin := intercDataEW(I-1)(J)\n middleEastOv.io.westDinValid := intercValidEW(I-1)(J) \n intercReadyEW(I-1)(J) := middleEastOv.io.westDinReady \n\n // ***** North\n intercDataNS(I)(J-1) := middleEastOv.io.northDout \n intercValidNS(I)(J-1) := middleEastOv.io.northDoutValid \n middleEastOv.io.northDoutReady := intercReadyNS(I)(J-1)\n\n // ***** East\n eastDout(J) := middleEastOv.io.eastDout \n eastDoutValid(J) := middleEastOv.io.eastDoutValid \n middleEastOv.io.eastDoutReady := eastDoutReady(J)\n\n // ***** South\n intercDataSN(I)(J) := middleEastOv.io.southDout \n intercValidSN(I)(J) := middleEastOv.io.southDoutValid \n middleEastOv.io.southDoutReady := intercReadySN(I)(J)\n\n // ***** West\n intercDataWE(I-1)(J) := middleEastOv.io.westDout \n intercValidWE(I-1)(J) := middleEastOv.io.westDoutValid \n middleEastOv.io.westDoutReady := intercReadyWE(I-1)(J)\n\n // ******* Config\n middleEastOv.io.configBits := configBits\n middleEastOv.io.catchConfig := catchConfig(I+inputNodesJ) \n } \n\n if (J == outputNodes - 1)\n {\n val middleSouthOv = Module(new ProcessingElement(dataWidth, fifoDepth))\n\n // ****** North\n middleSouthOv.io.northDin := intercDataSN(I)(J-1)\n middleSouthOv.io.northDinValid := intercValidSN(I)(J-1)\n intercReadySN(I)(J-1) := middleSouthOv.io.northDinReady \n\n // ***** East\n middleSouthOv.io.eastDin := 0.S \n middleSouthOv.io.eastDinValid := 0.U\n //io.eastDinReady = open\n\n // ***** South\n middleSouthOv.io.southDin := 0.S \n middleSouthOv.io.southDinValid := 0.U\n // io.southDinReady = open\n\n // ***** West\n middleSouthOv.io.westDin := intercDataEW(I-1)(J)\n middleSouthOv.io.westDinValid := intercValidEW(I-1)(J)\n intercReadyEW(I-1)(J) := middleSouthOv.io.westDinReady \n\n // ***** North\n intercDataNS(I)(J-1) := middleSouthOv.io.northDout \n intercValidNS(I)(J-1) := middleSouthOv.io.northDoutValid \n middleSouthOv.io.northDoutReady := intercReadyNS(I)(J-1)\n\n // ***** East\n eastDout(J) := middleSouthOv.io.eastDout \n eastDoutValid(J) := middleSouthOv.io.eastDoutValid \n middleSouthOv.io.eastDoutReady := eastDoutReady(J)\n\n // ***** South\n // southDout = open\n // southDoutValid = open\n middleSouthOv.io.southDoutReady := 0.U\n\n // ***** West\n intercDataWE(I-1)(J) := middleSouthOv.io.westDout \n intercValidWE(I-1)(J) := middleSouthOv.io.westDoutValid \n middleSouthOv.io.westDoutReady := intercReadyWE(I-1)(J)\n\n // ******* Config\n middleSouthOv.io.configBits := configBits\n middleSouthOv.io.catchConfig := catchConfig(I+inputNodes*J)\n } \n }\n } \n }\n for( i <- 0 to outputNodes - 1){\n vecDataOut(i) := eastDout(i)\n vecDataOutValid (i) := eastDoutValid(i) \n eastDoutReady(i) := io.dataOutReady(i)\n }\n io.dataOut := vecDataOut.asUInt \n io.dataOutValid := vecDataOutValid.asUInt \n}\n\n// Generate the Verilog code\nobject OverlayRoccMain extends App {\n println(\"Generating the hardware\")\n (new chisel3.stage.ChiselStage).emitVerilog(new OverlayRocc(32, 6, 6, 32), Array(\"--target-dir\", \"generated\"))\n}\n", "groundtruth": " when (io.cellConfig(191) === 1.U){\n catchConfig(unsignedCellConfig) := 1.B \n }\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/main/scala/ProcessingElement.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n *****************************************/\nimport chisel3._\nimport chisel3.util._\n\n", "right_context": " (\n dataWidth: Int, \n fifoDepth: Int\n ) \n extends Module {\n val io = IO(new Bundle {\n // Data in\n val northDin = Input(SInt(dataWidth.W))\n val northDinValid = Input(Bool())\n val northDinReady = Output(Bool())\n\n val eastDin = Input(SInt(dataWidth.W))\n val eastDinValid = Input(Bool())\n val eastDinReady = Output(Bool())\n\n val southDin = Input(SInt(dataWidth.W))\n val southDinValid = Input(Bool())\n val southDinReady = Output(Bool())\n\n val westDin = Input(SInt(dataWidth.W))\n val westDinValid = Input(Bool())\n val westDinReady = Output(Bool())\n\n // Data out\n val northDout = Output(SInt(dataWidth.W))\n val northDoutValid = Output(Bool())\n val northDoutReady = Input(Bool())\n\n val eastDout = Output(SInt(dataWidth.W))\n val eastDoutValid = Output(Bool())\n val eastDoutReady = Input(Bool())\n\n val southDout = Output(SInt(dataWidth.W))\n val southDoutValid = Output(Bool())\n val southDoutReady = Input(Bool())\n\n val westDout = Output(SInt(dataWidth.W))\n val westDoutValid = Output(Bool())\n val westDoutReady = Input(Bool())\n \n // Config\n val configBits = Input(UInt(182.W))\n val catchConfig = Input(Bool())\n })\n\n // Config signals\n val muxNsel = Wire(UInt(2.W))\n val muxEsel = Wire(UInt(2.W))\n val muxSsel = Wire(UInt(2.W))\n val muxWsel = Wire(UInt(2.W))\n val acceptMaskFrN = Wire(UInt(5.W))\n val acceptMaskFrE = Wire(UInt(5.W))\n val acceptMaskFrS = Wire(UInt(5.W))\n val acceptMaskFrW = Wire(UInt(5.W))\n val acceptMaskFsiN = Wire(UInt(5.W))\n val acceptMaskFsiE = Wire(UInt(5.W))\n val acceptMaskFsiS = Wire(UInt(5.W))\n val acceptMaskFsiW = Wire(UInt(5.W))\n\n val configBitsReg = RegInit(0.U(182.W))\n \n // Interconnect signals\n val northBuffer = Wire(SInt(dataWidth.W))\n val eastBuffer = Wire(SInt(dataWidth.W))\n val southBuffer = Wire(SInt(dataWidth.W))\n val westBuffer = Wire(SInt(dataWidth.W))\n\n val northBufferValid = Wire(UInt(1.W))\n val eastBufferValid = Wire(UInt(1.W))\n val southBufferValid = Wire(UInt(1.W))\n val westBufferValid = Wire(UInt(1.W))\n\n val northBufferReady = Wire(UInt(1.W))\n val eastBufferReady = Wire(UInt(1.W))\n val southBufferReady = Wire(UInt(1.W))\n val westBufferReady = Wire(UInt(1.W)) \n \n val northRegDin = Wire(SInt(dataWidth.W))\n val eastRegDin = Wire(SInt(dataWidth.W))\n val southRegDin = Wire(SInt(dataWidth.W))\n val westRegDin = Wire(SInt(dataWidth.W))\n\n val northRegDinValid = Wire(UInt(1.W))\n val eastRegDinValid = Wire(UInt(1.W))\n val southRegDinValid = Wire(UInt(1.W))\n val westRegDinValid = Wire(UInt(1.W))\n\n val northRegDinReady = Wire(UInt(1.W))\n val eastRegDinReady = Wire(UInt(1.W))\n val southRegDinReady = Wire(UInt(1.W))\n val westRegDinReady = Wire(UInt(1.W))\n // cell processing signals\n val fuDin1Ready = Wire(UInt(1.W))\n val fuDin2Ready = Wire(UInt(1.W))\n val fuDout = Wire(SInt(dataWidth.W))\n val fuDoutValid = Wire(UInt(1.W))\n \n when (io.catchConfig) {\n configBitsReg := io.configBits\n }\n // Configuration bits arrangement\n // val muxNsel = configBitsReg(7, 6)\n muxNsel := configBitsReg(7, 6)\n muxEsel := configBitsReg(9, 8)\n muxSsel := configBitsReg(11, 10)\n muxWsel := configBitsReg(13, 12)\n // cell_interior conf\n acceptMaskFsiN := configBitsReg(28, 24)\n acceptMaskFsiE := configBitsReg(33, 29)\n acceptMaskFsiS := configBitsReg(38, 34)\n acceptMaskFsiW := configBitsReg(43, 39)\n // cell_interior conf\n acceptMaskFrN := configBitsReg(61, 57)\n acceptMaskFrE := configBitsReg(66, 62)\n acceptMaskFrS := configBitsReg(71, 67)\n acceptMaskFrW := configBitsReg(76, 72)\n \n // ------------------------------- NORTH NODE -------------------------------\n\n val fifoNin = Module (new DFifo(dataWidth, fifoDepth))\n fifoNin.io.din := io.northDin \n fifoNin.io.dinValid := io.northDinValid\n fifoNin.io.doutReady := northBufferReady\n io.northDinReady := fifoNin.io.dinReady \n northBuffer := fifoNin.io.dout \n northBufferValid := fifoNin.io.doutValid \n\n val fsNin = Module (new Fs(5))\n val ready_out_fsNin = Cat(fuDin1Ready, fuDin2Ready, eastRegDinReady, southRegDinReady, westRegDinReady) \n fsNin.io.readyOut := ready_out_fsNin\n northBufferReady := fsNin.io.readyIn\n fsNin.io.forkMask := acceptMaskFsiN\n \n val muxNout = Module (new ConfMux(4, dataWidth))\n muxNout.io.selector := muxNsel\n muxNout.io.muxInput := (Cat(westBuffer, southBuffer, eastBuffer, fuDout)).asSInt \n northRegDin := muxNout.io.muxOutput\n \n val frNout = Module (new Fr(4, 5))\n val ready_frNout = Cat(fuDin1Ready, fuDin2Ready, eastRegDinReady, southRegDinReady, westRegDinReady) \n val validIn_frNout = Cat(westBufferValid, southBufferValid, eastBufferValid, fuDoutValid) \n frNout.io.readyOut := ready_frNout\n frNout.io.validIn := validIn_frNout\n frNout.io.validMuxSel := muxNsel\n frNout.io.forkMask := acceptMaskFrN\n northRegDinValid := frNout.io.validOut \n\n val regNout = Module (new DReg(dataWidth))\n \n regNout.io.din := northRegDin \n regNout.io.dinValid := northRegDinValid \n regNout.io.doutReady := io.northDoutReady\n\n northRegDinReady := regNout.io.dinReady\n io.northDout := regNout.io.dout \n io.northDoutValid := regNout.io.doutValid \n \n //------------------------------- NORTH NODE -------------------------------\n\n // ------------------------------- EAST NODE -------------------------------\n \n val fifoEin = Module (new DFifo(dataWidth, fifoDepth))\n fifoEin.io.din := io.eastDin \n fifoEin.io.dinValid := io.eastDinValid\n fifoEin.io.doutReady := eastBufferReady\n io.eastDinReady := fifoEin.io.dinReady \n eastBuffer := fifoEin.io.dout \n eastBufferValid := fifoEin.io.doutValid \n\n val fsEin = Module (new Fs(5))\n val ready_out_fsEin = Cat(fuDin1Ready, fuDin2Ready, northRegDinReady, southRegDinReady, westRegDinReady) \n fsEin.io.readyOut := ready_out_fsEin\n eastBufferReady := fsEin.io.readyIn\n fsEin.io.forkMask := acceptMaskFsiE\n\n val muxEout = Module (new ConfMux(4, dataWidth))\n muxEout.io.selector := muxEsel\n muxEout.io.muxInput := (Cat(westBuffer, southBuffer, northBuffer, fuDout)).asSInt\n eastRegDin := muxEout.io.muxOutput\n \n val frEout = Module (new Fr(4, 5))\n val ready_frEout = Cat(fuDin1Ready, fuDin2Ready, northRegDinReady, southRegDinReady, westRegDinReady) \n val validIn_frEout = Cat(westBufferValid, southBufferValid, northBufferValid, fuDoutValid) \n frEout.io.readyOut := ready_frEout\n frEout.io.validIn := validIn_frEout\n frEout.io.validMuxSel := muxEsel\n frEout.io.forkMask := acceptMaskFrE\n eastRegDinValid := frEout.io.validOut \n\n val regEout = Module (new DReg(dataWidth))\n \n regEout.io.din := eastRegDin \n regEout.io.dinValid := eastRegDinValid \n regEout.io.doutReady := io.eastDoutReady\n\n eastRegDinReady := regEout.io.dinReady\n io.eastDout := regEout.io.dout \n io.eastDoutValid := regEout.io.doutValid \n \n // ------------------------------- EAST NODE -------------------------------\n\n // ------------------------------- SOUTH NODE -------------------------------\n \n val fifoSin = Module (new DFifo(dataWidth, fifoDepth))\n fifoSin.io.din := io.southDin \n fifoSin.io.dinValid := io.southDinValid\n fifoSin.io.doutReady := southBufferReady\n io.southDinReady := fifoSin.io.dinReady \n southBuffer := fifoSin.io.dout \n southBufferValid := fifoSin.io.doutValid \n\n val fsSin = Module (new Fs(5))\n val ready_out_fsSin = Cat(fuDin1Ready, fuDin2Ready, northRegDinReady, eastRegDinReady, westRegDinReady) \n fsSin.io.readyOut := ready_out_fsSin\n southBufferReady := fsSin.io.readyIn\n fsSin.io.forkMask := acceptMaskFsiS\n \n val muxSout = Module (new ConfMux(4, dataWidth))\n muxSout.io.selector := muxSsel\n muxSout.io.muxInput := (Cat(westBuffer, eastBuffer, northBuffer, fuDout)).asSInt\n southRegDin := muxSout.io.muxOutput\n\n val frSout = Module (new Fr(4, 5))\n val ready_frSout = Cat(fuDin1Ready, fuDin2Ready, northRegDinReady, eastRegDinReady, westRegDinReady) \n val validIn_frSout = Cat(westBufferValid, eastBufferValid, northBufferValid, fuDoutValid) \n frSout.io.readyOut := ready_frSout\n frSout.io.validIn := validIn_frSout\n frSout.io.validMuxSel := muxSsel\n frSout.io.forkMask := acceptMaskFrS\n southRegDinValid := frSout.io.validOut \n\n val regSout = Module (new DReg(dataWidth))\n \n regSout.io.din := southRegDin \n regSout.io.dinValid := southRegDinValid \n regSout.io.doutReady := io.southDoutReady\n\n southRegDinReady := regSout.io.dinReady\n io.southDout := regSout.io.dout \n io.southDoutValid := regSout.io.doutValid \n // ------------------------------- SOUTH NODE -------------------------------\n\n // ------------------------------- WEST NODE -------------------------------\n\n val fifoWin = Module (new DFifo(dataWidth, fifoDepth))\n fifoWin.io.din := io.westDin \n fifoWin.io.dinValid := io.westDinValid\n fifoWin.io.doutReady := westBufferReady\n io.westDinReady := fifoWin.io.dinReady \n westBuffer := fifoWin.io.dout \n westBufferValid := fifoWin.io.doutValid \n\n val fsWin = Module (new Fs(5))\n val ready_out_fsWin = Cat(fuDin1Ready, fuDin2Ready, northRegDinReady, eastRegDinReady, southRegDinReady) \n fsWin.io.readyOut := ready_out_fsWin\n fsWin.io.forkMask := acceptMaskFsiW\n westBufferReady := fsWin.io.readyIn\n\n val muxWout = Module (new ConfMux(4, dataWidth))\n muxWout.io.selector := muxWsel\n muxWout.io.muxInput := (Cat(southBuffer, eastBuffer, northBuffer, fuDout)).asSInt \n westRegDin := muxWout.io.muxOutput\n\n val frWout = Module (new Fr(4, 5))\n val ready_frWout = Cat(fuDin1Ready, fuDin2Ready, northRegDinReady, eastRegDinReady, southRegDinReady) \n val validIn_frWout = Cat(southBufferValid, eastBufferValid, northBufferValid, fuDoutValid) \n frWout.io.readyOut := ready_frWout\n frWout.io.validIn := validIn_frWout\n frWout.io.validMuxSel := muxWsel\n frWout.io.forkMask := acceptMaskFrW\n westRegDinValid := frWout.io.validOut \n\n val regWout = Module (new DReg(dataWidth))\n \n regWout.io.din := westRegDin \n regWout.io.dinValid := westRegDinValid \n regWout.io.doutReady := io.westDoutReady\n\n westRegDinReady := regWout.io.dinReady\n io.westDout := regWout.io.dout \n io.westDoutValid := regWout.io.doutValid \n // ------------------------------- WEST NODE -------------------------------\n\n // cell processing\n val cell = Module (new CellProcessing(dataWidth))\n cell.io.northDin := northBuffer\n cell.io.northDinValid := northBufferValid\n cell.io.eastDin := eastBuffer\n cell.io.eastDinValid := eastBufferValid\n cell.io.southDin := southBuffer\n cell.io.southDinValid := southBufferValid\n cell.io.westDin := westBuffer\n cell.io.westDinValid := westBufferValid\n cell.io.northDoutReady := northRegDinReady\n cell.io.eastDoutReady := eastRegDinReady\n cell.io.southDoutReady := southRegDinReady\n cell.io.westDoutReady := westRegDinReady\n cell.io.configBits := configBitsReg\n fuDin1Ready := cell.io.fuDin1Ready \n fuDin2Ready := cell.io.fuDin2Ready \n fuDout := cell.io.dout \n fuDoutValid := cell.io.doutValid \n}\n\n// Generate the Verilog code\nobject ProcessingElementMain extends App {\n println(\"Generating the hardware\")\n (new chisel3.stage.ChiselStage).emitVerilog(new ProcessingElement(32, 32), Array(\"--target-dir\", \"generated\"))\n}", "groundtruth": "class ProcessingElement \n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/AluTest.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ****************************************/\nimport chisel3._\nimport chiseltest._\nimport org.scalatest.flatspec.AnyFlatSpec\n\nclass AluTest extends AnyFlatSpec with ChiselScalatestTester {\n \"AluTest test\" should \"pass\" in {\n test(new Alu(32, 4)) { dut =>\n\n var numOfTests = 10\n \n ////////////////////////////////////////////////////////////////\n // Test 1: SUM\n ////////////////////////////////////////////////////////////////\n dut.io.opConfig.poke(0.U)\n\n // Pos\n for (i <- 1 until numOfTests) {\n dut.io.din1.poke(i.S)\n dut.io.din2.poke((i+1).S)\n dut.clock.step(1)\n }\n // Neg \n for (i <- 1 until numOfTests) {\n dut.io.din1.poke((-i).S)\n dut.io.din2.poke((-(i+1)).S)\n dut.clock.step(1)\n }\n ////////////////////////////////////////////////////////////////\n // Test 2: MUL \n ////////////////////////////////////////////////////////////////\n dut.io.opConfig.poke(1.U)\n\n dut.io.din1.poke(5.S)\n dut.io.din2.poke(100.S)\n dut.clock.step(1)\n dut.io.din1.poke(-5.S)\n dut.io.din2.poke(100.S)\n dut.clock.step(1)\n dut.io.din1.poke(-5.S)\n dut.io.din2.poke(-100.S)\n dut.clock.step(1)\n dut.io.din1.poke(65535.S)\n dut.io.din2.poke(65535.S)\n dut.clock.step(1)\n dut.io.din1.poke(65535.S)\n dut.io.din2.poke(65536.S)\n dut.clock.step(1)\n dut.io.din1.poke(65535.S)\n dut.io.din2.poke(65537.S)\n dut.clock.step(1)\n dut.io.din1.poke(65537.S)\n dut.io.din2.poke(65547.S)\n dut.clock.step(1)\n ////////////////////////////////////////////////////////////////\n // Test 3: SUB \n ////////////////////////////////////////////////////////////////\n dut.io.opConfig.poke(2.U)\n\n for (i <- 1 until numOfTests) {\n dut.io.din1.poke((i+2).S)\n dut.io.din2.poke((i).S)\n dut.clock.step(1)\n }\n\n for (i <- 1 until numOfTests) {\n dut.io.din1.poke((-i).S)\n dut.io.din2.poke((-(i+1)).S)\n dut.clock.step(1)\n }\n ////////////////////////////////////////////////////////////////\n // Test 4: SLL \n ////////////////////////////////////////////////////////////////\n dut.io.opConfig.poke(3.U)\n\n dut.io.din1.poke(1.S)\n for (i <- 1 until numOfTests) {\n dut.io.din2.poke(i.S)\n dut.clock.step(1)\n }\n\n dut.io.din1.poke(-1.S)\n for (i <- 1 until numOfTests) {\n dut.io.din2.poke(i.S)\n dut.clock.step(1)\n }\n ////////////////////////////////////////////////////////////////\n // Test 5: SRA\n ////////////////////////////////////////////////////////////////\n dut.io.opConfig.poke(4.U)\n\n dut.io.din2.poke(1.S)\n for (i <- 1 until numOfTests) {\n dut.io.din1.poke(((i2)).S)\n dut.clock.step(1)\n }\n dut.io.din2.poke(2.S)\n for (i <- 1 until numOfTests) {\n dut.io.din1.poke((-(i2)).S)\n dut.clock.step(1)\n }\n ////////////////////////////////////////////////////////////////\n // Test 6: SRL \n ////////////////////////////////////////////////////////////////\n dut.io.opConfig.poke(5.U)\n\n for (i <- 1 until numOfTests) {\n dut.io.din1.poke((i2).S)\n dut.io.din2.poke(i.S)\n dut.clock.step(1)\n }\n\n", "right_context": "\n for (i <- 1 until numOfTests) {\n dut.io.din1.poke(i.S)\n dut.io.din2.poke((i+1).S)\n dut.clock.step(1)\n }\n ////////////////////////////////////////////////////////////////\n // Test 8: OR \n ////////////////////////////////////////////////////////////////\n dut.io.opConfig.poke(7.U)\n\n for (i <- 1 until numOfTests) {\n dut.io.din1.poke(i.S)\n dut.io.din2.poke((i+1).S)\n dut.clock.step(1)\n }\n ////////////////////////////////////////////////////////////////\n // Test 9: XOR \n ////////////////////////////////////////////////////////////////\n dut.io.opConfig.poke(8.U)\n\n for (i <- 1 until numOfTests) {\n dut.io.din1.poke(i.S)\n dut.io.din2.poke((i+1).S)\n dut.clock.step(1)\n } \n }\n } \n}", "groundtruth": " for (i <- 1 until numOfTests) {\n dut.io.din1.poke((-(i*2)).S)\n dut.io.din2.poke(i.S)\n dut.clock.step(1)\n }\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/CellProcessingTest.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ***************************************/\nimport chisel3._\nimport chiseltest._\nimport org.scalatest.flatspec.AnyFlatSpec\n\nclass CellProcessingTest extends AnyFlatSpec with ChiselScalatestTester {\n \"CellProcessingTest test\" should \"pass\" in {\n test(new CellProcessing(32)) { dut =>\n var northDin = 1.S \n var northDinValid = true.B \n var eastDin = 0.S \n var eastDinValid = false.B \n\n var southDin = 0.S \n var southDinValid = false.B \n var westDin = 2.S \n var westDinValid = true.B \n\n var northDoutReady = true.B \n var eastDoutReady = true.B \n var southDoutReady = true.B \n var westDoutReady = true.B \n \n println(\"*********************************\")\n println(\"Test 1: Summation\")\n println(\"*********************************\")\n var configBits = \"b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000010000000000000001000000000000000000000000011\".U \n \n dut.io.configBits.poke(configBits)\n dut.io.northDoutReady.poke(northDoutReady)\n dut.io.eastDoutReady.poke(eastDoutReady)\n\n dut.io.southDoutReady.poke(southDoutReady)\n dut.io.westDoutReady.poke(westDoutReady)\n dut.clock.step(1)\n dut.clock.step(1)\n\n dut.io.eastDin.poke(eastDin)\n", "right_context": " dut.clock.step(1)\n dut.io.northDin.poke(northDin)\n dut.io.northDinValid.poke(northDinValid)\n dut.io.westDin.poke(westDin)\n dut.io.westDinValid.poke(westDinValid)\n dut.clock.step(1)\n\n dut.io.northDin.poke(3.S)\n dut.io.westDin.poke(4.S)\n\n dut.clock.step(1)\n\n dut.io.northDin.poke(5.S)\n dut.io.westDin.poke(6.S)\n\n dut.clock.step(1)\n\n dut.io.northDin.poke(7.S)\n dut.io.westDin.poke(8.S)\n\n dut.clock.step(1)\n \n dut.io.northDin.poke(0.S)\n dut.io.northDinValid.poke(false.B)\n\n dut.io.westDin.poke(0.S)\n dut.io.westDinValid.poke(false.B)\n\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n\n // Outputs\n println(\"Outputs\")\n println(\"fuDin1Ready: \" + dut.io.fuDin1Ready.peek().toString)\n println(\"fuDin2Ready: \" + dut.io.fuDin2Ready.peek().toString)\n println(\"dout: \" + dut.io.dout.peek().toString)\n println(\"doutValid: \" + dut.io.doutValid.peek().toString)\n println(\"*********************************\")\n println(\"***********************************\")\n }\n } \n}\n", "groundtruth": " dut.io.eastDinValid.poke(eastDinValid)\n\n dut.io.southDin.poke(southDin)\n dut.io.southDinValid.poke(southDinValid)\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/ConfMuxTest.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ***************************************/\nimport chisel3._\nimport chiseltest._\nimport org.scalatest.flatspec.AnyFlatSpec\n\nclass ConfMuxTest extends AnyFlatSpec with ChiselScalatestTester {\n \"ConfMuxTest test\" should \"pass\" in {\n test(new ConfMux(2,2)) { dut =>\n // muxInput: 1011, selector: 1 ==> Mux Output: 10\n var selector = 1\n var muxInput = 11\n dut.io.selector.poke(selector.U)\n dut.io.muxInput.poke(muxInput.S)\n dut.clock.step(1)\n println(\"*********************************\")\n println(\"Mux Input: \" + dut.io.muxInput.peek().toString)\n println(\"Mux Selector: \" + dut.io.selector.peek().toString)\n println(\"Mux Output: \" + dut.io.muxOutput.peek().toString)\n println(\"*********************************\") \n", "right_context": " dut.clock.step(1)\n println(\"Mux Input: \" + dut.io.muxInput.peek().toString)\n println(\"Mux Selector: \" + dut.io.selector.peek().toString)\n println(\"Mux Output: \" + dut.io.muxOutput.peek().toString)\n println(\"***********************************\") \n dut.clock.step(1)\n }\n } \n}", "groundtruth": " dut.clock.step(1)\n selector = 2\n muxInput = 53\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/DEbTest.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ****************************************/\nimport chisel3._\nimport chiseltest._\nimport org.scalatest.flatspec.AnyFlatSpec\n\nclass DEbTest extends AnyFlatSpec with ChiselScalatestTester {\n \"DEbTest test\" should \"pass\" in {\n test(new DEb(32)) { dut =>\n var din = 0.S \n var doutReady = false.B \n var dinValid = false.B \n dut.io.din.poke(din)\n dut.io.dinValid.poke(dinValid)\n dut.io.doutReady.poke(doutReady)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.io.din.poke(1.S)\n dut.io.dinValid.poke(true.B)\n dut.io.doutReady.poke(true.B)\n dut.clock.step(1)\n dut.io.din.poke(2.S)\n dut.clock.step(1)\n dut.io.din.poke(3.S)\n dut.clock.step(1)\n dut.io.din.poke(4.S)\n dut.clock.step(1)\n dut.io.din.poke(5.S)\n dut.clock.step(1)\n dut.io.din.poke(6.S)\n dut.clock.step(1)\n dut.io.din.poke(7.S)\n dut.clock.step(1)\n dut.io.din.poke(0.S)\n dut.io.dinValid.poke(false.B)\n \n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n \n\n /\n ////////////////////////////////////////////////////////////////\n // Test 1 \n ////////////////////////////////////////////////////////////////\n println(\"***********************************\")\n println(\"Test 1: Vp: false, An: false\")\n println(\"*********************************\")\n println(\"*********************************\")\n println(\"*********************************\")\n println(\"Dp: \" + dut.io.din.peek().toString)\n println(\"Vp: \" + dut.io.dinValid.peek().toString)\n println(\"An: \" + dut.io.doutReady.peek().toString)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Dn: \" + dut.io.dout.peek().toString)\n println(\"Vn: \" + dut.io.doutValid.peek().toString)\n println(\"Ap: \" + dut.io.dinReady.peek().toString)\n println(\"*********************************\")\n println(\"*********************************\")\n ////////////////////////////////////////////////////////////////\n // Test 2 \n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 2: Vp: false, An: true\")\n println(\"*********************************\")\n dinValid = false.B \n doutReady = true.B \n dut.io.dinValid.poke(dinValid)\n dut.io.doutReady.poke(doutReady)\n println(\"Vp: \" + dut.io.dinValid.peek().toString)\n println(\"An: \" + dut.io.doutReady.peek().toString)\n dut.clock.step(1)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Dn: \" + dut.io.dout.peek().toString)\n println(\"Vn: \" + dut.io.doutValid.peek().toString)\n println(\"Ap: \" + dut.io.dinReady.peek().toString)\n println(\"*********************************\")\n println(\"*********************************\")\n ////////////////////////////////////////////////////////////////\n // Test 3 \n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 3: Vp: true, An: false\")\n println(\"*********************************\")\n dinValid = true.B \n doutReady = false.B \n dut.io.dinValid.poke(dinValid)\n dut.io.doutReady.poke(doutReady)\n println(\"Vp: \" + dut.io.dinValid.peek().toString)\n", "right_context": " println(\"Ap: \" + dut.io.dinReady.peek().toString)\n println(\"*********************************\")\n println(\"*********************************\") \n ////////////////////////////////////////////////////////////////\n // Test 4 \n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 4: Vp: true, An: true\")\n println(\"*********************************\")\n dinValid = true.B \n doutReady = true.B \n dut.io.dinValid.poke(dinValid)\n dut.io.doutReady.poke(doutReady)\n println(\"Vp: \" + dut.io.dinValid.peek().toString)\n println(\"An: \" + dut.io.doutReady.peek().toString)\n dut.clock.step(1)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Dn: \" + dut.io.dout.peek().toString)\n println(\"Vn: \" + dut.io.doutValid.peek().toString)\n println(\"Ap: \" + dut.io.dinReady.peek().toString)\n println(\"*********************************\")\n println(\"**********************************\") \n /\n }\n } \n}\n", "groundtruth": " println(\"An: \" + dut.io.doutReady.peek().toString)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.io.dinValid.poke(false.B)\n dut.clock.step(1)\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/DFifoTest.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n *****************************************/\nimport chisel3._\nimport chiseltest._\nimport org.scalatest.flatspec.AnyFlatSpec\nimport chisel3.stage.PrintFullStackTraceAnnotation\n\nclass DFifoTest extends AnyFlatSpec with ChiselScalatestTester {\n \"DFifoTest test\" should \"pass\" in {\n test(new DFifo(32, 32)).withAnnotations(Seq(VerilatorBackendAnnotation, WriteVcdAnnotation)) { dut =>\n \n //dut.io.din.poke(0.U)\n dut.io.doutReady.poke(true.B)\n dut.io.dinValid.poke(false.B)\n\n dut.clock.step(1)\n\n for (i <- 0 to 15) {\n", "right_context": " dut.io.dinValid.poke(false.B)\n dut.clock.step(10)\n }\n \n dut.clock.step(10)\n }\n } \n}\n", "groundtruth": " dut.io.din.poke(i.S) \n dut.io.dinValid.poke(true.B)\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/DRegTest.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ***************************************/\nimport chisel3._\nimport chiseltest._\nimport org.scalatest.flatspec.AnyFlatSpec\n\nclass DRegTest extends AnyFlatSpec with ChiselScalatestTester {\n \"DRegTest test\" should \"pass\" in {\n test(new DReg(8)) { dut =>\n var din = 10.S \n", "right_context": " dut.io.doutReady.poke(doutReady)\n dut.io.dinValid.poke(dinValid)\n ////////////////////////////////////////////////////////////////\n // Test 1 \n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 1: Vp: false, An: false\")\n println(\"*********************************\")\n println(\"Dp: \" + dut.io.din.peek().toString)\n println(\"*********************************\")\n println(\"*********************************\")\n println(\"Vp: \" + dut.io.dinValid.peek().toString)\n println(\"An: \" + dut.io.doutReady.peek().toString)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Dn: \" + dut.io.dout.peek().toString)\n println(\"Vn: \" + dut.io.doutValid.peek().toString)\n println(\"Ap: \" + dut.io.dinReady.peek().toString)\n ////////////////////////////////////////////////////////////////\n // Test 2\n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 2: Vp: true, An: true\")\n println(\"*********************************\")\n doutReady = true.B \n dinValid = true.B \n dut.io.doutReady.poke(doutReady)\n dut.io.dinValid.poke(dinValid)\n println(\"Vp: \" + dut.io.dinValid.peek().toString)\n println(\"An: \" + dut.io.doutReady.peek().toString)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Dn: \" + dut.io.dout.peek().toString)\n println(\"Vn: \" + dut.io.doutValid.peek().toString)\n println(\"Ap: \" + dut.io.dinReady.peek().toString)\n println(\"*********************************\")\n println(\"***********************************\")\n }\n } \n}\n", "groundtruth": " var doutReady = false.B\n var dinValid = false.B \n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/FrTest.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ***************************************/\nimport chisel3._\nimport chiseltest._\nimport org.scalatest.flatspec.AnyFlatSpec\n\nclass FrTest extends AnyFlatSpec with ChiselScalatestTester {\n \"FrTest test\" should \"pass\" in {\n test(new Fr(5,5)) { dut =>\n", "right_context": " dut.io.forkMask.poke(forkMask)\n println(\"*********************************\")\n println(\"*********************************\")\n println(\"Valid In: \" + dut.io.validIn.peek().toString)\n println(\"Ready Out: \" + dut.io.readyOut.peek().toString)\n println(\"Valid Mux Sel: \" + dut.io.validMuxSel.peek().toString)\n println(\"Fork Mask: \" + dut.io.forkMask.peek().toString)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Valid Out: \" + dut.io.validOut.peek().toString)\n validMuxSel = \"b1\".U \n dut.io.validMuxSel.poke(validMuxSel)\n println(\"*********************************\")\n println(\"*********************************\")\n println(\"Valid In: \" + dut.io.validIn.peek().toString)\n println(\"Ready Out: \" + dut.io.readyOut.peek().toString)\n println(\"Valid Mux Sel: \" + dut.io.validMuxSel.peek().toString)\n println(\"Fork Mask: \" + dut.io.forkMask.peek().toString)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Valid Out: \" + dut.io.validOut.peek().toString)\n println(\"*********************************\")\n println(\"***********************************\")\n }\n } \n}\n", "groundtruth": " \n var validIn = \"b11011\".U \n var readyOut = \"b11011\".U \n var validMuxSel = \"b10\".U \n var forkMask = \"b11011\".U \n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/FsTest.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ***************************************/\nimport chisel3._\nimport chiseltest._\nimport org.scalatest.flatspec.AnyFlatSpec\n\nclass FsTest extends AnyFlatSpec with ChiselScalatestTester {\n \"FsTest test\" should \"pass\" in {\n test(new Fs(5)) { dut =>\n", "right_context": " \n dut.io.readyOut.poke(\"b11111\".U)\n dut.io.forkMask.poke(\"b11000\".U)\n\n dut.clock.step(1)\n println(\"*********************************\")\n println(\"*********************************\")\n println(\"Ready Out: \" + dut.io.readyOut.peek().toString)\n println(\"Fork Mask: \" + dut.io.forkMask.peek().toString)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Ready In: \" + dut.io.readyIn.peek().toString)\n println(\"*********************************\")\n println(\"***********************************\")\n }\n } \n}\n", "groundtruth": " \n dut.io.readyOut.poke(\"b00000\".U)\n dut.io.forkMask.poke(\"b00000\".U)\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/FuTest.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ***************************************/\nimport chisel3._\nimport chiseltest._\nimport org.scalatest.flatspec.AnyFlatSpec\n\nclass FuTest extends AnyFlatSpec with ChiselScalatestTester {\n \"FuTest test\" should \"pass\" in {\n test(new Fu(32, 5)) { dut =>\n var din1 = 8.S\n var din2 = 3.S\n var opConfig = 0.U \n var dinValid = true.B\n var doutReady = true.B\n var loopSource = 0.U \n var iterationsReset = 0.U \n ////////////////////////////////////////////////////////////////\n // Test 1 \n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 1: Loop source: 0, Iterations Reset: 0\")\n println(\"*********************************\")\n dut.io.din1.poke(din1)\n dut.io.din2.poke(din2)\n dut.io.opConfig.poke(opConfig)\n dut.io.dinValid.poke(dinValid)\n dut.io.doutReady.poke(doutReady)\n dut.io.loopSource.poke(loopSource)\n dut.io.iterationsReset.poke(iterationsReset)\n println(\"*********************************\")\n println(\"*********************************\")\n println(\"Din1: \" + dut.io.din1.peek().toString)\n println(\"Din2: \" + dut.io.din2.peek().toString)\n println(\"VIn: \" + dut.io.dinValid.peek().toString)\n println(\"ROut: \" + dut.io.doutReady.peek().toString)\n println(\"Loop Source: \" + dut.io.loopSource.peek().toString)\n println(\"Iterarions Reset: \" + dut.io.iterationsReset.peek().toString)\n println(\"Op Config: \" + dut.io.opConfig.peek().toString)\n // Summation \n dut.clock.step(1)\n println(\"*********************************\")\n println(\"Summation: \" + dut.io.dout.peek().toString)\n opConfig = 1.U \n dut.io.opConfig.poke(opConfig)\n dut.clock.step(1)\n println(\"Multiplication: \" + dut.io.dout.peek().toString)\n opConfig = 2.U \n dut.io.opConfig.poke(opConfig)\n dut.clock.step(1)\n println(\"Subtraction: \" + dut.io.dout.peek().toString)\n opConfig = 3.U \n dut.io.opConfig.poke(opConfig)\n dut.clock.step(1)\n println(\"Shift Left Logical: \" + dut.io.dout.peek().toString)\n opConfig = 4.U \n dut.io.opConfig.poke(opConfig)\n dut.clock.step(1)\n println(\"Shift Right Arithmetic: \" + dut.io.dout.peek().toString)\n opConfig = 5.U \n dut.io.opConfig.poke(opConfig)\n dut.clock.step(1)\n println(\"Shift Right Logical: \" + dut.io.dout.peek().toString)\n opConfig = 6.U \n dut.io.opConfig.poke(opConfig)\n dut.clock.step(1)\n println(\"And: \" + dut.io.dout.peek().toString)\n opConfig = 7.U \n dut.io.opConfig.poke(opConfig)\n dut.clock.step(1)\n println(\"Or: \" + dut.io.dout.peek().toString)\n opConfig = 8.U \n dut.io.opConfig.poke(opConfig)\n dut.clock.step(1)\n println(\"Xor: \" + dut.io.dout.peek().toString)\n opConfig = 10.U \n dut.io.opConfig.poke(opConfig)\n dut.clock.step(1)\n dut.io.dinValid.poke(false.B)\n dut.clock.step(1)\n dut.clock.step(1)\n ////////////////////////////////////////////////////////////////\n // Test 2\n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 2: Loop source: 1, Iterations Reset: 3\")\n println(\"*********************************\")\n // dinValid: true\n // doutReady: true\n din1 = 1.S\n din2 = 1.S\n opConfig = 0.U \n loopSource = 1.U \n iterationsReset = 3.U \n dut.io.dinValid.poke(true.B)\n dut.io.din1.poke(din1)\n dut.io.din2.poke(din2)\n dut.io.opConfig.poke(0.U)\n dut.io.loopSource.poke(loopSource)\n dut.io.iterationsReset.poke(iterationsReset)\n dut.clock.step(1)\n println(\"*********************************\")\n println(\"Summation: \" + dut.io.dout.peek().toString)\n dut.clock.step(1)\n println(\"*********************************\")\n println(\"Summation: \" + dut.io.dout.peek().toString)\n dut.clock.step(1)\n println(\"*********************************\")\n println(\"Summation: \" + dut.io.dout.peek().toString)\n dut.clock.step(1)\n println(\"*********************************\")\n println(\"Summation: \" + dut.io.dout.peek().toString)\n dut.clock.step(1)\n println(\"*********************************\")\n println(\"Summation: \" + dut.io.dout.peek().toString)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n ////////////////////////////////////////////////////////////////\n // Test 3\n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 3: Loop source: 1, Iterations Reset: 3\")\n println(\"*********************************\")\n // dinValid: true\n // doutReady: true\n din1 = 8.S\n din2 = 1.S\n loopSource = 1.U \n iterationsReset = 3.U \n dut.io.din1.poke(din1)\n dut.io.din2.poke(din2)\n dut.io.opConfig.poke(3.U)\n dut.io.loopSource.poke(loopSource)\n dut.io.iterationsReset.poke(iterationsReset)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n ////////////////////////////////////////////////////////////////\n // Test 4\n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 4: Loop source: 0, Iterations Reset: 5\")\n println(\"*********************************\")\n // dinValid: true\n // doutReady: true\n din1 = 3.S\n din2 = 4.S\n opConfig = 0.U \n loopSource = 0.U \n iterationsReset = 5.U \n dut.io.din1.poke(din1)\n dut.io.din2.poke(din2)\n dut.io.opConfig.poke(opConfig)\n dut.io.loopSource.poke(loopSource)\n dut.io.iterationsReset.poke(iterationsReset)\n dut.clock.step(1)\n ////////////////////////////////////////////////////////////////\n // Test 5\n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 5: dinValid: 0, doutReady: 0\")\n println(\"*********************************\")\n // Loop source: 0\n // Iterations Reset: 0\n din1 = 1.S\n din2 = 2.S\n dinValid = false.B\n doutReady = false.B\n opConfig = 0.U \n loopSource = 0.U \n iterationsReset = 0.U \n dut.io.din1.poke(din1)\n dut.io.din2.poke(din2)\n dut.io.dinValid.poke(dinValid)\n dut.io.doutReady.poke(doutReady)\n dut.io.opConfig.poke(opConfig)\n dut.io.loopSource.poke(loopSource)\n dut.io.iterationsReset.poke(iterationsReset)\n dut.clock.step(1)\n ////////////////////////////////////////////////////////////////\n // Test 6\n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 5: dinValid: 0, doutReady: 1\")\n println(\"*********************************\")\n // Loop source: 0\n // Iterations Reset: 0\n din1 = 2.S\n din2 = 3.S\n dinValid = false.B\n doutReady = true.B\n opConfig = 0.U \n loopSource = 0.U \n iterationsReset = 0.U \n dut.io.din1.poke(din1)\n dut.io.din2.poke(din2)\n dut.io.dinValid.poke(dinValid)\n dut.io.doutReady.poke(doutReady)\n dut.io.opConfig.poke(opConfig)\n dut.io.loopSource.poke(loopSource)\n dut.io.iterationsReset.poke(iterationsReset)\n dut.clock.step(1)\n ////////////////////////////////////////////////////////////////\n // Test 7\n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 5: dinValid: 1, doutReady: 0\")\n println(\"*********************************\")\n // Loop source: 0\n // Iterations Reset: 0\n din1 = 3.S\n din2 = 4.S\n dinValid = true.B\n doutReady = false.B\n opConfig = 0.U \n loopSource = 0.U \n iterationsReset = 0.U \n dut.io.din1.poke(din1)\n dut.io.din2.poke(din2)\n", "right_context": " dut.io.doutReady.poke(doutReady)\n dut.io.opConfig.poke(opConfig)\n dut.io.loopSource.poke(loopSource)\n dut.io.iterationsReset.poke(iterationsReset)\n dut.clock.step(1)\n ////////////////////////////////////////////////////////////////\n // Test 8\n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Multiple inputs (din1 and din2)\")\n println(\"*********************************\")\n // dinValid: true\n // doutReady: true\n // Loop source: 0\n // Iterations Reset: 0\n din1 = 1.S\n din2 = 2.S\n dinValid = true.B\n doutReady = true.B\n opConfig = 0.U \n loopSource = 0.U \n iterationsReset = 0.U \n dut.io.din1.poke(din1)\n dut.io.din2.poke(din2)\n dut.io.dinValid.poke(dinValid)\n dut.io.doutReady.poke(doutReady)\n dut.io.opConfig.poke(opConfig)\n dut.io.loopSource.poke(loopSource)\n dut.io.iterationsReset.poke(iterationsReset)\n println(\"Din1: \" + dut.io.din1.peek().toString)\n println(\"Din2: \" + dut.io.din2.peek().toString)\n dut.clock.step(1)\n println(\"*********************************\")\n println(\"Summation: \" + dut.io.dout.peek().toString)\n din1 = 2.S\n din2 = 3.S\n dut.io.din1.poke(din1)\n dut.io.din2.poke(din2)\n println(\"Din1: \" + dut.io.din1.peek().toString)\n println(\"Din2: \" + dut.io.din2.peek().toString)\n dut.clock.step(1)\n println(\"*********************************\")\n println(\"Summation: \" + dut.io.dout.peek().toString)\n din1 = 3.S\n din2 = 4.S\n dut.io.din1.poke(din1)\n dut.io.din2.poke(din2)\n println(\"Din1: \" + dut.io.din1.peek().toString)\n println(\"Din2: \" + dut.io.din2.peek().toString)\n dut.clock.step(1)\n println(\"*********************************\")\n println(\"Summation: \" + dut.io.dout.peek().toString)\n din1 = 4.S\n din2 = 5.S\n dut.io.din1.poke(din1)\n dut.io.din2.poke(din2)\n println(\"Din1: \" + dut.io.din1.peek().toString)\n println(\"Din2: \" + dut.io.din2.peek().toString)\n dut.clock.step(1)\n println(\"*********************************\")\n println(\"Summation: \" + dut.io.dout.peek().toString)\n din1 = 5.S\n din2 = 6.S\n dut.io.din1.poke(din1)\n dut.io.din2.poke(din2)\n println(\"Din1: \" + dut.io.din1.peek().toString)\n println(\"Din2: \" + dut.io.din2.peek().toString)\n dut.clock.step(1)\n println(\"*********************************\")\n println(\"Summation: \" + dut.io.dout.peek().toString)\n din1 = 6.S\n din2 = 7.S\n dut.io.din1.poke(din1)\n dut.io.din2.poke(din2)\n println(\"Din1: \" + dut.io.din1.peek().toString)\n println(\"Din2: \" + dut.io.din2.peek().toString)\n dut.clock.step(1)\n println(\"***********************************\")\n println(\"Summation: \" + dut.io.dout.peek().toString)\n }\n } \n}\n", "groundtruth": " dut.io.dinValid.poke(dinValid)\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/JoinTest.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ***************************************/\nimport chisel3._\nimport chiseltest._\nimport org.scalatest.flatspec.AnyFlatSpec\n\nclass JoinTest extends AnyFlatSpec with ChiselScalatestTester {\n \"JoinTest test\" should \"pass\" in { \n test(new Join(32)) { dut =>\n var din1 = 10.S\n var din2 = 5.S\n var din1Valid = false.B\n var din2Valid = false.B \n var doutReady = false.B\n dut.io.din1.poke(din1)\n dut.io.din2.poke(din2)\n dut.io.din1Valid.poke(din1Valid)\n dut.io.din2Valid.poke(din2Valid)\n dut.io.doutReady.poke(doutReady)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n ////////////////////////////////////////////////////////////////\n // Test 1 \n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 1: Vin1: false, Vin2: false, Aout: false\")\n println(\"*********************************\")\n println(\"Din1: \" + dut.io.dout1.peek().toString)\n println(\"Din2: \" + dut.io.dout2.peek().toString)\n println(\"*********************************\")\n println(\"*********************************\")\n println(\"Vin1: \" + dut.io.din1Valid.peek().toString)\n println(\"Vin2: \" + dut.io.din2Valid.peek().toString)\n println(\"Aout: \" + dut.io.doutReady.peek().toString)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Ain1: \" + dut.io.din1Ready.peek().toString)\n println(\"Ain2: \" + dut.io.din2Ready.peek().toString)\n println(\"Dout1: \" + dut.io.dout1.peek().toString)\n println(\"Dout2: \" + dut.io.dout2.peek().toString)\n println(\"Vout: \" + dut.io.doutValid.peek().toString)\n println(\"*********************************\")\n println(\"*********************************\")\n ////////////////////////////////////////////////////////////////\n // Test 2\n ////////////////////////////////////////////////////////////////\n", "right_context": " println(\"Aout: \" + dut.io.doutReady.peek().toString)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Ain1: \" + dut.io.din1Ready.peek().toString)\n println(\"Ain2: \" + dut.io.din2Ready.peek().toString)\n println(\"Vout: \" + dut.io.doutValid.peek().toString)\n println(\"*********************************\")\n println(\"*********************************\")\n ////////////////////////////////////////////////////////////////\n // Test 3 \n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 3: Vin1: false, Vin2: true, Aout: false\")\n println(\"*********************************\")\n din1Valid = false.B\n din2Valid = true.B \n doutReady = false.B\n dut.io.din1Valid.poke(din1Valid)\n dut.io.din2Valid.poke(din2Valid)\n println(\"Vin1: \" + dut.io.din1Valid.peek().toString)\n println(\"Vin2: \" + dut.io.din2Valid.peek().toString)\n println(\"Aout: \" + dut.io.doutReady.peek().toString)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Ain1: \" + dut.io.din1Ready.peek().toString)\n println(\"Ain2: \" + dut.io.din2Ready.peek().toString)\n println(\"Vout: \" + dut.io.doutValid.peek().toString)\n println(\"*********************************\")\n println(\"*********************************\")\n ////////////////////////////////////////////////////////////////\n // Test 4 \n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 4: Vin1: true, Vin2: true, Aout: false\")\n println(\"*********************************\")\n din1Valid = true.B\n din2Valid = true.B \n doutReady = false.B\n dut.io.din1Valid.poke(din1Valid)\n dut.io.din2Valid.poke(din2Valid)\n dut.io.doutReady.poke(doutReady)\n println(\"Vin1: \" + dut.io.din1Valid.peek().toString)\n println(\"Vin2: \" + dut.io.din2Valid.peek().toString)\n println(\"Aout: \" + dut.io.doutReady.peek().toString)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Ain1: \" + dut.io.din1Ready.peek().toString)\n println(\"Ain2: \" + dut.io.din2Ready.peek().toString)\n println(\"Vout: \" + dut.io.doutValid.peek().toString)\n println(\"*********************************\")\n println(\"*********************************\")\n ////////////////////////////////////////////////////////////////\n // Test 5 \n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 5: Vin1: false, Vin2: false, Aout: true\")\n println(\"*********************************\")\n din1Valid = false.B\n din2Valid = false.B \n doutReady = true.B\n dut.io.din1Valid.poke(din1Valid)\n dut.io.din2Valid.poke(din2Valid)\n dut.io.doutReady.poke(doutReady)\n println(\"Vin1: \" + dut.io.din1Valid.peek().toString)\n println(\"Vin2: \" + dut.io.din2Valid.peek().toString)\n println(\"Aout: \" + dut.io.doutReady.peek().toString)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Ain1: \" + dut.io.din1Ready.peek().toString)\n println(\"Ain2: \" + dut.io.din2Ready.peek().toString)\n println(\"Vout: \" + dut.io.doutValid.peek().toString)\n println(\"*********************************\")\n println(\"*********************************\")\n ////////////////////////////////////////////////////////////////\n // Test 6 \n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 6: Vin1: true, Vin2: false, Aout: true\")\n println(\"*********************************\")\n din1Valid = true.B\n din2Valid = false.B \n doutReady = true.B\n dut.io.din1Valid.poke(din1Valid)\n dut.io.din2Valid.poke(din2Valid)\n dut.io.doutReady.poke(doutReady)\n println(\"Vin1: \" + dut.io.din1Valid.peek().toString)\n println(\"Vin2: \" + dut.io.din2Valid.peek().toString)\n println(\"Aout: \" + dut.io.doutReady.peek().toString)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Ain1: \" + dut.io.din1Ready.peek().toString)\n println(\"Ain2: \" + dut.io.din2Ready.peek().toString)\n println(\"Vout: \" + dut.io.doutValid.peek().toString)\n println(\"*********************************\")\n println(\"*********************************\")\n ////////////////////////////////////////////////////////////////\n // Test 7\n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 7: Vin1: false, Vin2: true, Aout: true\")\n println(\"*********************************\")\n din1Valid = false.B\n din2Valid = true.B \n doutReady = true.B\n dut.io.din1Valid.poke(din1Valid)\n dut.io.din2Valid.poke(din2Valid)\n dut.io.doutReady.poke(doutReady)\n println(\"Vin1: \" + dut.io.din1Valid.peek().toString)\n println(\"Vin2: \" + dut.io.din2Valid.peek().toString)\n println(\"Aout: \" + dut.io.doutReady.peek().toString)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Ain1: \" + dut.io.din1Ready.peek().toString)\n println(\"Ain2: \" + dut.io.din2Ready.peek().toString)\n println(\"Vout: \" + dut.io.doutValid.peek().toString)\n println(\"*********************************\")\n println(\"*********************************\")\n ////////////////////////////////////////////////////////////////\n // Test 8\n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 8: Vin1: true, Vin2: true, Aout: true\")\n println(\"*********************************\")\n din1Valid = true.B\n din2Valid = true.B \n doutReady = true.B\n dut.io.din1Valid.poke(din1Valid)\n dut.io.din2Valid.poke(din2Valid)\n dut.io.doutReady.poke(doutReady)\n println(\"Vin1: \" + dut.io.din1Valid.peek().toString)\n println(\"Vin2: \" + dut.io.din2Valid.peek().toString)\n println(\"Aout: \" + dut.io.doutReady.peek().toString)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Ain1: \" + dut.io.din1Ready.peek().toString)\n println(\"Ain2: \" + dut.io.din2Ready.peek().toString)\n println(\"Vout: \" + dut.io.doutValid.peek().toString)\n println(\"*********************************\")\n println(\"*********************************\")\n }\n } \n}\n", "groundtruth": " println(\"*********************************\")\n println(\"Test 1: Vin1: true, Vin2: false, Aout: false\")\n println(\"***********************************\")\n din1Valid = true.B\n din2Valid = false.B \n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/OverlayRoccTestACC.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ****************************************/\nimport chisel3._\nimport chiseltest._\nimport chisel3.util._\nimport org.scalatest.flatspec.AnyFlatSpec\nimport scala.io.Source\n\nclass OverlayRoccTestACC extends AnyFlatSpec with ChiselScalatestTester {\n \"OverlayRoccTestACC test\" should \"pass\" in {\n test(new OverlayRocc(32, 6, 6, 32)).withAnnotations(Seq(VerilatorBackendAnnotation, WriteVcdAnnotation)) { dut =>\n ///////////////////////////////////////////\n // Accumulate\n ///////////////////////////////////////////\n \n var dataInValid = \"b000000\".U \n var dataOutReady = \"b111111\".U \n dut.io.dataInValid.poke(dataInValid)\n", "right_context": " dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n }\n source.close()\n \n ///////////////////////////////////////////\n // Test 1: c = 2i \n // x = Σc (n = 4) + 1\n ///////////////////////////////////////////\n /\n val din1 = BigInt(\"00000000\" + \"00000001\" + \"00000002\"+ \"00000000\" + \"00000000\" + \"00000000\" ,16).S\n dut.io.dataIn.poke(din1)\n dut.io.dataInValid.poke(\"b011000\".U)\n dut.clock.step(30)\n dut.io.dataInValid.poke(\"b000000\".U)\n \n\n for (i <- 1 to 16) {\n // ------------------------------------------------------------------------------------------------\n // \| \| C5 \| C4 \| C3 \| C2 \| C1 \| C0 \|\n // ------------------------------------------------------------------------------------------------\n // ------------------------------------------------------------------------------------------------\n // \| \| a \| x \| c \| - \| - \| b \|\n // ------------------------------------------------------------------------------------------------\n val din2 = BigInt(\"00000000\" + \"00000000\" + \"00000000\"+ \"00000000\" + \"00000000\" + f\"$i%08X\" ,16).S\n dut.io.dataIn.poke(din2)\n dut.io.dataInValid.poke(\"b100001\".U)\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n }\n */\n\n ///////////////////////////////////////////\n // Test 2: c = 2(i+1) \n // x = Σc (n = 5) + 2 \n ///////////////////////////////////////////\n \n val din1 = BigInt(\"00000000\" + \"00000002\" + \"00000002\"+ \"00000000\" + \"00000000\" + \"00000000\" ,16).S\n dut.io.dataIn.poke(din1)\n dut.io.dataInValid.poke(\"b011000\".U)\n dut.clock.step(30)\n dut.io.dataInValid.poke(\"b000000\".U)\n \n\n for (i <- 1 to 16) {\n // ------------------------------------------------------------------------------------------------\n // \| \| C5 \| C4 \| C3 \| C2 \| C1 \| C0 \|\n // ------------------------------------------------------------------------------------------------\n // ------------------------------------------------------------------------------------------------\n // \| \| a \| x \| c \| - \| - \| b \|\n // ------------------------------------------------------------------------------------------------\n val din2 = BigInt((i).formatted(\"%08X\") + \"00000000\" + \"00000000\"+ \"00000000\" + \"00000000\" + \"00000001\" ,16).S\n dut.io.dataIn.poke(din2)\n dut.io.dataInValid.poke(\"b100001\".U)\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n }\n \n // Finish \n for( i <- 0 to 150){\n dut.clock.step(1)\n } \n println(\"End of the simulation\") \n }\n } \n}", "groundtruth": " dut.io.dataOutReady.poke(dataOutReady)\n dut.clock.step(1)\n\n var cellConfig: UInt = 0.U \n \n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/OverlayRoccTestCAP.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n *****************************************/\nimport chisel3._\nimport chiseltest._\nimport chisel3.util._\nimport org.scalatest.flatspec.AnyFlatSpec\nimport scala.io.Source\n\nclass OverlayRoccTestCAP extends AnyFlatSpec with ChiselScalatestTester {\n \"OverlayRoccCAP test\" should \"pass\" in {\n test(new OverlayRocc(32, 6, 6, 32)).withAnnotations(Seq(VerilatorBackendAnnotation, WriteVcdAnnotation)) { dut =>\n ///////////////////////////////////////////\n // CAP\n ///////////////////////////////////////////\n\n var dataInValid = \"b000000\".U \n var dataOutReady = \"b111111\".U \n dut.io.dataInValid.poke(dataInValid)\n dut.io.dataOutReady.poke(dataOutReady)\n dut.clock.step(1)\n\n var cellConfig: UInt = 0.U \n \n val source = Source.fromFile(\"src/test/scala/Bitstreams/cap.txt\")\n for (line <- source.getLines()){\n \n cellConfig = (\"b\" + line).U \n dut.io.cellConfig.poke(cellConfig)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n }\n source.close()\n\n ///////////////////////////////////////////\n // Test 1: int a [SIZE]= {2, 4, 8, 16,32};\n // int b [SIZE]= {1, 2, 3, 4, 5};\n ///////////////////////////////////////////\n var din = BigInt(\"00000001\" + \"00000000000000000000000000000000\" + \"00000002\" ,16).S \n dut.io.dataIn.poke(din)\n dut.io.dataInValid.poke(\"b100001\".U)\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n\n din = BigInt(\"00000002\" + \"00000000000000000000000000000000\" + \"00000004\" ,16).S \n dut.io.dataIn.poke(din)\n dut.io.dataInValid.poke(\"b100001\".U)\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n\n din = BigInt(\"00000003\" + \"00000000000000000000000000000000\" + \"00000008\" ,16).S \n dut.io.dataIn.poke(din)\n dut.io.dataInValid.poke(\"b100001\".U)\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n\n din = BigInt(\"00000004\" + \"00000000000000000000000000000000\" + \"00000010\" ,16).S \n dut.io.dataIn.poke(din)\n dut.io.dataInValid.poke(\"b100001\".U)\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n\n din = BigInt(\"00000005\" + \"00000000000000000000000000000000\" + \"00000020\" ,16).S \n dut.io.dataIn.poke(din)\n dut.io.dataInValid.poke(\"b100001\".U)\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n ///////////////////////////////////////////\n // Test 2: int a [SIZE]= {1, 2, 3, 4, 5};\n // int b [SIZE]= {1, 2, 3, 4, 5};\n ///////////////////////////////////////////\n din = BigInt(\"00000001\" + \"00000000000000000000000000000000\" + \"00000001\" ,16).S \n dut.io.dataIn.poke(din)\n", "right_context": " dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n\n din = BigInt(\"00000002\" + \"00000000000000000000000000000000\" + \"00000002\" ,16).S \n dut.io.dataIn.poke(din)\n<TARGET>\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n\n din = BigInt(\"00000003\" + \"00000000000000000000000000000000\" + \"00000003\" ,16).S \n dut.io.dataIn.poke(din)\n dut.io.dataInValid.poke(\"b100001\".U)\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n\n din = BigInt(\"00000004\" + \"00000000000000000000000000000000\" + \"00000004\" ,16).S \n dut.io.dataIn.poke(din)\n dut.io.dataInValid.poke(\"b100001\".U)\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n\n din = BigInt(\"00000005\" + \"00000000000000000000000000000000\" + \"00000005\" ,16).S \n dut.io.dataIn.poke(din)\n dut.io.dataInValid.poke(\"b100001\".U)\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n\n // Finish \n for( i <- 0 to 10){\n dut.clock.step(1)\n } \n println(\"End of the simulation\") \n }\n } \n}\n", "groundtruth": " dut.io.dataInValid.poke(\"b100001\".U)\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/OverlayRoccTestMAC.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ****************************************/\nimport chisel3._\nimport chiseltest._\nimport chisel3.util._\nimport org.scalatest.flatspec.AnyFlatSpec\nimport scala.io.Source\n\nclass OverlayRoccTestMAC extends AnyFlatSpec with ChiselScalatestTester {\n \"OverlayRoccTestMAC test\" should \"pass\" in {\n test(new OverlayRocc(32, 6, 6, 32)).withAnnotations(Seq(VerilatorBackendAnnotation, WriteVcdAnnotation)) { dut => \n ///////////////////////////////////////////\n // MAC\n ///////////////////////////////////////////\n\n var dataInValid = \"b000000\".U \n var dataOutReady = \"b111111\".U \n dut.io.dataInValid.poke(dataInValid)\n dut.io.dataOutReady.poke(dataOutReady)\n dut.clock.step(1)\n\n var cellConfig: UInt = 0.U \n \n val source = Source.fromFile(\"src/test/scala/Bitstreams/mac.txt\")\n for (line <- source.getLines()){\n \n cellConfig = (\"b\" + line).U \n dut.io.cellConfig.poke(cellConfig)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n }\n source.close()\n \n ///////////////////////////////////////////\n // Test 1: a = 2\n // b = i\n // x = Σc (n = 4) + 0\n ///////////////////////////////////////////\n /\n for (i <- 1 to 101) {\n val c4 = i.toString()\n val c5 = i.toString()\n \n val din = BigInt(\"00000000\" + f\"$i%08X\" + \"00000002\"+ \"00000000\" + \"00000000\" + \"00000000\" ,16).S\n \n dut.io.dataIn.poke(din)\n dut.io.dataInValid.poke(\"b111000\".U)\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n }\n */\n ///////////////////////////////////////////\n // Test 2: a = i\n // b = i\n // x = Σc (n = 5) + 3\n ///////////////////////////////////////////\n\n", "right_context": " // ------------------------------------------------------------------------------------------------\n // ------------------------------------------------------------------------------------------------\n // \| \| x \| b \| a \| - \| - \| - \|\n // ------------------------------------------------------------------------------------------------\n val din = BigInt(\"00000003\" + (i).formatted(\"%08X\") + (i).formatted(\"%08X\") + \"00000000\" + \"00000000\" + \"00000000\" ,16).S\n dut.io.dataIn.poke(din)\n dut.io.dataInValid.poke(\"b111000\".U)\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n }\n // Finish \n for( i <- 0 to 10){\n dut.clock.step(1)\n } \n println(\"End of the simulation\") \n }\n } \n}\n", "groundtruth": " for (i <- 1 to 101) {\n // ------------------------------------------------------------------------------------------------\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/OverlayRoccTestMAC2.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ****************************************/\nimport chisel3._\nimport chiseltest._\nimport chisel3.util._\nimport org.scalatest.flatspec.AnyFlatSpec\nimport scala.io.Source\n\nclass OverlayRoccTestMAC2 extends AnyFlatSpec with ChiselScalatestTester {\n \"OverlayRoccTestMAC2 test\" should \"pass\" in {\n test(new OverlayRocc(32, 6, 6, 32)).withAnnotations(Seq(VerilatorBackendAnnotation, WriteVcdAnnotation)) { dut =>\n ///////////////////////////////////////////\n // MAC2\n ///////////////////////////////////////////\n \n var dataInValid = \"b000000\".U \n var dataOutReady = \"b111111\".U \n dut.io.dataInValid.poke(dataInValid)\n dut.io.dataOutReady.poke(dataOutReady)\n dut.clock.step(1)\n\n var cellConfig: UInt = 0.U \n \n val source = Source.fromFile(\"src/test/scala/Bitstreams/mac2.txt\")\n for (line <- source.getLines()){ \n cellConfig = (\"b\" + line).U \n dut.io.cellConfig.poke(cellConfig)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n }\n source.close()\n \n ///////////////////////////////////////////\n // Test 1: x = Σ 1 (n = 4) + 3\n // y = Σ 2 (n = 4) + 3\n ///////////////////////////////////////////\n /\n for (i <- 1 to 16) {\n // ------------------------------------------------------------------------------------------------\n // \| \| C5 \| C4 \| C3 \| C2 \| C1 \| C0 \|\n // ------------------------------------------------------------------------------------------------\n // ------------------------------------------------------------------------------------------------\n // \| \| y \| x \| d \| c \| a \| b \|\n // ------------------------------------------------------------------------------------------------\n val din = BigInt(\"00000003\" + \"00000003\" + \"00000001\"+ \"00000001\" + \"00000001\" + \"00000001\" ,16).S\n \n dut.io.dataIn.poke(din)\n dut.io.dataInValid.poke(\"b111111\".U)\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n }\n */\n\n ///////////////////////////////////////////\n // Test 2: x = Σ 8 (n = 5) + 3\n // y = Σ 20i (n = 5) + 4\n ///////////////////////////////////////////\n \n", "right_context": " dut.io.dataIn.poke(din)\n dut.io.dataInValid.poke(\"b111111\".U)\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n }\n\n // Finish \n for( i <- 0 to 10){\n dut.clock.step(1)\n } \n println(\"End of the simulation\") \n }\n } \n}\n", "groundtruth": " for (i <- 1 to 16) {\n // ------------------------------------------------------------------------------------------------\n // \| \| C5 \| C4 \| C3 \| C2 \| C1 \| C0 \|\n // ------------------------------------------------------------------------------------------------\n // ------------------------------------------------------------------------------------------------\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/OverlayRoccTestSUM.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ****************************************/\nimport chisel3._\nimport chiseltest._\nimport chisel3.util._\nimport org.scalatest.flatspec.AnyFlatSpec\nimport scala.io.Source\n\nclass OverlayRoccTestSUM extends AnyFlatSpec with ChiselScalatestTester {\n \"OverlayRoccTestSUM test\" should \"pass\" in {\n test(new OverlayRocc(32, 6, 6, 32)).withAnnotations(Seq(VerilatorBackendAnnotation, WriteVcdAnnotation)) { dut =>\n ///////////////////////////////////////////\n // SUM\n ///////////////////////////////////////////\n var dataInValid = \"b000000\".U \n var dataOutReady = \"b111111\".U \n \n dut.io.dataInValid.poke(dataInValid)\n dut.io.dataOutReady.poke(dataOutReady)\n dut.clock.step(1)\n\n var cellConfig: UInt = 0.U \n \n val source = Source.fromFile(\"src/test/scala/Bitstreams/sum.txt\")\n for (line <- source.getLines()){\n cellConfig = (\"b\" + line).U \n dut.io.cellConfig.poke(cellConfig)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n }\n source.close()\n \n ///////////////////////////////////////////\n // Test 1: x = 2i + 1\n ///////////////////////////////////////////\n / \n for (i <- 1 to 16) {\n // ------------------------------------------------------------------------------------------------\n // \| \| C5 \| C4 \| C3 \| C2 \| C1 \| C0 \|\n // ------------------------------------------------------------------------------------------------\n // ------------------------------------------------------------------------------------------------\n // \| \| a \| b \| - \| - \| - \| - \|\n // ------------------------------------------------------------------------------------------------\n val din = BigInt((i+1).formatted(\"%08X\")+ f\"$i%08X\" + \"00000000000000000000000000000000\",16).S\n dut.io.dataIn.poke(din)\n dut.io.dataInValid.poke(\"b110000\".U)\n dut.clock.step(i)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(5)\n }\n /\n\n ///////////////////////////////////////////\n // Test 2: x = 2i + 3\n ///////////////////////////////////////////\n /\n for (i <- 1 to 16) {\n // ------------------------------------------------------------------------------------------------\n // \| \| C5 \| C4 \| C3 \| C2 \| C1 \| C0 \|\n // ------------------------------------------------------------------------------------------------\n // ------------------------------------------------------------------------------------------------\n // \| \| a \| b \| - \| - \| - \| - \|\n // ------------------------------------------------------------------------------------------------\n val din = BigInt((i+2).formatted(\"%08X\")+ (i+1).formatted(\"%08X\") + \"00000000000000000000000000000000\",16).S\n dut.io.dataIn.poke(din)\n dut.io.dataInValid.poke(\"b110000\".U)\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(5)\n }\n */\n\n ///////////////////////////////////////////\n // Test 3: x = i\n ///////////////////////////////////////////\n\n for (i <- 4 to 19) {\n // ------------------------------------------------------------------------------------------------\n // \| \| C5 \| C4 \| C3 \| C2 \| C1 \| C0 \|\n // ------------------------------------------------------------------------------------------------\n // ------------------------------------------------------------------------------------------------\n // \| \| a \| b \| - \| - \| - \| - \|\n // ------------------------------------------------------------------------------------------------\n val din = BigInt(\"00000003\" + (i-3).formatted(\"%08X\") + \"00000000000000000000000000000000\",16).S\n dut.io.dataIn.poke(din)\n dut.io.dataInValid.poke(\"b110000\".U)\n dut.clock.step(i)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(5)\n }\n \n // Finish \n", "right_context": " } \n}\n", "groundtruth": " for( i <- 0 to 10){\n dut.clock.step(1)\n } \n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/ProcessingElementTest.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ***************************************/\nimport chisel3._\nimport chiseltest._\nimport org.scalatest.flatspec.AnyFlatSpec\n\nobject ProcessingElementParams\n{\n def DATA_WIDTH = 32\n", "right_context": " def INSTRUCTION_CHANGE_DELAY = 5 \n}\n\nimport ProcessingElementParams._\n\nclass ProcessingElementTest extends AnyFlatSpec with ChiselScalatestTester {\n \"ProcessingElementTest test\" should \"pass\" in {\n // Test code for summation with positive numbers\n\n test(new ProcessingElement(DATA_WIDTH, FIFO_DEPTH)).withAnnotations(Seq(VerilatorBackendAnnotation, WriteVcdAnnotation)) { dut =>\n \n var numOfTests = 150\n\n var northDin = 0.S\n var northDinValid = false.B\n val northDoutReady = true.B \n\n var eastDin = 0.S \n var eastDinValid = false.B \n val eastDoutReady = true.B \n\n var southDin = 0.S \n var southDinValid = false.B \n val southDoutReady = true.B \n\n var westDin = 0.S \n var westDinValid = false.B \n val westDoutReady = true.B \n\n // Initialization\n dut.io.northDin.poke(northDin)\n dut.io.northDinValid.poke(northDinValid)\n dut.io.northDoutReady.poke(northDoutReady)\n \n dut.io.eastDin.poke(eastDin)\n dut.io.eastDinValid.poke(eastDinValid)\n dut.io.eastDoutReady.poke(eastDoutReady)\n\n dut.io.southDin.poke(southDin)\n dut.io.southDinValid.poke(southDinValid)\n dut.io.southDoutReady.poke(southDoutReady)\n\n dut.io.westDin.poke(westDin)\n dut.io.westDinValid.poke(westDinValid)\n dut.io.westDoutReady.poke(westDoutReady)\n\n ////////////////////////////////////////////////////////////////////////\n ////////\n ////////\n ////////\n //////// Feedback Loop\n ////////\n ////////\n ////////\n ////////\n ////////////////////////////////////////////////////////////////////////\n\n // Test case: SUM without feedback loop\n var configBits = \"b0000000000011110110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000001000000000000000_1000_0000_0000_0000_0000_0000_0011\".U \n var catchConfig = true.B \n // Configuration \n dut.io.catchConfig.poke(catchConfig)\n dut.io.catchConfig.poke(true.B)\n dut.io.configBits.poke(configBits)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.io.catchConfig.poke(false.B)\n configBits = 0.U\n dut.io.configBits.poke(configBits)\n \n // Inserting Data \n dut.io.northDinValid.poke(true.B)\n dut.io.westDinValid.poke(true.B)\n \n //dut.io.northDin.poke(1.S)\n //dut.io.westDin.poke(1.S)\n for (i <- 1 until 16) {\n dut.io.northDin.poke(i.S)\n dut.io.westDin.poke((i).S)\n dut.io.northDinValid.poke(true.B)\n dut.io.westDinValid.poke(true.B)\n dut.clock.step(1)\n dut.io.northDinValid.poke(false.B)\n dut.io.westDinValid.poke(false.B)\n dut.clock.step(10)\n }\n dut.io.northDin.poke(0.S)\n dut.io.westDin.poke(0.S)\n dut.io.northDinValid.poke(false.B)\n dut.io.westDinValid.poke(false.B)\n for (i <- 0 until INSTRUCTION_CHANGE_DELAY) {\n dut.clock.step(1)\n }\n\n // Test case: Mul\n configBits = \"b01000000000001101100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000110000000000000001000000000000000000000000011\".U \n catchConfig = true.B \n // Configuration \n dut.io.catchConfig.poke(catchConfig)\n dut.io.catchConfig.poke(true.B)\n dut.io.configBits.poke(configBits)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.io.catchConfig.poke(false.B)\n configBits = 0.U\n dut.io.configBits.poke(configBits)\n \n // Inserting Data \n dut.io.northDinValid.poke(true.B)\n dut.io.westDinValid.poke(true.B)\n\n dut.io.northDin.poke(2.S)\n dut.io.westDin.poke(1.S)\n \n for (i <- 1 until 27) {\n //dut.io.northDin.poke(i.S)\n //dut.io.westDin.poke((i+1).S)\n dut.clock.step(1)\n }\n dut.io.northDin.poke(0.S)\n dut.io.westDin.poke(0.S)\n dut.io.northDinValid.poke(false.B)\n dut.io.westDinValid.poke(false.B)\n for (i <- 0 until INSTRUCTION_CHANGE_DELAY) {\n dut.clock.step(1)\n }\n\n // Test case: Sub\n configBits = \"b01000000000111101100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000001010000000000000001000000000000000000000000011\".U \n catchConfig = true.B \n // Configuration \n dut.io.catchConfig.poke(catchConfig)\n dut.io.catchConfig.poke(true.B)\n dut.io.configBits.poke(configBits)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.io.catchConfig.poke(false.B)\n configBits = 0.U\n dut.io.configBits.poke(configBits)\n \n // Inserting Data \n dut.io.northDinValid.poke(true.B)\n dut.io.westDinValid.poke(true.B)\n \n dut.io.northDin.poke(1.S)\n dut.io.westDin.poke(124.S)\n \n for (i <- 1 until 123) {\n dut.clock.step(1)\n }\n dut.io.northDin.poke(0.S)\n dut.io.westDin.poke(0.S)\n dut.io.northDinValid.poke(false.B)\n dut.io.westDinValid.poke(false.B)\n for (i <- 0 until INSTRUCTION_CHANGE_DELAY) {\n dut.clock.step(1)\n }\n\n // Test case: Shift left (logic)\n //////////// North: din_2, West: din_1 \n configBits = \"b01000000000001111100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000001110000000000000001000000000000000000000000011\".U \n catchConfig = true.B \n // Configuration \n dut.io.catchConfig.poke(catchConfig)\n dut.io.catchConfig.poke(true.B)\n dut.io.configBits.poke(configBits)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.io.catchConfig.poke(false.B)\n configBits = 0.U\n dut.io.configBits.poke(configBits)\n \n // Inserting Data \n dut.io.northDinValid.poke(true.B)\n dut.io.westDinValid.poke(true.B)\n \n dut.io.westDin.poke(1.S)\n dut.io.northDin.poke(1.S)\n for (i <- 1 until 31) {\n dut.clock.step(1)\n }\n dut.io.westDin.poke(0.S)\n dut.io.northDin.poke(0.S)\n dut.io.northDinValid.poke(false.B)\n dut.io.westDinValid.poke(false.B)\n for (i <- 0 until INSTRUCTION_CHANGE_DELAY) {\n dut.clock.step(1)\n }\n\n // ** Test case: Shift left (arithmetic) ????? or Right ? \n\n configBits = \"b01000000000111101100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000010010000000000000001000000000000000000000000011\".U \n catchConfig = true.B \n // Configuration \n dut.io.catchConfig.poke(catchConfig)\n dut.io.catchConfig.poke(true.B)\n dut.io.configBits.poke(configBits)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.io.catchConfig.poke(false.B)\n configBits = 0.U\n dut.io.configBits.poke(configBits)\n \n // Inserting Data \n dut.io.northDinValid.poke(true.B)\n dut.io.westDinValid.poke(true.B)\n \n \n for (i <- 1 until numOfTests) {\n dut.io.westDin.poke((-(i4)).S)\n dut.io.northDin.poke((i-1).S)\n dut.clock.step(1)\n }\n dut.io.northDinValid.poke(false.B)\n dut.io.westDinValid.poke(false.B)\n for (i <- 0 until INSTRUCTION_CHANGE_DELAY) {\n dut.clock.step(1)\n }\n\n // *** Test case: Shift right (logic)\n\n configBits = \"b01000000000111101100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000010110000000000000001000000000000000000000000011\".U \n catchConfig = true.B \n // Configuration \n dut.io.catchConfig.poke(catchConfig)\n dut.io.catchConfig.poke(true.B)\n dut.io.configBits.poke(configBits)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.io.catchConfig.poke(false.B)\n configBits = 0.U\n dut.io.configBits.poke(configBits)\n \n // Inserting Data \n dut.io.northDinValid.poke(true.B)\n dut.io.westDinValid.poke(true.B)\n \n dut.io.northDin.poke(1.S)\n for (i <- 1 until numOfTests) {\n dut.io.westDin.poke((-(i2)).S)\n dut.io.northDin.poke((i-1).S)\n dut.clock.step(1)\n }\n \n dut.io.northDinValid.poke(false.B)\n dut.io.westDinValid.poke(false.B)\n for (i <- 0 until INSTRUCTION_CHANGE_DELAY) {\n dut.clock.step(1)\n }\n\n // * Test case: AND\n configBits = \"b01000000000111101100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000011010000000000000001000000000000000000000000011\".U \n catchConfig = true.B \n // Configuration \n dut.io.catchConfig.poke(catchConfig)\n dut.io.catchConfig.poke(true.B)\n dut.io.configBits.poke(configBits)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.io.catchConfig.poke(false.B)\n configBits = 0.U\n dut.io.configBits.poke(configBits)\n \n // Inserting Data \n dut.io.northDinValid.poke(true.B)\n dut.io.westDinValid.poke(true.B)\n \n \n for (i <- 1 until numOfTests) {\n dut.io.northDin.poke(i.S)\n if (i % 2 == 0) {\n dut.io.westDin.poke((i+1).S)\n } else {\n dut.io.westDin.poke((i+2).S)\n }\n dut.clock.step(1)\n }\n dut.io.northDinValid.poke(false.B)\n dut.io.westDinValid.poke(false.B)\n for (i <- 0 until INSTRUCTION_CHANGE_DELAY) {\n dut.clock.step(1)\n }\n\n // Test case: OR\n configBits = \"b01000000000111101100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000011110000000000000001000000000000000000000000011\".U \n catchConfig = true.B \n // Configuration \n dut.io.catchConfig.poke(catchConfig)\n dut.io.catchConfig.poke(true.B)\n dut.io.configBits.poke(configBits)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.io.catchConfig.poke(false.B)\n configBits = 0.U\n dut.io.configBits.poke(configBits)\n \n // Inserting Data \n dut.io.northDinValid.poke(true.B)\n dut.io.westDinValid.poke(true.B)\n \n for (i <- 1 until numOfTests) {\n dut.io.northDin.poke(i.S)\n if (i % 2 == 0) {\n dut.io.westDin.poke((i+1).S)\n } else {\n dut.io.westDin.poke((i+2).S)\n }\n dut.clock.step(1)\n }\n dut.io.northDinValid.poke(false.B)\n dut.io.westDinValid.poke(false.B)\n for (i <- 0 until INSTRUCTION_CHANGE_DELAY) {\n dut.clock.step(1)\n }\n // ** Test case: XOR\n configBits = \"b01000000000111101100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000100010000000000000001000000000000000000000000011\".U \n catchConfig = true.B \n // Configuration \n dut.io.catchConfig.poke(catchConfig)\n dut.io.catchConfig.poke(true.B)\n dut.io.configBits.poke(configBits)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.io.catchConfig.poke(false.B)\n configBits = 0.U\n dut.io.configBits.poke(configBits)\n \n // Inserting Data \n dut.io.northDinValid.poke(true.B)\n dut.io.westDinValid.poke(true.B)\n \n for (i <- 1 until numOfTests) {\n dut.io.northDin.poke(i.S)\n if (i % 2 == 0) {\n dut.io.westDin.poke((i+1).S)\n } else {\n dut.io.westDin.poke((i+2).S)\n }\n dut.clock.step(1)\n }\n dut.io.northDinValid.poke(false.B)\n dut.io.westDinValid.poke(false.B)\n for (i <- 0 until INSTRUCTION_CHANGE_DELAY) {\n dut.clock.step(1)\n }\n }\n } \n}", "groundtruth": " def FIFO_DEPTH = 32 \n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/example/detect2ones.test.scala", "left_context": "//> using scala \"2.13.14\"\n//> using dep \"com.github.rameloni::tywaves-chisel-api:0.4.2-SNAPSHOT\"\n//> using dep \"org.chipsalliance::chisel:6.4.0\"\n//> using plugin \"org.chipsalliance:::chisel-plugin:6.4.0\"\n//> using options \"-unchecked\", \"-deprecation\", \"-language:reflectiveCalls\", \"-feature\", \"-Xcheckinit\", \"-Xfatal-warnings\", \"-Ywarn-dead-code\", \"-Ywarn-unused\", \"-Ymacro-annotations\"\n//> using dep \"org.scalatest::scalatest:3.2.19\"\n\nimport chisel3._\nimport circt.stage._\nimport chisel3.util._\nimport tywaves.simulator._\nimport tywaves.simulator.simulatorSettings._\n\nimport org.scalatest.funspec.AnyFunSpec\nimport org.scalatest.matchers.should.Matchers\n\nclass DetectTwoOnes extends Module {\n val io = IO(new Bundle {\n val in = Input(Bool())\n val out = Output(Bool())\n })\n\n object State extends ChiselEnum { val sNone, sOne1, sTwo1s = Value }\n val state = RegInit(State.sNone)\n\n // Tmp signal 1\n val isOne = Wire(Bool())\n isOne := io.in\n // Tmp signal 2\n val willBeTwo1s = io.in && (state === State.sOne1 \|\| state === State.sTwo1s)\n\n io.out := (state === State.sTwo1s)\n\n switch(state) {\n is(State.sNone) { when(isOne) { state := State.sOne1 } }\n is(State.sOne1) { \n", "right_context": " }\n is(State.sTwo1s) { when(!isOne) { state := State.sNone } }\n }\n}\n\n\nclass DetectTwoOnesTest extends AnyFunSpec with Matchers {\n\n import TywavesSimulator._\n def runTest(fsm: DetectTwoOnes) = {\n // Inputs and expected results\n val inputs = Seq(0, 0, 1, 0, 1, 1, 0, 1, 1, 1)\n val expected = Seq(0, 0, 0, 0, 0, 1, 0, 0, 1, 1)\n\n // Reset\n fsm.io.in.poke(0)\n fsm.clock.step(1)\n\n for (i <- inputs.indices) {\n fsm.io.in.poke(inputs(i))\n fsm.clock.step(1)\n //\tc.clock.getStepCount\n fsm.io.out.expect(expected(i))\n //\tSystem.out.println(s\"In: ${inputs(i)}, out: ${expected(i)}\")\n }\n }\n\n describe(\"TywavesSimulator\") {\n it(\"runs DetectTwoOnes correctly\") {\n val chiselStage = new ChiselStage(true)\n \n chiselStage.execute(\n args = Array(\"--target\", \"chirrtl\"),\n annotations = Seq(\n chisel3.stage.ChiselGeneratorAnnotation(() => new DetectTwoOnes()),\n FirtoolOption(\"-g\"),\n FirtoolOption(\"--emit-hgldd\"),\n ),\n )\n\n simulate(new DetectTwoOnes(), Seq(VcdTrace, WithTywavesWaveformsGo(true)), simName = \"runs_detect2ones\") {\n fsm =>\n runTest(fsm)\n }\n\n }\n }\n\n}", "groundtruth": " when(isOne) { state := State.sTwo1s }.otherwise { state := State.sNone } \n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/example/gcd.test.scala", "left_context": "//> using scala \"2.13.14\"\n//> using dep \"com.github.rameloni::tywaves-chisel-api:0.4.2-SNAPSHOT\"\n//> using dep \"org.chipsalliance::chisel:6.4.0\"\n//> using plugin \"org.chipsalliance:::chisel-plugin:6.4.0\"\n//> using options \"-unchecked\", \"-deprecation\", \"-language:reflectiveCalls\", \"-feature\", \"-Xcheckinit\", \"-Xfatal-warnings\", \"-Ywarn-dead-code\", \"-Ywarn-unused\", \"-Ymacro-annotations\"\n//> using dep \"org.scalatest::scalatest:3.2.18\"\n\n// DO NOT EDIT THE ORTHER OF THESE IMPORTS (it will be solved in future versions)\nimport chisel3._\nimport tywaves.simulator._\nimport tywaves.simulator.ParametricSimulator._\nimport tywaves.simulator.simulatorSettings._\nimport circt.stage.ChiselStage\n// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._\n//import _root_.circt.stage.ChiselStage\nimport org.scalatest.funspec.AnyFunSpec\nimport org.scalatest.matchers.should.Matchers\n\n/** A simple module useful for testing Chisel generation and testing */\nclass GCD extends Module {\n val io = IO(new Bundle {\n val a = Input(UInt(32.W))\n val b = Input(UInt(32.W))\n val loadValues = Input(Bool())\n val result = Output(UInt(32.W))\n val resultIsValid = Output(Bool())\n })\n\n val x = Reg(UInt(32.W))\n val y = Reg(UInt(32.W))\n\n val tmp = x + y\n when(x > y) {\n val myTmpVal: UInt = x -% y\n x := myTmpVal\n }.otherwise {\n val myTmpVal = y -% x\n val myTmpVal3 = Wire(UInt(32.W))\n myTmpVal3 := myTmpVal\n y := y -% x\n }\n\n", "right_context": "\n io.result := x\n io.resultIsValid := y === 0.U\n}\n\nclass GCDTest extends AnyFunSpec with Matchers {\n describe(\"ParametricSimulator\") {\n it(\"runs GCD correctly\") {\n\n val chiselStage = new ChiselStage(true)\n chiselStage.execute(\n args = Array(\"--target\", \"chirrtl\"),\n annotations = Seq(\n chisel3.stage.ChiselGeneratorAnnotation(() => new GCD()),\n circt.stage.FirtoolOption(\"-g\"),\n circt.stage.FirtoolOption(\"--emit-hgldd\"),\n ),\n )\n println(\"Hello, world!\")\n simulate(new GCD(), Seq(VcdTrace, SaveWorkdirFile(\"gcdWorkdir\"))) { gcd =>\n gcd.io.a.poke(24.U)\n gcd.io.b.poke(36.U)\n gcd.io.loadValues.poke(1.B)\n gcd.clock.step()\n gcd.io.loadValues.poke(0.B)\n gcd.clock.stepUntil(sentinelPort = gcd.io.resultIsValid, sentinelValue = 1, maxCycles = 10)\n gcd.io.resultIsValid.expect(true.B)\n gcd.io.result.expect(12)\n }\n }\n }\n\n describe(\"TywavesSimulator\") {\n it(\"runs GCD correctly\") {\n import TywavesSimulator._\n\n simulate(new GCD(), Seq(VcdTrace, WithTywavesWaveforms(true)), simName = \"runs_GCD_correctly_launch_tywaves\") {\n gcd =>\n gcd.io.a.poke(24.U)\n gcd.io.b.poke(36.U)\n gcd.io.loadValues.poke(1.B)\n gcd.clock.step()\n gcd.io.loadValues.poke(0.B)\n gcd.clock.stepUntil(sentinelPort = gcd.io.resultIsValid, sentinelValue = 1, maxCycles = 10)\n gcd.io.resultIsValid.expect(true.B)\n gcd.io.result.expect(12)\n gcd.io.a.poke(24.U)\n gcd.io.b.poke(72.U)\n gcd.reset.poke(true.B)\n gcd.io.loadValues.poke(1.B)\n gcd.clock.step()\n gcd.io.loadValues.poke(0.B)\n gcd.reset.poke(false.B)\n gcd.clock.stepUntil(sentinelPort = gcd.io.resultIsValid, sentinelValue = 1, maxCycles = 10)\n gcd.io.resultIsValid.expect(true.B)\n gcd.io.result.expect(24)\n }\n }\n }\n\n}\n", "groundtruth": " when(io.loadValues) { x := io.a; y := io.b }\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/example/myfsm.test.scala", "left_context": "//> using scala \"2.13.14\"\n//> using dep \"com.github.rameloni::tywaves-chisel-api:0.4.2-SNAPSHOT\"\n//> using dep \"org.chipsalliance::chisel:6.4.0\"\n//> using plugin \"org.chipsalliance:::chisel-plugin:6.4.0\"\n//> using options \"-unchecked\", \"-deprecation\", \"-language:reflectiveCalls\", \"-feature\", \"-Xcheckinit\", \"-Xfatal-warnings\", \"-Ywarn-dead-code\", \"-Ywarn-unused\", \"-Ymacro-annotations\"\n//> using dep \"org.scalatest::scalatest:3.2.18\"\n\n// DO NOT EDIT THE ORTHER OF THESE IMPORTS (it will be solved in future versions)\nimport tywaves.simulator._\nimport tywaves.simulator.simulatorSettings._\nimport chisel3._\n// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._\n//import _root_.circt.stage.ChiselStage\nimport org.scalatest.funspec.AnyFunSpec\nimport org.scalatest.matchers.should.Matchers\nimport circt.stage.ChiselStage\n\n// Enum of possible states\nobject MyFSMStates extends ChiselEnum {\n val IDLE, StateA, StateB, END = Value\n}\n\nclass FSM extends Bundle {\n\n val inputState = IO(Input(MyFSMStates()))\n val state = RegInit(MyFSMStates.IDLE)\n val stateNxt = WireInit(MyFSMStates.IDLE)\n\n val endConst = WireInit(MyFSMStates.END)\n\n when(state === MyFSMStates.IDLE) {\n stateNxt := MyFSMStates.StateA\n }.elsewhen(state === MyFSMStates.StateA) {\n stateNxt := MyFSMStates.StateB\n }.elsewhen(state === MyFSMStates.StateB) {\n stateNxt := MyFSMStates.END\n }.otherwise {\n stateNxt := MyFSMStates.IDLE\n }\n\n when(inputState === MyFSMStates.END) {\n state := MyFSMStates.IDLE\n }.otherwise {\n state := stateNxt\n }\n}\n\nclass MyFSM extends Module {\n val fsm = new FSM\n\n val io = IO(new Bundle {\n val inputState = Input(MyFSMStates())\n })\n\n val aConstBundle = Wire(new Bundle {\n val bit = Bool()\n val bv = UInt(32.W)\n val subbundle = new Bundle {\n val x = SInt(3.W)\n }\n })\n aConstBundle.bit := 1.B\n aConstBundle.bv := 34.U\n aConstBundle.subbundle.x := 2.S\n}\n\n\nclass MyFSMTest extends AnyFunSpec with Matchers {\n\n describe(\"TywavesSimulator\") {\n it(\"runs MyFSM correctly\") {\n import TywavesSimulator._\n val chiselStage = new ChiselStage(true)\n \n chiselStage.execute(\n args = Array(\"--target\", \"chirrtl\"),\n annotations = Seq(\n chisel3.stage.ChiselGeneratorAnnotation(() => new MyFSM()),\n circt.stage.FirtoolOption(\"-g\"),\n circt.stage.FirtoolOption(\"--emit-hgldd\"),\n ),\n )\n simulate(new MyFSM(), Seq(VcdTrace, WithTywavesWaveformsGo(true)), simName = \"runs_MYFSM_correctly_launch_tywaves_and_go\") {\n fsm =>\n fsm.clock.step(10)\n fsm.clock.step(10)\n }\n simulate(new MyFSM(), Seq(VcdTrace, WithTywavesWaveforms(true)), simName = \"runs_MYFSM_correctly_launch_tywaves\") {\n fsm =>\n", "right_context": " }\n\n}\n", "groundtruth": " fsm.clock.step(10)\n fsm.io.inputState.poke(MyFSMStates.StateA)\n fsm.clock.step(10)\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/example/tydi-example-meaningfulnames.test.scala", "left_context": "//> using scala \"2.13.14\"\n//> using dep \"com.github.rameloni::tywaves-chisel-api:0.4.2-SNAPSHOT\"\n//> using dep \"nl.tudelft::tydi-chisel::0.1.0\"\n//> using plugin \"org.chipsalliance:::chisel-plugin:6.4.0\"\n//> using options \"-unchecked\", \"-deprecation\", \"-language:reflectiveCalls\", \"-feature\", \"-Xcheckinit\", \"-Xfatal-warnings\", \"-Ywarn-dead-code\", \"-Ywarn-unused\", \"-Ymacro-annotations\"\n//> using dep \"org.scalatest::scalatest:3.2.18\"\n\n// DO NOT EDIT THE ORTHER OF THESE IMPORTS (it will be solved in future versions)\nimport tywaves.simulator._\nimport tywaves.simulator.ParametricSimulator._\nimport tywaves.simulator.simulatorSettings._\nimport chisel3._\n\n// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._\n//import _root_.circt.stage.ChiselStage\nimport org.scalatest.funspec.AnyFunSpec\nimport org.scalatest.matchers.should.Matchers\n\nimport nl.tudelft.tydi_chisel._\nimport chisel3.util.Counter\n\nobject MyTypes {\n\n /** Bit(64) type, defined in pipelineSimple_types /\n def UInt_64_t = UInt(64.W)\n\n assert(this.UInt_64_t.getWidth == 64)\n\n /* Bit(64) type, defined in pipelineSimple_types /\n def generated_0_7_d3p7qsW3_29 = SInt(64.W)\n\n assert(this.generated_0_7_d3p7qsW3_29.getWidth == 64)\n}\n\n/\n Group element, defined in pipelineSimple_types. A composite type (like a\n * struct) that contains a value associated with a timestamp.\n /\nclass NumberGroup extends Group {\n val time = MyTypes.UInt_64_t\n val value = MyTypes.generated_0_7_d3p7qsW3_29\n}\n\n/\n Group element, defined in pipelineSimple_types. A composite type (like a\n * struct) that represents the stats of the implemented algorithm.\n /\nclass Stats extends Group {\n val average = (new UInt_64_t)\n val max = MyTypes.UInt_64_t\n val min = MyTypes.UInt_64_t\n val sum = MyTypes.UInt_64_t\n}\n\n/* Stream, defined in pipelineSimple_types. /\nclass Stats_stream(private val e: TydiEl = new Stats, n: Int = 1, d: Int = 1, c: Int = 1, r: Boolean = false, u: TydiEl = Null())\n extends PhysicalStreamDetailed(e = new Stats, n = n, d = d, c = c, r = r, u = u)\n\nobject Stats_stream {\n def apply(): Stats_stream = Wire(new Stats_stream())\n}\n\n/* Stream, defined in pipelineSimple_types. /\nclass Generated_0_36_xeHH4woS_24\n extends PhysicalStreamDetailed(e = new NumberGroup, n = 1, d = 2, c = 1, r = false, u = Null())\n\nobject Generated_0_36_xeHH4woS_24 {\n def apply(): Generated_0_36_xeHH4woS_24 = Wire(new Generated_0_36_xeHH4woS_24())\n}\n\n/* Stream, defined in pipelineSimple_types. /\nclass UInt_64_t_stream extends PhysicalStreamDetailed(e=new UInt_64_t, n=1, d=1, c=1, r=false, u=Null())\n\nobject UInt_64_t_stream {\n def apply(): UInt_64_t_stream = Wire(new UInt_64_t_stream())\n}\n\n/* Bit(64), defined in pipelineSimple_types. /\nclass UInt_64_t extends BitsEl(64.W)\n\n/* Bit(64), defined in pipelineSimple_types. /\n", "right_context": "\n/\n Streamlet, defined in pipelineSimple. Top level interface.\n /\nclass PipelineSimple_interface extends TydiModule {\n\n /* Stream of [[in]] with input direction. /\n val inStream = Generated_0_36_xeHH4woS_24().flip\n\n /* IO of [[inStream]] with input direction. /\n val in = inStream.toPhysical\n\n /* Stream of [[out]] with output direction. /\n val outStream = Stats_stream()\n\n /* IO of [[outStream]] with output direction. /\n val out = outStream.toPhysical\n\n val in2Stream = UInt_64_t_stream().flip\n /* IO of [[in2Stream]] with input direction. /\n val in2: PhysicalStream = in2Stream.toPhysical\n}\n\n/\n Streamlet, defined in pipelineSimple. Interface for the agg function.\n /\nclass Reducer_interface extends TydiModule {\n\n /* Stream of [[in]] with input direction. /\n val inStream = Generated_0_36_xeHH4woS_24().flip\n\n /* IO of [[inStream]] with input direction. /\n val in = inStream.toPhysical\n\n /* Stream of [[out]] with output direction. /\n val outStream = Stats_stream()\n\n /* IO of [[outStream]] with output direction. /\n val out = outStream.toPhysical\n}\n\n/\n Streamlet, defined in pipelineSimple. Interface for the non negative filter:\n * df.filter(col(\"value\") >= 0).\n /\nclass Instance_NonNegativeFilter_interface_RefToVargenerated_0_36_KLOZ7sts_25_1 extends TydiModule {\n\n /* Stream of [[in]] with input direction. /\n val inStream = Generated_0_36_xeHH4woS_24().flip\n\n /* IO of [[inStream]] with input direction. /\n val in = inStream.toPhysical\n\n /* Stream of [[out]] with output direction. /\n val outStream = Generated_0_36_xeHH4woS_24()\n\n /* IO of [[outStream]] with output direction. /\n val out = outStream.toPhysical\n}\n\n/\n Implementation, defined in pipelineSimple. Implementation of\n * df.filter(col(\"value\") >= 0).\n /\nclass NonNegativeFilter extends Instance_NonNegativeFilter_interface_RefToVargenerated_0_36_KLOZ7sts_25_1 {\n // Filtered only if the value is non-negative\n // inStream.valid tells us if the input is valid\n private val canPass: Bool = inStream.el.value >= 0.S && inStream.valid\n\n // Connect inStream to outStream\n // This is equivalent of connecting al the fields of the two streams\n // Every future assignment will overwrite the previous one\n outStream := inStream\n\n // Always ready to accept input\n inStream.ready := true.B\n\n // if (canPass) then { it can go out } else { it is not forwarded }\n outStream.valid := canPass && outStream.ready\n outStream.strb := inStream.strb(0) && canPass\n\n // All the other signals are forwarded\n // outStream.stai := inStream.stai\n // outStream.endi := inStream.endi\n // outStream.last := inStream.last\n // outStream.el := inStream.el\n}\n\n/\n Implementation, defined in pipelineSimple. Top level implementation. It\n * instantiates the subcomponents and connects them together.\n /\nclass PipelineSimple extends PipelineSimple_interface {\n inStream := DontCare\n outStream := DontCare // Probably not used\n in2Stream := DontCare\n\n // Modules\n private val filter = Module(new NonNegativeFilter)\n private val reducer = Module(new Reducer)\n\n // Connections\n filter.in := in // This will overload the inStream := in\n reducer.in := filter.out\n out := reducer.out // This will overload the out := outStream -> that's why outStream is not used\n}\n\n/\n Implementation, defined in pipelineSimple. Implementation of the agg\n * function.\n */\nclass Reducer extends Reducer_interface {\n // Set the data width to 64 bits, such as the [[MyTypes]] types\n private val dataWidth = 64.W\n\n // Computing min and max\n private val maxVal: BigInt = BigInt(Long.MaxValue) // Must work with BigInt or we get an overflow\n private val cMin: UInt = RegInit(maxVal.U(dataWidth)) // REG for the min value\n private val cMax: UInt = RegInit(0.U(dataWidth)) // REG for the max value\n // Computing the sum\n private val cSum: UInt = RegInit(0.U(dataWidth)) // REG for the sum\n // Computing the avg\n private val nValidSamples: Counter = Counter(Int.MaxValue) // The number of samples received (valid && strb(0))\n private val nSamples: Counter = Counter(Int.MaxValue) // The number of samples received (valid)\n\n // Set the streams IN ready and OUT valid signals\n // inReady = if (maxVal > 0) { true.B } else { false.B}\n inStream.ready := (if (maxVal > 0) true.B else false.B)\n // inStream.ready := true.B\n\n // The output is valid only if we have received at least one sample\n outStream.valid := nSamples.value > 0.U\n\n // When a value is received\n when(inStream.valid) {\n // Get the value from th input stream\n val value = inStream.el.value.asUInt\n nSamples.inc()\n\n // Check the strb line and perform the updates\n when(inStream.strb(0)) {\n cMin := cMin min value\n cMax := cMax max value\n cSum := cSum + value\n nValidSamples.inc()\n }\n }\n // Set the output stream\n outStream.el.sum := cSum\n outStream.el.min := cMin\n outStream.el.max := cMax\n outStream.el.average.value := Mux(nValidSamples.value > 0.U, cSum / nValidSamples.value, 0.U)\n\n // Set the output stream control signals:\n // they are fixed since the sum, min, max and average are updated every cycle\n // and they hold the same value if no change is performed\n outStream.strb := 1.U\n outStream.stai := 0.U\n outStream.endi := 1.U\n outStream.last(0) := inStream.last(0)\n}\n\nclass PipelineSimpleTest extends AnyFunSpec with Matchers {\n describe(\"ParametricSimulator\") {\n it(\"runs Pipeline Simple correctly\") {\n simulate(new PipelineSimple, Seq(VcdTrace, SaveWorkdirFile(\"aaa\"))) {\n dut => dut.clock.step()\n }\n }\n }\n\n describe(\"TywavesSimulator\") {\n it(\"runs Pipeline Simple correctly\") {\n import TywavesSimulator._\n\n simulate(\n new PipelineSimple(),\n Seq(VcdTrace, WithTywavesWaveforms(true)),\n simName = \"runs_GCD_correctly_launch_tywaves\",\n ) {\n dut => dut.clock.step()\n\n }\n }\n }\n\n}\n", "groundtruth": "class Generated_0_7_d3p7qsW3_29 extends BitsEl(64.W)\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/example/tydi-example.test.scala", "left_context": "//> using scala \"2.13.14\"\n//> using dep \"com.github.rameloni::tywaves-chisel-api:0.4.2-SNAPSHOT\"\n//> using dep \"nl.tudelft::tydi-chisel::0.1.0\"\n//> using plugin \"org.chipsalliance:::chisel-plugin:6.4.0\"\n//> using options \"-unchecked\", \"-deprecation\", \"-language:reflectiveCalls\", \"-feature\", \"-Xcheckinit\", \"-Xfatal-warnings\", \"-Ywarn-dead-code\", \"-Ywarn-unused\", \"-Ymacro-annotations\"\n//> using dep \"org.scalatest::scalatest:3.2.18\"\n\n// DO NOT EDIT THE ORTHER OF THESE IMPORTS (it will be solved in future versions)\nimport tywaves.simulator._\nimport tywaves.simulator.ParametricSimulator._\nimport tywaves.simulator.simulatorSettings._\nimport chisel3._\n\n// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._\n//import _root_.circt.stage.ChiselStage\nimport org.scalatest.funspec.AnyFunSpec\nimport org.scalatest.matchers.should.Matchers\n\nimport nl.tudelft.tydi_chisel._\nimport chisel3.util.Counter\n\nobject MyTypes {\n\n /** Bit(64) type, defined in pipelineSimple_types /\n", "right_context": "\n assert(this.generated_0_7_Tc5SbYQz_27.getWidth == 64)\n\n /* Bit(64) type, defined in pipelineSimple_types /\n def generated_0_7_d3p7qsW3_29 = SInt(64.W)\n\n assert(this.generated_0_7_d3p7qsW3_29.getWidth == 64)\n}\n\n/\n Group element, defined in pipelineSimple_types. A composite type (like a\n * struct) that contains a value associated with a timestamp.\n /\nclass NumberGroup extends Group {\n val time = MyTypes.generated_0_7_Tc5SbYQz_27\n val value = MyTypes.generated_0_7_d3p7qsW3_29\n}\n\n/\n Group element, defined in pipelineSimple_types. A composite type (like a\n * struct) that represents the stats of the implemented algorithm.\n /\nclass Stats extends Group {\n val average = MyTypes.generated_0_7_Tc5SbYQz_27\n val max = MyTypes.generated_0_7_Tc5SbYQz_27\n val min = MyTypes.generated_0_7_Tc5SbYQz_27\n val sum = MyTypes.generated_0_7_Tc5SbYQz_27\n}\n\n/* Stream, defined in pipelineSimple_types. /\nclass Generated_0_30_soHLkh1p_30\n extends PhysicalStreamDetailed(e = new Stats, n = 1, d = 1, c = 1, r = false, u = Null())\n\nobject Generated_0_30_soHLkh1p_30 {\n def apply(): Generated_0_30_soHLkh1p_30 = Wire(new Generated_0_30_soHLkh1p_30())\n}\n\n/* Stream, defined in pipelineSimple_types. /\nclass Generated_0_36_xeHH4woS_24\n extends PhysicalStreamDetailed(e = new NumberGroup, n = 1, d = 2, c = 1, r = false, u = Null())\n\nobject Generated_0_36_xeHH4woS_24 {\n def apply(): Generated_0_36_xeHH4woS_24 = Wire(new Generated_0_36_xeHH4woS_24())\n}\n\n/* Bit(64), defined in pipelineSimple_types. /\nclass Generated_0_7_Tc5SbYQz_27 extends BitsEl(64.W)\n\n/* Bit(64), defined in pipelineSimple_types. /\nclass Generated_0_7_d3p7qsW3_29 extends BitsEl(64.W)\n\n/\n Streamlet, defined in pipelineSimple. Top level interface.\n /\nclass PipelineSimple_interface extends TydiModule {\n\n /* Stream of [[in]] with input direction. /\n val inStream = Generated_0_36_xeHH4woS_24().flip\n\n /* IO of [[inStream]] with input direction. /\n val in = inStream.toPhysical\n\n /* Stream of [[out]] with output direction. /\n val outStream = Generated_0_30_soHLkh1p_30()\n\n /* IO of [[outStream]] with output direction. /\n val out = outStream.toPhysical\n}\n\n/\n Streamlet, defined in pipelineSimple. Interface for the agg function.\n /\nclass Reducer_interface extends TydiModule {\n\n /* Stream of [[in]] with input direction. /\n val inStream = Generated_0_36_xeHH4woS_24().flip\n\n /* IO of [[inStream]] with input direction. /\n val in = inStream.toPhysical\n\n /* Stream of [[out]] with output direction. /\n val outStream = Generated_0_30_soHLkh1p_30()\n\n /* IO of [[outStream]] with output direction. /\n val out = outStream.toPhysical\n}\n\n/\n Streamlet, defined in pipelineSimple. Interface for the non negative filter:\n * df.filter(col(\"value\") >= 0).\n /\nclass Instance_NonNegativeFilter_interface_RefToVargenerated_0_36_KLOZ7sts_25_1 extends TydiModule {\n\n /* Stream of [[in]] with input direction. /\n val inStream = Generated_0_36_xeHH4woS_24().flip\n\n /* IO of [[inStream]] with input direction. /\n val in = inStream.toPhysical\n\n /* Stream of [[out]] with output direction. /\n val outStream = Generated_0_36_xeHH4woS_24()\n\n /* IO of [[outStream]] with output direction. /\n val out = outStream.toPhysical\n}\n\n/\n Implementation, defined in pipelineSimple. Implementation of\n * df.filter(col(\"value\") >= 0).\n /\nclass NonNegativeFilter extends Instance_NonNegativeFilter_interface_RefToVargenerated_0_36_KLOZ7sts_25_1 {\n // Filtered only if the value is non-negative\n // inStream.valid tells us if the input is valid\n private val canPass: Bool = inStream.el.value >= 0.S && inStream.valid\n\n // Connect inStream to outStream\n // This is equivalent of connecting al the fields of the two streams\n // Every future assignment will overwrite the previous one\n outStream := inStream\n\n // Always ready to accept input\n inStream.ready := true.B\n\n // if (canPass) then { it can go out } else { it is not forwarded }\n outStream.valid := canPass && outStream.ready\n outStream.strb := inStream.strb(0) && canPass\n\n // All the other signals are forwarded\n // outStream.stai := inStream.stai\n // outStream.endi := inStream.endi\n // outStream.last := inStream.last\n // outStream.el := inStream.el\n}\n\n/\n Implementation, defined in pipelineSimple. Top level implementation. It\n * instantiates the subcomponents and connects them together.\n /\nclass PipelineSimple extends PipelineSimple_interface {\n inStream := DontCare\n outStream := DontCare // Probably not used\n\n // Modules\n private val filter = Module(new NonNegativeFilter)\n private val reducer = Module(new Reducer)\n\n // Connections\n filter.in := in // This will overload the inStream := in\n reducer.in := filter.out\n out := reducer.out // This will overload the out := outStream -> that's why outStream is not used\n}\n\n/\n Implementation, defined in pipelineSimple. Implementation of the agg\n * function.\n */\nclass Reducer extends Reducer_interface {\n // Set the data width to 64 bits, such as the [[MyTypes]] types\n private val dataWidth = 64.W\n\n // Computing min and max\n private val maxVal: BigInt = BigInt(Long.MaxValue) // Must work with BigInt or we get an overflow\n private val cMin: UInt = RegInit(maxVal.U(dataWidth)) // REG for the min value\n private val cMax: UInt = RegInit(0.U(dataWidth)) // REG for the max value\n // Computing the sum\n private val cSum: UInt = RegInit(0.U(dataWidth)) // REG for the sum\n // Computing the avg\n private val nValidSamples: Counter = Counter(Int.MaxValue) // The number of samples received (valid && strb(0))\n private val nSamples: Counter = Counter(Int.MaxValue) // The number of samples received (valid)\n\n // Set the streams IN ready and OUT valid signals\n // inReady = if (maxVal > 0) { true.B } else { false.B}\n inStream.ready := (if (maxVal > 0) true.B else false.B)\n // inStream.ready := true.B\n\n // The output is valid only if we have received at least one sample\n outStream.valid := nSamples.value > 0.U\n\n // When a value is received\n when(inStream.valid) {\n // Get the value from th input stream\n val value = inStream.el.value.asUInt\n nSamples.inc()\n\n // Check the strb line and perform the updates\n when(inStream.strb(0)) {\n cMin := cMin min value\n cMax := cMax max value\n cSum := cSum + value\n nValidSamples.inc()\n }\n }\n // Set the output stream\n outStream.el.sum := cSum\n outStream.el.min := cMin\n outStream.el.max := cMax\n outStream.el.average := Mux(nValidSamples.value > 0.U, cSum / nValidSamples.value, 0.U)\n\n // Set the output stream control signals:\n // they are fixed since the sum, min, max and average are updated every cycle\n // and they hold the same value if no change is performed\n outStream.strb := 1.U\n outStream.stai := 0.U\n outStream.endi := 1.U\n outStream.last(0) := inStream.last(0)\n}\n\nclass PipelineSimpleTest extends AnyFunSpec with Matchers {\n describe(\"ParametricSimulator\") {\n it(\"runs Pipeline Simple correctly\") {\n simulate(new PipelineSimple, Seq(VcdTrace, SaveWorkdirFile(\"pipelineSimpleWorkdir\"))) {\n dut => dut.clock.step()\n }\n }\n }\n\n describe(\"TywavesSimulator\") {\n it(\"runs Pipeline Simple correctly\") {\n import TywavesSimulator._\n\n simulate(\n new PipelineSimple(),\n Seq(VcdTrace, WithTywavesWaveforms(true)),\n simName = \"runs_GCD_correctly_launch_tywaves\",\n ) {\n dut => dut.clock.step()\n\n }\n }\n }\n\n}\n", "groundtruth": " def generated_0_7_Tc5SbYQz_27 = UInt(64.W)\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/main/scala/tywaves/circuitmapper/TypedConverter.scala", "left_context": "package tywaves.circuitmapper\n\nimport chisel3.RawModule\nimport chisel3.stage.ChiselGeneratorAnnotation\nimport tywaves.BuildInfo.firtoolBinaryPath\n\n/** This case class is used to store the top module name /\nprivate[tywaves] case class TopModuleName(private[circuitmapper] var name: Option[String])\n\n/* This object contains methods to create debug information from firtool /\nprivate[tywaves] object TypedConverter {\n private lazy val chiselStage = new circt.stage.ChiselStage(withDebug = true)\n\n private val chiselStageBaseArgs =\n Array(\"--target\", \"systemverilog\", \"--split-verilog\", \"--firtool-binary-path\", firtoolBinaryPath)\n\n val firtoolBaseArgs: Seq[String] =\n Seq(\"-O=debug\", \"-g\", \"--emit-hgldd\", \"--split-verilog\") // Run in debug mode compiled with optimizations\n // Directories where the debug information is stored\n private var hglddDebugDir = \"hgldd/debug\"\n private var hglddWithOptDir = \"hgldd/opt\" // TODO: remove\n private var workingDir: Option[String] = None\n private val topModuleName = TopModuleName(None)\n\n // Default firtool options encoded as annotations for ChiselStage\n private val defaultFirtoolOptAnno = createFirtoolOptions(firtoolBaseArgs)\n // \"-disable-annotation-unknown\",\n // \"--hgldd-output-prefix=<path>\",\n /,\"--output-final-mlir=WORK.mlir\"/\n\n // Map any sequence of string into FirtoolOptions\n private def createFirtoolOptions(args: Seq[String]) = args.map(circt.stage.FirtoolOption)\n\n /\n Create debug information from firtool by using the\n * [[circt.stage.ChiselStage]]\n /\n def createDebugInfoHgldd[T <: RawModule](\n generateModule: () => T,\n workingDir: String = \"workingDir\",\n additionalFirtoolArgs: Seq[String],\n ): Unit = {\n this.workingDir = Some(workingDir)\n hglddWithOptDir = workingDir + \"/\" + hglddWithOptDir\n hglddDebugDir = workingDir + \"/\" + hglddDebugDir\n // hglddDebugDir = workingDir + \"/\" + \"support-artifacts\"\n\n // Annotations for ChiselStage\n val annotations = Seq(ChiselGeneratorAnnotation(generateModule)) ++ defaultFirtoolOptAnno\n\n // Run without debug mode: TODO check it is actually not needed\n // chiselStage.execute(\n // chiselStageBaseArgs ++ Array(\"--target-dir\", hglddWithOptDir),\n // annotations,\n // ) // execute returns the passThrough annotations in CIRCT transform stage\n\n val finalAnno = chiselStage.execute(\n chiselStageBaseArgs ++ Array(\"--target-dir\", hglddDebugDir),\n createFirtoolOptions(additionalFirtoolArgs) ++ annotations,\n ) // execute returns the passThrough annotations in CIRCT transform stage\n\n // Get the module name\n topModuleName.name = finalAnno.collectFirst {\n case chisel3.stage.ChiselCircuitAnnotation(circuit) => circuit.name\n }\n }\n\n /* Get the directory where the debug information is stored /\n def getDebugInfoDir(gOpt: Boolean): String =\n if (gOpt) hglddDebugDir\n else hglddWithOptDir\n\n /\n Return the working directory used in the last call of\n * [[createDebugInfoHgldd]]\n /\n def getWorkingDir: Option[String] = workingDir\n\n /\n Return the top module name of the last circuit used in the last call of\n * [[createDebugInfoHgldd]]\n */\n", "right_context": "\n}\n", "groundtruth": " def getTopModuleName: Option[String] = topModuleName.name\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/main/scala/tywaves/simulator/ParametricSimulator.scala", "left_context": "package tywaves.simulator\n\nimport chisel3.RawModule\nimport chisel3.simulator.SingleBackendSimulator\nimport chisel3.simulator.PeekPokeAPI\nimport svsim._\n\nimport java.nio.file.Files\nimport java.time.{LocalDateTime, format}\n\n/*\n The interface object to the simulation.\n \n It uses [[svsim]] and [[PeekPokeAPI]] to run a simulation.\n /\nobject ParametricSimulator extends PeekPokeAPI {\n\n /* Use this method to run a simulations /\n def simulate[T <: RawModule](\n module: => T,\n settings: Seq[SimulatorSettings] = Seq(),\n simName: String = \"defaultSimulation\",\n )(body: T => Unit): Unit =\n (new ParametricSimulator).simulate(module, settings, simName)(body)\n}\n\n/\n A simulator that can be customized by passing some parameters through a list\n * of [[SimulatorSettings]]. It offers the possibility to:\n * - output a trace vcd file\n * - store the files generated during the simulation\n /\nclass ParametricSimulator {\n\n // Settings variable of the simulator\n private var _backendCompileSettings = verilator.Backend.CompilationSettings()\n private val _testRunDir = \"test_run_dir\"\n private var _moduleDutName = \"\"\n private val _simulatorName = getClass.getSimpleName.stripSuffix(\"$\")\n private var _simName = \"defaultSimulationName\"\n\n // Working directory and workspace\n private var _workdirFinalFile: Option[String] = None\n private var _workdir: Option[String] = None // Initialized when makeSimulator is called\n protected def wantedWorkspacePath: String =\n if (_workdirFinalFile.isDefined)\n Seq(_testRunDir, _moduleDutName, _simulatorName, _simName, _workdirFinalFile.get).mkString(\"/\")\n else\n Seq(_testRunDir, _moduleDutName, _simulatorName, _simName).mkString(\"/\")\n\n // Traces\n private var _traceExtension: Option[String] = None\n private var _traceWantedName: String = \"trace\"\n private var _finalTracePath: Option[String] = None\n\n def finalTracePath: Option[String] = _finalTracePath\n private def _emittedTraceRelPath: Option[String] =\n if (_workdir.isDefined && _traceExtension.isDefined)\n Some(Seq(_workdir.get, s\"trace.${_traceExtension.get}\").mkString(\"/\"))\n else None\n\n private var _firtoolArgs: Seq[String] = Seq()\n", "right_context": "\n /* Launch and execute a simulation given a list of [[SimulatorSettings]]. /\n def simulate[T <: RawModule](\n module: => T,\n settings: Seq[SimulatorSettings] = Seq(),\n simName: String,\n )(body: T => Unit): Unit = {\n\n // Set the initial settings before the simulation: i.e. backend compile settings\n setInitialSettings(settings)\n\n // Create a new simulator\n val simulator = makeSimulator\n simulator\n .simulate(module) { simulatedModule =>\n // Set the controller settings: i.e. enable trace\n setControllerSettings(simulatedModule.controller, settings)\n\n // Update the wanted workspace path\n _moduleDutName = simulatedModule.wrapped.name\n _simName = simName\n\n // Launch the actual simulation and return the result\n body(simulatedModule.wrapped)\n }\n .result\n\n // Cleanup the simulation after the execution\n simulator.cleanup()\n }\n\n /\n Set settings before the simulation starts. It sets the initial settings\n * such as the backend compile settings, trace style, etc.\n /\n private def setInitialSettings(settings: Seq[SimulatorSettings]): Unit = {\n settings.foreach {\n case t: TraceSetting =>\n _backendCompileSettings = verilator.Backend.CompilationSettings(\n traceStyle = Some(t.traceStyle),\n outputSplit = None,\n outputSplitCFuncs = None,\n disabledWarnings = Seq(),\n disableFatalExitOnWarnings = false,\n )\n // Set also the extension\n _traceExtension = Some(t.extension)\n\n case TraceName(name) =>\n if (\n !settings.exists {\n case _: TraceSetting => true\n case _ => false\n }\n ) throw new Exception(\"TraceName must be used with TraceSetting\")\n if (settings.count(_.isInstanceOf[TraceName]) > 1)\n throw new Exception(\"TraceName must be used only once\")\n _traceWantedName = name\n\n case SaveWorkspace(name) =>\n if (settings.count(_.isInstanceOf[SaveWorkspace]) > 1)\n throw new Exception(\"SaveWorkspace must be used only once\")\n if (name == \"\") // If no name is specified -> Current date time as default (gg-mm-ddThh:mm) no millis\n _workdirFinalFile =\n Some(LocalDateTime.now().format(format.DateTimeFormatter.ofPattern(\"dd_MM_yyyy:HH-mm-ss\")))\n else\n _workdirFinalFile = Some(name)\n\n case FirtoolArgs(args) => _firtoolArgs = args\n case _ =>\n }\n\n // If it contains underscore, add it to the trace name\n if (settings.contains(simulatorSettings.VcdTraceWithUnderscore))\n _traceWantedName = s\"${_traceWantedName}_underscore\"\n\n }\n\n /\n Set the controller settings. It sets settings such as the trace output\n * enable.\n /\n private def setControllerSettings(controller: Simulation.Controller, settings: Seq[SimulatorSettings]): Unit =\n settings.foreach {\n case _: TraceSetting => controller.setTraceEnabled(true)\n case _ => // Do nothing\n }\n\n /* Default ParametricSimulator /\n protected class DefaultParametricSimulator(val workspacePath: String, val tag: String)\n extends SingleBackendSimulator[verilator.Backend] {\n\n val backend: verilator.Backend = verilator.Backend.initializeFromProcessEnvironment()\n override val firtoolArgs: Seq[String] = _firtoolArgs\n\n val backendSpecificCompilationSettings: verilator.Backend.CompilationSettings = _backendCompileSettings\n val commonCompilationSettings: CommonCompilationSettings =\n CommonCompilationSettings(\n optimizationStyle = CommonCompilationSettings.OptimizationStyle.OptimizeForCompilationSpeed,\n availableParallelism = CommonCompilationSettings.AvailableParallelism.UpTo(4),\n defaultTimescale = Some(CommonCompilationSettings.Timescale.FromString(\"1ms/1ms\")),\n )\n\n /\n Cleanup the simulation and move the simulation workspace to the wanted\n * workspace path.\n /\n def cleanup(): Unit = {\n\n val workDirOld = os.Path(workspacePath)\n val workDir = os.pwd / os.RelPath(wantedWorkspacePath)\n\n // Check if the workspace must be saved or not\n if (_workdirFinalFile.isDefined)\n os.copy(workDirOld, workDir, replaceExisting = true, createFolders = true, mergeFolders = true)\n\n // Rename the wanted trace\n if (_traceExtension.isDefined) {\n val tracePath = workDirOld / os.RelPath(_emittedTraceRelPath.get)\n val wantedTracePath =\n os.pwd / os.RelPath(Seq(wantedWorkspacePath, s\"${_traceWantedName}.${_traceExtension.get}\").mkString(\"/\"))\n os.copy(tracePath, wantedTracePath, replaceExisting = true, createFolders = true)\n _finalTracePath = Some(wantedTracePath.toString)\n }\n\n }\n }\n\n /* Create a new simulator */\n protected def makeSimulator: DefaultParametricSimulator = { // def allows to create a new simulator each tim\n val className = _simulatorName\n val id = java.lang.management.ManagementFactory.getRuntimeMXBean.getName\n\n val tmpWorkspacePath = Files.createTempDirectory(s\"${className}_${id}_\").toString\n val tag = \"default\"\n val defaultSimulator = new DefaultParametricSimulator(tmpWorkspacePath, tag = tag)\n _workdir = Some(s\"${defaultSimulator.workingDirectoryPrefix}-$tag\")\n defaultSimulator\n }\n}\n", "groundtruth": " def getFirtoolArgs: Seq[String] = _firtoolArgs\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/main/scala/tywaves/simulator/ParametricSimulatorInterface.scala", "left_context": "package tywaves.simulator\n\nimport chisel3.RawModule\n\ntrait ParametricSimulatorInterface {\n private var simulator = new ParametricSimulator\n\n /** If true, the simulator will be reset before running each simulation /\n private var _resetSimulationBeforeRun = false\n\n /* Use this method to run a simulations /\n def simulate[T <: RawModule](\n module: => T,\n", "right_context": " Use this method to manually reset the simulator and run multiple\n * independent simulations\n */\n def reset(): Unit =\n simulator = new ParametricSimulator\n\n def resetBeforeEachRun(): Unit =\n _resetSimulationBeforeRun = true\n}\n", "groundtruth": " settings: Seq[SimulatorSettings] = Seq(),\n simName: String = \"defaultSimulation\",\n )(body: T => Unit): Unit = {\n if (_resetSimulationBeforeRun)\n reset()\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/main/scala/tywaves/simulator/SimulatorSettings.scala", "left_context": "package tywaves.simulator\n\nimport svsim.verilator\nimport verilator.Backend.CompilationSettings.TraceStyle\n\n/** Trait to represent the simulator settings /\ntrait SimulatorSettings\n\nprotected sealed trait TraceSetting extends SimulatorSettings {\n val traceStyle: TraceStyle\n val extension: String\n}\n\n/\n [[TraceVcd]] is an abstracted representation of the\n * [[verilator.Backend.CompilationSettings.TraceStyle.Vcd]] that can be used by\n * the user of the simulator.\n /\nprivate[simulator] case class TraceVcd(traceUnderscore: Boolean) extends TraceSetting with SimulatorSettings {\n val traceStyle: TraceStyle = TraceStyle.Vcd(traceUnderscore)\n val extension: String = \"vcd\"\n}\n\n/\n [[TraceName]] stores the name of the final trace file.\n /\nprivate[simulator] case class TraceName(name: String) extends SimulatorSettings\n\n/\n [[SaveWorkspace]] tells to save the workspace of the simulation and stores\n * the final name.\n /\nprivate[simulator] case class SaveWorkspace(name: String) extends SimulatorSettings\n\n/\n [[FirtoolArgs]] stores the arguments to pass to the firtool command.\n /\n", "right_context": "\n/\n Package object to expose the simulator settings to the user. The following\n * settings can be used by a simulator to allow users to configure the\n * simulation.\n */\npackage object simulatorSettings {\n // Interface to the simulation\n val VcdTrace: TraceVcd = TraceVcd(false)\n val VcdTraceWithUnderscore: TraceVcd = TraceVcd(true)\n\n val SaveWorkdirFile: String => SaveWorkspace = (name: String) => SaveWorkspace(name)\n val SaveWorkdir: SaveWorkspace = SaveWorkspace(\"\")\n\n val NameTrace: String => TraceName = (name: String) => TraceName(name)\n\n val WithFirtoolArgs: Seq[String] => FirtoolArgs = (args: Seq[String]) => FirtoolArgs(args)\n\n}\n", "groundtruth": "private[simulator] case class FirtoolArgs(args: Seq[String]) extends SimulatorSettings\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/main/scala/tywaves/simulator/TywavesInterface.scala", "left_context": "package tywaves.simulator\n\nimport scala.annotation.unused\n\nprivate[tywaves] object TywavesInterface {\n\n private val program = tywaves.BuildInfo.surferTywavesBinaryPath\n\n def run(\n vcdPath: String,\n hglddDirPath: Option[String],\n extraScopes: Seq[String],\n topModuleName: Option[String],\n waitFor: Boolean = true,\n ): Unit = {\n {\n import scala.sys.process._\n\n // Check if tywaves is installed\n val exitCode = s\"which $program\".!\n", "right_context": " case Some(_) => Some(\"--hgldd-dir\")\n case None => None\n }\n\n val extraScopesCmd = (extraScopes, topModuleName) match {\n case (Nil, _) \| (_, None) => Nil\n case _ => Seq(\"--extra-scopes\") ++ extraScopes ++\n Seq(\"--top-module\") ++ topModuleName\n }\n\n val cmd = Seq(program, vcdPath) ++ hglddDirCmd ++ hglddDirPath ++ extraScopesCmd\n\n // Execute and return to the caller\n @unused val process = new ProcessBuilder(cmd: _*).inheritIO().start()\n if (waitFor)\n process.waitFor()\n // No wait for the process to finish\n }\n}\n", "groundtruth": " if (exitCode != 0)\n throw new Exception(s\"$program not found on the PATH! Please install it running: make all\\n\")\n }\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/main/scala/tywaves/simulator/TywavesSimulator.scala", "left_context": "package tywaves.simulator\n\nimport chisel3.RawModule\nimport chisel3.simulator.PeekPokeAPI\nimport svsim.Workspace\nimport tywaves.circuitmapper.TypedConverter\n\nobject TywavesSimulator extends PeekPokeAPI {\n\n", "right_context": "\n /** Generate tywaves info and optionally run the waveform /\n val WithTywavesWaveforms: Boolean => Tywaves = (runWaves: Boolean) => Tywaves(runWaves, waitFor = true)\n\n /\n Generate tywaves info and optionally run the waveform without blocking sbt\n /\n val WithTywavesWaveformsGo: Boolean => Tywaves = (runWaves: Boolean) => Tywaves(runWaves, waitFor = false)\n\n /* Use this method to run a simulation */\n def simulate[T <: RawModule](\n module: => T,\n settings: Seq[SimulatorSettings] = Seq(),\n simName: String = \"defaultSimulation\",\n )(body: T => Unit): Unit = {\n\n // Create a new simulator instance\n val simulator = new TywavesSimulator\n\n val containTywaves = settings.exists(_.isInstanceOf[Tywaves])\n\n val finalSettings =\n if (containTywaves)\n settings ++ Seq(FirtoolArgs(TypedConverter.firtoolBaseArgs))\n // Seq(FirtoolArgs(Seq(\"-O=debug\", \"-g\", \"--emit-hgldd\", \"--split-verilog\", \"-o=WORK.v\")))\n else settings\n\n simulator.simulate(module, finalSettings, simName)(body)\n\n if (simulator.finalTracePath.nonEmpty && containTywaves) {\n // Get the extra scopes created by ChiselSim backend: TOP, svsimTestbench, dut\n val extraScopes = Seq(\"TOP\", Workspace.testbenchModuleName, \"dut\")\n\n // Create the debug info from the firtool and get the top module name\n // TODO: this may not be needed anymore, since the debug info can be generated directly from chiselsim, by giving the right options to firtool\n // But the problem is to call chiselstage with debug options\n TypedConverter.createDebugInfoHgldd(\n () => module,\n workingDir = simulator.wantedWorkspacePath,\n additionalFirtoolArgs = simulator.getFirtoolArgs,\n )\n\n // Run tywaves viewer if the Tywaves waveform generation is enabled by Tywaves(true)\n val (runWaves, waitFor) =\n if (finalSettings.contains(Tywaves(runWaves = true, waitFor = true))) { (true, true) }\n else if (finalSettings.contains(Tywaves(runWaves = true, waitFor = false))) { (true, false) }\n else { (false, false) }\n if (runWaves)\n TywavesInterface.run(\n vcdPath = simulator.finalTracePath.get,\n hglddDirPath = Some(TypedConverter.getDebugInfoDir(gOpt = true)),\n extraScopes = extraScopes,\n topModuleName = TypedConverter.getTopModuleName,\n waitFor = waitFor,\n )\n } else if (containTywaves)\n throw new Exception(\"Tywaves waveform generation requires a trace file. Please enable VcdTrace.\")\n\n }\n\n}\nclass TywavesSimulator extends ParametricSimulator\n", "groundtruth": " private[simulator] case class Tywaves(runWaves: Boolean, waitFor: Boolean) extends SimulatorSettings\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/main/scala/tywaves/utils/UniqueHashMap.scala", "left_context": "package tywaves.utils\n\nimport java.nio.file.Paths\nimport scala.collection.mutable\n\nclass UniqueHashMap[K, V] extends mutable.HashMap[K, V] {\n\n private val _debugList = new mutable.ListBuffer[(K, V)]()\n private val debugList = new mutable.ListBuffer[(K, V, Int)]()\n\n /** Same implementation of [[mutable.HashMap.put]] */\n def putOrReplace(key: K, value: V): Option[V] =\n super.put(key, value)\n\n override def put(key: K, value: V): Option[V] = {\n if (super.contains(key)) {\n this.foreach(Console.err.println(_))\n\n throw new Exception(s\"Key $key already exists in the map. This is likely a bug in the parser.\\n\" +\n s\"Probably a new ID mapping is needed or the element is parsed twice.\\n\" +\n s\"Val is $value.\")\n }\n if (_debugList.contains((key, value))) {\n // Get that element and update that element\n val index = _debugList.indexOf((key, value))\n debugList(index) = ((key, value, debugList(index)._3 + 1))\n } else {\n _debugList += ((key, value))\n debugList += ((key, value, 0))\n }\n super.put(key, value)\n }\n\n def dumpFile(file: String, header: String, append: Boolean = true): Unit = {\n val path = Paths.get(file)\n java.nio.file.Files.createDirectories(path.getParent)\n val bw = new java.io.BufferedWriter(new java.io.FileWriter(file, append))\n bw.write(s\"\\n$header\\n\")\n\n", "right_context": " println(s\"$key: $value\")\n }\n }\n def debugLog(): Unit =\n debugList.foreach(println)\n}\n", "groundtruth": " this.foreach { case (key, value) =>\n bw.write(s\"$key: $value\\n\")\n }\n bw.close()\n }\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/GetNameTest.scala", "left_context": "import chisel3.Bundle\nimport org.scalatest.flatspec.AnyFlatSpec\n\nimport scala.reflect.runtime.universe._\n", "right_context": "class GetNameTest extends AnyFlatSpec {\n behavior of \"GetNameTest\"\n def getClassName[T: TypeTag](obj: T): String = {\n val className = typeOf[T].typeSymbol.asClass.name.toString\n s\"$className\"\n }\n def getName(obj: Any): String =\n obj.getClass.getCanonicalName match {\n case null => \"Unknown Class Name\"\n case _ => obj.getClass.getCanonicalName\n }\n\n def printNames(obj: Bundle): Unit = {\n println(\"GetSimpleName: \" + obj.getClass.getSimpleName)\n println(\"GetName: \" + obj.getClass.getName)\n println(\"GetCanonicalName: \" + obj.getClass.getCanonicalName)\n println(\"GetTypeName: \" + obj.getClass.getTypeName)\n println(\"GetType: \" + obj.className)\n }\n\n it should \"get anonymous class name\" in {\n val anonBundle = new Bundle {}\n printNames(anonBundle)\n println(anonBundle.className)\n println(getClassName(anonBundle))\n// println(getClassName(an))\n }\n\n it should \"get named class name\" in {\n val namedBundle = new MyBundle\n printNames(namedBundle)\n println(getClassName(namedBundle))\n\n }\n\n it should \"get anonymous class name from named class\" in {\n val anonBundle = new MyBundle {}\n printNames(anonBundle)\n println(getClassName(anonBundle))\n\n }\n\n}\n", "groundtruth": "class MyBundle extends Bundle\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/bar/Bar.scala", "left_context": "package bar\n\nimport chisel3._\n\nclass Baz(n: Int) extends Bundle {\n val a = UInt(n.W)\n val b = UInt(n.W)\n\n val nestedBundle = new Bundle {\n val z = Bool()\n }\n}\n\nclass Bar extends Module {\n val io = IO(new Bundle {\n val a = Input(Bool())\n val b = Input(Bool())\n val out = Output(Bool())\n })\n\n val inputSum = IO(Input(new Baz(8)))\n val outputSum = IO(Output(SInt(8.W)))\n\n when(inputSum.nestedBundle.z === true.B) {\n outputSum := inputSum.a.asSInt + inputSum.b.asSInt\n }.otherwise {\n outputSum := inputSum.a.asSInt - inputSum.b.asSInt\n }\n", "right_context": "}\n\nobject MainBar extends App {\n import circt.stage.ChiselStage\n\n println(\n ChiselStage.emitSystemVerilog(\n new Bar,\n firtoolOpts = Array(\n \"-O=debug\",\n \"-g\",\n \"-emit-hgldd\",\n \"-output-final-mlir=Foo.mlir\",\n ),\n )\n )\n}\n", "groundtruth": "\n val cable =\n Wire(Bool()) // do not use reserved verilog words as val names (val wire) -> tywaves-demo does not work for them yet\n cable := io.a & io.b\n\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/bar/BarTest.scala", "left_context": "package bar\n\nimport org.scalatest.flatspec.AnyFlatSpec\nimport tywaves.simulator.ParametricSimulator._\nimport tywaves.simulator.simulatorSettings._\nimport chisel3.fromBooleanToLiteral\nimport tywaves.simulator.TywavesSimulator\n\nclass BarTest extends AnyFlatSpec {\n behavior of \"BarTest\"\n it should \"trace simple bar\" in {\n simulate(\n module = new Bar,\n settings = Seq(VcdTraceWithUnderscore, SaveWorkdir),\n simName = \"trace_simple_bar\",\n ) { c =>\n c.clock.step()\n c.io.a.poke(true)\n c.io.b.poke(false)\n c.io.out.expect(false.B)\n\n c.clock.step()\n c.io.a.poke(true)\n c.io.b.poke(true)\n c.io.out.expect(true.B)\n\n c.clock.step()\n c.clock.step(cycles = 10)\n }\n }\n\n it should \"trace simple bar with tywaves\" in {\n import tywaves.simulator.TywavesSimulator._\n\n simulate(\n module = new Bar,\n settings = Seq(VcdTraceWithUnderscore, SaveWorkdir, WithTywavesWaveforms(false)),\n simName = \"trace_simple_bar_with_tywaves\",\n ) { c =>\n c.clock.step()\n c.io.a.poke(true)\n c.io.b.poke(false)\n c.io.out.expect(false.B)\n\n c.clock.step()\n c.io.a.poke(true)\n c.io.b.poke(true)\n", "right_context": " c.clock.step(cycles = 10)\n }\n }\n}\n", "groundtruth": " c.io.out.expect(true.B)\n\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/foo/Foo.scala", "left_context": "package foo\n\nimport chisel3._\nimport circt.stage.ChiselStage\n\n", "right_context": "\nclass MyBundle extends Simple {\n val a = UInt(8.W)\n val b = UInt(8.W)\n val c = UInt(8.W)\n\n val bundle = new Bundle {\n val z = Bool()\n }\n}\n\nclass Foo extends Module {\n val x = IO(Input(Bool()))\n val s = IO(Input(new MyBundle))\n val io_a = Wire(Bool())\n\n val io = IO(new Bundle {\n val a = Input(Bool())\n val b = Input(Bool())\n val out = Output(UInt(8.W))\n })\n\n // val vec = VecInit(Seq.fill(4)(0.U(8.W)))\n // val reg = RegInit(0.U(8.W))\n\n dontTouch(io_a)\n // dontTouch(vec)\n\n io_a := 1.U\n io.out := io.a + io.b\n\n printf(p\"s: $s\\n\")\n}\n\nobject MainFoo extends App {\n\n println(\n ChiselStage.emitSystemVerilog(\n new Foo,\n firtoolOpts = Array(\n \"-O=debug\",\n \"-g\",\n \"-emit-hgldd\",\n \"-output-final-mlir=Fooa.mlir\",\n ),\n )\n )\n\n}\n", "groundtruth": "class Simple extends Bundle\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/foo/FooTest.scala", "left_context": "package foo\n\n// The high level simulation API: it uses svsim internally\nimport tywaves.simulator.ParametricSimulator._\nimport org.scalatest.flatspec.AnyFlatSpec\nimport tywaves.simulator.simulatorSettings._\n\nobject RunFoo {\n\n /** Run multiple times */\n def apply(c: => Foo): Unit = {\n // Inputs and expected results\n val a = Seq(0, 1, 0, 1)\n val b = Seq(0, 0, 1, 1)\n\n // Reset\n c.io.a.poke(false)\n c.io.b.poke(true)\n c.clock.step()\n\n for (i <- a.zip(b)) {\n c.io.a.poke(i._1)\n c.io.b.poke(i._2)\n c.clock.step()\n }\n }\n}\n\nclass FooTest extends AnyFlatSpec {\n behavior of \"FooTest\"\n\n it should \"trace with underscore\" in {\n // val testName = testNames.headOption.getOrElse(\"Unknown Test\")\n", "right_context": " simulate(new Foo, Seq(VcdTrace), simName = \"trace\") { c =>\n c.io.a.poke(true)\n c.io.b.poke(0)\n }\n }\n\n}\n", "groundtruth": " simulate(new Foo, Seq(VcdTraceWithUnderscore), simName = \"trace_with_underscore\") {\n println(\"Running test: \" + it)\n RunFoo(_)\n }\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/gcd/GCD.scala", "left_context": "package gcd\n\nimport chisel3._\n\n/** A simple module useful for testing Chisel generation and testing */\nclass GCD extends Module {\n val io = IO(new Bundle {\n val a = Input(UInt(32.W))\n val b = Input(UInt(32.W))\n val loadValues = Input(Bool())\n val result = Output(UInt(32.W))\n val resultIsValid = Output(Bool())\n })\n\n val x = Reg(UInt(32.W))\n val y = Reg(UInt(32.W))\n\n when(x > y)(x := x -% y).otherwise(y := y -% x)\n\n", "right_context": "\n io.result := x\n io.resultIsValid := y === 0.U\n}\n", "groundtruth": " when(io.loadValues) { x := io.a; y := io.b }\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/gcd/GCDTest.scala", "left_context": "package gcd\n\nimport org.scalatest.funspec.AnyFunSpec\nimport org.scalatest.matchers.must.Matchers\n\nimport tywaves.simulator._\nimport tywaves.simulator.ParametricSimulator._\nimport tywaves.simulator.simulatorSettings._\nimport chisel3._\n//import chisel3._\nclass GCDTest extends AnyFunSpec with Matchers {\n describe(\"ParametricSimulator\") {\n it(\"runs GCD correctly\") {\n simulate(new GCD(), Seq(VcdTrace, SaveWorkdirFile(\"gcdWorkDir\"))) { gcd =>\n", "right_context": " gcd.clock.step()\n gcd.io.loadValues.poke(0.B)\n gcd.clock.stepUntil(sentinelPort = gcd.io.resultIsValid, sentinelValue = 1, maxCycles = 10)\n gcd.io.resultIsValid.expect(true.B)\n gcd.io.result.expect(12)\n }\n }\n }\n\n describe(\"TywavesSimulator\") {\n it(\"runs GCD correctly\") {\n import TywavesSimulator._\n\n simulate(\n new GCD(),\n Seq(VcdTrace, WithTywavesWaveforms(false), WithFirtoolArgs(Seq(\"-g\", \"--emit-hgldd\")), SaveWorkdir),\n simName = \"runs_GCD_correctly\",\n ) {\n gcd =>\n gcd.io.a.poke(24.U)\n gcd.io.b.poke(36.U)\n gcd.io.loadValues.poke(1.B)\n gcd.clock.step()\n gcd.io.loadValues.poke(0.B)\n gcd.clock.stepUntil(sentinelPort = gcd.io.resultIsValid, sentinelValue = 1, maxCycles = 10)\n gcd.io.resultIsValid.expect(true.B)\n gcd.io.result.expect(12)\n }\n }\n }\n\n}\n", "groundtruth": " gcd.io.a.poke(24.U)\n gcd.io.b.poke(36.U)\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/hierarchicalmodules/Blink.scala", "left_context": "package hierarchicalmodules\n\nimport chisel3._\nimport chisel3.util.Counter\n\nclass Blink(period: Int) extends Module {\n assert(period > 0, \"limit must be greater than 0\")\n val io = IO(new Bundle {\n val enable: Bool = Input(Bool())\n val led: Bool = Output(Bool())\n })\n\n val cnt: Counter = Counter(period)\n val ledReg: Bool = RegInit(false.B)\n\n", "right_context": "object MainBlink extends App {\n import circt.stage.ChiselStage\n\n println(\n ChiselStage.emitSystemVerilog(\n new Blink(4),\n firtoolOpts = Array(\n \"-O=debug\",\n \"-g\",\n \"--disable-all-randomization\",\n \"--strip-debug-info\",\n ),\n )\n )\n}\n", "groundtruth": " when(io.enable) {\n when(cnt.inc() && cnt.value === (period - 1).U) {\n ledReg := ~ledReg\n }\n }\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/hierarchicalmodules/BlinkTest.scala", "left_context": "package hierarchicalmodules\n\nimport chisel3.fromBooleanToLiteral\nimport org.scalatest.funspec.AnyFunSpec\nimport org.scalatest.matchers.must.Matchers\n\nclass BlinkTest extends AnyFunSpec with Matchers {\n\n private def blinkTb(dut: => Blink): Unit = {\n import chisel3.simulator.PeekPokeAPI._\n dut.reset.poke(true.B)\n dut.io.enable.poke(true.B)\n dut.clock.step(5)\n dut.reset.poke(false.B)\n\n dut.io.led.expect(false.B)\n dut.clock.step() // 1\n dut.io.led.expect(false.B)\n dut.clock.step() // 2\n dut.io.led.expect(false.B)\n dut.clock.step() // 3\n dut.io.led.expect(false.B)\n dut.clock.step() // 4\n dut.io.led.expect(true.B)\n dut.clock.step() // 5\n dut.io.led.expect(true.B)\n dut.clock.step() // 6\n dut.io.led.expect(true.B)\n dut.clock.step()\n dut.clock.step(30)\n }\n\n describe(\"Blink with parametric simulator\") {\n import tywaves.simulator.ParametricSimulator._\n import tywaves.simulator.simulatorSettings._\n\n it(\"should work\") {\n simulate(\n new Blink(4),\n Seq(VcdTrace, WithFirtoolArgs(Seq(\"-O=debug\", \"-g\"))),\n simName = \"blink_with_parametric_sim_should_work\",\n ) { dut =>\n blinkTb(dut)\n }\n }\n } // end of describe(\"Blink with parametric simulator\")\n\n describe(\"Blink with tywaves simulator\") {\n import tywaves.simulator.TywavesSimulator._\n import tywaves.simulator.simulatorSettings._\n\n it(\"should work\") {\n simulate(\n new Blink(4),\n Seq(VcdTrace, WithTywavesWaveforms(false), SaveWorkdirFile(\"workdir\")),\n", "right_context": "", "groundtruth": " simName = \"blink_with_tywaves_sim_should_work\",\n ) { dut =>\n blinkTb(dut)\n }\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/hierarchicalmodules/MultiBlink.scala", "left_context": "package hierarchicalmodules\n\nimport chisel3._\n\nclass SubBlink(n: Int) extends Module {\n val io = IO(new Bundle {\n val enable = Input(Bool())\n val led = Output(Bool())\n })\n val blinkerx = Module(new Blink(n))\n\n blinkerx.io.enable := io.enable\n io.led := blinkerx.io.led\n}\n\nclass AnotherModule extends Module {\n val out = IO(Output(UInt(2.W)))\n\n val outReg = RegInit(false.B)\n outReg := ~outReg\n out := outReg\n}\nclass AMultiBlink extends Module {\n val io = IO(new Bundle {\n val enable: Bool = Input(Bool())\n val leds: UInt = Output(UInt(4.W))\n })\n\n val anotherModule: AnotherModule = Module(new AnotherModule)\n\n val blinker: SubBlink = Module(new SubBlink(5))\n val blinker2: Blink = Module(new Blink(3))\n val blinker3: Blink = Module(new Blink(2))\n\n blinker.io.enable := io.enable\n blinker2.io.enable := io.enable\n blinker3.io.enable := io.enable\n\n when(anotherModule.out === 1.U) {\n blinker.io.enable := false.B\n blinker2.io.enable := false.B\n }\n io.leds :=\n (blinker.io.led << 3).asUInt + (blinker.io.led << 2).asUInt + (blinker.io.led << 1).asUInt + (blinker.io.led << 0).asUInt\n\n}\n\nobject MainMultiBlink extends App {\n import circt.stage.ChiselStage\n\n println(\n", "right_context": " )\n}\n", "groundtruth": " ChiselStage.emitSystemVerilog(\n new AMultiBlink,\n firtoolOpts = Array(\n \"-O=debug\",\n \"-g\",\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/hierarchicalmodules/MultiBlinkTest.scala", "left_context": "package hierarchicalmodules\n\nimport chisel3.fromBooleanToLiteral\nimport org.scalatest.funspec.AnyFunSpec\nimport org.scalatest.matchers.must.Matchers\n\nclass MultiBlinkTest extends AnyFunSpec with Matchers {\n\n private def blinkTb(dut: => AMultiBlink): Unit = {\n import chisel3.simulator.PeekPokeAPI._\n dut.reset.poke(true.B)\n dut.io.enable.poke(false.B)\n dut.clock.step(5)\n dut.reset.poke(false.B)\n dut.io.enable.poke(true.B)\n\n dut.clock.step() // 1\n dut.clock.step() // 2\n dut.clock.step() // 3\n dut.clock.step() // 4\n", "right_context": "\n describe(\"Multi Blink with parametric simulator\") {\n import tywaves.simulator.ParametricSimulator._\n import tywaves.simulator.simulatorSettings._\n\n it(\"should work\") {\n simulate(\n new AMultiBlink,\n Seq(VcdTrace, WithFirtoolArgs(Seq(\"-O=debug\", \"-g\"))),\n simName = \"multiblink_with_parametric_sim_should_work\",\n ) { dut =>\n blinkTb(dut)\n }\n }\n } // end of describe(\"MultiBlink with parametric simulator\")\n\n describe(\"MultiBlink with tywaves simulator\") {\n import tywaves.simulator.TywavesSimulator._\n import tywaves.simulator.simulatorSettings._\n\n it(\"should work\") {\n simulate(\n new AMultiBlink,\n Seq(VcdTrace, WithTywavesWaveforms(false), SaveWorkdirFile(\"workdir\")),\n simName = \"multiblink_with_tywaves_sim_should_work\",\n ) { dut =>\n blinkTb(dut)\n }\n }\n } // end of describe(\"Blink with tywaves simulator\")\n}\n", "groundtruth": " dut.clock.step() // 5\n dut.clock.step() // 6\n dut.clock.step()\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/hierarchicalmodules/UseCounter.scala", "left_context": "package hierarchicalmodules\n\nimport chisel3.{Bits, Data, Module, Printable, UInt, UIntFactory, Wire, dontTouch, fromBooleanToLiteral, fromIntToWidth}\nimport chisel3.util.Counter\nimport org.scalatest.funspec.AnyFunSpec\nimport org.scalatest.matchers.must.Matchers\nimport tywaves.simulator.TraceVcd\n\nclass UseCounter extends AnyFunSpec with Matchers {\n\n class Char {\n val value: UInt = UInt(8.W)\n\n", "right_context": " }\n object Char {\n def apply(): Char = new Char\n }\n\n class MyCounter extends Module {\n import chisel3._\n\n val out: UInt = IO(Output(UInt(8.W)))\n\n val cnt: Counter = Counter(4)\n\n cnt.inc()\n out := cnt.value\n }\n\n describe(\"Blink with tywaves simulator\") {\n import tywaves.simulator.TywavesSimulator._\n import tywaves.simulator.simulatorSettings._\n\n it(\"should work\") {\n simulate(\n new MyCounter,\n Seq(VcdTrace, WithTywavesWaveforms(false), SaveWorkdirFile(\"workdir\")),\n simName = \"blink_with_tywaves_sim_should_work\",\n ) { dut =>\n dut.clock.step(10)\n }\n }\n }\n}\n", "groundtruth": " def apply: UInt = value\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/memories/BlockMem.scala", "left_context": "package memories\n\nimport chisel3._\nimport chisel3.util.log2Ceil\n\n\nclass MemIOBundle[T <: Data](depth: Int, t: T) extends Bundle {\n val rdAddr = Input(UInt(log2Ceil(depth).W))\n val rdData = Output(t)\n val wrEna = Input(Bool())\n val wrData = Input(t)\n", "right_context": "/** A simple module for testing memories in Tywaves */\nclass BlockMem[T <: Data](depth: Int, t: T) extends Module {\n val io = IO(new MemIOBundle(depth, t))\n\n val mem = SyncReadMem(depth, t)\n io.rdData := mem.read(io.rdAddr)\n\n when(io.wrEna) {\n mem.write(io.wrAddr, io.wrData)\n }\n}\n\n", "groundtruth": " val wrAddr = Input(UInt(log2Ceil(depth).W))\n}\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/memories/BlockMemTest.scala", "left_context": "package memories\n\nimport org.scalatest.funspec.AnyFunSpec\nimport org.scalatest.matchers.must.Matchers\n\nimport tywaves.simulator._\nimport tywaves.simulator.simulatorSettings._\nimport chisel3._\n\nclass BlockMemTest extends AnyFunSpec with Matchers {\n describe(\"TywavesSimulator\") {\n import TywavesSimulator._\n\n it(\"runs BlockMem of UInt8\") {\n val t = UInt(8.W)\n simulate(new BlockMem(15, t), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = \"runs_mem_uint8\")(dut =>\n dut.clock.step(2)\n )\n }\n\n it(\"runs BlockMem of Bundle\") {\n\n class ComplexElement extends Bundle {\n val a = new Bundle {\n val subA1 = UInt(8.W)\n val subA2 = SInt(8.W)\n }\n val payload = Bits(8.W)\n }\n\n val t = new ComplexElement\n simulate(\n new BlockMem(4, t),\n Seq(VcdTrace, WithTywavesWaveforms(false), SaveWorkdirFile(\"workdir\")),\n simName = \"runs_mem_bundle\",\n )(dut => dut.clock.step(2))\n }\n\n it(\"runs BlockMem of Vec\") {\n val t = Vec(4, UInt(8.W))\n simulate(new BlockMem(4, t), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = \"runs_mem_vec\")(dut =>\n dut.clock.step(2)\n )\n }\n\n it(\"runs BlockMem of Enum\") {\n object SelType extends ChiselEnum { val A, B, C = Value }\n val t = SelType()\n simulate(new BlockMem(4, t), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = \"runs_mem_enum\")(dut =>\n dut.clock.step(2)\n )\n }\n\n it(\"runs BlockMem of Enum in Bundle\") {\n object SelType extends ChiselEnum { val A, B, C = Value }\n class ComplexElement extends Bundle {\n val sel = SelType()\n val payload = Bits(8.W)\n }\n\n val t = new ComplexElement\n simulate(new BlockMem(4, t), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = \"runs_mem_enum_bundle\")(dut =>\n dut.clock.step(2)\n )\n }\n\n it(\"runs BlockMem of Enum in Vec\") {\n", "right_context": " val t = Vec(4, SelType())\n simulate(new BlockMem(4, t), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = \"runs_mem_enum_vec\")(dut =>\n dut.clock.step(2)\n )\n }\n\n it(\"runs BlockMem of Enum in 2D-Vec\") {\n<TARGET>\n val t = Vec(4, Vec(2, SelType()))\n simulate(new BlockMem(4, t), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = \"runs_mem_enum_2d_vec\")(dut =>\n dut.clock.step(2)\n )\n }\n\n }\n}\n", "groundtruth": " object SelType extends ChiselEnum { val A, B, C = Value }\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/tywaves/simulator/ImportSimulatorReverseOrder.scala", "left_context": "package tywaves.simulator\n\nimport gcd.GCD\nimport org.scalatest.funspec.AnyFunSpec\nimport org.scalatest.matchers.must.Matchers\n\nclass ImportSimulatorReverseOrder extends AnyFunSpec with Matchers {\n", "right_context": " gcd.io.loadValues.poke(true.B)\n }\n }\n it(\"Should import chisel after tywaves\") {\n import tywaves.simulator.TywavesSimulator._\n import chisel3._\n simulate(new GCD()) {\n gcd =>\n gcd.clock.step()\n gcd.io.loadValues.poke(true.B)\n }\n }\n }\n\n}\n", "groundtruth": " describe(\"Issue 27\") {\n it(\"Should import chisel before tywaves\") {\n import chisel3._\n import tywaves.simulator.TywavesSimulator._\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/tywaves/simulator/ParametricSimulatorSpec.scala", "left_context": "package tywaves.simulator\n\nimport tywaves.simulator.ParametricSimulator._\nimport tywaves.simulator.simulatorSettings._\nimport chisel3._\nimport org.scalatest.funspec.AnyFunSpec\nimport org.scalatest.matchers.must.Matchers\n\nimport java.nio.file.{Files, Paths}\n\nimport gcd.GCD\n\nclass ParametricSimulatorSpec extends AnyFunSpec with Matchers {\n\n private def gcdTb(gcd: => GCD): Unit = {\n gcd.io.a.poke(24.U)\n gcd.io.b.poke(36.U)\n gcd.io.loadValues.poke(1.B)\n gcd.clock.step()\n gcd.io.loadValues.poke(0.B)\n gcd.clock.stepUntil(sentinelPort = gcd.io.resultIsValid, sentinelValue = 1, maxCycles = 10)\n gcd.io.resultIsValid.expect(true.B)\n gcd.io.result.expect(12)\n }\n\n describe(\"ParametricSimulator Runs\") {\n\n it(\"runs GCD correctly without settings\") {\n simulate(new GCD())(gcd => gcdTb(gcd))\n }\n\n it(\"runs GCD with VCD trace file\") {\n simulate(new GCD(), Seq(VcdTrace))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/ParametricSimulator/defaultSimulation/trace.vcd\")))\n }\n\n it(\"runs GCD with VCD underscore trace\") {\n simulate(new GCD(), Seq(VcdTraceWithUnderscore))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/ParametricSimulator/defaultSimulation/trace_underscore.vcd\")))\n }\n\n it(\"runs GCD with VCD trace file with name\") {\n simulate(new GCD(), Seq(VcdTrace, NameTrace(\"gcdTbTraceName\")))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/ParametricSimulator/defaultSimulation/gcdTbTraceName.vcd\")))\n }\n\n it(\"runs underscore when VcdTrace and VcdTraceWithUnderscore are used\") {\n simulate(new GCD(), Seq(VcdTrace, VcdTraceWithUnderscore))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/ParametricSimulator/defaultSimulation/trace_underscore.vcd\")))\n\n simulate(new GCD(), Seq(VcdTraceWithUnderscore, VcdTrace))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/ParametricSimulator/defaultSimulation/trace_underscore.vcd\")))\n }\n\n it(\"runs GCD with VCD trace file with name and VCD underscore trace\") {\n simulate(new GCD(), Seq(VcdTrace, VcdTraceWithUnderscore, NameTrace(\"gcdTb1\")))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/ParametricSimulator/defaultSimulation/gcdTb1_underscore.vcd\")))\n\n simulate(new GCD(), Seq(VcdTraceWithUnderscore, VcdTrace, NameTrace(\"gcdTb2\")))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/ParametricSimulator/defaultSimulation/gcdTb2_underscore.vcd\")))\n\n simulate(new GCD(), Seq(NameTrace(\"gcdTb3\"), VcdTraceWithUnderscore, VcdTrace))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/ParametricSimulator/defaultSimulation/gcdTb3_underscore.vcd\")))\n }\n\n it(\"uses a name for the simulation\") {\n simulate(new GCD(), Seq(VcdTrace, NameTrace(\"gcdTb1\")), simName = \"use_a_name_for_the_simulation\")(gcd =>\n gcdTb(gcd)\n )\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/ParametricSimulator/use_a_name_for_the_simulation/gcdTb1.vcd\")))\n }\n\n", "right_context": " gcdTb(gcd)\n )\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/ParametricSimulator/defaultSimulation/myWorkdir2\")))\n assert(Files.exists(\n Paths.get(\"test_run_dir/GCD/ParametricSimulator/defaultSimulation/myWorkdir2/support-artifacts/GCD.dd\")\n ))\n }\n\n }\n\n describe(\"ParametricSimulator Exceptions\") {\n\n it(\"throws an exception when NameTrace is used without VcdTrace or VcdTraceWithUnderscore\") {\n intercept[Exception] {\n simulate(new GCD(), Seq(NameTrace(\"\")))(_ => gcdTb _)\n }\n }\n\n it(\"throws an exception with two or more NameTrace\") {\n intercept[Exception] {\n simulate(new GCD(), Seq(VcdTrace, NameTrace(\"a\"), NameTrace(\"b\")))(_ => gcdTb _)\n }\n }\n\n it(\"throws an exception with two or more SaveWorkdir\") {\n intercept[Exception] {\n simulate(new GCD(), Seq(SaveWorkdir, SaveWorkdir))(_ => gcdTb _)\n }\n }\n\n it(\"throws an exception with two or more SaveWorkdirFile\") {\n intercept[Exception] {\n simulate(new GCD(), Seq(SaveWorkdirFile(\"a\"), SaveWorkdirFile(\"b\")))(_ => gcdTb _)\n }\n }\n\n }\n}\n", "groundtruth": " it(\"save the workdir with a name\") {\n simulate(new GCD(), Seq(VcdTrace, SaveWorkdirFile(\"myWorkdir\")))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/ParametricSimulator/defaultSimulation/myWorkdir\")))\n }\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/tywaves/simulator/TywavesSimulatorSpec.scala", "left_context": "package tywaves.simulator\n\nimport tywaves.simulator.TywavesSimulator._\nimport tywaves.simulator.simulatorSettings._\nimport chisel3._\nimport gcd.GCD\nimport org.scalatest.funspec.AnyFunSpec\nimport org.scalatest.matchers.must.Matchers\n\nimport java.nio.file.{Files, Paths}\n\nclass TywavesSimulatorSpec extends AnyFunSpec with Matchers {\n\n private def gcdTb(gcd: => GCD): Unit = {\n gcd.io.a.poke(24.U)\n gcd.io.b.poke(36.U)\n gcd.io.loadValues.poke(1.B)\n gcd.clock.step()\n gcd.io.loadValues.poke(0.B)\n gcd.clock.stepUntil(sentinelPort = gcd.io.resultIsValid, sentinelValue = 1, maxCycles = 10)\n gcd.io.resultIsValid.expect(true.B)\n gcd.io.result.expect(12)\n }\n\n describe(\"New TywavesFunctionalities\") {\n\n it(\"runs GCD with waveform generation\") {\n simulate(new GCD(), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = \"runs_gcd_with_waveform_generation\") {\n gcd =>\n gcdTb(gcd)\n }\n\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/TywavesSimulator/runs_gcd_with_waveform_generation/trace.vcd\")))\n assert(Files.exists(\n Paths.get(\n \"test_run_dir/GCD/TywavesSimulator/runs_gcd_with_waveform_generation/hgldd/debug/GCD.dd\"\n )\n ))\n }\n\n it(\"runs GCD with waveform generation and custom name trace\") {\n simulate(\n new GCD(),\n Seq(VcdTrace, NameTrace(\"gcdTest\"), WithTywavesWaveforms(false)),\n simName = \"runs_gcd_with_waveform_generation\",\n ) { gcd =>\n gcdTb(gcd)\n }\n\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/TywavesSimulator/runs_gcd_with_waveform_generation/gcdTest.vcd\")))\n assert(Files.exists(\n Paths.get(\n \"test_run_dir/GCD/TywavesSimulator/runs_gcd_with_waveform_generation/hgldd/debug/GCD.dd\"\n )\n ))\n }\n\n it(\"raises an exception when Tywaves is used without VcdTrace\") {\n intercept[Exception] {\n simulate(new GCD(), Seq(WithTywavesWaveforms(false)))(_ => gcdTb _)\n }\n }\n\n }\n\n describe(\"Tywaves with ParametricSimulator Functionalities\") {\n\n it(\"runs GCD correctly without settings\") {\n simulate(new GCD())(gcd => gcdTb(gcd))\n }\n\n it(\"runs GCD with VCD trace file\") {\n simulate(new GCD(), Seq(VcdTrace))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/TywavesSimulator/defaultSimulation/trace.vcd\")))\n }\n\n it(\"runs GCD with VCD underscore trace\") {\n simulate(new GCD(), Seq(VcdTraceWithUnderscore))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/TywavesSimulator/defaultSimulation/trace_underscore.vcd\")))\n }\n\n it(\"runs GCD with VCD trace file with name\") {\n simulate(new GCD(), Seq(VcdTrace, NameTrace(\"gcdTbTraceName\")))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/TywavesSimulator/defaultSimulation/gcdTbTraceName.vcd\")))\n }\n\n it(\"runs underscore when VcdTrace and VcdTraceWithUnderscore are used\") {\n simulate(new GCD(), Seq(VcdTrace, VcdTraceWithUnderscore))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/TywavesSimulator/defaultSimulation/trace_underscore.vcd\")))\n\n simulate(new GCD(), Seq(VcdTraceWithUnderscore, VcdTrace))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/TywavesSimulator/defaultSimulation/trace_underscore.vcd\")))\n }\n\n it(\"runs GCD with VCD trace file with name and VCD underscore trace\") {\n simulate(new GCD(), Seq(VcdTrace, VcdTraceWithUnderscore, NameTrace(\"gcdTb1\")))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/TywavesSimulator/defaultSimulation/gcdTb1_underscore.vcd\")))\n\n simulate(new GCD(), Seq(VcdTraceWithUnderscore, VcdTrace, NameTrace(\"gcdTb2\")))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/TywavesSimulator/defaultSimulation/gcdTb2_underscore.vcd\")))\n\n simulate(new GCD(), Seq(NameTrace(\"gcdTb3\"), VcdTraceWithUnderscore, VcdTrace))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/TywavesSimulator/defaultSimulation/gcdTb3_underscore.vcd\")))\n }\n\n it(\"uses a name for the simulation\") {\n", "right_context": " simulate(new GCD(), Seq(VcdTrace, SaveWorkdirFile(\"myWorkdir\")))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/TywavesSimulator/defaultSimulation/myWorkdir\")))\n }\n\n it(\"uses firtool args\") {\n simulate(new GCD(), Seq(WithFirtoolArgs(Seq(\"-g\", \"--emit-hgldd\")), SaveWorkdirFile(\"myWorkdir2\")))(gcd =>\n gcdTb(gcd)\n )\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/TywavesSimulator/defaultSimulation/myWorkdir2\")))\n assert(Files.exists(\n Paths.get(\"test_run_dir/GCD/TywavesSimulator/defaultSimulation/myWorkdir2/support-artifacts/GCD.dd\")\n ))\n }\n\n }\n\n describe(\"TywavesSimulator Exceptions\") {\n it(\"throws an exception when NameTrace is used without VcdTrace or VcdTraceWithUnderscore\") {\n intercept[Exception] {\n simulate(new GCD(), Seq(NameTrace(\"\")))(_ => gcdTb _)\n }\n }\n\n it(\"throws an exception with two or more NameTrace\") {\n intercept[Exception] {\n simulate(new GCD(), Seq(VcdTrace, NameTrace(\"a\"), NameTrace(\"b\")))(_ => gcdTb _)\n }\n }\n\n it(\"throws an exception with two or more SaveWorkdir\") {\n intercept[Exception] {\n simulate(new GCD(), Seq(SaveWorkdir, SaveWorkdir))(_ => gcdTb _)\n }\n }\n\n it(\"throws an exception with two or more SaveWorkdirFile\") {\n intercept[Exception] {\n simulate(new GCD(), Seq(SaveWorkdirFile(\"a\"), SaveWorkdirFile(\"b\")))(_ => gcdTb _)\n }\n }\n\n }\n}\n", "groundtruth": " simulate(new GCD(), Seq(VcdTrace, NameTrace(\"gcdTb1\")), simName = \"use_a_name_for_the_simulation\")(gcd =>\n gcdTb(gcd)\n )\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/TywavesSimulator/use_a_name_for_the_simulation/gcdTb1.vcd\")))\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ethcontroller/design/EthRxController.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.design\n\nimport Chisel._\nimport ethcontroller.interfaces.MIIChannel\nimport ethcontroller.protocols.EthernetConstants\nimport ocp._\n\n/*\n The RX channel of the Ethernet controller manages both\n * the RX MII channel and implements FIFO access to the connected buffers\n \n @param numFrameBuffers the numbers of buffers used\n * @param timeStampWidth the timestamp bit-width\n /\nclass EthRxController(numFrameBuffers: Int, timeStampWidth: Int) extends Module {\n val io = new Bundle() {\n val ocp = new OcpCoreSlavePort(32, 32)\n val ramPorts = Vec.fill(numFrameBuffers) {\n new OcpCoreMasterPort(32, 32)\n }\n val miiChannel = new MIIChannel().asInput\n val rtcTimestamp = UInt(INPUT, width = timeStampWidth)\n }\n\n /\n Constants and types defs\n /\n val constRamIdWidth = log2Ceil(numFrameBuffers)\n val constRamAddrWidth = log2Ceil(EthernetConstants.constEthFrameLength)\n val stWaitSFD :: stCollectPayload :: Nil = Enum(UInt(), 2)\n val miiRx = Module(new MIIRx())\n\n /\n Registers\n /\n val stateReg = Reg(init = stWaitSFD)\n val ethByteReg = RegEnable(miiRx.io.ethByte, miiRx.io.ethByteDv)\n val ethByteDvReg = Reg(next = miiRx.io.ethByteDv)\n val ocpMasterReg = Reg(next = io.ocp.M)\n val wrRamIdReg = Reg(init = UInt(0, width = constRamIdWidth))\n val rdRamIdReg = Reg(init = UInt(0, width = constRamIdWidth))\n val byteCntReg = Reg(init = UInt(0, width = constRamAddrWidth))\n val ramMasterRegs = Vec.fill(numFrameBuffers) {\n Reg(new OcpCoreMasterSignals(constRamAddrWidth, 32))\n }\n val ocpDataReg = Reg(init = Bits(0, width = 32))\n val ocpRespReg = Reg(init = OcpResp.NULL)\n val rxEnReg = Reg(init = true.B)\n val rxFrameSizeReg = Reg(init = UInt(0, width = constRamAddrWidth)) //bytes\n val fifoCountReg = Reg(init = UInt(0, width = constRamIdWidth + 1))\n val fifoEmptyReg = Reg(init = true.B)\n val fifoFullReg = Reg(init = false.B)\n val fifoPopReg = Reg(init = false.B)\n val fifoPushReg = Reg(init = false.B)\n val macRxFilterReg = Reg(init = UInt(0, width = EthernetConstants.constEthMacLength))\n val ethRxCtrlRegMap = Map(\n \"rxEn\" -> Map(\"Reg\" -> rxEnReg, \"Addr\" -> Bits(\"h00\")),\n \"frameSize\" -> Map(\"Reg\" -> rxFrameSizeReg, \"Addr\" -> Bits(\"h01\")),\n \"fifoCount\" -> Map(\"Reg\" -> fifoCountReg, \"Addr\" -> Bits(\"h02\")),\n \"fifoEmpty\" -> Map(\"Reg\" -> fifoEmptyReg, \"Addr\" -> Bits(\"h03\")),\n \"fifoFull\" -> Map(\"Reg\" -> fifoFullReg, \"Addr\" -> Bits(\"h04\")),\n \"fifoPop\" -> Map(\"Reg\" -> fifoPopReg, \"Addr\" -> Bits(\"h05\")),\n \"fifoPush\" -> Map(\"Reg\" -> fifoPushReg, \"Addr\" -> Bits(\"h06\")),\n \"macFilter\" -> Map(\"Reg\" -> macRxFilterReg, \"Addr\" -> Bits(\"h07\"))\n )\n\n\n /\n Fifo Management\n /\n fifoEmptyReg := fifoCountReg === 0.U\n fifoFullReg := fifoCountReg === numFrameBuffers.U\n\n /\n State machine Control\n /\n val ramWrSelOH = UIntToOH(wrRamIdReg)\n val ramRdSelOH = UIntToOH(rdRamIdReg)\n\n val ocpSelRam = ~ocpMasterReg.Addr(constRamAddrWidth) && ocpMasterReg.Cmd =/= OcpCmd.IDLE\n val validRamPop = fifoPopReg && !fifoEmptyReg\n val validRamPush = fifoPushReg && !fifoFullReg\n\n val ethRamWrEn = ethByteDvReg && stateReg === stCollectPayload\n val ocpRamRdEn = ocpMasterReg.Cmd === OcpCmd.RD && ocpSelRam\n\n fifoPushReg := false.B\n fifoPopReg := false.B\n switch(stateReg) {\n is(stWaitSFD) {\n when(miiRx.io.ethSof && !fifoFullReg) {\n stateReg := stCollectPayload\n }\n }\n is(stCollectPayload) {\n when(miiRx.io.ethEof) {\n stateReg := stWaitSFD\n rxFrameSizeReg := byteCntReg\n byteCntReg := 0.U\n fifoPushReg := true.B\n }\n }\n }\n\n when(ethRamWrEn) {\n byteCntReg := byteCntReg + 1.U\n }\n\n\n when(validRamPop) {\n rdRamIdReg := rdRamIdReg + 1.U\n fifoCountReg := fifoCountReg - 1.U\n }\n\n when(validRamPush) {\n wrRamIdReg := wrRamIdReg + 1.U\n fifoCountReg := fifoCountReg + 1.U\n }\n\n /\n Ram Master Control\n /\n for (ramId <- 0 until numFrameBuffers) {\n ramMasterRegs(ramId).Addr := RegNext(Mux(ramId.U === wrRamIdReg && ocpSelRam, byteCntReg(constRamAddrWidth - 1, 2), ocpMasterReg.Addr(constRamAddrWidth - 1, 2)))\n ramMasterRegs(ramId).ByteEn := RegNext(Mux(ramId.U === wrRamIdReg && ocpSelRam, UIntToOH(byteCntReg(1, 0), width = 4), Mux(ocpRamRdEn, ocpMasterReg.ByteEn, Bits(\"b0000\"))))\n", "right_context": "\n /\n Regs Master Control\n /\n ocpRespReg := OcpResp.NULL\n when(ocpSelRam) {\n ocpDataReg := io.ramPorts(rdRamIdReg).S.Data\n ocpRespReg := Mux(!fifoFullReg, io.ramPorts(rdRamIdReg).S.Resp, OcpResp.FAIL)\n }.otherwise {\n when(ocpMasterReg.Cmd === OcpCmd.RD) {\n ocpRespReg := OcpResp.DVA\n when(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"rxEn\")(\"Addr\")) {\n ocpDataReg := ethRxCtrlRegMap(\"rxEn\")(\"Reg\")\n }.elsewhen(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"frameSize\")(\"Addr\")) {\n ocpDataReg := ethRxCtrlRegMap(\"frameSize\")(\"Reg\")\n }.elsewhen(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"fifoCount\")(\"Addr\")) {\n ocpDataReg := ethRxCtrlRegMap(\"fifoCount\")(\"Reg\")\n }.elsewhen(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"fifoEmpty\")(\"Addr\")) {\n ocpDataReg := ethRxCtrlRegMap(\"fifoEmpty\")(\"Reg\")\n }.elsewhen(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"fifoFull\")(\"Addr\")) {\n ocpDataReg := ethRxCtrlRegMap(\"fifoFull\")(\"Reg\")\n }.elsewhen(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"fifoPop\")(\"Addr\")) {\n ocpDataReg := ethRxCtrlRegMap(\"fifoPop\")(\"Reg\")\n }.elsewhen(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"fifoPush\")(\"Addr\")) {\n ocpDataReg := ethRxCtrlRegMap(\"fifoPush\")(\"Reg\")\n }.elsewhen(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"macFilter\")(\"Addr\")) {\n ocpDataReg := ethRxCtrlRegMap(\"macFilter\")(\"Reg\")\n }\n }.elsewhen(ocpMasterReg.Cmd === OcpCmd.WR) {\n when(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"rxEn\")(\"Addr\")) {\n ethRxCtrlRegMap(\"rxEn\")(\"Reg\") := ocpMasterReg.Data.orR\n ocpRespReg := OcpResp.DVA\n }.elsewhen(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"frameSize\")(\"Addr\")) {\n ocpRespReg := OcpResp.ERR\n }.elsewhen(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"fifoCount\")(\"Addr\")) {\n ocpRespReg := OcpResp.ERR\n }.elsewhen(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"fifoEmpty\")(\"Addr\")) {\n ocpRespReg := OcpResp.ERR\n }.elsewhen(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"fifoFull\")(\"Addr\")) {\n ocpRespReg := OcpResp.ERR\n }.elsewhen(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"fifoPop\")(\"Addr\")) {\n ethRxCtrlRegMap(\"fifoPop\")(\"Reg\") := true.B //set on write and reset in the next clock cycle\n ocpRespReg := OcpResp.DVA //is the responsibility of the master to check first the count ?\n }.elsewhen(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"fifoPush\")(\"Addr\")) {\n ocpRespReg := OcpResp.ERR\n }.elsewhen(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"macFilter\")(\"Addr\")) {\n ethRxCtrlRegMap(\"macFilter\")(\"Reg\") := ocpMasterReg.Data\n ocpRespReg := OcpResp.DVA\n }\n }.otherwise {\n ocpRespReg := OcpResp.NULL\n }\n }\n\n /\n I/O plumbing\n */\n io.ocp.S.Data := ocpDataReg\n io.ocp.S.Resp := ocpRespReg\n miiRx.io.miiChannel <> io.miiChannel\n miiRx.io.rxEn := ethRxCtrlRegMap(\"rxEn\")(\"Reg\")\n for (ramId <- 0 until numFrameBuffers) {\n io.ramPorts(ramId).M := ramMasterRegs(ramId)\n }\n}\n\nobject EthRxController extends App {\n chiselMain(Array[String](\"--backend\", \"v\", \"--targetDir\", \"generated/\" + this.getClass.getSimpleName.dropRight(1)),\n () => Module(new EthRxController(2, 64)))\n}\n", "groundtruth": " ramMasterRegs(ramId).Cmd := RegNext(Mux(ramId.U === wrRamIdReg && ocpSelRam, OcpCmd.WR, Mux(ocpRamRdEn, OcpCmd.RD, OcpCmd.IDLE)))\n ramMasterRegs(ramId).Data := RegNext(ethByteReg)\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ethcontroller/design/EthTxController.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.design\n\nimport Chisel._\nimport ethcontroller.interfaces.MIIChannel\nimport ethcontroller.protocols.EthernetConstants\nimport ocp._\n\n/*\n The TX channel of the Ethernet controller manages both\n * the TX MII channel and implements FIFO access to the connected buffers\n \n @param numFrameBuffers the numbers of buffers used\n * @param timeStampWidth the timestamp bit-width\n /\nclass EthTxController(numFrameBuffers: Int, timeStampWidth: Int) extends Module {\n val io = new Bundle() {\n val ocp = new OcpCoreSlavePort(32, 32)\n val ramPorts = Vec.fill(numFrameBuffers) {\n new OcpCoreMasterPort(32, 32)\n }\n val miiChannel = new MIIChannel()\n val rtcTimestamp = UInt(INPUT, width = timeStampWidth)\n }\n\n\n /\n Constants and types defs\n /\n val constRamIdWidth = log2Ceil(numFrameBuffers)\n val constRamAddrWidth = log2Ceil(EthernetConstants.constEthFrameLength)\n val stWait :: stTxPreamble :: stTxFrame :: stTxFCS :: stIFG :: stEoF :: Nil = Enum(UInt(), 6)\n val miiTx = Module(new MIITx())\n\n /\n Registers\n /\n val stateReg = Reg(init = stWait)\n val ocpMasterReg = Reg(next = io.ocp.M)\n val wrRamIdReg = Reg(init = UInt(0, width = constRamIdWidth))\n val rdRamIdReg = Reg(init = UInt(0, width = constRamIdWidth))\n val byteCntReg = Reg(init = UInt(0, width = constRamAddrWidth))\n val ethRamRdEn = Reg(init = false.B)\n val ramMasterRegs = Vec.fill(numFrameBuffers) {\n Reg(new OcpCoreMasterSignals(constRamAddrWidth, 32))\n }\n val ocpDataReg = Reg(init = Bits(0, width = 32))\n val ocpRespReg = Reg(init = OcpResp.NULL)\n\n val ramDataReg = Reg(init = Bits(0, width = 32))\n val ramRespReg = Reg(init = OcpResp.NULL)\n\n val txEnReg = Reg(init = true.B)\n val txFrameSizeReg = Reg(init = UInt(0, width = constRamAddrWidth)) //bytes\n val fifoCountReg = Reg(init = UInt(0, width = constRamIdWidth + 1))\n val fifoEmptyReg = Reg(init = true.B)\n val fifoFullReg = Reg(init = false.B)\n val fifoPopReg = Reg(init = false.B)\n val fifoPushReg = Reg(init = false.B)\n val macRxFilterReg = Reg(init = UInt(0, width = EthernetConstants.constEthMacLength))\n\n val ethTxCtrlRegMap = Map(\n \"txEn\" -> Map(\"Reg\" -> txEnReg, \"Addr\" -> Bits(\"h00\")), //0x0\n \"frameSize\" -> Map(\"Reg\" -> txFrameSizeReg, \"Addr\" -> Bits(\"h04\")), //0x4\n \"fifoCount\" -> Map(\"Reg\" -> fifoCountReg, \"Addr\" -> Bits(\"h08\")), //0x8\n \"fifoEmpty\" -> Map(\"Reg\" -> fifoEmptyReg, \"Addr\" -> Bits(\"h0C\")), //0xC\n \"fifoFull\" -> Map(\"Reg\" -> fifoFullReg, \"Addr\" -> Bits(\"h10\")), //0x10\n \"fifoPop\" -> Map(\"Reg\" -> fifoPopReg, \"Addr\" -> Bits(\"h14\")), //0x14\n \"fifoPush\" -> Map(\"Reg\" -> fifoPushReg, \"Addr\" -> Bits(\"h18\")), //0x18\n \"macFilter\" -> Map(\"Reg\" -> macRxFilterReg, \"Addr\" -> Bits(\"h1C\")) //0x1C\n )\n\n val preambleReg = Reg(init = UInt(EthernetConstants.constSFD, width = 64))\n val fcsReg = Reg(init = UInt(0, width = 16))\n\n val miiByteDataReg = Reg(init = UInt(0, width = 8))\n val miiByteLoadReg = Reg(init = false.B)\n val miiIsReady = Wire(init = false.B)\n\n /\n Fifo Management\n /\n fifoEmptyReg := fifoCountReg === 0.U\n fifoFullReg := fifoCountReg === numFrameBuffers.U\n\n val ocpSelRam = ~ocpMasterReg.Addr(constRamAddrWidth) && ocpMasterReg.Cmd =/= OcpCmd.IDLE\n val validRamPop = fifoPopReg === true.B && !fifoEmptyReg\n val validRamPush = fifoPushReg === true.B && !fifoFullReg\n\n //Reset regs to default values\n fifoPushReg := false.B\n fifoPopReg := false.B\n miiByteLoadReg := false.B\n //State Machine\n switch(stateReg) {\n is(stWait) { //wait for available data in FIFORam\n when(!fifoEmptyReg) {\n stateReg := stTxPreamble\n }\n }\n is(stTxPreamble) {\n when(miiIsReady & ~miiByteLoadReg) { //wait until miiIsReady and then countup the PREAMBLE\n when(byteCntReg < 8.U) {\n miiByteLoadReg := true.B\n byteCntReg := byteCntReg + 1.U\n }.otherwise {\n byteCntReg := 0.U\n ethRamRdEn := true.B\n stateReg := stTxFrame\n }\n }\n }\n is(stTxFrame) {\n when(ramRespReg === OcpResp.DVA) {\n when(miiIsReady) {\n when(byteCntReg < txFrameSizeReg) {\n byteCntReg := byteCntReg + 1.U\n }.otherwise {\n byteCntReg := 0.U\n stateReg := stTxFrame\n }\n }\n }\n }\n is(stTxFCS) {\n when(miiIsReady) {\n when(byteCntReg < 4.U) {\n byteCntReg := byteCntReg + 1.U\n }.otherwise {\n byteCntReg := 0.U\n ethRamRdEn := false.B\n stateReg := stEoF\n }\n }\n }\n is(stEoF) {\n stateReg := stIFG\n }\n is(stIFG) {\n when(byteCntReg < 24.U) {\n byteCntReg := byteCntReg + 1.U\n }.otherwise {\n byteCntReg := 0.U\n stateReg := stWait\n fifoPopReg := true.B\n }\n }\n }\n\n when(validRamPush) {\n wrRamIdReg := wrRamIdReg + 1.U\n fifoCountReg := fifoCountReg + 1.U\n }\n\n when(validRamPop) {\n rdRamIdReg := rdRamIdReg + 1.U\n fifoCountReg := fifoCountReg - 1.U\n }\n\n\n /\n Multiplexing MII byte source\n /\n miiByteDataReg := RegNext(Mux(stateReg === stTxFCS, preambleReg(8.U + 8.U byteCntReg - 1.U, 8.U * byteCntReg),\n Mux(stateReg === stTxFCS, fcsReg(8.U + 8.U * byteCntReg - 1.U, 8.U * byteCntReg), ramDataReg)))\n\n\n /*\n Ram master-port Control\n /\n for (ramId <- 0 until numFrameBuffers) {\n ramMasterRegs(ramId).Cmd := Mux(ramId.U === wrRamIdReg && ocpSelRam, ocpMasterReg.Cmd, Mux(ethRamRdEn, OcpCmd.RD, OcpCmd.IDLE))\n ramMasterRegs(ramId).Addr := Mux(ramId.U === wrRamIdReg && ocpSelRam, ocpMasterReg.Addr(constRamAddrWidth - 1, 2), byteCntReg(constRamAddrWidth - 1, 2))\n ramMasterRegs(ramId).ByteEn := Mux(ramId.U === wrRamIdReg && ocpSelRam, ocpMasterReg.ByteEn, UIntToOH(byteCntReg(1, 0), width = 4))\n ramMasterRegs(ramId).Data := ocpMasterReg.Data\n }\n\n /\n Ram slave-port Control\n /\n ramDataReg := io.ramPorts(rdRamIdReg).S.Data\n ramRespReg := io.ramPorts(rdRamIdReg).S.Resp\n\n /\n Regs Master Control\n /\n ocpRespReg := OcpResp.NULL\n when(ocpSelRam) {\n ocpDataReg := io.ramPorts(wrRamIdReg).S.Data\n ocpRespReg := Mux(!fifoFullReg, io.ramPorts(wrRamIdReg).S.Resp, OcpResp.FAIL)\n }.otherwise {\n when(ocpMasterReg.Cmd === OcpCmd.RD) {\n ocpRespReg := OcpResp.DVA\n when(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"txEn\")(\"Addr\")) {\n ocpDataReg := ethTxCtrlRegMap(\"txEn\")(\"Reg\")\n }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"frameSize\")(\"Addr\")) {\n ocpDataReg := ethTxCtrlRegMap(\"frameSize\")(\"Reg\")\n }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"fifoCount\")(\"Addr\")) {\n ocpDataReg := ethTxCtrlRegMap(\"fifoCount\")(\"Reg\")\n", "right_context": " ocpDataReg := ethTxCtrlRegMap(\"fifoPop\")(\"Reg\")\n }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"fifoPush\")(\"Addr\")) {\n ocpDataReg := ethTxCtrlRegMap(\"fifoPush\")(\"Reg\")\n }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"macFilter\")(\"Addr\")) {\n ocpDataReg := ethTxCtrlRegMap(\"macFilter\")(\"Reg\")\n }\n }.elsewhen(ocpMasterReg.Cmd === OcpCmd.WR) {\n when(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"txEn\")(\"Addr\")) {\n ethTxCtrlRegMap(\"txEn\")(\"Reg\") := orR(ocpMasterReg.Data)\n ocpRespReg := OcpResp.DVA\n }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"frameSize\")(\"Addr\")) {\n ethTxCtrlRegMap(\"frameSize\")(\"Reg\") := ocpDataReg\n ocpRespReg := OcpResp.DVA\n }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"fifoCount\")(\"Addr\")) {\n ocpRespReg := OcpResp.ERR\n }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"fifoEmpty\")(\"Addr\")) {\n ocpRespReg := OcpResp.ERR\n }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"fifoFull\")(\"Addr\")) {\n ocpRespReg := OcpResp.ERR\n }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"fifoPop\")(\"Addr\")) {\n ocpRespReg := OcpResp.ERR\n }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"fifoPush\")(\"Addr\")) {\n ethTxCtrlRegMap(\"fifoPush\")(\"Reg\") := orR(ocpMasterReg.Data) //set on write and reset in the next clock cycle\n ocpRespReg := OcpResp.DVA //is the responsibility of the master to check first the count ?\n }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"macFilter\")(\"Addr\")) {\n ethTxCtrlRegMap(\"macFilter\")(\"Reg\") := ocpMasterReg.Data\n ocpRespReg := OcpResp.DVA\n }\n }.otherwise {\n ocpRespReg := OcpResp.NULL\n }\n }\n\n /\n IO Plumbing\n */\n io.ocp.S.Data := ocpDataReg\n io.ocp.S.Resp := ocpRespReg\n miiIsReady := miiTx.io.ready\n miiTx.io.macDataDv := miiByteLoadReg\n miiTx.io.macData := miiByteDataReg\n miiTx.io.miiChannel <> io.miiChannel\n for (ramId <- 0 until numFrameBuffers) {\n io.ramPorts(ramId).M := ramMasterRegs(ramId)\n }\n}\n\nobject EthTxController extends App {\n chiselMain(Array[String](\"--backend\", \"v\", \"--targetDir\", \"generated/\" + this.getClass.getSimpleName.dropRight(1)),\n () => Module(new EthTxController(2, 64)))\n}\n", "groundtruth": " }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"fifoEmpty\")(\"Addr\")) {\n ocpDataReg := ethTxCtrlRegMap(\"fifoEmpty\")(\"Reg\")\n }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"fifoFull\")(\"Addr\")) {\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ethcontroller/design/MIIRx.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.design\n\nimport Chisel._\nimport ethcontroller.interfaces.MIIChannel\nimport ethcontroller.protocols.EthernetConstants\nimport ethcontroller.utils.{Deserializer, ExtClockSampler}\n\n/*\n The RX MII channel manages the reception of bytes from the PHY\n /\nclass MIIRx extends Module {\n val io = new Bundle() {\n val miiChannel = new MIIChannel().asInput\n val rxEn = Bool(INPUT)\n val phyErr = Bool(OUTPUT)\n val ethSof = Bool(OUTPUT)\n val ethEof = Bool(OUTPUT)\n val ethByte = Bits(OUTPUT, width = 8)\n val ethByteDv = Bool(OUTPUT)\n }\n\n /\n Registers\n /\n val sofReg = Reg(init = Bool(false))\n val eofReg = Reg(init = Bool(false))\n val validPHYDataReg = Reg(init = Bool(false))\n\n /\n Sampling clock and line of MII\n /\n val miiClkSampler = Module(new ExtClockSampler(true, 2))\n miiClkSampler.io.extClk := io.miiChannel.clk\n val miiDvSyncedReg = ShiftRegister(io.miiChannel.dv, 2)\n val miiDataSyncedReg = ShiftRegister(io.miiChannel.data, 2)\n val miiErrSyncedReg = ShiftRegister(io.miiChannel.err, 2)\n\n /\n Flags\n /\n val phyNA = io.miiChannel.col & ~io.miiChannel.crs\n val phyError = phyNA \|\| miiErrSyncedReg\n val validPHYData = miiDvSyncedReg & ~miiErrSyncedReg & ~phyNA\n validPHYDataReg := validPHYData\n val risingMIIEdge = miiClkSampler.io.sampledClk\n\n /\n Buffering PHY bytes\n /\n val deserializePHYByte = Module(new Deserializer(false, 4, 8))\n deserializePHYByte.io.en := io.rxEn & risingMIIEdge & validPHYData\n deserializePHYByte.io.clr := phyError \|\| eofReg\n deserializePHYByte.io.shiftIn := miiDataSyncedReg\n val byteReg = Reg(init = Bits(0, width = 8), next = deserializePHYByte.io.shiftOut)\n val wrByteReg = Reg(init = Bool(false), next = deserializePHYByte.io.done)\n\n /\n Buffer & re-order PHY double-words\n /\n val deserializePHYBuffer = Module(new Deserializer(true, 8, 64))\n deserializePHYBuffer.io.en := deserializePHYByte.io.done\n deserializePHYBuffer.io.clr := phyError \|\| eofReg\n deserializePHYBuffer.io.shiftIn := deserializePHYByte.io.shiftOut\n val regBuffer = Reg(init = Bits(0, width = 64), next = deserializePHYBuffer.io.shiftOut)\n val regBufferDv = Reg(init = Bool(false), next = deserializePHYBuffer.io.done)\n\n /\n Ethernet frame detection logic\n /\n sofReg := false.B\n when(regBuffer === EthernetConstants.constSFD && regBufferDv) {\n sofReg := true.B\n }\n\n eofReg := false.B\n when(validPHYDataReg && ~validPHYData) {\n", "right_context": " }\n\n /\n I/O plumbing\n */\n io.phyErr := phyNA\n io.ethSof := sofReg\n io.ethEof := eofReg\n io.ethByte := byteReg\n io.ethByteDv := wrByteReg\n}\n", "groundtruth": " eofReg := true.B\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ethcontroller/design/MIITx.scala", "left_context": "package ethcontroller.design\n\nimport Chisel._\nimport ethcontroller.interfaces.MIIChannel\nimport ethcontroller.utils.{ExtClockSampler, Serializer}\n\n/*\n The TX MII channel manages the reception of bytes from the PHY\n /\nclass MIITx extends Module {\n val io = new Bundle() {\n val miiChannel = new MIIChannel()\n val macDataDv = Bool(INPUT)\n val macData = Bits(INPUT, width = 8)\n val ready = Bool(OUTPUT)\n val phyErr = Bool(OUTPUT)\n }\n\n /\n Registers and components\n /\n val transmittingReg = Reg(init = false.B)\n\n /\n Sampling clock and line of MII\n /\n val miiClkSampler = Module(new ExtClockSampler(true, 2))\n miiClkSampler.io.extClk := io.miiChannel.clk\n val miiErrSyncedReg = ShiftRegister(io.miiChannel.err, 2)\n val miiDataReg = Reg(init = UInt(0, width = 4))\n val miiDvReg = Reg(init = false.B)\n\n /\n Flags\n /\n val phyNA = io.miiChannel.col & ~io.miiChannel.crs\n val phyError = phyNA \|\| miiErrSyncedReg\n val miiClkEdge = miiClkSampler.io.sampledClk\n\n /\n Serialize Output to Nibble\n /\n val serializeByteToNibble = Module(new Serializer(false, 8, 4))\n serializeByteToNibble.io.load := io.macDataDv\n serializeByteToNibble.io.shiftIn := io.macData\n serializeByteToNibble.io.en := miiClkEdge\n\n", "right_context": "\n /\n Place data on the falling MII clock edge so that they are available on the rising edge\n /\n when(miiClkEdge) {\n //(De-)Assert MII data valid\n when(transmittingReg) {\n miiDvReg := true.B\n }.elsewhen(~transmittingReg) {\n miiDvReg := false.B\n }\n //Data nibble\n miiDataReg := serializeByteToNibble.io.shiftOut\n }\n\n /\n I/O plumbing\n */\n io.ready := ~transmittingReg \|\| ~serializeByteToNibble.io.dv\n io.miiChannel.data := miiDataReg\n io.miiChannel.dv := miiDvReg\n io.phyErr := phyNA\n\n}\n", "groundtruth": " when(~transmittingReg && serializeByteToNibble.io.dv) {\n transmittingReg := true.B\n }.elsewhen(~serializeByteToNibble.io.dv && serializeByteToNibble.io.done) {\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ethcontroller/interfaces/MIIChannel.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.interfaces\n\nimport Chisel.{Bits, Bool, Bundle, INPUT, OUTPUT}\n\nclass MIIChannel extends Bundle {\n /** Clock from the PHY /\n", "right_context": " /* Received nibble data /\n val data = Bits(OUTPUT, width = 4)\n /* Signal could not be decoded to data /\n val err = Bool(INPUT)\n /* Carrier-sense signal /\n val crs = Bool(INPUT)\n /* Collision detection signal /\n val col = Bool(INPUT)\n}\n", "groundtruth": " val clk = Bool(INPUT)\n /* Received data valid */\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ethcontroller/interfaces/PHYChannel.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.interfaces\n\nimport Chisel.{Bool, Bundle, INPUT, OUTPUT}\n\nclass PHYChannel extends Bundle {\n /** Management data clock to the PHY /\n val mdc = Bool(OUTPUT)\n /* Management output data /\n val mdo = Bool(OUTPUT)\n", "right_context": " val md_t = Bool(OUTPUT)\n}\n", "groundtruth": " /* Management input data */\n val mdi = Bool(INPUT)\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ethcontroller/protocols/EthernetConstants.scala", "left_context": "package ethcontroller.protocols\n\nimport Chisel._\n\nobject EthernetConstants {\n\n // Constants\n val constEthFrameLength = 1518 * 8 //bits\n val constEthMacLength = 6 * 8 //bits\n val constFCSLength = 4 * 8 //bits\n val constSFD = Bits(\"h55555555555555D5\", width = 64)\n val constIFG = Bits(\"h0000000000000000\", width = 64)\n", "right_context": " val constVLANt2 = Bits(\"h88A8\", width = 16)\n val constVLANt3 = Bits(\"h9100\", width = 16)\n val constMPLSt1 = Bits(\"h8847\", width = 16)\n val constMPLSt2 = Bits(\"h8848\", width = 16)\n val constIPv4t = Bits(\"h0800\", width = 16)\n val constIPv6t = Bits(\"h86DD\", width = 16)\n val constPTP2t = Bits(\"h88F7\", width = 16)\n val constPTP4t1 = Bits(\"h013F\", width = 16)\n val constPTP4t2 = Bits(\"h0140\", width = 16)\n val constPTPGeneralPort = 319.U\n val constPTPEventPort = 320.U\n val constPTPSyncType = Bits(\"h00\")\n val constPTPFollowType = Bits(\"h08\")\n val constPTPDlyReqType = Bits(\"h01\")\n val constPTPDlyRplyType = Bits(\"h09\")\n\n}\n", "groundtruth": " val constVLANt1 = Bits(\"h8100\", width = 16)\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ethcontroller/protocols/EthernetFrame.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.protocols\n\n/*\n Mockup Ethernet frame\n * Nibbles in the frame are in LSB-first per byte order\n */\nabstract class EthernetFrame {\n\n val PREAMBLE_END = 0xD5\n val IP_UDP_PROTOCOL = 0x11\n val PTP_FOLLOW_UP_TYPE = 0x8\n\n //Vars\n val preamble: Array[Byte]\n val dstMac: Array[Byte]\n val srcMac: Array[Byte]\n val ethType: Array[Byte]\n val data: Array[Byte]\n\n //Special cases\n val ipHeader: Array[Byte]\n val udpHeader: Array[Byte]\n val ptpHeader: Array[Byte]\n val ptpBody: Array[Byte]\n val ptpSuffix: Array[Byte]\n val fcs: Array[Byte]\n val igp: Array[Byte]\n\n //Getters for nibbles\n def preambleNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(preamble, msbFirst = false)\n\n def dstMacNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(dstMac, msbFirst = false)\n\n def srcMacNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(srcMac, msbFirst = false)\n\n", "right_context": "\n def dataNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(data, msbFirst = false)\n\n def ipHeaderNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(ipHeader, msbFirst = false)\n\n def udpHeaderNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(udpHeader, msbFirst = false)\n\n def ptpHeaderNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(ptpHeader, msbFirst = false)\n\n def ptpBodyNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(ptpBody, msbFirst = false)\n\n def ptpSuffixNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(ptpSuffix, msbFirst = false)\n\n def fcsNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(fcs, msbFirst = false)\n\n def igpNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(igp, msbFirst = false)\n}\n", "groundtruth": " def ethTypeNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(ethType, msbFirst = false)\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ethcontroller/protocols/EthernetUtils.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.protocols\n\nobject EthernetUtils {\n /*\n Converts a byte to an array of nibbles\n \n @param byte gets broken down to nibbles\n * @param msbFirst controls the order of the nibbles\n * @return an array of two nibbles\n /\n def byteToNibble(byte: Int, msbFirst: Boolean): Array[Int] = {\n val nibbles = new Array[Int](2)\n nibbles(0) = byte & 0x0F\n nibbles(1) = (byte & 0xF0) >> 4\n if (msbFirst) {\n nibbles.reverse\n } else {\n nibbles\n }\n }\n\n /\n Converts an array of bytes to an array of nibbles\n \n @param bytes the data to be broken down to nibbles\n * @param msbFirst controls the order of the nibbles per byte\n * @return an array of nibbles size bytes.size2\n /\n def dataBytesToNibbles(bytes: Array[Byte], msbFirst: Boolean): Array[Int] = {\n val nibbles = new Array[Int](bytes.length * 2)\n var i = 0\n for (byte <- bytes) {\n val tempByteNibbles = byteToNibble(byte, msbFirst)\n nibbles(i) = tempByteNibbles(0)\n nibbles(i + 1) = tempByteNibbles(1)\n i = i + 2\n }\n nibbles\n }\n\n /*\n Lazy way for converting Integer values in array to bytes\n \n @param xs Integer Array values\n * @return Array of bytes\n /\n", "right_context": "}\n", "groundtruth": " def toBytes(xs: Int) = xs.map(_.toByte).toArray\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ethcontroller/utils/Deserializer.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.utils\n\nimport Chisel._\n\n/*\n Deserialize an M-bit input to an N-bit output based on a specified order\n \n @param inputWidth the bit width of the serial input\n * @param outputWidth the bit width of the parallel\n * @param msbFirst the serial input order\n */\nclass Deserializer(msbFirst: Boolean = false, inputWidth: Int = 4, outputWidth: Int = 8) extends Module {\n val io = new Bundle() {\n val en = Bool(INPUT)\n val clr = Bool(INPUT)\n val shiftIn = Bits(INPUT, width = inputWidth)\n val shiftOut = Bits(OUTPUT, width = outputWidth)\n val done = Bool(OUTPUT)\n }\n\n val shiftReg = Reg(init = Bits(0, width = outputWidth))\n\n // Shift-register\n when(io.clr) {\n shiftReg := 0.U\n }.elsewhen(io.en) {\n if (msbFirst) {\n shiftReg(inputWidth - 1, 0) := io.shiftIn\n shiftReg(outputWidth - 1, inputWidth) := shiftReg(outputWidth - inputWidth - 1, 0)\n", "right_context": "\n val countReg = Reg(init = UInt(outputWidth / inputWidth - 1, width = log2Floor(outputWidth / inputWidth) + 1))\n val doneReg = Reg(init = Bool(false))\n\n // Shift Counter\n when(io.clr) {\n countReg := (outputWidth / inputWidth - 1).U\n doneReg := false.B\n }.elsewhen(io.en) {\n when(countReg === 0.U) {\n countReg := (outputWidth / inputWidth - 1).U\n doneReg := true.B\n }.otherwise {\n countReg := countReg - 1.U\n doneReg := false.B\n }\n }.elsewhen(doneReg) {\n doneReg := false.B\n }\n\n io.shiftOut := shiftReg\n io.done := doneReg\n}\n\nobject Deserializer extends App {\n chiselMain(Array[String](\"--backend\", \"v\", \"--targetDir\", \"generated/\" + this.getClass.getSimpleName.dropRight(1)),\n () => Module(new Deserializer(false, 4, 8)))\n}", "groundtruth": " } else {\n shiftReg(outputWidth - inputWidth - 1, 0) := shiftReg(outputWidth - 1, inputWidth)\n shiftReg(outputWidth - 1, outputWidth - inputWidth) := io.shiftIn\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ethcontroller/utils/ExtClockSampler.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.utils\n\nimport Chisel._\n\n/*\n Synchronizes external clock using a flip-flop synchronizer chain and samples the\n * requested external clock edge\n \n @param sampleRisingEdge if true it samples the rising edge, else the falling edge\n * @param syncChainDepth the number of FF synchronizers to use\n */\nclass ExtClockSampler(sampleRisingEdge: Boolean = true, syncChainDepth: Int = 2) extends Module {\n val io = new Bundle() {\n val extClk = Bool(INPUT)\n val sampledClk = Bool(OUTPUT)\n }\n\n val extClkEdge = Wire(init = false.B) //this will be our sampled edge\n\n val extClkSyncedReg = ShiftRegister(io.extClk, syncChainDepth)\n val extClkSyncedOldReg = Reg(next = extClkSyncedReg)\n", "right_context": "", "groundtruth": "\n if (sampleRisingEdge) {\n extClkEdge := extClkSyncedReg & ~extClkSyncedOldReg //check for a rising edge\n } else {\n extClkEdge := ~extClkSyncedReg & extClkSyncedOldReg //or check for a falling edge\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ethcontroller/utils/Serializer.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.utils\n\nimport Chisel._\n\n/*\n Serializes an M-bit input to an N-bit output based on a specified order\n * after an initial load\n \n @param inputWidth the bit width of the parallel input\n * @param outputWidth the bit width of the serial output\n * @param msbFirst the serial output order\n /\nclass Serializer(msbFirst: Boolean = false, inputWidth: Int = 8, outputWidth: Int = 4) extends Module {\n val io = new Bundle() {\n val load = Bool(INPUT)\n val en = Bool(INPUT)\n val shiftIn = Bits(INPUT, width = inputWidth)\n val shiftOut = Bits(OUTPUT, width = outputWidth)\n val dv = Bool(OUTPUT)\n val done = Bool(OUTPUT)\n }\n\n val constShiftStages = inputWidth / outputWidth\n val shiftReg = Reg(init = Bits(0, width = inputWidth))\n val busyReg = Reg(init = Bool(false))\n val doneReg = Reg(init = Bool(false))\n val countReg = Reg(init = UInt(constShiftStages - 1, width = log2Floor(constShiftStages) + 1))\n val selHi = UInt()\n val selLo = UInt()\n\n // Shift-register\n when(~busyReg && io.load) {\n shiftReg := io.shiftIn\n busyReg := true.B\n doneReg := false.B\n }.elsewhen(io.en && busyReg) {\n when(countReg === 0.U) {\n countReg := (constShiftStages - 1).U\n doneReg := true.B\n", "right_context": " selHi := countReg outputWidth.U + outputWidth.U - 1.U\n selLo := countReg * outputWidth.U\n } else {\n selHi := (constShiftStages.U - 1.U - countReg) * outputWidth.U + outputWidth.U - 1.U\n selLo := (constShiftStages.U - 1.U - countReg) * outputWidth.U\n }\n\n /*\n I/O plumbing\n */\n io.shiftOut := shiftReg(selHi, selLo)\n io.done := doneReg\n io.dv := busyReg\n}\n\nobject Serializer extends App {\n chiselMain(Array[String](\"--backend\", \"v\", \"--targetDir\", \"generated/\" + this.getClass.getSimpleName.dropRight(1)),\n () => Module(new Serializer(false, 8, 4)))\n}\n", "groundtruth": " }.otherwise {\n countReg := countReg - 1.U\n doneReg := false.B\n }\n }.elsewhen(doneReg) {\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ocp/Arbiter.scala", "left_context": "\n/\n Arbiter for OCP burst slaves.\n * Pseudo round robin arbitration. Each turn for a non-requesting master costs 1 clock cycle.\n \n Author: Martin Schoeberl (martin@jopdesign.com)\n \n /\n\npackage ocp\n\nimport Chisel._\n\nclass Arbiter(cnt: Int, addrWidth: Int, dataWidth: Int, burstLen: Int) extends Module {\n // MS: I'm always confused from which direction the name shall be\n // probably the other way round...\n val io = IO(new Bundle {\n val master = Vec.fill(cnt) {\n new OcpBurstSlavePort(addrWidth, dataWidth, burstLen)\n }\n val slave = new OcpBurstMasterPort(addrWidth, dataWidth, burstLen)\n })\n\n val turnReg = Reg(init = UInt(0, log2Up(cnt)))\n val burstCntReg = Reg(init = UInt(0, log2Up(burstLen)))\n\n val sIdle :: sRead :: sWrite :: Nil = Enum(UInt(), 3)\n val stateReg = Reg(init = sIdle)\n\n // buffer signals from master to cut critical paths\n val masterBuffer = Vec(io.master.map { m =>\n val port = new OcpBurstSlavePort(addrWidth, dataWidth, burstLen)\n val bus = Module(new OcpBurstBus(addrWidth, dataWidth, burstLen))\n m <> bus.io.slave\n new OcpBurstBuffer(bus.io.master, port)\n port\n })\n\n val master = masterBuffer(turnReg).M\n\n when(stateReg === sIdle) {\n when(master.Cmd =/= OcpCmd.IDLE) {\n when(master.Cmd === OcpCmd.RD) {\n stateReg := sRead\n }\n when(master.Cmd === OcpCmd.WR) {\n", "right_context": " }\n .otherwise {\n turnReg := Mux(turnReg === UInt(cnt - 1), UInt(0), turnReg + UInt(1))\n }\n }\n when(stateReg === sWrite) {\n // Just wait on the DVA after the write\n when(io.slave.S.Resp === OcpResp.DVA) {\n turnReg := Mux(turnReg === UInt(cnt - 1), UInt(0), turnReg + UInt(1))\n stateReg := sIdle\n }\n }\n when(stateReg === sRead) {\n // For read we have to count the DVAs\n when(io.slave.S.Resp === OcpResp.DVA) {\n burstCntReg := burstCntReg + UInt(1)\n when(burstCntReg === UInt(burstLen) - UInt(1)) {\n turnReg := Mux(turnReg === UInt(cnt - 1), UInt(0), turnReg + UInt(1))\n stateReg := sIdle\n }\n }\n }\n\n io.slave.M := master\n\n for (i <- 0 to cnt - 1) {\n masterBuffer(i).S.CmdAccept := Bits(0)\n masterBuffer(i).S.DataAccept := Bits(0)\n masterBuffer(i).S.Resp := OcpResp.NULL\n // we forward the data to all masters\n masterBuffer(i).S.Data := io.slave.S.Data\n }\n masterBuffer(turnReg).S := io.slave.S\n\n // The response of the SSRAM comes a little bit late\n}\n\nobject ArbiterMain {\n def main(args: Array[String]): Unit = {\n\n val chiselArgs = args.slice(4, args.length)\n val cnt = args(0)\n val addrWidth = args(1)\n val dataWidth = args(2)\n val burstLen = args(3)\n\n chiselMain(chiselArgs, () => Module(new Arbiter(cnt.toInt, addrWidth.toInt, dataWidth.toInt, burstLen.toInt)))\n }\n}\n\n\n", "groundtruth": " stateReg := sWrite\n burstCntReg := UInt(0)\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ocp/NodeTdmArbiter.scala", "left_context": "\n/\n Arbiter for OCP burst slaves.\n * TDM arbitration. Each turn for a non-requesting master costs 16+4+2 clock cycle.\n \n Author: Martin Schoeberl (martin@jopdesign.com) David Chong (davidchong99@gmail.com)\n \n /\n\npackage ocp\n\nimport Chisel._\n\nclass NodeTdmArbiter(cnt: Int, addrWidth: Int, dataWidth: Int, burstLen: Int, ctrlDelay: Int) extends Module {\n // MS: I'm always confused from which direction the name shall be\n // probably the other way round...\n val io = IO(new Bundle {\n val master = new OcpBurstSlavePort(addrWidth, dataWidth, burstLen)\n val slave = new OcpBurstMasterPort(addrWidth, dataWidth, burstLen)\n val node = UInt(INPUT, 6)\n })\n debug(io.master)\n debug(io.slave)\n debug(io.node)\n\n // MS: have all generated constants at one place\n\n val cntReg = Reg(init = UInt(0, log2Up(cnt * (burstLen + ctrlDelay + 1))))\n // slot length = burst size + 1 \n val burstCntReg = Reg(init = UInt(0, log2Up(burstLen)))\n val period = cnt * (burstLen + ctrlDelay + 1)\n val slotLen = burstLen + ctrlDelay + 1\n val numPipe = 3\n\n val wrPipeDelay = burstLen + ctrlDelay + numPipe\n val wrCntReg = Reg(init = UInt(0, log2Up(wrPipeDelay)))\n\n val rdPipeDelay = burstLen + ctrlDelay + numPipe\n val rdCntReg = Reg(init = UInt(0, log2Up(rdPipeDelay)))\n\n // MS: merge rdCntReg and wrCntReg and let it count till slot length\n\n val cpuSlot = Vec.fill(cnt) {\n Reg(init = UInt(0, width = 1))\n }\n\n val sIdle :: sRead :: sWrite :: Nil = Enum(UInt(), 3)\n val stateReg = Reg(init = sIdle)\n\n debug(cntReg)\n for (i <- (0 until cnt))\n debug(cpuSlot(i))\n\n debug(stateReg)\n debug(wrCntReg)\n debug(rdCntReg)\n\n cntReg := Mux(cntReg === UInt(period - 1), UInt(0), cntReg + UInt(1))\n\n", "right_context": " cpuSlot(i) := slotTable(i)\n }\n\n // Initialize master data to zero when cpuSlot is not enabled \n io.slave.M.Addr := Bits(0)\n io.slave.M.Cmd := Bits(0)\n io.slave.M.DataByteEn := Bits(0)\n io.slave.M.DataValid := Bits(0)\n io.slave.M.Data := Bits(0)\n\n // Initialize slave data to zero\n io.master.S.Data := Bits(0)\n io.master.S.Resp := OcpResp.NULL\n io.master.S.CmdAccept := Bits(0)\n io.master.S.DataAccept := Bits(0)\n\n // FSM for TDM Arbiter \n when(stateReg === sIdle) {\n when(cpuSlot(io.node) === UInt(1)) {\n val master = io.master.M\n //io.slave.M := master\n\n when(master.Cmd =/= OcpCmd.IDLE) {\n when(master.Cmd === OcpCmd.RD) {\n io.slave.M := master\n stateReg := sRead\n io.master.S.CmdAccept := UInt(1)\n rdCntReg := UInt(0)\n }\n when(master.Cmd === OcpCmd.WR) {\n io.slave.M := master\n stateReg := sWrite\n io.master.S.CmdAccept := UInt(1)\n io.master.S.DataAccept := UInt(1)\n wrCntReg := UInt(0)\n }\n }\n }\n }\n\n when(stateReg === sWrite) {\n io.slave.M := io.master.M\n io.master.S.DataAccept := UInt(1)\n // MS: why not counting just up to the slot length\n // Then we can avoid >= and use =\n wrCntReg := Mux(wrCntReg === UInt(wrPipeDelay), UInt(0), wrCntReg + UInt(1))\n\n // Sends ZEROs after the burst is done \n when(wrCntReg >= UInt(burstLen - 1)) {\n io.slave.M.Cmd := Bits(0)\n io.slave.M.Addr := Bits(0)\n io.slave.M.Data := Bits(0)\n io.slave.M.DataValid := Bits(0)\n io.slave.M.DataByteEn := Bits(0)\n }\n\n // Turn off the DataValid after a burst of 4\n when(wrCntReg >= UInt(burstLen - 1)) {\n io.master.S.DataAccept := UInt(0)\n }\n\n // Forward Rsp/DVA back to node \n // Ms: not hard coded constants in the source\n when(wrCntReg === UInt(4)) {\n io.master.S.Resp := OcpResp.DVA\n }\n // Wait on DVA \n when(io.master.S.Resp === OcpResp.DVA) {\n stateReg := sIdle\n }\n }\n\n when(stateReg === sRead) {\n io.slave.M := io.master.M\n rdCntReg := Mux(rdCntReg === UInt(rdPipeDelay + burstLen), UInt(0), rdCntReg + UInt(1))\n\n // Sends ZEROs after the burst is done \n // MS: This should also (as in write) be just the slot length.\n when(rdCntReg >= UInt(burstLen - 1)) {\n io.slave.M.Cmd := Bits(0)\n io.slave.M.Addr := Bits(0)\n io.slave.M.Data := Bits(0)\n io.slave.M.DataValid := Bits(0)\n io.slave.M.DataByteEn := Bits(0)\n }\n\n // rdCntReg starts 1 clock cycle after the arrival of the 1st data\n // MS: rdCntReg is used for two different purposes -- fix it\n // The following shall also include number of pipeline stages on the return path\n when(rdCntReg >= UInt(ctrlDelay + numPipe)) {\n io.master.S.Data := io.slave.S.Data\n io.master.S.Resp := io.slave.S.Resp\n }\n\n when(io.master.S.Resp === OcpResp.DVA) {\n burstCntReg := burstCntReg + UInt(1)\n when(burstCntReg === UInt(burstLen) - UInt(1)) {\n stateReg := sIdle\n }\n }\n }\n\n debug(io.slave.M)\n\n //io.master.S := io.slave.S\n\n}\n\n/* Mux for all arbiters' outputs /\nclass MemMuxIntf(nr: Int, addrWidth: Int, dataWidth: Int, burstLen: Int) extends Module {\n val io = new Bundle {\n val master = Vec.fill(nr) {\n new OcpBurstSlavePort(addrWidth, dataWidth, burstLen)\n }\n val slave = new OcpBurstMasterPort(addrWidth, dataWidth, burstLen)\n }\n debug(io.master)\n debug(io.slave)\n\n // MS: would like pipeline number configurable\n\n // 1st stage pipeline registers for inputs\n val mCmd_p1_Reg = Vec.fill(nr) {\n Reg(init = UInt(0, width = 3))\n }\n val mAddr_p1_Reg = Vec.fill(nr) {\n Reg(UInt(width = addrWidth))\n }\n val mData_p1_Reg = Vec.fill(nr) {\n Reg(UInt(width = dataWidth))\n }\n val mDataByteEn_p1_Reg = Vec.fill(nr) {\n Reg(UInt(width = dataWidth / 8))\n }\n val mDataValid_p1_Reg = Vec.fill(nr) {\n Reg(UInt(width = 1))\n }\n\n // 2st stage pipeline registers for inputs\n // MS: what about using the whole bundle as a single signal?\n // val mMasterReg = Reg(init=OcpBurstMasterSignals(...))\n val mCmd_p2_Reg = Reg(init = UInt(0, width = 3))\n val mAddr_p2_Reg = Reg(UInt(width = addrWidth))\n val mData_p2_Reg = Reg(UInt(width = dataWidth))\n val mDataByteEn_p2_Reg = Reg(UInt(width = dataWidth / 8))\n val mDataValid_p2_Reg = Reg(UInt(width = 1))\n\n // Pipeline registers default to 0\n mCmd_p1_Reg := Bits(0)\n mAddr_p1_Reg := Bits(0)\n mData_p1_Reg := Bits(0)\n mDataByteEn_p1_Reg := Bits(0)\n mDataValid_p1_Reg := Bits(0)\n\n // 1st stage pipeline of the input\n for (i <- 0 until nr) {\n mCmd_p1_Reg(i) := io.master(i).M.Cmd\n }\n\n for (i <- 0 until nr) {\n mAddr_p1_Reg(i) := io.master(i).M.Addr\n }\n\n for (i <- 0 until nr) {\n mData_p1_Reg(i) := io.master(i).M.Data\n }\n\n for (i <- 0 until nr) {\n mDataByteEn_p1_Reg(i) := io.master(i).M.DataByteEn\n }\n\n for (i <- 0 until nr) {\n mDataValid_p1_Reg(i) := io.master(i).M.DataValid\n }\n\n // OR gate of all inputs (2nd stage pipeline)\n\n mCmd_p2_Reg := mCmd_p1_Reg.reduce(_ \| _)\n mAddr_p2_Reg := mAddr_p1_Reg.reduce(_ \| _)\n mData_p2_Reg := mData_p1_Reg.reduce(_ \| _)\n mDataByteEn_p2_Reg := mDataByteEn_p1_Reg.reduce(_ \| _)\n mDataValid_p2_Reg := mDataValid_p1_Reg.reduce(_ \| _)\n\n // Transfer data from input pipeline registers to output\n io.slave.M.Addr := mAddr_p2_Reg\n io.slave.M.Cmd := mCmd_p2_Reg\n io.slave.M.DataByteEn := mDataByteEn_p2_Reg\n io.slave.M.DataValid := mDataValid_p2_Reg\n io.slave.M.Data := mData_p2_Reg\n\n // 1st stage pipeline registers for output\n val sResp_p1_Reg = Reg(next = io.slave.S.Resp)\n val sData_p1_Reg = Reg(next = io.slave.S.Data)\n\n\n // Forward response to all arbiters\n for (i <- 0 until nr) {\n io.master(i).S.Data := sData_p1_Reg\n io.master(i).S.Resp := sResp_p1_Reg\n }\n\n}\n\nobject NodeTdmArbiterMain {\n def main(args: Array[String]): Unit = {\n\n val chiselArgs = args.slice(5, args.length)\n val cnt = args(0)\n val addrWidth = args(1)\n val dataWidth = args(2)\n val burstLen = args(3)\n val ctrlDelay = args(4)\n\n chiselMain(chiselArgs, () => Module(new NodeTdmArbiter(cnt.toInt, addrWidth.toInt, dataWidth.toInt, burstLen.toInt, ctrlDelay.toInt)))\n }\n}\n\n\n", "groundtruth": " def slotTable(i: Int): UInt = {\n (cntReg === UInt(i slotLen)).toUInt\n }\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ocp/Ocp.scala", "left_context": "\n/\n Generic definitions for OCP\n \n Authors: Wolfgang Puffitsch (wpuffitsch@gmail.com)\n \n /\n\npackage ocp\n\nimport Chisel._\n\n// Constants for MCmd\n", "right_context": " val IDLE = Bits(\"b000\")\n val WR = Bits(\"b001\")\n val RD = Bits(\"b010\")\n // val RDEX = Bits(\"b011\")\n // val RDL = Bits(\"b100\")\n // val WRNP = Bits(\"b101\")\n // val WRC = Bits(\"b110\")\n // val BCST = Bits(\"b111\")\n}\n\n// Constants for SResp\nobject OcpResp {\n val NULL = Bits(\"b00\")\n val DVA = Bits(\"b01\")\n val FAIL = Bits(\"b10\")\n val ERR = Bits(\"b11\")\n}\n\n// MS: would like fields (e.g. data) to start with lower case.\n// Just classes start with upper case.\n\n// Signals generated by master\nclass OcpMasterSignals(addrWidth: Int, dataWidth: Int) extends Bundle() {\n val Cmd = Bits(width = 3)\n val Addr = Bits(width = addrWidth)\n val Data = Bits(width = dataWidth)\n\n // This does not really clone, but Data.clone doesn't either\n override def clone() = {\n val res = new OcpMasterSignals(addrWidth, dataWidth)\n res.asInstanceOf[this.type]\n }\n}\n\n// Signals generated by slave\nclass OcpSlaveSignals(dataWidth: Int) extends Bundle() {\n val Resp = Bits(width = 2)\n val Data = Bits(width = dataWidth)\n\n // This does not really clone, but Data.clone doesn't either\n override def clone() = {\n val res = new OcpSlaveSignals(dataWidth)\n res.asInstanceOf[this.type]\n }\n}\n", "groundtruth": "object OcpCmd {\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ocp/OcpBurst.scala", "left_context": "\n/\n Definitions for OCP ports that support Bursts\n \n Authors: Wolfgang Puffitsch (wpuffitsch@gmail.com)\n \n /\n\npackage ocp\n\nimport Chisel._\n\n// Burst masters provide handshake signals\nclass OcpBurstMasterSignals(addrWidth: Int, dataWidth: Int)\n extends OcpMasterSignals(addrWidth, dataWidth) {\n val DataValid = Bits(width = 1)\n val DataByteEn = Bits(width = dataWidth / 8)\n\n // This does not really clone, but Data.clone doesn't either\n override def clone() = {\n val res = new OcpBurstMasterSignals(addrWidth, dataWidth)\n res.asInstanceOf[this.type]\n }\n}\n\n// Burst slaves provide handshake signal\nclass OcpBurstSlaveSignals(dataWidth: Int)\n extends OcpSlaveSignals(dataWidth) {\n val CmdAccept = Bits(width = 1)\n val DataAccept = Bits(width = 1)\n\n // This does not really clone, but Data.clone doesn't either\n override def clone() = {\n val res = new OcpBurstSlaveSignals(dataWidth)\n res.asInstanceOf[this.type]\n }\n}\n\n// Master port\nclass OcpBurstMasterPort(addrWidth: Int, dataWidth: Int, burstLen: Int) extends Bundle() {\n val burstLength = burstLen\n // Clk is implicit in Chisel\n val M = new OcpBurstMasterSignals(addrWidth, dataWidth).asOutput\n val S = new OcpBurstSlaveSignals(dataWidth).asInput\n}\n\n// Slave port is reverse of master port\nclass OcpBurstSlavePort(addrWidth: Int, dataWidth: Int, burstLen: Int) extends Bundle() {\n val burstLength = burstLen\n // Clk is implicit in Chisel\n val M = new OcpBurstMasterSignals(addrWidth, dataWidth).asInput\n val S = new OcpBurstSlaveSignals(dataWidth).asOutput\n\n // This does not really clone, but Data.clone doesn't either\n override def clone() = {\n val res = new OcpBurstSlavePort(addrWidth, dataWidth, burstLen)\n res.asInstanceOf[this.type]\n }\n\n}\n\n// Bridge between word-oriented port and burst port\nclass OcpBurstBridge(master: OcpCacheMasterPort, slave: OcpBurstSlavePort) {\n val addrWidth = master.M.Addr.getWidth\n val dataWidth = master.M.Data.getWidth\n val burstLength = slave.burstLength\n val burstAddrBits = log2Up(burstLength)\n\n // State of transmission\n val idle :: read :: readResp :: write :: Nil = Enum(Bits(), 4)\n val state = Reg(init = idle)\n val burstCnt = Reg(init = UInt(0, burstAddrBits))\n val cmdPos = Reg(Bits(width = burstAddrBits))\n\n // Register signals that come from master\n val masterReg = Reg(init = master.M)\n\n // Register to delay response\n val slaveReg = Reg(master.S)\n\n when(state =/= write && (masterReg.Cmd === OcpCmd.IDLE \|\| slave.S.CmdAccept === Bits(1))) {\n masterReg := master.M\n }\n\n // Default values\n slave.M.Cmd := masterReg.Cmd\n slave.M.Addr := Cat(masterReg.Addr(addrWidth - 1, burstAddrBits + log2Up(dataWidth / 8)),\n Fill(burstAddrBits + log2Up(dataWidth / 8), Bits(0)))\n slave.M.Data := Bits(0)\n slave.M.DataByteEn := Bits(0)\n slave.M.DataValid := Bits(0)\n master.S := slave.S\n\n // Read burst\n when(state === read) {\n when(slave.S.Resp =/= OcpResp.NULL) {\n when(burstCnt === cmdPos) {\n slaveReg := slave.S\n }\n when(burstCnt === UInt(burstLength - 1)) {\n state := readResp\n }\n burstCnt := burstCnt + UInt(1)\n }\n master.S.Resp := OcpResp.NULL\n master.S.Data := Bits(0)\n }\n when(state === readResp) {\n state := idle\n master.S := slaveReg\n }\n\n // Write burst\n when(state === write) {\n masterReg.Cmd := OcpCmd.IDLE\n slave.M.DataValid := Bits(1)\n when(burstCnt === cmdPos) {\n slave.M.Data := masterReg.Data\n slave.M.DataByteEn := masterReg.ByteEn\n }\n when(burstCnt === UInt(burstLength - 1)) {\n state := idle\n }\n when(slave.S.DataAccept === Bits(1)) {\n burstCnt := burstCnt + UInt(1)\n }\n }\n\n // Start new transaction\n when(master.M.Cmd === OcpCmd.RD) {\n state := read\n cmdPos := master.M.Addr(burstAddrBits + log2Up(dataWidth / 8) - 1, log2Up(dataWidth / 8))\n }\n when(master.M.Cmd === OcpCmd.WR) {\n state := write\n cmdPos := master.M.Addr(burstAddrBits + log2Up(dataWidth / 8) - 1, log2Up(dataWidth / 8))\n }\n}\n\n// Join two OcpBurst ports, assume no collisions between requests\nclass OcpBurstJoin(left: OcpBurstMasterPort, right: OcpBurstMasterPort,\n joined: OcpBurstSlavePort, selectLeft: Bool = Bool()) {\n\n val selRightReg = Reg(Bool())\n val selRight = Mux(left.M.Cmd =/= OcpCmd.IDLE, Bool(false),\n Mux(right.M.Cmd =/= OcpCmd.IDLE, Bool(true),\n selRightReg))\n\n joined.M := left.M\n when(selRight) {\n joined.M := right.M\n }\n joined.M.Cmd := right.M.Cmd \| left.M.Cmd\n\n right.S := joined.S\n left.S := joined.S\n\n when(selRightReg) {\n left.S.Resp := OcpResp.NULL\n }\n .otherwise {\n right.S.Resp := OcpResp.NULL\n }\n\n selRightReg := selRight\n\n selectLeft := !selRight\n}\n\n// Join two OcpBurst ports, left port has priority in case of colliding requests\nclass OcpBurstPriorityJoin(left: OcpBurstMasterPort, right: OcpBurstMasterPort,\n joined: OcpBurstSlavePort, selectLeft: Bool = Bool()) {\n\n val selLeft = left.M.Cmd =/= OcpCmd.IDLE\n val selRight = right.M.Cmd =/= OcpCmd.IDLE\n\n val leftPendingReg = Reg(init = Bool(false))\n val rightPendingReg = Reg(init = Bool(false))\n\n val pendingRespReg = Reg(init = UInt(0))\n\n // default port forwarding\n joined.M := Mux(rightPendingReg, right.M, left.M)\n\n // pass back data to masters\n right.S := joined.S\n left.S := joined.S\n // suppress responses when not serving a request\n when(!rightPendingReg) {\n right.S.Resp := OcpResp.NULL\n }\n when(!leftPendingReg) {\n left.S.Resp := OcpResp.NULL\n }\n\n // do not accept commands while another request is being served\n left.S.CmdAccept := Mux(rightPendingReg, Bits(0), joined.S.CmdAccept)\n left.S.DataAccept := Mux(rightPendingReg, Bits(0), joined.S.DataAccept)\n right.S.CmdAccept := Mux(leftPendingReg, Bits(0), joined.S.CmdAccept)\n right.S.DataAccept := Mux(leftPendingReg, Bits(0), joined.S.DataAccept)\n\n // forward requests from left port\n when(selLeft) {\n when(!rightPendingReg) {\n joined.M := left.M\n pendingRespReg := Mux(left.M.Cmd === OcpCmd.WR, UInt(1), UInt(left.burstLength))\n leftPendingReg := Bool(true)\n right.S.CmdAccept := Bits(0)\n right.S.DataAccept := Bits(0)\n }\n }\n // forward requests from right port\n when(selRight) {\n when(!selLeft && !leftPendingReg) {\n joined.M := right.M\n pendingRespReg := Mux(right.M.Cmd === OcpCmd.WR, UInt(1), UInt(right.burstLength))\n rightPendingReg := Bool(true)\n }\n }\n\n // count responses, clear pending flags at end of requests\n when(joined.S.Resp =/= OcpResp.NULL) {\n pendingRespReg := pendingRespReg - UInt(1)\n when(pendingRespReg === UInt(1)) {\n when(leftPendingReg) {\n leftPendingReg := Bool(false)\n }\n when(rightPendingReg) {\n rightPendingReg := Bool(false)\n }\n }\n }\n\n selectLeft := selLeft\n}\n\n// Provide a \"bus\" with a master port and a slave port to simplify plumbing\nclass OcpBurstBus(addrWidth: Int, dataWidth: Int, burstLen: Int) extends Module {\n val io = new Bundle {\n val master = new OcpBurstMasterPort(addrWidth, dataWidth, burstLen)\n val slave = new OcpBurstSlavePort(addrWidth, dataWidth, burstLen)\n }\n io.master <> io.slave\n}\n\n// Buffer a burst for pipelining\nclass OcpBurstBuffer(master: OcpBurstMasterPort, slave: OcpBurstSlavePort) {\n\n val MBuffer = Vec.fill(master.burstLength) {\n Reg(init = master.M)\n }\n\n val free = MBuffer(0).Cmd === OcpCmd.IDLE\n when(free \|\| slave.S.CmdAccept === Bits(1)) {\n", "right_context": "\n master.S.CmdAccept := free\n master.S.DataAccept := free\n}\n", "groundtruth": " for (i <- 0 until master.burstLength - 1) {\n MBuffer(i) := MBuffer(i + 1)\n }\n MBuffer(master.burstLength - 1) := master.M\n }\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ocp/OcpCache.scala", "left_context": "/\n Definitions for OCP ports for split cache\n \n Authors: Wolfgang Puffitsch (wpuffitsch@gmail.com)\n \n /\n\npackage ocp\n\nimport Chisel._\n\nobject OcpCache {\n val STACK_CACHE = Bits(\"b00\")\n val DATA_CACHE = Bits(\"b10\")\n val UNCACHED = Bits(\"b11\")\n}\n\n// Cache masters provide address space signal\nclass OcpCacheMasterSignals(addrWidth: Int, dataWidth: Int)\n extends OcpCoreMasterSignals(addrWidth, dataWidth) {\n val AddrSpace = Bits(width = 2)\n\n // This does not really clone, but Data.clone doesn't either\n override def clone() = {\n val res = new OcpCacheMasterSignals(addrWidth, dataWidth)\n res.asInstanceOf[this.type]\n }\n}\n\n// Master port\nclass OcpCacheMasterPort(addrWidth: Int, dataWidth: Int) extends Bundle() {\n // Clk is implicit in Chisel\n val M = new OcpCacheMasterSignals(addrWidth, dataWidth).asOutput\n val S = new OcpSlaveSignals(dataWidth).asInput\n}\n\n// Slave port is reverse of master port\n", "right_context": " val slave = new OcpCacheSlavePort(addrWidth, dataWidth)\n val master = new OcpCacheMasterPort(addrWidth, dataWidth)\n }\n io.master <> io.slave\n}\n", "groundtruth": "class OcpCacheSlavePort(addrWidth: Int, dataWidth: Int) extends Bundle() {\n // Clk is implicit in Chisel\n val M = new OcpCacheMasterSignals(addrWidth, dataWidth).asInput\n val S = new OcpSlaveSignals(dataWidth).asOutput\n}\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ocp/OcpCore.scala", "left_context": "/\n Definitions for OCP as generated by the Patmos pipeline\n \n Authors: Wolfgang Puffitsch (wpuffitsch@gmail.com)\n \n /\n\npackage ocp\n\nimport Chisel._\n\n// Masters include a byte-enable signal\nclass OcpCoreMasterSignals(addrWidth: Int, dataWidth: Int)\n extends OcpMasterSignals(addrWidth, dataWidth) {\n val ByteEn = Bits(width = dataWidth / 8)\n\n // This does not really clone, but Data.clone doesn't either\n override def clone() = {\n val res = new OcpCoreMasterSignals(addrWidth, dataWidth)\n res.asInstanceOf[this.type]\n }\n}\n\n// Master port\nclass OcpCoreMasterPort(addrWidth: Int, dataWidth: Int) extends Bundle() {\n val M = new OcpCoreMasterSignals(addrWidth, dataWidth).asOutput\n val S = new OcpSlaveSignals(dataWidth).asInput\n", "right_context": "class OcpCoreSlavePort(addrWidth: Int, dataWidth: Int) extends Bundle() {\n val M = new OcpCoreMasterSignals(addrWidth, dataWidth).asInput\n val S = new OcpSlaveSignals(dataWidth).asOutput\n\n // This does not really clone, but Data.clone doesn't either\n override def clone() = {\n val res = new OcpCoreSlavePort(addrWidth, dataWidth)\n res.asInstanceOf[this.type]\n }\n\n}\n\n// Provide a \"bus\" with a master port and a slave port to simplify plumbing\nclass OcpCoreBus(addrWidth: Int, dataWidth: Int) extends Module {\n val io = new Bundle {\n val slave = new OcpCoreSlavePort(addrWidth, dataWidth)\n val master = new OcpCoreMasterPort(addrWidth, dataWidth)\n }\n io.master <> io.slave\n}\n", "groundtruth": "\n // This does not really clone, but Data.clone doesn't either\n override def clone() = {\n val res = new OcpCoreMasterPort(addrWidth, dataWidth)\n res.asInstanceOf[this.type]\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ocp/OcpIO.scala", "left_context": "/\n Definitions for Patmos' OCP ports for general I/O\n \n Authors: Wolfgang Puffitsch (wpuffitsch@gmail.com)\n \n /\n\npackage ocp\n\nimport Chisel._\n\n// Masters include a RespAccept signal\nclass OcpIOMasterSignals(addrWidth: Int, dataWidth: Int)\n extends OcpCoreMasterSignals(addrWidth, dataWidth) {\n val RespAccept = Bits(width = 1)\n\n // This does not really clone, but Data.clone doesn't either\n override def clone() = {\n val res = new OcpIOMasterSignals(addrWidth, dataWidth)\n res.asInstanceOf[this.type]\n }\n}\n\n// Slaves include a CmdAccept signal\nclass OcpIOSlaveSignals(dataWidth: Int)\n extends OcpSlaveSignals(dataWidth) {\n val CmdAccept = Bits(width = 1)\n\n // This does not really clone, but Data.clone doesn't either\n override def clone() = {\n val res = new OcpIOSlaveSignals(dataWidth)\n res.asInstanceOf[this.type]\n }\n}\n\n// Master port\nclass OcpIOMasterPort(addrWidth: Int, dataWidth: Int) extends Bundle() {\n // Clk is implicit in Chisel\n val M = new OcpIOMasterSignals(addrWidth, dataWidth).asOutput\n val S = new OcpIOSlaveSignals(dataWidth).asInput\n}\n\n// Slave port is reverse of master port\nclass OcpIOSlavePort(addrWidth: Int, dataWidth: Int) extends Bundle() {\n // Clk is implicit in Chisel\n val M = new OcpIOMasterSignals(addrWidth, dataWidth).asInput\n val S = new OcpIOSlaveSignals(dataWidth).asOutput\n}\n\n// Bridge between ports that do/do not support CmdAccept\nclass OcpIOBridge(master: OcpCoreMasterPort, slave: OcpIOSlavePort) {\n // Register signals that come from master\n val masterReg = Reg(init = master.M)\n", "right_context": " slave.M.RespAccept := Bits(\"b1\")\n\n // Forward slave signals to master\n master.S <> slave.S\n}\n\n// Bridge between ports that do/do not support CmdAccept\n// An alternative version, being on the safer side for reset.\n// Inserts one cycle delay for the command register (could be improved)\n// including the earlier reaction on CmdAccep\n// adds than combinational paths\nclass OcpIOBridgeAlt(master: OcpCoreMasterPort, slave: OcpIOSlavePort) {\n\n val masterReg = Reg(init = master.M) // What is the reset value of this bundle?\n val busyReg = Reg(init = Bool(false))\n\n when(!busyReg) {\n masterReg := master.M\n }\n when(master.M.Cmd === OcpCmd.RD \|\| master.M.Cmd === OcpCmd.WR) {\n busyReg := Bool(true)\n }\n when(busyReg && slave.S.CmdAccept === Bits(1)) {\n busyReg := Bool(false)\n masterReg.Cmd := OcpCmd.IDLE\n }\n\n // Forward master signals to slave, always accept responses\n slave.M := masterReg\n slave.M.RespAccept := Bits(\"b1\")\n\n // Forward slave signals to master\n master.S <> slave.S\n}\n\n// Provide a \"bus\" with a master port and a slave port to simplify plumbing\nclass OcpIOBus(addrWidth: Int, dataWidth: Int) extends Module {\n val io = new Bundle {\n val slave = new OcpIOSlavePort(addrWidth, dataWidth)\n val master = new OcpIOMasterPort(addrWidth, dataWidth)\n }\n io.master <> io.slave\n}\n", "groundtruth": " when(masterReg.Cmd === OcpCmd.IDLE \|\| slave.S.CmdAccept === Bits(1)) {\n masterReg := master.M\n }\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ocp/OcpNI.scala", "left_context": "/\n Definitions for OCP port for the network interface\n \n Authors: Wolfgang Puffitsch (wpuffitsch@gmail.com)\n \n /\n\npackage ocp\n\nimport Chisel._\n\n// Cache masters provide address space signal\nclass OcpNISlaveSignals(dataWidth: Int)\n extends OcpIOSlaveSignals(dataWidth) {\n val Reset_n = Bits(width = 1)\n val Flag = Bits(width = 2)\n", "right_context": "\n// Master port\nclass OcpNIMasterPort(addrWidth: Int, dataWidth: Int) extends Bundle() {\n // Clk is implicit in Chisel\n val M = new OcpIOMasterSignals(addrWidth, dataWidth).asOutput\n val S = new OcpNISlaveSignals(dataWidth).asInput\n}\n\n// Slave port is reverse of master port\nclass OcpNISlavePort(addrWidth: Int, dataWidth: Int) extends Bundle() {\n // Clk is implicit in Chisel\n val M = new OcpIOMasterSignals(addrWidth, dataWidth).asInput\n val S = new OcpNISlaveSignals(dataWidth).asOutput\n}\n", "groundtruth": "\n // This does not really clone, but Data.clone doesn't either\n override def clone() = {\n val res = new OcpNISlaveSignals(dataWidth)\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ocp/OcpTest.scala", "left_context": "/\n Test for usability of OCP definitions\n \n Authors: Wolfgang Puffitsch (wpuffitsch@gmail.com)\n \n /\n\npackage ocp\n\nimport Chisel._\n\nclass OcpMaster() extends Module {\n val io = IO(new OcpCacheMasterPort(8, 32))\n\n val cnt = Reg(UInt(), init = UInt(0))\n cnt := cnt + UInt(1, 32)\n\n io.M.Cmd := OcpCmd.IDLE\n io.M.Addr := cnt(15, 8)\n io.M.Data := cnt\n io.M.ByteEn := cnt(7, 4)\n\n when(cnt(3, 0) === Bits(\"b1111\")) {\n io.M.Cmd := OcpCmd.WR\n }\n}\n\nclass OcpSlave() extends Module {\n val io = IO(new OcpBurstSlavePort(8, 32, 4))\n\n val M = Reg(next = io.M)\n\n val data = Reg(UInt(), init = UInt(0))\n data := data + UInt(1, 32)\n\n val cnt = Reg(UInt(), init = UInt(0))\n\n io.S.Resp := OcpResp.NULL\n io.S.Data := data\n when(M.Cmd =/= OcpCmd.IDLE) {\n cnt := UInt(4)\n }\n\n", "right_context": " val io = IO(new OcpBurstSlavePort(8, 32, 4))\n\n val master = Module(new OcpMaster())\n val slave = Module(new OcpSlave())\n val bridge = new OcpBurstBridge(master.io, slave.io)\n\n io <> slave.io\n}\n\nobject OcpTestMain {\n def main(args: Array[String]): Unit = {\n chiselMain(args, () => Module(new Ocp()))\n }\n}\n", "groundtruth": " when(cnt =/= UInt(0)) {\n cnt := cnt - UInt(1)\n io.S.Resp := OcpResp.DVA\n }\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ocp/TdmArbiter.scala", "left_context": "/\n Arbiter for OCP burst slaves.\n * Pseudo round robin arbitration. Each turn for a non-requesting master costs 1 clock cycle.\n \n Author: Martin Schoeberl (martin@jopdesign.com) David Chong (davidchong99@gmail.com)\n \n /\n\npackage ocp\n\nimport Chisel._\n\nclass TdmArbiter(cnt: Int, addrWidth: Int, dataWidth: Int, burstLen: Int) extends Module {\n // MS: I'm always confused from which direction the name shall be\n // probably the other way round...\n val io = IO(new Bundle {\n val master = Vec.fill(cnt) {\n new OcpBurstSlavePort(addrWidth, dataWidth, burstLen)\n }\n val slave = new OcpBurstMasterPort(addrWidth, dataWidth, burstLen)\n })\n debug(io.master)\n debug(io.slave)\n\n val cntReg = Reg(init = UInt(0, log2Up(cnt * (burstLen + 2))))\n // slot length = burst size + 2 \n val burstCntReg = Reg(init = UInt(0, log2Up(burstLen)))\n val period = cnt * (burstLen + 2)\n val slotLen = burstLen + 2\n val cpuSlot = Vec.fill(cnt) {\n Reg(init = UInt(0, width = 1))\n }\n\n val sIdle :: sRead :: sWrite :: Nil = Enum(UInt(), 3)\n val stateReg = Vec.fill(cnt) {\n Reg(init = sIdle)\n }\n\n debug(cntReg)\n debug(cpuSlot(0))\n debug(cpuSlot(1))\n debug(cpuSlot(2))\n debug(stateReg(0))\n debug(stateReg(1))\n debug(stateReg(2))\n\n cntReg := Mux(cntReg === UInt(period - 1), UInt(0), cntReg + UInt(1))\n\n // Generater the slot Table for the whole period\n def slotTable(i: Int): UInt = {\n (cntReg === UInt(i * slotLen)).toUInt\n }\n\n for (i <- 0 until cnt) {\n cpuSlot(i) := slotTable(i)\n }\n\n // Initialize data to zero when cpuSlot is not enabled\n io.slave.M.Addr := Bits(0)\n io.slave.M.Cmd := Bits(0)\n io.slave.M.DataByteEn := Bits(0)\n io.slave.M.DataValid := Bits(0)\n io.slave.M.Data := Bits(0)\n\n // Initialize slave data to zero\n for (i <- 0 to cnt - 1) {\n io.master(i).S.CmdAccept := Bits(0)\n io.master(i).S.DataAccept := Bits(0)\n io.master(i).S.Resp := OcpResp.NULL\n io.master(i).S.Data := Bits(0)\n }\n\n // Temporarily assigned to master 0\n //val masterIdReg = Reg(init = UInt(0, log2Up(cnt)))\n\n for (i <- 0 to cnt - 1) {\n\n when(stateReg(i) === sIdle) {\n when(cpuSlot(i) === UInt(1)) {\n\n when(io.master(i).M.Cmd =/= OcpCmd.IDLE) {\n when(io.master(i).M.Cmd === OcpCmd.RD) {\n io.slave.M := io.master(i).M\n io.master(i).S := io.slave.S\n stateReg(i) := sRead\n }\n when(io.master(i).M.Cmd === OcpCmd.WR) {\n io.slave.M := io.master(i).M\n io.master(i).S := io.slave.S\n stateReg(i) := sWrite\n burstCntReg := UInt(0)\n }\n }\n }\n }\n\n when(stateReg(i) === sWrite) {\n io.slave.M := io.master(i).M\n io.master(i).S := io.slave.S\n // Wait on DVA\n", "right_context": " when(stateReg(i) === sRead) {\n io.slave.M := io.master(i).M\n io.master(i).S := io.slave.S\n when(io.slave.S.Resp === OcpResp.DVA) {\n burstCntReg := burstCntReg + UInt(1)\n when(burstCntReg === UInt(burstLen) - UInt(1)) {\n stateReg := sIdle\n }\n }\n }\n }\n\n //io.slave.M := io.master(masterIdReg).M\n debug(io.slave.M)\n\n}\n\nobject TdmArbiterMain {\n def main(args: Array[String]): Unit = {\n\n val chiselArgs = args.slice(4, args.length)\n val cnt = args(0)\n val addrWidth = args(1)\n val dataWidth = args(2)\n val burstLen = args(3)\n\n chiselMain(chiselArgs, () => Module(new TdmArbiter(cnt.toInt, addrWidth.toInt, dataWidth.toInt, burstLen.toInt)))\n }\n}\n\n\n", "groundtruth": " when(io.slave.S.Resp === OcpResp.DVA) {\n stateReg(i) := sIdle\n }\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ocp/TdmArbiterWrapper.scala", "left_context": "/\n Wrapper for NodeTdmArbiter \n \n Author: Martin Schoeberl (martin@jopdesign.com) David Chong (davidchong99@gmail.com)\n \n /\n\n/\n Switching between different arbiters in Aegean:\n * Change 'Arbiter' in aegeanGen.py and in aegeanCode.py to 'TdmArbiterWrapper'.\n * Three places all together.\n */\n\npackage ocp\n\nimport Chisel._\n\nclass TdmArbiterWrapper(cnt: Int, addrWidth: Int, dataWidth: Int, burstLen: Int) extends Module {\n // MS: I'm always confused from which direction the name shall be\n // probably the other way round...\n val io = IO(new Bundle {\n", "right_context": "\n val memMux = Module(new MemMuxIntf(cnt, addrWidth, dataWidth, burstLen))\n\n for (i <- 0 until cnt) {\n val nodeID = UInt(i, width = 6)\n val arb = Module(new ocp.NodeTdmArbiter(cnt, addrWidth, dataWidth, burstLen, 16))\n arb.io.master <> io.master(i)\n arb.io.node := nodeID\n\n memMux.io.master(i) <> arb.io.slave\n }\n\n io.slave <> memMux.io.slave\n}\n\nobject TdmArbiterWrapperMain {\n def main(args: Array[String]): Unit = {\n\n val chiselArgs = args.slice(4, args.length)\n val cnt = args(0)\n val addrWidth = args(1)\n val dataWidth = args(2)\n val burstLen = args(3)\n\n chiselMain(chiselArgs, () => Module(new TdmArbiterWrapper(cnt.toInt, addrWidth.toInt, dataWidth.toInt, burstLen.toInt)))\n }\n}\n\n", "groundtruth": " val master = Vec.fill(cnt) {\n new OcpBurstSlavePort(addrWidth, dataWidth, burstLen)\n }\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/test/scala/ethcontroller/design/EthRxControllerTester.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.design\n\nimport Chisel._\nimport ethcontroller.protocols.{EthernetFrame, EthernetTesting, EthernetUtils}\n\nimport scala.language.postfixOps\nimport scala.sys.process._\n\nclass EthRxControllerTester(dut: EthRxController, frame: EthernetFrame, injectNoFrames: Int) extends Tester(dut) {\n\n def initPHY2MII(clockDiv: Int): Unit = {\n poke(dut.io.miiChannel.col, 0)\n poke(dut.io.miiChannel.crs, 0)\n poke(dut.io.miiChannel.clk, 0)\n step(clockDiv)\n }\n\n def txPHY2MIIData(nibble: Int, clockDiv: Int): Unit = {\n poke(dut.io.miiChannel.dv, 1)\n poke(dut.io.miiChannel.data, nibble)\n poke(dut.io.miiChannel.clk, 0)\n step(clockDiv)\n poke(dut.io.miiChannel.clk, 1)\n step(clockDiv)\n }\n\n def stopTxPHY2MII(clockDiv: Int): Unit = {\n poke(dut.io.miiChannel.dv, 0)\n poke(dut.io.miiChannel.clk, 0)\n step(clockDiv)\n poke(dut.io.miiChannel.clk, 1)\n step(clockDiv)\n }\n\n def peekEthRxStatus(): Unit = {\n peek(dut.stateReg)\n peek(dut.ethByteReg)\n peek(dut.ethByteDvReg)\n peek(dut.rdRamIdReg)\n peek(dut.wrRamIdReg)\n peek(dut.fifoCountReg)\n peek(dut.fifoEmptyReg)\n peek(dut.fifoFullReg)\n peek(dut.rxFrameSizeReg)\n }\n\n def testSingleFrameReception(frame: EthernetFrame, initTime: Long): Unit = {\n initPHY2MII(4)\n println(\"Testing preamble\")\n for (nibble <- frame.preambleNibbles) {\n txPHY2MIIData(nibble, 6)\n peek(dut.miiRx.deserializePHYByte.doneReg)\n peek(dut.miiRx.deserializePHYByte.shiftReg)\n peek(dut.miiRx.regBuffer)\n }\n println(\"Testing MAC\")\n", "right_context": " txPHY2MIIData(nibble, 6)\n peekEthRxStatus()\n }\n }\n println(\"Testing EoF\")\n stopTxPHY2MII(6)\n peekEthRxStatus()\n }\n\n /*\n Testing EthernetRxController\n */\n println(\"Test Starting...\")\n var time: Long = 0x53C38A1000000000L\n for (i <- 0 until injectNoFrames) {\n println(\"...\")\n println(\"TEST FRAME ITERATION #\" + i + \" at t = \" + time.toHexString)\n testSingleFrameReception(frame, time)\n println(\"END TEST FRAME ITERATION #\" + i + \" at t = \" + time.toHexString)\n step(1)\n step(1)\n println(\"...\")\n println(\"...\")\n }\n}\n\nobject EthRxControllerTester extends App {\n private val pathToVCD = \"generated/\" + this.getClass.getSimpleName.dropRight(1)\n private val nameOfVCD = this.getClass.getSimpleName.dropRight(7) + \".vcd\"\n\n //Chisel3\n // iotesters.Driver.execute(Array(\"--target-dir\", \"generated\", \"--fint-write-vcd\"), () => new EthRxController(4, 64)) {\n // // iotesters.Driver.execute(Array(\"--target-dir\", \"generated\", \"--fint-write-vcd\", \"--wave-form-file-name\", \"generated/BubbleFifo.vcd\"), () => new BubbleFifo(8, 4)) {\n // c => new EthRxControllerTester(c, EthernetTesting.mockupPTPEthFrameOverIpUDP, 3)\n // }\n\n //Chisel 2\n chiselMainTest(Array(\"--genHarness\", \"--test\", \"--backend\", \"c\",\n \"--compile\", \"--vcd\", \"--targetDir\", pathToVCD),\n () => Module(new EthRxController(4, 64))) {\n dut => new EthRxControllerTester(dut, EthernetTesting.mockupPTPEthFrameOverIpUDP, 5)\n }\n\n \"gtkwave \" + pathToVCD + \"/\" + nameOfVCD + \" \" + pathToVCD + \"/\" + \"view.sav\" !\n}\n\n", "groundtruth": " for (nibble <- frame.dstMacNibbles ++ frame.srcMacNibbles ++ frame.ethTypeNibbles) {\n txPHY2MIIData(nibble, 6)\n peekEthRxStatus()\n }\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/test/scala/ethcontroller/design/EthTxControllerTester.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.design\n\nimport Chisel.{Module, Tester, chiselMainTest}\nimport ethcontroller.protocols.{EthernetFrame, EthernetTesting}\nimport ocp.OcpCmd\n\nimport scala.language.postfixOps\nimport scala.sys.process._\n\n\nclass EthTxControllerTester(dut: EthTxController, frame: EthernetFrame, injectNoFrames: Int) extends Tester(dut) {\n\n val MII_TICKS_TO_CLKS: Int = 2\n\n var miiClkValue: Int = 0\n var numberOfSysSteps: Int = 0\n\n def testSingleFrameTransmission(frame: EthernetFrame, initTime: Long): Unit = {\n initPHY2MII(4)\n println(\"Testing OCP write to buffer\")\n ocpLoadFrameToBuffer()\n println(\"Testing EthTx transmission\")\n println(\"Testing preamble\")\n // for (nibble <- frame.preambleNibbles) {\n // stepWithMIIClock(6)\n // peek(dut.miiTx.serializeByteToNibble.doneReg)\n // peek(dut.miiTx.serializeByteToNibble.shiftReg)\n // peekEthTxStatus()\n // }\n // println(\"Testing MAC\")\n // for (nibble <- frame.dstMacNibbles ++ frame.srcMacNibbles ++ frame.ethTypeNibbles) {\n // stepWithMIIClock(6)\n // peekEthTxStatus()\n // }\n // println(\"Testing Raw Ethernet frame II payload\")\n // for (payloadData <- 0 until 45) {\n // for (nibble <- frame.dataNibbles) {\n // stepWithMIIClock(6)\n // peekEthTxStatus()\n // }\n // }\n println(\"Testing EoF\")\n stepWithMIIClock()\n }\n\n def initPHY2MII(steps: Int): Unit = {\n poke(dut.io.miiChannel.col, 0)\n poke(dut.io.miiChannel.crs, 0)\n poke(dut.io.miiChannel.clk, 0)\n step(steps)\n }\n\n def ocpLoadFrameToBuffer(): Unit = {\n val totalFrame = frame.dstMac ++ frame.srcMac ++ frame.ethType ++ frame.data\n var ocpAddr = 0x0\n var byteCnt = 0x1\n for (byte <- totalFrame) {\n poke(dut.io.ocp.M.Addr, ocpAddr)\n poke(dut.io.ocp.M.ByteEn, byteCnt)\n poke(dut.io.ocp.M.Data, byte)\n poke(dut.io.ocp.M.Cmd, OcpCmd.WR.litValue())\n stepWithMIIClock()\n", "right_context": "\n poke(dut.io.ocp.M.Cmd, OcpCmd.IDLE.litValue())\n stepWithMIIClock()\n poke(dut.io.ocp.M.Addr, 1 << dut.constRamAddrWidth \| 0x18)\n poke(dut.io.ocp.M.ByteEn, 0xF)\n poke(dut.io.ocp.M.Data, 0x1)\n poke(dut.io.ocp.M.Cmd, OcpCmd.WR.litValue())\n stepWithMIIClock()\n poke(dut.io.ocp.M.Cmd, OcpCmd.IDLE.litValue())\n stepWithMIIClock()\n expect(dut.fifoPushReg, true)\n }\n\n def peekEthTxStatus(): Unit = {\n peek(dut.stateReg)\n peek(dut.byteCntReg)\n peek(dut.rdRamIdReg)\n peek(dut.wrRamIdReg)\n peek(dut.fifoCountReg)\n peek(dut.fifoEmptyReg)\n peek(dut.fifoFullReg)\n peek(dut.txFrameSizeReg)\n peek(dut.miiTx.transmittingReg)\n }\n\n def stepWithMIIClock(): Unit = {\n poke(dut.io.miiChannel.clk, miiClkValue)\n step(1)\n if (numberOfSysSteps > MII_TICKS_TO_CLKS) {\n miiClkValue = 1 - miiClkValue\n numberOfSysSteps = 0\n } else {\n numberOfSysSteps += 1\n }\n }\n\n /*\n Testing EthernetRxController\n */\n println(\"Test Starting...\")\n var time: Long = 0x53C38A1000000000L\n for (i <- 0 until injectNoFrames) {\n println(\"...\")\n println(\"TEST FRAME ITERATION #\" + i + \" at t = \" + time.toHexString)\n testSingleFrameTransmission(frame, time)\n println(\"END TEST FRAME ITERATION #\" + i + \" at t = \" + time.toHexString)\n stepWithMIIClock()\n stepWithMIIClock()\n println(\"...\")\n println(\"...\")\n }\n\n}\n\nobject EthTxControllerTester extends App {\n private val pathToVCD = \"generated/\" + this.getClass.getSimpleName.dropRight(1)\n private val nameOfVCD = this.getClass.getSimpleName.dropRight(7) + \".vcd\"\n\n chiselMainTest(Array(\"--genHarness\", \"--test\", \"--backend\", \"c\",\n \"--compile\", \"--vcd\", \"--targetDir\", pathToVCD),\n () => Module(new EthTxController(4, 64))) {\n dut => new EthTxControllerTester(dut, EthernetTesting.mockupTTEPCFFrame, 5)\n }\n\n var waveHandle = \"gtkwave \" + pathToVCD + \"/\" + nameOfVCD + \" \" + pathToVCD + \"/\" + \"view.sav\" !\n\n println(\"gtkwave running as PID:\" + waveHandle)\n}\n\n\n\n", "groundtruth": " if (byteCnt == 8) {\n byteCnt = 1\n ocpAddr += 0x1\n } else {\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/test/scala/ethcontroller/design/MIIRxTester.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.design\n\nimport Chisel.{Module, Tester, chiselMainTest}\nimport ethcontroller.protocols.{EthernetFrame, EthernetTesting}\n\nimport scala.language.postfixOps\nimport scala.sys.process._\n\nclass MIIRxTester(dut: MIIRx, frame: EthernetFrame) extends Tester(dut) {\n // Shifting of discrete numbers for clarity\n poke(dut.io.miiChannel.col, 0)\n poke(dut.io.miiChannel.crs, 0)\n poke(dut.io.rxEn, true)\n poke(dut.io.miiChannel.dv, 1)\n poke(dut.io.miiChannel.clk, 0)\n step(1)\n println(\"(Testing preamble)\")\n for (nibble <- frame.preambleNibbles) {\n poke(dut.io.miiChannel.data, nibble)\n poke(dut.io.miiChannel.clk, 0)\n step(3)\n peek(dut.deserializePHYByte.countReg)\n peek(dut.deserializePHYByte.doneReg)\n peek(dut.deserializePHYByte.shiftReg)\n peek(dut.regBuffer)\n poke(dut.io.miiChannel.clk, 1)\n step(3)\n }\n poke(dut.io.miiChannel.clk, 0)\n step(3)\n poke(dut.io.miiChannel.clk, 1)\n expect(dut.io.ethSof, true, \"--checking for start-of-frame detected\")\n expect(dut.regBuffer, BigInt(frame.preamble), \"--checking for preamble registered\")\n step(3)\n println(\"Testing EoF\")\n poke(dut.io.miiChannel.clk, 0)\n", "right_context": " poke(dut.io.miiChannel.clk, 1)\n step(3)\n poke(dut.io.miiChannel.clk, 0)\n step(3)\n}\n\nobject MIIRxTester extends App {\n private val pathToVCD = \"generated/\" + this.getClass.getSimpleName.dropRight(1)\n private val nameOfVCD = this.getClass.getSimpleName.dropRight(7) + \".vcd\"\n\n try {\n chiselMainTest(Array(\"--genHarness\", \"--test\", \"--backend\", \"c\",\n \"--compile\", \"--vcd\", \"--targetDir\", \"generated/\" + this.getClass.getSimpleName.dropRight(1)),\n () => Module(new MIIRx())) {\n dut => new MIIRxTester(dut, EthernetTesting.mockupPTPEthFrameOverIpUDP)\n }\n } finally {\n \"gtkwave \" + pathToVCD + \"/\" + nameOfVCD + \" \" + pathToVCD + \"/\" + \"view.sav &\" !\n }\n}\n", "groundtruth": " poke(dut.io.miiChannel.dv, 0)\n step(3)\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/test/scala/ethcontroller/design/MIITxTester.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.design\n\nimport Chisel.{Module, Tester, chiselMainTest}\nimport ethcontroller.protocols.{EthernetFrame, EthernetTesting}\n\nimport scala.language.postfixOps\nimport scala.sys.process._\n\nclass MIITxTester(dut: MIITx, frame: EthernetFrame) extends Tester(dut) {\n // Shifting of discrete numbers for clarity\n var byteAddr = 0\n // poke(dut.io.startTx, true)\n poke(dut.io.miiChannel.clk, 0)\n step(3)\n // poke(dut.io.startTx, false)\n println(\"-- Testing the preamble\")\n while(byteAddr < frame.preamble.length){\n if(peek(dut.io.ready) == 1){\n poke(dut.io.macDataDv, true)\n poke(dut.io.macData, BigInt(frame.preamble(byteAddr)))\n byteAddr+=1\n }\n peek(dut.serializeByteToNibble.selHi)\n peek(dut.serializeByteToNibble.selLo)\n poke(dut.io.miiChannel.clk, 0)\n step(1)\n poke(dut.io.macDataDv, false)\n step(2)\n poke(dut.io.miiChannel.clk, 1)\n step(3)\n }\n while(peek(dut.io.ready) == 0){\n poke(dut.io.miiChannel.clk, 0)\n step(3)\n poke(dut.io.miiChannel.clk, 1)\n step(3)\n }\n // poke(dut.io.endTx, true)\n poke(dut.io.miiChannel.clk, 0)\n step(1)\n // poke(dut.io.endTx, true)\n step(2)\n poke(dut.io.miiChannel.clk, 1)\n step(3)\n poke(dut.io.miiChannel.clk, 0)\n step(3)\n poke(dut.io.miiChannel.clk, 1)\n step(3)\n expect(dut.io.miiChannel.dv, false, \"Expecting an idle bus\")\n expect(dut.serializeByteToNibble.io.done, true, \"Expecting the serializer to have finished\")\n}\n\nobject MIITxTester extends App {\n private val pathToVCD = \"generated/\" + this.getClass.getSimpleName.dropRight(1)\n private val nameOfVCD = this.getClass.getSimpleName.dropRight(7) + \".vcd\"\n\n try {\n chiselMainTest(Array(\"--genHarness\", \"--test\", \"--backend\", \"c\",\n \"--compile\", \"--vcd\", \"--targetDir\", \"generated/\" + this.getClass.getSimpleName.dropRight(1)),\n", "right_context": "", "groundtruth": " () => Module(new MIITx())) {\n dut => new MIITxTester(dut, EthernetTesting.mockupPTPEthFrameOverIpUDP)\n }\n } finally {\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/test/scala/ethcontroller/protocols/EthernetTesting.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.protocols\n\nobject EthernetTesting {\n\n val mockupPTPEthFrameDHCP = new DefaultEthFrame {\n override val dstMac: Array[Byte] = EthernetUtils.toBytes(0xff, 0xff, 0xff, 0xff, 0xff, 0xff)\n override val srcMac: Array[Byte] = EthernetUtils.toBytes(0x80, 0xce, 0x62, 0xd8, 0xc7, 0x39)\n override val ethType: Array[Byte] = EthernetUtils.toBytes(0x08, 0x00)\n override val ipHeader: Array[Byte] = EthernetUtils.toBytes(0x45, 0x10, 0x01, 0x48, 0x00, 0x00, 0x00, 0x00,\n 0x80, 0x11, 0x39, 0x96, 0x00, 0x00, 0x00, 0x00,\n 0xff, 0xff, 0xff, 0xff)\n override val udpHeader: Array[Byte] = EthernetUtils.toBytes(0x00, 0x44, 0x00, 0x43, 0x01, 0x34, 0x5c, 0xec)\n //Should be ignored\n override val ptpHeader: Array[Byte] = EthernetUtils.toBytes(PTP_FOLLOW_UP_TYPE, 0x02, 0x00, 0x2C, 0x00, 0x00, 0x00, 0x00,\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n 0x00, 0x00, 0x00, 0x00, 0xE4, 0xAF, 0xA1, 0x30,\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x55, 0x55,\n 0x00, 0x00)\n override val ptpBody: Array[Byte] = EthernetUtils.toBytes(0x54, 0x32, 0x11, 0x11, 0x55, 0x55, 0xAA, 0xAA)\n override val ptpSuffix: Array[Byte] = EthernetUtils.toBytes(0x00)\n override val fcs: Array[Byte] = EthernetUtils.toBytes(0x00)\n override val igp: Array[Byte] = EthernetUtils.toBytes(0x00)\n override val data: Array[Byte] = ipHeader ++ udpHeader ++ ptpHeader ++ ptpBody ++ ptpSuffix ++ fcs ++ igp\n }\n val mockupPTPVLANFrameOverIpUDP = new DefaultEthFrame {\n override val dstMac: Array[Byte] = EthernetUtils.toBytes(0x01, 0x00, 0x5E, 0x00, 0x01, 0x81)\n override val srcMac: Array[Byte] = EthernetUtils.toBytes(0x01, 0x00, 0x5E, 0x00, 0x01, 0x81)\n override val ethType: Array[Byte] = EthernetUtils.toBytes(0x81, 0x00, 0x01, 0x11, 0x08, 0x00)\n override val ipHeader: Array[Byte] = EthernetUtils.toBytes(0x45, 0x00, 0x00, 0x48, 0x00, 0x5D, 0x40, 0x00,\n 0x01, 0x11, 0x29, 0x68, 0xC0, 0xA8, 0x01, 0x01,\n 0xE0, 0x00, 0x01, 0x81)\n override val udpHeader: Array[Byte] = EthernetUtils.toBytes(0x01, 0x3F, 0x01, 0x3F, 0x00, 0x34, 0x00, 0x00)\n override val ptpHeader: Array[Byte] = EthernetUtils.toBytes(PTP_FOLLOW_UP_TYPE, 0x02, 0x00, 0x2C, 0x00, 0x00, 0x00, 0x00,\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n 0x00, 0x00, 0x00, 0x00, 0xE4, 0xAF, 0xA1, 0x30,\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x55, 0x55,\n 0x00, 0x00)\n override val ptpBody: Array[Byte] = EthernetUtils.toBytes(0x54, 0x32, 0x11, 0x11, 0x55, 0x55, 0xAA, 0xAA)\n override val ptpSuffix: Array[Byte] = EthernetUtils.toBytes(0x00)\n override val fcs: Array[Byte] = EthernetUtils.toBytes(0x00)\n override val igp: Array[Byte] = EthernetUtils.toBytes(0x00)\n override val data: Array[Byte] = ipHeader ++ udpHeader ++ ptpHeader ++ ptpBody ++ ptpSuffix ++ fcs ++ igp\n }\n val mockupPTPEthFrameOverIpUDP = new DefaultEthFrame {\n override val dstMac: Array[Byte] = EthernetUtils.toBytes(0x01, 0x00, 0x5E, 0x00, 0x01, 0x81)\n override val srcMac: Array[Byte] = EthernetUtils.toBytes(0x01, 0x00, 0x5E, 0x00, 0x01, 0x81)\n override val ethType: Array[Byte] = EthernetUtils.toBytes(0x08, 0x00)\n override val ipHeader: Array[Byte] = EthernetUtils.toBytes(0x45, 0x00, 0x00, 0x48, 0x00, 0x5D, 0x40, 0x00,\n 0x01, 0x11, 0x29, 0x68, 0xC0, 0xA8, 0x01, 0x01,\n 0xE0, 0x00, 0x01, 0x81)\n override val udpHeader: Array[Byte] = EthernetUtils.toBytes(0x01, 0x3F, 0x01, 0x3F, 0x00, 0x34, 0x00, 0x00)\n override val ptpHeader: Array[Byte] = EthernetUtils.toBytes(PTP_FOLLOW_UP_TYPE, 0x02, 0x00, 0x2C, 0x00, 0x00, 0x00, 0x00,\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n 0x00, 0x00, 0x00, 0x00, 0xE4, 0xAF, 0xA1, 0x30,\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x55, 0x55,\n 0x00, 0x00)\n override val ptpBody: Array[Byte] = EthernetUtils.toBytes(0x54, 0x32, 0x11, 0x11, 0x55, 0x55, 0xAA, 0xAA)\n override val ptpSuffix: Array[Byte] = EthernetUtils.toBytes(0x00)\n override val fcs: Array[Byte] = EthernetUtils.toBytes(0x00)\n override val igp: Array[Byte] = EthernetUtils.toBytes(0x00)\n override val data: Array[Byte] = ipHeader ++ udpHeader ++ ptpHeader ++ ptpBody ++ ptpSuffix ++ fcs ++ igp\n }\n val mockupTTEPCFFrame = new DefaultEthFrame {\n override val dstMac: Array[Byte] = EthernetUtils.toBytes(0xAB, 0xAD, 0xBA, 0xBE, 0x0F, 0xCE)\n override val srcMac: Array[Byte] = EthernetUtils.toBytes(0x00, 0x11, 0x22, 0x33, 0x44, 0x55)\n override val ethType: Array[Byte] = EthernetUtils.toBytes(0x89, 0x1D)\n override val data: Array[Byte] = EthernetUtils.toBytes(0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x02, 0x00,\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1b, 0xc0, 0x00, 0x00)\n }\n\n class DefaultEthFrame extends EthernetFrame {\n override val preamble: Array[Byte] = EthernetUtils.toBytes(0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xD5)\n override val dstMac: Array[Byte] = Array.emptyByteArray\n override val srcMac: Array[Byte] = Array.emptyByteArray\n override val ethType: Array[Byte] = Array.emptyByteArray\n override val ipHeader: Array[Byte] = Array.emptyByteArray\n override val udpHeader: Array[Byte] = Array.emptyByteArray\n override val ptpHeader: Array[Byte] = Array.emptyByteArray\n override val ptpBody: Array[Byte] = Array.emptyByteArray\n", "right_context": "\n}", "groundtruth": " override val ptpSuffix: Array[Byte] = Array.emptyByteArray\n override val fcs: Array[Byte] = Array.emptyByteArray\n override val igp: Array[Byte] = Array.emptyByteArray\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/test/scala/ethcontroller/utils/DeserializerTester.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.utils\n\nimport Chisel._\nimport ethcontroller.protocols.{EthernetFrame, EthernetTesting}\n\nimport scala.language.postfixOps\nimport scala.sys.process._\n\nclass DeserializerTester(dut: Deserializer, frame: EthernetFrame) extends Tester(dut) {\n // Shifting of discrete numbers for clarity\n poke(dut.io.en, true)\n for (i <- frame.preambleNibbles) {\n poke(dut.io.shiftIn, i)\n", "right_context": " expect(dut.io.shiftOut, frame.PREAMBLE_END)\n poke(dut.io.en, false)\n step(1)\n poke(dut.io.clr, true)\n step(1)\n expect(dut.countReg, 8 / 4 - 1)\n expect(dut.shiftReg, 0)\n expect(dut.doneReg, false)\n}\n\nobject DeserializerTester extends App {\n private val pathToVCD = \"generated/\" + this.getClass.getSimpleName.dropRight(1)\n private val nameOfVCD = this.getClass.getSimpleName.dropRight(7) + \".vcd\"\n\n try {\n chiselMainTest(Array(\"--genHarness\", \"--test\", \"--backend\", \"c\",\n \"--compile\", \"--vcd\", \"--targetDir\", \"generated/\" + this.getClass.getSimpleName.dropRight(1)),\n () => Module(new Deserializer(false, 4, 8))) {\n dut => new DeserializerTester(dut, EthernetTesting.mockupPTPEthFrameOverIpUDP)\n }\n } finally {\n \"gtkwave \" + pathToVCD + \"/\" + nameOfVCD + \" \" + pathToVCD + \"/\" + \"view.sav\" !\n }\n}\n", "groundtruth": " peek(dut.io.shiftOut)\n peek(dut.io.done)\n step(1)\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/test/scala/ethcontroller/utils/SerializerTester.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.utils\n\nimport Chisel._\nimport ethcontroller.protocols.{EthernetFrame, EthernetTesting}\n\nimport scala.language.postfixOps\nimport scala.sys.process._\n\nclass SerializerTester(dut: Serializer, frame: EthernetFrame) extends Tester(dut) {\n // Shifting of discrete numbers for clarity\n poke(dut.io.en, true)\n for (i <- frame.preamble) {\n step(1)\n poke(dut.io.load, true)\n poke(dut.io.shiftIn, i.toInt)\n step(1)\n poke(dut.io.load, false)\n do {\n step(1)\n } while (peek(dut.io.done) == 0)\n peek(dut.io.shiftOut)\n }\n expect(dut.io.done, true)\n expect(dut.io.shiftOut, frame.PREAMBLE_END)\n step(1)\n poke(dut.io.en, false)\n expect(dut.countReg, 8 / 4 - 1)\n expect(dut.shiftReg, 0)\n expect(dut.doneReg, false)\n}\n\nobject SerializerTester extends App {\n private val pathToVCD = \"generated/\" + this.getClass.getSimpleName.dropRight(1)\n private val nameOfVCD = this.getClass.getSimpleName.dropRight(7) + \".vcd\"\n\n try {\n chiselMainTest(Array(\"--genHarness\", \"--test\", \"--backend\", \"c\",\n \"--compile\", \"--vcd\", \"--targetDir\", \"generated/\" + this.getClass.getSimpleName.dropRight(1)),\n", "right_context": " }\n}", "groundtruth": " () => Module(new Serializer(false, 8, 4))) {\n dut => new SerializerTester(dut, EthernetTesting.mockupPTPEthFrameOverIpUDP)\n }\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/ALU.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chisel3.util.{is, switch}\nimport chiselv.Instruction._\n\nclass ALUPort(bitWidth: Int = 32) extends Bundle {\n val inst = Input(Instruction())\n val a = Input(UInt(bitWidth.W))\n val b = Input(UInt(bitWidth.W))\n val x = Output(UInt(bitWidth.W))\n}\nclass ALU(bitWidth: Int = 32) extends Module {\n val io = IO(new ALUPort(bitWidth))\n val out = WireDefault(0.U(bitWidth.W))\n\n // For RV32I the shift amount is 5 bits, for RV64I is 6 bits\n", "right_context": "\n switch(io.inst) {\n // Arithmetic\n is(ADD, ADDI)(out := io.a + io.b)\n is(SUB)(out := io.a - io.b)\n // Shifts\n is(SRA, SRAI)(out := (io.a.asSInt >> io.b(shamt, 0)).asUInt) // Signed\n is(SRL, SRLI)(out := io.a >> io.b(shamt, 0))\n is(SLL, SLLI)(out := io.a << io.b(shamt, 0))\n // Logical\n is(AND, ANDI)(out := io.a & io.b)\n is(OR, ORI)(out := io.a \| io.b)\n is(XOR, XORI)(out := io.a ^ io.b)\n // Compare\n is(SLT, SLTI)(out := Mux(io.a.asSInt < io.b.asSInt, 1.U, 0.U)) // Signed\n is(SLTU, SLTIU)(out := Mux(io.a < io.b, 1.U, 0.U))\n // Auxiliary\n is(EQ)(out := Mux(io.a === io.b, 1.U, 0.U))\n is(NEQ)(out := Mux(io.a =/= io.b, 1.U, 0.U))\n is(GTE)(out := Mux(io.a.asSInt >= io.b.asSInt, 1.U, 0.U))\n is(GTEU)(out := Mux(io.a >= io.b, 1.U, 0.U))\n }\n\n io.x := out\n}\n", "groundtruth": " val shamt = (if (bitWidth == 32) 5 else if (bitWidth == 64) 6 else 0) - 1\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/Blink.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chisel3.util.Counter\n\n/*\n The blinking LED module.\n \n @constructor\n * creates a new blinking LED module that flashes every second.\n * @param freq\n * the frequency of the core in Hertz.\n * @param startOn\n * if true, the LED is initially on.\n * @param io_led0\n * (Output) is the led output\n */\nclass Blinky(freq: Int, startOn: Boolean = false) extends Module {\n val io = IO(new Bundle {\n val led0 = Output(Bool())\n })\n\n // Blink leds every second (start on)\n val led = RegInit(startOn.B)\n val (_, counterWrap) = Counter(true.B, freq / 2)\n", "right_context": "}\n", "groundtruth": " when(counterWrap) {\n led := ~led\n }\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/CPUSingleCycle.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chisel3.experimental.Analog\nimport chisel3.util.{Cat, Fill, is, switch}\nimport chiselv.Instruction._\n\nclass CPUSingleCycle(\n cpuFrequency: Int,\n entryPoint: Long,\n bitWidth: Int = 32,\n instructionMemorySize: Int = 1 * 1024,\n dataMemorySize: Int = 1 * 1024,\n numGPIO: Int = 8,\n ) extends Module {\n val io = IO(new Bundle {\n val GPIO0External = Analog(numGPIO.W) // GPIO external port\n\n val UART0Port = Flipped(new UARTPort) // UART0 data port\n val SysconPort = Flipped(new SysconPort(bitWidth))\n val instructionMemPort = Flipped(new InstructionMemPort(bitWidth, instructionMemorySize))\n val dataMemPort = Flipped(new MemoryPortDual(bitWidth, dataMemorySize))\n })\n\n val stall = WireDefault(false.B)\n\n // Instantiate and initialize the Register Bank\n val registerBank = Module(new RegisterBank(bitWidth))\n registerBank.io.writeEnable := false.B\n registerBank.io.regwr_data := 0.U\n registerBank.io.stall := stall\n\n // Instantiate and initialize the Program Counter\n val PC = Module(new ProgramCounter(bitWidth, entryPoint))\n PC.io.writeEnable := false.B\n PC.io.dataIn := 0.U\n PC.io.writeAdd := false.B\n\n // Instantiate and initialize the ALU\n val ALU = Module(new ALU(bitWidth))\n ALU.io.inst := ERR_INST\n ALU.io.a := 0.U\n ALU.io.b := 0.U\n\n // Instantiate and initialize the Instruction Decoder\n val decoder = Module(new Decoder(bitWidth))\n decoder.io.op := 0.U\n\n // Instantiate and initialize the Memory IO Manager\n val memoryIOManager = Module(new MemoryIOManager(bitWidth, dataMemorySize))\n memoryIOManager.io.MemoryIOPort.readRequest := false.B\n memoryIOManager.io.MemoryIOPort.writeRequest := false.B\n memoryIOManager.io.MemoryIOPort.readAddr := 0.U\n memoryIOManager.io.MemoryIOPort.writeAddr := 0.U\n memoryIOManager.io.MemoryIOPort.writeData := 0.U\n memoryIOManager.io.MemoryIOPort.dataSize := 0.U\n memoryIOManager.io.MemoryIOPort.writeMask := 0.U\n // Connect MMIO to the devices\n memoryIOManager.io.DataMemPort <> io.dataMemPort\n memoryIOManager.io.UART0Port <> io.UART0Port\n memoryIOManager.io.SysconPort <> io.SysconPort\n\n // Instantiate and connect GPIO\n val GPIO0 = Module(new GPIO(bitWidth, numGPIO))\n memoryIOManager.io.GPIO0Port <> GPIO0.io.GPIOPort\n if (numGPIO > 0) {\n GPIO0.io.externalPort <> io.GPIO0External\n }\n\n // Instantiate and connect the Timer\n val timer0 = Module(new Timer(bitWidth, cpuFrequency))\n memoryIOManager.io.Timer0Port <> timer0.io\n\n // --------------- CPU Control --------------- //\n // State of the CPU Stall\n stall := memoryIOManager.io.stall\n when(!stall) {\n // If CPU is stalled, do not advance PC\n PC.io.writeEnable := true.B\n PC.io.dataIn := PC.io.PC4\n }\n\n // Connect PC output to instruction memory\n when(io.instructionMemPort.ready) {\n io.instructionMemPort.readAddr := PC.io.PC\n }.otherwise(\n io.instructionMemPort.readAddr := DontCare\n )\n\n // Connect the instruction memory to the decoder\n decoder.io.op := io.instructionMemPort.readData\n\n // Connect the decoder output to register bank inputs\n registerBank.io.regwr_addr := decoder.io.rd\n registerBank.io.rs1_addr := decoder.io.rs1\n registerBank.io.rs2_addr := decoder.io.rs2\n\n // ----- CPU Operations ----- //\n\n // ALU Operations\n when(decoder.io.toALU) {\n ALU.io.inst := decoder.io.inst\n ALU.io.a := registerBank.io.rs1\n ALU.io.b := Mux(\n decoder.io.use_imm,\n decoder.io.imm.asUInt,\n registerBank.io.rs2,\n )\n\n registerBank.io.writeEnable := true.B\n registerBank.io.regwr_data := ALU.io.x\n }\n\n // Branch Operations\n when(decoder.io.branch) {\n ALU.io.a := registerBank.io.rs1\n ALU.io.b := registerBank.io.rs2\n switch(decoder.io.inst) {\n is(BEQ)(ALU.io.inst := EQ)\n is(BNE)(ALU.io.inst := NEQ)\n is(BLT)(ALU.io.inst := SLT)\n is(BGE)(ALU.io.inst := GTE)\n is(BLTU)(ALU.io.inst := SLTU)\n is(BGEU)(ALU.io.inst := GTEU)\n }\n when(ALU.io.x === 1.U) {\n PC.io.writeEnable := true.B\n PC.io.writeAdd := true.B\n PC.io.dataIn := decoder.io.imm.asUInt\n }\n }\n\n // Jump Operations\n when(decoder.io.jump) {\n // Write next instruction address to rd\n registerBank.io.writeEnable := true.B\n // Use the ALU to get the result\n ALU.io.inst := ADD\n ALU.io.a := PC.io.PC\n ALU.io.b := 4.U\n registerBank.io.regwr_data := ALU.io.x\n\n PC.io.writeEnable := true.B\n when(decoder.io.inst === JAL) {\n // Set PC to jump address\n PC.io.writeAdd := true.B\n PC.io.dataIn := decoder.io.imm.asUInt\n }\n when(decoder.io.inst === JALR) {\n // Set PC to jump address\n PC.io.dataIn := Cat(\n (registerBank.io.rs1 + decoder.io.imm.asUInt)(31, 1),\n 0.U,\n )\n }\n }\n\n // LUI\n when(decoder.io.inst === LUI) {\n registerBank.io.writeEnable := true.B\n registerBank.io.regwr_data := decoder.io.imm.asUInt\n }\n\n // AUIPC\n when(decoder.io.inst === AUIPC) {\n registerBank.io.writeEnable := true.B\n ALU.io.inst := ADD\n ALU.io.a := PC.io.PC\n ALU.io.b :=\n decoder.io.imm.asUInt\n registerBank.io.regwr_data := ALU.io.x\n }\n\n // Loads & Stores\n when(decoder.io.is_load \|\| decoder.io.is_store) {\n // Use the ALU to get the resulting address\n ALU.io.inst := ADD\n ALU.io.a := registerBank.io.rs1\n ALU.io.b := decoder.io.imm.asUInt\n\n memoryIOManager.io.MemoryIOPort.writeAddr := ALU.io.x\n memoryIOManager.io.MemoryIOPort.readAddr := ALU.io.x\n }\n\n when(decoder.io.is_load) {\n val dataSize = WireDefault(0.U(2.W)) // Data size, 1 = byte, 2 = halfword, 3 = word\n val dataOut = WireDefault(0.U(32.W))\n\n // Load Word\n", "right_context": " dataOut := Cat(\n Fill(16, memoryIOManager.io.MemoryIOPort.readData(15)),\n memoryIOManager.io.MemoryIOPort.readData(15, 0),\n )\n }\n // Load Halfword Unsigned\n when(decoder.io.inst === LHU) {\n dataSize := 2.U\n dataOut := Cat(Fill(16, 0.U), memoryIOManager.io.MemoryIOPort.readData(15, 0))\n }\n // Load Byte\n when(decoder.io.inst === LB) {\n dataSize := 1.U\n dataOut := Cat(\n Fill(24, memoryIOManager.io.MemoryIOPort.readData(7)),\n memoryIOManager.io.MemoryIOPort.readData(7, 0),\n )\n }\n // Load Byte Unsigned\n when(decoder.io.inst === LBU) {\n dataSize := 1.U\n dataOut := Cat(Fill(24, 0.U), memoryIOManager.io.MemoryIOPort.readData(7, 0))\n }\n memoryIOManager.io.MemoryIOPort.readRequest := decoder.io.is_load\n memoryIOManager.io.MemoryIOPort.dataSize := dataSize\n registerBank.io.writeEnable := true.B\n registerBank.io.regwr_data := dataOut\n }\n\n when(decoder.io.is_store) {\n // Define if operation is a load or store\n memoryIOManager.io.MemoryIOPort.writeRequest := decoder.io.is_store\n\n // Stores\n val dataOut = WireDefault(0.U(32.W))\n val dataSize = WireDefault(0.U(2.W)) // Data size, 1 = byte, 2 = halfword, 3 = word\n\n // Store Word\n when(decoder.io.inst === SW) {\n dataOut := registerBank.io.rs2\n dataSize := 3.U\n }\n // Store Halfword\n when(decoder.io.inst === SH) {\n dataOut := Cat(Fill(16, 0.U), registerBank.io.rs2(15, 0))\n dataSize := 2.U\n }\n // Store Byte\n when(decoder.io.inst === SB) {\n dataOut := Cat(Fill(24, 0.U), registerBank.io.rs2(7, 0))\n dataSize := 1.U\n }\n memoryIOManager.io.MemoryIOPort.dataSize := dataSize\n memoryIOManager.io.MemoryIOPort.writeData := dataOut\n }\n}\n", "groundtruth": " when(decoder.io.inst === LW) {\n dataSize := 3.U\n dataOut := memoryIOManager.io.MemoryIOPort.readData\n }\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/Constants.scala", "left_context": "package chiselv\n\nimport chisel3.ChiselEnum\n\nobject Instruction extends ChiselEnum {\n val ERR_INST,\n // RV32I\n ADD, ADDI, SUB, LUI, AUIPC, // Arithmetic\n SLL, SLLI, SRL, SRLI, SRA, SRAI, // Shifts\n AND, ANDI, OR, ORI, XOR, XORI, // Logical\n SLT, SLTI, SLTU, SLTIU, // Compare\n BEQ, BNE, BLT, BGE, BLTU, BGEU, // Branches\n JAL, JALR, // Jump & Link\n FENCE, FENCEI, // Sync\n ECALL, EBREAK, // Environment\n CSRRW, CSRRS, CSRRC, CSRRWI, CSRRSI, CSRRCI, // CSR\n LB, LH, LBU, LHU, LW, // Loads\n SB, SH, SW, // Stores\n EQ, NEQ, GTE, GTEU // Not instructions but auxiliaries\n = Value\n}\n\n", "right_context": "", "groundtruth": "object InstructionType extends ChiselEnum {\n val IN_ERR, INST_R, INST_I, INST_S, INST_B, INST_U, INST_J, INST_Z = Value\n}\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/DataMemory.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chisel3.util.experimental.loadMemoryFromFileInline\nimport chisel3.util.log2Ceil\n\nclass MemoryPortDual(val bitWidth: Int, val addressSize: Long) extends Bundle {\n val readAddress = Input(UInt(log2Ceil(addressSize).W))\n val readData = Output(UInt(bitWidth.W))\n val writeAddress = Input(UInt(log2Ceil(addressSize).W))\n val writeData = Input(UInt(bitWidth.W))\n val writeMask = Input(UInt((bitWidth / 8).W))\n val dataSize = Input(UInt(2.W))\n val writeEnable = Input(Bool())\n}\nclass DualPortRAM(\n bitWidth: Int = 32,\n sizeBytes: Long = 1,\n memoryFile: String = \"\",\n debugMsg: Boolean = false,\n ) extends Module {\n val words = sizeBytes / bitWidth\n val io = IO(new MemoryPortDual(bitWidth, sizeBytes))\n\n if (debugMsg) {\n println(s\"Dual-port Memory Parameters:\")\n println(s\" Words: $words\")\n println(s\" Size: \" + words * bitWidth + \" bytes\")\n println(s\" Bit width: $bitWidth bit\")\n println(s\" Addr Width: \" + io.readAddress.getWidth + \" bit\")\n }\n\n val mem = SyncReadMem(words, UInt(bitWidth.W))\n\n // Divide memory address by 4 to get the word due to pc+4 addressing\n val readAddress = io.readAddress >> 2\n val writeAddress = io.writeAddress >> 2\n\n if (memoryFile.trim().nonEmpty) {\n", "right_context": " loadMemoryFromFileInline(mem, memoryFile)\n }\n\n io.readData := mem.read(readAddress)\n\n when(io.writeEnable === true.B) {\n mem.write(writeAddress, io.writeData)\n }\n}\n", "groundtruth": " if (debugMsg) println(s\" Load memory file: \" + memoryFile)\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/Decoder.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chisel3.util._\nimport chiselv.Instruction._\nimport chiselv.InstructionType._\n\nclass DecoderPort(bitWidth: Int = 32) extends Bundle {\n val op = Input(UInt(bitWidth.W)) // Op is the 32 bit instruction read received for decoding\n val inst = Output(Instruction()) // Instruction is the decoded instruction\n val rd = Output(UInt(5.W)) // Rd is the 5 bit destiny register\n val rs1 = Output(UInt(5.W)) // Rs1 is the 5 bit source register 1\n val rs2 = Output(UInt(5.W)) // Rs2 is the 5 bit source register 2\n val imm = Output(SInt(bitWidth.W)) // Imm is the 32 bit immediate\n val toALU = Output(Bool()) // ToALU is a flag to indicate if the instruction is to be executed in the ALU\n val branch = Output(Bool()) // Branch is a flag to indicate if the instruction should jump and link. Update PC\n val use_imm = Output(Bool()) // Use_imm is a flag to indicate if the instruction has an immediate\n val jump = Output(Bool()) // jump is a flag to indicate if the instruction has is a jump\n val is_load = Output(Bool()) // is_load is a flag to indicate if the instruction has a load from memory\n val is_store = Output(Bool()) // is_store is a flag to indicate if the instruction has a store to memory\n}\n\nclass Decoder(bitWidth: Int = 32) extends Module {\n val io = IO(new DecoderPort(bitWidth))\n\n val signals =\n ListLookup(\n io.op,\n // format: off\n List( IN_ERR, ERR_INST, false.B, false.B, false.B, false.B, false.B, false.B), // Default values\n Array(\n /* inst_type, inst to_alu branch use_imm jump is_load is_store /\n // Arithmetic\n BitPat(\"b0000000??????????000?????0110011\") -> List(INST_R, ADD, true.B, false.B, false.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????000?????0010011\") -> List(INST_I, ADDI, true.B, false.B, true.B, false.B, false.B, false.B),\n BitPat(\"b0100000??????????000?????0110011\") -> List(INST_R, SUB, true.B, false.B, false.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????????????0110111\") -> List(INST_U, LUI, false.B, false.B, true.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????????????0010111\") -> List(INST_U, AUIPC, false.B, false.B, true.B, false.B, false.B, false.B),\n // Shifts\n BitPat(\"b0000000??????????001?????0110011\") -> List(INST_R, SLL, true.B, false.B, false.B, false.B, false.B, false.B),\n BitPat(\"b0000000??????????001?????0010011\") -> List(INST_I, SLLI, true.B, false.B, true.B, false.B, false.B, false.B),\n BitPat(\"b0000000??????????101?????0110011\") -> List(INST_R, SRL, true.B, false.B, false.B, false.B, false.B, false.B),\n BitPat(\"b0000000??????????101?????0010011\") -> List(INST_I, SRLI, true.B, false.B, true.B, false.B, false.B, false.B),\n BitPat(\"b0100000??????????101?????0110011\") -> List(INST_R, SRA, true.B, false.B, false.B, false.B, false.B, false.B),\n BitPat(\"b0100000??????????101?????0010011\") -> List(INST_I, SRAI, true.B, false.B, true.B, false.B, false.B, false.B),\n // Logical\n BitPat(\"b0000000??????????100?????0110011\") -> List(INST_R, XOR, true.B, false.B, false.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????100?????0010011\") -> List(INST_I, XORI, true.B, false.B, true.B, false.B, false.B, false.B),\n BitPat(\"b0000000??????????110?????0110011\") -> List(INST_R, OR, true.B, false.B, false.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????110?????0010011\") -> List(INST_I, ORI, true.B, false.B, true.B, false.B, false.B, false.B),\n BitPat(\"b0000000??????????111?????0110011\") -> List(INST_R, AND, true.B, false.B, false.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????111?????0010011\") -> List(INST_I, ANDI, true.B, false.B, true.B, false.B, false.B, false.B),\n // Compare\n BitPat(\"b0000000??????????010?????0110011\") -> List(INST_R, SLT, true.B, false.B, false.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????010?????0010011\") -> List(INST_I, SLTI, true.B, false.B, true.B, false.B, false.B, false.B),\n BitPat(\"b0000000??????????011?????0110011\") -> List(INST_R, SLTU, true.B, false.B, false.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????011?????0010011\") -> List(INST_I, SLTIU, true.B, false.B, true.B, false.B, false.B, false.B),\n // Branches\n BitPat(\"b?????????????????000?????1100011\") -> List(INST_B, BEQ, false.B, true.B, true.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????001?????1100011\") -> List(INST_B, BNE, false.B, true.B, true.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????100?????1100011\") -> List(INST_B, BLT, false.B, true.B, true.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????101?????1100011\") -> List(INST_B, BGE, false.B, true.B, true.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????110?????1100011\") -> List(INST_B, BLTU, false.B, true.B, true.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????111?????1100011\") -> List(INST_B, BGEU, false.B, true.B, true.B, false.B, false.B, false.B),\n // Jump & link\n BitPat(\"b?????????????????????????1101111\") -> List(INST_J, JAL, false.B, false.B, true.B, true.B, false.B, false.B),\n BitPat(\"b?????????????????000?????1100111\") -> List(INST_I, JALR, false.B, false.B, true.B, true.B, false.B, false.B),\n // Sync\n BitPat(\"b0000????????00000000000000001111\") -> List(INST_I, FENCE, false.B, false.B, false.B, false.B, false.B, false.B),\n BitPat(\"b00000000000000000000001000001111\") -> List(INST_I, FENCEI, false.B, false.B, true.B, false.B, false.B, false.B),\n // Environment\n BitPat(\"b00000000000000000000000001110011\") -> List(INST_I, ECALL, false.B, false.B, false.B, false.B, false.B, false.B),\n BitPat(\"b00000000000100000000000001110011\") -> List(INST_I, EBREAK, false.B, false.B, false.B, false.B, false.B, false.B),\n // CSR\n BitPat(\"b?????????????????001?????1110011\") -> List(INST_I, CSRRW, false.B, false.B, false.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????010?????1110011\") -> List(INST_I, CSRRS, false.B, false.B, false.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????011?????1110011\") -> List(INST_I, CSRRC, false.B, false.B, false.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????101?????1110011\") -> List(INST_I, CSRRWI, false.B, false.B, true.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????110?????1110011\") -> List(INST_I, CSRRSI, false.B, false.B, true.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????111?????1110011\") -> List(INST_I, CSRRCI, false.B, false.B, true.B, false.B, false.B, false.B),\n // Loads\n BitPat(\"b?????????????????000?????0000011\") -> List(INST_I, LB, false.B, false.B, true.B, false.B, true.B, false.B),\n BitPat(\"b?????????????????001?????0000011\") -> List(INST_I, LH, false.B, false.B, true.B, false.B, true.B, false.B),\n BitPat(\"b?????????????????100?????0000011\") -> List(INST_I, LBU, false.B, false.B, true.B, false.B, true.B, false.B),\n BitPat(\"b?????????????????101?????0000011\") -> List(INST_I, LHU, false.B, false.B, true.B, false.B, true.B, false.B),\n BitPat(\"b?????????????????010?????0000011\") -> List(INST_I, LW, false.B, false.B, true.B, false.B, true.B, false.B),\n // Stores\n BitPat(\"b?????????????????000?????0100011\") -> List(INST_S, SB, false.B, false.B, true.B, false.B, false.B, true.B),\n BitPat(\"b?????????????????001?????0100011\") -> List(INST_S, SH, false.B, false.B, true.B, false.B, false.B, true.B),\n BitPat(\"b?????????????????010?????0100011\") -> List(INST_S, SW, false.B, false.B, true.B, false.B, false.B, true.B),\n )\n ) // format: on\n\n io.rd := 0.U\n io.rs1 := 0.U\n io.rs2 := 0.U\n io.imm := 0.S\n io.inst := signals(1)\n io.toALU := signals(2)\n io.branch := signals(3)\n io.use_imm := signals(4)\n io.jump := signals(5)\n io.is_load := signals(6)\n io.is_store := signals(7)\n\n switch(signals(0)) {\n is(INST_R) {\n io.rd := io.op(11, 7)\n io.rs1 := io.op(19, 15)\n io.rs2 := io.op(24, 20)\n }\n is(INST_I) {\n io.rd := io.op(11, 7)\n io.rs1 := io.op(19, 15)\n io.imm := ImmGenerator(INST_I, io.op)\n }\n is(INST_S) {\n io.rs1 := io.op(19, 15)\n io.rs2 := io.op(24, 20)\n io.imm := ImmGenerator(INST_S, io.op)\n }\n is(INST_B) {\n io.rs1 := io.op(19, 15)\n io.rs2 := io.op(24, 20)\n io.imm := ImmGenerator(INST_B, io.op)\n }\n is(INST_U) {\n io.rd := io.op(11, 7)\n io.imm := ImmGenerator(INST_U, io.op)\n }\n is(INST_J) {\n io.rd := io.op(11, 7)\n io.imm := ImmGenerator(INST_J, io.op)\n }\n }\n\n /\n ImmGenerator generates the immadiate value depending on the instruction\n * type\n \n @param regType\n * is the instruction type from `Constants.scala`\n * @return\n * the imm value\n */\n def ImmGenerator(regType: InstructionType.Type, inst: UInt): SInt = regType match {\n", "right_context": " case INST_Z => Cat(Fill(27, 0.U), inst(19, 15)).asSInt // for csri\n case _ => 0.S\n }\n}\n", "groundtruth": " case INST_R => 0.S\n case INST_I => Cat(Fill(20, inst(31)), inst(31, 20)).asSInt\n case INST_S => Cat(Fill(20, inst(31)), inst(31, 25), inst(11, 7)).asSInt\n case INST_B => Cat(Fill(19, inst(31)), inst(31), inst(7), inst(30, 25), inst(11, 8), 0.U(1.W)).asSInt\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/GPIO.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chisel3.experimental.Analog\nimport chisel3.util.HasBlackBoxInline // For Analog type\n\nclass GPIOPort(bitWidth: Int = 32) extends Bundle {\n val dataIn = Input(UInt(bitWidth.W))\n val valueOut = Output(UInt(bitWidth.W))\n val directionOut = Output(UInt(bitWidth.W))\n val writeValue = Input(Bool())\n val writeDirection = Input(Bool())\n val stall = Output(Bool()) // >1 => Stall, 0 => Run\n}\n\nclass GPIO(bitWidth: Int = 32, numGPIO: Int = 8) extends Module {\n require(\n numGPIO <= bitWidth,\n \"Number of GPIOs must be less than or equal to the bitwidth, if needed, create another GPIO bank.\",\n )\n val io = IO(new Bundle {\n val GPIOPort = new GPIOPort(bitWidth)\n val externalPort = Analog(numGPIO.W)\n })\n\n val GPIO = RegInit(0.U(bitWidth.W))\n val direction = RegInit(0.U(bitWidth.W)) // 0 = input, 1 = output\n\n io.GPIOPort.stall := false.B\n io.GPIOPort.directionOut := direction\n\n // Only instantiate GPIO external interface if needed\n // this avoids using Verilator backend on tests that don't need it\n if (numGPIO > 0) {\n val InOut = Module(new GPIOInOut(numGPIO))\n io.GPIOPort.valueOut := InOut.io.dataOut\n InOut.io.dataIn := GPIO\n InOut.io.dir := direction\n io.externalPort <> InOut.io.dataIO\n } else {\n io.GPIOPort.valueOut := 0.U\n io.externalPort := DontCare\n }\n\n when(io.GPIOPort.writeValue) {\n GPIO := io.GPIOPort.dataIn\n }\n when(io.GPIOPort.writeDirection) {\n direction := io.GPIOPort.dataIn\n }\n}\n\nclass GPIOInOut(numGPIO: Int) extends BlackBox with HasBlackBoxInline {\n val io = IO(new Bundle {\n val dataIn = Input(UInt(numGPIO.W))\n val dataOut = Output(UInt(numGPIO.W))\n val dir = Input(UInt(numGPIO.W))\n val dataIO = Analog(numGPIO.W)\n })\n setInline(\n \"GPIOInOut.v\",\n s\"\"\"\|// This module is inspired by Lucas Teske's Riscow digital port\n \|// https://github.com/racerxdl/riskow/blob/main/devices/digital_port.v\n \|//\n \|module GPIOInOut (\n \| inout [${numGPIO - 1}:0] dataIO,\n \| input [${numGPIO - 1}:0] dataIn,\n", "right_context": " \| input [${numGPIO - 1}:0] dir);\n \|\n \| generate\n \| genvar idx;\n \| for(idx = 0; idx < $numGPIO; idx = idx+1) begin: register\n \| `ifdef SIMULATION\n \| assign dataIO[idx] = dir[idx] ? dataIn[idx] : 1'b0;\n \| `else\n \| assign dataIO [idx]= dir[idx] ? dataIn[idx] : 1'bZ;\n \| `endif\n \| end\n \| endgenerate\n \| assign dataOut = dataIO;\n \|\n \|endmodule\n \|\"\"\".stripMargin,\n )\n}\n", "groundtruth": " \| output [${numGPIO - 1}:0] dataOut,\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/InstructionMemory.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chisel3.util.experimental.loadMemoryFromFileInline\nimport chisel3.util.log2Ceil\n\nclass InstructionMemPort(val bitWidth: Int, val sizeBytes: Long) extends Bundle {\n val readAddr = Input(UInt(log2Ceil(sizeBytes).W))\n val readData = Output(UInt(bitWidth.W))\n val ready = Output(Bool())\n}\n\nclass InstructionMemory(\n bitWidth: Int = 32,\n sizeBytes: Long = 1,\n memoryFile: String = \"\",\n ) extends Module {\n val words = sizeBytes / bitWidth\n val io = IO(new InstructionMemPort(bitWidth, sizeBytes))\n\n val mem = Mem(words, UInt(bitWidth.W))\n // Divide memory address by 4 to get the word due to pc+4 addressing\n val readAddress = io.readAddr >> 2\n", "right_context": " io.ready := true.B\n}\n", "groundtruth": " if (memoryFile.trim().nonEmpty) {\n loadMemoryFromFileInline(mem, memoryFile)\n }\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/MemoryIOManager.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chisel3.util.{Cat, Fill, is, log2Ceil, switch}\n\n/* Memory Map\n \n 0x0000_0000 - 0x0000_00FF: Reserved\n * 0x0000_0100 - 0x0000_0FFF: Debug\n * 0x0000_1000 - 0x0000_1FFF: Syscon\n * 0x0000_2000 - 0x0000_FFFF: Reserved\n * 0x0003_0000 - 0x0003_FFFF: ROM (64KB)\n * 0x0001_0000 - 0x2FFF_FFFF: Reserved\n * 0x3000_0000 - 0x3000_0FFF: UART0\n * 0x00 (TX Write)\n * 0x04 (RX Read)\n * 0x0C (Status Read) [txFull\|rxFull\|txEmpty\|rxEmpty]\n * 0x10 (Clock Divisor Read/Write)\n * 0x3000_1000 - 0x3000_1FFF: GPIO0\n * 0x00 (direction - 0: input, 1: output)\n * 0x04 (value - 0: low, 1: high)\n * 0x3000_2000 - 0x3000_2FFF: PWM0\n * 0x3000_3000 - 0x3000_3FFF: Timer0\n * 0x00 (32 bit value in miliseconds)\n * 0x3000_4000 - 0x3FFF_FFFF: Reserved\n * 0x4000_0000 - 0x4FFF_FFFF: Reserved\n * 0x5000_0000 - 0x7000_0000: Reserved\n * 0x8000_0000 - 0x8FFF_FFFF: On-chip memory RAM\n * 0x9000_0000 - 0x9FFF_FFFF: Reserved\n /\n\nclass MMIOPort(val bitWidth: Int, val addressSize: Long) extends Bundle {\n val writeRequest = Input(Bool())\n val readRequest = Input(Bool())\n val readAddr = Input(UInt(log2Ceil(addressSize).W))\n val readData = Output(UInt(bitWidth.W))\n val writeAddr = Input(UInt(log2Ceil(addressSize).W))\n val writeData = Input(UInt(bitWidth.W))\n val writeMask = Input(UInt((bitWidth / 8).W))\n val dataSize = Input(UInt(2.W))\n}\n\nclass MemoryIOManager(bitWidth: Int = 32, sizeBytes: Long = 1024) extends Module {\n val io = IO(new Bundle {\n val MemoryIOPort = new MMIOPort(bitWidth, scala.math.pow(2, bitWidth).toLong)\n val GPIO0Port = Flipped(new GPIOPort(bitWidth))\n val Timer0Port = Flipped(new TimerPort(bitWidth))\n val UART0Port = Flipped(new UARTPort)\n val DataMemPort = Flipped(new MemoryPortDual(bitWidth, sizeBytes))\n val SysconPort = Flipped(new SysconPort(bitWidth))\n val stall = Output(Bool())\n })\n\n val dataOut = WireDefault(0.U(bitWidth.W))\n val readAddress = io.MemoryIOPort.readAddr\n val writeAddress = io.MemoryIOPort.writeAddr\n\n // Initialize IO\n io.GPIO0Port.dataIn := 0.U\n io.GPIO0Port.writeValue := false.B\n io.GPIO0Port.writeDirection := false.B\n\n io.Timer0Port.dataIn := 0.U\n io.Timer0Port.writeEnable := false.B\n\n io.UART0Port.txQueue.valid := false.B\n io.UART0Port.txQueue.bits := 0.U\n io.UART0Port.rxQueue.ready := false.B\n io.UART0Port.clockDivisor.bits := 0.U\n io.UART0Port.clockDivisor.valid := false.B\n\n io.DataMemPort.writeEnable := false.B\n io.DataMemPort.writeData := 0.U\n io.DataMemPort.readAddress := 0.U\n io.DataMemPort.writeAddress := 0.U\n io.DataMemPort.dataSize := 0.U\n io.DataMemPort.writeMask := 0.U\n\n io.SysconPort.Address := 0.U\n\n // Stall Management\n val stallLatency = WireDefault(0.U(4.W))\n val stallEnable = WireDefault(false.B)\n val DACK = RegInit(0.U(2.W))\n DACK := Mux(\n DACK > 0.U,\n DACK - 1.U,\n Mux(io.MemoryIOPort.readRequest \|\| io.MemoryIOPort.writeRequest, stallLatency, 0.U),\n )\n io.stall := (io.MemoryIOPort.readRequest \|\| io.MemoryIOPort.writeRequest) && DACK =/= 1.U && stallEnable\n\n / --- Syscon --- /\n when(readAddress(31, 12) === 0x0000_1L.U && io.MemoryIOPort.readRequest) {\n io.SysconPort.Address := readAddress(11, 0)\n dataOut := io.SysconPort.DataOut\n }\n\n / --- UART0 --- /\n when(readAddress(31, 12) === 0x3000_0L.U \|\| writeAddress(31, 12) === 0x3000_0L.U) {\n // Reads\n when(io.MemoryIOPort.readRequest) {\n when(readAddress(7, 0) === 0x04.U) {\n / RX /\n when(io.UART0Port.rxQueue.valid) {\n io.UART0Port.rxQueue.ready := true.B\n dataOut := io.UART0Port.rxQueue.bits\n }\n }\n / Status /\n .elsewhen(readAddress(7, 0) === 0x0c.U) {\n dataOut := Cat(io.UART0Port.txFull, io.UART0Port.rxFull, io.UART0Port.txEmpty, io.UART0Port.rxEmpty)\n }\n / Invalid /\n .otherwise(dataOut := 0.U)\n }\n // Writes (TX)\n when(io.MemoryIOPort.writeRequest) {\n when(writeAddress(7, 0) === 0x00.U) {\n / TX /\n io.UART0Port.txQueue.valid := true.B\n io.UART0Port.txQueue.bits := io.MemoryIOPort.writeData(7, 0)\n }\n / clock divisor /\n .elsewhen(writeAddress(7, 0) === 0x10.U) {\n io.UART0Port.clockDivisor.valid := true.B\n io.UART0Port.clockDivisor.bits := io.MemoryIOPort.writeData(7, 0)\n }\n }\n }\n\n // GPIO0\n when(readAddress(31, 12) === 0x3000_1L.U \|\| writeAddress(31, 12) === 0x3000_1L.U) {\n // Reads\n when(io.MemoryIOPort.readRequest) {\n // -- Direction\n when(readAddress(7, 0) === 0x00.U) {\n dataOut := io.GPIO0Port.directionOut\n }\n // -- Value\n .elsewhen(readAddress(7, 0) === 0x04.U) {\n dataOut := io.GPIO0Port.valueOut\n }\n .otherwise(dataOut := 0.U)\n }\n // Writes\n when(io.MemoryIOPort.writeRequest) {\n // -- Direction\n when(writeAddress(7, 0) === 0x00.U) {\n io.GPIO0Port.writeDirection := io.MemoryIOPort.writeRequest\n }\n // -- Value\n .elsewhen(writeAddress(7, 0) === 0x04.U) {\n io.GPIO0Port.writeValue := io.MemoryIOPort.writeRequest\n }\n io.GPIO0Port.dataIn := io.MemoryIOPort.writeData\n }\n\n }\n\n / --- PWM0 --- /\n when(readAddress(31, 12) === 0x3000_2L.U \|\| writeAddress(31, 12) === 0x3000_2L.U) {\n dataOut := 0.U\n }\n\n / --- Timer0 --- /\n when(readAddress(31, 12) === 0x3000_3L.U \|\| writeAddress(31, 12) === 0x3000_3L.U) {\n when(io.MemoryIOPort.writeRequest) {\n io.Timer0Port.writeEnable := io.MemoryIOPort.writeRequest\n io.Timer0Port.dataIn := io.MemoryIOPort.writeData\n }\n when(io.MemoryIOPort.readRequest) {\n dataOut := io.Timer0Port.dataOut\n }\n }\n\n / --- Data Memory --- /\n when(readAddress(31, 28) === 0x8.U \|\| writeAddress(31, 28) === 0x8.U) {\n // Stall core for 1 cycle\n stallLatency := 1.U\n stallEnable := true.B\n io.DataMemPort.readAddress := Cat(Fill(4, 0.U), readAddress(27, 0))\n\n switch(io.MemoryIOPort.dataSize) {\n is(3.U)(dataOut := io.DataMemPort.readData) // Read word\n is(2.U) { // Read halfword\n switch(io.DataMemPort.readAddress(1).asUInt) {\n is(1.U)(dataOut := Cat(Fill(16, 0.U), io.DataMemPort.readData(31, 16).asUInt)) // Read half word 1\n is(0.U)(dataOut := Cat(Fill(16, 0.U), io.DataMemPort.readData(15, 0).asUInt)) // Read half word 0\n }\n }\n is(1.U) { // Write byte\n switch(io.DataMemPort.readAddress(1, 0)) {\n is(3.U)(dataOut := Cat(Fill(24, 0.U), io.DataMemPort.readData(31, 24).asUInt)) // Read byte 3\n is(2.U)(dataOut := Cat(Fill(24, 0.U), io.DataMemPort.readData(23, 16).asUInt)) // Read byte 2\n is(1.U)(dataOut := Cat(Fill(24, 0.U), io.DataMemPort.readData(15, 8).asUInt)) // Read byte 1\n is(0.U)(dataOut := Cat(Fill(24, 0.U), io.DataMemPort.readData(7, 0).asUInt)) // Read byte 0\n }\n }\n }\n\n when(io.MemoryIOPort.writeRequest) {\n when(!io.stall) {\n val dataToWrite = WireDefault(0.U(bitWidth.W))\n val writeMask = WireDefault(0.U(4.W))\n\n io.DataMemPort.writeAddress := Cat(Fill(4, 0.U), writeAddress(27, 0))\n io.DataMemPort.writeEnable := io.MemoryIOPort.writeRequest\n\n switch(io.MemoryIOPort.dataSize) {\n is(3.U) { // Write word\n dataToWrite := io.MemoryIOPort.writeData\n writeMask := \"b1111\".U\n", "right_context": " writeMask := \"b0011\".U\n }\n }\n }\n is(1.U) { // Write byte\n switch(io.DataMemPort.writeAddress(1, 0)) {\n is(3.U) { // Write byte 3\n dataToWrite := Cat(io.MemoryIOPort.writeData(7, 0).asUInt, Fill(24, 0.U))\n writeMask := \"b1000\".U\n }\n is(2.U) { // Write byte 2\n dataToWrite := Cat(Fill(8, 0.U), io.MemoryIOPort.writeData(7, 0).asUInt, Fill(16, 0.U))\n writeMask := \"b0100\".U\n }\n is(1.U) { // Write byte 2\n dataToWrite := Cat(Fill(16, 0.U), io.MemoryIOPort.writeData(7, 0).asUInt, Fill(8, 0.U))\n writeMask := \"b0010\".U\n }\n is(0.U) { // Write byte 0\n dataToWrite := Cat(Fill(24, 0.U), io.MemoryIOPort.writeData(7, 0).asUInt)\n writeMask := \"b0001\".U\n }\n }\n }\n }\n\n val dataIn = Cat(\n Mux(writeMask(3), dataToWrite(3 8 + 7, 3 * 8), io.DataMemPort.readData(3 * 8 + 7, 3 * 8)),\n Mux(writeMask(2), dataToWrite(2 * 8 + 7, 2 * 8), io.DataMemPort.readData(2 * 8 + 7, 2 * 8)),\n Mux(writeMask(1), dataToWrite(1 * 8 + 7, 1 * 8), io.DataMemPort.readData(1 * 8 + 7, 1 * 8)),\n Mux(writeMask(0), dataToWrite(0 * 8 + 7, 0 * 8), io.DataMemPort.readData(0 * 8 + 7, 0 * 8)),\n )\n io.DataMemPort.writeData := dataIn\n dataOut := dataIn\n }\n }\n }\n\n io.MemoryIOPort.readData := dataOut\n}\n", "groundtruth": " }\n is(2.U) { // Write halfword\n switch(io.DataMemPort.writeAddress(1).asUInt) {\n is(1.U) { // Write half word 1\n dataToWrite := Cat(io.MemoryIOPort.writeData(15, 0).asUInt, Fill(16, 0.U))\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/PLLBlackBox.scala", "left_context": "package chiselv\n\nimport scala.io.Source\n\nimport chisel3._\nimport chisel3.util.HasBlackBoxInline\n\nclass PLL0(board: String) extends BlackBox with HasBlackBoxInline {\n val io = IO(new Bundle {\n val clki = Input(Clock())\n val clko = Output(Clock());\n", "right_context": "", "groundtruth": " val lock = Output(Clock())\n })\n\n val filename = \"pll_\" + board + \".v\"\n val verilog = Source.fromResource(filename).getLines().mkString(\"\\n\")\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/ProgramCounter.scala", "left_context": "package chiselv\n\nimport chisel3._\n\nclass PCPort(bitWidth: Int = 32) extends Bundle {\n val dataIn = Input(UInt(bitWidth.W))\n", "right_context": " val writeAdd = Input(Bool()) // 1 => Add dataIn to PC, 0 => Set dataIn to PC\n}\n\nclass ProgramCounter(regWidth: Int = 32, entryPoint: Long = 0) extends Module {\n val io = IO(new PCPort(regWidth))\n\n val pc = RegInit(entryPoint.U(regWidth.W))\n when(io.writeEnable) {\n pc := Mux(io.writeAdd, (pc.asSInt + io.dataIn.asSInt).asUInt, io.dataIn)\n }\n io.PC4 := pc + 4.U\n io.PC := pc\n}\n", "groundtruth": " val PC = Output(UInt(bitWidth.W))\n val PC4 = Output(UInt(bitWidth.W))\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/RVFI_Wrapper.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chisel3.util.{is, switch}\nimport circt.stage.ChiselStage\nimport mainargs.{Leftover, ParserForMethods, arg, main}\n\n// Chisel Bundle implementation of RISC-V Formal Interface (RVFI)\nclass RVFIPort extends Bundle {\n val valid = Output(Bool())\n val order = Output(UInt(64.W))\n val insn = Output(UInt(32.W))\n val trap = Output(Bool())\n val halt = Output(Bool())\n val intr = Output(Bool())\n val ixl = Output(UInt(2.W))\n val mode = Output(UInt(2.W))\n val rs1_addr = Output(UInt(5.W))\n val rs1_rdata = Output(UInt(32.W))\n val rs2_addr = Output(UInt(5.W))\n val rs2_rdata = Output(UInt(32.W))\n val rd_addr = Output(UInt(5.W))\n val rd_wdata = Output(UInt(32.W))\n val pc_rdata = Output(UInt(32.W))\n val pc_wdata = Output(UInt(32.W))\n val mem_addr = Output(UInt(32.W))\n val mem_rmask = Output(UInt(4.W))\n val mem_wmask = Output(UInt(4.W))\n val mem_rdata = Output(UInt(32.W))\n val mem_wdata = Output(UInt(32.W))\n}\n\nclass RVFICPUWrapper(\n cpuFrequency: Int = 50000000,\n bitWidth: Int = 32,\n instructionMemorySize: Int = 64 * 1024,\n dataMemorySize: Int = 64 * 1024,\n ) extends CPUSingleCycle(\n cpuFrequency = cpuFrequency,\n entryPoint = 0x0,\n bitWidth = bitWidth,\n instructionMemorySize = instructionMemorySize,\n dataMemorySize = dataMemorySize,\n numGPIO = 0,\n ) {\n val rvfi = IO(new RVFIPort) // RVFI interface for RISCV-Formal\n\n // RVFI Interface\n val rvfi_valid = RegInit(false.B)\n val rvfi_order = RegInit(0.U(64.W))\n val rvfi_insn = RegInit(0.U(32.W))\n\n val rvfi_halt = RegInit(false.B)\n\n val rvfi_intr = RegInit(false.B)\n val rvfi_mode = RegInit(3.U(2.W))\n\n val rvfi_mem_size_mask = WireDefault(0.U(2.W))\n switch(memoryIOManager.io.DataMemPort.dataSize) {\n is(1.U)(rvfi_mem_size_mask := 1.U)\n is(2.U)(rvfi_mem_size_mask := 3.U)\n is(3.U)(rvfi_mem_size_mask := 15.U)\n }\n\n // Connect RVFI interface outputs\n rvfi_valid := !reset.asBool && !stall\n when(rvfi_valid) {\n rvfi_order := rvfi_order + 1.U\n }\n rvfi.valid := rvfi_valid\n rvfi.order := rvfi_order\n", "right_context": " rvfi.rs1_rdata := registerBank.io.rs1\n rvfi.rs2_addr := registerBank.io.rs2_addr\n rvfi.rs2_rdata := registerBank.io.rs2\n rvfi.rd_addr := registerBank.io.regwr_addr\n rvfi.rd_wdata := registerBank.io.regwr_data\n\n rvfi.pc_rdata := PC.io.PC\n rvfi.pc_wdata := Mux(\n PC.io.writeAdd,\n (PC.io.PC.asSInt + PC.io.dataIn.asSInt).asUInt,\n PC.io.PC4,\n )\n\n rvfi.mem_addr := Mux(decoder.io.is_load \|\| decoder.io.is_store, ALU.io.x, 0.U)\n rvfi.mem_rdata := Mux(decoder.io.is_load, memoryIOManager.io.DataMemPort.readData, 0.U)\n rvfi.mem_rmask := Mux(decoder.io.is_load, rvfi_mem_size_mask, 0.U)\n\n rvfi.mem_wdata := Mux(decoder.io.is_store, memoryIOManager.io.DataMemPort.writeData, 0.U)\n rvfi.mem_wmask := Mux(decoder.io.is_store, rvfi_mem_size_mask, 0.U)\n\n rvfi.mode := rvfi_mode\n rvfi.trap := false.B\n when(decoder.io.inst === Instruction.ERR_INST) {\n rvfi.trap := true.B\n }\n\n rvfi.halt := rvfi_halt\n rvfi.intr := rvfi_intr\n rvfi.ixl := 1.U\n}\n\n// This is the Topmodule used in RISCV-Formal\nclass RVFI(\n bitWidth: Int = 32\n ) extends Module {\n val io = IO(new Bundle {\n val imem_addr = Output(UInt(bitWidth.W))\n val imem_ready = Input(Bool())\n val imem_rdata = Input(UInt(bitWidth.W))\n\n val dmem_rdata = Input(UInt(bitWidth.W))\n val dmem_raddr = Output(UInt(bitWidth.W))\n val dmem_waddr = Output(UInt(bitWidth.W))\n val dmem_wdata = Output(UInt(bitWidth.W))\n val dmem_wen = Output(Bool())\n })\n val rvfi = IO(new RVFIPort) // RVFI interface for RISCV-Formal\n\n // Instantiate the wrapped CPU with RVFI interface\n val CPU = Module(\n new RVFICPUWrapper(bitWidth)\n )\n\n // Initialize unused IO\n CPU.io.UART0Port.rxQueue.bits := 0.U\n CPU.io.UART0Port.rxEmpty := true.B\n CPU.io.UART0Port.txQueue.ready := true.B\n CPU.io.UART0Port.txFull := false.B\n CPU.io.UART0Port.txEmpty := true.B\n CPU.io.UART0Port.rxFull := false.B\n CPU.io.UART0Port.rxQueue.valid := false.B\n CPU.io.SysconPort.DataOut := 0.U\n\n // Connect RVFI port\n rvfi <> CPU.rvfi\n\n // Connect instruction memory\n io.imem_addr := CPU.io.instructionMemPort.readAddr\n CPU.io.instructionMemPort.readData := io.imem_rdata\n CPU.io.instructionMemPort.ready := io.imem_ready\n\n // Connect data memory\n io.dmem_waddr := CPU.io.dataMemPort.writeAddress\n io.dmem_wdata := CPU.io.dataMemPort.writeData\n io.dmem_wen := CPU.io.dataMemPort.writeEnable\n\n io.dmem_raddr := CPU.io.dataMemPort.readAddress\n CPU.io.dataMemPort.readData := io.dmem_rdata\n}\n\nobject RVFI {\n @main\n def run(@arg(short = 'c', doc = \"Chisel arguments\") chiselArgs: Leftover[String]) =\n // Generate SystemVerilog\n ChiselStage.emitSystemVerilogFile(\n new RVFI,\n chiselArgs.value.toArray,\n Array(\n // Removes debug information from the generated Verilog\n \"--strip-debug-info\",\n // Disables reg and memory randomization on initialization\n \"--disable-all-randomization\",\n // Creates memories with write masks in a single reg. Ref. https://github.com/llvm/circt/pull/4275\n \"--lower-memories\",\n // Avoids \"unexpected TOK_AUTOMATIC\" errors in Yosys. Ref. https://github.com/llvm/circt/issues/4751\n \"--lowering-options=disallowLocalVariables,disallowPackedArrays\",\n // Splits the generated Verilog into multiple files\n // \"--split-verilog\",\n // Generates the Verilog files in the specified directory\n \"-o=./generated/Toplevel_RVFI.sv\",\n ),\n )\n\n def main(args: Array[String]): Unit =\n ParserForMethods(this).runOrExit(args.toIndexedSeq)\n}\n", "groundtruth": " rvfi.insn := decoder.io.op\n\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/RegisterBank.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chisel3.util.log2Ceil\n\nclass RegisterBankPort(bitWidth: Int = 32) extends Bundle {\n val rs1 = Output(UInt(bitWidth.W))\n val rs2 = Output(UInt(bitWidth.W))\n val rs1_addr = Input(UInt(log2Ceil(bitWidth).W))\n val rs2_addr = Input(UInt(log2Ceil(bitWidth).W))\n", "right_context": " val stall = Input(Bool()) // >1 => Stall, 0 => Run\n}\n\nclass RegisterBank(numRegs: Int = 32, regWidth: Int = 32) extends Module {\n val io = IO(new RegisterBankPort(regWidth))\n\n val regs = RegInit(VecInit(Seq.fill(numRegs)(0.U(regWidth.W))))\n regs(0) := 0.U // Register x0 is always 0\n\n io.rs1 := regs(io.rs1_addr)\n io.rs2 := regs(io.rs2_addr)\n when(io.writeEnable && io.regwr_addr =/= 0.U && !io.stall) {\n regs(io.regwr_addr) := io.regwr_data\n }\n}\n", "groundtruth": " val regwr_addr = Input(UInt(log2Ceil(bitWidth).W))\n val regwr_data = Input(UInt(bitWidth.W))\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/SOC.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chisel3.experimental.Analog\n\nclass SOC(\n cpuFrequency: Int,\n entryPoint: Long,\n bitWidth: Int = 32,\n instructionMemorySize: Int = 1 * 1024,\n dataMemorySize: Int = 1 * 1024,\n memoryFile: String = \"\",\n ramFile: String = \"\",\n numGPIO: Int = 8,\n ) extends Module {\n val io = IO(new Bundle {\n val led0 = Output(Bool()) // LED 0 is the heartbeat\n val GPIO0External = Analog(numGPIO.W) // GPIO external port\n val UART0SerialPort = new UARTSerialPort // UART0 serial port\n })\n\n // Heartbeat LED - Keep on if reached an error\n val blink = Module(new Blinky(cpuFrequency))\n io.led0 := blink.io.led0\n\n // Instantiate and initialize the Instruction memory\n val instructionMemory = Module(new InstructionMemory(bitWidth, instructionMemorySize, memoryFile))\n instructionMemory.io.readAddr := 0.U\n\n // Instantiate and initialize the Data memory\n val dataMemory = Module(new DualPortRAM(bitWidth, dataMemorySize, ramFile))\n dataMemory.io.writeEnable := false.B\n dataMemory.io.writeData := 0.U\n dataMemory.io.readAddress := 0.U\n dataMemory.io.writeAddress := 0.U\n dataMemory.io.dataSize := 0.U\n dataMemory.io.writeMask := 0.U\n\n // Instantiate and connect the UART\n val fifoLength = 128\n val rxOverclock = 16\n val UART0 = Module(new Uart(fifoLength, rxOverclock))\n UART0.io.serialPort <> io.UART0SerialPort\n\n // Instantiate the Syscon Module\n val syscon = Module(new Syscon(32, cpuFrequency, numGPIO, entryPoint, instructionMemorySize, dataMemorySize))\n\n // Instantiate our core\n val core = Module(\n new CPUSingleCycle(cpuFrequency, entryPoint, bitWidth, instructionMemorySize, dataMemorySize, numGPIO)\n )\n\n // Connect the core to the devices\n core.io.instructionMemPort <> instructionMemory.io\n core.io.dataMemPort <> dataMemory.io\n core.io.UART0Port <> UART0.io.dataPort\n core.io.SysconPort <> syscon.io\n", "right_context": "", "groundtruth": " if (numGPIO > 0) {\n core.io.GPIO0External <> io.GPIO0External\n }\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/Syscon.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chisel3.util.{is, switch}\n\n", "right_context": " clockFreq: Long,\n numGPIO0: Int,\n bootAddr: Long,\n romSize: Int,\n ramSize: Int,\n ) extends Module {\n val io = IO(new SysconPort(bitWidth))\n\n val dataOut = WireDefault(0.U(bitWidth.W))\n\n switch(io.Address) {\n is(0x0L.U)(dataOut := 0xbaad_cafeL.U)\n // Clock frequency - (0x0000_1008)\n is(0x8L.U)(dataOut := clockFreq.asUInt)\n // Has UART0 - (0x0000_1010)\n is(0x10L.U)(dataOut := 1.U)\n // Has GPIO0 - (0x0000_1018)\n is(0x18L.U)(dataOut := 1.U)\n // Has PWM0 - (0x0000_1020)\n is(0x20L.U)(dataOut := 0.U)\n // Has Timer0 - (0x0000_1024)\n is(0x24L.U)(dataOut := 1.U)\n // Num GPIOs in GPIO0 - (0x0000_1028)\n is(0x28L.U)(dataOut := numGPIO0.asUInt)\n // Boot io.address - (0x0000_102c)\n is(0x2cL.U)(dataOut := bootAddr.asUInt)\n // ROM Size - (0x0000_1030)\n is(0x30L.U)(dataOut := romSize.asUInt)\n // RAM Size - (0x0000_1034)\n is(0x34L.U)(dataOut := ramSize.asUInt)\n }\n\n io.DataOut := dataOut\n}\n", "groundtruth": "class SysconPort(val bitWidth: Int) extends Bundle {\n val Address = Input(UInt(12.W))\n val DataOut = Output(UInt(bitWidth.W))\n}\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/Timer.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chisel3.util.Counter\n\nclass TimerPort(bitWidth: Int = 32) extends Bundle {\n val dataIn = Input(UInt(bitWidth.W))\n val dataOut = Output(UInt(bitWidth.W))\n val writeEnable = Input(Bool())\n val stall = Output(Bool()) // >1 => Stall, 0 => Run\n}\n\nclass Timer(bitWidth: Int = 32, cpuFrequency: Int) extends Module {\n val io = IO(new TimerPort(bitWidth))\n\n val counter = RegInit(0.U(bitWidth.W))\n\n when(io.writeEnable) {\n counter := io.dataIn\n }.otherwise {\n // Count up in milliseconds\n val (_, counterWrap) = Counter(true.B, cpuFrequency / 1000)\n", "right_context": " io.stall := false.B\n}\n", "groundtruth": " when(counterWrap) {\n counter := counter + 1.U\n }\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/Toplevel.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chisel3.experimental.Analog\nimport circt.stage.ChiselStage\nimport mainargs.{Leftover, ParserForMethods, arg, main}\n\n// Project Top level\nclass Toplevel(\n board: String,\n invReset: Boolean = true,\n cpuFrequency: Int,\n ) extends Module {\n val io = FlatIO(new Bundle {\n val led0 = Output(Bool()) // LED 0 is the heartbeat\n val UART0 = new UARTSerialPort // UART 0\n val GPIO0 = Analog(8.W) // GPIO 0\n })\n\n // Instantiate PLL module based on board\n val pll = Module(new PLL0(board))\n pll.io.clki := clock\n // Define if reset should be inverted based on board switch\n", "right_context": "\n // Instantiate the Core connecting using the PLL clock\n withClockAndReset(pll.io.clko, customReset) {\n val bitWidth = 32\n val instructionMemorySize = 64 * 1024\n val dataMemorySize = 64 * 1024\n val numGPIO = 8\n\n val SOC =\n Module(\n new SOC(\n cpuFrequency = cpuFrequency,\n entryPoint = 0x00000000,\n bitWidth = bitWidth,\n instructionMemorySize = instructionMemorySize,\n dataMemorySize = dataMemorySize,\n memoryFile = \"progload.mem\",\n ramFile = \"progload-RAM.mem\",\n numGPIO = numGPIO,\n )\n )\n\n // Connect IO\n io.led0 <> SOC.io.led0\n io.GPIO0 <> SOC.io.GPIO0External\n io.UART0 <> SOC.io.UART0SerialPort\n }\n}\n\n// The Main object extending App to generate the Verilog code.\nobject Toplevel {\n @main\n def run(\n // Parse command line arguments and extract required parameters\n @arg(short = 'b', doc = \"FPGA Board to use\") board: String = \"bypass\",\n @arg(short = 'r', doc = \"FPGA Board have inverted reset\") invreset: Boolean = false,\n @arg(short = 'f', doc = \"CPU Frequency to run core\") cpufreq: Int = 50000000,\n @arg(short = 'c', doc = \"Chisel arguments\") chiselArgs: Leftover[String],\n ) =\n // Generate SystemVerilog\n ChiselStage.emitSystemVerilogFile(\n new Toplevel(board, invreset, cpufreq),\n chiselArgs.value.toArray,\n Array(\n // Removes debug information from the generated Verilog\n \"--strip-debug-info\",\n // Disables reg and memory randomization on initialization\n \"--disable-all-randomization\",\n // Creates memories with write masks in a single reg. Ref. https://github.com/llvm/circt/pull/4275\n \"--lower-memories\",\n // Avoids \"unexpected TOK_AUTOMATIC\" errors in Yosys. Ref. https://github.com/llvm/circt/issues/4751\n \"--lowering-options=disallowLocalVariables,disallowPackedArrays\",\n ),\n )\n\n def main(args: Array[String]): Unit =\n ParserForMethods(this).runOrExit(args.toIndexedSeq)\n}\n", "groundtruth": " val customReset = if (invReset) ~reset.asBool else reset\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/Uart.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chisel3.util._\n\n/\n A simple TTL serial module. Idle is high. Start bits are low, stop bits\n * are high and we send each byte out LSB first. We only implement 8n1,\n * ie 1 start bit, no parity and 1 stop bit. There is no flow control, so\n * we might overflow the RX fifo if the rxQueue consumer can't keep up.\n \n We oversample RX. clockDivisor is set as follows:\n \n clockDivisor = (clock_freq / (baudrate * rxOverclock)) - 1\n \n When programming the divider, software currently assumes we overclock 16x.\n \n Also note that if the input clock frequency is low enough then the errors\n * introduced by oversampling might be significant. Eg at 10MHz, 115200 baud,\n * 16x oversampling we have almost 8% error and the UART fails to work.\n \n This file has been created by Anton Blanchard on Chiselwatt repository at:\n * https://github.com/antonblanchard/chiselwatt\n /\n\nclass UARTSerialPort extends Bundle {\n val rx = Input(UInt(1.W))\n val tx = Output(UInt(1.W))\n}\n\nclass UARTPort extends Bundle {\n val rxQueue = Decoupled(UInt(8.W))\n val txQueue = Flipped(Decoupled(UInt(8.W)))\n val rxEmpty = Output(Bool())\n val txEmpty = Output(Bool())\n val rxFull = Output(Bool())\n val txFull = Output(Bool())\n val clockDivisor = Flipped(Valid(UInt(8.W)))\n}\n\nclass Uart(val fifoLength: Int, val rxOverclock: Int) extends Module {\n val io = IO(new Bundle {\n val serialPort = new UARTSerialPort\n val dataPort = new UARTPort\n })\n\n require(isPow2(rxOverclock))\n\n val sampleClk = RegInit(0.U(1.W))\n val sampleClkCounter = RegInit(0.U(8.W))\n val clockDivisor = RegInit(0.U(8.W))\n\n when(io.dataPort.clockDivisor.valid) {\n clockDivisor := io.dataPort.clockDivisor.bits\n }\n\n val txQueue = Module(new Queue(UInt(8.W), fifoLength))\n val rxQueue = Module(new Queue(UInt(8.W), fifoLength))\n\n io.dataPort.rxEmpty := rxQueue.io.count === 0.U\n io.dataPort.txEmpty := txQueue.io.count === 0.U\n io.dataPort.rxFull := rxQueue.io.count === fifoLength.U\n io.dataPort.txFull := txQueue.io.count === fifoLength.U\n\n val uartEnabled = clockDivisor.orR\n\n when(uartEnabled) {\n when(sampleClkCounter === clockDivisor) {\n sampleClk := 1.U\n sampleClkCounter := 0.U\n }.otherwise {\n sampleClk := 0.U\n sampleClkCounter := sampleClkCounter + 1.U\n }\n }.otherwise {\n sampleClk := 0.U\n sampleClkCounter := 0.U\n }\n\n /\n * Our TX clock needs to match our baud rate. This means we need to\n * further divide sampleClk by rxOverclock.\n /\n val (txCounterValue, txCounterWrap) = Counter(sampleClk === 1.U, rxOverclock)\n val txClk = txCounterWrap\n\n / TX /\n val sTxIdle :: sTxTx :: sTxStop :: Nil = Enum(3)\n val txState = RegInit(sTxIdle)\n val txByte = Reg(UInt(8.W))\n val txByteBit = Reg(UInt(3.W))\n / RS232 idle state is high /\n val tx = RegInit(1.U(1.W))\n\n txQueue.io.deq.ready := false.B\n\n / We run the tx state machine off the txClk /\n when(txClk === 1.U) {\n switch(txState) {\n is(sTxIdle) {\n / Does the FIFO contain data? /\n when(txQueue.io.deq.valid) {\n txQueue.io.deq.ready := true.B\n txByte := txQueue.io.deq.bits\n txByteBit := 0.U\n txState := sTxTx\n / Send start bit /\n tx := 0.U\n }.otherwise {\n tx := 1.U\n }\n }\n\n is(sTxTx) {\n when(txByteBit === 7.U) {\n txState := sTxStop\n }\n tx := txByte(txByteBit)\n txByteBit := txByteBit + 1.U\n }\n\n is(sTxStop) {\n txState := sTxIdle\n / Send stop bit /\n tx := 1.U\n }\n }\n }\n\n io.serialPort.tx := tx\n\n / RX /\n val sRxIdle :: sRxStart :: sRxRx :: sRxStop :: sRxError1 :: sRxError2 :: Nil =\n Enum(6)\n val rxState = RegInit(sRxIdle)\n val rxCounter = RegInit(0.U(log2Ceil(rxOverclock).W))\n val rxByte = RegInit(VecInit(Seq.fill(8)(0.U(1.W))))\n val rxByteBit = RegInit(0.U(3.W))\n\n rxQueue.io.enq.bits := 0.U\n rxQueue.io.enq.valid := false.B\n\n / Synchronize the input to avoid any metastability issues /\n val rx = RegNext(RegNext(RegNext(io.serialPort.rx)))\n\n when(sampleClk === 1.U) {\n switch(rxState) {\n is(sRxIdle) {\n when(rx === 0.U) {\n rxState := sRxStart\n rxCounter := 1.U\n rxByte := Seq.fill(8)(0.U)\n rxByteBit := 0.U\n }\n }\n\n is(sRxStart) {\n rxCounter := rxCounter + 1.U\n / We should be at the middle of the start bit /\n when(rxCounter === (rxOverclock / 2).U) {\n rxCounter := 1.U\n rxState := sRxRx\n }\n }\n\n is(sRxRx) {\n rxCounter := rxCounter + 1.U\n when(rxCounter === 0.U) {\n when(rxByteBit === 7.U) {\n rxState := sRxStop\n }\n rxByte(rxByteBit) := rx\n rxByteBit := rxByteBit + 1.U\n }\n }\n\n is(sRxStop) {\n rxCounter := rxCounter + 1.U\n when(rxCounter === 0.U) {\n / Ensure the stop bit is high /\n", "right_context": " }\n }\n\n /\n * We might not have synchronised on a start bit. Delay 2 bits on\n * each error so we eventually line up with the start bit.\n /\n is(sRxError1) {\n / Delay one bit /\n rxCounter := rxCounter + 1.U\n when(rxCounter === 0.U) {\n rxState := sRxError2\n }\n }\n\n is(sRxError2) {\n / Delay another bit /\n rxCounter := rxCounter + 1.U\n when(rxCounter === 0.U) {\n rxState := sRxIdle\n }\n }\n }\n }\n\n rxQueue.io.deq <> io.dataPort.rxQueue\n txQueue.io.enq <> io.dataPort.txQueue\n}\n", "groundtruth": " when(rx === 1.U) {\n / We might overflow the queue if we can't keep up */\n rxQueue.io.enq.bits := rxByte.reverse.reduce(_ ## _)\n rxQueue.io.enq.valid := true.B\n rxState := sRxIdle\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/test/src/ALUSpec.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chiseltest._\nimport com.carlosedp.riscvassembler.ObjectUtils.NumericManipulation\nimport org.scalatest._\n\nimport Instruction._\nimport flatspec._\nimport matchers._\n\nclass ALUSpec extends AnyFlatSpec with ChiselScalatestTester with should.Matchers {\n val one = BigInt(1)\n val max = (one << 32) - one\n val min_signed = one << 32 - 1\n val max_signed = (one << 32 - 1) - one\n val cases =\n Array[BigInt](1, 2, 4, 123, -1, -2, -4, 0, 0x7fffffffL, 0x80000000L, max, min_signed, max_signed) ++ Seq.fill(10)(\n BigInt(scala.util.Random.nextInt())\n )\n\n it should \"ADD\" in {\n testCycle(ADD)\n }\n it should \"ADDI\" in {\n testCycle(ADDI)\n }\n it should \"SUB\" in {\n testCycle(SUB)\n }\n it should \"AND\" in {\n testCycle(AND)\n }\n it should \"ANDI\" in {\n testCycle(ANDI)\n }\n it should \"OR\" in {\n testCycle(OR)\n }\n it should \"ORI\" in {\n testCycle(ORI)\n }\n it should \"XOR\" in {\n testCycle(XOR)\n }\n it should \"XORI\" in {\n testCycle(XORI)\n }\n it should \"SRA\" in {\n testCycle(SRA)\n }\n it should \"SRAI\" in {\n testCycle(SRAI)\n }\n it should \"SRL\" in {\n testCycle(SRL)\n }\n it should \"SRLI\" in {\n testCycle(SRLI)\n }\n it should \"SLL\" in {\n testCycle(SLL)\n }\n it should \"SLLI\" in {\n testCycle(SLLI)\n }\n it should \"SLT\" in {\n testCycle(SLT)\n }\n it should \"SLTI\" in {\n testCycle(SLTI)\n }\n it should \"SLTU\" in {\n testCycle(SLTU)\n }\n it should \"SLTIU\" in {\n testCycle(SLTIU)\n }\n it should \"EQ\" in {\n testCycle(EQ)\n }\n it should \"NEQ\" in {\n testCycle(NEQ)\n }\n it should \"GT\" in {\n testCycle(GTE)\n }\n it should \"GTU\" in {\n testCycle(GTEU)\n }\n // --------------------- Test Helpers ---------------------\n def aluHelper(\n a: BigInt,\n b: BigInt,\n op: Type,\n ): BigInt =\n op match {\n case ADD \| ADDI => (a + b).to32Bit\n case SUB => a - b\n case AND \| ANDI => a & b\n case OR \| ORI => a \| b\n case XOR \| XORI => a ^ b\n case SRA \| SRAI => a.toInt >> (b.toInt & 0x1f)\n case SRL \| SRLI => a.toInt >>> b.toInt\n case SLL \| SLLI => a.toInt << b.toInt\n case SLT \| SLTI => if (a.toInt < b.toInt) 1 else 0\n case SLTU \| SLTIU => if (a.to32Bit < b.to32Bit) 1 else 0\n case EQ => if (a.to32Bit == b.to32Bit) 1 else 0\n case NEQ => if (a.to32Bit != b.to32Bit) 1 else 0\n", "right_context": " case GTEU => if (a.to32Bit >= b.to32Bit) 1 else 0\n case _ => 0 // Never happens\n }\n\n def testDut(\n i: BigInt,\n j: BigInt,\n out: BigInt,\n op: Type,\n dut: ALU,\n ) = {\n // print(s\"Inputs: $i $op $j \| Test result should be ${aluHelper(i, j, op)} \| \")\n dut.io.inst.poke(op)\n dut.io.a.poke(i.to32Bit)\n dut.io.b.poke(j.to32Bit)\n dut.clock.step()\n dut.io.x.peekInt() should be(out)\n }\n def testCycle(\n op: Type\n ) =\n test(new ALU) { c =>\n cases.foreach { i =>\n cases.foreach { j =>\n testDut(i, j, aluHelper(i, j, op).to32Bit, op, c)\n }\n }\n }\n\n def toUInt(\n i: BigInt\n ) = i.to32Bit.asUInt(32.W)\n}\n", "groundtruth": " case GTE => if (a.toInt >= b.toInt) 1 else 0\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/test/src/CPUDemoAppsSpec.scala", "left_context": "package chiselv\n\nimport chiseltest._\nimport chiseltest.experimental._\nimport org.scalatest._\n\nimport flatspec._\nimport matchers._\n\n// Extend the SOC module to add the observer for sub-module signals\nclass SOCWrapperDemo(\n cpuFrequency: Int,\n bitWidth: Int,\n instructionMemorySize: Int,\n memorySize: Int,\n memoryFile: String,\n ramFile: String,\n numGPIO: Int,\n // baudRate: Int,\n ) extends SOC(\n cpuFrequency,\n entryPoint = 0,\n bitWidth,\n instructionMemorySize,\n memorySize,\n memoryFile,\n ramFile,\n numGPIO,\n ) {\n val registers = expose(core.registerBank.regs)\n val pc = expose(core.PC.pc)\n}\n\nclass CPUDemoAppsSpec extends AnyFlatSpec with ChiselScalatestTester with should.Matchers {\n val cpuFrequency = 10000\n val bitWidth = 32\n val instructionMemorySize = 64 * 1024\n val memorySize = 64 * 1024\n\n def defaultDut(\n memoryfile: String,\n ramFile: String = \"\",\n ) =\n test(\n new SOCWrapperDemo(\n cpuFrequency,\n bitWidth,\n instructionMemorySize,\n memorySize,\n memoryfile,\n ramFile,\n 8,\n // 1200,\n )\n )\n .withAnnotations(\n Seq(\n WriteVcdAnnotation,\n VerilatorBackendAnnotation,\n )\n )\n\n behavior of \"GPIODemo\"\n it should \"lit a LED connected to GPIO from gcc program\" in {\n val filename = \"./gcc/simpleLED/main.mem\"\n defaultDut(filename) { c =>\n c.clock.setTimeout(10000)\n c.clock.step(1) // Step from initial PC\n while (c.pc.peekInt() != 0x0)\n c.clock.step(1)\n }\n }\n\n it should \"blink LED connected to GPIO0 from gcc program\" in {\n val filename = \"./gcc/blinkLED/main-rom.mem\"\n", "right_context": " it should \"print to UART0 from gcc program\" in {\n val filename = \"./gcc/helloUART/main-rom.mem\"\n val filename_ram = \"./gcc/helloUART/main-ram.mem\"\n defaultDut(filename, filename_ram) { c =>\n c.clock.setTimeout(30000)\n c.clock.step(25000)\n // while (c.pc.peekInt() != 0x90) { // 0x90 is the address of _halt\n // c.clock.step(1)\n // }\n }\n }\n}\n", "groundtruth": " defaultDut(filename) { c =>\n c.clock.setTimeout(3000)\n c.clock.step(2000)\n }\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/test/src/CPUSingleCycleAppsSpec.scala", "left_context": "package chiselv\n\nimport chiseltest._\nimport chiseltest.experimental._\nimport org.scalatest._\n\nimport flatspec._\nimport matchers._\n\n// Extend the Control module to add the observer for sub-module signals\nclass CPUSingleCycleWrapperApps(memoryFile: String) extends SOC(\n cpuFrequency = 25000000,\n entryPoint = 0,\n bitWidth = 32,\n instructionMemorySize = 1 * 1024,\n dataMemorySize = 1 * 1024,\n memoryFile = memoryFile,\n numGPIO = 0,\n ) {\n val registers = expose(core.registerBank.regs)\n val pc = expose(core.PC.pc)\n val memWriteAddr = expose(core.memoryIOManager.io.MemoryIOPort.writeAddr)\n val memWriteData = expose(core.memoryIOManager.io.MemoryIOPort.writeData)\n val memReadAddr = expose(core.memoryIOManager.io.MemoryIOPort.readAddr)\n val memReadData = expose(core.memoryIOManager.io.MemoryIOPort.readData)\n}\n\nclass CPUSingleCycleAppsSpec extends AnyFlatSpec with ChiselScalatestTester with should.Matchers {\n val writeLatency = 2\n val readLatency = 1\n\n def defaultDut(memoryfile: String) =\n test(new CPUSingleCycleWrapperApps(memoryFile = memoryfile))\n .withAnnotations(\n Seq(\n WriteVcdAnnotation\n )\n )\n\n it should \"load instructions from file to write to all registers with ADDI\" in {\n val filename = \"./gcc/test/test_addi.mem\"\n defaultDut(filename) { c =>\n c.clock.setTimeout(0)\n val results = List.fill(8)(List(0, 1000, 3000, 2000)).flatten\n for ((i, r) <- 0 until 31 zip results) {\n c.registers(i).peekInt() should be(r)\n c.clock.step(1)\n }\n c.clock.step(20)\n }\n }\n\n it should \"load program and end with 25 (0x19) in mem address 100 (0x64)\" in {\n val filename = \"./gcc/test/test_book.mem\"\n defaultDut(filename) { c =>\n c.clock.setTimeout(0)\n c.clock.step(1) // addi\n c.registers(2).peekInt() should be(5)\n c.clock.step(1) // addi\n c.registers(3).peekInt() should be(12)\n c.clock.step(1) // addi\n c.registers(7).peekInt() should be(3)\n c.clock.step(1) // lui\n c.registers(6).peekInt() should be(0x80000000L)\n c.clock.step(1) // or\n c.registers(4).peekInt() should be(7)\n c.clock.step(1) // and\n c.registers(5).peekInt() should be(4)\n c.clock.step(1) // add\n c.registers(5).peekInt() should be(11)\n c.clock.step(1) // beq (skip)\n c.clock.step(1) // slt\n c.registers(4).peekInt() should be(0)\n c.clock.step(1) // beq (skip next addi)\n c.clock.step(1) // slt\n c.registers(4).peekInt() should be(1)\n c.clock.step(1) // add\n c.registers(7).peekInt() should be(12)\n c.clock.step(1) // sub\n c.registers(7).peekInt() should be(7)\n // Check Memory write at address 0x80000000\n c.memWriteAddr.peekInt() should be(0x80000000L)\n c.memWriteData.peekInt() should be(7)\n", "right_context": " c.memReadData.peekInt() should be(7)\n c.clock.step(1 + readLatency) // lw\n c.registers(2).peekInt() should be(7)\n c.clock.step(1) // add\n c.registers(9).peekInt() should be(18)\n c.clock.step(1) // jal (skip next addi)\n c.clock.step(1) // add\n c.registers(2).peekInt() should be(25)\n // // Check Memory address 0x80000000 + 100 (0x64)\n c.memWriteAddr.peekInt() should be(0x80000000L + 0x64)\n c.memWriteData.peekInt() should be(25)\n c.clock.step(1 + writeLatency) // sw\n\n // Add some padding at the end\n c.clock.step(10)\n }\n }\n\n it should \"loop thru ascii table writing to 0x3000_0000 region\" in {\n val filename = \"./gcc/test/test_ascii.mem\"\n defaultDut(filename) { c =>\n c.clock.setTimeout(0)\n c.clock.step(1)\n c.registers(1).peekInt() should be(40)\n c.clock.step(1)\n c.registers(2).peekInt() should be(33)\n c.clock.step(1)\n c.registers(3).peekInt() should be(126)\n c.clock.step(1)\n c.registers(4).peekInt() should be(0x3000_0000)\n\n for (i <- 33 until 127) {\n // Check memory write at address 0x30000000\n c.memWriteAddr.peekInt() should be(0x30000000L)\n c.memWriteData.peekInt() should be(i)\n c.clock.step(1) // sb (no latency to write 0x30000000 region)\n c.clock.step(1) // addi\n c.clock.step(1) // bge\n }\n c.clock.step(10)\n }\n }\n}\n", "groundtruth": " c.clock.step(1 + writeLatency) // sw\n // Check Memory read at address 0x80000000\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/test/src/CPUSingleCycleIOSpec.scala", "left_context": "package chiselv\n\nimport chiseltest._\nimport chiseltest.experimental._\nimport com.carlosedp.riscvassembler.RISCVAssembler\nimport org.scalatest._\n\nimport flatspec._\nimport matchers._\n\n// Extend the Control module to add the observer for sub-module signals\nclass CPUSingleCycleIOWrapper(memoryFile: String) extends SOC(\n cpuFrequency = 25000000,\n entryPoint = 0,\n bitWidth = 32,\n instructionMemorySize = 1 * 1024,\n dataMemorySize = 1 * 1024,\n memoryFile = memoryFile,\n numGPIO = 8,\n ) {\n val registers = expose(core.registerBank.regs)\n val pc = expose(core.PC.pc)\n val memWriteAddr = expose(core.memoryIOManager.io.MemoryIOPort.writeAddr)\n val memWriteData = expose(core.memoryIOManager.io.MemoryIOPort.writeData)\n val memReadAddr = expose(core.memoryIOManager.io.MemoryIOPort.readAddr)\n val memReadData = expose(core.memoryIOManager.io.MemoryIOPort.readData)\n\n val GPIO0_value = expose(core.GPIO0.GPIO)\n val GPIO0_direction = expose(core.GPIO0.direction)\n val timerCounter = expose(core.timer0.counter)\n}\n\nclass CPUSingleCycleIOSpec\n extends AnyFlatSpec\n with ChiselScalatestTester\n with BeforeAndAfterEach\n with BeforeAndAfterAll\n with should.Matchers {\n val cpuFrequency = 25000000\n val ms = cpuFrequency / 1000\n var memoryfile: os.Path = _\n val tmpdir = os.pwd / \"tmphex\"\n\n override def beforeAll(): Unit =\n os.makeDir.all(tmpdir)\n override def afterAll(): Unit =\n scala.util.Try(os.remove(tmpdir))\n override def beforeEach(): Unit =\n memoryfile = tmpdir / (scala.util.Random.alphanumeric.filter(_.isLetter).take(15).mkString + \".hex\")\n override def afterEach(): Unit =\n os.remove.all(memoryfile)\n\n def defaultDut(prog: String) = {\n val hex = RISCVAssembler.fromString(prog)\n os.write(memoryfile, hex)\n test(new CPUSingleCycleIOWrapper(memoryFile = memoryfile.toString))\n .withAnnotations(\n Seq(\n WriteVcdAnnotation,\n VerilatorBackendAnnotation, // GPIO needs Verilator backend\n )\n )\n }\n\n it should \"write to GPIO0\" in {\n val prog = \"\"\"\n lui x1, 0x30001\n addi x5, x0, -1\n addi x3, x3, 1\n addi x4, x0, 7\n sw x5, 0(x1)\n add x2, x2, x3\n sw x2, 4(x1)\n jal x0, -8\n \"\"\"\n defaultDut(prog) { c =>\n c.clock.setTimeout(0)\n c.registers(1).peekInt() should be(0)\n c.registers(2).peekInt() should be(0)\n c.registers(3).peekInt() should be(0)\n c.registers(4).peekInt() should be(0)\n c.clock.step(1) // lui\n c.registers(1).peekInt() should be(0x30001000L)\n c.clock.step(1) // addi\n c.registers(5).peekInt() should be(0xffffffffL)\n c.clock.step(1) // addi\n c.registers(3).peekInt() should be(1)\n c.clock.step(1) // addi\n c.registers(4).peekInt() should be(7)\n // Check memory address 0x30001000L for direction (GPIO0)\n c.memWriteAddr.peekInt() should be(0x30001000L)\n c.memWriteData.peekInt() should be(0xffffffffL)\n c.clock.step(1) // sw\n c.clock.step(1) // add\n c.GPIO0_direction.peekInt() should be(0xffffffffL)\n c.registers(2).peekInt() should be(1)\n c.memWriteAddr.peekInt() should be(0x30001004L)\n c.memWriteData.peekInt() should be(1)\n c.clock.step(1) // sw\n c.GPIO0_value.peekInt() should be(1)\n c.clock.step(1) // jal\n c.clock.step(1) // add\n c.registers(2).peekInt() should be(2)\n c.memWriteAddr.peekInt() should be(0x30001004L)\n c.memWriteData.peekInt() should be(2)\n c.clock.step(1) // sw\n c.GPIO0_value.peekInt() should be(2)\n }\n }\n\n behavior of \"Timer\"\n it should \"read timer and wait for 2 ms\" in {\n val prog = \"\"\"\n main: lui x1, 0x30003\n addi x2, x0, 2\n wait: lw x3, 0(x1)\n bne x2, x3, -4\n cont: addi x4, x0, 1\n \"\"\"\n defaultDut(prog) { c =>\n c.clock.setTimeout(0)\n c.registers(1).peekInt() should be(0)\n c.registers(2).peekInt() should be(0)\n c.registers(3).peekInt() should be(0)\n c.timerCounter.peekInt() should be(0)\n c.clock.step(1) // lui\n c.registers(1).peekInt() should be(0x30003000L)\n c.clock.step(1) // addi\n c.registers(2).peekInt() should be(2)\n // Check read from memory address 0x30003000L\n c.memReadAddr.peekInt() should be(0x30003000L)\n c.memReadData.peekInt() should be(0)\n c.clock.step(1) // lw\n", "right_context": "\n it should \"reset timer after 1ms and wait for 1 ms\" in {\n val prog = \"\"\"\n main: lui x1, 0x30003\n addi x2, x0, 1\n wait: lw x3, 0(x1)\n bne x2, x3, -4\n cont: sw x0, 0(x1)\n wait2: lw x3, 0(x1)\n bne x2, x3, -4\n cont2: addi x3, x0, 2\n \"\"\"\n defaultDut(prog) { c =>\n c.clock.setTimeout(0)\n c.registers(1).peekInt() should be(0)\n c.registers(2).peekInt() should be(0)\n c.registers(3).peekInt() should be(0)\n c.timerCounter.peekInt() should be(0)\n c.clock.step(1) // lui\n c.registers(1).peekInt() should be(0x30003000L)\n c.clock.step(1) // addi\n c.registers(2).peekInt() should be(1)\n // Check read from memory address 0x30003000L\n c.memReadAddr.peekInt() should be(0x30003000L)\n c.memReadData.peekInt() should be(0)\n c.registers(3).peekInt() should be(0)\n c.clock.step(ms) // wait 1ms\n c.timerCounter.peekInt() should be(1)\n c.registers(3).peekInt() should be(1)\n c.clock.step(1)\n c.clock.step(1)\n c.clock.step(1) // sw\n // Check write to memory address 0x30003000L (reset)\n c.memWriteAddr.peekInt() should be(0x30003000L)\n c.memWriteData.peekInt() should be(0)\n c.timerCounter.peekInt() should be(0)\n c.registers(3).peekInt() should be(0)\n c.clock.step(ms) // wait 1ms\n c.timerCounter.peekInt() should be(1)\n c.clock.step(1) // lw\n c.clock.step(1) // bne\n c.clock.step(1) // addi\n c.registers(3).peekInt() should be(2)\n }\n }\n}\n", "groundtruth": " c.registers(3).peekInt() should be(0)\n c.clock.step(1) // bne\n c.clock.step(2 * ms) // wait 2ms\n c.timerCounter.peekInt() should be(2)\n c.registers(3).peekInt() should be(2)\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/test/src/CPUSingleCycleInstructionSpec.scala", "left_context": "package chiselv\n\nimport chiseltest._\nimport chiseltest.experimental._\nimport com.carlosedp.riscvassembler.RISCVAssembler\nimport org.scalatest._\n\nimport flatspec._\nimport matchers._\n\n// Extend the Control module to add the observer for sub-module signals\nclass CPUSingleCycleInstWrapper(memoryFile: String) extends SOC(\n cpuFrequency = 25000000,\n entryPoint = 0,\n bitWidth = 32,\n instructionMemorySize = 1 * 1024,\n dataMemorySize = 1 * 1024,\n memoryFile = memoryFile,\n numGPIO = 0,\n ) {\n val registers = expose(core.registerBank.regs)\n val pc = expose(core.PC.pc)\n val memWriteAddr = expose(core.memoryIOManager.io.MemoryIOPort.writeAddr)\n val memWriteData = expose(core.memoryIOManager.io.MemoryIOPort.writeData)\n val memReadAddr = expose(core.memoryIOManager.io.MemoryIOPort.readAddr)\n val memReadData = expose(core.memoryIOManager.io.MemoryIOPort.readData)\n}\n\nclass CPUSingleCycleInstructionSpec\n extends AnyFlatSpec\n with ChiselScalatestTester\n with BeforeAndAfterEach\n with BeforeAndAfterAll\n with should.Matchers {\n val memReadLatency = 1\n val memWriteLatency = 1\n var memoryfile: os.Path = _\n val tmpdir = os.pwd / \"tmphex\"\n\n override def beforeAll(): Unit =\n os.makeDir.all(tmpdir)\n override def afterAll(): Unit =\n scala.util.Try(os.remove(tmpdir))\n override def beforeEach(): Unit =\n memoryfile = tmpdir / (scala.util.Random.alphanumeric.filter(_.isLetter).take(15).mkString + \".hex\")\n override def afterEach(): Unit =\n os.remove.all(memoryfile)\n\n def defaultDut(prog: String) = {\n // Generate the hex file from asm source\n val hex = RISCVAssembler.fromString(prog)\n os.write(memoryfile, hex)\n test(new CPUSingleCycleInstWrapper(memoryfile.relativeTo(os.pwd).toString))\n .withAnnotations(\n Seq(\n WriteVcdAnnotation\n )\n )\n }\n\n it should \"validate ADD/ADDI instructions\" in {\n val prog = \"\"\"\n addi x1, x1, 1\n addi x2, x2, 1\n add x3, x1, x2\n \"\"\"\n defaultDut(prog) { c =>\n c.clock.setTimeout(0)\n c.registers(1).peekInt() should be(0)\n c.registers(2).peekInt() should be(0)\n c.registers(3).peekInt() should be(0)\n c.clock.step(1)\n c.registers(1).peekInt() should be(1)\n c.clock.step(1)\n c.registers(2).peekInt() should be(1)\n c.clock.step(1)\n c.registers(3).peekInt() should be(2)\n }\n }\n\n it should \"validate Branch instructions\" in {\n val prog = \"\"\"\n addi x1, x0, 4\n addi x2, x0, 4\n addi x3, x0, 2\n beq x1, x2, +8\n jal x0, 0\n bne x2, x3, +8\n jal x0, 0\n blt x3, x2, +8\n jal x0, 0\n bge x2, x3, +8\n jal x0, 0\n \"\"\"\n defaultDut(prog) { c =>\n c.clock.setTimeout(0)\n c.registers(1).peekInt() should be(0x0)\n c.registers(2).peekInt() should be(0x0)\n c.registers(3).peekInt() should be(0x0)\n c.clock.step(1)\n c.registers(1).peekInt() should be(4)\n c.clock.step(1)\n c.registers(2).peekInt() should be(4)\n c.clock.step(1)\n c.registers(3).peekInt() should be(2)\n c.pc.peekInt() should be(0x0c)\n c.clock.step(1)\n c.pc.peekInt() should be(0x14)\n c.clock.step(1)\n c.pc.peekInt() should be(0x1c)\n c.clock.step(1)\n c.pc.peekInt() should be(0x24)\n c.clock.step(1)\n c.pc.peekInt() should be(0x2c)\n }\n }\n\n it should \"validate JAL/JALR instructions\" in {\n val prog = \"\"\"\n", "right_context": " c.pc.peekInt() should be(8)\n c.registers(1).peekInt() should be(4)\n c.clock.step(1) // jalr\n c.pc.peekInt() should be(2048)\n c.registers(2).peekInt() should be(0xc)\n }\n }\n\n it should \"validate LUI instruction\" in {\n val prog = \"\"\"\n lui x2, 0xc0000\n \"\"\"\n defaultDut(prog) { c =>\n c.clock.setTimeout(0)\n c.registers(2).peekInt() should be(0x00000000L)\n c.clock.step(1)\n c.registers(2).peekInt() should be(0xc0000000L)\n }\n }\n\n it should \"validate AUIPC instruction\" in {\n val prog = \"\"\"\n auipc x2, 4096\n auipc x3, 4096\n \"\"\"\n defaultDut(prog) { c =>\n c.clock.setTimeout(0)\n c.registers(2).peekInt() should be(0x00000000L)\n c.clock.step(1)\n c.registers(2).peekInt() should be(0x01000000L)\n c.clock.step(1)\n c.registers(3).peekInt() should be(0x01000004L)\n }\n }\n\n it should \"validate SW instruction\" in {\n val prog = \"\"\"\n lui x1, 0x80000\n addi x1, x1, 20\n addi x2, x0, 291\n sw x2, 0(x1)\n lw x3, 0(x1)\n \"\"\"\n defaultDut(prog) { c =>\n c.registers(1).peekInt() should be(0)\n c.clock.step(1) // lui\n c.registers(1).peekInt() should be(0x80000000L)\n c.clock.step(1) // addi\n c.registers(1).peekInt() should be(0x80000014L)\n c.clock.step(1) // addi\n c.registers(2).peekInt() should be(0x123)\n // Check memory address 0x14 with offset\n c.memWriteAddr.peekInt() should be(0x80000000L + 0x14)\n c.memWriteData.peekInt() should be(0x123)\n c.clock.step(1 + memWriteLatency) // sw\n // Check memory address 0x14 with offset\n c.memReadAddr.peekInt() should be(0x80000000L + 0x14)\n c.memReadData.peekInt() should be(0x123)\n c.clock.step(2 + memReadLatency) // lw\n c.registers(3).peekInt() should be(0x123)\n }\n }\n\n it should \"validate SH instruction\" in {\n val prog = \"\"\"\n lui x1, 0x80000\n lui x2, 0x12345\n addi x2, x2, 1656\n addi x3, x3, -1\n sw x3, 48(x1) // Memory offset 48 (0x30) should be 0xffffffff\n sh x2, 52(x1) // Memory offset 52 (0x34) should be 0x00005678\n sh x2, 48(x1) // Memory offset 48 (0x30) should be 0xffff5678\n sh x2, 54(x1) // Memory offset 52 (0x34) should be 0x56785678\n lw x4, 48(x1) // x4 should be 0xffff5678\n lw x5, 52(x1) // x5 should be 0x56785678\n \"\"\"\n defaultDut(prog) { c =>\n c.registers(1).peekInt() should be(0)\n c.clock.step(1) // lui\n c.registers(1).peekInt() should be(0x80000000L)\n c.clock.step(1) // lui\n c.registers(2).peekInt() should be(0x12345000L)\n c.clock.step(1) // addi\n c.registers(2).peekInt() should be(0x12345678L)\n c.clock.step(1) // addi\n c.registers(3).peekInt() should be(0xffffffffL)\n // Check memory address offset 0x30\n c.memWriteAddr.peekInt() should be(0x80000000L + 0x30)\n c.memWriteData.peekInt() should be(0xffffffffL)\n c.clock.step(1 + memWriteLatency) // sw\n // Check memory address offset 0x34\n c.memWriteAddr.peekInt() should be(0x80000000L + 0x34)\n c.memWriteData.peekInt() should be(0x5678L)\n c.clock.step(1 + memWriteLatency) // sh\n // Check memory address 0x30\n c.memWriteAddr.peekInt() should be(0x80000000L + 0x30)\n c.memWriteData.peekInt() should be(0x5678L)\n c.clock.step(1 + memWriteLatency) // sh\n // Check memory address offset 0x34\n c.memWriteAddr.peekInt() should be(0x80000000L + 0x36)\n c.memWriteData.peekInt() should be(0x5678L)\n c.clock.step(1 + memWriteLatency) // sh\n // Check memory address 0x30\n c.clock.step(1) // lw - stall\n c.memReadAddr.peekInt() should be(0x80000000L + 0x30)\n c.memReadData.peekInt() should be(0xffff5678L)\n c.clock.step(1) // lw\n c.clock.step(1) // lw - stall\n c.registers(4).peekInt() should be(0xffff5678L)\n // Check memory address 0x34\n c.memReadAddr.peekInt() should be(0x80000000L + 0x34)\n c.memReadData.peekInt() should be(0x56785678L)\n c.clock.step(1) // lw\n c.registers(5).peekInt() should be(0x56785678L)\n c.clock.step(10) // padding\n }\n }\n\n it should \"validate SB instruction\" in {\n val prog = \"\"\"\n lui x1, 0x80000\n lui x2, 0x12345\n addi x2, x2, 1656\n addi x3, x3, -1\n sw x3, 48(x1) // Memory offset 48 (0x30) should be 0xffffffff\n sb x2, 52(x1) // Memory offset 52 (0x34) should be 0x00000078\n sb x2, 48(x1) // Memory offset 48 (0x30) should be 0xffffff78\n sb x2, 54(x1) // Memory offset 52 (0x34) should be 0x00780078\n sb x2, 51(x1) // Memory offset 51 (0x33) should be 0x78ffff78\n lw x4, 48(x1) // x4 should be 0x78ffff78\n lw x5, 52(x1) // x5 should be 0x00780078\n \"\"\"\n defaultDut(prog) { c =>\n c.registers(1).peekInt() should be(0)\n c.clock.step(1) // lui\n c.registers(1).peekInt() should be(0x80000000L)\n c.clock.step(1) // lui\n c.registers(2).peekInt() should be(0x12345000L)\n c.clock.step(1) // addi\n c.registers(2).peekInt() should be(0x12345678L)\n c.clock.step(1) // addi\n c.registers(3).peekInt() should be(0xffffffffL)\n // Check memory address offset 0x30\n c.memWriteAddr.peekInt() should be(0x80000000L + 0x30)\n c.memWriteData.peekInt() should be(0xffffffffL)\n c.clock.step(1 + memWriteLatency) // sw\n // Check memory address offset 0x34\n c.memWriteAddr.peekInt() should be(0x80000000L + 0x34)\n c.memWriteData.peekInt() should be(0x78L)\n c.clock.step(1 + memWriteLatency) // sb\n // Check memory address 0x30\n c.memWriteAddr.peekInt() should be(0x80000000L + 0x30)\n c.memWriteData.peekInt() should be(0x78L)\n c.clock.step(1 + memWriteLatency) // sb\n // Check memory address offset 0x34\n c.memWriteAddr.peekInt() should be(0x80000000L + 0x36)\n c.memWriteData.peekInt() should be(0x78L)\n c.clock.step(1 + memWriteLatency) // sb\n // Check memory address offset 0x33\n c.memWriteAddr.peekInt() should be(0x80000000L + 0x33)\n c.memWriteData.peekInt() should be(0x78L)\n c.clock.step(1 + memWriteLatency) // sb\n // Check memory address 0x30\n c.memReadAddr.peekInt() should be(0x80000000L + 0x30)\n c.clock.step(1) // lw\n c.memReadData.peekInt() should be(0x78ffff78L)\n c.clock.step(1) // lw\n c.registers(4).peekInt() should be(0x78ffff78L)\n // Check memory address 0x34\n c.memReadAddr.peekInt() should be(0x80000000L + 0x34)\n c.clock.step(1) // lw\n c.memReadData.peekInt() should be(0x00780078L)\n c.clock.step(1) // lw\n c.registers(5).peekInt() should be(0x00780078L)\n c.clock.step(10) // padding\n }\n }\n\n it should \"validate LW instruction\" in {\n val prog = \"\"\"\n lui x1, 0xf0f0f\n addi x1, x1, 240\n lui x2, 0x80000\n sw x1, 0(x2)\n lw x3, 0(x2)\n \"\"\"\n defaultDut(prog) { c =>\n c.registers(1).peekInt() should be(0)\n c.clock.step(1) // lui\n c.registers(1).peekInt() should be(0xf0f0f000L)\n c.clock.step(1) // addi\n c.registers(1).peekInt() should be(0xf0f0f0f0L)\n c.clock.step(1) // lui\n c.registers(2).peekInt() should be(0x80000000L)\n // Check memory write at address 0x80000000L\n c.memWriteAddr.peekInt() should be(0x80000000L)\n c.memWriteData.peekInt() should be(0xf0f0f0f0L)\n c.clock.step(1 + memWriteLatency) // sw\n // Check memory read at address 0x20 (32)\n c.memReadAddr.peekInt() should be(0x80000000L)\n c.memReadData.peekInt() should be(0xf0f0f0f0L)\n c.clock.step(1 + memReadLatency) // lw\n // Check loaded data\n c.registers(3).peekInt() should be(0xf0f0f0f0L)\n c.clock.step(5) // Paddding\n }\n }\n\n it should \"validate LH instruction\" in {\n val prog = \"\"\"\n lui x1, 0xffff1\n addi x1, x1, 564\n lui x2, 0x80000\n sw x1, 0(x2)\n lh x3, 0(x2)\n lh x4, 2(x2)\n \"\"\"\n defaultDut(prog) { c =>\n c.registers(1).peekInt() should be(0)\n c.clock.step(1)\n c.registers(1).peekInt() should be(0xffff1000L)\n c.clock.step(1)\n c.registers(1).peekInt() should be(0xffff1234L)\n c.clock.step(1)\n c.registers(2).peekInt() should be(0x80000000L)\n // Check memory write at address 0x80000000L\n c.memWriteAddr.peekInt() should be(0x80000000L)\n c.memWriteData.peekInt() should be(0xffff1234L)\n c.clock.step(1 + memWriteLatency) // sw\n // Check memory read at address 0x80000000L\n c.memReadAddr.peekInt() should be(0x80000000L)\n c.memReadData.peekInt() should be(0x00001234L)\n c.clock.step(1 + memReadLatency) // lh\n // Check loaded data\n c.registers(3).peekInt() should be(0x00001234L)\n // Check memory read at address 0x80000002L\n c.memReadAddr.peekInt() should be(0x80000000L + 0x2)\n c.memReadData.peekInt() should be(0x0000ffffL)\n c.clock.step(1 + memReadLatency) // lh\n c.registers(4).peekInt() should be(0xffffffffL)\n c.clock.step(5) // Paddding\n }\n }\n\n it should \"validate LHU instruction\" in {\n val prog = \"\"\"\n lui x1, 0xffff1\n addi x1, x1, 564\n lui x2, 0x80000\n sw x1, 0(x2)\n lhu x3, 0(x2)\n lhu x4, 2(x2)\n \"\"\"\n defaultDut(prog) { c =>\n c.registers(1).peekInt() should be(0)\n c.clock.step(1)\n c.registers(1).peekInt() should be(0xffff1000L)\n c.clock.step(1)\n c.registers(1).peekInt() should be(0xffff1234L)\n c.clock.step(1)\n c.registers(2).peekInt() should be(0x80000000L)\n // Check memory write at address 0x80000000L\n c.memWriteAddr.peekInt() should be(0x80000000L)\n c.memWriteData.peekInt() should be(0xffff1234L)\n c.clock.step(1 + memWriteLatency) // sw\n // Check memory read at address 0x80000000L\n c.memReadAddr.peekInt() should be(0x80000000L)\n c.memReadData.peekInt() should be(0x00001234L)\n c.clock.step(1 + memReadLatency) // lh\n // Check loaded data\n c.registers(3).peekInt() should be(0x00001234L)\n // Check memory read at address 0x80000002L\n c.memReadAddr.peekInt() should be(0x80000000L + 0x2)\n c.memReadData.peekInt() should be(0x0000ffffL)\n c.clock.step(1 + memReadLatency) // lh\n c.registers(4).peekInt() should be(0x0000ffffL)\n c.clock.step(5) // Paddding\n }\n }\n\n it should \"validate LB instruction\" in {\n val prog = \"\"\"\n lui x1, 0xabcde\n addi x1, x1, 0x123\n lui x2, 0x80000\n sw x1, 0(x2)\n lb x3, 0(x2)\n lb x4, 1(x2)\n lb x5, 2(x2)\n lb x6, 3(x2)\n \"\"\"\n defaultDut(prog) { c =>\n c.registers(1).peekInt() should be(0)\n c.clock.step(1)\n c.registers(1).peekInt() should be(0xabcde000L)\n c.clock.step(1)\n c.registers(1).peekInt() should be(0xabcde123L)\n c.clock.step(1)\n c.registers(2).peekInt() should be(0x80000000L)\n // Check memory write at address 0x80000000L\n c.memWriteAddr.peekInt() should be(0x80000000L)\n c.memWriteData.peekInt() should be(0xabcde123L)\n c.clock.step(1 + memWriteLatency) // sw\n // Check memory read at address 0x80000000L\n c.memReadAddr.peekInt() should be(0x80000000L)\n c.memReadData.peekInt() should be(0x23L)\n c.clock.step(1 + memReadLatency) // lb (offset 0)\n c.registers(3).peekInt() should be(0x00000023L)\n // Check memory read at address 0x80000001L\n c.memReadAddr.peekInt() should be(0x80000001L)\n c.memReadData.peekInt() should be(0xe1L)\n c.clock.step(1 + memReadLatency) // lb (offset 1)\n c.registers(4).peekInt() should be(0xffffffe1L)\n // Check memory read at address 0x80000002L\n c.memReadAddr.peekInt() should be(0x80000002L)\n c.memReadData.peekInt() should be(0xcdL)\n c.clock.step(1 + memReadLatency) // lb (offset 2)\n c.registers(5).peekInt() should be(0xffffffcdL)\n // Check memory read at address 0x80000003L\n c.memReadAddr.peekInt() should be(0x80000003L)\n c.memReadData.peekInt() should be(0xabL)\n c.clock.step(1 + memReadLatency) // lb (offset 3)\n c.registers(6).peekInt() should be(0xffffffabL)\n // Check loaded data\n c.clock.step(5) // Paddding\n }\n }\n\n it should \"validate LBU instruction\" in {\n val prog = \"\"\"\n lui x1, 0xabcde\n addi x1, x1, 0x123\n lui x2, 0x80000\n sw x1, 0(x2)\n lbu x3, 0(x2)\n lbu x4, 1(x2)\n lbu x5, 2(x2)\n lbu x6, 3(x2)\n \"\"\"\n defaultDut(prog) { c =>\n c.registers(1).peekInt() should be(0)\n c.clock.step(1)\n c.registers(1).peekInt() should be(0xabcde000L)\n c.clock.step(1)\n c.registers(1).peekInt() should be(0xabcde123L)\n c.clock.step(1)\n c.registers(2).peekInt() should be(0x80000000L)\n // Check memory write at address 0x80000000L\n c.memWriteAddr.peekInt() should be(0x80000000L)\n c.memWriteData.peekInt() should be(0xabcde123L)\n c.clock.step(1 + memWriteLatency) // sw\n // Check memory read at address 0x80000000L\n c.memReadAddr.peekInt() should be(0x80000000L)\n c.memReadData.peekInt() should be(0x23L)\n c.clock.step(1 + memReadLatency) // lb (offset 0)\n c.registers(3).peekInt() should be(0x00000023L)\n // Check memory read at address 0x80000001L\n c.memReadAddr.peekInt() should be(0x80000001L)\n c.memReadData.peekInt() should be(0xe1L)\n c.clock.step(1 + memReadLatency) // lb (offset 1)\n c.registers(4).peekInt() should be(0x000000e1L)\n // Check memory read at address 0x80000002L\n c.memReadAddr.peekInt() should be(0x80000002L)\n c.memReadData.peekInt() should be(0xcdL)\n c.clock.step(1 + memReadLatency) // lb (offset 2)\n c.registers(5).peekInt() should be(0x000000cdL)\n // Check memory read at address 0x80000003L\n c.memReadAddr.peekInt() should be(0x80000003L)\n c.memReadData.peekInt() should be(0xabL)\n c.clock.step(1 + memReadLatency) // lb (offset 3)\n c.registers(6).peekInt() should be(0x000000abL)\n // Check loaded data\n c.clock.step(5) // Paddding\n }\n }\n}\n", "groundtruth": " jal x1, +8\n nop\n jalr x2, x1, +2044\n \"\"\"\n defaultDut(prog) { c =>\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/test/src/DecoderSpec.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chiseltest._\nimport com.carlosedp.riscvassembler.RISCVAssembler\nimport org.scalatest._\n\nimport Instruction._\nimport flatspec._\nimport matchers._\n\nclass DecoderSpec extends AnyFlatSpec with ChiselScalatestTester with should.Matchers {\n behavior of \"Decoder - Aritmetic\"\n\n it should \"Decode an ADD instruction (type R)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"add x1, x2, x3\"))\n c.clock.step()\n validateResult(c, ADD, 1, 2, 3, 0, true, false)\n }\n }\n it should \"Decode an ADDI instruction (type I)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"addi x1, x2, 5\"))\n c.clock.step()\n validateResult(c, ADDI, 1, 2, 0, 5, true, false, true)\n }\n }\n it should \"Decode an SUB instruction (type R)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"sub x1, x2, x3\"))\n c.clock.step()\n validateResult(c, SUB, 1, 2, 3, 0, true, false)\n }\n }\n it should \"Decode an LUI instruction (type U)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"lui x23, 0x12345\"))\n c.clock.step()\n validateResult(c, LUI, 23, 0, 0, 305418240, false, false, true)\n }\n }\n it should \"Decode an AUIPC instruction (type U)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"auipc x23, 0x12345\"))\n c.clock.step()\n validateResult(c, AUIPC, 23, 0, 0, 305418240, false, false, true)\n }\n }\n\n behavior of \"Decoder - Shifts\"\n\n it should \"Decode an SLL instruction (type R)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"sll x1, x2, x3\"))\n c.clock.step()\n validateResult(c, SLL, 1, 2, 3, 0, true, false)\n }\n }\n it should \"Decode an SLLI instruction (type I)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"slli x1, x2, 5\"))\n c.clock.step()\n validateResult(c, SLLI, 1, 2, 0, 5, true, false, true)\n }\n }\n it should \"Decode an SRL instruction (type R)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"srl x1, x2, x3\"))\n c.clock.step()\n validateResult(c, SRL, 1, 2, 3, 0, true, false)\n }\n }\n it should \"Decode an SRLI instruction (type I)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"srli x1, x2, 5\"))\n c.clock.step()\n validateResult(c, SRLI, 1, 2, 0, 5, true, false, true)\n }\n }\n it should \"Decode an SRA instruction (type R)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"sra x1, x2, x3\"))\n c.clock.step()\n validateResult(c, SRA, 1, 2, 3, 0, true, false)\n }\n }\n it should \"Decode an SRAI instruction (type I)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"srai x1, x2, 1\"))\n c.clock.step()\n validateResult(c, SRAI, 1, 2, 0, 1025, true, false, true)\n }\n }\n\n behavior of \"Decoder - Logical\"\n\n it should \"Decode an AND instruction (type R)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"and x1, x2, x3\"))\n c.clock.step()\n validateResult(c, AND, 1, 2, 3, 0, true, false)\n }\n }\n it should \"Decode an ANDI instruction (type I)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"andi x7, x24, -1\"))\n c.clock.step()\n validateResult(c, ANDI, 7, 24, 0, -1, true, false, true)\n }\n }\n it should \"Decode an OR instruction (type R)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"or x1, x2, x3\"))\n c.clock.step()\n validateResult(c, OR, 1, 2, 3, 0, true, false)\n }\n }\n it should \"Decode an ORI instruction (type I)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"ori x7, x24, -1\"))\n c.clock.step()\n validateResult(c, ORI, 7, 24, 0, -1, true, false, true)\n }\n }\n it should \"Decode an XOR instruction (type R)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"xor x1, x2, x3\"))\n c.clock.step()\n validateResult(c, XOR, 1, 2, 3, 0, true, false)\n }\n }\n it should \"Decode an XORI instruction (type I)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"xori x7, x24, -1\"))\n c.clock.step()\n validateResult(c, XORI, 7, 24, 0, -1, true, false, true)\n }\n }\n\n behavior of \"Decoder - Compare\"\n\n it should \"Decode an SLT instruction (type R)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"slt x1, x2, x3\"))\n c.clock.step()\n validateResult(c, SLT, 1, 2, 3, 0, true, false)\n }\n }\n it should \"Decode an SLTI instruction (type I)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"slti x7, x24, -1\"))\n c.clock.step()\n validateResult(c, SLTI, 7, 24, 0, -1, true, false, true)\n }\n }\n it should \"Decode an SLTU instruction (type R)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"sltu x1, x2, x3\"))\n c.clock.step()\n validateResult(c, SLTU, 1, 2, 3, 0, true, false)\n }\n }\n it should \"Decode an SLTIU instruction (type I)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"sltiu x7, x24, -1\"))\n c.clock.step()\n validateResult(c, SLTIU, 7, 24, 0, -1, true, false, true)\n }\n }\n\n behavior of \"Decoder - Branches\"\n\n it should \"Decode an BEQ instruction (type B)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"beq x21, x10, -1366\"))\n c.clock.step()\n validateResult(c, BEQ, 0, 21, 10, -1366, false, true, true)\n }\n }\n it should \"Decode an BNE instruction (type B)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"bne x21, x10, -1366\"))\n c.clock.step()\n validateResult(c, BNE, 0, 21, 10, -1366, false, true, true)\n }\n }\n it should \"Decode an BLT instruction (type B)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"blt x21, x10, -1366\"))\n c.clock.step()\n validateResult(c, BLT, 0, 21, 10, -1366, false, true, true)\n }\n }\n it should \"Decode an BGE instruction (type B)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"bge x21, x10, -1366\"))\n c.clock.step()\n validateResult(c, BGE, 0, 21, 10, -1366, false, true, true)\n }\n }\n it should \"Decode an BLTU instruction (type B)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"bltu x21, x10, -1366\"))\n c.clock.step()\n validateResult(c, BLTU, 0, 21, 10, -1366, false, true, true)\n }\n }\n it should \"Decode an BGEU instruction (type B)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"bgeu x21, x10, -1366\"))\n c.clock.step()\n validateResult(c, BGEU, 0, 21, 10, -1366, false, true, true)\n }\n }\n\n behavior of \"Decoder - Jumps\"\n\n it should \"Decode an JAL instruction (type J)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"jal x21, -699052\"))\n c.clock.step()\n validateResult(c, JAL, 21, 0, 0, -699052, false, false, true, true)\n }\n }\n it should \"Decode an JALR instruction (type I)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"jalr x21, x1, 1234\"))\n c.clock.step()\n validateResult(c, JALR, 21, 1, 0, 1234, false, false, true, true)\n }\n }\n\n behavior of \"Decoder - Loads/Stores\"\n\n it should \"Decode an LB instruction (type I)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"lb x1, 16(x2)\"))\n c.clock.step()\n validateResult(c, LB, 1, 2, 0, 16, false, false, true, false, true, false)\n }\n }\n it should \"Decode an LH instruction (type I)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"lh x1, 16(x2)\"))\n c.clock.step()\n validateResult(c, LH, 1, 2, 0, 16, false, false, true, false, true, false)\n }\n }\n it should \"Decode an LBU instruction (type I)\" in {\n", "right_context": " }\n it should \"Decode an LHU instruction (type I)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"lhu x1, 16(x2)\"))\n c.clock.step()\n validateResult(c, LHU, 1, 2, 0, 16, false, false, true, false, true, false)\n }\n }\n it should \"Decode an LW instruction (type I)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"lw x1, 16(x2)\"))\n c.clock.step()\n validateResult(c, LW, 1, 2, 0, 16, false, false, true, false, true, false)\n }\n }\n it should \"Decode an SB instruction (type S)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"sb x10, -81(x21)\"))\n c.clock.step()\n validateResult(c, SB, 0, 21, 10, -81, false, false, true, false, false, true)\n }\n }\n it should \"Decode an SH instruction (type S)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"sh x10, -81(x21)\"))\n c.clock.step()\n validateResult(c, SH, 0, 21, 10, -81, false, false, true, false, false, true)\n }\n }\n it should \"Decode an SW instruction (type S)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"sw x10, -81(x21)\"))\n c.clock.step()\n validateResult(c, SW, 0, 21, 10, -81, false, false, true, false, false, true)\n }\n }\n\n // --------------------- Test Helpers ---------------------\n\n def makeBin(\n in: String\n ): UInt = {\n val bin = RISCVAssembler.binOutput(in)\n (\"b\" + bin).U\n }\n\n def validateResult(\n c: Decoder,\n inst: Instruction.Type,\n rd: Int,\n rs1: Int,\n rs2: Int,\n imm: Int,\n toALU: Boolean = false,\n branch: Boolean = false,\n use_imm: Boolean = false,\n jump: Boolean = false,\n load: Boolean = false,\n store: Boolean = false,\n ) = {\n c.io.inst.expect(inst)\n c.io.rd.peekInt() should be(rd)\n c.io.rs1.peekInt() should be(rs1)\n c.io.rs2.peekInt() should be(rs2)\n c.io.imm.peekInt() should be(imm)\n c.io.toALU.peekBoolean() should be(toALU)\n c.io.branch.peekBoolean() should be(branch)\n c.io.use_imm.peekBoolean() should be(use_imm)\n c.io.jump.peekBoolean() should be(jump)\n c.io.is_load.peekBoolean() should be(load)\n c.io.is_store.peekBoolean() should be(store)\n }\n}\n", "groundtruth": " test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"lbu x1, 16(x2)\"))\n c.clock.step()\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/test/src/GPIOSpec.scala", "left_context": "package chiselv\n\nimport chiseltest._\nimport chiseltest.experimental.expose\nimport com.carlosedp.riscvassembler.ObjectUtils._\nimport org.scalatest._\n\nimport flatspec._\nimport matchers._\n\nclass GPIOWrapper(bitWidth: Int = 32, numGPIO: Int = 8) extends GPIO(bitWidth, numGPIO) {\n val obs_GPIO = expose(GPIO)\n val obs_DIRECTION = expose(direction)\n}\nclass GPIOSpec extends AnyFlatSpec with ChiselScalatestTester with should.Matchers {\n def defaultDut =\n test(new GPIOWrapper(32, 8)).withAnnotations(\n Seq(\n WriteVcdAnnotation,\n VerilatorBackendAnnotation,\n )\n", "right_context": " c.obs_GPIO.peekInt() should be(0)\n c.obs_DIRECTION.peekInt() should be(0)\n }\n }\n\n it should \"write direction then read\" in {\n defaultDut { c =>\n c.io.GPIOPort.writeDirection.poke(true)\n c.io.GPIOPort.dataIn.poke(\"10101010\".b)\n c.clock.step()\n c.obs_DIRECTION.peekInt() should be(\"10101010\".b)\n c.io.GPIOPort.directionOut.peekInt() should be(\"10101010\".b)\n }\n }\n\n it should \"write IO data then read\" in {\n defaultDut { c =>\n c.io.GPIOPort.writeValue.poke(true)\n c.io.GPIOPort.dataIn.poke(\"11111111\".b)\n c.clock.step()\n c.obs_GPIO.peekInt() should be(\"11111111\".b)\n c.io.GPIOPort.writeDirection.poke(true)\n c.io.GPIOPort.dataIn.poke(\"01010101\".b)\n c.clock.step()\n c.io.GPIOPort.valueOut.peekInt() should be(\"01010101\".b)\n c.clock.step(5)\n }\n }\n\n // Doesn't work since we can't poke the analog port\n //\n // it should \"read IO data from input\" in {\n // defaultDut(){ c =>\n // c.io.GPIOPort.dataOut.peekInt() should be(0)\n // c.io.GPIOPort.dir.poke(0.U) // Read input\n // // c.InOut.io.dataIO.poke(1.U) // Write to input pin\n // c.clock.step()\n // c.io.GPIOPort.dataOut.peekInt() should be(1)\n // }\n // }\n\n}\n", "groundtruth": " )\n\n it should \"read GPIO output and direction as 0 when initialized\" in {\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/test/src/MemorySpec.scala", "left_context": "package chiselv\n\nimport chiseltest._\nimport org.scalatest._\n\nimport flatspec._\nimport matchers._\n\nclass MemorySpec extends AnyFlatSpec with ChiselScalatestTester with should.Matchers {\n\n it should \"write and read from address\" in {\n test(new DualPortRAM(32, 1 * 1024)).withAnnotations(\n Seq(\n WriteVcdAnnotation\n )\n ) { c =>\n c.io.writeEnable.poke(true)\n c.io.writeAddress.poke(1)\n c.io.writeData.poke(1234)\n c.clock.step(1)\n c.io.readAddress.poke(1)\n c.clock.step(2)\n c.io.readData.peekInt() should be(1234)\n }\n }\n it should \"not allow write to address\" in {\n test(new DualPortRAM(32, 1 * 1024)) { c =>\n c.io.writeAddress.poke(0x00000010)\n c.io.readAddress.poke(0x00000010)\n c.clock.step()\n c.io.writeData.poke(1234)\n c.clock.step()\n c.io.readData.peekInt() should be(0)\n }\n }\n\n it should \"write data and follow with a read in same address\" in {\n test(new DualPortRAM(32, 64 * 1024)) { c =>\n val addressOffset = 0x0000100L\n val addresses = Seq(0x0L, 0x0010L, 0x0d00L, 0x1000L, 0x2000L, 0x8000L, 0xe000L)\n val values = Seq(0, 1, 0x0000_cafeL, 0xbaad_cafeL, 0xffff_ffffL)\n", "right_context": " c.io.readData.peekInt() should be(value)\n }\n }\n c.clock.step(10)\n }\n }\n\n behavior of \"InstructionMemory\"\n it should \"load from file and read multiple instructions\" in {\n val filename = \"MemorySpecTestFile.hex\"\n // Create memory test file with 32bit address space\n val file = os.pwd / \"MemorySpecTestFile.hex\"\n os.remove(file)\n os.write(file, \"00010203\\r\\n08090A0B\\r\\nDEADBEEF\\r\\n07060504\\r\\n\")\n test(new InstructionMemory(32, 16 * 1024, filename)).withAnnotations(Seq(WriteVcdAnnotation)) { c =>\n c.io.readAddr.poke(0)\n c.clock.step()\n c.io.readData.peekInt() should be(0x00010203L)\n c.io.readAddr.poke(4)\n c.clock.step()\n c.io.readData.peekInt() should be(0x08090a0bL)\n c.io.readAddr.poke(8)\n c.clock.step()\n c.io.readData.peekInt() should be(0xdeadbeefL)\n c.io.readAddr.poke(12)\n c.clock.step()\n c.clock.step()\n c.io.readData.peekInt() should be(0x07060504L)\n c.io.readAddr.poke(1)\n c.clock.step()\n }\n os.remove.all(file)\n }\n}\n", "groundtruth": " addresses.foreach { address =>\n values.foreach { value =>\n c.io.writeEnable.poke(true)\n c.io.writeAddress.poke(addressOffset + address)\n c.io.readAddress.poke(addressOffset + address)\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/test/src/ProgramCounterSpec.scala", "left_context": "package chiselv\n\nimport chiseltest._\nimport org.scalatest._\n\nimport flatspec._\nimport matchers._\n\nclass ProgramCounterSpec extends AnyFlatSpec with ChiselScalatestTester with should.Matchers {\n\n it should \"initialize to 0\" in {\n test(new ProgramCounter) { c =>\n c.io.PC.peekInt() should be(0)\n }\n }\n it should \"initialize to 0x00400000\" in {\n test(new ProgramCounter(entryPoint = 0x00400000)) { c =>\n c.io.PC.peekInt() should be(0x00400000L)\n }\n }\n it should \"walk 4 bytes\" in {\n test(new ProgramCounter) { c =>\n c.io.PC.peekInt() should be(0)\n c.io.PC4.peekInt() should be(4)\n", "right_context": " c.io.writeEnable.poke(true)\n c.io.dataIn.poke(c.io.PC4.peek())\n<TARGET>\n c.io.PC.peekInt() should be(4)\n }\n }\n it should \"jump to 0xbaddcafe (write)\" in {\n test(new ProgramCounter) { c =>\n c.io.writeEnable.poke(true)\n c.io.dataIn.poke(0xbaddcafeL)\n c.clock.step()\n c.io.PC.peekInt() should be(0xbaddcafeL)\n }\n }\n it should \"add 32 to PC ending up in 40\" in {\n test(new ProgramCounter) { c =>\n c.io.writeEnable.poke(true)\n c.io.dataIn.poke(8)\n c.clock.step()\n c.io.PC.peekInt() should be(8)\n c.io.writeAdd.poke(true)\n c.io.dataIn.poke(32)\n c.clock.step()\n c.io.PC.peekInt() should be(40)\n }\n }\n}\n", "groundtruth": " c.clock.step()\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/test/src/RegisterBankSpec.scala", "left_context": "package chiselv\n\nimport scala.util.Random\nimport chisel3._\nimport chiseltest._\nimport org.scalatest._\n\nimport flatspec._\nimport matchers._\n\nclass RegisterBankSpec extends AnyFlatSpec with ChiselScalatestTester with should.Matchers {\n\n it should \"have x0 equal to 0\" in {\n", "right_context": " c.io.writeEnable.poke(true)\n c.io.regwr_addr.poke(0.U)\n c.io.regwr_data.poke(123.U)\n c.clock.step()\n c.io.rs1_addr.peekInt() should be(0)\n }\n }\n it should \"not write if not enabled\" in {\n test(new RegisterBank) { c =>\n c.io.rs1_addr.poke(1)\n c.io.regwr_addr.poke(1)\n c.io.regwr_data.poke(123.U)\n c.clock.step()\n c.io.rs1.expect(0.U)\n }\n }\n it should \"write all other registers and read values as expected\" in {\n test(new RegisterBank).withAnnotations(Seq(WriteVcdAnnotation)) { c =>\n val one = BigInt(1)\n val max = (one << 32) - one\n val cases = Array[BigInt](1, 2, 4, 123, 0, 0x7fffffffL, max) ++ Seq.fill(10)(\n BigInt(Random.nextLong(max.toLong))\n )\n Random.shuffle(1 to 31).foreach { i =>\n cases.foreach { v =>\n c.io.writeEnable.poke(true)\n c.clock.step()\n c.io.regwr_addr.poke(i)\n c.io.regwr_data.poke(v.U)\n c.io.rs2_addr.poke(i)\n c.clock.step()\n c.io.writeEnable.poke(false)\n c.clock.step()\n c.io.rs2.expect(v)\n }\n }\n c.clock.step(10)\n }\n }\n}\n", "groundtruth": " test(new RegisterBank) { c =>\n c.io.rs1_addr.poke(0.U)\n c.io.rs1.expect(0.U)\n }\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/test/src/SysconSpec.scala", "left_context": "package chiselv\n\nimport chiseltest._\nimport org.scalatest._\n\nimport flatspec._\nimport matchers._\n\nclass SysconSpec extends AnyFlatSpec with ChiselScalatestTester with should.Matchers {\n\n def defaultDut =\n test(new Syscon(32, 50000000, 8, 0L, 64 * 1024, 64 * 1024)).withAnnotations(\n Seq(\n WriteVcdAnnotation\n )\n )\n\n it should \"read dummy value from Syscon 0x0\" in {\n defaultDut { c =>\n c.io.Address.poke(0x00)\n c.clock.step()\n c.io.DataOut.peekInt() should be(0xbaad_cafeL)\n }\n }\n it should \"read clock speed from Syscon\" in {\n defaultDut { c =>\n c.io.Address.poke(0x08)\n c.clock.step()\n c.io.DataOut.peekInt() should be(50000000)\n }\n }\n it should \"check if UART0 is available in Syscon\" in {\n defaultDut { c =>\n c.io.Address.poke(0x10)\n<TARGET>\n it should \"check if GPIO0 is available in Syscon\" in {\n defaultDut { c =>\n c.io.Address.poke(0x18)\n", "right_context": " it should \"check num of GPIO0s in Syscon\" in {\n defaultDut { c =>\n c.io.Address.poke(0x28)\n c.clock.step()\n c.io.DataOut.peekInt() should be(8)\n }\n }\n it should \"check if Timer0 is available in Syscon\" in {\n defaultDut { c =>\n c.io.Address.poke(0x24)\n c.clock.step()\n c.io.DataOut.peekInt() should be(1)\n }\n }\n it should \"check RAM size in Syscon\" in {\n defaultDut { c =>\n c.io.Address.poke(0x34)\n c.clock.step()\n c.io.DataOut.peekInt() should be(64 * 1024)\n }\n }\n}\n", "groundtruth": " c.clock.step()\n c.io.DataOut.peekInt() should be(1)\n }\n }\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/test/src/TimerSpec.scala", "left_context": "package chiselv\n\nimport chiseltest._\nimport chiseltest.experimental._\nimport org.scalatest._\nimport chiselv.Timer\n\nimport flatspec._\nimport matchers._\n\nclass TimerWrapper(bitWidth: Int = 32, cpuFrequency: Int) extends Timer(bitWidth, cpuFrequency) {\n val obs_counter = expose(counter)\n}\nclass TimerSpec extends AnyFlatSpec with ChiselScalatestTester with should.Matchers {\n\n val cpuFrequency = 25000000\n def defaultDut =\n test(new TimerWrapper(32, cpuFrequency)).withAnnotations(\n Seq(\n // WriteVcdAnnotation\n )\n )\n\n val ms = cpuFrequency / 1000\n it should \"read timer after 1ms\" in {\n defaultDut { c =>\n c.clock.setTimeout(0)\n", "right_context": " it should \"reset timer after 3ms and continue counting\" in {\n defaultDut { c =>\n c.clock.setTimeout(0)\n c.clock.step(3 * ms)\n c.obs_counter.peekInt() should be(3)\n c.io.dataOut.peekInt() should be(3)\n c.io.writeEnable.poke(true)\n c.io.dataIn.poke(0)\n c.clock.step()\n c.io.writeEnable.poke(false)\n c.obs_counter.peekInt() should be(0)\n c.obs_counter.peekInt() should be(0)\n c.clock.step(ms)\n c.io.dataOut.peekInt() should be(1)\n c.obs_counter.peekInt() should be(1)\n }\n }\n}\n", "groundtruth": " c.io.dataOut.peekInt() should be(0)\n c.obs_counter.peekInt() should be(0)\n c.clock.step(ms)\n c.io.dataOut.peekInt() should be(1)\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/test/src/UartSpec.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chiseltest._\nimport org.scalatest._\n\nimport flatspec._\nimport matchers._\n\n/\n This file has been provided by Anton Blanchard's Chiselwatt repository at:\n * https://github.com/antonblanchard/chiselwatt\n /\n\nclass UartSpec extends AnyFlatSpec with ChiselScalatestTester with should.Matchers {\n val rxOverclock = 16\n val fpgaClock = 15000000\n val baudRate = 115200\n val divider = Math.round(1.0f fpgaClock / (baudRate * rxOverclock) - 1)\n\n", "right_context": "\n private def rxOne(u: Uart, c: UInt) = {\n /* Start bit /\n u.io.serialPort.rx.poke(0.U)\n clockSerial(u.clock)\n\n /\n * This doesn't work:\n * c.pad(8).asBools.foreach({cc =>\n /\n c.asBools.foreach { cc =>\n u.io.serialPort.rx.poke(cc)\n clockSerial(u.clock)\n }\n\n / Have to do this instead: /\n u.io.serialPort.rx.poke(0.U)\n clockSerial(u.clock)\n\n / Stop bit */\n u.io.serialPort.rx.poke(1.U)\n clockSerial(u.clock)\n }\n\n it should \"pass a unit test\" in {\n test(new Uart(64, rxOverclock)).withAnnotations(Seq(WriteVcdAnnotation)) { u =>\n u.clock.setTimeout(10000)\n\n u.io.dataPort.clockDivisor.valid.poke(true.B)\n u.io.dataPort.clockDivisor.bits.poke(divider.U)\n\n u.io.dataPort.rxQueue.ready.poke(false.B)\n\n val testChars = Seq(\"h41\".U, \"h6E\".U, \"h74\".U, \"h6F\".U, \"h6E\".U)\n\n testChars.foreach(c => rxOne(u, c))\n\n u.io.dataPort.rxQueue.ready.poke(true.B)\n testChars.foreach { c =>\n u.io.dataPort.rxQueue.valid.expect(true.B)\n u.io.dataPort.rxQueue.bits.expect(c)\n u.clock.step()\n }\n u.io.dataPort.rxQueue.ready.poke(false.B)\n\n u.io.dataPort.rxFull.expect(false.B)\n u.io.dataPort.txFull.expect(false.B)\n\n rxOne(u, \"h5a\".U)\n u.io.dataPort.rxFull.expect(false.B)\n (0 to 64).foreach(_ => rxOne(u, \"h5a\".U))\n u.io.dataPort.rxFull.expect(true.B)\n\n u.io.dataPort.txQueue.bits.poke(\"h75\".U)\n u.io.dataPort.txQueue.valid.poke(true.B)\n u.clock.step()\n u.io.dataPort.txFull.expect(false.B)\n (0 to 64).foreach(_ => u.clock.step())\n u.io.dataPort.txFull.expect(true.B)\n }\n }\n}\n", "groundtruth": " def clockSerial(clk: Clock) = clk.step(fpgaClock / baudRate)\n", "crossfile_context": ""}

	{"task_id": "CGRAs", "path": "CGRAs/src/main/scala/Alu.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ****************************************/\nimport chisel3._\n\nobject operations\n{\n def SUM = 0.U // Summation \n def MUL = 1.U // Multiplication\n def SUB = 2.U // Subtraction\n def SLL = 3.U // Shift Left Logical\n def SRA = 4.U // Shift Right Arithmetic\n def SRL = 5.U // Shift Right Logical\n", "right_context": " def OR = 7.U // Or\n def XOR = 8.U // Xor \n def DIV = 9.U // Div (NOT IMPLEMENTED)\n def MIN = 10.U // Minimum (NOT IMPLEMENTED)\n def MAX = 11.U // Maximum (NOT IMPLEMENTED)\n}\n \nimport operations._\n \nclass Alu \n (\n dataWidth: Int, \n opWidth: Int\n )\n extends Module {\n val io = IO(new Bundle {\n val din1 = Input(SInt(dataWidth.W))\n val din2 = Input(SInt(dataWidth.W))\n val dout = Output(SInt(dataWidth.W))\n val opConfig = Input(UInt(opWidth.W))\n })\n // Result \n val outAux = Wire(SInt((dataWidth).W))\n\n when (io.opConfig === SUM) { // SUM\n outAux := io.din1 + io.din2 \n }\n .elsewhen (io.opConfig === MUL) { // MUL\n outAux := io.din1 io.din2 \n } \n .elsewhen (io.opConfig === SUB) { // SUB\n outAux := io.din1 - io.din2 \n }\n .elsewhen (io.opConfig === SLL) { // SLL\n outAux := io.din1 << (io.din2(18, 0)).asUInt\n } \n .elsewhen (io.opConfig === SRA) { // SRA\n outAux := io.din1 >> io.din2.asUInt\n } \n .elsewhen (io.opConfig === SRL) { // SRL\n outAux := (io.din1.asUInt >> io.din2.asUInt).asSInt \n }\n .elsewhen (io.opConfig === AND) { // AND\n outAux := io.din1 & io.din2 \n } \n .elsewhen (io.opConfig === OR) { // OR\n outAux := io.din1 \| io.din2 \n } \n .elsewhen (io.opConfig === XOR) { // XOR\n outAux := io.din1 ^ io.din2 \n } \n .otherwise { \n outAux := 0.S // Default \n }\n \n io.dout := outAux\n}\n\n// Generate the Verilog code\nobject AluMain extends App {\n println(\"Generating the hardware\")\n (new chisel3.stage.ChiselStage).emitVerilog(new Alu(32, 5), Array(\"--target-dir\", \"generated\"))\n}", "groundtruth": " def AND = 6.U // And \n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/main/scala/CellProcessing.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n *****************************************/\nimport chisel3._\nimport chisel3.util._\n\nclass CellProcessing \n (\n dataWidth: Int\n ) \n extends Module {\n val io = IO(new Bundle {\n val northDin = Input(SInt(dataWidth.W))\n val northDinValid = Input(Bool())\n val eastDin = Input(SInt(dataWidth.W))\n val eastDinValid = Input(Bool())\n val southDin = Input(SInt(dataWidth.W))\n val southDinValid = Input(Bool())\n val westDin = Input(SInt(dataWidth.W))\n val westDinValid = Input(Bool())\n val fuDin1Ready = Output(Bool()) \n val fuDin2Ready = Output(Bool()) \n val dout = Output(SInt(dataWidth.W))\n val doutValid = Output(Bool()) \n val northDoutReady = Input(Bool())\n val eastDoutReady = Input(Bool())\n val southDoutReady = Input(Bool())\n val westDoutReady = Input(Bool())\n val configBits = Input(UInt(182.W))\n })\n // Config signals\n val selectorMux1 = Wire(UInt(3.W))\n val selectorMux2 = Wire(UInt(3.W))\n val forkReceiverMask1 = Wire(UInt(4.W))\n val forkReceiverMask2 = Wire(UInt(4.W))\n val opConfig = Wire(UInt(5.W))\n val forkSenderMask = Wire(UInt(5.W))\n val I1CONST = Wire(UInt(dataWidth.W))\n val initialVaueLoad = Wire(UInt(dataWidth.W))\n val iterationsResetLoad = Wire(UInt(16.W))\n val fifoLengthLoad = Wire(UInt(16.W))\n val loadInitialValue = Wire(UInt(2.W))\n val fuDout = Wire(SInt(dataWidth.W))\n val ebDin1 = Wire(SInt(dataWidth.W))\n val ebDin2 = Wire(SInt(dataWidth.W))\n val joinDin1 = Wire(SInt(dataWidth.W))\n val joindin2 = Wire(SInt(dataWidth.W))\n val joinDout1 = Wire(SInt(dataWidth.W))\n val joinDout2 = Wire(SInt(dataWidth.W))\n val fuDoutValid = Wire(Bool())\n val fuDoutReady = Wire(Bool())\n val ebDin1Valid = Wire(Bool())\n val ebDin2Valid = Wire(Bool())\n val joinDin1Valid = Wire(Bool())\n val joinDin1Ready = Wire(Bool())\n val joinDin2Valid = Wire(Bool())\n val joinDin2Ready = Wire(Bool())\n val joinDoutValid = Wire(Bool())\n val joinDoutReady = Wire(Bool())\n val forkedDoutReady = Wire(Bool())\n\n // Configuration bits arrangement\n selectorMux1 := io.configBits(2, 0) \n selectorMux2 := io.configBits(5, 3)\n forkReceiverMask1 := io.configBits(17, 14)\n // 2 fill bits (19 , 18)\n forkReceiverMask2 := io.configBits(23, 20)\n // structure conf\n opConfig := io.configBits(48, 44)\n // 3 fill bits (50 , 48)\n forkSenderMask := io.configBits(56, 52)\n // structure conf\n I1CONST := io.configBits(115, 84)\n initialVaueLoad := io.configBits(147, 116) \n fifoLengthLoad := io.configBits(163, 148)\n iterationsResetLoad := io.configBits(179, 164)\n loadInitialValue := io.configBits(181, 180)\n\n val fr1 = Module (new Fr(6, 4))\n val readyfr1 = Cat(io.northDoutReady, io.eastDoutReady, io.southDoutReady, io.westDoutReady) \n val validInfr1 = Cat(fuDoutValid.asUInt, \"b1\".U, io.westDinValid, io.southDinValid, io.eastDinValid, io.northDinValid) \n fr1.io.readyOut := readyfr1\n fr1.io.validIn := validInfr1\n fr1.io.validMuxSel := selectorMux1\n fr1.io.forkMask := forkReceiverMask1 \n ebDin1Valid := fr1.io.validOut \n\n val mux1 = Module (new ConfMux(6, dataWidth))\n mux1.io.selector := selectorMux1\n mux1.io.muxInput := (Cat(fuDout, I1CONST, io.westDin, io.southDin, io.eastDin, io.northDin)).asSInt\n ebDin1 := mux1.io.muxOutput\n\n val eb1 = Module (new DEb(dataWidth))\n eb1.io.din := ebDin1\n eb1.io.dinValid := ebDin1Valid\n io.fuDin1Ready := eb1.io.dinReady \n joinDin1 := eb1.io.dout \n joinDin1Valid := eb1.io.doutValid \n eb1.io.doutReady := joinDin1Ready\n\n val fr2 = Module (new Fr(6, 4))\n val ready_fr2 = Cat(io.northDoutReady, io.eastDoutReady, io.southDoutReady, io.westDoutReady) \n val validIn_fr2 = Cat(fuDoutValid.asUInt, \"b1\".U, io.westDinValid, io.southDinValid, io.eastDinValid, io.northDinValid) \n fr2.io.readyOut := ready_fr2\n fr2.io.validIn := validIn_fr2\n fr2.io.validMuxSel := selectorMux2\n fr2.io.forkMask := forkReceiverMask2 \n ebDin2Valid := fr2.io.validOut \n\n val mux2 = Module (new ConfMux(6, dataWidth))\n mux2.io.selector := selectorMux2\n mux2.io.muxInput := (Cat(fuDout, I1CONST, io.westDin, io.southDin, io.eastDin, io.northDin)).asSInt \n ebDin2 := mux2.io.muxOutput\n\n val eb2 = Module (new DEb(dataWidth))\n eb2.io.din := ebDin2\n eb2.io.dinValid := ebDin2Valid\n io.fuDin2Ready := eb2.io.dinReady \n joindin2 := eb2.io.dout \n", "right_context": " eb2.io.doutReady := joinDin2Ready \n\n val joinInst = Module (new Join(dataWidth))\n joinInst.io.din1 := joinDin1\n joinInst.io.din2 := joindin2 \n joinInst.io.doutReady := joinDoutReady\n joinInst.io.din1Valid := joinDin1Valid\n joinInst.io.din2Valid := joinDin2Valid\n\n joinDoutValid := joinInst.io.doutValid \n joinDin1Ready := joinInst.io.din1Ready \n joinDin2Ready := joinInst.io.din2Ready \n joinDout1 := joinInst.io.dout1\n joinDout2 := joinInst.io.dout2\n\n val fuInst = Module (new Fu(dataWidth, 5))\n fuInst.io.din1 := joinDout1\n fuInst.io.din2 := joinDout2\n fuInst.io.dinValid := joinDoutValid\n joinDoutReady := fuInst.io.dinReady \n fuInst.io.loopSource := loadInitialValue\n fuInst.io.iterationsReset := iterationsResetLoad \n fuInst.io.opConfig := opConfig \n fuDout := fuInst.io.dout \n fuDoutValid := fuInst.io.doutValid\n \n fuInst.io.doutReady := fuDoutReady\n\n val ebOut = Module (new DEb(dataWidth))\n ebOut.io.din := fuDout\n ebOut.io.dinValid := fuDoutValid\n ebOut.io.din := fuInst.io.dout \n ebOut.io.dinValid := fuInst.io.doutValid\n\n fuDoutReady := ebOut.io.dinReady\n io.dout := ebOut.io.dout \n io.doutValid := ebOut.io.doutValid \n ebOut.io.doutReady := forkedDoutReady\n\n val fs = Module (new Fs(5))\n val readyOutFs = Cat(\"b1\".U, io.northDoutReady, io.eastDoutReady, io.southDoutReady, io.westDoutReady) \n fs.io.readyOut := readyOutFs\n forkedDoutReady := fs.io.readyIn\n fs.io.forkMask := forkSenderMask\n}\n\n// Generate the Verilog code\nobject CellProcessingMain extends App {\n println(\"Generating the hardware\")\n (new chisel3.stage.ChiselStage).emitVerilog(new CellProcessing(32), Array(\"--target-dir\", \"generated\"))\n}", "groundtruth": " joinDin2Valid := eb2.io.doutValid\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/main/scala/ConfMux.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ***************************************/\n\n/\n * Multiplexer module that separates a series of input data based on the provided parameters.\n * numInput: The number of inputs to the multiplexer.\n * muxInput: The input data to be separated. Each input is assumed to be of equal size.\n * selector: The index to select the output from the separated input data.\n * muxOutput: The selected output based on the provided selector.\n * Example:\n * If `numInput` is 2 and each input data is 8 bits the multiplexer separates it \n * into 2 separate data, each containing 4 bits. If `selector` is 0, it returns the first 4 bits.\n */\n\nimport chisel3._\nimport chisel3.util._\n\nclass ConfMux \n (\n numInputs: Int = 2, \n dataWidth: Int = 1\n )\n extends Module {\n val io = IO(new Bundle { \n val selector = Input(UInt(log2Ceil(numInputs).W))\n val muxInput = Input(SInt((numInputsdataWidth).W))\n val muxOutput = Output(SInt(dataWidth.W))\n })\n \n val inputs = Wire(Vec(numInputs, SInt(dataWidth.W))) \n\n for (i <- 0 until numInputs) {\n inputs(i) := (io.muxInput((i+1)dataWidth-1,idataWidth)).asSInt\n }\n io.muxOutput := inputs(io.selector)\n}\n\n// Generate the Verilog code\n", "right_context": "", "groundtruth": "object ConfMuxMain extends App {\n println(\"Generating the hardware\")\n (new chisel3.stage.ChiselStage).emitVerilog(new ConfMux(2, 1), Array(\"--target-dir\", \"generated\"))\n}\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/main/scala/DEb.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ***************************************/\n\n/\n * The Elastic Buffer operates as a 2-slot FIFO, utilizing latches or flip-flops for implementation. \n * When EBs are adjacent, they synchronize data transfer (D) through a set of control signals: \n * a forward data-presence valid signal (V) indicating the presence of data or emptiness within the EB, \n * and a back-propagating stall/accept (A) signal, indicating if the EB is stalled or ready to receive new data. \n * A generalized EB extends this concept to an N-slot FIFO, typically realized through RAM implementation.\n **/\n\nimport chisel3._\nimport chisel3.util._\n\nclass DEb \n (\n dataWidth: Int\n )\n extends Module {\n val io = IO(new Bundle {\n val din = Input(SInt(dataWidth.W))\n val dinValid = Input(Bool())\n val dinReady = Output(Bool())\n val dout = Output(SInt(dataWidth.W))\n val doutValid = Output(Bool())\n val doutReady = Input(Bool()) \n })\n\n val regDin1 = RegInit(0.S(dataWidth.W))\n val regDin2 = RegInit(0.S(dataWidth.W))\n val regDinValid1 = RegInit(0.B)\n val regDinValid2 = RegInit(0.B)\n val regAreg = RegInit(0.B)\n\n when(regAreg) {\n regDin1 := io.din\n regDin2 := regDin1\n \n regDinValid1 := io.dinValid\n regDinValid2 := regDinValid1\n }\n\n regAreg := ~io.doutValid \| io.doutReady\n\n // Combinational assignments\n io.dinReady := regAreg\n\n when(regAreg) {\n", "right_context": " io.doutValid := regDinValid1\n }.otherwise {\n io.dout := regDin2\n io.doutValid := regDinValid2\n }\n}\n \n// Generate the Verilog code\nobject DEbMain extends App {\n println(\"Generating the hardware\")\n (new chisel3.stage.ChiselStage).emitVerilog(new DEb(32), Array(\"--target-dir\", \"generated\"))\n}\n", "groundtruth": " io.dout := regDin1\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/main/scala/DFifo.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n *****************************************/\nimport chisel3._\nimport chisel3.util._\nimport chisel3.stage.PrintFullStackTraceAnnotation\n\n", "right_context": " (\n dataWidth: Int, \n fifoDepth: Int\n ) \n extends Module {\n val io = IO(new Bundle {\n val din = Input(SInt(dataWidth.W)) \n val dinValid = Input(Bool())\n val doutReady = Input(Bool())\n val dinReady = Output(Bool())\n val dout = Output(SInt(dataWidth.W)) \n val doutValid = Output(Bool()) \n })\n\n val fifo = Module(new DFifoImp(dataWidth, fifoDepth))\n fifo.io.clock := clock\n fifo.io.reset := reset.asBool \n fifo.io.din := io.din \n fifo.io.dinValid := io.dinValid\n fifo.io.doutReady := io.doutReady\n io.dinReady := fifo.io.dinReady\n io.dout := fifo.io.dout \n io.doutValid := fifo.io.doutValid \n}\n\n// Generate the Verilog code\nobject DFifoMain extends App {\n println(\"Generating the hardware\")\n (new chisel3.stage.ChiselStage).emitVerilog(new DFifo(32, 32), Array(\"--target-dir\", \"generated\"))\n}", "groundtruth": "class DFifo\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/main/scala/DFifoImp.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n *****************************************/\nimport chisel3._\nimport chisel3.util._\nimport chisel3.util.HasBlackBoxResource\nimport chisel3.experimental.{IntParam, BaseModule}\n\nclass DFifoImp\n (\n dataWidth: Int, \n fifoDepth: Int\n ) \n", "right_context": " val reset = Input(Bool())\n val din = Input(SInt(dataWidth.W)) \n val dinValid = Input(Bool())\n val doutReady = Input(Bool())\n val dinReady = Output(Bool())\n val dout = Output(SInt(dataWidth.W)) \n val doutValid = Output(Bool()) \n })\n\n addResource(\"vsrc/DFifoImp.v\")\n}", "groundtruth": " extends BlackBox(Map(\"dataWidth\" -> dataWidth, \"fifoDepth\" -> fifoDepth)) with HasBlackBoxResource{ \n val io = IO(new Bundle {\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/main/scala/DReg.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n *****************************************/\nimport chisel3._\nimport chisel3.util._\n\nclass DReg\n (\n dataWidth: Int\n )\n extends Module {\n val io = IO(new Bundle {\n val din = Input(SInt(dataWidth.W))\n val dinValid = Input(Bool())\n val doutReady = Input(Bool())\n val dout = Output(SInt(dataWidth.W))\n val doutValid = Output(Bool())\n val dinReady = Output(Bool()) \n })\n\n val data = RegInit(0.S(dataWidth.W))\n val valid = RegInit(0.B)\n\n data := 0.S \n valid := false.B \n \n", "right_context": "}\n\n// Generate the Verilog code\nobject DRegMain extends App {\n println(\"Generating the hardware\")\n (new chisel3.stage.ChiselStage).emitVerilog(new DReg(8), Array(\"--target-dir\", \"generated\"))\n}", "groundtruth": " when (io.doutReady === true.B) {\n data := io.din\n valid := io.dinValid\n } \n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/main/scala/Fr.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n *****************************************/\nimport chisel3._\nimport chisel3.util._\n\n", "right_context": " (\n numberOfValids: Int, \n numberOfReadys: Int\n ) \n extends Module {\n val io = IO(new Bundle {\n val validIn = Input(UInt(numberOfValids.W))\n val readyOut = Input(UInt(numberOfReadys.W))\n val validMuxSel = Input(UInt((log2Ceil(numberOfValids).W)))\n val forkMask = Input(UInt(numberOfReadys.W))\n val validOut = Output(Bool()) \n })\n // All wires \n val aux = Wire(Vec(numberOfReadys+1, Bool()))\n val temp = Wire(Vec(numberOfReadys+1, Bool()))\n val vaux = Wire(SInt(1.W))\n\n for (i <- 0 until numberOfReadys) {\n aux(i) := ((~io.forkMask(i)) \| io.readyOut(i)).asBool\n }\n val confMux = Module (new ConfMux(numberOfValids, 1))\n confMux.io.selector := io.validMuxSel\n confMux.io.muxInput := (io.validIn).asSInt \n vaux := confMux.io.muxOutput\n\n aux(numberOfReadys) := vaux(0).asBool \n temp(0) := aux(0)\n\n for (i <- 1 until numberOfReadys+1) {\n temp(i) := temp(i-1) & aux(i)\n }\n io.validOut := temp(numberOfReadys) \n}\n\n// Generate the Verilog code\nobject FrMain extends App {\n println(\"Generating the hardware\")\n (new chisel3.stage.ChiselStage).emitVerilog(new Fr(5, 5), Array(\"--target-dir\", \"generated\"))\n}", "groundtruth": "class Fr \n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/main/scala/Fs.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ***************************************/\n\n/\n * The Fork Sender's responsibility is to verify the readiness of all potential destinations \n * for the input data. The AND gate in this block ensures that the valid signal is asserted only \n * when the Fork Sender confirms that all receivers are available.\n **/\n\nimport chisel3._\nimport chisel3.util._\n\nclass Fs \n (\n numberOfReadys: Int\n )\n extends Module {\n val io = IO(new Bundle {\n val readyOut = Input(UInt(numberOfReadys.W))\n val forkMask = Input(UInt(numberOfReadys.W))\n val readyIn = Output(Bool()) \n })\n \n val aux = Wire(Vec(numberOfReadys, Bool()))\n val temp = Wire(Vec(numberOfReadys, Bool()))\n\n for (i <- 0 until numberOfReadys) {\n aux(i) := ((~io.forkMask(i)) \| io.readyOut(i)).asBool\n }\n\n temp(0) := aux(0) \n\n for (i <- 1 until numberOfReadys) {\n temp(i) := temp(i-1) & aux(i)\n }\n io.readyIn := temp(numberOfReadys - 1).asBool \n}\n\n// Generate the Verilog code\n", "right_context": "", "groundtruth": "object FsMain extends App {\n println(\"Generating the hardware\")\n (new chisel3.stage.ChiselStage).emitVerilog(new Fs(5), Array(\"--target-dir\", \"generated\"))\n} \n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/main/scala/Fu.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ***************************************/\n\n/\n * An FU is a circuit that executes the operation of a data flow graph node. \n * The FU executes an operation only when its inputs are ready and when its output is free.\n **/\n\nimport chisel3._\nimport chisel3.util._\n\nobject states\n{\n", "right_context": " def STATE_1 = 1.U(2.W) // 01\n def STATE_2 = 2.U(2.W) // 10\n def STATE_3 = 3.U(2.W) // 11\n}\n\nimport states._\n\nclass Fu\n (\n dataWidth: Int, \n opWidth: Int\n )\n extends Module {\n val io = IO(new Bundle {\n val din1 = Input(SInt(dataWidth.W))\n val din2 = Input(SInt(dataWidth.W))\n val dinValid = Input(Bool())\n val doutReady = Input(Bool())\n val loopSource = Input(UInt(2.W))\n val iterationsReset = Input(UInt(16.W))\n val opConfig = Input(UInt(opWidth.W))\n val dinReady = Output(Bool())\n val dout = Output(SInt(dataWidth.W))\n val doutValid = Output(Bool()) \n })\n\n val aluDin1 = Wire(SInt(dataWidth.W))\n val aluDin2 = Wire(SInt(dataWidth.W))\n \n val aluDout = Wire(SInt(dataWidth.W))\n\n val doutReg = RegInit(0.S(dataWidth.W))\n val count = RegInit(0.U(16.W))\n val loaded = RegInit(0.U(1.W))\n\n //val valid = RegInit(0.U(1.W))\n val valid = Wire(Bool()) \n\n val alu = Module (new Alu(dataWidth, opWidth))\n alu.io.din1 := aluDin1\n alu.io.din2 := aluDin2\n aluDout := alu.io.dout \n alu.io.opConfig := io.opConfig\n \n when (io.loopSource === STATE_0) {\n aluDin1 := io.din1\n aluDin2 := io.din2 \n }\n .elsewhen (io.loopSource === STATE_1) {\n when (loaded === 0.U) {\n aluDin1 := io.din1\n aluDin2 := io.din2 \n } \n .otherwise {\n aluDin1 := doutReg\n aluDin2 := io.din2 \n } \n } \n .elsewhen (io.loopSource === STATE_2) {\n when (loaded === 0.U) {\n aluDin1 := io.din1\n aluDin2 := io.din2 \n } \n .otherwise {\n aluDin1 := io.din1\n aluDin2 := doutReg \n } \n } \n .otherwise { \n aluDin1 := (dataWidth - 1).S\n aluDin2 := (dataWidth - 1).S\n }\n \n when (io.doutReady === 1.U) {\n valid := 0.U \n }.otherwise{\n valid := 1.U \n }\n \n when (io.dinValid === 1.U && io.doutReady === 1.U && \n (io.loopSource === STATE_1 \|\| io.loopSource === STATE_2)) {\n loaded := 1.U\n count := count + 1.U \n }\n \n when (count === io.iterationsReset && \n (io.loopSource === STATE_1 \|\| io.loopSource === STATE_2) && \n io.doutReady === 1.U){\n count := 0.U\n loaded := 0.U\n valid := 1.U \n doutReg := aluDout\n } \n .elsewhen ((io.loopSource === STATE_1 \|\| io.loopSource === STATE_2) && \n io.dinValid === 1.U && io.doutReady === 1.U){\n doutReg := aluDout\n } \n\n io.dinReady := io.doutReady\n\n when (io.loopSource === STATE_0){\n io.dout := aluDout\n io.doutValid := io.dinValid \n }\n .otherwise{\n io.dout := doutReg\n io.doutValid := valid \n } \n}\n\n// Generate the Verilog code\nobject FuMain extends App {\n println(\"Generating the hardware\")\n (new chisel3.stage.ChiselStage).emitVerilog(new Fu(32, 5), Array(\"--target-dir\", \"generated\"))\n}\n", "groundtruth": " def STATE_0 = 0.U(2.W) // 00\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/main/scala/Join.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ***************************************/\n\n/\n * This block stops both din1 and din2 until they have data. \n * So din1 and din2 shouldn't signal a stop when they're empty. \n * If they do, it will hold up the movement of data in the earlier \n * pipeline stages and stop din1 and din2 from getting valid data \n * during the stalled state.\n **/\n\nimport chisel3._\nimport chisel3.util._\n\nclass Join \n (\n dataWidth: Int\n )\n extends Module {\n val io = IO(new Bundle {\n val din1 = Input(SInt(dataWidth.W))\n val din2 = Input(SInt(dataWidth.W))\n val doutReady = Input(Bool())\n val din1Valid = Input(Bool())\n val din2Valid = Input(Bool())\n val doutValid = Output(Bool())\n val din1Ready = Output(Bool())\n val din2Ready = Output(Bool())\n val dout1 = Output(SInt(dataWidth.W))\n val dout2 = Output(SInt(dataWidth.W))\n })\n\n io.dout1 := io.din1\n io.dout2 := io.din2 \n io.doutValid := io.din1Valid & io.din2Valid\n io.din1Ready := io.doutReady & io.din2Valid \n io.din2Ready := io.doutReady & io.din1Valid \n}\n\n// Generate the Verilog code\n", "right_context": "", "groundtruth": "object JoinMain extends App {\n println(\"Generating the hardware\")\n (new chisel3.stage.ChiselStage).emitVerilog(new Join(32), Array(\"--target-dir\", \"generated\"))\n}\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/main/scala/OverlayRocc.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ****************************************/\nimport chisel3._\nimport chisel3.util._\n\nclass OverlayRocc \n (\n dataWidth: Int = 32, \n inputNodes: Int = 6, \n outputNodes: Int = 6, \n fifoDepth: Int = 32\n ) \n extends Module { val io = IO(new Bundle {\n val dataIn = Input(SInt((dataWidthinputNodes).W))\n val dataInValid = Input(UInt(inputNodes.W))\n val dataInReady = Output(UInt(inputNodes.W))\n val dataOut = Output(UInt((dataWidthinputNodes).W))\n val dataOutValid = Output(UInt(inputNodes.W))\n val dataOutReady = Input(UInt(inputNodes.W))\n val cellConfig = Input(UInt(192.W))\n })\n \n val northDin = Wire(Vec(inputNodes, SInt(dataWidth.W)))\n val northDinValid = Wire(Vec(inputNodes, Bool()))\n\n val vecDataInReady = Wire(Vec(inputNodes, Bool()))\n\n val vecDataOutValid = Wire(Vec(inputNodes, Bool()))\n val northDinReady = Wire(Vec(inputNodes, Bool()))\n\n val eastDout = Wire(Vec(outputNodes, SInt(dataWidth.W)))\n val eastDoutValid = Wire(Vec(outputNodes, Bool()))\n val eastDoutReady = Wire(Vec(outputNodes, Bool()))\n \n\n val intercDataWE = VecInit.fill(inputNodes -1, outputNodes)(0.asSInt(dataWidth.W)) \n val intercDataEW = VecInit.fill(inputNodes -1, outputNodes)(0.asSInt(dataWidth.W)) \n\n val intercValidWE = VecInit.fill(inputNodes -1, outputNodes)(0.asUInt(1.W)) \n val intercValidEW = VecInit.fill(inputNodes -1, outputNodes)(0.asUInt(1.W)) \n\n val intercReadyWE = VecInit.fill(inputNodes -1, outputNodes)(0.asUInt(1.W)) \n val intercReadyEW = VecInit.fill(inputNodes -1, outputNodes)(0.asUInt(1.W)) \n\n\n val intercDataNS = VecInit.fill(inputNodes, outputNodes - 1)(0.asSInt(dataWidth.W)) \n val intercDataSN = VecInit.fill(inputNodes, outputNodes - 1)(0.asSInt(dataWidth.W)) \n\n val intercValidNS = VecInit.fill(inputNodes, outputNodes -1)(0.asUInt(1.W))\n val intercValidSN = VecInit.fill(inputNodes, outputNodes -1)(0.asUInt(1.W))\n\n val intercReadyNS = VecInit.fill(inputNodes, outputNodes -1)(0.asUInt(1.W))\n val intercReadySN = VecInit.fill(inputNodes, outputNodes -1)(0.asUInt(1.W))\n\n val configBits = Wire(UInt(182.W))\n val catchConfig = Wire(Vec(inputNodesoutputNodes, Bool()))\n\n \n // ***************************************************************** Needs test\n val unsignedCellConfig = io.cellConfig(190,185).asUInt\n configBits := io.cellConfig(181,0)\n\n for( i <- 0 to inputNodesoutputNodes - 1){\n catchConfig(i) := 0.B \n }\n\n", "right_context": " northDin(i) := (io.dataIn(dataWidth(i+1) - 1, dataWidthi)).asSInt\n northDinValid(i) := io.dataInValid(i) \n vecDataInReady(i) := northDinReady(i)\n \n }\n\n io.dataInReady := vecDataInReady.asUInt \n val vecDataOut = Wire(Vec(outputNodes, SInt(dataWidth.W)))\n\n val I = RegInit(0.U(log2Ceil(inputNodes).W))\n val J = RegInit(0.U(log2Ceil(outputNodes).W))\n\n for (I <- 0 until inputNodes) \n { \n for (J <- 0 until outputNodes) \n {\n // WEST_OV \n if (I == 0) \n {\n if (J == 0) \n {\n val northWestOv = Module(new ProcessingElement(dataWidth, fifoDepth))\n\n // ****** North\n northWestOv.io.northDin := northDin(I)\n northWestOv.io.northDinValid := northDinValid(I)\n northDinReady(I) := northWestOv.io.northDinReady.asBool \n\n // ***** East\n northWestOv.io.eastDin := intercDataWE(I)(J)\n northWestOv.io.eastDinValid := intercValidWE(I)(J)\n intercReadyWE(I)(J) := northWestOv.io.eastDinReady \n\n // ***** South \n northWestOv.io.southDin := intercDataNS(I)(J)\n northWestOv.io.southDinValid := intercValidNS(I)(J)\n intercReadyNS(I)(J) := northWestOv.io.southDinReady \n\n // ***** West\n northWestOv.io.westDin := 0.S \n northWestOv.io.westDinValid := 0.U \n // westDinReady = open \n\n // ***** North\n // northDout = open\n // northDoutValid = open\n northWestOv.io.northDoutReady := 0.U \n\n // ***** East\n intercDataEW(I)(J) := northWestOv.io.eastDout \n intercValidEW(I)(J) := northWestOv.io.eastDoutValid \n northWestOv.io.eastDoutReady := intercReadyEW(I)(J)\n\n // ***** South\n intercDataSN(I)(J) := northWestOv.io.southDout \n intercValidSN(I)(J) := northWestOv.io.southDoutValid \n northWestOv.io.southDoutReady := intercReadySN(I)(J)\n\n // ***** West\n // westDout = open\n // westDoutValid = open\n northWestOv.io.westDoutReady := 0.U \n\n // ******* Config\n northWestOv.io.configBits := configBits\n northWestOv.io.catchConfig := catchConfig(I+inputNodesJ) \n }\n\n if (J != 0 & J != outputNodes - 1) \n {\n val midWestOv = Module(new ProcessingElement(dataWidth, fifoDepth))\n\n // ****** North\n midWestOv.io.northDin := intercDataSN(I)(J-1) \n midWestOv.io.northDinValid := intercValidSN(I)(J-1) \n intercReadySN(I)(J-1) := midWestOv.io.northDinReady \n\n // ***** East\n midWestOv.io.eastDin := intercDataWE(I)(J) \n midWestOv.io.eastDinValid := intercValidWE(I)(J) \n intercReadyWE(I)(J) := midWestOv.io.eastDinReady \n\n // ***** South\n midWestOv.io.southDin := intercDataNS(I)(J) \n midWestOv.io.southDinValid := intercValidNS(I)(J) \n intercReadyNS(I)(J) := midWestOv.io.southDinReady \n\n // ***** West\n midWestOv.io.westDin := 0.S \n midWestOv.io.westDinValid := 0.U\n //westDinReady = open \n\n // ***** North\n intercDataNS(I)(J-1) := midWestOv.io.northDout \n intercValidNS(I)(J-1) := midWestOv.io.northDoutValid \n midWestOv.io.northDoutReady := intercReadyNS(I)(J-1) \n\n // ***** East\n intercDataEW(I)(J) := midWestOv.io.eastDout \n intercValidEW(I)(J) := midWestOv.io.eastDoutValid \n midWestOv.io.eastDoutReady := intercReadyEW(I)(J) \n\n // ***** South\n intercDataSN(I)(J) := midWestOv.io.southDout \n intercValidSN(I)(J) := midWestOv.io.southDoutValid \n midWestOv.io.southDoutReady := intercReadySN(I)(J) \n\n // ***** West\n //westDout = open \n //westDoutValid = open \n midWestOv.io.westDoutReady := 0.U \n\n // ******* Config\n midWestOv.io.configBits := configBits\n midWestOv.io.catchConfig := catchConfig(I+inputNodesJ) \n }\n\n if (J == outputNodes - 1) \n {\n val southWestOv = Module(new ProcessingElement(dataWidth, fifoDepth))\n\n // ****** North\n southWestOv.io.northDin := intercDataSN(I)(J-1) \n southWestOv.io.northDinValid := intercValidSN(I)(J-1) \n intercReadySN(I)(J-1) := southWestOv.io.northDinReady \n\n // ***** East\n southWestOv.io.eastDin := intercDataWE(I)(J) \n southWestOv.io.eastDinValid := intercValidWE(I)(J) \n intercReadyWE(I)(J) := southWestOv.io.eastDinReady \n\n // ***** South\n southWestOv.io.southDin := 0.S \n southWestOv.io.southDinValid := 0.U \n // southDinReady = open\n\n // ***** West\n southWestOv.io.westDin := 0.S \n southWestOv.io.westDinValid := 0.U \n // westDinReady = open \n\n // ***** North\n intercDataNS(I)(J-1) := southWestOv.io.northDout \n intercValidNS(I)(J-1) := southWestOv.io.northDoutValid \n southWestOv.io.northDoutReady := intercReadyNS(I)(J-1) \n\n // ***** East\n intercDataEW(I)(J) := southWestOv.io.eastDout\n intercValidEW(I)(J) := southWestOv.io.eastDoutValid\n southWestOv.io.eastDoutReady := intercReadyEW(I)(J) \n\n // ***** South\n // southDout = open \n // southDoutValid = open \n southWestOv.io.southDoutReady := 0.U \n\n // ***** West\n // westDout = open \n // westDoutValid = open \n southWestOv.io.westDoutReady := 0.U \n\n // ******* Config\n southWestOv.io.configBits := configBits\n southWestOv.io.catchConfig := catchConfig(I+inputNodesJ) \n }\n } \n //////////////////////////////////////////////////// \n // MIDDLE_OV \n if (I != 0 & I != inputNodes - 1) \n {\n if (J == 0)\n {\n val middleNorthOv = Module(new ProcessingElement(dataWidth, fifoDepth))\n\n // ****** North\n middleNorthOv.io.northDin := northDin(I) \n middleNorthOv.io.northDinValid := northDinValid(I) \n northDinReady(I) := middleNorthOv.io.northDinReady \n\n // ***** East\n middleNorthOv.io.eastDin:= intercDataWE(I)(J) \n middleNorthOv.io.eastDinValid := intercValidWE(I)(J) \n intercReadyWE(I)(J) := middleNorthOv.io.eastDinReady \n\n // ***** South\n middleNorthOv.io.southDin := intercDataNS(I)(J) \n middleNorthOv.io.southDinValid := intercValidNS(I)(J) \n intercReadyNS(I)(J) := middleNorthOv.io.southDinReady \n\n // ***** West\n middleNorthOv.io.westDin:= intercDataEW(I-1)(J) \n middleNorthOv.io.westDinValid := intercValidEW(I-1)(J) \n intercReadyEW(I-1)(J) := middleNorthOv.io.westDinReady \n \n // ***** North\n // northDout = open \n // northDoutValid = open \n middleNorthOv.io.northDoutReady := 0.U\n\n // ***** East \n intercDataEW(I)(J) := middleNorthOv.io.eastDout \n intercValidEW(I)(J) := middleNorthOv.io.eastDoutValid \n middleNorthOv.io.eastDoutReady := intercReadyEW(I)(J)\n\n // ***** South\n intercDataSN(I)(J) := middleNorthOv.io.southDout \n intercValidSN(I)(J) := middleNorthOv.io.southDoutValid\n middleNorthOv.io.southDoutReady := intercReadySN(I)(J)\n\n // ***** West\n intercDataWE(I-1)(J) := middleNorthOv.io.westDout \n intercValidWE(I-1)(J) := middleNorthOv.io.westDoutValid \n middleNorthOv.io.westDoutReady := intercReadyWE(I-1)(J)\n\n // ******* Config\n middleNorthOv.io.configBits := configBits \n middleNorthOv.io.catchConfig := catchConfig(I+inputNodesJ) \n }\n\n if(J != 0 & J != outputNodes - 1)\n {\n val middleMiddleOv = Module(new ProcessingElement(dataWidth, fifoDepth))\n\n // ****** North\n middleMiddleOv.io.northDin := intercDataSN(I)(J-1) \n middleMiddleOv.io.northDinValid := intercValidSN(I)(J-1) \n intercReadySN(I)(J-1) := middleMiddleOv.io.northDinReady \n\n // ***** East\n middleMiddleOv.io.eastDin := intercDataWE(I)(J) \n middleMiddleOv.io.eastDinValid := intercValidWE(I)(J) \n intercReadyWE(I)(J) := middleMiddleOv.io.eastDinReady \n\n // ***** South\n middleMiddleOv.io.southDin := intercDataNS(I)(J) \n middleMiddleOv.io.southDinValid := intercValidNS(I)(J) \n intercReadyNS(I)(J) := middleMiddleOv.io.southDinReady \n\n // ***** West\n middleMiddleOv.io.westDin := intercDataEW(I-1)(J) \n middleMiddleOv.io.westDinValid := intercValidEW(I-1)(J)\n intercReadyEW(I-1)(J) := middleMiddleOv.io.westDinReady \n\n // ***** North\n intercDataNS(I)(J-1) := middleMiddleOv.io.northDout \n intercValidNS(I)(J-1) := middleMiddleOv.io.northDoutValid\n middleMiddleOv.io.northDoutReady := intercReadyNS(I)(J-1)\n\n // ***** East\n intercDataEW(I)(J) := middleMiddleOv.io.eastDout\n intercValidEW(I)(J) := middleMiddleOv.io.eastDoutValid \n middleMiddleOv.io.eastDoutReady := intercReadyEW(I)(J)\n\n // ***** South\n intercDataSN(I)(J) := middleMiddleOv.io.southDout \n intercValidSN(I)(J) := middleMiddleOv.io.southDoutValid\n middleMiddleOv.io.southDoutReady := intercReadySN(I)(J) \n\n // ***** West\n intercDataWE(I-1)(J) := middleMiddleOv.io.westDout \n intercValidWE(I-1)(J) := middleMiddleOv.io.westDoutValid \n middleMiddleOv.io.westDoutReady := intercReadyWE(I-1)(J) \n\n // ******* Config\n middleMiddleOv.io.configBits := configBits\n middleMiddleOv.io.catchConfig:= catchConfig(I+inputNodesJ) \n } \n\n if (J == outputNodes - 1)\n {\n val middleSouthOv = Module(new ProcessingElement(dataWidth, fifoDepth))\n\n // ****** North\n middleSouthOv.io.northDin := intercDataSN(I)(J-1) \n middleSouthOv.io.northDinValid := intercValidSN(I)(J-1)\n intercReadySN(I)(J-1) := middleSouthOv.io.northDinReady \n\n // ***** East\n middleSouthOv.io.eastDin := intercDataWE(I)(J) \n middleSouthOv.io.eastDinValid := intercValidWE(I)(J) \n intercReadyWE(I)(J) := middleSouthOv.io.eastDinReady \n\n // ***** South\n middleSouthOv.io.southDin := 0.S \n middleSouthOv.io.southDinValid := 0.U \n // southDinReady = open \n\n // ***** West\n middleSouthOv.io.westDin := intercDataEW(I-1)(J) \n middleSouthOv.io.westDinValid := intercValidEW(I-1)(J) \n intercReadyEW(I-1)(J) := middleSouthOv.io.westDinReady \n \n // ***** North\n intercDataNS(I)(J-1) := middleSouthOv.io.northDout \n intercValidNS(I)(J-1) := middleSouthOv.io.northDoutValid \n middleSouthOv.io.northDoutReady := intercReadyNS(I)(J-1) \n\n // ***** East\n intercDataEW(I)(J) := middleSouthOv.io.eastDout \n intercValidEW(I)(J) := middleSouthOv.io.eastDoutValid \n middleSouthOv.io.eastDoutReady := intercReadyEW(I)(J)\n\n // ***** South\n // southDout = open \n // southDoutValid = open \n middleSouthOv.io.southDoutReady := 0.U\n\n // ***** West\n intercDataWE(I-1)(J) := middleSouthOv.io.westDout \n intercValidWE(I-1)(J) := middleSouthOv.io.westDoutValid \n middleSouthOv.io.westDoutReady := intercReadyWE(I-1)(J) \n\n // ******* Config\n middleSouthOv.io.configBits := configBits\n middleSouthOv.io.catchConfig := catchConfig(I+inputNodesJ) \n } \n }\n \n // EAST_OV \n if (I == inputNodes - 1)\n {\n if (J == 0)\n {\n val northEastOv = Module(new ProcessingElement(dataWidth, fifoDepth))\n\n // ****** North\n northEastOv.io.northDin := northDin(I) \n northEastOv.io.northDinValid := northDinValid(I) \n northDinReady(I) := northEastOv.io.northDinReady \n\n // ***** East\n northEastOv.io.eastDin := 0.S \n northEastOv.io.eastDinValid := 0.U \n // eastDinReady = open \n\n // ***** South\n northEastOv.io.southDin := intercDataNS(I)(J) \n northEastOv.io.southDinValid := intercValidNS(I)(J) \n intercReadyNS(I)(J) := northEastOv.io.southDinReady \n\n // ***** West\n northEastOv.io.westDin := intercDataEW(I-1)(J) \n northEastOv.io.westDinValid := intercValidEW(I-1)(J) \n intercReadyEW(I-1)(J) := northEastOv.io.westDinReady \n\n // ***** North\n // northDout = open \n // northDoutValid = open \n northEastOv.io.northDoutReady := 0.U \n\n // ***** East\n eastDout(J) := northEastOv.io.eastDout \n eastDoutValid(J) := northEastOv.io.eastDoutValid \n northEastOv.io.eastDoutReady := eastDoutReady(J) \n\n // ***** South\n intercDataSN(I)(J) := northEastOv.io.southDout \n intercValidSN(I)(J) := northEastOv.io.southDoutValid \n northEastOv.io.southDoutReady := intercReadySN(I)(J) \n\n // ***** West\n intercDataWE(I-1)(J) := northEastOv.io.westDout \n intercValidWE(I-1)(J) := northEastOv.io.westDoutValid \n northEastOv.io.westDoutReady := intercReadyWE(I-1)(J)\n\n // ******* Config\n northEastOv.io.configBits := configBits\n northEastOv.io.catchConfig := catchConfig(I+inputNodesJ) \n }\n\n if (J != 0 & J != outputNodes - 1)\n {\n val middleEastOv = Module(new ProcessingElement(dataWidth,fifoDepth))\n\n // ****** North\n middleEastOv.io.northDin := intercDataSN(I)(J-1) \n middleEastOv.io.northDinValid := intercValidSN(I)(J-1)\n intercReadySN(I)(J-1) := middleEastOv.io.northDinReady \n \n // ***** East\n middleEastOv.io.eastDin := 0.S \n middleEastOv.io.eastDinValid := 0.U \n // io.eastDinReady = open \n\n // ***** South\n middleEastOv.io.southDin := intercDataNS(I)(J)\n middleEastOv.io.southDinValid:= intercValidNS(I)(J)\n intercReadyNS(I)(J) := middleEastOv.io.southDinReady \n\n // ***** West\n middleEastOv.io.westDin := intercDataEW(I-1)(J)\n middleEastOv.io.westDinValid := intercValidEW(I-1)(J) \n intercReadyEW(I-1)(J) := middleEastOv.io.westDinReady \n\n // ***** North\n intercDataNS(I)(J-1) := middleEastOv.io.northDout \n intercValidNS(I)(J-1) := middleEastOv.io.northDoutValid \n middleEastOv.io.northDoutReady := intercReadyNS(I)(J-1)\n\n // ***** East\n eastDout(J) := middleEastOv.io.eastDout \n eastDoutValid(J) := middleEastOv.io.eastDoutValid \n middleEastOv.io.eastDoutReady := eastDoutReady(J)\n\n // ***** South\n intercDataSN(I)(J) := middleEastOv.io.southDout \n intercValidSN(I)(J) := middleEastOv.io.southDoutValid \n middleEastOv.io.southDoutReady := intercReadySN(I)(J)\n\n // ***** West\n intercDataWE(I-1)(J) := middleEastOv.io.westDout \n intercValidWE(I-1)(J) := middleEastOv.io.westDoutValid \n middleEastOv.io.westDoutReady := intercReadyWE(I-1)(J)\n\n // ******* Config\n middleEastOv.io.configBits := configBits\n middleEastOv.io.catchConfig := catchConfig(I+inputNodesJ) \n } \n\n if (J == outputNodes - 1)\n {\n val middleSouthOv = Module(new ProcessingElement(dataWidth, fifoDepth))\n\n // ****** North\n middleSouthOv.io.northDin := intercDataSN(I)(J-1)\n middleSouthOv.io.northDinValid := intercValidSN(I)(J-1)\n intercReadySN(I)(J-1) := middleSouthOv.io.northDinReady \n\n // ***** East\n middleSouthOv.io.eastDin := 0.S \n middleSouthOv.io.eastDinValid := 0.U\n //io.eastDinReady = open\n\n // ***** South\n middleSouthOv.io.southDin := 0.S \n middleSouthOv.io.southDinValid := 0.U\n // io.southDinReady = open\n\n // ***** West\n middleSouthOv.io.westDin := intercDataEW(I-1)(J)\n middleSouthOv.io.westDinValid := intercValidEW(I-1)(J)\n intercReadyEW(I-1)(J) := middleSouthOv.io.westDinReady \n\n // ***** North\n intercDataNS(I)(J-1) := middleSouthOv.io.northDout \n intercValidNS(I)(J-1) := middleSouthOv.io.northDoutValid \n middleSouthOv.io.northDoutReady := intercReadyNS(I)(J-1)\n\n // ***** East\n eastDout(J) := middleSouthOv.io.eastDout \n eastDoutValid(J) := middleSouthOv.io.eastDoutValid \n middleSouthOv.io.eastDoutReady := eastDoutReady(J)\n\n // ***** South\n // southDout = open\n // southDoutValid = open\n middleSouthOv.io.southDoutReady := 0.U\n\n // ***** West\n intercDataWE(I-1)(J) := middleSouthOv.io.westDout \n intercValidWE(I-1)(J) := middleSouthOv.io.westDoutValid \n middleSouthOv.io.westDoutReady := intercReadyWE(I-1)(J)\n\n // ******* Config\n middleSouthOv.io.configBits := configBits\n middleSouthOv.io.catchConfig := catchConfig(I+inputNodes*J)\n } \n }\n } \n }\n for( i <- 0 to outputNodes - 1){\n vecDataOut(i) := eastDout(i)\n vecDataOutValid (i) := eastDoutValid(i) \n eastDoutReady(i) := io.dataOutReady(i)\n }\n io.dataOut := vecDataOut.asUInt \n io.dataOutValid := vecDataOutValid.asUInt \n}\n\n// Generate the Verilog code\nobject OverlayRoccMain extends App {\n println(\"Generating the hardware\")\n (new chisel3.stage.ChiselStage).emitVerilog(new OverlayRocc(32, 6, 6, 32), Array(\"--target-dir\", \"generated\"))\n}\n", "groundtruth": " when (io.cellConfig(191) === 1.U){\n catchConfig(unsignedCellConfig) := 1.B \n }\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/main/scala/ProcessingElement.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n *****************************************/\nimport chisel3._\nimport chisel3.util._\n\n", "right_context": " (\n dataWidth: Int, \n fifoDepth: Int\n ) \n extends Module {\n val io = IO(new Bundle {\n // Data in\n val northDin = Input(SInt(dataWidth.W))\n val northDinValid = Input(Bool())\n val northDinReady = Output(Bool())\n\n val eastDin = Input(SInt(dataWidth.W))\n val eastDinValid = Input(Bool())\n val eastDinReady = Output(Bool())\n\n val southDin = Input(SInt(dataWidth.W))\n val southDinValid = Input(Bool())\n val southDinReady = Output(Bool())\n\n val westDin = Input(SInt(dataWidth.W))\n val westDinValid = Input(Bool())\n val westDinReady = Output(Bool())\n\n // Data out\n val northDout = Output(SInt(dataWidth.W))\n val northDoutValid = Output(Bool())\n val northDoutReady = Input(Bool())\n\n val eastDout = Output(SInt(dataWidth.W))\n val eastDoutValid = Output(Bool())\n val eastDoutReady = Input(Bool())\n\n val southDout = Output(SInt(dataWidth.W))\n val southDoutValid = Output(Bool())\n val southDoutReady = Input(Bool())\n\n val westDout = Output(SInt(dataWidth.W))\n val westDoutValid = Output(Bool())\n val westDoutReady = Input(Bool())\n \n // Config\n val configBits = Input(UInt(182.W))\n val catchConfig = Input(Bool())\n })\n\n // Config signals\n val muxNsel = Wire(UInt(2.W))\n val muxEsel = Wire(UInt(2.W))\n val muxSsel = Wire(UInt(2.W))\n val muxWsel = Wire(UInt(2.W))\n val acceptMaskFrN = Wire(UInt(5.W))\n val acceptMaskFrE = Wire(UInt(5.W))\n val acceptMaskFrS = Wire(UInt(5.W))\n val acceptMaskFrW = Wire(UInt(5.W))\n val acceptMaskFsiN = Wire(UInt(5.W))\n val acceptMaskFsiE = Wire(UInt(5.W))\n val acceptMaskFsiS = Wire(UInt(5.W))\n val acceptMaskFsiW = Wire(UInt(5.W))\n\n val configBitsReg = RegInit(0.U(182.W))\n \n // Interconnect signals\n val northBuffer = Wire(SInt(dataWidth.W))\n val eastBuffer = Wire(SInt(dataWidth.W))\n val southBuffer = Wire(SInt(dataWidth.W))\n val westBuffer = Wire(SInt(dataWidth.W))\n\n val northBufferValid = Wire(UInt(1.W))\n val eastBufferValid = Wire(UInt(1.W))\n val southBufferValid = Wire(UInt(1.W))\n val westBufferValid = Wire(UInt(1.W))\n\n val northBufferReady = Wire(UInt(1.W))\n val eastBufferReady = Wire(UInt(1.W))\n val southBufferReady = Wire(UInt(1.W))\n val westBufferReady = Wire(UInt(1.W)) \n \n val northRegDin = Wire(SInt(dataWidth.W))\n val eastRegDin = Wire(SInt(dataWidth.W))\n val southRegDin = Wire(SInt(dataWidth.W))\n val westRegDin = Wire(SInt(dataWidth.W))\n\n val northRegDinValid = Wire(UInt(1.W))\n val eastRegDinValid = Wire(UInt(1.W))\n val southRegDinValid = Wire(UInt(1.W))\n val westRegDinValid = Wire(UInt(1.W))\n\n val northRegDinReady = Wire(UInt(1.W))\n val eastRegDinReady = Wire(UInt(1.W))\n val southRegDinReady = Wire(UInt(1.W))\n val westRegDinReady = Wire(UInt(1.W))\n // cell processing signals\n val fuDin1Ready = Wire(UInt(1.W))\n val fuDin2Ready = Wire(UInt(1.W))\n val fuDout = Wire(SInt(dataWidth.W))\n val fuDoutValid = Wire(UInt(1.W))\n \n when (io.catchConfig) {\n configBitsReg := io.configBits\n }\n // Configuration bits arrangement\n // val muxNsel = configBitsReg(7, 6)\n muxNsel := configBitsReg(7, 6)\n muxEsel := configBitsReg(9, 8)\n muxSsel := configBitsReg(11, 10)\n muxWsel := configBitsReg(13, 12)\n // cell_interior conf\n acceptMaskFsiN := configBitsReg(28, 24)\n acceptMaskFsiE := configBitsReg(33, 29)\n acceptMaskFsiS := configBitsReg(38, 34)\n acceptMaskFsiW := configBitsReg(43, 39)\n // cell_interior conf\n acceptMaskFrN := configBitsReg(61, 57)\n acceptMaskFrE := configBitsReg(66, 62)\n acceptMaskFrS := configBitsReg(71, 67)\n acceptMaskFrW := configBitsReg(76, 72)\n \n // ------------------------------- NORTH NODE -------------------------------\n\n val fifoNin = Module (new DFifo(dataWidth, fifoDepth))\n fifoNin.io.din := io.northDin \n fifoNin.io.dinValid := io.northDinValid\n fifoNin.io.doutReady := northBufferReady\n io.northDinReady := fifoNin.io.dinReady \n northBuffer := fifoNin.io.dout \n northBufferValid := fifoNin.io.doutValid \n\n val fsNin = Module (new Fs(5))\n val ready_out_fsNin = Cat(fuDin1Ready, fuDin2Ready, eastRegDinReady, southRegDinReady, westRegDinReady) \n fsNin.io.readyOut := ready_out_fsNin\n northBufferReady := fsNin.io.readyIn\n fsNin.io.forkMask := acceptMaskFsiN\n \n val muxNout = Module (new ConfMux(4, dataWidth))\n muxNout.io.selector := muxNsel\n muxNout.io.muxInput := (Cat(westBuffer, southBuffer, eastBuffer, fuDout)).asSInt \n northRegDin := muxNout.io.muxOutput\n \n val frNout = Module (new Fr(4, 5))\n val ready_frNout = Cat(fuDin1Ready, fuDin2Ready, eastRegDinReady, southRegDinReady, westRegDinReady) \n val validIn_frNout = Cat(westBufferValid, southBufferValid, eastBufferValid, fuDoutValid) \n frNout.io.readyOut := ready_frNout\n frNout.io.validIn := validIn_frNout\n frNout.io.validMuxSel := muxNsel\n frNout.io.forkMask := acceptMaskFrN\n northRegDinValid := frNout.io.validOut \n\n val regNout = Module (new DReg(dataWidth))\n \n regNout.io.din := northRegDin \n regNout.io.dinValid := northRegDinValid \n regNout.io.doutReady := io.northDoutReady\n\n northRegDinReady := regNout.io.dinReady\n io.northDout := regNout.io.dout \n io.northDoutValid := regNout.io.doutValid \n \n //------------------------------- NORTH NODE -------------------------------\n\n // ------------------------------- EAST NODE -------------------------------\n \n val fifoEin = Module (new DFifo(dataWidth, fifoDepth))\n fifoEin.io.din := io.eastDin \n fifoEin.io.dinValid := io.eastDinValid\n fifoEin.io.doutReady := eastBufferReady\n io.eastDinReady := fifoEin.io.dinReady \n eastBuffer := fifoEin.io.dout \n eastBufferValid := fifoEin.io.doutValid \n\n val fsEin = Module (new Fs(5))\n val ready_out_fsEin = Cat(fuDin1Ready, fuDin2Ready, northRegDinReady, southRegDinReady, westRegDinReady) \n fsEin.io.readyOut := ready_out_fsEin\n eastBufferReady := fsEin.io.readyIn\n fsEin.io.forkMask := acceptMaskFsiE\n\n val muxEout = Module (new ConfMux(4, dataWidth))\n muxEout.io.selector := muxEsel\n muxEout.io.muxInput := (Cat(westBuffer, southBuffer, northBuffer, fuDout)).asSInt\n eastRegDin := muxEout.io.muxOutput\n \n val frEout = Module (new Fr(4, 5))\n val ready_frEout = Cat(fuDin1Ready, fuDin2Ready, northRegDinReady, southRegDinReady, westRegDinReady) \n val validIn_frEout = Cat(westBufferValid, southBufferValid, northBufferValid, fuDoutValid) \n frEout.io.readyOut := ready_frEout\n frEout.io.validIn := validIn_frEout\n frEout.io.validMuxSel := muxEsel\n frEout.io.forkMask := acceptMaskFrE\n eastRegDinValid := frEout.io.validOut \n\n val regEout = Module (new DReg(dataWidth))\n \n regEout.io.din := eastRegDin \n regEout.io.dinValid := eastRegDinValid \n regEout.io.doutReady := io.eastDoutReady\n\n eastRegDinReady := regEout.io.dinReady\n io.eastDout := regEout.io.dout \n io.eastDoutValid := regEout.io.doutValid \n \n // ------------------------------- EAST NODE -------------------------------\n\n // ------------------------------- SOUTH NODE -------------------------------\n \n val fifoSin = Module (new DFifo(dataWidth, fifoDepth))\n fifoSin.io.din := io.southDin \n fifoSin.io.dinValid := io.southDinValid\n fifoSin.io.doutReady := southBufferReady\n io.southDinReady := fifoSin.io.dinReady \n southBuffer := fifoSin.io.dout \n southBufferValid := fifoSin.io.doutValid \n\n val fsSin = Module (new Fs(5))\n val ready_out_fsSin = Cat(fuDin1Ready, fuDin2Ready, northRegDinReady, eastRegDinReady, westRegDinReady) \n fsSin.io.readyOut := ready_out_fsSin\n southBufferReady := fsSin.io.readyIn\n fsSin.io.forkMask := acceptMaskFsiS\n \n val muxSout = Module (new ConfMux(4, dataWidth))\n muxSout.io.selector := muxSsel\n muxSout.io.muxInput := (Cat(westBuffer, eastBuffer, northBuffer, fuDout)).asSInt\n southRegDin := muxSout.io.muxOutput\n\n val frSout = Module (new Fr(4, 5))\n val ready_frSout = Cat(fuDin1Ready, fuDin2Ready, northRegDinReady, eastRegDinReady, westRegDinReady) \n val validIn_frSout = Cat(westBufferValid, eastBufferValid, northBufferValid, fuDoutValid) \n frSout.io.readyOut := ready_frSout\n frSout.io.validIn := validIn_frSout\n frSout.io.validMuxSel := muxSsel\n frSout.io.forkMask := acceptMaskFrS\n southRegDinValid := frSout.io.validOut \n\n val regSout = Module (new DReg(dataWidth))\n \n regSout.io.din := southRegDin \n regSout.io.dinValid := southRegDinValid \n regSout.io.doutReady := io.southDoutReady\n\n southRegDinReady := regSout.io.dinReady\n io.southDout := regSout.io.dout \n io.southDoutValid := regSout.io.doutValid \n // ------------------------------- SOUTH NODE -------------------------------\n\n // ------------------------------- WEST NODE -------------------------------\n\n val fifoWin = Module (new DFifo(dataWidth, fifoDepth))\n fifoWin.io.din := io.westDin \n fifoWin.io.dinValid := io.westDinValid\n fifoWin.io.doutReady := westBufferReady\n io.westDinReady := fifoWin.io.dinReady \n westBuffer := fifoWin.io.dout \n westBufferValid := fifoWin.io.doutValid \n\n val fsWin = Module (new Fs(5))\n val ready_out_fsWin = Cat(fuDin1Ready, fuDin2Ready, northRegDinReady, eastRegDinReady, southRegDinReady) \n fsWin.io.readyOut := ready_out_fsWin\n fsWin.io.forkMask := acceptMaskFsiW\n westBufferReady := fsWin.io.readyIn\n\n val muxWout = Module (new ConfMux(4, dataWidth))\n muxWout.io.selector := muxWsel\n muxWout.io.muxInput := (Cat(southBuffer, eastBuffer, northBuffer, fuDout)).asSInt \n westRegDin := muxWout.io.muxOutput\n\n val frWout = Module (new Fr(4, 5))\n val ready_frWout = Cat(fuDin1Ready, fuDin2Ready, northRegDinReady, eastRegDinReady, southRegDinReady) \n val validIn_frWout = Cat(southBufferValid, eastBufferValid, northBufferValid, fuDoutValid) \n frWout.io.readyOut := ready_frWout\n frWout.io.validIn := validIn_frWout\n frWout.io.validMuxSel := muxWsel\n frWout.io.forkMask := acceptMaskFrW\n westRegDinValid := frWout.io.validOut \n\n val regWout = Module (new DReg(dataWidth))\n \n regWout.io.din := westRegDin \n regWout.io.dinValid := westRegDinValid \n regWout.io.doutReady := io.westDoutReady\n\n westRegDinReady := regWout.io.dinReady\n io.westDout := regWout.io.dout \n io.westDoutValid := regWout.io.doutValid \n // ------------------------------- WEST NODE -------------------------------\n\n // cell processing\n val cell = Module (new CellProcessing(dataWidth))\n cell.io.northDin := northBuffer\n cell.io.northDinValid := northBufferValid\n cell.io.eastDin := eastBuffer\n cell.io.eastDinValid := eastBufferValid\n cell.io.southDin := southBuffer\n cell.io.southDinValid := southBufferValid\n cell.io.westDin := westBuffer\n cell.io.westDinValid := westBufferValid\n cell.io.northDoutReady := northRegDinReady\n cell.io.eastDoutReady := eastRegDinReady\n cell.io.southDoutReady := southRegDinReady\n cell.io.westDoutReady := westRegDinReady\n cell.io.configBits := configBitsReg\n fuDin1Ready := cell.io.fuDin1Ready \n fuDin2Ready := cell.io.fuDin2Ready \n fuDout := cell.io.dout \n fuDoutValid := cell.io.doutValid \n}\n\n// Generate the Verilog code\nobject ProcessingElementMain extends App {\n println(\"Generating the hardware\")\n (new chisel3.stage.ChiselStage).emitVerilog(new ProcessingElement(32, 32), Array(\"--target-dir\", \"generated\"))\n}", "groundtruth": "class ProcessingElement \n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/AluTest.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ****************************************/\nimport chisel3._\nimport chiseltest._\nimport org.scalatest.flatspec.AnyFlatSpec\n\nclass AluTest extends AnyFlatSpec with ChiselScalatestTester {\n \"AluTest test\" should \"pass\" in {\n test(new Alu(32, 4)) { dut =>\n\n var numOfTests = 10\n \n ////////////////////////////////////////////////////////////////\n // Test 1: SUM\n ////////////////////////////////////////////////////////////////\n dut.io.opConfig.poke(0.U)\n\n // Pos\n for (i <- 1 until numOfTests) {\n dut.io.din1.poke(i.S)\n dut.io.din2.poke((i+1).S)\n dut.clock.step(1)\n }\n // Neg \n for (i <- 1 until numOfTests) {\n dut.io.din1.poke((-i).S)\n dut.io.din2.poke((-(i+1)).S)\n dut.clock.step(1)\n }\n ////////////////////////////////////////////////////////////////\n // Test 2: MUL \n ////////////////////////////////////////////////////////////////\n dut.io.opConfig.poke(1.U)\n\n dut.io.din1.poke(5.S)\n dut.io.din2.poke(100.S)\n dut.clock.step(1)\n dut.io.din1.poke(-5.S)\n dut.io.din2.poke(100.S)\n dut.clock.step(1)\n dut.io.din1.poke(-5.S)\n dut.io.din2.poke(-100.S)\n dut.clock.step(1)\n dut.io.din1.poke(65535.S)\n dut.io.din2.poke(65535.S)\n dut.clock.step(1)\n dut.io.din1.poke(65535.S)\n dut.io.din2.poke(65536.S)\n dut.clock.step(1)\n dut.io.din1.poke(65535.S)\n dut.io.din2.poke(65537.S)\n dut.clock.step(1)\n dut.io.din1.poke(65537.S)\n dut.io.din2.poke(65547.S)\n dut.clock.step(1)\n ////////////////////////////////////////////////////////////////\n // Test 3: SUB \n ////////////////////////////////////////////////////////////////\n dut.io.opConfig.poke(2.U)\n\n for (i <- 1 until numOfTests) {\n dut.io.din1.poke((i+2).S)\n dut.io.din2.poke((i).S)\n dut.clock.step(1)\n }\n\n for (i <- 1 until numOfTests) {\n dut.io.din1.poke((-i).S)\n dut.io.din2.poke((-(i+1)).S)\n dut.clock.step(1)\n }\n ////////////////////////////////////////////////////////////////\n // Test 4: SLL \n ////////////////////////////////////////////////////////////////\n dut.io.opConfig.poke(3.U)\n\n dut.io.din1.poke(1.S)\n for (i <- 1 until numOfTests) {\n dut.io.din2.poke(i.S)\n dut.clock.step(1)\n }\n\n dut.io.din1.poke(-1.S)\n for (i <- 1 until numOfTests) {\n dut.io.din2.poke(i.S)\n dut.clock.step(1)\n }\n ////////////////////////////////////////////////////////////////\n // Test 5: SRA\n ////////////////////////////////////////////////////////////////\n dut.io.opConfig.poke(4.U)\n\n dut.io.din2.poke(1.S)\n for (i <- 1 until numOfTests) {\n dut.io.din1.poke(((i2)).S)\n dut.clock.step(1)\n }\n dut.io.din2.poke(2.S)\n for (i <- 1 until numOfTests) {\n dut.io.din1.poke((-(i2)).S)\n dut.clock.step(1)\n }\n ////////////////////////////////////////////////////////////////\n // Test 6: SRL \n ////////////////////////////////////////////////////////////////\n dut.io.opConfig.poke(5.U)\n\n for (i <- 1 until numOfTests) {\n dut.io.din1.poke((i2).S)\n dut.io.din2.poke(i.S)\n dut.clock.step(1)\n }\n\n", "right_context": "\n for (i <- 1 until numOfTests) {\n dut.io.din1.poke(i.S)\n dut.io.din2.poke((i+1).S)\n dut.clock.step(1)\n }\n ////////////////////////////////////////////////////////////////\n // Test 8: OR \n ////////////////////////////////////////////////////////////////\n dut.io.opConfig.poke(7.U)\n\n for (i <- 1 until numOfTests) {\n dut.io.din1.poke(i.S)\n dut.io.din2.poke((i+1).S)\n dut.clock.step(1)\n }\n ////////////////////////////////////////////////////////////////\n // Test 9: XOR \n ////////////////////////////////////////////////////////////////\n dut.io.opConfig.poke(8.U)\n\n for (i <- 1 until numOfTests) {\n dut.io.din1.poke(i.S)\n dut.io.din2.poke((i+1).S)\n dut.clock.step(1)\n } \n }\n } \n}", "groundtruth": " for (i <- 1 until numOfTests) {\n dut.io.din1.poke((-(i*2)).S)\n dut.io.din2.poke(i.S)\n dut.clock.step(1)\n }\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/CellProcessingTest.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ***************************************/\nimport chisel3._\nimport chiseltest._\nimport org.scalatest.flatspec.AnyFlatSpec\n\nclass CellProcessingTest extends AnyFlatSpec with ChiselScalatestTester {\n \"CellProcessingTest test\" should \"pass\" in {\n test(new CellProcessing(32)) { dut =>\n var northDin = 1.S \n var northDinValid = true.B \n var eastDin = 0.S \n var eastDinValid = false.B \n\n var southDin = 0.S \n var southDinValid = false.B \n var westDin = 2.S \n var westDinValid = true.B \n\n var northDoutReady = true.B \n var eastDoutReady = true.B \n var southDoutReady = true.B \n var westDoutReady = true.B \n \n println(\"*********************************\")\n println(\"Test 1: Summation\")\n println(\"*********************************\")\n var configBits = \"b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000010000000000000001000000000000000000000000011\".U \n \n dut.io.configBits.poke(configBits)\n dut.io.northDoutReady.poke(northDoutReady)\n dut.io.eastDoutReady.poke(eastDoutReady)\n\n dut.io.southDoutReady.poke(southDoutReady)\n dut.io.westDoutReady.poke(westDoutReady)\n dut.clock.step(1)\n dut.clock.step(1)\n\n dut.io.eastDin.poke(eastDin)\n", "right_context": " dut.clock.step(1)\n dut.io.northDin.poke(northDin)\n dut.io.northDinValid.poke(northDinValid)\n dut.io.westDin.poke(westDin)\n dut.io.westDinValid.poke(westDinValid)\n dut.clock.step(1)\n\n dut.io.northDin.poke(3.S)\n dut.io.westDin.poke(4.S)\n\n dut.clock.step(1)\n\n dut.io.northDin.poke(5.S)\n dut.io.westDin.poke(6.S)\n\n dut.clock.step(1)\n\n dut.io.northDin.poke(7.S)\n dut.io.westDin.poke(8.S)\n\n dut.clock.step(1)\n \n dut.io.northDin.poke(0.S)\n dut.io.northDinValid.poke(false.B)\n\n dut.io.westDin.poke(0.S)\n dut.io.westDinValid.poke(false.B)\n\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n\n // Outputs\n println(\"Outputs\")\n println(\"fuDin1Ready: \" + dut.io.fuDin1Ready.peek().toString)\n println(\"fuDin2Ready: \" + dut.io.fuDin2Ready.peek().toString)\n println(\"dout: \" + dut.io.dout.peek().toString)\n println(\"doutValid: \" + dut.io.doutValid.peek().toString)\n println(\"*********************************\")\n println(\"***********************************\")\n }\n } \n}\n", "groundtruth": " dut.io.eastDinValid.poke(eastDinValid)\n\n dut.io.southDin.poke(southDin)\n dut.io.southDinValid.poke(southDinValid)\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/ConfMuxTest.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ***************************************/\nimport chisel3._\nimport chiseltest._\nimport org.scalatest.flatspec.AnyFlatSpec\n\nclass ConfMuxTest extends AnyFlatSpec with ChiselScalatestTester {\n \"ConfMuxTest test\" should \"pass\" in {\n test(new ConfMux(2,2)) { dut =>\n // muxInput: 1011, selector: 1 ==> Mux Output: 10\n var selector = 1\n var muxInput = 11\n dut.io.selector.poke(selector.U)\n dut.io.muxInput.poke(muxInput.S)\n dut.clock.step(1)\n println(\"*********************************\")\n println(\"Mux Input: \" + dut.io.muxInput.peek().toString)\n println(\"Mux Selector: \" + dut.io.selector.peek().toString)\n println(\"Mux Output: \" + dut.io.muxOutput.peek().toString)\n println(\"*********************************\") \n", "right_context": " dut.clock.step(1)\n println(\"Mux Input: \" + dut.io.muxInput.peek().toString)\n println(\"Mux Selector: \" + dut.io.selector.peek().toString)\n println(\"Mux Output: \" + dut.io.muxOutput.peek().toString)\n println(\"***********************************\") \n dut.clock.step(1)\n }\n } \n}", "groundtruth": " dut.clock.step(1)\n selector = 2\n muxInput = 53\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/DEbTest.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ****************************************/\nimport chisel3._\nimport chiseltest._\nimport org.scalatest.flatspec.AnyFlatSpec\n\nclass DEbTest extends AnyFlatSpec with ChiselScalatestTester {\n \"DEbTest test\" should \"pass\" in {\n test(new DEb(32)) { dut =>\n var din = 0.S \n var doutReady = false.B \n var dinValid = false.B \n dut.io.din.poke(din)\n dut.io.dinValid.poke(dinValid)\n dut.io.doutReady.poke(doutReady)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.io.din.poke(1.S)\n dut.io.dinValid.poke(true.B)\n dut.io.doutReady.poke(true.B)\n dut.clock.step(1)\n dut.io.din.poke(2.S)\n dut.clock.step(1)\n dut.io.din.poke(3.S)\n dut.clock.step(1)\n dut.io.din.poke(4.S)\n dut.clock.step(1)\n dut.io.din.poke(5.S)\n dut.clock.step(1)\n dut.io.din.poke(6.S)\n dut.clock.step(1)\n dut.io.din.poke(7.S)\n dut.clock.step(1)\n dut.io.din.poke(0.S)\n dut.io.dinValid.poke(false.B)\n \n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n \n\n /\n ////////////////////////////////////////////////////////////////\n // Test 1 \n ////////////////////////////////////////////////////////////////\n println(\"***********************************\")\n println(\"Test 1: Vp: false, An: false\")\n println(\"*********************************\")\n println(\"*********************************\")\n println(\"*********************************\")\n println(\"Dp: \" + dut.io.din.peek().toString)\n println(\"Vp: \" + dut.io.dinValid.peek().toString)\n println(\"An: \" + dut.io.doutReady.peek().toString)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Dn: \" + dut.io.dout.peek().toString)\n println(\"Vn: \" + dut.io.doutValid.peek().toString)\n println(\"Ap: \" + dut.io.dinReady.peek().toString)\n println(\"*********************************\")\n println(\"*********************************\")\n ////////////////////////////////////////////////////////////////\n // Test 2 \n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 2: Vp: false, An: true\")\n println(\"*********************************\")\n dinValid = false.B \n doutReady = true.B \n dut.io.dinValid.poke(dinValid)\n dut.io.doutReady.poke(doutReady)\n println(\"Vp: \" + dut.io.dinValid.peek().toString)\n println(\"An: \" + dut.io.doutReady.peek().toString)\n dut.clock.step(1)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Dn: \" + dut.io.dout.peek().toString)\n println(\"Vn: \" + dut.io.doutValid.peek().toString)\n println(\"Ap: \" + dut.io.dinReady.peek().toString)\n println(\"*********************************\")\n println(\"*********************************\")\n ////////////////////////////////////////////////////////////////\n // Test 3 \n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 3: Vp: true, An: false\")\n println(\"*********************************\")\n dinValid = true.B \n doutReady = false.B \n dut.io.dinValid.poke(dinValid)\n dut.io.doutReady.poke(doutReady)\n println(\"Vp: \" + dut.io.dinValid.peek().toString)\n", "right_context": " println(\"Ap: \" + dut.io.dinReady.peek().toString)\n println(\"*********************************\")\n println(\"*********************************\") \n ////////////////////////////////////////////////////////////////\n // Test 4 \n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 4: Vp: true, An: true\")\n println(\"*********************************\")\n dinValid = true.B \n doutReady = true.B \n dut.io.dinValid.poke(dinValid)\n dut.io.doutReady.poke(doutReady)\n println(\"Vp: \" + dut.io.dinValid.peek().toString)\n println(\"An: \" + dut.io.doutReady.peek().toString)\n dut.clock.step(1)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Dn: \" + dut.io.dout.peek().toString)\n println(\"Vn: \" + dut.io.doutValid.peek().toString)\n println(\"Ap: \" + dut.io.dinReady.peek().toString)\n println(\"*********************************\")\n println(\"**********************************\") \n /\n }\n } \n}\n", "groundtruth": " println(\"An: \" + dut.io.doutReady.peek().toString)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.io.dinValid.poke(false.B)\n dut.clock.step(1)\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/DFifoTest.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n *****************************************/\nimport chisel3._\nimport chiseltest._\nimport org.scalatest.flatspec.AnyFlatSpec\nimport chisel3.stage.PrintFullStackTraceAnnotation\n\nclass DFifoTest extends AnyFlatSpec with ChiselScalatestTester {\n \"DFifoTest test\" should \"pass\" in {\n test(new DFifo(32, 32)).withAnnotations(Seq(VerilatorBackendAnnotation, WriteVcdAnnotation)) { dut =>\n \n //dut.io.din.poke(0.U)\n dut.io.doutReady.poke(true.B)\n dut.io.dinValid.poke(false.B)\n\n dut.clock.step(1)\n\n for (i <- 0 to 15) {\n", "right_context": " dut.io.dinValid.poke(false.B)\n dut.clock.step(10)\n }\n \n dut.clock.step(10)\n }\n } \n}\n", "groundtruth": " dut.io.din.poke(i.S) \n dut.io.dinValid.poke(true.B)\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/DRegTest.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ***************************************/\nimport chisel3._\nimport chiseltest._\nimport org.scalatest.flatspec.AnyFlatSpec\n\nclass DRegTest extends AnyFlatSpec with ChiselScalatestTester {\n \"DRegTest test\" should \"pass\" in {\n test(new DReg(8)) { dut =>\n var din = 10.S \n", "right_context": " dut.io.doutReady.poke(doutReady)\n dut.io.dinValid.poke(dinValid)\n ////////////////////////////////////////////////////////////////\n // Test 1 \n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 1: Vp: false, An: false\")\n println(\"*********************************\")\n println(\"Dp: \" + dut.io.din.peek().toString)\n println(\"*********************************\")\n println(\"*********************************\")\n println(\"Vp: \" + dut.io.dinValid.peek().toString)\n println(\"An: \" + dut.io.doutReady.peek().toString)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Dn: \" + dut.io.dout.peek().toString)\n println(\"Vn: \" + dut.io.doutValid.peek().toString)\n println(\"Ap: \" + dut.io.dinReady.peek().toString)\n ////////////////////////////////////////////////////////////////\n // Test 2\n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 2: Vp: true, An: true\")\n println(\"*********************************\")\n doutReady = true.B \n dinValid = true.B \n dut.io.doutReady.poke(doutReady)\n dut.io.dinValid.poke(dinValid)\n println(\"Vp: \" + dut.io.dinValid.peek().toString)\n println(\"An: \" + dut.io.doutReady.peek().toString)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Dn: \" + dut.io.dout.peek().toString)\n println(\"Vn: \" + dut.io.doutValid.peek().toString)\n println(\"Ap: \" + dut.io.dinReady.peek().toString)\n println(\"*********************************\")\n println(\"***********************************\")\n }\n } \n}\n", "groundtruth": " var doutReady = false.B\n var dinValid = false.B \n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/FrTest.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ***************************************/\nimport chisel3._\nimport chiseltest._\nimport org.scalatest.flatspec.AnyFlatSpec\n\nclass FrTest extends AnyFlatSpec with ChiselScalatestTester {\n \"FrTest test\" should \"pass\" in {\n test(new Fr(5,5)) { dut =>\n", "right_context": " dut.io.forkMask.poke(forkMask)\n println(\"*********************************\")\n println(\"*********************************\")\n println(\"Valid In: \" + dut.io.validIn.peek().toString)\n println(\"Ready Out: \" + dut.io.readyOut.peek().toString)\n println(\"Valid Mux Sel: \" + dut.io.validMuxSel.peek().toString)\n println(\"Fork Mask: \" + dut.io.forkMask.peek().toString)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Valid Out: \" + dut.io.validOut.peek().toString)\n validMuxSel = \"b1\".U \n dut.io.validMuxSel.poke(validMuxSel)\n println(\"*********************************\")\n println(\"*********************************\")\n println(\"Valid In: \" + dut.io.validIn.peek().toString)\n println(\"Ready Out: \" + dut.io.readyOut.peek().toString)\n println(\"Valid Mux Sel: \" + dut.io.validMuxSel.peek().toString)\n println(\"Fork Mask: \" + dut.io.forkMask.peek().toString)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Valid Out: \" + dut.io.validOut.peek().toString)\n println(\"*********************************\")\n println(\"***********************************\")\n }\n } \n}\n", "groundtruth": " \n var validIn = \"b11011\".U \n var readyOut = \"b11011\".U \n var validMuxSel = \"b10\".U \n var forkMask = \"b11011\".U \n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/FsTest.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ***************************************/\nimport chisel3._\nimport chiseltest._\nimport org.scalatest.flatspec.AnyFlatSpec\n\nclass FsTest extends AnyFlatSpec with ChiselScalatestTester {\n \"FsTest test\" should \"pass\" in {\n test(new Fs(5)) { dut =>\n", "right_context": " \n dut.io.readyOut.poke(\"b11111\".U)\n dut.io.forkMask.poke(\"b11000\".U)\n\n dut.clock.step(1)\n println(\"*********************************\")\n println(\"*********************************\")\n println(\"Ready Out: \" + dut.io.readyOut.peek().toString)\n println(\"Fork Mask: \" + dut.io.forkMask.peek().toString)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Ready In: \" + dut.io.readyIn.peek().toString)\n println(\"*********************************\")\n println(\"***********************************\")\n }\n } \n}\n", "groundtruth": " \n dut.io.readyOut.poke(\"b00000\".U)\n dut.io.forkMask.poke(\"b00000\".U)\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/FuTest.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ***************************************/\nimport chisel3._\nimport chiseltest._\nimport org.scalatest.flatspec.AnyFlatSpec\n\nclass FuTest extends AnyFlatSpec with ChiselScalatestTester {\n \"FuTest test\" should \"pass\" in {\n test(new Fu(32, 5)) { dut =>\n var din1 = 8.S\n var din2 = 3.S\n var opConfig = 0.U \n var dinValid = true.B\n var doutReady = true.B\n var loopSource = 0.U \n var iterationsReset = 0.U \n ////////////////////////////////////////////////////////////////\n // Test 1 \n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 1: Loop source: 0, Iterations Reset: 0\")\n println(\"*********************************\")\n dut.io.din1.poke(din1)\n dut.io.din2.poke(din2)\n dut.io.opConfig.poke(opConfig)\n dut.io.dinValid.poke(dinValid)\n dut.io.doutReady.poke(doutReady)\n dut.io.loopSource.poke(loopSource)\n dut.io.iterationsReset.poke(iterationsReset)\n println(\"*********************************\")\n println(\"*********************************\")\n println(\"Din1: \" + dut.io.din1.peek().toString)\n println(\"Din2: \" + dut.io.din2.peek().toString)\n println(\"VIn: \" + dut.io.dinValid.peek().toString)\n println(\"ROut: \" + dut.io.doutReady.peek().toString)\n println(\"Loop Source: \" + dut.io.loopSource.peek().toString)\n println(\"Iterarions Reset: \" + dut.io.iterationsReset.peek().toString)\n println(\"Op Config: \" + dut.io.opConfig.peek().toString)\n // Summation \n dut.clock.step(1)\n println(\"*********************************\")\n println(\"Summation: \" + dut.io.dout.peek().toString)\n opConfig = 1.U \n dut.io.opConfig.poke(opConfig)\n dut.clock.step(1)\n println(\"Multiplication: \" + dut.io.dout.peek().toString)\n opConfig = 2.U \n dut.io.opConfig.poke(opConfig)\n dut.clock.step(1)\n println(\"Subtraction: \" + dut.io.dout.peek().toString)\n opConfig = 3.U \n dut.io.opConfig.poke(opConfig)\n dut.clock.step(1)\n println(\"Shift Left Logical: \" + dut.io.dout.peek().toString)\n opConfig = 4.U \n dut.io.opConfig.poke(opConfig)\n dut.clock.step(1)\n println(\"Shift Right Arithmetic: \" + dut.io.dout.peek().toString)\n opConfig = 5.U \n dut.io.opConfig.poke(opConfig)\n dut.clock.step(1)\n println(\"Shift Right Logical: \" + dut.io.dout.peek().toString)\n opConfig = 6.U \n dut.io.opConfig.poke(opConfig)\n dut.clock.step(1)\n println(\"And: \" + dut.io.dout.peek().toString)\n opConfig = 7.U \n dut.io.opConfig.poke(opConfig)\n dut.clock.step(1)\n println(\"Or: \" + dut.io.dout.peek().toString)\n opConfig = 8.U \n dut.io.opConfig.poke(opConfig)\n dut.clock.step(1)\n println(\"Xor: \" + dut.io.dout.peek().toString)\n opConfig = 10.U \n dut.io.opConfig.poke(opConfig)\n dut.clock.step(1)\n dut.io.dinValid.poke(false.B)\n dut.clock.step(1)\n dut.clock.step(1)\n ////////////////////////////////////////////////////////////////\n // Test 2\n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 2: Loop source: 1, Iterations Reset: 3\")\n println(\"*********************************\")\n // dinValid: true\n // doutReady: true\n din1 = 1.S\n din2 = 1.S\n opConfig = 0.U \n loopSource = 1.U \n iterationsReset = 3.U \n dut.io.dinValid.poke(true.B)\n dut.io.din1.poke(din1)\n dut.io.din2.poke(din2)\n dut.io.opConfig.poke(0.U)\n dut.io.loopSource.poke(loopSource)\n dut.io.iterationsReset.poke(iterationsReset)\n dut.clock.step(1)\n println(\"*********************************\")\n println(\"Summation: \" + dut.io.dout.peek().toString)\n dut.clock.step(1)\n println(\"*********************************\")\n println(\"Summation: \" + dut.io.dout.peek().toString)\n dut.clock.step(1)\n println(\"*********************************\")\n println(\"Summation: \" + dut.io.dout.peek().toString)\n dut.clock.step(1)\n println(\"*********************************\")\n println(\"Summation: \" + dut.io.dout.peek().toString)\n dut.clock.step(1)\n println(\"*********************************\")\n println(\"Summation: \" + dut.io.dout.peek().toString)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n ////////////////////////////////////////////////////////////////\n // Test 3\n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 3: Loop source: 1, Iterations Reset: 3\")\n println(\"*********************************\")\n // dinValid: true\n // doutReady: true\n din1 = 8.S\n din2 = 1.S\n loopSource = 1.U \n iterationsReset = 3.U \n dut.io.din1.poke(din1)\n dut.io.din2.poke(din2)\n dut.io.opConfig.poke(3.U)\n dut.io.loopSource.poke(loopSource)\n dut.io.iterationsReset.poke(iterationsReset)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n ////////////////////////////////////////////////////////////////\n // Test 4\n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 4: Loop source: 0, Iterations Reset: 5\")\n println(\"*********************************\")\n // dinValid: true\n // doutReady: true\n din1 = 3.S\n din2 = 4.S\n opConfig = 0.U \n loopSource = 0.U \n iterationsReset = 5.U \n dut.io.din1.poke(din1)\n dut.io.din2.poke(din2)\n dut.io.opConfig.poke(opConfig)\n dut.io.loopSource.poke(loopSource)\n dut.io.iterationsReset.poke(iterationsReset)\n dut.clock.step(1)\n ////////////////////////////////////////////////////////////////\n // Test 5\n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 5: dinValid: 0, doutReady: 0\")\n println(\"*********************************\")\n // Loop source: 0\n // Iterations Reset: 0\n din1 = 1.S\n din2 = 2.S\n dinValid = false.B\n doutReady = false.B\n opConfig = 0.U \n loopSource = 0.U \n iterationsReset = 0.U \n dut.io.din1.poke(din1)\n dut.io.din2.poke(din2)\n dut.io.dinValid.poke(dinValid)\n dut.io.doutReady.poke(doutReady)\n dut.io.opConfig.poke(opConfig)\n dut.io.loopSource.poke(loopSource)\n dut.io.iterationsReset.poke(iterationsReset)\n dut.clock.step(1)\n ////////////////////////////////////////////////////////////////\n // Test 6\n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 5: dinValid: 0, doutReady: 1\")\n println(\"*********************************\")\n // Loop source: 0\n // Iterations Reset: 0\n din1 = 2.S\n din2 = 3.S\n dinValid = false.B\n doutReady = true.B\n opConfig = 0.U \n loopSource = 0.U \n iterationsReset = 0.U \n dut.io.din1.poke(din1)\n dut.io.din2.poke(din2)\n dut.io.dinValid.poke(dinValid)\n dut.io.doutReady.poke(doutReady)\n dut.io.opConfig.poke(opConfig)\n dut.io.loopSource.poke(loopSource)\n dut.io.iterationsReset.poke(iterationsReset)\n dut.clock.step(1)\n ////////////////////////////////////////////////////////////////\n // Test 7\n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 5: dinValid: 1, doutReady: 0\")\n println(\"*********************************\")\n // Loop source: 0\n // Iterations Reset: 0\n din1 = 3.S\n din2 = 4.S\n dinValid = true.B\n doutReady = false.B\n opConfig = 0.U \n loopSource = 0.U \n iterationsReset = 0.U \n dut.io.din1.poke(din1)\n dut.io.din2.poke(din2)\n", "right_context": " dut.io.doutReady.poke(doutReady)\n dut.io.opConfig.poke(opConfig)\n dut.io.loopSource.poke(loopSource)\n dut.io.iterationsReset.poke(iterationsReset)\n dut.clock.step(1)\n ////////////////////////////////////////////////////////////////\n // Test 8\n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Multiple inputs (din1 and din2)\")\n println(\"*********************************\")\n // dinValid: true\n // doutReady: true\n // Loop source: 0\n // Iterations Reset: 0\n din1 = 1.S\n din2 = 2.S\n dinValid = true.B\n doutReady = true.B\n opConfig = 0.U \n loopSource = 0.U \n iterationsReset = 0.U \n dut.io.din1.poke(din1)\n dut.io.din2.poke(din2)\n dut.io.dinValid.poke(dinValid)\n dut.io.doutReady.poke(doutReady)\n dut.io.opConfig.poke(opConfig)\n dut.io.loopSource.poke(loopSource)\n dut.io.iterationsReset.poke(iterationsReset)\n println(\"Din1: \" + dut.io.din1.peek().toString)\n println(\"Din2: \" + dut.io.din2.peek().toString)\n dut.clock.step(1)\n println(\"*********************************\")\n println(\"Summation: \" + dut.io.dout.peek().toString)\n din1 = 2.S\n din2 = 3.S\n dut.io.din1.poke(din1)\n dut.io.din2.poke(din2)\n println(\"Din1: \" + dut.io.din1.peek().toString)\n println(\"Din2: \" + dut.io.din2.peek().toString)\n dut.clock.step(1)\n println(\"*********************************\")\n println(\"Summation: \" + dut.io.dout.peek().toString)\n din1 = 3.S\n din2 = 4.S\n dut.io.din1.poke(din1)\n dut.io.din2.poke(din2)\n println(\"Din1: \" + dut.io.din1.peek().toString)\n println(\"Din2: \" + dut.io.din2.peek().toString)\n dut.clock.step(1)\n println(\"*********************************\")\n println(\"Summation: \" + dut.io.dout.peek().toString)\n din1 = 4.S\n din2 = 5.S\n dut.io.din1.poke(din1)\n dut.io.din2.poke(din2)\n println(\"Din1: \" + dut.io.din1.peek().toString)\n println(\"Din2: \" + dut.io.din2.peek().toString)\n dut.clock.step(1)\n println(\"*********************************\")\n println(\"Summation: \" + dut.io.dout.peek().toString)\n din1 = 5.S\n din2 = 6.S\n dut.io.din1.poke(din1)\n dut.io.din2.poke(din2)\n println(\"Din1: \" + dut.io.din1.peek().toString)\n println(\"Din2: \" + dut.io.din2.peek().toString)\n dut.clock.step(1)\n println(\"*********************************\")\n println(\"Summation: \" + dut.io.dout.peek().toString)\n din1 = 6.S\n din2 = 7.S\n dut.io.din1.poke(din1)\n dut.io.din2.poke(din2)\n println(\"Din1: \" + dut.io.din1.peek().toString)\n println(\"Din2: \" + dut.io.din2.peek().toString)\n dut.clock.step(1)\n println(\"***********************************\")\n println(\"Summation: \" + dut.io.dout.peek().toString)\n }\n } \n}\n", "groundtruth": " dut.io.dinValid.poke(dinValid)\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/JoinTest.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ***************************************/\nimport chisel3._\nimport chiseltest._\nimport org.scalatest.flatspec.AnyFlatSpec\n\nclass JoinTest extends AnyFlatSpec with ChiselScalatestTester {\n \"JoinTest test\" should \"pass\" in { \n test(new Join(32)) { dut =>\n var din1 = 10.S\n var din2 = 5.S\n var din1Valid = false.B\n var din2Valid = false.B \n var doutReady = false.B\n dut.io.din1.poke(din1)\n dut.io.din2.poke(din2)\n dut.io.din1Valid.poke(din1Valid)\n dut.io.din2Valid.poke(din2Valid)\n dut.io.doutReady.poke(doutReady)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n ////////////////////////////////////////////////////////////////\n // Test 1 \n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 1: Vin1: false, Vin2: false, Aout: false\")\n println(\"*********************************\")\n println(\"Din1: \" + dut.io.dout1.peek().toString)\n println(\"Din2: \" + dut.io.dout2.peek().toString)\n println(\"*********************************\")\n println(\"*********************************\")\n println(\"Vin1: \" + dut.io.din1Valid.peek().toString)\n println(\"Vin2: \" + dut.io.din2Valid.peek().toString)\n println(\"Aout: \" + dut.io.doutReady.peek().toString)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Ain1: \" + dut.io.din1Ready.peek().toString)\n println(\"Ain2: \" + dut.io.din2Ready.peek().toString)\n println(\"Dout1: \" + dut.io.dout1.peek().toString)\n println(\"Dout2: \" + dut.io.dout2.peek().toString)\n println(\"Vout: \" + dut.io.doutValid.peek().toString)\n println(\"*********************************\")\n println(\"*********************************\")\n ////////////////////////////////////////////////////////////////\n // Test 2\n ////////////////////////////////////////////////////////////////\n", "right_context": " println(\"Aout: \" + dut.io.doutReady.peek().toString)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Ain1: \" + dut.io.din1Ready.peek().toString)\n println(\"Ain2: \" + dut.io.din2Ready.peek().toString)\n println(\"Vout: \" + dut.io.doutValid.peek().toString)\n println(\"*********************************\")\n println(\"*********************************\")\n ////////////////////////////////////////////////////////////////\n // Test 3 \n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 3: Vin1: false, Vin2: true, Aout: false\")\n println(\"*********************************\")\n din1Valid = false.B\n din2Valid = true.B \n doutReady = false.B\n dut.io.din1Valid.poke(din1Valid)\n dut.io.din2Valid.poke(din2Valid)\n println(\"Vin1: \" + dut.io.din1Valid.peek().toString)\n println(\"Vin2: \" + dut.io.din2Valid.peek().toString)\n println(\"Aout: \" + dut.io.doutReady.peek().toString)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Ain1: \" + dut.io.din1Ready.peek().toString)\n println(\"Ain2: \" + dut.io.din2Ready.peek().toString)\n println(\"Vout: \" + dut.io.doutValid.peek().toString)\n println(\"*********************************\")\n println(\"*********************************\")\n ////////////////////////////////////////////////////////////////\n // Test 4 \n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 4: Vin1: true, Vin2: true, Aout: false\")\n println(\"*********************************\")\n din1Valid = true.B\n din2Valid = true.B \n doutReady = false.B\n dut.io.din1Valid.poke(din1Valid)\n dut.io.din2Valid.poke(din2Valid)\n dut.io.doutReady.poke(doutReady)\n println(\"Vin1: \" + dut.io.din1Valid.peek().toString)\n println(\"Vin2: \" + dut.io.din2Valid.peek().toString)\n println(\"Aout: \" + dut.io.doutReady.peek().toString)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Ain1: \" + dut.io.din1Ready.peek().toString)\n println(\"Ain2: \" + dut.io.din2Ready.peek().toString)\n println(\"Vout: \" + dut.io.doutValid.peek().toString)\n println(\"*********************************\")\n println(\"*********************************\")\n ////////////////////////////////////////////////////////////////\n // Test 5 \n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 5: Vin1: false, Vin2: false, Aout: true\")\n println(\"*********************************\")\n din1Valid = false.B\n din2Valid = false.B \n doutReady = true.B\n dut.io.din1Valid.poke(din1Valid)\n dut.io.din2Valid.poke(din2Valid)\n dut.io.doutReady.poke(doutReady)\n println(\"Vin1: \" + dut.io.din1Valid.peek().toString)\n println(\"Vin2: \" + dut.io.din2Valid.peek().toString)\n println(\"Aout: \" + dut.io.doutReady.peek().toString)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Ain1: \" + dut.io.din1Ready.peek().toString)\n println(\"Ain2: \" + dut.io.din2Ready.peek().toString)\n println(\"Vout: \" + dut.io.doutValid.peek().toString)\n println(\"*********************************\")\n println(\"*********************************\")\n ////////////////////////////////////////////////////////////////\n // Test 6 \n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 6: Vin1: true, Vin2: false, Aout: true\")\n println(\"*********************************\")\n din1Valid = true.B\n din2Valid = false.B \n doutReady = true.B\n dut.io.din1Valid.poke(din1Valid)\n dut.io.din2Valid.poke(din2Valid)\n dut.io.doutReady.poke(doutReady)\n println(\"Vin1: \" + dut.io.din1Valid.peek().toString)\n println(\"Vin2: \" + dut.io.din2Valid.peek().toString)\n println(\"Aout: \" + dut.io.doutReady.peek().toString)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Ain1: \" + dut.io.din1Ready.peek().toString)\n println(\"Ain2: \" + dut.io.din2Ready.peek().toString)\n println(\"Vout: \" + dut.io.doutValid.peek().toString)\n println(\"*********************************\")\n println(\"*********************************\")\n ////////////////////////////////////////////////////////////////\n // Test 7\n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 7: Vin1: false, Vin2: true, Aout: true\")\n println(\"*********************************\")\n din1Valid = false.B\n din2Valid = true.B \n doutReady = true.B\n dut.io.din1Valid.poke(din1Valid)\n dut.io.din2Valid.poke(din2Valid)\n dut.io.doutReady.poke(doutReady)\n println(\"Vin1: \" + dut.io.din1Valid.peek().toString)\n println(\"Vin2: \" + dut.io.din2Valid.peek().toString)\n println(\"Aout: \" + dut.io.doutReady.peek().toString)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Ain1: \" + dut.io.din1Ready.peek().toString)\n println(\"Ain2: \" + dut.io.din2Ready.peek().toString)\n println(\"Vout: \" + dut.io.doutValid.peek().toString)\n println(\"*********************************\")\n println(\"*********************************\")\n ////////////////////////////////////////////////////////////////\n // Test 8\n ////////////////////////////////////////////////////////////////\n println(\"*********************************\")\n println(\"Test 8: Vin1: true, Vin2: true, Aout: true\")\n println(\"*********************************\")\n din1Valid = true.B\n din2Valid = true.B \n doutReady = true.B\n dut.io.din1Valid.poke(din1Valid)\n dut.io.din2Valid.poke(din2Valid)\n dut.io.doutReady.poke(doutReady)\n println(\"Vin1: \" + dut.io.din1Valid.peek().toString)\n println(\"Vin2: \" + dut.io.din2Valid.peek().toString)\n println(\"Aout: \" + dut.io.doutReady.peek().toString)\n dut.clock.step(1)\n println(\"--------------------------------------\")\n println(\"Ain1: \" + dut.io.din1Ready.peek().toString)\n println(\"Ain2: \" + dut.io.din2Ready.peek().toString)\n println(\"Vout: \" + dut.io.doutValid.peek().toString)\n println(\"*********************************\")\n println(\"*********************************\")\n }\n } \n}\n", "groundtruth": " println(\"*********************************\")\n println(\"Test 1: Vin1: true, Vin2: false, Aout: false\")\n println(\"***********************************\")\n din1Valid = true.B\n din2Valid = false.B \n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/OverlayRoccTestACC.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ****************************************/\nimport chisel3._\nimport chiseltest._\nimport chisel3.util._\nimport org.scalatest.flatspec.AnyFlatSpec\nimport scala.io.Source\n\nclass OverlayRoccTestACC extends AnyFlatSpec with ChiselScalatestTester {\n \"OverlayRoccTestACC test\" should \"pass\" in {\n test(new OverlayRocc(32, 6, 6, 32)).withAnnotations(Seq(VerilatorBackendAnnotation, WriteVcdAnnotation)) { dut =>\n ///////////////////////////////////////////\n // Accumulate\n ///////////////////////////////////////////\n \n var dataInValid = \"b000000\".U \n var dataOutReady = \"b111111\".U \n dut.io.dataInValid.poke(dataInValid)\n", "right_context": " dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n }\n source.close()\n \n ///////////////////////////////////////////\n // Test 1: c = 2i \n // x = Σc (n = 4) + 1\n ///////////////////////////////////////////\n /\n val din1 = BigInt(\"00000000\" + \"00000001\" + \"00000002\"+ \"00000000\" + \"00000000\" + \"00000000\" ,16).S\n dut.io.dataIn.poke(din1)\n dut.io.dataInValid.poke(\"b011000\".U)\n dut.clock.step(30)\n dut.io.dataInValid.poke(\"b000000\".U)\n \n\n for (i <- 1 to 16) {\n // ------------------------------------------------------------------------------------------------\n // \| \| C5 \| C4 \| C3 \| C2 \| C1 \| C0 \|\n // ------------------------------------------------------------------------------------------------\n // ------------------------------------------------------------------------------------------------\n // \| \| a \| x \| c \| - \| - \| b \|\n // ------------------------------------------------------------------------------------------------\n val din2 = BigInt(\"00000000\" + \"00000000\" + \"00000000\"+ \"00000000\" + \"00000000\" + f\"$i%08X\" ,16).S\n dut.io.dataIn.poke(din2)\n dut.io.dataInValid.poke(\"b100001\".U)\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n }\n */\n\n ///////////////////////////////////////////\n // Test 2: c = 2(i+1) \n // x = Σc (n = 5) + 2 \n ///////////////////////////////////////////\n \n val din1 = BigInt(\"00000000\" + \"00000002\" + \"00000002\"+ \"00000000\" + \"00000000\" + \"00000000\" ,16).S\n dut.io.dataIn.poke(din1)\n dut.io.dataInValid.poke(\"b011000\".U)\n dut.clock.step(30)\n dut.io.dataInValid.poke(\"b000000\".U)\n \n\n for (i <- 1 to 16) {\n // ------------------------------------------------------------------------------------------------\n // \| \| C5 \| C4 \| C3 \| C2 \| C1 \| C0 \|\n // ------------------------------------------------------------------------------------------------\n // ------------------------------------------------------------------------------------------------\n // \| \| a \| x \| c \| - \| - \| b \|\n // ------------------------------------------------------------------------------------------------\n val din2 = BigInt((i).formatted(\"%08X\") + \"00000000\" + \"00000000\"+ \"00000000\" + \"00000000\" + \"00000001\" ,16).S\n dut.io.dataIn.poke(din2)\n dut.io.dataInValid.poke(\"b100001\".U)\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n }\n \n // Finish \n for( i <- 0 to 150){\n dut.clock.step(1)\n } \n println(\"End of the simulation\") \n }\n } \n}", "groundtruth": " dut.io.dataOutReady.poke(dataOutReady)\n dut.clock.step(1)\n\n var cellConfig: UInt = 0.U \n \n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/OverlayRoccTestCAP.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n *****************************************/\nimport chisel3._\nimport chiseltest._\nimport chisel3.util._\nimport org.scalatest.flatspec.AnyFlatSpec\nimport scala.io.Source\n\nclass OverlayRoccTestCAP extends AnyFlatSpec with ChiselScalatestTester {\n \"OverlayRoccCAP test\" should \"pass\" in {\n test(new OverlayRocc(32, 6, 6, 32)).withAnnotations(Seq(VerilatorBackendAnnotation, WriteVcdAnnotation)) { dut =>\n ///////////////////////////////////////////\n // CAP\n ///////////////////////////////////////////\n\n var dataInValid = \"b000000\".U \n var dataOutReady = \"b111111\".U \n dut.io.dataInValid.poke(dataInValid)\n dut.io.dataOutReady.poke(dataOutReady)\n dut.clock.step(1)\n\n var cellConfig: UInt = 0.U \n \n val source = Source.fromFile(\"src/test/scala/Bitstreams/cap.txt\")\n for (line <- source.getLines()){\n \n cellConfig = (\"b\" + line).U \n dut.io.cellConfig.poke(cellConfig)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n }\n source.close()\n\n ///////////////////////////////////////////\n // Test 1: int a [SIZE]= {2, 4, 8, 16,32};\n // int b [SIZE]= {1, 2, 3, 4, 5};\n ///////////////////////////////////////////\n var din = BigInt(\"00000001\" + \"00000000000000000000000000000000\" + \"00000002\" ,16).S \n dut.io.dataIn.poke(din)\n dut.io.dataInValid.poke(\"b100001\".U)\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n\n din = BigInt(\"00000002\" + \"00000000000000000000000000000000\" + \"00000004\" ,16).S \n dut.io.dataIn.poke(din)\n dut.io.dataInValid.poke(\"b100001\".U)\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n\n din = BigInt(\"00000003\" + \"00000000000000000000000000000000\" + \"00000008\" ,16).S \n dut.io.dataIn.poke(din)\n dut.io.dataInValid.poke(\"b100001\".U)\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n\n din = BigInt(\"00000004\" + \"00000000000000000000000000000000\" + \"00000010\" ,16).S \n dut.io.dataIn.poke(din)\n dut.io.dataInValid.poke(\"b100001\".U)\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n\n din = BigInt(\"00000005\" + \"00000000000000000000000000000000\" + \"00000020\" ,16).S \n dut.io.dataIn.poke(din)\n dut.io.dataInValid.poke(\"b100001\".U)\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n ///////////////////////////////////////////\n // Test 2: int a [SIZE]= {1, 2, 3, 4, 5};\n // int b [SIZE]= {1, 2, 3, 4, 5};\n ///////////////////////////////////////////\n din = BigInt(\"00000001\" + \"00000000000000000000000000000000\" + \"00000001\" ,16).S \n dut.io.dataIn.poke(din)\n", "right_context": " dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n\n din = BigInt(\"00000002\" + \"00000000000000000000000000000000\" + \"00000002\" ,16).S \n dut.io.dataIn.poke(din)\n<TARGET>\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n\n din = BigInt(\"00000003\" + \"00000000000000000000000000000000\" + \"00000003\" ,16).S \n dut.io.dataIn.poke(din)\n dut.io.dataInValid.poke(\"b100001\".U)\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n\n din = BigInt(\"00000004\" + \"00000000000000000000000000000000\" + \"00000004\" ,16).S \n dut.io.dataIn.poke(din)\n dut.io.dataInValid.poke(\"b100001\".U)\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n\n din = BigInt(\"00000005\" + \"00000000000000000000000000000000\" + \"00000005\" ,16).S \n dut.io.dataIn.poke(din)\n dut.io.dataInValid.poke(\"b100001\".U)\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n\n // Finish \n for( i <- 0 to 10){\n dut.clock.step(1)\n } \n println(\"End of the simulation\") \n }\n } \n}\n", "groundtruth": " dut.io.dataInValid.poke(\"b100001\".U)\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/OverlayRoccTestMAC.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ****************************************/\nimport chisel3._\nimport chiseltest._\nimport chisel3.util._\nimport org.scalatest.flatspec.AnyFlatSpec\nimport scala.io.Source\n\nclass OverlayRoccTestMAC extends AnyFlatSpec with ChiselScalatestTester {\n \"OverlayRoccTestMAC test\" should \"pass\" in {\n test(new OverlayRocc(32, 6, 6, 32)).withAnnotations(Seq(VerilatorBackendAnnotation, WriteVcdAnnotation)) { dut => \n ///////////////////////////////////////////\n // MAC\n ///////////////////////////////////////////\n\n var dataInValid = \"b000000\".U \n var dataOutReady = \"b111111\".U \n dut.io.dataInValid.poke(dataInValid)\n dut.io.dataOutReady.poke(dataOutReady)\n dut.clock.step(1)\n\n var cellConfig: UInt = 0.U \n \n val source = Source.fromFile(\"src/test/scala/Bitstreams/mac.txt\")\n for (line <- source.getLines()){\n \n cellConfig = (\"b\" + line).U \n dut.io.cellConfig.poke(cellConfig)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n }\n source.close()\n \n ///////////////////////////////////////////\n // Test 1: a = 2\n // b = i\n // x = Σc (n = 4) + 0\n ///////////////////////////////////////////\n /\n for (i <- 1 to 101) {\n val c4 = i.toString()\n val c5 = i.toString()\n \n val din = BigInt(\"00000000\" + f\"$i%08X\" + \"00000002\"+ \"00000000\" + \"00000000\" + \"00000000\" ,16).S\n \n dut.io.dataIn.poke(din)\n dut.io.dataInValid.poke(\"b111000\".U)\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n }\n */\n ///////////////////////////////////////////\n // Test 2: a = i\n // b = i\n // x = Σc (n = 5) + 3\n ///////////////////////////////////////////\n\n", "right_context": " // ------------------------------------------------------------------------------------------------\n // ------------------------------------------------------------------------------------------------\n // \| \| x \| b \| a \| - \| - \| - \|\n // ------------------------------------------------------------------------------------------------\n val din = BigInt(\"00000003\" + (i).formatted(\"%08X\") + (i).formatted(\"%08X\") + \"00000000\" + \"00000000\" + \"00000000\" ,16).S\n dut.io.dataIn.poke(din)\n dut.io.dataInValid.poke(\"b111000\".U)\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n }\n // Finish \n for( i <- 0 to 10){\n dut.clock.step(1)\n } \n println(\"End of the simulation\") \n }\n } \n}\n", "groundtruth": " for (i <- 1 to 101) {\n // ------------------------------------------------------------------------------------------------\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/OverlayRoccTestMAC2.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ****************************************/\nimport chisel3._\nimport chiseltest._\nimport chisel3.util._\nimport org.scalatest.flatspec.AnyFlatSpec\nimport scala.io.Source\n\nclass OverlayRoccTestMAC2 extends AnyFlatSpec with ChiselScalatestTester {\n \"OverlayRoccTestMAC2 test\" should \"pass\" in {\n test(new OverlayRocc(32, 6, 6, 32)).withAnnotations(Seq(VerilatorBackendAnnotation, WriteVcdAnnotation)) { dut =>\n ///////////////////////////////////////////\n // MAC2\n ///////////////////////////////////////////\n \n var dataInValid = \"b000000\".U \n var dataOutReady = \"b111111\".U \n dut.io.dataInValid.poke(dataInValid)\n dut.io.dataOutReady.poke(dataOutReady)\n dut.clock.step(1)\n\n var cellConfig: UInt = 0.U \n \n val source = Source.fromFile(\"src/test/scala/Bitstreams/mac2.txt\")\n for (line <- source.getLines()){ \n cellConfig = (\"b\" + line).U \n dut.io.cellConfig.poke(cellConfig)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n }\n source.close()\n \n ///////////////////////////////////////////\n // Test 1: x = Σ 1 (n = 4) + 3\n // y = Σ 2 (n = 4) + 3\n ///////////////////////////////////////////\n /\n for (i <- 1 to 16) {\n // ------------------------------------------------------------------------------------------------\n // \| \| C5 \| C4 \| C3 \| C2 \| C1 \| C0 \|\n // ------------------------------------------------------------------------------------------------\n // ------------------------------------------------------------------------------------------------\n // \| \| y \| x \| d \| c \| a \| b \|\n // ------------------------------------------------------------------------------------------------\n val din = BigInt(\"00000003\" + \"00000003\" + \"00000001\"+ \"00000001\" + \"00000001\" + \"00000001\" ,16).S\n \n dut.io.dataIn.poke(din)\n dut.io.dataInValid.poke(\"b111111\".U)\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n }\n */\n\n ///////////////////////////////////////////\n // Test 2: x = Σ 8 (n = 5) + 3\n // y = Σ 20i (n = 5) + 4\n ///////////////////////////////////////////\n \n", "right_context": " dut.io.dataIn.poke(din)\n dut.io.dataInValid.poke(\"b111111\".U)\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(10)\n }\n\n // Finish \n for( i <- 0 to 10){\n dut.clock.step(1)\n } \n println(\"End of the simulation\") \n }\n } \n}\n", "groundtruth": " for (i <- 1 to 16) {\n // ------------------------------------------------------------------------------------------------\n // \| \| C5 \| C4 \| C3 \| C2 \| C1 \| C0 \|\n // ------------------------------------------------------------------------------------------------\n // ------------------------------------------------------------------------------------------------\n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/OverlayRoccTestSUM.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ****************************************/\nimport chisel3._\nimport chiseltest._\nimport chisel3.util._\nimport org.scalatest.flatspec.AnyFlatSpec\nimport scala.io.Source\n\nclass OverlayRoccTestSUM extends AnyFlatSpec with ChiselScalatestTester {\n \"OverlayRoccTestSUM test\" should \"pass\" in {\n test(new OverlayRocc(32, 6, 6, 32)).withAnnotations(Seq(VerilatorBackendAnnotation, WriteVcdAnnotation)) { dut =>\n ///////////////////////////////////////////\n // SUM\n ///////////////////////////////////////////\n var dataInValid = \"b000000\".U \n var dataOutReady = \"b111111\".U \n \n dut.io.dataInValid.poke(dataInValid)\n dut.io.dataOutReady.poke(dataOutReady)\n dut.clock.step(1)\n\n var cellConfig: UInt = 0.U \n \n val source = Source.fromFile(\"src/test/scala/Bitstreams/sum.txt\")\n for (line <- source.getLines()){\n cellConfig = (\"b\" + line).U \n dut.io.cellConfig.poke(cellConfig)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.clock.step(1)\n }\n source.close()\n \n ///////////////////////////////////////////\n // Test 1: x = 2i + 1\n ///////////////////////////////////////////\n / \n for (i <- 1 to 16) {\n // ------------------------------------------------------------------------------------------------\n // \| \| C5 \| C4 \| C3 \| C2 \| C1 \| C0 \|\n // ------------------------------------------------------------------------------------------------\n // ------------------------------------------------------------------------------------------------\n // \| \| a \| b \| - \| - \| - \| - \|\n // ------------------------------------------------------------------------------------------------\n val din = BigInt((i+1).formatted(\"%08X\")+ f\"$i%08X\" + \"00000000000000000000000000000000\",16).S\n dut.io.dataIn.poke(din)\n dut.io.dataInValid.poke(\"b110000\".U)\n dut.clock.step(i)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(5)\n }\n /\n\n ///////////////////////////////////////////\n // Test 2: x = 2i + 3\n ///////////////////////////////////////////\n /\n for (i <- 1 to 16) {\n // ------------------------------------------------------------------------------------------------\n // \| \| C5 \| C4 \| C3 \| C2 \| C1 \| C0 \|\n // ------------------------------------------------------------------------------------------------\n // ------------------------------------------------------------------------------------------------\n // \| \| a \| b \| - \| - \| - \| - \|\n // ------------------------------------------------------------------------------------------------\n val din = BigInt((i+2).formatted(\"%08X\")+ (i+1).formatted(\"%08X\") + \"00000000000000000000000000000000\",16).S\n dut.io.dataIn.poke(din)\n dut.io.dataInValid.poke(\"b110000\".U)\n dut.clock.step(1)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(5)\n }\n */\n\n ///////////////////////////////////////////\n // Test 3: x = i\n ///////////////////////////////////////////\n\n for (i <- 4 to 19) {\n // ------------------------------------------------------------------------------------------------\n // \| \| C5 \| C4 \| C3 \| C2 \| C1 \| C0 \|\n // ------------------------------------------------------------------------------------------------\n // ------------------------------------------------------------------------------------------------\n // \| \| a \| b \| - \| - \| - \| - \|\n // ------------------------------------------------------------------------------------------------\n val din = BigInt(\"00000003\" + (i-3).formatted(\"%08X\") + \"00000000000000000000000000000000\",16).S\n dut.io.dataIn.poke(din)\n dut.io.dataInValid.poke(\"b110000\".U)\n dut.clock.step(i)\n dut.io.dataInValid.poke(\"b000000\".U)\n dut.clock.step(5)\n }\n \n // Finish \n", "right_context": " } \n}\n", "groundtruth": " for( i <- 0 to 10){\n dut.clock.step(1)\n } \n", "crossfile_context": ""}
	{"task_id": "CGRAs", "path": "CGRAs/src/test/scala/ProcessingElementTest.scala", "left_context": "/****************************************** \n * \\`-._ __ \n \\\\ `-..____,.' `. \n :`. / \\`. \n : ) : : \\ \n ;' ' ; \| : \n ).. .. .:.`.; : \n /::... .:::... ` ; \n ; _ ' __ /:\\ \n `:o> /\\o_> ;:. `. \n `-`.__ ; __..--- /:. \\ \n === \\_/ ;=====_.':. ; \n ,/'`--'...`--.... ; \n ; ; \n .' ; \n .' ; \n .' .. , . ; \n : ::.. / ;::. \| \n / `.;::. \| ;:.. ; \n : \|:. : ;:. ; \n : :: ;:.. \|. ; \n : :; :::....\| \| \n /\\ ,/ \\ ;:::::; ; \n .:. \\:..\| : ; '.--\| ; \n ::. :'' `-.,,; ;' ; ; \n .-'. _.'\\ / `; \\,__: \\ \n `---' `----' ; / \\,.,,,/ \n `----` \n ***************************************\n Yasna Katebzadeh \n yasna.katebzadeh@gmail.com \n ***************************************/\nimport chisel3._\nimport chiseltest._\nimport org.scalatest.flatspec.AnyFlatSpec\n\nobject ProcessingElementParams\n{\n def DATA_WIDTH = 32\n", "right_context": " def INSTRUCTION_CHANGE_DELAY = 5 \n}\n\nimport ProcessingElementParams._\n\nclass ProcessingElementTest extends AnyFlatSpec with ChiselScalatestTester {\n \"ProcessingElementTest test\" should \"pass\" in {\n // Test code for summation with positive numbers\n\n test(new ProcessingElement(DATA_WIDTH, FIFO_DEPTH)).withAnnotations(Seq(VerilatorBackendAnnotation, WriteVcdAnnotation)) { dut =>\n \n var numOfTests = 150\n\n var northDin = 0.S\n var northDinValid = false.B\n val northDoutReady = true.B \n\n var eastDin = 0.S \n var eastDinValid = false.B \n val eastDoutReady = true.B \n\n var southDin = 0.S \n var southDinValid = false.B \n val southDoutReady = true.B \n\n var westDin = 0.S \n var westDinValid = false.B \n val westDoutReady = true.B \n\n // Initialization\n dut.io.northDin.poke(northDin)\n dut.io.northDinValid.poke(northDinValid)\n dut.io.northDoutReady.poke(northDoutReady)\n \n dut.io.eastDin.poke(eastDin)\n dut.io.eastDinValid.poke(eastDinValid)\n dut.io.eastDoutReady.poke(eastDoutReady)\n\n dut.io.southDin.poke(southDin)\n dut.io.southDinValid.poke(southDinValid)\n dut.io.southDoutReady.poke(southDoutReady)\n\n dut.io.westDin.poke(westDin)\n dut.io.westDinValid.poke(westDinValid)\n dut.io.westDoutReady.poke(westDoutReady)\n\n ////////////////////////////////////////////////////////////////////////\n ////////\n ////////\n ////////\n //////// Feedback Loop\n ////////\n ////////\n ////////\n ////////\n ////////////////////////////////////////////////////////////////////////\n\n // Test case: SUM without feedback loop\n var configBits = \"b0000000000011110110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000001000000000000000_1000_0000_0000_0000_0000_0000_0011\".U \n var catchConfig = true.B \n // Configuration \n dut.io.catchConfig.poke(catchConfig)\n dut.io.catchConfig.poke(true.B)\n dut.io.configBits.poke(configBits)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.io.catchConfig.poke(false.B)\n configBits = 0.U\n dut.io.configBits.poke(configBits)\n \n // Inserting Data \n dut.io.northDinValid.poke(true.B)\n dut.io.westDinValid.poke(true.B)\n \n //dut.io.northDin.poke(1.S)\n //dut.io.westDin.poke(1.S)\n for (i <- 1 until 16) {\n dut.io.northDin.poke(i.S)\n dut.io.westDin.poke((i).S)\n dut.io.northDinValid.poke(true.B)\n dut.io.westDinValid.poke(true.B)\n dut.clock.step(1)\n dut.io.northDinValid.poke(false.B)\n dut.io.westDinValid.poke(false.B)\n dut.clock.step(10)\n }\n dut.io.northDin.poke(0.S)\n dut.io.westDin.poke(0.S)\n dut.io.northDinValid.poke(false.B)\n dut.io.westDinValid.poke(false.B)\n for (i <- 0 until INSTRUCTION_CHANGE_DELAY) {\n dut.clock.step(1)\n }\n\n // Test case: Mul\n configBits = \"b01000000000001101100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000110000000000000001000000000000000000000000011\".U \n catchConfig = true.B \n // Configuration \n dut.io.catchConfig.poke(catchConfig)\n dut.io.catchConfig.poke(true.B)\n dut.io.configBits.poke(configBits)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.io.catchConfig.poke(false.B)\n configBits = 0.U\n dut.io.configBits.poke(configBits)\n \n // Inserting Data \n dut.io.northDinValid.poke(true.B)\n dut.io.westDinValid.poke(true.B)\n\n dut.io.northDin.poke(2.S)\n dut.io.westDin.poke(1.S)\n \n for (i <- 1 until 27) {\n //dut.io.northDin.poke(i.S)\n //dut.io.westDin.poke((i+1).S)\n dut.clock.step(1)\n }\n dut.io.northDin.poke(0.S)\n dut.io.westDin.poke(0.S)\n dut.io.northDinValid.poke(false.B)\n dut.io.westDinValid.poke(false.B)\n for (i <- 0 until INSTRUCTION_CHANGE_DELAY) {\n dut.clock.step(1)\n }\n\n // Test case: Sub\n configBits = \"b01000000000111101100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000001010000000000000001000000000000000000000000011\".U \n catchConfig = true.B \n // Configuration \n dut.io.catchConfig.poke(catchConfig)\n dut.io.catchConfig.poke(true.B)\n dut.io.configBits.poke(configBits)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.io.catchConfig.poke(false.B)\n configBits = 0.U\n dut.io.configBits.poke(configBits)\n \n // Inserting Data \n dut.io.northDinValid.poke(true.B)\n dut.io.westDinValid.poke(true.B)\n \n dut.io.northDin.poke(1.S)\n dut.io.westDin.poke(124.S)\n \n for (i <- 1 until 123) {\n dut.clock.step(1)\n }\n dut.io.northDin.poke(0.S)\n dut.io.westDin.poke(0.S)\n dut.io.northDinValid.poke(false.B)\n dut.io.westDinValid.poke(false.B)\n for (i <- 0 until INSTRUCTION_CHANGE_DELAY) {\n dut.clock.step(1)\n }\n\n // Test case: Shift left (logic)\n //////////// North: din_2, West: din_1 \n configBits = \"b01000000000001111100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000001110000000000000001000000000000000000000000011\".U \n catchConfig = true.B \n // Configuration \n dut.io.catchConfig.poke(catchConfig)\n dut.io.catchConfig.poke(true.B)\n dut.io.configBits.poke(configBits)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.io.catchConfig.poke(false.B)\n configBits = 0.U\n dut.io.configBits.poke(configBits)\n \n // Inserting Data \n dut.io.northDinValid.poke(true.B)\n dut.io.westDinValid.poke(true.B)\n \n dut.io.westDin.poke(1.S)\n dut.io.northDin.poke(1.S)\n for (i <- 1 until 31) {\n dut.clock.step(1)\n }\n dut.io.westDin.poke(0.S)\n dut.io.northDin.poke(0.S)\n dut.io.northDinValid.poke(false.B)\n dut.io.westDinValid.poke(false.B)\n for (i <- 0 until INSTRUCTION_CHANGE_DELAY) {\n dut.clock.step(1)\n }\n\n // ** Test case: Shift left (arithmetic) ????? or Right ? \n\n configBits = \"b01000000000111101100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000010010000000000000001000000000000000000000000011\".U \n catchConfig = true.B \n // Configuration \n dut.io.catchConfig.poke(catchConfig)\n dut.io.catchConfig.poke(true.B)\n dut.io.configBits.poke(configBits)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.io.catchConfig.poke(false.B)\n configBits = 0.U\n dut.io.configBits.poke(configBits)\n \n // Inserting Data \n dut.io.northDinValid.poke(true.B)\n dut.io.westDinValid.poke(true.B)\n \n \n for (i <- 1 until numOfTests) {\n dut.io.westDin.poke((-(i4)).S)\n dut.io.northDin.poke((i-1).S)\n dut.clock.step(1)\n }\n dut.io.northDinValid.poke(false.B)\n dut.io.westDinValid.poke(false.B)\n for (i <- 0 until INSTRUCTION_CHANGE_DELAY) {\n dut.clock.step(1)\n }\n\n // *** Test case: Shift right (logic)\n\n configBits = \"b01000000000111101100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000010110000000000000001000000000000000000000000011\".U \n catchConfig = true.B \n // Configuration \n dut.io.catchConfig.poke(catchConfig)\n dut.io.catchConfig.poke(true.B)\n dut.io.configBits.poke(configBits)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.io.catchConfig.poke(false.B)\n configBits = 0.U\n dut.io.configBits.poke(configBits)\n \n // Inserting Data \n dut.io.northDinValid.poke(true.B)\n dut.io.westDinValid.poke(true.B)\n \n dut.io.northDin.poke(1.S)\n for (i <- 1 until numOfTests) {\n dut.io.westDin.poke((-(i2)).S)\n dut.io.northDin.poke((i-1).S)\n dut.clock.step(1)\n }\n \n dut.io.northDinValid.poke(false.B)\n dut.io.westDinValid.poke(false.B)\n for (i <- 0 until INSTRUCTION_CHANGE_DELAY) {\n dut.clock.step(1)\n }\n\n // * Test case: AND\n configBits = \"b01000000000111101100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000011010000000000000001000000000000000000000000011\".U \n catchConfig = true.B \n // Configuration \n dut.io.catchConfig.poke(catchConfig)\n dut.io.catchConfig.poke(true.B)\n dut.io.configBits.poke(configBits)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.io.catchConfig.poke(false.B)\n configBits = 0.U\n dut.io.configBits.poke(configBits)\n \n // Inserting Data \n dut.io.northDinValid.poke(true.B)\n dut.io.westDinValid.poke(true.B)\n \n \n for (i <- 1 until numOfTests) {\n dut.io.northDin.poke(i.S)\n if (i % 2 == 0) {\n dut.io.westDin.poke((i+1).S)\n } else {\n dut.io.westDin.poke((i+2).S)\n }\n dut.clock.step(1)\n }\n dut.io.northDinValid.poke(false.B)\n dut.io.westDinValid.poke(false.B)\n for (i <- 0 until INSTRUCTION_CHANGE_DELAY) {\n dut.clock.step(1)\n }\n\n // Test case: OR\n configBits = \"b01000000000111101100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000011110000000000000001000000000000000000000000011\".U \n catchConfig = true.B \n // Configuration \n dut.io.catchConfig.poke(catchConfig)\n dut.io.catchConfig.poke(true.B)\n dut.io.configBits.poke(configBits)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.io.catchConfig.poke(false.B)\n configBits = 0.U\n dut.io.configBits.poke(configBits)\n \n // Inserting Data \n dut.io.northDinValid.poke(true.B)\n dut.io.westDinValid.poke(true.B)\n \n for (i <- 1 until numOfTests) {\n dut.io.northDin.poke(i.S)\n if (i % 2 == 0) {\n dut.io.westDin.poke((i+1).S)\n } else {\n dut.io.westDin.poke((i+2).S)\n }\n dut.clock.step(1)\n }\n dut.io.northDinValid.poke(false.B)\n dut.io.westDinValid.poke(false.B)\n for (i <- 0 until INSTRUCTION_CHANGE_DELAY) {\n dut.clock.step(1)\n }\n // ** Test case: XOR\n configBits = \"b01000000000111101100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000100010000000000000001000000000000000000000000011\".U \n catchConfig = true.B \n // Configuration \n dut.io.catchConfig.poke(catchConfig)\n dut.io.catchConfig.poke(true.B)\n dut.io.configBits.poke(configBits)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.io.catchConfig.poke(false.B)\n configBits = 0.U\n dut.io.configBits.poke(configBits)\n \n // Inserting Data \n dut.io.northDinValid.poke(true.B)\n dut.io.westDinValid.poke(true.B)\n \n for (i <- 1 until numOfTests) {\n dut.io.northDin.poke(i.S)\n if (i % 2 == 0) {\n dut.io.westDin.poke((i+1).S)\n } else {\n dut.io.westDin.poke((i+2).S)\n }\n dut.clock.step(1)\n }\n dut.io.northDinValid.poke(false.B)\n dut.io.westDinValid.poke(false.B)\n for (i <- 0 until INSTRUCTION_CHANGE_DELAY) {\n dut.clock.step(1)\n }\n }\n } \n}", "groundtruth": " def FIFO_DEPTH = 32 \n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/example/detect2ones.test.scala", "left_context": "//> using scala \"2.13.14\"\n//> using dep \"com.github.rameloni::tywaves-chisel-api:0.4.2-SNAPSHOT\"\n//> using dep \"org.chipsalliance::chisel:6.4.0\"\n//> using plugin \"org.chipsalliance:::chisel-plugin:6.4.0\"\n//> using options \"-unchecked\", \"-deprecation\", \"-language:reflectiveCalls\", \"-feature\", \"-Xcheckinit\", \"-Xfatal-warnings\", \"-Ywarn-dead-code\", \"-Ywarn-unused\", \"-Ymacro-annotations\"\n//> using dep \"org.scalatest::scalatest:3.2.19\"\n\nimport chisel3._\nimport circt.stage._\nimport chisel3.util._\nimport tywaves.simulator._\nimport tywaves.simulator.simulatorSettings._\n\nimport org.scalatest.funspec.AnyFunSpec\nimport org.scalatest.matchers.should.Matchers\n\nclass DetectTwoOnes extends Module {\n val io = IO(new Bundle {\n val in = Input(Bool())\n val out = Output(Bool())\n })\n\n object State extends ChiselEnum { val sNone, sOne1, sTwo1s = Value }\n val state = RegInit(State.sNone)\n\n // Tmp signal 1\n val isOne = Wire(Bool())\n isOne := io.in\n // Tmp signal 2\n val willBeTwo1s = io.in && (state === State.sOne1 \|\| state === State.sTwo1s)\n\n io.out := (state === State.sTwo1s)\n\n switch(state) {\n is(State.sNone) { when(isOne) { state := State.sOne1 } }\n is(State.sOne1) { \n", "right_context": " }\n is(State.sTwo1s) { when(!isOne) { state := State.sNone } }\n }\n}\n\n\nclass DetectTwoOnesTest extends AnyFunSpec with Matchers {\n\n import TywavesSimulator._\n def runTest(fsm: DetectTwoOnes) = {\n // Inputs and expected results\n val inputs = Seq(0, 0, 1, 0, 1, 1, 0, 1, 1, 1)\n val expected = Seq(0, 0, 0, 0, 0, 1, 0, 0, 1, 1)\n\n // Reset\n fsm.io.in.poke(0)\n fsm.clock.step(1)\n\n for (i <- inputs.indices) {\n fsm.io.in.poke(inputs(i))\n fsm.clock.step(1)\n //\tc.clock.getStepCount\n fsm.io.out.expect(expected(i))\n //\tSystem.out.println(s\"In: ${inputs(i)}, out: ${expected(i)}\")\n }\n }\n\n describe(\"TywavesSimulator\") {\n it(\"runs DetectTwoOnes correctly\") {\n val chiselStage = new ChiselStage(true)\n \n chiselStage.execute(\n args = Array(\"--target\", \"chirrtl\"),\n annotations = Seq(\n chisel3.stage.ChiselGeneratorAnnotation(() => new DetectTwoOnes()),\n FirtoolOption(\"-g\"),\n FirtoolOption(\"--emit-hgldd\"),\n ),\n )\n\n simulate(new DetectTwoOnes(), Seq(VcdTrace, WithTywavesWaveformsGo(true)), simName = \"runs_detect2ones\") {\n fsm =>\n runTest(fsm)\n }\n\n }\n }\n\n}", "groundtruth": " when(isOne) { state := State.sTwo1s }.otherwise { state := State.sNone } \n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/example/gcd.test.scala", "left_context": "//> using scala \"2.13.14\"\n//> using dep \"com.github.rameloni::tywaves-chisel-api:0.4.2-SNAPSHOT\"\n//> using dep \"org.chipsalliance::chisel:6.4.0\"\n//> using plugin \"org.chipsalliance:::chisel-plugin:6.4.0\"\n//> using options \"-unchecked\", \"-deprecation\", \"-language:reflectiveCalls\", \"-feature\", \"-Xcheckinit\", \"-Xfatal-warnings\", \"-Ywarn-dead-code\", \"-Ywarn-unused\", \"-Ymacro-annotations\"\n//> using dep \"org.scalatest::scalatest:3.2.18\"\n\n// DO NOT EDIT THE ORTHER OF THESE IMPORTS (it will be solved in future versions)\nimport chisel3._\nimport tywaves.simulator._\nimport tywaves.simulator.ParametricSimulator._\nimport tywaves.simulator.simulatorSettings._\nimport circt.stage.ChiselStage\n// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._\n//import _root_.circt.stage.ChiselStage\nimport org.scalatest.funspec.AnyFunSpec\nimport org.scalatest.matchers.should.Matchers\n\n/** A simple module useful for testing Chisel generation and testing */\nclass GCD extends Module {\n val io = IO(new Bundle {\n val a = Input(UInt(32.W))\n val b = Input(UInt(32.W))\n val loadValues = Input(Bool())\n val result = Output(UInt(32.W))\n val resultIsValid = Output(Bool())\n })\n\n val x = Reg(UInt(32.W))\n val y = Reg(UInt(32.W))\n\n val tmp = x + y\n when(x > y) {\n val myTmpVal: UInt = x -% y\n x := myTmpVal\n }.otherwise {\n val myTmpVal = y -% x\n val myTmpVal3 = Wire(UInt(32.W))\n myTmpVal3 := myTmpVal\n y := y -% x\n }\n\n", "right_context": "\n io.result := x\n io.resultIsValid := y === 0.U\n}\n\nclass GCDTest extends AnyFunSpec with Matchers {\n describe(\"ParametricSimulator\") {\n it(\"runs GCD correctly\") {\n\n val chiselStage = new ChiselStage(true)\n chiselStage.execute(\n args = Array(\"--target\", \"chirrtl\"),\n annotations = Seq(\n chisel3.stage.ChiselGeneratorAnnotation(() => new GCD()),\n circt.stage.FirtoolOption(\"-g\"),\n circt.stage.FirtoolOption(\"--emit-hgldd\"),\n ),\n )\n println(\"Hello, world!\")\n simulate(new GCD(), Seq(VcdTrace, SaveWorkdirFile(\"gcdWorkdir\"))) { gcd =>\n gcd.io.a.poke(24.U)\n gcd.io.b.poke(36.U)\n gcd.io.loadValues.poke(1.B)\n gcd.clock.step()\n gcd.io.loadValues.poke(0.B)\n gcd.clock.stepUntil(sentinelPort = gcd.io.resultIsValid, sentinelValue = 1, maxCycles = 10)\n gcd.io.resultIsValid.expect(true.B)\n gcd.io.result.expect(12)\n }\n }\n }\n\n describe(\"TywavesSimulator\") {\n it(\"runs GCD correctly\") {\n import TywavesSimulator._\n\n simulate(new GCD(), Seq(VcdTrace, WithTywavesWaveforms(true)), simName = \"runs_GCD_correctly_launch_tywaves\") {\n gcd =>\n gcd.io.a.poke(24.U)\n gcd.io.b.poke(36.U)\n gcd.io.loadValues.poke(1.B)\n gcd.clock.step()\n gcd.io.loadValues.poke(0.B)\n gcd.clock.stepUntil(sentinelPort = gcd.io.resultIsValid, sentinelValue = 1, maxCycles = 10)\n gcd.io.resultIsValid.expect(true.B)\n gcd.io.result.expect(12)\n gcd.io.a.poke(24.U)\n gcd.io.b.poke(72.U)\n gcd.reset.poke(true.B)\n gcd.io.loadValues.poke(1.B)\n gcd.clock.step()\n gcd.io.loadValues.poke(0.B)\n gcd.reset.poke(false.B)\n gcd.clock.stepUntil(sentinelPort = gcd.io.resultIsValid, sentinelValue = 1, maxCycles = 10)\n gcd.io.resultIsValid.expect(true.B)\n gcd.io.result.expect(24)\n }\n }\n }\n\n}\n", "groundtruth": " when(io.loadValues) { x := io.a; y := io.b }\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/example/myfsm.test.scala", "left_context": "//> using scala \"2.13.14\"\n//> using dep \"com.github.rameloni::tywaves-chisel-api:0.4.2-SNAPSHOT\"\n//> using dep \"org.chipsalliance::chisel:6.4.0\"\n//> using plugin \"org.chipsalliance:::chisel-plugin:6.4.0\"\n//> using options \"-unchecked\", \"-deprecation\", \"-language:reflectiveCalls\", \"-feature\", \"-Xcheckinit\", \"-Xfatal-warnings\", \"-Ywarn-dead-code\", \"-Ywarn-unused\", \"-Ymacro-annotations\"\n//> using dep \"org.scalatest::scalatest:3.2.18\"\n\n// DO NOT EDIT THE ORTHER OF THESE IMPORTS (it will be solved in future versions)\nimport tywaves.simulator._\nimport tywaves.simulator.simulatorSettings._\nimport chisel3._\n// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._\n//import _root_.circt.stage.ChiselStage\nimport org.scalatest.funspec.AnyFunSpec\nimport org.scalatest.matchers.should.Matchers\nimport circt.stage.ChiselStage\n\n// Enum of possible states\nobject MyFSMStates extends ChiselEnum {\n val IDLE, StateA, StateB, END = Value\n}\n\nclass FSM extends Bundle {\n\n val inputState = IO(Input(MyFSMStates()))\n val state = RegInit(MyFSMStates.IDLE)\n val stateNxt = WireInit(MyFSMStates.IDLE)\n\n val endConst = WireInit(MyFSMStates.END)\n\n when(state === MyFSMStates.IDLE) {\n stateNxt := MyFSMStates.StateA\n }.elsewhen(state === MyFSMStates.StateA) {\n stateNxt := MyFSMStates.StateB\n }.elsewhen(state === MyFSMStates.StateB) {\n stateNxt := MyFSMStates.END\n }.otherwise {\n stateNxt := MyFSMStates.IDLE\n }\n\n when(inputState === MyFSMStates.END) {\n state := MyFSMStates.IDLE\n }.otherwise {\n state := stateNxt\n }\n}\n\nclass MyFSM extends Module {\n val fsm = new FSM\n\n val io = IO(new Bundle {\n val inputState = Input(MyFSMStates())\n })\n\n val aConstBundle = Wire(new Bundle {\n val bit = Bool()\n val bv = UInt(32.W)\n val subbundle = new Bundle {\n val x = SInt(3.W)\n }\n })\n aConstBundle.bit := 1.B\n aConstBundle.bv := 34.U\n aConstBundle.subbundle.x := 2.S\n}\n\n\nclass MyFSMTest extends AnyFunSpec with Matchers {\n\n describe(\"TywavesSimulator\") {\n it(\"runs MyFSM correctly\") {\n import TywavesSimulator._\n val chiselStage = new ChiselStage(true)\n \n chiselStage.execute(\n args = Array(\"--target\", \"chirrtl\"),\n annotations = Seq(\n chisel3.stage.ChiselGeneratorAnnotation(() => new MyFSM()),\n circt.stage.FirtoolOption(\"-g\"),\n circt.stage.FirtoolOption(\"--emit-hgldd\"),\n ),\n )\n simulate(new MyFSM(), Seq(VcdTrace, WithTywavesWaveformsGo(true)), simName = \"runs_MYFSM_correctly_launch_tywaves_and_go\") {\n fsm =>\n fsm.clock.step(10)\n fsm.clock.step(10)\n }\n simulate(new MyFSM(), Seq(VcdTrace, WithTywavesWaveforms(true)), simName = \"runs_MYFSM_correctly_launch_tywaves\") {\n fsm =>\n", "right_context": " }\n\n}\n", "groundtruth": " fsm.clock.step(10)\n fsm.io.inputState.poke(MyFSMStates.StateA)\n fsm.clock.step(10)\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/example/tydi-example-meaningfulnames.test.scala", "left_context": "//> using scala \"2.13.14\"\n//> using dep \"com.github.rameloni::tywaves-chisel-api:0.4.2-SNAPSHOT\"\n//> using dep \"nl.tudelft::tydi-chisel::0.1.0\"\n//> using plugin \"org.chipsalliance:::chisel-plugin:6.4.0\"\n//> using options \"-unchecked\", \"-deprecation\", \"-language:reflectiveCalls\", \"-feature\", \"-Xcheckinit\", \"-Xfatal-warnings\", \"-Ywarn-dead-code\", \"-Ywarn-unused\", \"-Ymacro-annotations\"\n//> using dep \"org.scalatest::scalatest:3.2.18\"\n\n// DO NOT EDIT THE ORTHER OF THESE IMPORTS (it will be solved in future versions)\nimport tywaves.simulator._\nimport tywaves.simulator.ParametricSimulator._\nimport tywaves.simulator.simulatorSettings._\nimport chisel3._\n\n// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._\n//import _root_.circt.stage.ChiselStage\nimport org.scalatest.funspec.AnyFunSpec\nimport org.scalatest.matchers.should.Matchers\n\nimport nl.tudelft.tydi_chisel._\nimport chisel3.util.Counter\n\nobject MyTypes {\n\n /** Bit(64) type, defined in pipelineSimple_types /\n def UInt_64_t = UInt(64.W)\n\n assert(this.UInt_64_t.getWidth == 64)\n\n /* Bit(64) type, defined in pipelineSimple_types /\n def generated_0_7_d3p7qsW3_29 = SInt(64.W)\n\n assert(this.generated_0_7_d3p7qsW3_29.getWidth == 64)\n}\n\n/\n Group element, defined in pipelineSimple_types. A composite type (like a\n * struct) that contains a value associated with a timestamp.\n /\nclass NumberGroup extends Group {\n val time = MyTypes.UInt_64_t\n val value = MyTypes.generated_0_7_d3p7qsW3_29\n}\n\n/\n Group element, defined in pipelineSimple_types. A composite type (like a\n * struct) that represents the stats of the implemented algorithm.\n /\nclass Stats extends Group {\n val average = (new UInt_64_t)\n val max = MyTypes.UInt_64_t\n val min = MyTypes.UInt_64_t\n val sum = MyTypes.UInt_64_t\n}\n\n/* Stream, defined in pipelineSimple_types. /\nclass Stats_stream(private val e: TydiEl = new Stats, n: Int = 1, d: Int = 1, c: Int = 1, r: Boolean = false, u: TydiEl = Null())\n extends PhysicalStreamDetailed(e = new Stats, n = n, d = d, c = c, r = r, u = u)\n\nobject Stats_stream {\n def apply(): Stats_stream = Wire(new Stats_stream())\n}\n\n/* Stream, defined in pipelineSimple_types. /\nclass Generated_0_36_xeHH4woS_24\n extends PhysicalStreamDetailed(e = new NumberGroup, n = 1, d = 2, c = 1, r = false, u = Null())\n\nobject Generated_0_36_xeHH4woS_24 {\n def apply(): Generated_0_36_xeHH4woS_24 = Wire(new Generated_0_36_xeHH4woS_24())\n}\n\n/* Stream, defined in pipelineSimple_types. /\nclass UInt_64_t_stream extends PhysicalStreamDetailed(e=new UInt_64_t, n=1, d=1, c=1, r=false, u=Null())\n\nobject UInt_64_t_stream {\n def apply(): UInt_64_t_stream = Wire(new UInt_64_t_stream())\n}\n\n/* Bit(64), defined in pipelineSimple_types. /\nclass UInt_64_t extends BitsEl(64.W)\n\n/* Bit(64), defined in pipelineSimple_types. /\n", "right_context": "\n/\n Streamlet, defined in pipelineSimple. Top level interface.\n /\nclass PipelineSimple_interface extends TydiModule {\n\n /* Stream of [[in]] with input direction. /\n val inStream = Generated_0_36_xeHH4woS_24().flip\n\n /* IO of [[inStream]] with input direction. /\n val in = inStream.toPhysical\n\n /* Stream of [[out]] with output direction. /\n val outStream = Stats_stream()\n\n /* IO of [[outStream]] with output direction. /\n val out = outStream.toPhysical\n\n val in2Stream = UInt_64_t_stream().flip\n /* IO of [[in2Stream]] with input direction. /\n val in2: PhysicalStream = in2Stream.toPhysical\n}\n\n/\n Streamlet, defined in pipelineSimple. Interface for the agg function.\n /\nclass Reducer_interface extends TydiModule {\n\n /* Stream of [[in]] with input direction. /\n val inStream = Generated_0_36_xeHH4woS_24().flip\n\n /* IO of [[inStream]] with input direction. /\n val in = inStream.toPhysical\n\n /* Stream of [[out]] with output direction. /\n val outStream = Stats_stream()\n\n /* IO of [[outStream]] with output direction. /\n val out = outStream.toPhysical\n}\n\n/\n Streamlet, defined in pipelineSimple. Interface for the non negative filter:\n * df.filter(col(\"value\") >= 0).\n /\nclass Instance_NonNegativeFilter_interface_RefToVargenerated_0_36_KLOZ7sts_25_1 extends TydiModule {\n\n /* Stream of [[in]] with input direction. /\n val inStream = Generated_0_36_xeHH4woS_24().flip\n\n /* IO of [[inStream]] with input direction. /\n val in = inStream.toPhysical\n\n /* Stream of [[out]] with output direction. /\n val outStream = Generated_0_36_xeHH4woS_24()\n\n /* IO of [[outStream]] with output direction. /\n val out = outStream.toPhysical\n}\n\n/\n Implementation, defined in pipelineSimple. Implementation of\n * df.filter(col(\"value\") >= 0).\n /\nclass NonNegativeFilter extends Instance_NonNegativeFilter_interface_RefToVargenerated_0_36_KLOZ7sts_25_1 {\n // Filtered only if the value is non-negative\n // inStream.valid tells us if the input is valid\n private val canPass: Bool = inStream.el.value >= 0.S && inStream.valid\n\n // Connect inStream to outStream\n // This is equivalent of connecting al the fields of the two streams\n // Every future assignment will overwrite the previous one\n outStream := inStream\n\n // Always ready to accept input\n inStream.ready := true.B\n\n // if (canPass) then { it can go out } else { it is not forwarded }\n outStream.valid := canPass && outStream.ready\n outStream.strb := inStream.strb(0) && canPass\n\n // All the other signals are forwarded\n // outStream.stai := inStream.stai\n // outStream.endi := inStream.endi\n // outStream.last := inStream.last\n // outStream.el := inStream.el\n}\n\n/\n Implementation, defined in pipelineSimple. Top level implementation. It\n * instantiates the subcomponents and connects them together.\n /\nclass PipelineSimple extends PipelineSimple_interface {\n inStream := DontCare\n outStream := DontCare // Probably not used\n in2Stream := DontCare\n\n // Modules\n private val filter = Module(new NonNegativeFilter)\n private val reducer = Module(new Reducer)\n\n // Connections\n filter.in := in // This will overload the inStream := in\n reducer.in := filter.out\n out := reducer.out // This will overload the out := outStream -> that's why outStream is not used\n}\n\n/\n Implementation, defined in pipelineSimple. Implementation of the agg\n * function.\n */\nclass Reducer extends Reducer_interface {\n // Set the data width to 64 bits, such as the [[MyTypes]] types\n private val dataWidth = 64.W\n\n // Computing min and max\n private val maxVal: BigInt = BigInt(Long.MaxValue) // Must work with BigInt or we get an overflow\n private val cMin: UInt = RegInit(maxVal.U(dataWidth)) // REG for the min value\n private val cMax: UInt = RegInit(0.U(dataWidth)) // REG for the max value\n // Computing the sum\n private val cSum: UInt = RegInit(0.U(dataWidth)) // REG for the sum\n // Computing the avg\n private val nValidSamples: Counter = Counter(Int.MaxValue) // The number of samples received (valid && strb(0))\n private val nSamples: Counter = Counter(Int.MaxValue) // The number of samples received (valid)\n\n // Set the streams IN ready and OUT valid signals\n // inReady = if (maxVal > 0) { true.B } else { false.B}\n inStream.ready := (if (maxVal > 0) true.B else false.B)\n // inStream.ready := true.B\n\n // The output is valid only if we have received at least one sample\n outStream.valid := nSamples.value > 0.U\n\n // When a value is received\n when(inStream.valid) {\n // Get the value from th input stream\n val value = inStream.el.value.asUInt\n nSamples.inc()\n\n // Check the strb line and perform the updates\n when(inStream.strb(0)) {\n cMin := cMin min value\n cMax := cMax max value\n cSum := cSum + value\n nValidSamples.inc()\n }\n }\n // Set the output stream\n outStream.el.sum := cSum\n outStream.el.min := cMin\n outStream.el.max := cMax\n outStream.el.average.value := Mux(nValidSamples.value > 0.U, cSum / nValidSamples.value, 0.U)\n\n // Set the output stream control signals:\n // they are fixed since the sum, min, max and average are updated every cycle\n // and they hold the same value if no change is performed\n outStream.strb := 1.U\n outStream.stai := 0.U\n outStream.endi := 1.U\n outStream.last(0) := inStream.last(0)\n}\n\nclass PipelineSimpleTest extends AnyFunSpec with Matchers {\n describe(\"ParametricSimulator\") {\n it(\"runs Pipeline Simple correctly\") {\n simulate(new PipelineSimple, Seq(VcdTrace, SaveWorkdirFile(\"aaa\"))) {\n dut => dut.clock.step()\n }\n }\n }\n\n describe(\"TywavesSimulator\") {\n it(\"runs Pipeline Simple correctly\") {\n import TywavesSimulator._\n\n simulate(\n new PipelineSimple(),\n Seq(VcdTrace, WithTywavesWaveforms(true)),\n simName = \"runs_GCD_correctly_launch_tywaves\",\n ) {\n dut => dut.clock.step()\n\n }\n }\n }\n\n}\n", "groundtruth": "class Generated_0_7_d3p7qsW3_29 extends BitsEl(64.W)\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/example/tydi-example.test.scala", "left_context": "//> using scala \"2.13.14\"\n//> using dep \"com.github.rameloni::tywaves-chisel-api:0.4.2-SNAPSHOT\"\n//> using dep \"nl.tudelft::tydi-chisel::0.1.0\"\n//> using plugin \"org.chipsalliance:::chisel-plugin:6.4.0\"\n//> using options \"-unchecked\", \"-deprecation\", \"-language:reflectiveCalls\", \"-feature\", \"-Xcheckinit\", \"-Xfatal-warnings\", \"-Ywarn-dead-code\", \"-Ywarn-unused\", \"-Ymacro-annotations\"\n//> using dep \"org.scalatest::scalatest:3.2.18\"\n\n// DO NOT EDIT THE ORTHER OF THESE IMPORTS (it will be solved in future versions)\nimport tywaves.simulator._\nimport tywaves.simulator.ParametricSimulator._\nimport tywaves.simulator.simulatorSettings._\nimport chisel3._\n\n// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._\n//import _root_.circt.stage.ChiselStage\nimport org.scalatest.funspec.AnyFunSpec\nimport org.scalatest.matchers.should.Matchers\n\nimport nl.tudelft.tydi_chisel._\nimport chisel3.util.Counter\n\nobject MyTypes {\n\n /** Bit(64) type, defined in pipelineSimple_types /\n", "right_context": "\n assert(this.generated_0_7_Tc5SbYQz_27.getWidth == 64)\n\n /* Bit(64) type, defined in pipelineSimple_types /\n def generated_0_7_d3p7qsW3_29 = SInt(64.W)\n\n assert(this.generated_0_7_d3p7qsW3_29.getWidth == 64)\n}\n\n/\n Group element, defined in pipelineSimple_types. A composite type (like a\n * struct) that contains a value associated with a timestamp.\n /\nclass NumberGroup extends Group {\n val time = MyTypes.generated_0_7_Tc5SbYQz_27\n val value = MyTypes.generated_0_7_d3p7qsW3_29\n}\n\n/\n Group element, defined in pipelineSimple_types. A composite type (like a\n * struct) that represents the stats of the implemented algorithm.\n /\nclass Stats extends Group {\n val average = MyTypes.generated_0_7_Tc5SbYQz_27\n val max = MyTypes.generated_0_7_Tc5SbYQz_27\n val min = MyTypes.generated_0_7_Tc5SbYQz_27\n val sum = MyTypes.generated_0_7_Tc5SbYQz_27\n}\n\n/* Stream, defined in pipelineSimple_types. /\nclass Generated_0_30_soHLkh1p_30\n extends PhysicalStreamDetailed(e = new Stats, n = 1, d = 1, c = 1, r = false, u = Null())\n\nobject Generated_0_30_soHLkh1p_30 {\n def apply(): Generated_0_30_soHLkh1p_30 = Wire(new Generated_0_30_soHLkh1p_30())\n}\n\n/* Stream, defined in pipelineSimple_types. /\nclass Generated_0_36_xeHH4woS_24\n extends PhysicalStreamDetailed(e = new NumberGroup, n = 1, d = 2, c = 1, r = false, u = Null())\n\nobject Generated_0_36_xeHH4woS_24 {\n def apply(): Generated_0_36_xeHH4woS_24 = Wire(new Generated_0_36_xeHH4woS_24())\n}\n\n/* Bit(64), defined in pipelineSimple_types. /\nclass Generated_0_7_Tc5SbYQz_27 extends BitsEl(64.W)\n\n/* Bit(64), defined in pipelineSimple_types. /\nclass Generated_0_7_d3p7qsW3_29 extends BitsEl(64.W)\n\n/\n Streamlet, defined in pipelineSimple. Top level interface.\n /\nclass PipelineSimple_interface extends TydiModule {\n\n /* Stream of [[in]] with input direction. /\n val inStream = Generated_0_36_xeHH4woS_24().flip\n\n /* IO of [[inStream]] with input direction. /\n val in = inStream.toPhysical\n\n /* Stream of [[out]] with output direction. /\n val outStream = Generated_0_30_soHLkh1p_30()\n\n /* IO of [[outStream]] with output direction. /\n val out = outStream.toPhysical\n}\n\n/\n Streamlet, defined in pipelineSimple. Interface for the agg function.\n /\nclass Reducer_interface extends TydiModule {\n\n /* Stream of [[in]] with input direction. /\n val inStream = Generated_0_36_xeHH4woS_24().flip\n\n /* IO of [[inStream]] with input direction. /\n val in = inStream.toPhysical\n\n /* Stream of [[out]] with output direction. /\n val outStream = Generated_0_30_soHLkh1p_30()\n\n /* IO of [[outStream]] with output direction. /\n val out = outStream.toPhysical\n}\n\n/\n Streamlet, defined in pipelineSimple. Interface for the non negative filter:\n * df.filter(col(\"value\") >= 0).\n /\nclass Instance_NonNegativeFilter_interface_RefToVargenerated_0_36_KLOZ7sts_25_1 extends TydiModule {\n\n /* Stream of [[in]] with input direction. /\n val inStream = Generated_0_36_xeHH4woS_24().flip\n\n /* IO of [[inStream]] with input direction. /\n val in = inStream.toPhysical\n\n /* Stream of [[out]] with output direction. /\n val outStream = Generated_0_36_xeHH4woS_24()\n\n /* IO of [[outStream]] with output direction. /\n val out = outStream.toPhysical\n}\n\n/\n Implementation, defined in pipelineSimple. Implementation of\n * df.filter(col(\"value\") >= 0).\n /\nclass NonNegativeFilter extends Instance_NonNegativeFilter_interface_RefToVargenerated_0_36_KLOZ7sts_25_1 {\n // Filtered only if the value is non-negative\n // inStream.valid tells us if the input is valid\n private val canPass: Bool = inStream.el.value >= 0.S && inStream.valid\n\n // Connect inStream to outStream\n // This is equivalent of connecting al the fields of the two streams\n // Every future assignment will overwrite the previous one\n outStream := inStream\n\n // Always ready to accept input\n inStream.ready := true.B\n\n // if (canPass) then { it can go out } else { it is not forwarded }\n outStream.valid := canPass && outStream.ready\n outStream.strb := inStream.strb(0) && canPass\n\n // All the other signals are forwarded\n // outStream.stai := inStream.stai\n // outStream.endi := inStream.endi\n // outStream.last := inStream.last\n // outStream.el := inStream.el\n}\n\n/\n Implementation, defined in pipelineSimple. Top level implementation. It\n * instantiates the subcomponents and connects them together.\n /\nclass PipelineSimple extends PipelineSimple_interface {\n inStream := DontCare\n outStream := DontCare // Probably not used\n\n // Modules\n private val filter = Module(new NonNegativeFilter)\n private val reducer = Module(new Reducer)\n\n // Connections\n filter.in := in // This will overload the inStream := in\n reducer.in := filter.out\n out := reducer.out // This will overload the out := outStream -> that's why outStream is not used\n}\n\n/\n Implementation, defined in pipelineSimple. Implementation of the agg\n * function.\n */\nclass Reducer extends Reducer_interface {\n // Set the data width to 64 bits, such as the [[MyTypes]] types\n private val dataWidth = 64.W\n\n // Computing min and max\n private val maxVal: BigInt = BigInt(Long.MaxValue) // Must work with BigInt or we get an overflow\n private val cMin: UInt = RegInit(maxVal.U(dataWidth)) // REG for the min value\n private val cMax: UInt = RegInit(0.U(dataWidth)) // REG for the max value\n // Computing the sum\n private val cSum: UInt = RegInit(0.U(dataWidth)) // REG for the sum\n // Computing the avg\n private val nValidSamples: Counter = Counter(Int.MaxValue) // The number of samples received (valid && strb(0))\n private val nSamples: Counter = Counter(Int.MaxValue) // The number of samples received (valid)\n\n // Set the streams IN ready and OUT valid signals\n // inReady = if (maxVal > 0) { true.B } else { false.B}\n inStream.ready := (if (maxVal > 0) true.B else false.B)\n // inStream.ready := true.B\n\n // The output is valid only if we have received at least one sample\n outStream.valid := nSamples.value > 0.U\n\n // When a value is received\n when(inStream.valid) {\n // Get the value from th input stream\n val value = inStream.el.value.asUInt\n nSamples.inc()\n\n // Check the strb line and perform the updates\n when(inStream.strb(0)) {\n cMin := cMin min value\n cMax := cMax max value\n cSum := cSum + value\n nValidSamples.inc()\n }\n }\n // Set the output stream\n outStream.el.sum := cSum\n outStream.el.min := cMin\n outStream.el.max := cMax\n outStream.el.average := Mux(nValidSamples.value > 0.U, cSum / nValidSamples.value, 0.U)\n\n // Set the output stream control signals:\n // they are fixed since the sum, min, max and average are updated every cycle\n // and they hold the same value if no change is performed\n outStream.strb := 1.U\n outStream.stai := 0.U\n outStream.endi := 1.U\n outStream.last(0) := inStream.last(0)\n}\n\nclass PipelineSimpleTest extends AnyFunSpec with Matchers {\n describe(\"ParametricSimulator\") {\n it(\"runs Pipeline Simple correctly\") {\n simulate(new PipelineSimple, Seq(VcdTrace, SaveWorkdirFile(\"pipelineSimpleWorkdir\"))) {\n dut => dut.clock.step()\n }\n }\n }\n\n describe(\"TywavesSimulator\") {\n it(\"runs Pipeline Simple correctly\") {\n import TywavesSimulator._\n\n simulate(\n new PipelineSimple(),\n Seq(VcdTrace, WithTywavesWaveforms(true)),\n simName = \"runs_GCD_correctly_launch_tywaves\",\n ) {\n dut => dut.clock.step()\n\n }\n }\n }\n\n}\n", "groundtruth": " def generated_0_7_Tc5SbYQz_27 = UInt(64.W)\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/main/scala/tywaves/circuitmapper/TypedConverter.scala", "left_context": "package tywaves.circuitmapper\n\nimport chisel3.RawModule\nimport chisel3.stage.ChiselGeneratorAnnotation\nimport tywaves.BuildInfo.firtoolBinaryPath\n\n/** This case class is used to store the top module name /\nprivate[tywaves] case class TopModuleName(private[circuitmapper] var name: Option[String])\n\n/* This object contains methods to create debug information from firtool /\nprivate[tywaves] object TypedConverter {\n private lazy val chiselStage = new circt.stage.ChiselStage(withDebug = true)\n\n private val chiselStageBaseArgs =\n Array(\"--target\", \"systemverilog\", \"--split-verilog\", \"--firtool-binary-path\", firtoolBinaryPath)\n\n val firtoolBaseArgs: Seq[String] =\n Seq(\"-O=debug\", \"-g\", \"--emit-hgldd\", \"--split-verilog\") // Run in debug mode compiled with optimizations\n // Directories where the debug information is stored\n private var hglddDebugDir = \"hgldd/debug\"\n private var hglddWithOptDir = \"hgldd/opt\" // TODO: remove\n private var workingDir: Option[String] = None\n private val topModuleName = TopModuleName(None)\n\n // Default firtool options encoded as annotations for ChiselStage\n private val defaultFirtoolOptAnno = createFirtoolOptions(firtoolBaseArgs)\n // \"-disable-annotation-unknown\",\n // \"--hgldd-output-prefix=<path>\",\n /,\"--output-final-mlir=WORK.mlir\"/\n\n // Map any sequence of string into FirtoolOptions\n private def createFirtoolOptions(args: Seq[String]) = args.map(circt.stage.FirtoolOption)\n\n /\n Create debug information from firtool by using the\n * [[circt.stage.ChiselStage]]\n /\n def createDebugInfoHgldd[T <: RawModule](\n generateModule: () => T,\n workingDir: String = \"workingDir\",\n additionalFirtoolArgs: Seq[String],\n ): Unit = {\n this.workingDir = Some(workingDir)\n hglddWithOptDir = workingDir + \"/\" + hglddWithOptDir\n hglddDebugDir = workingDir + \"/\" + hglddDebugDir\n // hglddDebugDir = workingDir + \"/\" + \"support-artifacts\"\n\n // Annotations for ChiselStage\n val annotations = Seq(ChiselGeneratorAnnotation(generateModule)) ++ defaultFirtoolOptAnno\n\n // Run without debug mode: TODO check it is actually not needed\n // chiselStage.execute(\n // chiselStageBaseArgs ++ Array(\"--target-dir\", hglddWithOptDir),\n // annotations,\n // ) // execute returns the passThrough annotations in CIRCT transform stage\n\n val finalAnno = chiselStage.execute(\n chiselStageBaseArgs ++ Array(\"--target-dir\", hglddDebugDir),\n createFirtoolOptions(additionalFirtoolArgs) ++ annotations,\n ) // execute returns the passThrough annotations in CIRCT transform stage\n\n // Get the module name\n topModuleName.name = finalAnno.collectFirst {\n case chisel3.stage.ChiselCircuitAnnotation(circuit) => circuit.name\n }\n }\n\n /* Get the directory where the debug information is stored /\n def getDebugInfoDir(gOpt: Boolean): String =\n if (gOpt) hglddDebugDir\n else hglddWithOptDir\n\n /\n Return the working directory used in the last call of\n * [[createDebugInfoHgldd]]\n /\n def getWorkingDir: Option[String] = workingDir\n\n /\n Return the top module name of the last circuit used in the last call of\n * [[createDebugInfoHgldd]]\n */\n", "right_context": "\n}\n", "groundtruth": " def getTopModuleName: Option[String] = topModuleName.name\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/main/scala/tywaves/simulator/ParametricSimulator.scala", "left_context": "package tywaves.simulator\n\nimport chisel3.RawModule\nimport chisel3.simulator.SingleBackendSimulator\nimport chisel3.simulator.PeekPokeAPI\nimport svsim._\n\nimport java.nio.file.Files\nimport java.time.{LocalDateTime, format}\n\n/*\n The interface object to the simulation.\n \n It uses [[svsim]] and [[PeekPokeAPI]] to run a simulation.\n /\nobject ParametricSimulator extends PeekPokeAPI {\n\n /* Use this method to run a simulations /\n def simulate[T <: RawModule](\n module: => T,\n settings: Seq[SimulatorSettings] = Seq(),\n simName: String = \"defaultSimulation\",\n )(body: T => Unit): Unit =\n (new ParametricSimulator).simulate(module, settings, simName)(body)\n}\n\n/\n A simulator that can be customized by passing some parameters through a list\n * of [[SimulatorSettings]]. It offers the possibility to:\n * - output a trace vcd file\n * - store the files generated during the simulation\n /\nclass ParametricSimulator {\n\n // Settings variable of the simulator\n private var _backendCompileSettings = verilator.Backend.CompilationSettings()\n private val _testRunDir = \"test_run_dir\"\n private var _moduleDutName = \"\"\n private val _simulatorName = getClass.getSimpleName.stripSuffix(\"$\")\n private var _simName = \"defaultSimulationName\"\n\n // Working directory and workspace\n private var _workdirFinalFile: Option[String] = None\n private var _workdir: Option[String] = None // Initialized when makeSimulator is called\n protected def wantedWorkspacePath: String =\n if (_workdirFinalFile.isDefined)\n Seq(_testRunDir, _moduleDutName, _simulatorName, _simName, _workdirFinalFile.get).mkString(\"/\")\n else\n Seq(_testRunDir, _moduleDutName, _simulatorName, _simName).mkString(\"/\")\n\n // Traces\n private var _traceExtension: Option[String] = None\n private var _traceWantedName: String = \"trace\"\n private var _finalTracePath: Option[String] = None\n\n def finalTracePath: Option[String] = _finalTracePath\n private def _emittedTraceRelPath: Option[String] =\n if (_workdir.isDefined && _traceExtension.isDefined)\n Some(Seq(_workdir.get, s\"trace.${_traceExtension.get}\").mkString(\"/\"))\n else None\n\n private var _firtoolArgs: Seq[String] = Seq()\n", "right_context": "\n /* Launch and execute a simulation given a list of [[SimulatorSettings]]. /\n def simulate[T <: RawModule](\n module: => T,\n settings: Seq[SimulatorSettings] = Seq(),\n simName: String,\n )(body: T => Unit): Unit = {\n\n // Set the initial settings before the simulation: i.e. backend compile settings\n setInitialSettings(settings)\n\n // Create a new simulator\n val simulator = makeSimulator\n simulator\n .simulate(module) { simulatedModule =>\n // Set the controller settings: i.e. enable trace\n setControllerSettings(simulatedModule.controller, settings)\n\n // Update the wanted workspace path\n _moduleDutName = simulatedModule.wrapped.name\n _simName = simName\n\n // Launch the actual simulation and return the result\n body(simulatedModule.wrapped)\n }\n .result\n\n // Cleanup the simulation after the execution\n simulator.cleanup()\n }\n\n /\n Set settings before the simulation starts. It sets the initial settings\n * such as the backend compile settings, trace style, etc.\n /\n private def setInitialSettings(settings: Seq[SimulatorSettings]): Unit = {\n settings.foreach {\n case t: TraceSetting =>\n _backendCompileSettings = verilator.Backend.CompilationSettings(\n traceStyle = Some(t.traceStyle),\n outputSplit = None,\n outputSplitCFuncs = None,\n disabledWarnings = Seq(),\n disableFatalExitOnWarnings = false,\n )\n // Set also the extension\n _traceExtension = Some(t.extension)\n\n case TraceName(name) =>\n if (\n !settings.exists {\n case _: TraceSetting => true\n case _ => false\n }\n ) throw new Exception(\"TraceName must be used with TraceSetting\")\n if (settings.count(_.isInstanceOf[TraceName]) > 1)\n throw new Exception(\"TraceName must be used only once\")\n _traceWantedName = name\n\n case SaveWorkspace(name) =>\n if (settings.count(_.isInstanceOf[SaveWorkspace]) > 1)\n throw new Exception(\"SaveWorkspace must be used only once\")\n if (name == \"\") // If no name is specified -> Current date time as default (gg-mm-ddThh:mm) no millis\n _workdirFinalFile =\n Some(LocalDateTime.now().format(format.DateTimeFormatter.ofPattern(\"dd_MM_yyyy:HH-mm-ss\")))\n else\n _workdirFinalFile = Some(name)\n\n case FirtoolArgs(args) => _firtoolArgs = args\n case _ =>\n }\n\n // If it contains underscore, add it to the trace name\n if (settings.contains(simulatorSettings.VcdTraceWithUnderscore))\n _traceWantedName = s\"${_traceWantedName}_underscore\"\n\n }\n\n /\n Set the controller settings. It sets settings such as the trace output\n * enable.\n /\n private def setControllerSettings(controller: Simulation.Controller, settings: Seq[SimulatorSettings]): Unit =\n settings.foreach {\n case _: TraceSetting => controller.setTraceEnabled(true)\n case _ => // Do nothing\n }\n\n /* Default ParametricSimulator /\n protected class DefaultParametricSimulator(val workspacePath: String, val tag: String)\n extends SingleBackendSimulator[verilator.Backend] {\n\n val backend: verilator.Backend = verilator.Backend.initializeFromProcessEnvironment()\n override val firtoolArgs: Seq[String] = _firtoolArgs\n\n val backendSpecificCompilationSettings: verilator.Backend.CompilationSettings = _backendCompileSettings\n val commonCompilationSettings: CommonCompilationSettings =\n CommonCompilationSettings(\n optimizationStyle = CommonCompilationSettings.OptimizationStyle.OptimizeForCompilationSpeed,\n availableParallelism = CommonCompilationSettings.AvailableParallelism.UpTo(4),\n defaultTimescale = Some(CommonCompilationSettings.Timescale.FromString(\"1ms/1ms\")),\n )\n\n /\n Cleanup the simulation and move the simulation workspace to the wanted\n * workspace path.\n /\n def cleanup(): Unit = {\n\n val workDirOld = os.Path(workspacePath)\n val workDir = os.pwd / os.RelPath(wantedWorkspacePath)\n\n // Check if the workspace must be saved or not\n if (_workdirFinalFile.isDefined)\n os.copy(workDirOld, workDir, replaceExisting = true, createFolders = true, mergeFolders = true)\n\n // Rename the wanted trace\n if (_traceExtension.isDefined) {\n val tracePath = workDirOld / os.RelPath(_emittedTraceRelPath.get)\n val wantedTracePath =\n os.pwd / os.RelPath(Seq(wantedWorkspacePath, s\"${_traceWantedName}.${_traceExtension.get}\").mkString(\"/\"))\n os.copy(tracePath, wantedTracePath, replaceExisting = true, createFolders = true)\n _finalTracePath = Some(wantedTracePath.toString)\n }\n\n }\n }\n\n /* Create a new simulator */\n protected def makeSimulator: DefaultParametricSimulator = { // def allows to create a new simulator each tim\n val className = _simulatorName\n val id = java.lang.management.ManagementFactory.getRuntimeMXBean.getName\n\n val tmpWorkspacePath = Files.createTempDirectory(s\"${className}_${id}_\").toString\n val tag = \"default\"\n val defaultSimulator = new DefaultParametricSimulator(tmpWorkspacePath, tag = tag)\n _workdir = Some(s\"${defaultSimulator.workingDirectoryPrefix}-$tag\")\n defaultSimulator\n }\n}\n", "groundtruth": " def getFirtoolArgs: Seq[String] = _firtoolArgs\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/main/scala/tywaves/simulator/ParametricSimulatorInterface.scala", "left_context": "package tywaves.simulator\n\nimport chisel3.RawModule\n\ntrait ParametricSimulatorInterface {\n private var simulator = new ParametricSimulator\n\n /** If true, the simulator will be reset before running each simulation /\n private var _resetSimulationBeforeRun = false\n\n /* Use this method to run a simulations /\n def simulate[T <: RawModule](\n module: => T,\n", "right_context": " Use this method to manually reset the simulator and run multiple\n * independent simulations\n */\n def reset(): Unit =\n simulator = new ParametricSimulator\n\n def resetBeforeEachRun(): Unit =\n _resetSimulationBeforeRun = true\n}\n", "groundtruth": " settings: Seq[SimulatorSettings] = Seq(),\n simName: String = \"defaultSimulation\",\n )(body: T => Unit): Unit = {\n if (_resetSimulationBeforeRun)\n reset()\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/main/scala/tywaves/simulator/SimulatorSettings.scala", "left_context": "package tywaves.simulator\n\nimport svsim.verilator\nimport verilator.Backend.CompilationSettings.TraceStyle\n\n/** Trait to represent the simulator settings /\ntrait SimulatorSettings\n\nprotected sealed trait TraceSetting extends SimulatorSettings {\n val traceStyle: TraceStyle\n val extension: String\n}\n\n/\n [[TraceVcd]] is an abstracted representation of the\n * [[verilator.Backend.CompilationSettings.TraceStyle.Vcd]] that can be used by\n * the user of the simulator.\n /\nprivate[simulator] case class TraceVcd(traceUnderscore: Boolean) extends TraceSetting with SimulatorSettings {\n val traceStyle: TraceStyle = TraceStyle.Vcd(traceUnderscore)\n val extension: String = \"vcd\"\n}\n\n/\n [[TraceName]] stores the name of the final trace file.\n /\nprivate[simulator] case class TraceName(name: String) extends SimulatorSettings\n\n/\n [[SaveWorkspace]] tells to save the workspace of the simulation and stores\n * the final name.\n /\nprivate[simulator] case class SaveWorkspace(name: String) extends SimulatorSettings\n\n/\n [[FirtoolArgs]] stores the arguments to pass to the firtool command.\n /\n", "right_context": "\n/\n Package object to expose the simulator settings to the user. The following\n * settings can be used by a simulator to allow users to configure the\n * simulation.\n */\npackage object simulatorSettings {\n // Interface to the simulation\n val VcdTrace: TraceVcd = TraceVcd(false)\n val VcdTraceWithUnderscore: TraceVcd = TraceVcd(true)\n\n val SaveWorkdirFile: String => SaveWorkspace = (name: String) => SaveWorkspace(name)\n val SaveWorkdir: SaveWorkspace = SaveWorkspace(\"\")\n\n val NameTrace: String => TraceName = (name: String) => TraceName(name)\n\n val WithFirtoolArgs: Seq[String] => FirtoolArgs = (args: Seq[String]) => FirtoolArgs(args)\n\n}\n", "groundtruth": "private[simulator] case class FirtoolArgs(args: Seq[String]) extends SimulatorSettings\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/main/scala/tywaves/simulator/TywavesInterface.scala", "left_context": "package tywaves.simulator\n\nimport scala.annotation.unused\n\nprivate[tywaves] object TywavesInterface {\n\n private val program = tywaves.BuildInfo.surferTywavesBinaryPath\n\n def run(\n vcdPath: String,\n hglddDirPath: Option[String],\n extraScopes: Seq[String],\n topModuleName: Option[String],\n waitFor: Boolean = true,\n ): Unit = {\n {\n import scala.sys.process._\n\n // Check if tywaves is installed\n val exitCode = s\"which $program\".!\n", "right_context": " case Some(_) => Some(\"--hgldd-dir\")\n case None => None\n }\n\n val extraScopesCmd = (extraScopes, topModuleName) match {\n case (Nil, _) \| (_, None) => Nil\n case _ => Seq(\"--extra-scopes\") ++ extraScopes ++\n Seq(\"--top-module\") ++ topModuleName\n }\n\n val cmd = Seq(program, vcdPath) ++ hglddDirCmd ++ hglddDirPath ++ extraScopesCmd\n\n // Execute and return to the caller\n @unused val process = new ProcessBuilder(cmd: _*).inheritIO().start()\n if (waitFor)\n process.waitFor()\n // No wait for the process to finish\n }\n}\n", "groundtruth": " if (exitCode != 0)\n throw new Exception(s\"$program not found on the PATH! Please install it running: make all\\n\")\n }\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/main/scala/tywaves/simulator/TywavesSimulator.scala", "left_context": "package tywaves.simulator\n\nimport chisel3.RawModule\nimport chisel3.simulator.PeekPokeAPI\nimport svsim.Workspace\nimport tywaves.circuitmapper.TypedConverter\n\nobject TywavesSimulator extends PeekPokeAPI {\n\n", "right_context": "\n /** Generate tywaves info and optionally run the waveform /\n val WithTywavesWaveforms: Boolean => Tywaves = (runWaves: Boolean) => Tywaves(runWaves, waitFor = true)\n\n /\n Generate tywaves info and optionally run the waveform without blocking sbt\n /\n val WithTywavesWaveformsGo: Boolean => Tywaves = (runWaves: Boolean) => Tywaves(runWaves, waitFor = false)\n\n /* Use this method to run a simulation */\n def simulate[T <: RawModule](\n module: => T,\n settings: Seq[SimulatorSettings] = Seq(),\n simName: String = \"defaultSimulation\",\n )(body: T => Unit): Unit = {\n\n // Create a new simulator instance\n val simulator = new TywavesSimulator\n\n val containTywaves = settings.exists(_.isInstanceOf[Tywaves])\n\n val finalSettings =\n if (containTywaves)\n settings ++ Seq(FirtoolArgs(TypedConverter.firtoolBaseArgs))\n // Seq(FirtoolArgs(Seq(\"-O=debug\", \"-g\", \"--emit-hgldd\", \"--split-verilog\", \"-o=WORK.v\")))\n else settings\n\n simulator.simulate(module, finalSettings, simName)(body)\n\n if (simulator.finalTracePath.nonEmpty && containTywaves) {\n // Get the extra scopes created by ChiselSim backend: TOP, svsimTestbench, dut\n val extraScopes = Seq(\"TOP\", Workspace.testbenchModuleName, \"dut\")\n\n // Create the debug info from the firtool and get the top module name\n // TODO: this may not be needed anymore, since the debug info can be generated directly from chiselsim, by giving the right options to firtool\n // But the problem is to call chiselstage with debug options\n TypedConverter.createDebugInfoHgldd(\n () => module,\n workingDir = simulator.wantedWorkspacePath,\n additionalFirtoolArgs = simulator.getFirtoolArgs,\n )\n\n // Run tywaves viewer if the Tywaves waveform generation is enabled by Tywaves(true)\n val (runWaves, waitFor) =\n if (finalSettings.contains(Tywaves(runWaves = true, waitFor = true))) { (true, true) }\n else if (finalSettings.contains(Tywaves(runWaves = true, waitFor = false))) { (true, false) }\n else { (false, false) }\n if (runWaves)\n TywavesInterface.run(\n vcdPath = simulator.finalTracePath.get,\n hglddDirPath = Some(TypedConverter.getDebugInfoDir(gOpt = true)),\n extraScopes = extraScopes,\n topModuleName = TypedConverter.getTopModuleName,\n waitFor = waitFor,\n )\n } else if (containTywaves)\n throw new Exception(\"Tywaves waveform generation requires a trace file. Please enable VcdTrace.\")\n\n }\n\n}\nclass TywavesSimulator extends ParametricSimulator\n", "groundtruth": " private[simulator] case class Tywaves(runWaves: Boolean, waitFor: Boolean) extends SimulatorSettings\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/main/scala/tywaves/utils/UniqueHashMap.scala", "left_context": "package tywaves.utils\n\nimport java.nio.file.Paths\nimport scala.collection.mutable\n\nclass UniqueHashMap[K, V] extends mutable.HashMap[K, V] {\n\n private val _debugList = new mutable.ListBuffer[(K, V)]()\n private val debugList = new mutable.ListBuffer[(K, V, Int)]()\n\n /** Same implementation of [[mutable.HashMap.put]] */\n def putOrReplace(key: K, value: V): Option[V] =\n super.put(key, value)\n\n override def put(key: K, value: V): Option[V] = {\n if (super.contains(key)) {\n this.foreach(Console.err.println(_))\n\n throw new Exception(s\"Key $key already exists in the map. This is likely a bug in the parser.\\n\" +\n s\"Probably a new ID mapping is needed or the element is parsed twice.\\n\" +\n s\"Val is $value.\")\n }\n if (_debugList.contains((key, value))) {\n // Get that element and update that element\n val index = _debugList.indexOf((key, value))\n debugList(index) = ((key, value, debugList(index)._3 + 1))\n } else {\n _debugList += ((key, value))\n debugList += ((key, value, 0))\n }\n super.put(key, value)\n }\n\n def dumpFile(file: String, header: String, append: Boolean = true): Unit = {\n val path = Paths.get(file)\n java.nio.file.Files.createDirectories(path.getParent)\n val bw = new java.io.BufferedWriter(new java.io.FileWriter(file, append))\n bw.write(s\"\\n$header\\n\")\n\n", "right_context": " println(s\"$key: $value\")\n }\n }\n def debugLog(): Unit =\n debugList.foreach(println)\n}\n", "groundtruth": " this.foreach { case (key, value) =>\n bw.write(s\"$key: $value\\n\")\n }\n bw.close()\n }\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/GetNameTest.scala", "left_context": "import chisel3.Bundle\nimport org.scalatest.flatspec.AnyFlatSpec\n\nimport scala.reflect.runtime.universe._\n", "right_context": "class GetNameTest extends AnyFlatSpec {\n behavior of \"GetNameTest\"\n def getClassName[T: TypeTag](obj: T): String = {\n val className = typeOf[T].typeSymbol.asClass.name.toString\n s\"$className\"\n }\n def getName(obj: Any): String =\n obj.getClass.getCanonicalName match {\n case null => \"Unknown Class Name\"\n case _ => obj.getClass.getCanonicalName\n }\n\n def printNames(obj: Bundle): Unit = {\n println(\"GetSimpleName: \" + obj.getClass.getSimpleName)\n println(\"GetName: \" + obj.getClass.getName)\n println(\"GetCanonicalName: \" + obj.getClass.getCanonicalName)\n println(\"GetTypeName: \" + obj.getClass.getTypeName)\n println(\"GetType: \" + obj.className)\n }\n\n it should \"get anonymous class name\" in {\n val anonBundle = new Bundle {}\n printNames(anonBundle)\n println(anonBundle.className)\n println(getClassName(anonBundle))\n// println(getClassName(an))\n }\n\n it should \"get named class name\" in {\n val namedBundle = new MyBundle\n printNames(namedBundle)\n println(getClassName(namedBundle))\n\n }\n\n it should \"get anonymous class name from named class\" in {\n val anonBundle = new MyBundle {}\n printNames(anonBundle)\n println(getClassName(anonBundle))\n\n }\n\n}\n", "groundtruth": "class MyBundle extends Bundle\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/bar/Bar.scala", "left_context": "package bar\n\nimport chisel3._\n\nclass Baz(n: Int) extends Bundle {\n val a = UInt(n.W)\n val b = UInt(n.W)\n\n val nestedBundle = new Bundle {\n val z = Bool()\n }\n}\n\nclass Bar extends Module {\n val io = IO(new Bundle {\n val a = Input(Bool())\n val b = Input(Bool())\n val out = Output(Bool())\n })\n\n val inputSum = IO(Input(new Baz(8)))\n val outputSum = IO(Output(SInt(8.W)))\n\n when(inputSum.nestedBundle.z === true.B) {\n outputSum := inputSum.a.asSInt + inputSum.b.asSInt\n }.otherwise {\n outputSum := inputSum.a.asSInt - inputSum.b.asSInt\n }\n", "right_context": "}\n\nobject MainBar extends App {\n import circt.stage.ChiselStage\n\n println(\n ChiselStage.emitSystemVerilog(\n new Bar,\n firtoolOpts = Array(\n \"-O=debug\",\n \"-g\",\n \"-emit-hgldd\",\n \"-output-final-mlir=Foo.mlir\",\n ),\n )\n )\n}\n", "groundtruth": "\n val cable =\n Wire(Bool()) // do not use reserved verilog words as val names (val wire) -> tywaves-demo does not work for them yet\n cable := io.a & io.b\n\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/bar/BarTest.scala", "left_context": "package bar\n\nimport org.scalatest.flatspec.AnyFlatSpec\nimport tywaves.simulator.ParametricSimulator._\nimport tywaves.simulator.simulatorSettings._\nimport chisel3.fromBooleanToLiteral\nimport tywaves.simulator.TywavesSimulator\n\nclass BarTest extends AnyFlatSpec {\n behavior of \"BarTest\"\n it should \"trace simple bar\" in {\n simulate(\n module = new Bar,\n settings = Seq(VcdTraceWithUnderscore, SaveWorkdir),\n simName = \"trace_simple_bar\",\n ) { c =>\n c.clock.step()\n c.io.a.poke(true)\n c.io.b.poke(false)\n c.io.out.expect(false.B)\n\n c.clock.step()\n c.io.a.poke(true)\n c.io.b.poke(true)\n c.io.out.expect(true.B)\n\n c.clock.step()\n c.clock.step(cycles = 10)\n }\n }\n\n it should \"trace simple bar with tywaves\" in {\n import tywaves.simulator.TywavesSimulator._\n\n simulate(\n module = new Bar,\n settings = Seq(VcdTraceWithUnderscore, SaveWorkdir, WithTywavesWaveforms(false)),\n simName = \"trace_simple_bar_with_tywaves\",\n ) { c =>\n c.clock.step()\n c.io.a.poke(true)\n c.io.b.poke(false)\n c.io.out.expect(false.B)\n\n c.clock.step()\n c.io.a.poke(true)\n c.io.b.poke(true)\n", "right_context": " c.clock.step(cycles = 10)\n }\n }\n}\n", "groundtruth": " c.io.out.expect(true.B)\n\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/foo/Foo.scala", "left_context": "package foo\n\nimport chisel3._\nimport circt.stage.ChiselStage\n\n", "right_context": "\nclass MyBundle extends Simple {\n val a = UInt(8.W)\n val b = UInt(8.W)\n val c = UInt(8.W)\n\n val bundle = new Bundle {\n val z = Bool()\n }\n}\n\nclass Foo extends Module {\n val x = IO(Input(Bool()))\n val s = IO(Input(new MyBundle))\n val io_a = Wire(Bool())\n\n val io = IO(new Bundle {\n val a = Input(Bool())\n val b = Input(Bool())\n val out = Output(UInt(8.W))\n })\n\n // val vec = VecInit(Seq.fill(4)(0.U(8.W)))\n // val reg = RegInit(0.U(8.W))\n\n dontTouch(io_a)\n // dontTouch(vec)\n\n io_a := 1.U\n io.out := io.a + io.b\n\n printf(p\"s: $s\\n\")\n}\n\nobject MainFoo extends App {\n\n println(\n ChiselStage.emitSystemVerilog(\n new Foo,\n firtoolOpts = Array(\n \"-O=debug\",\n \"-g\",\n \"-emit-hgldd\",\n \"-output-final-mlir=Fooa.mlir\",\n ),\n )\n )\n\n}\n", "groundtruth": "class Simple extends Bundle\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/foo/FooTest.scala", "left_context": "package foo\n\n// The high level simulation API: it uses svsim internally\nimport tywaves.simulator.ParametricSimulator._\nimport org.scalatest.flatspec.AnyFlatSpec\nimport tywaves.simulator.simulatorSettings._\n\nobject RunFoo {\n\n /** Run multiple times */\n def apply(c: => Foo): Unit = {\n // Inputs and expected results\n val a = Seq(0, 1, 0, 1)\n val b = Seq(0, 0, 1, 1)\n\n // Reset\n c.io.a.poke(false)\n c.io.b.poke(true)\n c.clock.step()\n\n for (i <- a.zip(b)) {\n c.io.a.poke(i._1)\n c.io.b.poke(i._2)\n c.clock.step()\n }\n }\n}\n\nclass FooTest extends AnyFlatSpec {\n behavior of \"FooTest\"\n\n it should \"trace with underscore\" in {\n // val testName = testNames.headOption.getOrElse(\"Unknown Test\")\n", "right_context": " simulate(new Foo, Seq(VcdTrace), simName = \"trace\") { c =>\n c.io.a.poke(true)\n c.io.b.poke(0)\n }\n }\n\n}\n", "groundtruth": " simulate(new Foo, Seq(VcdTraceWithUnderscore), simName = \"trace_with_underscore\") {\n println(\"Running test: \" + it)\n RunFoo(_)\n }\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/gcd/GCD.scala", "left_context": "package gcd\n\nimport chisel3._\n\n/** A simple module useful for testing Chisel generation and testing */\nclass GCD extends Module {\n val io = IO(new Bundle {\n val a = Input(UInt(32.W))\n val b = Input(UInt(32.W))\n val loadValues = Input(Bool())\n val result = Output(UInt(32.W))\n val resultIsValid = Output(Bool())\n })\n\n val x = Reg(UInt(32.W))\n val y = Reg(UInt(32.W))\n\n when(x > y)(x := x -% y).otherwise(y := y -% x)\n\n", "right_context": "\n io.result := x\n io.resultIsValid := y === 0.U\n}\n", "groundtruth": " when(io.loadValues) { x := io.a; y := io.b }\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/gcd/GCDTest.scala", "left_context": "package gcd\n\nimport org.scalatest.funspec.AnyFunSpec\nimport org.scalatest.matchers.must.Matchers\n\nimport tywaves.simulator._\nimport tywaves.simulator.ParametricSimulator._\nimport tywaves.simulator.simulatorSettings._\nimport chisel3._\n//import chisel3._\nclass GCDTest extends AnyFunSpec with Matchers {\n describe(\"ParametricSimulator\") {\n it(\"runs GCD correctly\") {\n simulate(new GCD(), Seq(VcdTrace, SaveWorkdirFile(\"gcdWorkDir\"))) { gcd =>\n", "right_context": " gcd.clock.step()\n gcd.io.loadValues.poke(0.B)\n gcd.clock.stepUntil(sentinelPort = gcd.io.resultIsValid, sentinelValue = 1, maxCycles = 10)\n gcd.io.resultIsValid.expect(true.B)\n gcd.io.result.expect(12)\n }\n }\n }\n\n describe(\"TywavesSimulator\") {\n it(\"runs GCD correctly\") {\n import TywavesSimulator._\n\n simulate(\n new GCD(),\n Seq(VcdTrace, WithTywavesWaveforms(false), WithFirtoolArgs(Seq(\"-g\", \"--emit-hgldd\")), SaveWorkdir),\n simName = \"runs_GCD_correctly\",\n ) {\n gcd =>\n gcd.io.a.poke(24.U)\n gcd.io.b.poke(36.U)\n gcd.io.loadValues.poke(1.B)\n gcd.clock.step()\n gcd.io.loadValues.poke(0.B)\n gcd.clock.stepUntil(sentinelPort = gcd.io.resultIsValid, sentinelValue = 1, maxCycles = 10)\n gcd.io.resultIsValid.expect(true.B)\n gcd.io.result.expect(12)\n }\n }\n }\n\n}\n", "groundtruth": " gcd.io.a.poke(24.U)\n gcd.io.b.poke(36.U)\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/hierarchicalmodules/Blink.scala", "left_context": "package hierarchicalmodules\n\nimport chisel3._\nimport chisel3.util.Counter\n\nclass Blink(period: Int) extends Module {\n assert(period > 0, \"limit must be greater than 0\")\n val io = IO(new Bundle {\n val enable: Bool = Input(Bool())\n val led: Bool = Output(Bool())\n })\n\n val cnt: Counter = Counter(period)\n val ledReg: Bool = RegInit(false.B)\n\n", "right_context": "object MainBlink extends App {\n import circt.stage.ChiselStage\n\n println(\n ChiselStage.emitSystemVerilog(\n new Blink(4),\n firtoolOpts = Array(\n \"-O=debug\",\n \"-g\",\n \"--disable-all-randomization\",\n \"--strip-debug-info\",\n ),\n )\n )\n}\n", "groundtruth": " when(io.enable) {\n when(cnt.inc() && cnt.value === (period - 1).U) {\n ledReg := ~ledReg\n }\n }\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/hierarchicalmodules/BlinkTest.scala", "left_context": "package hierarchicalmodules\n\nimport chisel3.fromBooleanToLiteral\nimport org.scalatest.funspec.AnyFunSpec\nimport org.scalatest.matchers.must.Matchers\n\nclass BlinkTest extends AnyFunSpec with Matchers {\n\n private def blinkTb(dut: => Blink): Unit = {\n import chisel3.simulator.PeekPokeAPI._\n dut.reset.poke(true.B)\n dut.io.enable.poke(true.B)\n dut.clock.step(5)\n dut.reset.poke(false.B)\n\n dut.io.led.expect(false.B)\n dut.clock.step() // 1\n dut.io.led.expect(false.B)\n dut.clock.step() // 2\n dut.io.led.expect(false.B)\n dut.clock.step() // 3\n dut.io.led.expect(false.B)\n dut.clock.step() // 4\n dut.io.led.expect(true.B)\n dut.clock.step() // 5\n dut.io.led.expect(true.B)\n dut.clock.step() // 6\n dut.io.led.expect(true.B)\n dut.clock.step()\n dut.clock.step(30)\n }\n\n describe(\"Blink with parametric simulator\") {\n import tywaves.simulator.ParametricSimulator._\n import tywaves.simulator.simulatorSettings._\n\n it(\"should work\") {\n simulate(\n new Blink(4),\n Seq(VcdTrace, WithFirtoolArgs(Seq(\"-O=debug\", \"-g\"))),\n simName = \"blink_with_parametric_sim_should_work\",\n ) { dut =>\n blinkTb(dut)\n }\n }\n } // end of describe(\"Blink with parametric simulator\")\n\n describe(\"Blink with tywaves simulator\") {\n import tywaves.simulator.TywavesSimulator._\n import tywaves.simulator.simulatorSettings._\n\n it(\"should work\") {\n simulate(\n new Blink(4),\n Seq(VcdTrace, WithTywavesWaveforms(false), SaveWorkdirFile(\"workdir\")),\n", "right_context": "", "groundtruth": " simName = \"blink_with_tywaves_sim_should_work\",\n ) { dut =>\n blinkTb(dut)\n }\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/hierarchicalmodules/MultiBlink.scala", "left_context": "package hierarchicalmodules\n\nimport chisel3._\n\nclass SubBlink(n: Int) extends Module {\n val io = IO(new Bundle {\n val enable = Input(Bool())\n val led = Output(Bool())\n })\n val blinkerx = Module(new Blink(n))\n\n blinkerx.io.enable := io.enable\n io.led := blinkerx.io.led\n}\n\nclass AnotherModule extends Module {\n val out = IO(Output(UInt(2.W)))\n\n val outReg = RegInit(false.B)\n outReg := ~outReg\n out := outReg\n}\nclass AMultiBlink extends Module {\n val io = IO(new Bundle {\n val enable: Bool = Input(Bool())\n val leds: UInt = Output(UInt(4.W))\n })\n\n val anotherModule: AnotherModule = Module(new AnotherModule)\n\n val blinker: SubBlink = Module(new SubBlink(5))\n val blinker2: Blink = Module(new Blink(3))\n val blinker3: Blink = Module(new Blink(2))\n\n blinker.io.enable := io.enable\n blinker2.io.enable := io.enable\n blinker3.io.enable := io.enable\n\n when(anotherModule.out === 1.U) {\n blinker.io.enable := false.B\n blinker2.io.enable := false.B\n }\n io.leds :=\n (blinker.io.led << 3).asUInt + (blinker.io.led << 2).asUInt + (blinker.io.led << 1).asUInt + (blinker.io.led << 0).asUInt\n\n}\n\nobject MainMultiBlink extends App {\n import circt.stage.ChiselStage\n\n println(\n", "right_context": " )\n}\n", "groundtruth": " ChiselStage.emitSystemVerilog(\n new AMultiBlink,\n firtoolOpts = Array(\n \"-O=debug\",\n \"-g\",\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/hierarchicalmodules/MultiBlinkTest.scala", "left_context": "package hierarchicalmodules\n\nimport chisel3.fromBooleanToLiteral\nimport org.scalatest.funspec.AnyFunSpec\nimport org.scalatest.matchers.must.Matchers\n\nclass MultiBlinkTest extends AnyFunSpec with Matchers {\n\n private def blinkTb(dut: => AMultiBlink): Unit = {\n import chisel3.simulator.PeekPokeAPI._\n dut.reset.poke(true.B)\n dut.io.enable.poke(false.B)\n dut.clock.step(5)\n dut.reset.poke(false.B)\n dut.io.enable.poke(true.B)\n\n dut.clock.step() // 1\n dut.clock.step() // 2\n dut.clock.step() // 3\n dut.clock.step() // 4\n", "right_context": "\n describe(\"Multi Blink with parametric simulator\") {\n import tywaves.simulator.ParametricSimulator._\n import tywaves.simulator.simulatorSettings._\n\n it(\"should work\") {\n simulate(\n new AMultiBlink,\n Seq(VcdTrace, WithFirtoolArgs(Seq(\"-O=debug\", \"-g\"))),\n simName = \"multiblink_with_parametric_sim_should_work\",\n ) { dut =>\n blinkTb(dut)\n }\n }\n } // end of describe(\"MultiBlink with parametric simulator\")\n\n describe(\"MultiBlink with tywaves simulator\") {\n import tywaves.simulator.TywavesSimulator._\n import tywaves.simulator.simulatorSettings._\n\n it(\"should work\") {\n simulate(\n new AMultiBlink,\n Seq(VcdTrace, WithTywavesWaveforms(false), SaveWorkdirFile(\"workdir\")),\n simName = \"multiblink_with_tywaves_sim_should_work\",\n ) { dut =>\n blinkTb(dut)\n }\n }\n } // end of describe(\"Blink with tywaves simulator\")\n}\n", "groundtruth": " dut.clock.step() // 5\n dut.clock.step() // 6\n dut.clock.step()\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/hierarchicalmodules/UseCounter.scala", "left_context": "package hierarchicalmodules\n\nimport chisel3.{Bits, Data, Module, Printable, UInt, UIntFactory, Wire, dontTouch, fromBooleanToLiteral, fromIntToWidth}\nimport chisel3.util.Counter\nimport org.scalatest.funspec.AnyFunSpec\nimport org.scalatest.matchers.must.Matchers\nimport tywaves.simulator.TraceVcd\n\nclass UseCounter extends AnyFunSpec with Matchers {\n\n class Char {\n val value: UInt = UInt(8.W)\n\n", "right_context": " }\n object Char {\n def apply(): Char = new Char\n }\n\n class MyCounter extends Module {\n import chisel3._\n\n val out: UInt = IO(Output(UInt(8.W)))\n\n val cnt: Counter = Counter(4)\n\n cnt.inc()\n out := cnt.value\n }\n\n describe(\"Blink with tywaves simulator\") {\n import tywaves.simulator.TywavesSimulator._\n import tywaves.simulator.simulatorSettings._\n\n it(\"should work\") {\n simulate(\n new MyCounter,\n Seq(VcdTrace, WithTywavesWaveforms(false), SaveWorkdirFile(\"workdir\")),\n simName = \"blink_with_tywaves_sim_should_work\",\n ) { dut =>\n dut.clock.step(10)\n }\n }\n }\n}\n", "groundtruth": " def apply: UInt = value\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/memories/BlockMem.scala", "left_context": "package memories\n\nimport chisel3._\nimport chisel3.util.log2Ceil\n\n\nclass MemIOBundle[T <: Data](depth: Int, t: T) extends Bundle {\n val rdAddr = Input(UInt(log2Ceil(depth).W))\n val rdData = Output(t)\n val wrEna = Input(Bool())\n val wrData = Input(t)\n", "right_context": "/** A simple module for testing memories in Tywaves */\nclass BlockMem[T <: Data](depth: Int, t: T) extends Module {\n val io = IO(new MemIOBundle(depth, t))\n\n val mem = SyncReadMem(depth, t)\n io.rdData := mem.read(io.rdAddr)\n\n when(io.wrEna) {\n mem.write(io.wrAddr, io.wrData)\n }\n}\n\n", "groundtruth": " val wrAddr = Input(UInt(log2Ceil(depth).W))\n}\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/memories/BlockMemTest.scala", "left_context": "package memories\n\nimport org.scalatest.funspec.AnyFunSpec\nimport org.scalatest.matchers.must.Matchers\n\nimport tywaves.simulator._\nimport tywaves.simulator.simulatorSettings._\nimport chisel3._\n\nclass BlockMemTest extends AnyFunSpec with Matchers {\n describe(\"TywavesSimulator\") {\n import TywavesSimulator._\n\n it(\"runs BlockMem of UInt8\") {\n val t = UInt(8.W)\n simulate(new BlockMem(15, t), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = \"runs_mem_uint8\")(dut =>\n dut.clock.step(2)\n )\n }\n\n it(\"runs BlockMem of Bundle\") {\n\n class ComplexElement extends Bundle {\n val a = new Bundle {\n val subA1 = UInt(8.W)\n val subA2 = SInt(8.W)\n }\n val payload = Bits(8.W)\n }\n\n val t = new ComplexElement\n simulate(\n new BlockMem(4, t),\n Seq(VcdTrace, WithTywavesWaveforms(false), SaveWorkdirFile(\"workdir\")),\n simName = \"runs_mem_bundle\",\n )(dut => dut.clock.step(2))\n }\n\n it(\"runs BlockMem of Vec\") {\n val t = Vec(4, UInt(8.W))\n simulate(new BlockMem(4, t), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = \"runs_mem_vec\")(dut =>\n dut.clock.step(2)\n )\n }\n\n it(\"runs BlockMem of Enum\") {\n object SelType extends ChiselEnum { val A, B, C = Value }\n val t = SelType()\n simulate(new BlockMem(4, t), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = \"runs_mem_enum\")(dut =>\n dut.clock.step(2)\n )\n }\n\n it(\"runs BlockMem of Enum in Bundle\") {\n object SelType extends ChiselEnum { val A, B, C = Value }\n class ComplexElement extends Bundle {\n val sel = SelType()\n val payload = Bits(8.W)\n }\n\n val t = new ComplexElement\n simulate(new BlockMem(4, t), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = \"runs_mem_enum_bundle\")(dut =>\n dut.clock.step(2)\n )\n }\n\n it(\"runs BlockMem of Enum in Vec\") {\n", "right_context": " val t = Vec(4, SelType())\n simulate(new BlockMem(4, t), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = \"runs_mem_enum_vec\")(dut =>\n dut.clock.step(2)\n )\n }\n\n it(\"runs BlockMem of Enum in 2D-Vec\") {\n<TARGET>\n val t = Vec(4, Vec(2, SelType()))\n simulate(new BlockMem(4, t), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = \"runs_mem_enum_2d_vec\")(dut =>\n dut.clock.step(2)\n )\n }\n\n }\n}\n", "groundtruth": " object SelType extends ChiselEnum { val A, B, C = Value }\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/tywaves/simulator/ImportSimulatorReverseOrder.scala", "left_context": "package tywaves.simulator\n\nimport gcd.GCD\nimport org.scalatest.funspec.AnyFunSpec\nimport org.scalatest.matchers.must.Matchers\n\nclass ImportSimulatorReverseOrder extends AnyFunSpec with Matchers {\n", "right_context": " gcd.io.loadValues.poke(true.B)\n }\n }\n it(\"Should import chisel after tywaves\") {\n import tywaves.simulator.TywavesSimulator._\n import chisel3._\n simulate(new GCD()) {\n gcd =>\n gcd.clock.step()\n gcd.io.loadValues.poke(true.B)\n }\n }\n }\n\n}\n", "groundtruth": " describe(\"Issue 27\") {\n it(\"Should import chisel before tywaves\") {\n import chisel3._\n import tywaves.simulator.TywavesSimulator._\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/tywaves/simulator/ParametricSimulatorSpec.scala", "left_context": "package tywaves.simulator\n\nimport tywaves.simulator.ParametricSimulator._\nimport tywaves.simulator.simulatorSettings._\nimport chisel3._\nimport org.scalatest.funspec.AnyFunSpec\nimport org.scalatest.matchers.must.Matchers\n\nimport java.nio.file.{Files, Paths}\n\nimport gcd.GCD\n\nclass ParametricSimulatorSpec extends AnyFunSpec with Matchers {\n\n private def gcdTb(gcd: => GCD): Unit = {\n gcd.io.a.poke(24.U)\n gcd.io.b.poke(36.U)\n gcd.io.loadValues.poke(1.B)\n gcd.clock.step()\n gcd.io.loadValues.poke(0.B)\n gcd.clock.stepUntil(sentinelPort = gcd.io.resultIsValid, sentinelValue = 1, maxCycles = 10)\n gcd.io.resultIsValid.expect(true.B)\n gcd.io.result.expect(12)\n }\n\n describe(\"ParametricSimulator Runs\") {\n\n it(\"runs GCD correctly without settings\") {\n simulate(new GCD())(gcd => gcdTb(gcd))\n }\n\n it(\"runs GCD with VCD trace file\") {\n simulate(new GCD(), Seq(VcdTrace))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/ParametricSimulator/defaultSimulation/trace.vcd\")))\n }\n\n it(\"runs GCD with VCD underscore trace\") {\n simulate(new GCD(), Seq(VcdTraceWithUnderscore))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/ParametricSimulator/defaultSimulation/trace_underscore.vcd\")))\n }\n\n it(\"runs GCD with VCD trace file with name\") {\n simulate(new GCD(), Seq(VcdTrace, NameTrace(\"gcdTbTraceName\")))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/ParametricSimulator/defaultSimulation/gcdTbTraceName.vcd\")))\n }\n\n it(\"runs underscore when VcdTrace and VcdTraceWithUnderscore are used\") {\n simulate(new GCD(), Seq(VcdTrace, VcdTraceWithUnderscore))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/ParametricSimulator/defaultSimulation/trace_underscore.vcd\")))\n\n simulate(new GCD(), Seq(VcdTraceWithUnderscore, VcdTrace))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/ParametricSimulator/defaultSimulation/trace_underscore.vcd\")))\n }\n\n it(\"runs GCD with VCD trace file with name and VCD underscore trace\") {\n simulate(new GCD(), Seq(VcdTrace, VcdTraceWithUnderscore, NameTrace(\"gcdTb1\")))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/ParametricSimulator/defaultSimulation/gcdTb1_underscore.vcd\")))\n\n simulate(new GCD(), Seq(VcdTraceWithUnderscore, VcdTrace, NameTrace(\"gcdTb2\")))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/ParametricSimulator/defaultSimulation/gcdTb2_underscore.vcd\")))\n\n simulate(new GCD(), Seq(NameTrace(\"gcdTb3\"), VcdTraceWithUnderscore, VcdTrace))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/ParametricSimulator/defaultSimulation/gcdTb3_underscore.vcd\")))\n }\n\n it(\"uses a name for the simulation\") {\n simulate(new GCD(), Seq(VcdTrace, NameTrace(\"gcdTb1\")), simName = \"use_a_name_for_the_simulation\")(gcd =>\n gcdTb(gcd)\n )\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/ParametricSimulator/use_a_name_for_the_simulation/gcdTb1.vcd\")))\n }\n\n", "right_context": " gcdTb(gcd)\n )\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/ParametricSimulator/defaultSimulation/myWorkdir2\")))\n assert(Files.exists(\n Paths.get(\"test_run_dir/GCD/ParametricSimulator/defaultSimulation/myWorkdir2/support-artifacts/GCD.dd\")\n ))\n }\n\n }\n\n describe(\"ParametricSimulator Exceptions\") {\n\n it(\"throws an exception when NameTrace is used without VcdTrace or VcdTraceWithUnderscore\") {\n intercept[Exception] {\n simulate(new GCD(), Seq(NameTrace(\"\")))(_ => gcdTb _)\n }\n }\n\n it(\"throws an exception with two or more NameTrace\") {\n intercept[Exception] {\n simulate(new GCD(), Seq(VcdTrace, NameTrace(\"a\"), NameTrace(\"b\")))(_ => gcdTb _)\n }\n }\n\n it(\"throws an exception with two or more SaveWorkdir\") {\n intercept[Exception] {\n simulate(new GCD(), Seq(SaveWorkdir, SaveWorkdir))(_ => gcdTb _)\n }\n }\n\n it(\"throws an exception with two or more SaveWorkdirFile\") {\n intercept[Exception] {\n simulate(new GCD(), Seq(SaveWorkdirFile(\"a\"), SaveWorkdirFile(\"b\")))(_ => gcdTb _)\n }\n }\n\n }\n}\n", "groundtruth": " it(\"save the workdir with a name\") {\n simulate(new GCD(), Seq(VcdTrace, SaveWorkdirFile(\"myWorkdir\")))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/ParametricSimulator/defaultSimulation/myWorkdir\")))\n }\n", "crossfile_context": ""}
	{"task_id": "tywaves-chisel", "path": "tywaves-chisel/src/test/scala/tywaves/simulator/TywavesSimulatorSpec.scala", "left_context": "package tywaves.simulator\n\nimport tywaves.simulator.TywavesSimulator._\nimport tywaves.simulator.simulatorSettings._\nimport chisel3._\nimport gcd.GCD\nimport org.scalatest.funspec.AnyFunSpec\nimport org.scalatest.matchers.must.Matchers\n\nimport java.nio.file.{Files, Paths}\n\nclass TywavesSimulatorSpec extends AnyFunSpec with Matchers {\n\n private def gcdTb(gcd: => GCD): Unit = {\n gcd.io.a.poke(24.U)\n gcd.io.b.poke(36.U)\n gcd.io.loadValues.poke(1.B)\n gcd.clock.step()\n gcd.io.loadValues.poke(0.B)\n gcd.clock.stepUntil(sentinelPort = gcd.io.resultIsValid, sentinelValue = 1, maxCycles = 10)\n gcd.io.resultIsValid.expect(true.B)\n gcd.io.result.expect(12)\n }\n\n describe(\"New TywavesFunctionalities\") {\n\n it(\"runs GCD with waveform generation\") {\n simulate(new GCD(), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = \"runs_gcd_with_waveform_generation\") {\n gcd =>\n gcdTb(gcd)\n }\n\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/TywavesSimulator/runs_gcd_with_waveform_generation/trace.vcd\")))\n assert(Files.exists(\n Paths.get(\n \"test_run_dir/GCD/TywavesSimulator/runs_gcd_with_waveform_generation/hgldd/debug/GCD.dd\"\n )\n ))\n }\n\n it(\"runs GCD with waveform generation and custom name trace\") {\n simulate(\n new GCD(),\n Seq(VcdTrace, NameTrace(\"gcdTest\"), WithTywavesWaveforms(false)),\n simName = \"runs_gcd_with_waveform_generation\",\n ) { gcd =>\n gcdTb(gcd)\n }\n\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/TywavesSimulator/runs_gcd_with_waveform_generation/gcdTest.vcd\")))\n assert(Files.exists(\n Paths.get(\n \"test_run_dir/GCD/TywavesSimulator/runs_gcd_with_waveform_generation/hgldd/debug/GCD.dd\"\n )\n ))\n }\n\n it(\"raises an exception when Tywaves is used without VcdTrace\") {\n intercept[Exception] {\n simulate(new GCD(), Seq(WithTywavesWaveforms(false)))(_ => gcdTb _)\n }\n }\n\n }\n\n describe(\"Tywaves with ParametricSimulator Functionalities\") {\n\n it(\"runs GCD correctly without settings\") {\n simulate(new GCD())(gcd => gcdTb(gcd))\n }\n\n it(\"runs GCD with VCD trace file\") {\n simulate(new GCD(), Seq(VcdTrace))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/TywavesSimulator/defaultSimulation/trace.vcd\")))\n }\n\n it(\"runs GCD with VCD underscore trace\") {\n simulate(new GCD(), Seq(VcdTraceWithUnderscore))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/TywavesSimulator/defaultSimulation/trace_underscore.vcd\")))\n }\n\n it(\"runs GCD with VCD trace file with name\") {\n simulate(new GCD(), Seq(VcdTrace, NameTrace(\"gcdTbTraceName\")))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/TywavesSimulator/defaultSimulation/gcdTbTraceName.vcd\")))\n }\n\n it(\"runs underscore when VcdTrace and VcdTraceWithUnderscore are used\") {\n simulate(new GCD(), Seq(VcdTrace, VcdTraceWithUnderscore))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/TywavesSimulator/defaultSimulation/trace_underscore.vcd\")))\n\n simulate(new GCD(), Seq(VcdTraceWithUnderscore, VcdTrace))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/TywavesSimulator/defaultSimulation/trace_underscore.vcd\")))\n }\n\n it(\"runs GCD with VCD trace file with name and VCD underscore trace\") {\n simulate(new GCD(), Seq(VcdTrace, VcdTraceWithUnderscore, NameTrace(\"gcdTb1\")))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/TywavesSimulator/defaultSimulation/gcdTb1_underscore.vcd\")))\n\n simulate(new GCD(), Seq(VcdTraceWithUnderscore, VcdTrace, NameTrace(\"gcdTb2\")))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/TywavesSimulator/defaultSimulation/gcdTb2_underscore.vcd\")))\n\n simulate(new GCD(), Seq(NameTrace(\"gcdTb3\"), VcdTraceWithUnderscore, VcdTrace))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/TywavesSimulator/defaultSimulation/gcdTb3_underscore.vcd\")))\n }\n\n it(\"uses a name for the simulation\") {\n", "right_context": " simulate(new GCD(), Seq(VcdTrace, SaveWorkdirFile(\"myWorkdir\")))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/TywavesSimulator/defaultSimulation/myWorkdir\")))\n }\n\n it(\"uses firtool args\") {\n simulate(new GCD(), Seq(WithFirtoolArgs(Seq(\"-g\", \"--emit-hgldd\")), SaveWorkdirFile(\"myWorkdir2\")))(gcd =>\n gcdTb(gcd)\n )\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/TywavesSimulator/defaultSimulation/myWorkdir2\")))\n assert(Files.exists(\n Paths.get(\"test_run_dir/GCD/TywavesSimulator/defaultSimulation/myWorkdir2/support-artifacts/GCD.dd\")\n ))\n }\n\n }\n\n describe(\"TywavesSimulator Exceptions\") {\n it(\"throws an exception when NameTrace is used without VcdTrace or VcdTraceWithUnderscore\") {\n intercept[Exception] {\n simulate(new GCD(), Seq(NameTrace(\"\")))(_ => gcdTb _)\n }\n }\n\n it(\"throws an exception with two or more NameTrace\") {\n intercept[Exception] {\n simulate(new GCD(), Seq(VcdTrace, NameTrace(\"a\"), NameTrace(\"b\")))(_ => gcdTb _)\n }\n }\n\n it(\"throws an exception with two or more SaveWorkdir\") {\n intercept[Exception] {\n simulate(new GCD(), Seq(SaveWorkdir, SaveWorkdir))(_ => gcdTb _)\n }\n }\n\n it(\"throws an exception with two or more SaveWorkdirFile\") {\n intercept[Exception] {\n simulate(new GCD(), Seq(SaveWorkdirFile(\"a\"), SaveWorkdirFile(\"b\")))(_ => gcdTb _)\n }\n }\n\n }\n}\n", "groundtruth": " simulate(new GCD(), Seq(VcdTrace, NameTrace(\"gcdTb1\")), simName = \"use_a_name_for_the_simulation\")(gcd =>\n gcdTb(gcd)\n )\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/TywavesSimulator/use_a_name_for_the_simulation/gcdTb1.vcd\")))\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ethcontroller/design/EthRxController.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.design\n\nimport Chisel._\nimport ethcontroller.interfaces.MIIChannel\nimport ethcontroller.protocols.EthernetConstants\nimport ocp._\n\n/*\n The RX channel of the Ethernet controller manages both\n * the RX MII channel and implements FIFO access to the connected buffers\n \n @param numFrameBuffers the numbers of buffers used\n * @param timeStampWidth the timestamp bit-width\n /\nclass EthRxController(numFrameBuffers: Int, timeStampWidth: Int) extends Module {\n val io = new Bundle() {\n val ocp = new OcpCoreSlavePort(32, 32)\n val ramPorts = Vec.fill(numFrameBuffers) {\n new OcpCoreMasterPort(32, 32)\n }\n val miiChannel = new MIIChannel().asInput\n val rtcTimestamp = UInt(INPUT, width = timeStampWidth)\n }\n\n /\n Constants and types defs\n /\n val constRamIdWidth = log2Ceil(numFrameBuffers)\n val constRamAddrWidth = log2Ceil(EthernetConstants.constEthFrameLength)\n val stWaitSFD :: stCollectPayload :: Nil = Enum(UInt(), 2)\n val miiRx = Module(new MIIRx())\n\n /\n Registers\n /\n val stateReg = Reg(init = stWaitSFD)\n val ethByteReg = RegEnable(miiRx.io.ethByte, miiRx.io.ethByteDv)\n val ethByteDvReg = Reg(next = miiRx.io.ethByteDv)\n val ocpMasterReg = Reg(next = io.ocp.M)\n val wrRamIdReg = Reg(init = UInt(0, width = constRamIdWidth))\n val rdRamIdReg = Reg(init = UInt(0, width = constRamIdWidth))\n val byteCntReg = Reg(init = UInt(0, width = constRamAddrWidth))\n val ramMasterRegs = Vec.fill(numFrameBuffers) {\n Reg(new OcpCoreMasterSignals(constRamAddrWidth, 32))\n }\n val ocpDataReg = Reg(init = Bits(0, width = 32))\n val ocpRespReg = Reg(init = OcpResp.NULL)\n val rxEnReg = Reg(init = true.B)\n val rxFrameSizeReg = Reg(init = UInt(0, width = constRamAddrWidth)) //bytes\n val fifoCountReg = Reg(init = UInt(0, width = constRamIdWidth + 1))\n val fifoEmptyReg = Reg(init = true.B)\n val fifoFullReg = Reg(init = false.B)\n val fifoPopReg = Reg(init = false.B)\n val fifoPushReg = Reg(init = false.B)\n val macRxFilterReg = Reg(init = UInt(0, width = EthernetConstants.constEthMacLength))\n val ethRxCtrlRegMap = Map(\n \"rxEn\" -> Map(\"Reg\" -> rxEnReg, \"Addr\" -> Bits(\"h00\")),\n \"frameSize\" -> Map(\"Reg\" -> rxFrameSizeReg, \"Addr\" -> Bits(\"h01\")),\n \"fifoCount\" -> Map(\"Reg\" -> fifoCountReg, \"Addr\" -> Bits(\"h02\")),\n \"fifoEmpty\" -> Map(\"Reg\" -> fifoEmptyReg, \"Addr\" -> Bits(\"h03\")),\n \"fifoFull\" -> Map(\"Reg\" -> fifoFullReg, \"Addr\" -> Bits(\"h04\")),\n \"fifoPop\" -> Map(\"Reg\" -> fifoPopReg, \"Addr\" -> Bits(\"h05\")),\n \"fifoPush\" -> Map(\"Reg\" -> fifoPushReg, \"Addr\" -> Bits(\"h06\")),\n \"macFilter\" -> Map(\"Reg\" -> macRxFilterReg, \"Addr\" -> Bits(\"h07\"))\n )\n\n\n /\n Fifo Management\n /\n fifoEmptyReg := fifoCountReg === 0.U\n fifoFullReg := fifoCountReg === numFrameBuffers.U\n\n /\n State machine Control\n /\n val ramWrSelOH = UIntToOH(wrRamIdReg)\n val ramRdSelOH = UIntToOH(rdRamIdReg)\n\n val ocpSelRam = ~ocpMasterReg.Addr(constRamAddrWidth) && ocpMasterReg.Cmd =/= OcpCmd.IDLE\n val validRamPop = fifoPopReg && !fifoEmptyReg\n val validRamPush = fifoPushReg && !fifoFullReg\n\n val ethRamWrEn = ethByteDvReg && stateReg === stCollectPayload\n val ocpRamRdEn = ocpMasterReg.Cmd === OcpCmd.RD && ocpSelRam\n\n fifoPushReg := false.B\n fifoPopReg := false.B\n switch(stateReg) {\n is(stWaitSFD) {\n when(miiRx.io.ethSof && !fifoFullReg) {\n stateReg := stCollectPayload\n }\n }\n is(stCollectPayload) {\n when(miiRx.io.ethEof) {\n stateReg := stWaitSFD\n rxFrameSizeReg := byteCntReg\n byteCntReg := 0.U\n fifoPushReg := true.B\n }\n }\n }\n\n when(ethRamWrEn) {\n byteCntReg := byteCntReg + 1.U\n }\n\n\n when(validRamPop) {\n rdRamIdReg := rdRamIdReg + 1.U\n fifoCountReg := fifoCountReg - 1.U\n }\n\n when(validRamPush) {\n wrRamIdReg := wrRamIdReg + 1.U\n fifoCountReg := fifoCountReg + 1.U\n }\n\n /\n Ram Master Control\n /\n for (ramId <- 0 until numFrameBuffers) {\n ramMasterRegs(ramId).Addr := RegNext(Mux(ramId.U === wrRamIdReg && ocpSelRam, byteCntReg(constRamAddrWidth - 1, 2), ocpMasterReg.Addr(constRamAddrWidth - 1, 2)))\n ramMasterRegs(ramId).ByteEn := RegNext(Mux(ramId.U === wrRamIdReg && ocpSelRam, UIntToOH(byteCntReg(1, 0), width = 4), Mux(ocpRamRdEn, ocpMasterReg.ByteEn, Bits(\"b0000\"))))\n", "right_context": "\n /\n Regs Master Control\n /\n ocpRespReg := OcpResp.NULL\n when(ocpSelRam) {\n ocpDataReg := io.ramPorts(rdRamIdReg).S.Data\n ocpRespReg := Mux(!fifoFullReg, io.ramPorts(rdRamIdReg).S.Resp, OcpResp.FAIL)\n }.otherwise {\n when(ocpMasterReg.Cmd === OcpCmd.RD) {\n ocpRespReg := OcpResp.DVA\n when(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"rxEn\")(\"Addr\")) {\n ocpDataReg := ethRxCtrlRegMap(\"rxEn\")(\"Reg\")\n }.elsewhen(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"frameSize\")(\"Addr\")) {\n ocpDataReg := ethRxCtrlRegMap(\"frameSize\")(\"Reg\")\n }.elsewhen(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"fifoCount\")(\"Addr\")) {\n ocpDataReg := ethRxCtrlRegMap(\"fifoCount\")(\"Reg\")\n }.elsewhen(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"fifoEmpty\")(\"Addr\")) {\n ocpDataReg := ethRxCtrlRegMap(\"fifoEmpty\")(\"Reg\")\n }.elsewhen(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"fifoFull\")(\"Addr\")) {\n ocpDataReg := ethRxCtrlRegMap(\"fifoFull\")(\"Reg\")\n }.elsewhen(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"fifoPop\")(\"Addr\")) {\n ocpDataReg := ethRxCtrlRegMap(\"fifoPop\")(\"Reg\")\n }.elsewhen(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"fifoPush\")(\"Addr\")) {\n ocpDataReg := ethRxCtrlRegMap(\"fifoPush\")(\"Reg\")\n }.elsewhen(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"macFilter\")(\"Addr\")) {\n ocpDataReg := ethRxCtrlRegMap(\"macFilter\")(\"Reg\")\n }\n }.elsewhen(ocpMasterReg.Cmd === OcpCmd.WR) {\n when(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"rxEn\")(\"Addr\")) {\n ethRxCtrlRegMap(\"rxEn\")(\"Reg\") := ocpMasterReg.Data.orR\n ocpRespReg := OcpResp.DVA\n }.elsewhen(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"frameSize\")(\"Addr\")) {\n ocpRespReg := OcpResp.ERR\n }.elsewhen(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"fifoCount\")(\"Addr\")) {\n ocpRespReg := OcpResp.ERR\n }.elsewhen(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"fifoEmpty\")(\"Addr\")) {\n ocpRespReg := OcpResp.ERR\n }.elsewhen(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"fifoFull\")(\"Addr\")) {\n ocpRespReg := OcpResp.ERR\n }.elsewhen(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"fifoPop\")(\"Addr\")) {\n ethRxCtrlRegMap(\"fifoPop\")(\"Reg\") := true.B //set on write and reset in the next clock cycle\n ocpRespReg := OcpResp.DVA //is the responsibility of the master to check first the count ?\n }.elsewhen(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"fifoPush\")(\"Addr\")) {\n ocpRespReg := OcpResp.ERR\n }.elsewhen(ocpMasterReg.Addr(4, 2) === ethRxCtrlRegMap(\"macFilter\")(\"Addr\")) {\n ethRxCtrlRegMap(\"macFilter\")(\"Reg\") := ocpMasterReg.Data\n ocpRespReg := OcpResp.DVA\n }\n }.otherwise {\n ocpRespReg := OcpResp.NULL\n }\n }\n\n /\n I/O plumbing\n */\n io.ocp.S.Data := ocpDataReg\n io.ocp.S.Resp := ocpRespReg\n miiRx.io.miiChannel <> io.miiChannel\n miiRx.io.rxEn := ethRxCtrlRegMap(\"rxEn\")(\"Reg\")\n for (ramId <- 0 until numFrameBuffers) {\n io.ramPorts(ramId).M := ramMasterRegs(ramId)\n }\n}\n\nobject EthRxController extends App {\n chiselMain(Array[String](\"--backend\", \"v\", \"--targetDir\", \"generated/\" + this.getClass.getSimpleName.dropRight(1)),\n () => Module(new EthRxController(2, 64)))\n}\n", "groundtruth": " ramMasterRegs(ramId).Cmd := RegNext(Mux(ramId.U === wrRamIdReg && ocpSelRam, OcpCmd.WR, Mux(ocpRamRdEn, OcpCmd.RD, OcpCmd.IDLE)))\n ramMasterRegs(ramId).Data := RegNext(ethByteReg)\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ethcontroller/design/EthTxController.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.design\n\nimport Chisel._\nimport ethcontroller.interfaces.MIIChannel\nimport ethcontroller.protocols.EthernetConstants\nimport ocp._\n\n/*\n The TX channel of the Ethernet controller manages both\n * the TX MII channel and implements FIFO access to the connected buffers\n \n @param numFrameBuffers the numbers of buffers used\n * @param timeStampWidth the timestamp bit-width\n /\nclass EthTxController(numFrameBuffers: Int, timeStampWidth: Int) extends Module {\n val io = new Bundle() {\n val ocp = new OcpCoreSlavePort(32, 32)\n val ramPorts = Vec.fill(numFrameBuffers) {\n new OcpCoreMasterPort(32, 32)\n }\n val miiChannel = new MIIChannel()\n val rtcTimestamp = UInt(INPUT, width = timeStampWidth)\n }\n\n\n /\n Constants and types defs\n /\n val constRamIdWidth = log2Ceil(numFrameBuffers)\n val constRamAddrWidth = log2Ceil(EthernetConstants.constEthFrameLength)\n val stWait :: stTxPreamble :: stTxFrame :: stTxFCS :: stIFG :: stEoF :: Nil = Enum(UInt(), 6)\n val miiTx = Module(new MIITx())\n\n /\n Registers\n /\n val stateReg = Reg(init = stWait)\n val ocpMasterReg = Reg(next = io.ocp.M)\n val wrRamIdReg = Reg(init = UInt(0, width = constRamIdWidth))\n val rdRamIdReg = Reg(init = UInt(0, width = constRamIdWidth))\n val byteCntReg = Reg(init = UInt(0, width = constRamAddrWidth))\n val ethRamRdEn = Reg(init = false.B)\n val ramMasterRegs = Vec.fill(numFrameBuffers) {\n Reg(new OcpCoreMasterSignals(constRamAddrWidth, 32))\n }\n val ocpDataReg = Reg(init = Bits(0, width = 32))\n val ocpRespReg = Reg(init = OcpResp.NULL)\n\n val ramDataReg = Reg(init = Bits(0, width = 32))\n val ramRespReg = Reg(init = OcpResp.NULL)\n\n val txEnReg = Reg(init = true.B)\n val txFrameSizeReg = Reg(init = UInt(0, width = constRamAddrWidth)) //bytes\n val fifoCountReg = Reg(init = UInt(0, width = constRamIdWidth + 1))\n val fifoEmptyReg = Reg(init = true.B)\n val fifoFullReg = Reg(init = false.B)\n val fifoPopReg = Reg(init = false.B)\n val fifoPushReg = Reg(init = false.B)\n val macRxFilterReg = Reg(init = UInt(0, width = EthernetConstants.constEthMacLength))\n\n val ethTxCtrlRegMap = Map(\n \"txEn\" -> Map(\"Reg\" -> txEnReg, \"Addr\" -> Bits(\"h00\")), //0x0\n \"frameSize\" -> Map(\"Reg\" -> txFrameSizeReg, \"Addr\" -> Bits(\"h04\")), //0x4\n \"fifoCount\" -> Map(\"Reg\" -> fifoCountReg, \"Addr\" -> Bits(\"h08\")), //0x8\n \"fifoEmpty\" -> Map(\"Reg\" -> fifoEmptyReg, \"Addr\" -> Bits(\"h0C\")), //0xC\n \"fifoFull\" -> Map(\"Reg\" -> fifoFullReg, \"Addr\" -> Bits(\"h10\")), //0x10\n \"fifoPop\" -> Map(\"Reg\" -> fifoPopReg, \"Addr\" -> Bits(\"h14\")), //0x14\n \"fifoPush\" -> Map(\"Reg\" -> fifoPushReg, \"Addr\" -> Bits(\"h18\")), //0x18\n \"macFilter\" -> Map(\"Reg\" -> macRxFilterReg, \"Addr\" -> Bits(\"h1C\")) //0x1C\n )\n\n val preambleReg = Reg(init = UInt(EthernetConstants.constSFD, width = 64))\n val fcsReg = Reg(init = UInt(0, width = 16))\n\n val miiByteDataReg = Reg(init = UInt(0, width = 8))\n val miiByteLoadReg = Reg(init = false.B)\n val miiIsReady = Wire(init = false.B)\n\n /\n Fifo Management\n /\n fifoEmptyReg := fifoCountReg === 0.U\n fifoFullReg := fifoCountReg === numFrameBuffers.U\n\n val ocpSelRam = ~ocpMasterReg.Addr(constRamAddrWidth) && ocpMasterReg.Cmd =/= OcpCmd.IDLE\n val validRamPop = fifoPopReg === true.B && !fifoEmptyReg\n val validRamPush = fifoPushReg === true.B && !fifoFullReg\n\n //Reset regs to default values\n fifoPushReg := false.B\n fifoPopReg := false.B\n miiByteLoadReg := false.B\n //State Machine\n switch(stateReg) {\n is(stWait) { //wait for available data in FIFORam\n when(!fifoEmptyReg) {\n stateReg := stTxPreamble\n }\n }\n is(stTxPreamble) {\n when(miiIsReady & ~miiByteLoadReg) { //wait until miiIsReady and then countup the PREAMBLE\n when(byteCntReg < 8.U) {\n miiByteLoadReg := true.B\n byteCntReg := byteCntReg + 1.U\n }.otherwise {\n byteCntReg := 0.U\n ethRamRdEn := true.B\n stateReg := stTxFrame\n }\n }\n }\n is(stTxFrame) {\n when(ramRespReg === OcpResp.DVA) {\n when(miiIsReady) {\n when(byteCntReg < txFrameSizeReg) {\n byteCntReg := byteCntReg + 1.U\n }.otherwise {\n byteCntReg := 0.U\n stateReg := stTxFrame\n }\n }\n }\n }\n is(stTxFCS) {\n when(miiIsReady) {\n when(byteCntReg < 4.U) {\n byteCntReg := byteCntReg + 1.U\n }.otherwise {\n byteCntReg := 0.U\n ethRamRdEn := false.B\n stateReg := stEoF\n }\n }\n }\n is(stEoF) {\n stateReg := stIFG\n }\n is(stIFG) {\n when(byteCntReg < 24.U) {\n byteCntReg := byteCntReg + 1.U\n }.otherwise {\n byteCntReg := 0.U\n stateReg := stWait\n fifoPopReg := true.B\n }\n }\n }\n\n when(validRamPush) {\n wrRamIdReg := wrRamIdReg + 1.U\n fifoCountReg := fifoCountReg + 1.U\n }\n\n when(validRamPop) {\n rdRamIdReg := rdRamIdReg + 1.U\n fifoCountReg := fifoCountReg - 1.U\n }\n\n\n /\n Multiplexing MII byte source\n /\n miiByteDataReg := RegNext(Mux(stateReg === stTxFCS, preambleReg(8.U + 8.U byteCntReg - 1.U, 8.U * byteCntReg),\n Mux(stateReg === stTxFCS, fcsReg(8.U + 8.U * byteCntReg - 1.U, 8.U * byteCntReg), ramDataReg)))\n\n\n /*\n Ram master-port Control\n /\n for (ramId <- 0 until numFrameBuffers) {\n ramMasterRegs(ramId).Cmd := Mux(ramId.U === wrRamIdReg && ocpSelRam, ocpMasterReg.Cmd, Mux(ethRamRdEn, OcpCmd.RD, OcpCmd.IDLE))\n ramMasterRegs(ramId).Addr := Mux(ramId.U === wrRamIdReg && ocpSelRam, ocpMasterReg.Addr(constRamAddrWidth - 1, 2), byteCntReg(constRamAddrWidth - 1, 2))\n ramMasterRegs(ramId).ByteEn := Mux(ramId.U === wrRamIdReg && ocpSelRam, ocpMasterReg.ByteEn, UIntToOH(byteCntReg(1, 0), width = 4))\n ramMasterRegs(ramId).Data := ocpMasterReg.Data\n }\n\n /\n Ram slave-port Control\n /\n ramDataReg := io.ramPorts(rdRamIdReg).S.Data\n ramRespReg := io.ramPorts(rdRamIdReg).S.Resp\n\n /\n Regs Master Control\n /\n ocpRespReg := OcpResp.NULL\n when(ocpSelRam) {\n ocpDataReg := io.ramPorts(wrRamIdReg).S.Data\n ocpRespReg := Mux(!fifoFullReg, io.ramPorts(wrRamIdReg).S.Resp, OcpResp.FAIL)\n }.otherwise {\n when(ocpMasterReg.Cmd === OcpCmd.RD) {\n ocpRespReg := OcpResp.DVA\n when(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"txEn\")(\"Addr\")) {\n ocpDataReg := ethTxCtrlRegMap(\"txEn\")(\"Reg\")\n }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"frameSize\")(\"Addr\")) {\n ocpDataReg := ethTxCtrlRegMap(\"frameSize\")(\"Reg\")\n }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"fifoCount\")(\"Addr\")) {\n ocpDataReg := ethTxCtrlRegMap(\"fifoCount\")(\"Reg\")\n", "right_context": " ocpDataReg := ethTxCtrlRegMap(\"fifoPop\")(\"Reg\")\n }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"fifoPush\")(\"Addr\")) {\n ocpDataReg := ethTxCtrlRegMap(\"fifoPush\")(\"Reg\")\n }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"macFilter\")(\"Addr\")) {\n ocpDataReg := ethTxCtrlRegMap(\"macFilter\")(\"Reg\")\n }\n }.elsewhen(ocpMasterReg.Cmd === OcpCmd.WR) {\n when(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"txEn\")(\"Addr\")) {\n ethTxCtrlRegMap(\"txEn\")(\"Reg\") := orR(ocpMasterReg.Data)\n ocpRespReg := OcpResp.DVA\n }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"frameSize\")(\"Addr\")) {\n ethTxCtrlRegMap(\"frameSize\")(\"Reg\") := ocpDataReg\n ocpRespReg := OcpResp.DVA\n }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"fifoCount\")(\"Addr\")) {\n ocpRespReg := OcpResp.ERR\n }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"fifoEmpty\")(\"Addr\")) {\n ocpRespReg := OcpResp.ERR\n }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"fifoFull\")(\"Addr\")) {\n ocpRespReg := OcpResp.ERR\n }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"fifoPop\")(\"Addr\")) {\n ocpRespReg := OcpResp.ERR\n }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"fifoPush\")(\"Addr\")) {\n ethTxCtrlRegMap(\"fifoPush\")(\"Reg\") := orR(ocpMasterReg.Data) //set on write and reset in the next clock cycle\n ocpRespReg := OcpResp.DVA //is the responsibility of the master to check first the count ?\n }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"macFilter\")(\"Addr\")) {\n ethTxCtrlRegMap(\"macFilter\")(\"Reg\") := ocpMasterReg.Data\n ocpRespReg := OcpResp.DVA\n }\n }.otherwise {\n ocpRespReg := OcpResp.NULL\n }\n }\n\n /\n IO Plumbing\n */\n io.ocp.S.Data := ocpDataReg\n io.ocp.S.Resp := ocpRespReg\n miiIsReady := miiTx.io.ready\n miiTx.io.macDataDv := miiByteLoadReg\n miiTx.io.macData := miiByteDataReg\n miiTx.io.miiChannel <> io.miiChannel\n for (ramId <- 0 until numFrameBuffers) {\n io.ramPorts(ramId).M := ramMasterRegs(ramId)\n }\n}\n\nobject EthTxController extends App {\n chiselMain(Array[String](\"--backend\", \"v\", \"--targetDir\", \"generated/\" + this.getClass.getSimpleName.dropRight(1)),\n () => Module(new EthTxController(2, 64)))\n}\n", "groundtruth": " }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"fifoEmpty\")(\"Addr\")) {\n ocpDataReg := ethTxCtrlRegMap(\"fifoEmpty\")(\"Reg\")\n }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"fifoFull\")(\"Addr\")) {\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ethcontroller/design/MIIRx.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.design\n\nimport Chisel._\nimport ethcontroller.interfaces.MIIChannel\nimport ethcontroller.protocols.EthernetConstants\nimport ethcontroller.utils.{Deserializer, ExtClockSampler}\n\n/*\n The RX MII channel manages the reception of bytes from the PHY\n /\nclass MIIRx extends Module {\n val io = new Bundle() {\n val miiChannel = new MIIChannel().asInput\n val rxEn = Bool(INPUT)\n val phyErr = Bool(OUTPUT)\n val ethSof = Bool(OUTPUT)\n val ethEof = Bool(OUTPUT)\n val ethByte = Bits(OUTPUT, width = 8)\n val ethByteDv = Bool(OUTPUT)\n }\n\n /\n Registers\n /\n val sofReg = Reg(init = Bool(false))\n val eofReg = Reg(init = Bool(false))\n val validPHYDataReg = Reg(init = Bool(false))\n\n /\n Sampling clock and line of MII\n /\n val miiClkSampler = Module(new ExtClockSampler(true, 2))\n miiClkSampler.io.extClk := io.miiChannel.clk\n val miiDvSyncedReg = ShiftRegister(io.miiChannel.dv, 2)\n val miiDataSyncedReg = ShiftRegister(io.miiChannel.data, 2)\n val miiErrSyncedReg = ShiftRegister(io.miiChannel.err, 2)\n\n /\n Flags\n /\n val phyNA = io.miiChannel.col & ~io.miiChannel.crs\n val phyError = phyNA \|\| miiErrSyncedReg\n val validPHYData = miiDvSyncedReg & ~miiErrSyncedReg & ~phyNA\n validPHYDataReg := validPHYData\n val risingMIIEdge = miiClkSampler.io.sampledClk\n\n /\n Buffering PHY bytes\n /\n val deserializePHYByte = Module(new Deserializer(false, 4, 8))\n deserializePHYByte.io.en := io.rxEn & risingMIIEdge & validPHYData\n deserializePHYByte.io.clr := phyError \|\| eofReg\n deserializePHYByte.io.shiftIn := miiDataSyncedReg\n val byteReg = Reg(init = Bits(0, width = 8), next = deserializePHYByte.io.shiftOut)\n val wrByteReg = Reg(init = Bool(false), next = deserializePHYByte.io.done)\n\n /\n Buffer & re-order PHY double-words\n /\n val deserializePHYBuffer = Module(new Deserializer(true, 8, 64))\n deserializePHYBuffer.io.en := deserializePHYByte.io.done\n deserializePHYBuffer.io.clr := phyError \|\| eofReg\n deserializePHYBuffer.io.shiftIn := deserializePHYByte.io.shiftOut\n val regBuffer = Reg(init = Bits(0, width = 64), next = deserializePHYBuffer.io.shiftOut)\n val regBufferDv = Reg(init = Bool(false), next = deserializePHYBuffer.io.done)\n\n /\n Ethernet frame detection logic\n /\n sofReg := false.B\n when(regBuffer === EthernetConstants.constSFD && regBufferDv) {\n sofReg := true.B\n }\n\n eofReg := false.B\n when(validPHYDataReg && ~validPHYData) {\n", "right_context": " }\n\n /\n I/O plumbing\n */\n io.phyErr := phyNA\n io.ethSof := sofReg\n io.ethEof := eofReg\n io.ethByte := byteReg\n io.ethByteDv := wrByteReg\n}\n", "groundtruth": " eofReg := true.B\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ethcontroller/design/MIITx.scala", "left_context": "package ethcontroller.design\n\nimport Chisel._\nimport ethcontroller.interfaces.MIIChannel\nimport ethcontroller.utils.{ExtClockSampler, Serializer}\n\n/*\n The TX MII channel manages the reception of bytes from the PHY\n /\nclass MIITx extends Module {\n val io = new Bundle() {\n val miiChannel = new MIIChannel()\n val macDataDv = Bool(INPUT)\n val macData = Bits(INPUT, width = 8)\n val ready = Bool(OUTPUT)\n val phyErr = Bool(OUTPUT)\n }\n\n /\n Registers and components\n /\n val transmittingReg = Reg(init = false.B)\n\n /\n Sampling clock and line of MII\n /\n val miiClkSampler = Module(new ExtClockSampler(true, 2))\n miiClkSampler.io.extClk := io.miiChannel.clk\n val miiErrSyncedReg = ShiftRegister(io.miiChannel.err, 2)\n val miiDataReg = Reg(init = UInt(0, width = 4))\n val miiDvReg = Reg(init = false.B)\n\n /\n Flags\n /\n val phyNA = io.miiChannel.col & ~io.miiChannel.crs\n val phyError = phyNA \|\| miiErrSyncedReg\n val miiClkEdge = miiClkSampler.io.sampledClk\n\n /\n Serialize Output to Nibble\n /\n val serializeByteToNibble = Module(new Serializer(false, 8, 4))\n serializeByteToNibble.io.load := io.macDataDv\n serializeByteToNibble.io.shiftIn := io.macData\n serializeByteToNibble.io.en := miiClkEdge\n\n", "right_context": "\n /\n Place data on the falling MII clock edge so that they are available on the rising edge\n /\n when(miiClkEdge) {\n //(De-)Assert MII data valid\n when(transmittingReg) {\n miiDvReg := true.B\n }.elsewhen(~transmittingReg) {\n miiDvReg := false.B\n }\n //Data nibble\n miiDataReg := serializeByteToNibble.io.shiftOut\n }\n\n /\n I/O plumbing\n */\n io.ready := ~transmittingReg \|\| ~serializeByteToNibble.io.dv\n io.miiChannel.data := miiDataReg\n io.miiChannel.dv := miiDvReg\n io.phyErr := phyNA\n\n}\n", "groundtruth": " when(~transmittingReg && serializeByteToNibble.io.dv) {\n transmittingReg := true.B\n }.elsewhen(~serializeByteToNibble.io.dv && serializeByteToNibble.io.done) {\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ethcontroller/interfaces/MIIChannel.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.interfaces\n\nimport Chisel.{Bits, Bool, Bundle, INPUT, OUTPUT}\n\nclass MIIChannel extends Bundle {\n /** Clock from the PHY /\n", "right_context": " /* Received nibble data /\n val data = Bits(OUTPUT, width = 4)\n /* Signal could not be decoded to data /\n val err = Bool(INPUT)\n /* Carrier-sense signal /\n val crs = Bool(INPUT)\n /* Collision detection signal /\n val col = Bool(INPUT)\n}\n", "groundtruth": " val clk = Bool(INPUT)\n /* Received data valid */\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ethcontroller/interfaces/PHYChannel.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.interfaces\n\nimport Chisel.{Bool, Bundle, INPUT, OUTPUT}\n\nclass PHYChannel extends Bundle {\n /** Management data clock to the PHY /\n val mdc = Bool(OUTPUT)\n /* Management output data /\n val mdo = Bool(OUTPUT)\n", "right_context": " val md_t = Bool(OUTPUT)\n}\n", "groundtruth": " /* Management input data */\n val mdi = Bool(INPUT)\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ethcontroller/protocols/EthernetConstants.scala", "left_context": "package ethcontroller.protocols\n\nimport Chisel._\n\nobject EthernetConstants {\n\n // Constants\n val constEthFrameLength = 1518 * 8 //bits\n val constEthMacLength = 6 * 8 //bits\n val constFCSLength = 4 * 8 //bits\n val constSFD = Bits(\"h55555555555555D5\", width = 64)\n val constIFG = Bits(\"h0000000000000000\", width = 64)\n", "right_context": " val constVLANt2 = Bits(\"h88A8\", width = 16)\n val constVLANt3 = Bits(\"h9100\", width = 16)\n val constMPLSt1 = Bits(\"h8847\", width = 16)\n val constMPLSt2 = Bits(\"h8848\", width = 16)\n val constIPv4t = Bits(\"h0800\", width = 16)\n val constIPv6t = Bits(\"h86DD\", width = 16)\n val constPTP2t = Bits(\"h88F7\", width = 16)\n val constPTP4t1 = Bits(\"h013F\", width = 16)\n val constPTP4t2 = Bits(\"h0140\", width = 16)\n val constPTPGeneralPort = 319.U\n val constPTPEventPort = 320.U\n val constPTPSyncType = Bits(\"h00\")\n val constPTPFollowType = Bits(\"h08\")\n val constPTPDlyReqType = Bits(\"h01\")\n val constPTPDlyRplyType = Bits(\"h09\")\n\n}\n", "groundtruth": " val constVLANt1 = Bits(\"h8100\", width = 16)\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ethcontroller/protocols/EthernetFrame.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.protocols\n\n/*\n Mockup Ethernet frame\n * Nibbles in the frame are in LSB-first per byte order\n */\nabstract class EthernetFrame {\n\n val PREAMBLE_END = 0xD5\n val IP_UDP_PROTOCOL = 0x11\n val PTP_FOLLOW_UP_TYPE = 0x8\n\n //Vars\n val preamble: Array[Byte]\n val dstMac: Array[Byte]\n val srcMac: Array[Byte]\n val ethType: Array[Byte]\n val data: Array[Byte]\n\n //Special cases\n val ipHeader: Array[Byte]\n val udpHeader: Array[Byte]\n val ptpHeader: Array[Byte]\n val ptpBody: Array[Byte]\n val ptpSuffix: Array[Byte]\n val fcs: Array[Byte]\n val igp: Array[Byte]\n\n //Getters for nibbles\n def preambleNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(preamble, msbFirst = false)\n\n def dstMacNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(dstMac, msbFirst = false)\n\n def srcMacNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(srcMac, msbFirst = false)\n\n", "right_context": "\n def dataNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(data, msbFirst = false)\n\n def ipHeaderNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(ipHeader, msbFirst = false)\n\n def udpHeaderNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(udpHeader, msbFirst = false)\n\n def ptpHeaderNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(ptpHeader, msbFirst = false)\n\n def ptpBodyNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(ptpBody, msbFirst = false)\n\n def ptpSuffixNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(ptpSuffix, msbFirst = false)\n\n def fcsNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(fcs, msbFirst = false)\n\n def igpNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(igp, msbFirst = false)\n}\n", "groundtruth": " def ethTypeNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(ethType, msbFirst = false)\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ethcontroller/protocols/EthernetUtils.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.protocols\n\nobject EthernetUtils {\n /*\n Converts a byte to an array of nibbles\n \n @param byte gets broken down to nibbles\n * @param msbFirst controls the order of the nibbles\n * @return an array of two nibbles\n /\n def byteToNibble(byte: Int, msbFirst: Boolean): Array[Int] = {\n val nibbles = new Array[Int](2)\n nibbles(0) = byte & 0x0F\n nibbles(1) = (byte & 0xF0) >> 4\n if (msbFirst) {\n nibbles.reverse\n } else {\n nibbles\n }\n }\n\n /\n Converts an array of bytes to an array of nibbles\n \n @param bytes the data to be broken down to nibbles\n * @param msbFirst controls the order of the nibbles per byte\n * @return an array of nibbles size bytes.size2\n /\n def dataBytesToNibbles(bytes: Array[Byte], msbFirst: Boolean): Array[Int] = {\n val nibbles = new Array[Int](bytes.length * 2)\n var i = 0\n for (byte <- bytes) {\n val tempByteNibbles = byteToNibble(byte, msbFirst)\n nibbles(i) = tempByteNibbles(0)\n nibbles(i + 1) = tempByteNibbles(1)\n i = i + 2\n }\n nibbles\n }\n\n /*\n Lazy way for converting Integer values in array to bytes\n \n @param xs Integer Array values\n * @return Array of bytes\n /\n", "right_context": "}\n", "groundtruth": " def toBytes(xs: Int) = xs.map(_.toByte).toArray\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ethcontroller/utils/Deserializer.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.utils\n\nimport Chisel._\n\n/*\n Deserialize an M-bit input to an N-bit output based on a specified order\n \n @param inputWidth the bit width of the serial input\n * @param outputWidth the bit width of the parallel\n * @param msbFirst the serial input order\n */\nclass Deserializer(msbFirst: Boolean = false, inputWidth: Int = 4, outputWidth: Int = 8) extends Module {\n val io = new Bundle() {\n val en = Bool(INPUT)\n val clr = Bool(INPUT)\n val shiftIn = Bits(INPUT, width = inputWidth)\n val shiftOut = Bits(OUTPUT, width = outputWidth)\n val done = Bool(OUTPUT)\n }\n\n val shiftReg = Reg(init = Bits(0, width = outputWidth))\n\n // Shift-register\n when(io.clr) {\n shiftReg := 0.U\n }.elsewhen(io.en) {\n if (msbFirst) {\n shiftReg(inputWidth - 1, 0) := io.shiftIn\n shiftReg(outputWidth - 1, inputWidth) := shiftReg(outputWidth - inputWidth - 1, 0)\n", "right_context": "\n val countReg = Reg(init = UInt(outputWidth / inputWidth - 1, width = log2Floor(outputWidth / inputWidth) + 1))\n val doneReg = Reg(init = Bool(false))\n\n // Shift Counter\n when(io.clr) {\n countReg := (outputWidth / inputWidth - 1).U\n doneReg := false.B\n }.elsewhen(io.en) {\n when(countReg === 0.U) {\n countReg := (outputWidth / inputWidth - 1).U\n doneReg := true.B\n }.otherwise {\n countReg := countReg - 1.U\n doneReg := false.B\n }\n }.elsewhen(doneReg) {\n doneReg := false.B\n }\n\n io.shiftOut := shiftReg\n io.done := doneReg\n}\n\nobject Deserializer extends App {\n chiselMain(Array[String](\"--backend\", \"v\", \"--targetDir\", \"generated/\" + this.getClass.getSimpleName.dropRight(1)),\n () => Module(new Deserializer(false, 4, 8)))\n}", "groundtruth": " } else {\n shiftReg(outputWidth - inputWidth - 1, 0) := shiftReg(outputWidth - 1, inputWidth)\n shiftReg(outputWidth - 1, outputWidth - inputWidth) := io.shiftIn\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ethcontroller/utils/ExtClockSampler.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.utils\n\nimport Chisel._\n\n/*\n Synchronizes external clock using a flip-flop synchronizer chain and samples the\n * requested external clock edge\n \n @param sampleRisingEdge if true it samples the rising edge, else the falling edge\n * @param syncChainDepth the number of FF synchronizers to use\n */\nclass ExtClockSampler(sampleRisingEdge: Boolean = true, syncChainDepth: Int = 2) extends Module {\n val io = new Bundle() {\n val extClk = Bool(INPUT)\n val sampledClk = Bool(OUTPUT)\n }\n\n val extClkEdge = Wire(init = false.B) //this will be our sampled edge\n\n val extClkSyncedReg = ShiftRegister(io.extClk, syncChainDepth)\n val extClkSyncedOldReg = Reg(next = extClkSyncedReg)\n", "right_context": "", "groundtruth": "\n if (sampleRisingEdge) {\n extClkEdge := extClkSyncedReg & ~extClkSyncedOldReg //check for a rising edge\n } else {\n extClkEdge := ~extClkSyncedReg & extClkSyncedOldReg //or check for a falling edge\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ethcontroller/utils/Serializer.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.utils\n\nimport Chisel._\n\n/*\n Serializes an M-bit input to an N-bit output based on a specified order\n * after an initial load\n \n @param inputWidth the bit width of the parallel input\n * @param outputWidth the bit width of the serial output\n * @param msbFirst the serial output order\n /\nclass Serializer(msbFirst: Boolean = false, inputWidth: Int = 8, outputWidth: Int = 4) extends Module {\n val io = new Bundle() {\n val load = Bool(INPUT)\n val en = Bool(INPUT)\n val shiftIn = Bits(INPUT, width = inputWidth)\n val shiftOut = Bits(OUTPUT, width = outputWidth)\n val dv = Bool(OUTPUT)\n val done = Bool(OUTPUT)\n }\n\n val constShiftStages = inputWidth / outputWidth\n val shiftReg = Reg(init = Bits(0, width = inputWidth))\n val busyReg = Reg(init = Bool(false))\n val doneReg = Reg(init = Bool(false))\n val countReg = Reg(init = UInt(constShiftStages - 1, width = log2Floor(constShiftStages) + 1))\n val selHi = UInt()\n val selLo = UInt()\n\n // Shift-register\n when(~busyReg && io.load) {\n shiftReg := io.shiftIn\n busyReg := true.B\n doneReg := false.B\n }.elsewhen(io.en && busyReg) {\n when(countReg === 0.U) {\n countReg := (constShiftStages - 1).U\n doneReg := true.B\n", "right_context": " selHi := countReg outputWidth.U + outputWidth.U - 1.U\n selLo := countReg * outputWidth.U\n } else {\n selHi := (constShiftStages.U - 1.U - countReg) * outputWidth.U + outputWidth.U - 1.U\n selLo := (constShiftStages.U - 1.U - countReg) * outputWidth.U\n }\n\n /*\n I/O plumbing\n */\n io.shiftOut := shiftReg(selHi, selLo)\n io.done := doneReg\n io.dv := busyReg\n}\n\nobject Serializer extends App {\n chiselMain(Array[String](\"--backend\", \"v\", \"--targetDir\", \"generated/\" + this.getClass.getSimpleName.dropRight(1)),\n () => Module(new Serializer(false, 8, 4)))\n}\n", "groundtruth": " }.otherwise {\n countReg := countReg - 1.U\n doneReg := false.B\n }\n }.elsewhen(doneReg) {\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ocp/Arbiter.scala", "left_context": "\n/\n Arbiter for OCP burst slaves.\n * Pseudo round robin arbitration. Each turn for a non-requesting master costs 1 clock cycle.\n \n Author: Martin Schoeberl (martin@jopdesign.com)\n \n /\n\npackage ocp\n\nimport Chisel._\n\nclass Arbiter(cnt: Int, addrWidth: Int, dataWidth: Int, burstLen: Int) extends Module {\n // MS: I'm always confused from which direction the name shall be\n // probably the other way round...\n val io = IO(new Bundle {\n val master = Vec.fill(cnt) {\n new OcpBurstSlavePort(addrWidth, dataWidth, burstLen)\n }\n val slave = new OcpBurstMasterPort(addrWidth, dataWidth, burstLen)\n })\n\n val turnReg = Reg(init = UInt(0, log2Up(cnt)))\n val burstCntReg = Reg(init = UInt(0, log2Up(burstLen)))\n\n val sIdle :: sRead :: sWrite :: Nil = Enum(UInt(), 3)\n val stateReg = Reg(init = sIdle)\n\n // buffer signals from master to cut critical paths\n val masterBuffer = Vec(io.master.map { m =>\n val port = new OcpBurstSlavePort(addrWidth, dataWidth, burstLen)\n val bus = Module(new OcpBurstBus(addrWidth, dataWidth, burstLen))\n m <> bus.io.slave\n new OcpBurstBuffer(bus.io.master, port)\n port\n })\n\n val master = masterBuffer(turnReg).M\n\n when(stateReg === sIdle) {\n when(master.Cmd =/= OcpCmd.IDLE) {\n when(master.Cmd === OcpCmd.RD) {\n stateReg := sRead\n }\n when(master.Cmd === OcpCmd.WR) {\n", "right_context": " }\n .otherwise {\n turnReg := Mux(turnReg === UInt(cnt - 1), UInt(0), turnReg + UInt(1))\n }\n }\n when(stateReg === sWrite) {\n // Just wait on the DVA after the write\n when(io.slave.S.Resp === OcpResp.DVA) {\n turnReg := Mux(turnReg === UInt(cnt - 1), UInt(0), turnReg + UInt(1))\n stateReg := sIdle\n }\n }\n when(stateReg === sRead) {\n // For read we have to count the DVAs\n when(io.slave.S.Resp === OcpResp.DVA) {\n burstCntReg := burstCntReg + UInt(1)\n when(burstCntReg === UInt(burstLen) - UInt(1)) {\n turnReg := Mux(turnReg === UInt(cnt - 1), UInt(0), turnReg + UInt(1))\n stateReg := sIdle\n }\n }\n }\n\n io.slave.M := master\n\n for (i <- 0 to cnt - 1) {\n masterBuffer(i).S.CmdAccept := Bits(0)\n masterBuffer(i).S.DataAccept := Bits(0)\n masterBuffer(i).S.Resp := OcpResp.NULL\n // we forward the data to all masters\n masterBuffer(i).S.Data := io.slave.S.Data\n }\n masterBuffer(turnReg).S := io.slave.S\n\n // The response of the SSRAM comes a little bit late\n}\n\nobject ArbiterMain {\n def main(args: Array[String]): Unit = {\n\n val chiselArgs = args.slice(4, args.length)\n val cnt = args(0)\n val addrWidth = args(1)\n val dataWidth = args(2)\n val burstLen = args(3)\n\n chiselMain(chiselArgs, () => Module(new Arbiter(cnt.toInt, addrWidth.toInt, dataWidth.toInt, burstLen.toInt)))\n }\n}\n\n\n", "groundtruth": " stateReg := sWrite\n burstCntReg := UInt(0)\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ocp/NodeTdmArbiter.scala", "left_context": "\n/\n Arbiter for OCP burst slaves.\n * TDM arbitration. Each turn for a non-requesting master costs 16+4+2 clock cycle.\n \n Author: Martin Schoeberl (martin@jopdesign.com) David Chong (davidchong99@gmail.com)\n \n /\n\npackage ocp\n\nimport Chisel._\n\nclass NodeTdmArbiter(cnt: Int, addrWidth: Int, dataWidth: Int, burstLen: Int, ctrlDelay: Int) extends Module {\n // MS: I'm always confused from which direction the name shall be\n // probably the other way round...\n val io = IO(new Bundle {\n val master = new OcpBurstSlavePort(addrWidth, dataWidth, burstLen)\n val slave = new OcpBurstMasterPort(addrWidth, dataWidth, burstLen)\n val node = UInt(INPUT, 6)\n })\n debug(io.master)\n debug(io.slave)\n debug(io.node)\n\n // MS: have all generated constants at one place\n\n val cntReg = Reg(init = UInt(0, log2Up(cnt * (burstLen + ctrlDelay + 1))))\n // slot length = burst size + 1 \n val burstCntReg = Reg(init = UInt(0, log2Up(burstLen)))\n val period = cnt * (burstLen + ctrlDelay + 1)\n val slotLen = burstLen + ctrlDelay + 1\n val numPipe = 3\n\n val wrPipeDelay = burstLen + ctrlDelay + numPipe\n val wrCntReg = Reg(init = UInt(0, log2Up(wrPipeDelay)))\n\n val rdPipeDelay = burstLen + ctrlDelay + numPipe\n val rdCntReg = Reg(init = UInt(0, log2Up(rdPipeDelay)))\n\n // MS: merge rdCntReg and wrCntReg and let it count till slot length\n\n val cpuSlot = Vec.fill(cnt) {\n Reg(init = UInt(0, width = 1))\n }\n\n val sIdle :: sRead :: sWrite :: Nil = Enum(UInt(), 3)\n val stateReg = Reg(init = sIdle)\n\n debug(cntReg)\n for (i <- (0 until cnt))\n debug(cpuSlot(i))\n\n debug(stateReg)\n debug(wrCntReg)\n debug(rdCntReg)\n\n cntReg := Mux(cntReg === UInt(period - 1), UInt(0), cntReg + UInt(1))\n\n", "right_context": " cpuSlot(i) := slotTable(i)\n }\n\n // Initialize master data to zero when cpuSlot is not enabled \n io.slave.M.Addr := Bits(0)\n io.slave.M.Cmd := Bits(0)\n io.slave.M.DataByteEn := Bits(0)\n io.slave.M.DataValid := Bits(0)\n io.slave.M.Data := Bits(0)\n\n // Initialize slave data to zero\n io.master.S.Data := Bits(0)\n io.master.S.Resp := OcpResp.NULL\n io.master.S.CmdAccept := Bits(0)\n io.master.S.DataAccept := Bits(0)\n\n // FSM for TDM Arbiter \n when(stateReg === sIdle) {\n when(cpuSlot(io.node) === UInt(1)) {\n val master = io.master.M\n //io.slave.M := master\n\n when(master.Cmd =/= OcpCmd.IDLE) {\n when(master.Cmd === OcpCmd.RD) {\n io.slave.M := master\n stateReg := sRead\n io.master.S.CmdAccept := UInt(1)\n rdCntReg := UInt(0)\n }\n when(master.Cmd === OcpCmd.WR) {\n io.slave.M := master\n stateReg := sWrite\n io.master.S.CmdAccept := UInt(1)\n io.master.S.DataAccept := UInt(1)\n wrCntReg := UInt(0)\n }\n }\n }\n }\n\n when(stateReg === sWrite) {\n io.slave.M := io.master.M\n io.master.S.DataAccept := UInt(1)\n // MS: why not counting just up to the slot length\n // Then we can avoid >= and use =\n wrCntReg := Mux(wrCntReg === UInt(wrPipeDelay), UInt(0), wrCntReg + UInt(1))\n\n // Sends ZEROs after the burst is done \n when(wrCntReg >= UInt(burstLen - 1)) {\n io.slave.M.Cmd := Bits(0)\n io.slave.M.Addr := Bits(0)\n io.slave.M.Data := Bits(0)\n io.slave.M.DataValid := Bits(0)\n io.slave.M.DataByteEn := Bits(0)\n }\n\n // Turn off the DataValid after a burst of 4\n when(wrCntReg >= UInt(burstLen - 1)) {\n io.master.S.DataAccept := UInt(0)\n }\n\n // Forward Rsp/DVA back to node \n // Ms: not hard coded constants in the source\n when(wrCntReg === UInt(4)) {\n io.master.S.Resp := OcpResp.DVA\n }\n // Wait on DVA \n when(io.master.S.Resp === OcpResp.DVA) {\n stateReg := sIdle\n }\n }\n\n when(stateReg === sRead) {\n io.slave.M := io.master.M\n rdCntReg := Mux(rdCntReg === UInt(rdPipeDelay + burstLen), UInt(0), rdCntReg + UInt(1))\n\n // Sends ZEROs after the burst is done \n // MS: This should also (as in write) be just the slot length.\n when(rdCntReg >= UInt(burstLen - 1)) {\n io.slave.M.Cmd := Bits(0)\n io.slave.M.Addr := Bits(0)\n io.slave.M.Data := Bits(0)\n io.slave.M.DataValid := Bits(0)\n io.slave.M.DataByteEn := Bits(0)\n }\n\n // rdCntReg starts 1 clock cycle after the arrival of the 1st data\n // MS: rdCntReg is used for two different purposes -- fix it\n // The following shall also include number of pipeline stages on the return path\n when(rdCntReg >= UInt(ctrlDelay + numPipe)) {\n io.master.S.Data := io.slave.S.Data\n io.master.S.Resp := io.slave.S.Resp\n }\n\n when(io.master.S.Resp === OcpResp.DVA) {\n burstCntReg := burstCntReg + UInt(1)\n when(burstCntReg === UInt(burstLen) - UInt(1)) {\n stateReg := sIdle\n }\n }\n }\n\n debug(io.slave.M)\n\n //io.master.S := io.slave.S\n\n}\n\n/* Mux for all arbiters' outputs /\nclass MemMuxIntf(nr: Int, addrWidth: Int, dataWidth: Int, burstLen: Int) extends Module {\n val io = new Bundle {\n val master = Vec.fill(nr) {\n new OcpBurstSlavePort(addrWidth, dataWidth, burstLen)\n }\n val slave = new OcpBurstMasterPort(addrWidth, dataWidth, burstLen)\n }\n debug(io.master)\n debug(io.slave)\n\n // MS: would like pipeline number configurable\n\n // 1st stage pipeline registers for inputs\n val mCmd_p1_Reg = Vec.fill(nr) {\n Reg(init = UInt(0, width = 3))\n }\n val mAddr_p1_Reg = Vec.fill(nr) {\n Reg(UInt(width = addrWidth))\n }\n val mData_p1_Reg = Vec.fill(nr) {\n Reg(UInt(width = dataWidth))\n }\n val mDataByteEn_p1_Reg = Vec.fill(nr) {\n Reg(UInt(width = dataWidth / 8))\n }\n val mDataValid_p1_Reg = Vec.fill(nr) {\n Reg(UInt(width = 1))\n }\n\n // 2st stage pipeline registers for inputs\n // MS: what about using the whole bundle as a single signal?\n // val mMasterReg = Reg(init=OcpBurstMasterSignals(...))\n val mCmd_p2_Reg = Reg(init = UInt(0, width = 3))\n val mAddr_p2_Reg = Reg(UInt(width = addrWidth))\n val mData_p2_Reg = Reg(UInt(width = dataWidth))\n val mDataByteEn_p2_Reg = Reg(UInt(width = dataWidth / 8))\n val mDataValid_p2_Reg = Reg(UInt(width = 1))\n\n // Pipeline registers default to 0\n mCmd_p1_Reg := Bits(0)\n mAddr_p1_Reg := Bits(0)\n mData_p1_Reg := Bits(0)\n mDataByteEn_p1_Reg := Bits(0)\n mDataValid_p1_Reg := Bits(0)\n\n // 1st stage pipeline of the input\n for (i <- 0 until nr) {\n mCmd_p1_Reg(i) := io.master(i).M.Cmd\n }\n\n for (i <- 0 until nr) {\n mAddr_p1_Reg(i) := io.master(i).M.Addr\n }\n\n for (i <- 0 until nr) {\n mData_p1_Reg(i) := io.master(i).M.Data\n }\n\n for (i <- 0 until nr) {\n mDataByteEn_p1_Reg(i) := io.master(i).M.DataByteEn\n }\n\n for (i <- 0 until nr) {\n mDataValid_p1_Reg(i) := io.master(i).M.DataValid\n }\n\n // OR gate of all inputs (2nd stage pipeline)\n\n mCmd_p2_Reg := mCmd_p1_Reg.reduce(_ \| _)\n mAddr_p2_Reg := mAddr_p1_Reg.reduce(_ \| _)\n mData_p2_Reg := mData_p1_Reg.reduce(_ \| _)\n mDataByteEn_p2_Reg := mDataByteEn_p1_Reg.reduce(_ \| _)\n mDataValid_p2_Reg := mDataValid_p1_Reg.reduce(_ \| _)\n\n // Transfer data from input pipeline registers to output\n io.slave.M.Addr := mAddr_p2_Reg\n io.slave.M.Cmd := mCmd_p2_Reg\n io.slave.M.DataByteEn := mDataByteEn_p2_Reg\n io.slave.M.DataValid := mDataValid_p2_Reg\n io.slave.M.Data := mData_p2_Reg\n\n // 1st stage pipeline registers for output\n val sResp_p1_Reg = Reg(next = io.slave.S.Resp)\n val sData_p1_Reg = Reg(next = io.slave.S.Data)\n\n\n // Forward response to all arbiters\n for (i <- 0 until nr) {\n io.master(i).S.Data := sData_p1_Reg\n io.master(i).S.Resp := sResp_p1_Reg\n }\n\n}\n\nobject NodeTdmArbiterMain {\n def main(args: Array[String]): Unit = {\n\n val chiselArgs = args.slice(5, args.length)\n val cnt = args(0)\n val addrWidth = args(1)\n val dataWidth = args(2)\n val burstLen = args(3)\n val ctrlDelay = args(4)\n\n chiselMain(chiselArgs, () => Module(new NodeTdmArbiter(cnt.toInt, addrWidth.toInt, dataWidth.toInt, burstLen.toInt, ctrlDelay.toInt)))\n }\n}\n\n\n", "groundtruth": " def slotTable(i: Int): UInt = {\n (cntReg === UInt(i slotLen)).toUInt\n }\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ocp/Ocp.scala", "left_context": "\n/\n Generic definitions for OCP\n \n Authors: Wolfgang Puffitsch (wpuffitsch@gmail.com)\n \n /\n\npackage ocp\n\nimport Chisel._\n\n// Constants for MCmd\n", "right_context": " val IDLE = Bits(\"b000\")\n val WR = Bits(\"b001\")\n val RD = Bits(\"b010\")\n // val RDEX = Bits(\"b011\")\n // val RDL = Bits(\"b100\")\n // val WRNP = Bits(\"b101\")\n // val WRC = Bits(\"b110\")\n // val BCST = Bits(\"b111\")\n}\n\n// Constants for SResp\nobject OcpResp {\n val NULL = Bits(\"b00\")\n val DVA = Bits(\"b01\")\n val FAIL = Bits(\"b10\")\n val ERR = Bits(\"b11\")\n}\n\n// MS: would like fields (e.g. data) to start with lower case.\n// Just classes start with upper case.\n\n// Signals generated by master\nclass OcpMasterSignals(addrWidth: Int, dataWidth: Int) extends Bundle() {\n val Cmd = Bits(width = 3)\n val Addr = Bits(width = addrWidth)\n val Data = Bits(width = dataWidth)\n\n // This does not really clone, but Data.clone doesn't either\n override def clone() = {\n val res = new OcpMasterSignals(addrWidth, dataWidth)\n res.asInstanceOf[this.type]\n }\n}\n\n// Signals generated by slave\nclass OcpSlaveSignals(dataWidth: Int) extends Bundle() {\n val Resp = Bits(width = 2)\n val Data = Bits(width = dataWidth)\n\n // This does not really clone, but Data.clone doesn't either\n override def clone() = {\n val res = new OcpSlaveSignals(dataWidth)\n res.asInstanceOf[this.type]\n }\n}\n", "groundtruth": "object OcpCmd {\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ocp/OcpBurst.scala", "left_context": "\n/\n Definitions for OCP ports that support Bursts\n \n Authors: Wolfgang Puffitsch (wpuffitsch@gmail.com)\n \n /\n\npackage ocp\n\nimport Chisel._\n\n// Burst masters provide handshake signals\nclass OcpBurstMasterSignals(addrWidth: Int, dataWidth: Int)\n extends OcpMasterSignals(addrWidth, dataWidth) {\n val DataValid = Bits(width = 1)\n val DataByteEn = Bits(width = dataWidth / 8)\n\n // This does not really clone, but Data.clone doesn't either\n override def clone() = {\n val res = new OcpBurstMasterSignals(addrWidth, dataWidth)\n res.asInstanceOf[this.type]\n }\n}\n\n// Burst slaves provide handshake signal\nclass OcpBurstSlaveSignals(dataWidth: Int)\n extends OcpSlaveSignals(dataWidth) {\n val CmdAccept = Bits(width = 1)\n val DataAccept = Bits(width = 1)\n\n // This does not really clone, but Data.clone doesn't either\n override def clone() = {\n val res = new OcpBurstSlaveSignals(dataWidth)\n res.asInstanceOf[this.type]\n }\n}\n\n// Master port\nclass OcpBurstMasterPort(addrWidth: Int, dataWidth: Int, burstLen: Int) extends Bundle() {\n val burstLength = burstLen\n // Clk is implicit in Chisel\n val M = new OcpBurstMasterSignals(addrWidth, dataWidth).asOutput\n val S = new OcpBurstSlaveSignals(dataWidth).asInput\n}\n\n// Slave port is reverse of master port\nclass OcpBurstSlavePort(addrWidth: Int, dataWidth: Int, burstLen: Int) extends Bundle() {\n val burstLength = burstLen\n // Clk is implicit in Chisel\n val M = new OcpBurstMasterSignals(addrWidth, dataWidth).asInput\n val S = new OcpBurstSlaveSignals(dataWidth).asOutput\n\n // This does not really clone, but Data.clone doesn't either\n override def clone() = {\n val res = new OcpBurstSlavePort(addrWidth, dataWidth, burstLen)\n res.asInstanceOf[this.type]\n }\n\n}\n\n// Bridge between word-oriented port and burst port\nclass OcpBurstBridge(master: OcpCacheMasterPort, slave: OcpBurstSlavePort) {\n val addrWidth = master.M.Addr.getWidth\n val dataWidth = master.M.Data.getWidth\n val burstLength = slave.burstLength\n val burstAddrBits = log2Up(burstLength)\n\n // State of transmission\n val idle :: read :: readResp :: write :: Nil = Enum(Bits(), 4)\n val state = Reg(init = idle)\n val burstCnt = Reg(init = UInt(0, burstAddrBits))\n val cmdPos = Reg(Bits(width = burstAddrBits))\n\n // Register signals that come from master\n val masterReg = Reg(init = master.M)\n\n // Register to delay response\n val slaveReg = Reg(master.S)\n\n when(state =/= write && (masterReg.Cmd === OcpCmd.IDLE \|\| slave.S.CmdAccept === Bits(1))) {\n masterReg := master.M\n }\n\n // Default values\n slave.M.Cmd := masterReg.Cmd\n slave.M.Addr := Cat(masterReg.Addr(addrWidth - 1, burstAddrBits + log2Up(dataWidth / 8)),\n Fill(burstAddrBits + log2Up(dataWidth / 8), Bits(0)))\n slave.M.Data := Bits(0)\n slave.M.DataByteEn := Bits(0)\n slave.M.DataValid := Bits(0)\n master.S := slave.S\n\n // Read burst\n when(state === read) {\n when(slave.S.Resp =/= OcpResp.NULL) {\n when(burstCnt === cmdPos) {\n slaveReg := slave.S\n }\n when(burstCnt === UInt(burstLength - 1)) {\n state := readResp\n }\n burstCnt := burstCnt + UInt(1)\n }\n master.S.Resp := OcpResp.NULL\n master.S.Data := Bits(0)\n }\n when(state === readResp) {\n state := idle\n master.S := slaveReg\n }\n\n // Write burst\n when(state === write) {\n masterReg.Cmd := OcpCmd.IDLE\n slave.M.DataValid := Bits(1)\n when(burstCnt === cmdPos) {\n slave.M.Data := masterReg.Data\n slave.M.DataByteEn := masterReg.ByteEn\n }\n when(burstCnt === UInt(burstLength - 1)) {\n state := idle\n }\n when(slave.S.DataAccept === Bits(1)) {\n burstCnt := burstCnt + UInt(1)\n }\n }\n\n // Start new transaction\n when(master.M.Cmd === OcpCmd.RD) {\n state := read\n cmdPos := master.M.Addr(burstAddrBits + log2Up(dataWidth / 8) - 1, log2Up(dataWidth / 8))\n }\n when(master.M.Cmd === OcpCmd.WR) {\n state := write\n cmdPos := master.M.Addr(burstAddrBits + log2Up(dataWidth / 8) - 1, log2Up(dataWidth / 8))\n }\n}\n\n// Join two OcpBurst ports, assume no collisions between requests\nclass OcpBurstJoin(left: OcpBurstMasterPort, right: OcpBurstMasterPort,\n joined: OcpBurstSlavePort, selectLeft: Bool = Bool()) {\n\n val selRightReg = Reg(Bool())\n val selRight = Mux(left.M.Cmd =/= OcpCmd.IDLE, Bool(false),\n Mux(right.M.Cmd =/= OcpCmd.IDLE, Bool(true),\n selRightReg))\n\n joined.M := left.M\n when(selRight) {\n joined.M := right.M\n }\n joined.M.Cmd := right.M.Cmd \| left.M.Cmd\n\n right.S := joined.S\n left.S := joined.S\n\n when(selRightReg) {\n left.S.Resp := OcpResp.NULL\n }\n .otherwise {\n right.S.Resp := OcpResp.NULL\n }\n\n selRightReg := selRight\n\n selectLeft := !selRight\n}\n\n// Join two OcpBurst ports, left port has priority in case of colliding requests\nclass OcpBurstPriorityJoin(left: OcpBurstMasterPort, right: OcpBurstMasterPort,\n joined: OcpBurstSlavePort, selectLeft: Bool = Bool()) {\n\n val selLeft = left.M.Cmd =/= OcpCmd.IDLE\n val selRight = right.M.Cmd =/= OcpCmd.IDLE\n\n val leftPendingReg = Reg(init = Bool(false))\n val rightPendingReg = Reg(init = Bool(false))\n\n val pendingRespReg = Reg(init = UInt(0))\n\n // default port forwarding\n joined.M := Mux(rightPendingReg, right.M, left.M)\n\n // pass back data to masters\n right.S := joined.S\n left.S := joined.S\n // suppress responses when not serving a request\n when(!rightPendingReg) {\n right.S.Resp := OcpResp.NULL\n }\n when(!leftPendingReg) {\n left.S.Resp := OcpResp.NULL\n }\n\n // do not accept commands while another request is being served\n left.S.CmdAccept := Mux(rightPendingReg, Bits(0), joined.S.CmdAccept)\n left.S.DataAccept := Mux(rightPendingReg, Bits(0), joined.S.DataAccept)\n right.S.CmdAccept := Mux(leftPendingReg, Bits(0), joined.S.CmdAccept)\n right.S.DataAccept := Mux(leftPendingReg, Bits(0), joined.S.DataAccept)\n\n // forward requests from left port\n when(selLeft) {\n when(!rightPendingReg) {\n joined.M := left.M\n pendingRespReg := Mux(left.M.Cmd === OcpCmd.WR, UInt(1), UInt(left.burstLength))\n leftPendingReg := Bool(true)\n right.S.CmdAccept := Bits(0)\n right.S.DataAccept := Bits(0)\n }\n }\n // forward requests from right port\n when(selRight) {\n when(!selLeft && !leftPendingReg) {\n joined.M := right.M\n pendingRespReg := Mux(right.M.Cmd === OcpCmd.WR, UInt(1), UInt(right.burstLength))\n rightPendingReg := Bool(true)\n }\n }\n\n // count responses, clear pending flags at end of requests\n when(joined.S.Resp =/= OcpResp.NULL) {\n pendingRespReg := pendingRespReg - UInt(1)\n when(pendingRespReg === UInt(1)) {\n when(leftPendingReg) {\n leftPendingReg := Bool(false)\n }\n when(rightPendingReg) {\n rightPendingReg := Bool(false)\n }\n }\n }\n\n selectLeft := selLeft\n}\n\n// Provide a \"bus\" with a master port and a slave port to simplify plumbing\nclass OcpBurstBus(addrWidth: Int, dataWidth: Int, burstLen: Int) extends Module {\n val io = new Bundle {\n val master = new OcpBurstMasterPort(addrWidth, dataWidth, burstLen)\n val slave = new OcpBurstSlavePort(addrWidth, dataWidth, burstLen)\n }\n io.master <> io.slave\n}\n\n// Buffer a burst for pipelining\nclass OcpBurstBuffer(master: OcpBurstMasterPort, slave: OcpBurstSlavePort) {\n\n val MBuffer = Vec.fill(master.burstLength) {\n Reg(init = master.M)\n }\n\n val free = MBuffer(0).Cmd === OcpCmd.IDLE\n when(free \|\| slave.S.CmdAccept === Bits(1)) {\n", "right_context": "\n master.S.CmdAccept := free\n master.S.DataAccept := free\n}\n", "groundtruth": " for (i <- 0 until master.burstLength - 1) {\n MBuffer(i) := MBuffer(i + 1)\n }\n MBuffer(master.burstLength - 1) := master.M\n }\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ocp/OcpCache.scala", "left_context": "/\n Definitions for OCP ports for split cache\n \n Authors: Wolfgang Puffitsch (wpuffitsch@gmail.com)\n \n /\n\npackage ocp\n\nimport Chisel._\n\nobject OcpCache {\n val STACK_CACHE = Bits(\"b00\")\n val DATA_CACHE = Bits(\"b10\")\n val UNCACHED = Bits(\"b11\")\n}\n\n// Cache masters provide address space signal\nclass OcpCacheMasterSignals(addrWidth: Int, dataWidth: Int)\n extends OcpCoreMasterSignals(addrWidth, dataWidth) {\n val AddrSpace = Bits(width = 2)\n\n // This does not really clone, but Data.clone doesn't either\n override def clone() = {\n val res = new OcpCacheMasterSignals(addrWidth, dataWidth)\n res.asInstanceOf[this.type]\n }\n}\n\n// Master port\nclass OcpCacheMasterPort(addrWidth: Int, dataWidth: Int) extends Bundle() {\n // Clk is implicit in Chisel\n val M = new OcpCacheMasterSignals(addrWidth, dataWidth).asOutput\n val S = new OcpSlaveSignals(dataWidth).asInput\n}\n\n// Slave port is reverse of master port\n", "right_context": " val slave = new OcpCacheSlavePort(addrWidth, dataWidth)\n val master = new OcpCacheMasterPort(addrWidth, dataWidth)\n }\n io.master <> io.slave\n}\n", "groundtruth": "class OcpCacheSlavePort(addrWidth: Int, dataWidth: Int) extends Bundle() {\n // Clk is implicit in Chisel\n val M = new OcpCacheMasterSignals(addrWidth, dataWidth).asInput\n val S = new OcpSlaveSignals(dataWidth).asOutput\n}\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ocp/OcpCore.scala", "left_context": "/\n Definitions for OCP as generated by the Patmos pipeline\n \n Authors: Wolfgang Puffitsch (wpuffitsch@gmail.com)\n \n /\n\npackage ocp\n\nimport Chisel._\n\n// Masters include a byte-enable signal\nclass OcpCoreMasterSignals(addrWidth: Int, dataWidth: Int)\n extends OcpMasterSignals(addrWidth, dataWidth) {\n val ByteEn = Bits(width = dataWidth / 8)\n\n // This does not really clone, but Data.clone doesn't either\n override def clone() = {\n val res = new OcpCoreMasterSignals(addrWidth, dataWidth)\n res.asInstanceOf[this.type]\n }\n}\n\n// Master port\nclass OcpCoreMasterPort(addrWidth: Int, dataWidth: Int) extends Bundle() {\n val M = new OcpCoreMasterSignals(addrWidth, dataWidth).asOutput\n val S = new OcpSlaveSignals(dataWidth).asInput\n", "right_context": "class OcpCoreSlavePort(addrWidth: Int, dataWidth: Int) extends Bundle() {\n val M = new OcpCoreMasterSignals(addrWidth, dataWidth).asInput\n val S = new OcpSlaveSignals(dataWidth).asOutput\n\n // This does not really clone, but Data.clone doesn't either\n override def clone() = {\n val res = new OcpCoreSlavePort(addrWidth, dataWidth)\n res.asInstanceOf[this.type]\n }\n\n}\n\n// Provide a \"bus\" with a master port and a slave port to simplify plumbing\nclass OcpCoreBus(addrWidth: Int, dataWidth: Int) extends Module {\n val io = new Bundle {\n val slave = new OcpCoreSlavePort(addrWidth, dataWidth)\n val master = new OcpCoreMasterPort(addrWidth, dataWidth)\n }\n io.master <> io.slave\n}\n", "groundtruth": "\n // This does not really clone, but Data.clone doesn't either\n override def clone() = {\n val res = new OcpCoreMasterPort(addrWidth, dataWidth)\n res.asInstanceOf[this.type]\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ocp/OcpIO.scala", "left_context": "/\n Definitions for Patmos' OCP ports for general I/O\n \n Authors: Wolfgang Puffitsch (wpuffitsch@gmail.com)\n \n /\n\npackage ocp\n\nimport Chisel._\n\n// Masters include a RespAccept signal\nclass OcpIOMasterSignals(addrWidth: Int, dataWidth: Int)\n extends OcpCoreMasterSignals(addrWidth, dataWidth) {\n val RespAccept = Bits(width = 1)\n\n // This does not really clone, but Data.clone doesn't either\n override def clone() = {\n val res = new OcpIOMasterSignals(addrWidth, dataWidth)\n res.asInstanceOf[this.type]\n }\n}\n\n// Slaves include a CmdAccept signal\nclass OcpIOSlaveSignals(dataWidth: Int)\n extends OcpSlaveSignals(dataWidth) {\n val CmdAccept = Bits(width = 1)\n\n // This does not really clone, but Data.clone doesn't either\n override def clone() = {\n val res = new OcpIOSlaveSignals(dataWidth)\n res.asInstanceOf[this.type]\n }\n}\n\n// Master port\nclass OcpIOMasterPort(addrWidth: Int, dataWidth: Int) extends Bundle() {\n // Clk is implicit in Chisel\n val M = new OcpIOMasterSignals(addrWidth, dataWidth).asOutput\n val S = new OcpIOSlaveSignals(dataWidth).asInput\n}\n\n// Slave port is reverse of master port\nclass OcpIOSlavePort(addrWidth: Int, dataWidth: Int) extends Bundle() {\n // Clk is implicit in Chisel\n val M = new OcpIOMasterSignals(addrWidth, dataWidth).asInput\n val S = new OcpIOSlaveSignals(dataWidth).asOutput\n}\n\n// Bridge between ports that do/do not support CmdAccept\nclass OcpIOBridge(master: OcpCoreMasterPort, slave: OcpIOSlavePort) {\n // Register signals that come from master\n val masterReg = Reg(init = master.M)\n", "right_context": " slave.M.RespAccept := Bits(\"b1\")\n\n // Forward slave signals to master\n master.S <> slave.S\n}\n\n// Bridge between ports that do/do not support CmdAccept\n// An alternative version, being on the safer side for reset.\n// Inserts one cycle delay for the command register (could be improved)\n// including the earlier reaction on CmdAccep\n// adds than combinational paths\nclass OcpIOBridgeAlt(master: OcpCoreMasterPort, slave: OcpIOSlavePort) {\n\n val masterReg = Reg(init = master.M) // What is the reset value of this bundle?\n val busyReg = Reg(init = Bool(false))\n\n when(!busyReg) {\n masterReg := master.M\n }\n when(master.M.Cmd === OcpCmd.RD \|\| master.M.Cmd === OcpCmd.WR) {\n busyReg := Bool(true)\n }\n when(busyReg && slave.S.CmdAccept === Bits(1)) {\n busyReg := Bool(false)\n masterReg.Cmd := OcpCmd.IDLE\n }\n\n // Forward master signals to slave, always accept responses\n slave.M := masterReg\n slave.M.RespAccept := Bits(\"b1\")\n\n // Forward slave signals to master\n master.S <> slave.S\n}\n\n// Provide a \"bus\" with a master port and a slave port to simplify plumbing\nclass OcpIOBus(addrWidth: Int, dataWidth: Int) extends Module {\n val io = new Bundle {\n val slave = new OcpIOSlavePort(addrWidth, dataWidth)\n val master = new OcpIOMasterPort(addrWidth, dataWidth)\n }\n io.master <> io.slave\n}\n", "groundtruth": " when(masterReg.Cmd === OcpCmd.IDLE \|\| slave.S.CmdAccept === Bits(1)) {\n masterReg := master.M\n }\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ocp/OcpNI.scala", "left_context": "/\n Definitions for OCP port for the network interface\n \n Authors: Wolfgang Puffitsch (wpuffitsch@gmail.com)\n \n /\n\npackage ocp\n\nimport Chisel._\n\n// Cache masters provide address space signal\nclass OcpNISlaveSignals(dataWidth: Int)\n extends OcpIOSlaveSignals(dataWidth) {\n val Reset_n = Bits(width = 1)\n val Flag = Bits(width = 2)\n", "right_context": "\n// Master port\nclass OcpNIMasterPort(addrWidth: Int, dataWidth: Int) extends Bundle() {\n // Clk is implicit in Chisel\n val M = new OcpIOMasterSignals(addrWidth, dataWidth).asOutput\n val S = new OcpNISlaveSignals(dataWidth).asInput\n}\n\n// Slave port is reverse of master port\nclass OcpNISlavePort(addrWidth: Int, dataWidth: Int) extends Bundle() {\n // Clk is implicit in Chisel\n val M = new OcpIOMasterSignals(addrWidth, dataWidth).asInput\n val S = new OcpNISlaveSignals(dataWidth).asOutput\n}\n", "groundtruth": "\n // This does not really clone, but Data.clone doesn't either\n override def clone() = {\n val res = new OcpNISlaveSignals(dataWidth)\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ocp/OcpTest.scala", "left_context": "/\n Test for usability of OCP definitions\n \n Authors: Wolfgang Puffitsch (wpuffitsch@gmail.com)\n \n /\n\npackage ocp\n\nimport Chisel._\n\nclass OcpMaster() extends Module {\n val io = IO(new OcpCacheMasterPort(8, 32))\n\n val cnt = Reg(UInt(), init = UInt(0))\n cnt := cnt + UInt(1, 32)\n\n io.M.Cmd := OcpCmd.IDLE\n io.M.Addr := cnt(15, 8)\n io.M.Data := cnt\n io.M.ByteEn := cnt(7, 4)\n\n when(cnt(3, 0) === Bits(\"b1111\")) {\n io.M.Cmd := OcpCmd.WR\n }\n}\n\nclass OcpSlave() extends Module {\n val io = IO(new OcpBurstSlavePort(8, 32, 4))\n\n val M = Reg(next = io.M)\n\n val data = Reg(UInt(), init = UInt(0))\n data := data + UInt(1, 32)\n\n val cnt = Reg(UInt(), init = UInt(0))\n\n io.S.Resp := OcpResp.NULL\n io.S.Data := data\n when(M.Cmd =/= OcpCmd.IDLE) {\n cnt := UInt(4)\n }\n\n", "right_context": " val io = IO(new OcpBurstSlavePort(8, 32, 4))\n\n val master = Module(new OcpMaster())\n val slave = Module(new OcpSlave())\n val bridge = new OcpBurstBridge(master.io, slave.io)\n\n io <> slave.io\n}\n\nobject OcpTestMain {\n def main(args: Array[String]): Unit = {\n chiselMain(args, () => Module(new Ocp()))\n }\n}\n", "groundtruth": " when(cnt =/= UInt(0)) {\n cnt := cnt - UInt(1)\n io.S.Resp := OcpResp.DVA\n }\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ocp/TdmArbiter.scala", "left_context": "/\n Arbiter for OCP burst slaves.\n * Pseudo round robin arbitration. Each turn for a non-requesting master costs 1 clock cycle.\n \n Author: Martin Schoeberl (martin@jopdesign.com) David Chong (davidchong99@gmail.com)\n \n /\n\npackage ocp\n\nimport Chisel._\n\nclass TdmArbiter(cnt: Int, addrWidth: Int, dataWidth: Int, burstLen: Int) extends Module {\n // MS: I'm always confused from which direction the name shall be\n // probably the other way round...\n val io = IO(new Bundle {\n val master = Vec.fill(cnt) {\n new OcpBurstSlavePort(addrWidth, dataWidth, burstLen)\n }\n val slave = new OcpBurstMasterPort(addrWidth, dataWidth, burstLen)\n })\n debug(io.master)\n debug(io.slave)\n\n val cntReg = Reg(init = UInt(0, log2Up(cnt * (burstLen + 2))))\n // slot length = burst size + 2 \n val burstCntReg = Reg(init = UInt(0, log2Up(burstLen)))\n val period = cnt * (burstLen + 2)\n val slotLen = burstLen + 2\n val cpuSlot = Vec.fill(cnt) {\n Reg(init = UInt(0, width = 1))\n }\n\n val sIdle :: sRead :: sWrite :: Nil = Enum(UInt(), 3)\n val stateReg = Vec.fill(cnt) {\n Reg(init = sIdle)\n }\n\n debug(cntReg)\n debug(cpuSlot(0))\n debug(cpuSlot(1))\n debug(cpuSlot(2))\n debug(stateReg(0))\n debug(stateReg(1))\n debug(stateReg(2))\n\n cntReg := Mux(cntReg === UInt(period - 1), UInt(0), cntReg + UInt(1))\n\n // Generater the slot Table for the whole period\n def slotTable(i: Int): UInt = {\n (cntReg === UInt(i * slotLen)).toUInt\n }\n\n for (i <- 0 until cnt) {\n cpuSlot(i) := slotTable(i)\n }\n\n // Initialize data to zero when cpuSlot is not enabled\n io.slave.M.Addr := Bits(0)\n io.slave.M.Cmd := Bits(0)\n io.slave.M.DataByteEn := Bits(0)\n io.slave.M.DataValid := Bits(0)\n io.slave.M.Data := Bits(0)\n\n // Initialize slave data to zero\n for (i <- 0 to cnt - 1) {\n io.master(i).S.CmdAccept := Bits(0)\n io.master(i).S.DataAccept := Bits(0)\n io.master(i).S.Resp := OcpResp.NULL\n io.master(i).S.Data := Bits(0)\n }\n\n // Temporarily assigned to master 0\n //val masterIdReg = Reg(init = UInt(0, log2Up(cnt)))\n\n for (i <- 0 to cnt - 1) {\n\n when(stateReg(i) === sIdle) {\n when(cpuSlot(i) === UInt(1)) {\n\n when(io.master(i).M.Cmd =/= OcpCmd.IDLE) {\n when(io.master(i).M.Cmd === OcpCmd.RD) {\n io.slave.M := io.master(i).M\n io.master(i).S := io.slave.S\n stateReg(i) := sRead\n }\n when(io.master(i).M.Cmd === OcpCmd.WR) {\n io.slave.M := io.master(i).M\n io.master(i).S := io.slave.S\n stateReg(i) := sWrite\n burstCntReg := UInt(0)\n }\n }\n }\n }\n\n when(stateReg(i) === sWrite) {\n io.slave.M := io.master(i).M\n io.master(i).S := io.slave.S\n // Wait on DVA\n", "right_context": " when(stateReg(i) === sRead) {\n io.slave.M := io.master(i).M\n io.master(i).S := io.slave.S\n when(io.slave.S.Resp === OcpResp.DVA) {\n burstCntReg := burstCntReg + UInt(1)\n when(burstCntReg === UInt(burstLen) - UInt(1)) {\n stateReg := sIdle\n }\n }\n }\n }\n\n //io.slave.M := io.master(masterIdReg).M\n debug(io.slave.M)\n\n}\n\nobject TdmArbiterMain {\n def main(args: Array[String]): Unit = {\n\n val chiselArgs = args.slice(4, args.length)\n val cnt = args(0)\n val addrWidth = args(1)\n val dataWidth = args(2)\n val burstLen = args(3)\n\n chiselMain(chiselArgs, () => Module(new TdmArbiter(cnt.toInt, addrWidth.toInt, dataWidth.toInt, burstLen.toInt)))\n }\n}\n\n\n", "groundtruth": " when(io.slave.S.Resp === OcpResp.DVA) {\n stateReg(i) := sIdle\n }\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/main/scala/ocp/TdmArbiterWrapper.scala", "left_context": "/\n Wrapper for NodeTdmArbiter \n \n Author: Martin Schoeberl (martin@jopdesign.com) David Chong (davidchong99@gmail.com)\n \n /\n\n/\n Switching between different arbiters in Aegean:\n * Change 'Arbiter' in aegeanGen.py and in aegeanCode.py to 'TdmArbiterWrapper'.\n * Three places all together.\n */\n\npackage ocp\n\nimport Chisel._\n\nclass TdmArbiterWrapper(cnt: Int, addrWidth: Int, dataWidth: Int, burstLen: Int) extends Module {\n // MS: I'm always confused from which direction the name shall be\n // probably the other way round...\n val io = IO(new Bundle {\n", "right_context": "\n val memMux = Module(new MemMuxIntf(cnt, addrWidth, dataWidth, burstLen))\n\n for (i <- 0 until cnt) {\n val nodeID = UInt(i, width = 6)\n val arb = Module(new ocp.NodeTdmArbiter(cnt, addrWidth, dataWidth, burstLen, 16))\n arb.io.master <> io.master(i)\n arb.io.node := nodeID\n\n memMux.io.master(i) <> arb.io.slave\n }\n\n io.slave <> memMux.io.slave\n}\n\nobject TdmArbiterWrapperMain {\n def main(args: Array[String]): Unit = {\n\n val chiselArgs = args.slice(4, args.length)\n val cnt = args(0)\n val addrWidth = args(1)\n val dataWidth = args(2)\n val burstLen = args(3)\n\n chiselMain(chiselArgs, () => Module(new TdmArbiterWrapper(cnt.toInt, addrWidth.toInt, dataWidth.toInt, burstLen.toInt)))\n }\n}\n\n", "groundtruth": " val master = Vec.fill(cnt) {\n new OcpBurstSlavePort(addrWidth, dataWidth, burstLen)\n }\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/test/scala/ethcontroller/design/EthRxControllerTester.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.design\n\nimport Chisel._\nimport ethcontroller.protocols.{EthernetFrame, EthernetTesting, EthernetUtils}\n\nimport scala.language.postfixOps\nimport scala.sys.process._\n\nclass EthRxControllerTester(dut: EthRxController, frame: EthernetFrame, injectNoFrames: Int) extends Tester(dut) {\n\n def initPHY2MII(clockDiv: Int): Unit = {\n poke(dut.io.miiChannel.col, 0)\n poke(dut.io.miiChannel.crs, 0)\n poke(dut.io.miiChannel.clk, 0)\n step(clockDiv)\n }\n\n def txPHY2MIIData(nibble: Int, clockDiv: Int): Unit = {\n poke(dut.io.miiChannel.dv, 1)\n poke(dut.io.miiChannel.data, nibble)\n poke(dut.io.miiChannel.clk, 0)\n step(clockDiv)\n poke(dut.io.miiChannel.clk, 1)\n step(clockDiv)\n }\n\n def stopTxPHY2MII(clockDiv: Int): Unit = {\n poke(dut.io.miiChannel.dv, 0)\n poke(dut.io.miiChannel.clk, 0)\n step(clockDiv)\n poke(dut.io.miiChannel.clk, 1)\n step(clockDiv)\n }\n\n def peekEthRxStatus(): Unit = {\n peek(dut.stateReg)\n peek(dut.ethByteReg)\n peek(dut.ethByteDvReg)\n peek(dut.rdRamIdReg)\n peek(dut.wrRamIdReg)\n peek(dut.fifoCountReg)\n peek(dut.fifoEmptyReg)\n peek(dut.fifoFullReg)\n peek(dut.rxFrameSizeReg)\n }\n\n def testSingleFrameReception(frame: EthernetFrame, initTime: Long): Unit = {\n initPHY2MII(4)\n println(\"Testing preamble\")\n for (nibble <- frame.preambleNibbles) {\n txPHY2MIIData(nibble, 6)\n peek(dut.miiRx.deserializePHYByte.doneReg)\n peek(dut.miiRx.deserializePHYByte.shiftReg)\n peek(dut.miiRx.regBuffer)\n }\n println(\"Testing MAC\")\n", "right_context": " txPHY2MIIData(nibble, 6)\n peekEthRxStatus()\n }\n }\n println(\"Testing EoF\")\n stopTxPHY2MII(6)\n peekEthRxStatus()\n }\n\n /*\n Testing EthernetRxController\n */\n println(\"Test Starting...\")\n var time: Long = 0x53C38A1000000000L\n for (i <- 0 until injectNoFrames) {\n println(\"...\")\n println(\"TEST FRAME ITERATION #\" + i + \" at t = \" + time.toHexString)\n testSingleFrameReception(frame, time)\n println(\"END TEST FRAME ITERATION #\" + i + \" at t = \" + time.toHexString)\n step(1)\n step(1)\n println(\"...\")\n println(\"...\")\n }\n}\n\nobject EthRxControllerTester extends App {\n private val pathToVCD = \"generated/\" + this.getClass.getSimpleName.dropRight(1)\n private val nameOfVCD = this.getClass.getSimpleName.dropRight(7) + \".vcd\"\n\n //Chisel3\n // iotesters.Driver.execute(Array(\"--target-dir\", \"generated\", \"--fint-write-vcd\"), () => new EthRxController(4, 64)) {\n // // iotesters.Driver.execute(Array(\"--target-dir\", \"generated\", \"--fint-write-vcd\", \"--wave-form-file-name\", \"generated/BubbleFifo.vcd\"), () => new BubbleFifo(8, 4)) {\n // c => new EthRxControllerTester(c, EthernetTesting.mockupPTPEthFrameOverIpUDP, 3)\n // }\n\n //Chisel 2\n chiselMainTest(Array(\"--genHarness\", \"--test\", \"--backend\", \"c\",\n \"--compile\", \"--vcd\", \"--targetDir\", pathToVCD),\n () => Module(new EthRxController(4, 64))) {\n dut => new EthRxControllerTester(dut, EthernetTesting.mockupPTPEthFrameOverIpUDP, 5)\n }\n\n \"gtkwave \" + pathToVCD + \"/\" + nameOfVCD + \" \" + pathToVCD + \"/\" + \"view.sav\" !\n}\n\n", "groundtruth": " for (nibble <- frame.dstMacNibbles ++ frame.srcMacNibbles ++ frame.ethTypeNibbles) {\n txPHY2MIIData(nibble, 6)\n peekEthRxStatus()\n }\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/test/scala/ethcontroller/design/EthTxControllerTester.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.design\n\nimport Chisel.{Module, Tester, chiselMainTest}\nimport ethcontroller.protocols.{EthernetFrame, EthernetTesting}\nimport ocp.OcpCmd\n\nimport scala.language.postfixOps\nimport scala.sys.process._\n\n\nclass EthTxControllerTester(dut: EthTxController, frame: EthernetFrame, injectNoFrames: Int) extends Tester(dut) {\n\n val MII_TICKS_TO_CLKS: Int = 2\n\n var miiClkValue: Int = 0\n var numberOfSysSteps: Int = 0\n\n def testSingleFrameTransmission(frame: EthernetFrame, initTime: Long): Unit = {\n initPHY2MII(4)\n println(\"Testing OCP write to buffer\")\n ocpLoadFrameToBuffer()\n println(\"Testing EthTx transmission\")\n println(\"Testing preamble\")\n // for (nibble <- frame.preambleNibbles) {\n // stepWithMIIClock(6)\n // peek(dut.miiTx.serializeByteToNibble.doneReg)\n // peek(dut.miiTx.serializeByteToNibble.shiftReg)\n // peekEthTxStatus()\n // }\n // println(\"Testing MAC\")\n // for (nibble <- frame.dstMacNibbles ++ frame.srcMacNibbles ++ frame.ethTypeNibbles) {\n // stepWithMIIClock(6)\n // peekEthTxStatus()\n // }\n // println(\"Testing Raw Ethernet frame II payload\")\n // for (payloadData <- 0 until 45) {\n // for (nibble <- frame.dataNibbles) {\n // stepWithMIIClock(6)\n // peekEthTxStatus()\n // }\n // }\n println(\"Testing EoF\")\n stepWithMIIClock()\n }\n\n def initPHY2MII(steps: Int): Unit = {\n poke(dut.io.miiChannel.col, 0)\n poke(dut.io.miiChannel.crs, 0)\n poke(dut.io.miiChannel.clk, 0)\n step(steps)\n }\n\n def ocpLoadFrameToBuffer(): Unit = {\n val totalFrame = frame.dstMac ++ frame.srcMac ++ frame.ethType ++ frame.data\n var ocpAddr = 0x0\n var byteCnt = 0x1\n for (byte <- totalFrame) {\n poke(dut.io.ocp.M.Addr, ocpAddr)\n poke(dut.io.ocp.M.ByteEn, byteCnt)\n poke(dut.io.ocp.M.Data, byte)\n poke(dut.io.ocp.M.Cmd, OcpCmd.WR.litValue())\n stepWithMIIClock()\n", "right_context": "\n poke(dut.io.ocp.M.Cmd, OcpCmd.IDLE.litValue())\n stepWithMIIClock()\n poke(dut.io.ocp.M.Addr, 1 << dut.constRamAddrWidth \| 0x18)\n poke(dut.io.ocp.M.ByteEn, 0xF)\n poke(dut.io.ocp.M.Data, 0x1)\n poke(dut.io.ocp.M.Cmd, OcpCmd.WR.litValue())\n stepWithMIIClock()\n poke(dut.io.ocp.M.Cmd, OcpCmd.IDLE.litValue())\n stepWithMIIClock()\n expect(dut.fifoPushReg, true)\n }\n\n def peekEthTxStatus(): Unit = {\n peek(dut.stateReg)\n peek(dut.byteCntReg)\n peek(dut.rdRamIdReg)\n peek(dut.wrRamIdReg)\n peek(dut.fifoCountReg)\n peek(dut.fifoEmptyReg)\n peek(dut.fifoFullReg)\n peek(dut.txFrameSizeReg)\n peek(dut.miiTx.transmittingReg)\n }\n\n def stepWithMIIClock(): Unit = {\n poke(dut.io.miiChannel.clk, miiClkValue)\n step(1)\n if (numberOfSysSteps > MII_TICKS_TO_CLKS) {\n miiClkValue = 1 - miiClkValue\n numberOfSysSteps = 0\n } else {\n numberOfSysSteps += 1\n }\n }\n\n /*\n Testing EthernetRxController\n */\n println(\"Test Starting...\")\n var time: Long = 0x53C38A1000000000L\n for (i <- 0 until injectNoFrames) {\n println(\"...\")\n println(\"TEST FRAME ITERATION #\" + i + \" at t = \" + time.toHexString)\n testSingleFrameTransmission(frame, time)\n println(\"END TEST FRAME ITERATION #\" + i + \" at t = \" + time.toHexString)\n stepWithMIIClock()\n stepWithMIIClock()\n println(\"...\")\n println(\"...\")\n }\n\n}\n\nobject EthTxControllerTester extends App {\n private val pathToVCD = \"generated/\" + this.getClass.getSimpleName.dropRight(1)\n private val nameOfVCD = this.getClass.getSimpleName.dropRight(7) + \".vcd\"\n\n chiselMainTest(Array(\"--genHarness\", \"--test\", \"--backend\", \"c\",\n \"--compile\", \"--vcd\", \"--targetDir\", pathToVCD),\n () => Module(new EthTxController(4, 64))) {\n dut => new EthTxControllerTester(dut, EthernetTesting.mockupTTEPCFFrame, 5)\n }\n\n var waveHandle = \"gtkwave \" + pathToVCD + \"/\" + nameOfVCD + \" \" + pathToVCD + \"/\" + \"view.sav\" !\n\n println(\"gtkwave running as PID:\" + waveHandle)\n}\n\n\n\n", "groundtruth": " if (byteCnt == 8) {\n byteCnt = 1\n ocpAddr += 0x1\n } else {\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/test/scala/ethcontroller/design/MIIRxTester.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.design\n\nimport Chisel.{Module, Tester, chiselMainTest}\nimport ethcontroller.protocols.{EthernetFrame, EthernetTesting}\n\nimport scala.language.postfixOps\nimport scala.sys.process._\n\nclass MIIRxTester(dut: MIIRx, frame: EthernetFrame) extends Tester(dut) {\n // Shifting of discrete numbers for clarity\n poke(dut.io.miiChannel.col, 0)\n poke(dut.io.miiChannel.crs, 0)\n poke(dut.io.rxEn, true)\n poke(dut.io.miiChannel.dv, 1)\n poke(dut.io.miiChannel.clk, 0)\n step(1)\n println(\"(Testing preamble)\")\n for (nibble <- frame.preambleNibbles) {\n poke(dut.io.miiChannel.data, nibble)\n poke(dut.io.miiChannel.clk, 0)\n step(3)\n peek(dut.deserializePHYByte.countReg)\n peek(dut.deserializePHYByte.doneReg)\n peek(dut.deserializePHYByte.shiftReg)\n peek(dut.regBuffer)\n poke(dut.io.miiChannel.clk, 1)\n step(3)\n }\n poke(dut.io.miiChannel.clk, 0)\n step(3)\n poke(dut.io.miiChannel.clk, 1)\n expect(dut.io.ethSof, true, \"--checking for start-of-frame detected\")\n expect(dut.regBuffer, BigInt(frame.preamble), \"--checking for preamble registered\")\n step(3)\n println(\"Testing EoF\")\n poke(dut.io.miiChannel.clk, 0)\n", "right_context": " poke(dut.io.miiChannel.clk, 1)\n step(3)\n poke(dut.io.miiChannel.clk, 0)\n step(3)\n}\n\nobject MIIRxTester extends App {\n private val pathToVCD = \"generated/\" + this.getClass.getSimpleName.dropRight(1)\n private val nameOfVCD = this.getClass.getSimpleName.dropRight(7) + \".vcd\"\n\n try {\n chiselMainTest(Array(\"--genHarness\", \"--test\", \"--backend\", \"c\",\n \"--compile\", \"--vcd\", \"--targetDir\", \"generated/\" + this.getClass.getSimpleName.dropRight(1)),\n () => Module(new MIIRx())) {\n dut => new MIIRxTester(dut, EthernetTesting.mockupPTPEthFrameOverIpUDP)\n }\n } finally {\n \"gtkwave \" + pathToVCD + \"/\" + nameOfVCD + \" \" + pathToVCD + \"/\" + \"view.sav &\" !\n }\n}\n", "groundtruth": " poke(dut.io.miiChannel.dv, 0)\n step(3)\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/test/scala/ethcontroller/design/MIITxTester.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.design\n\nimport Chisel.{Module, Tester, chiselMainTest}\nimport ethcontroller.protocols.{EthernetFrame, EthernetTesting}\n\nimport scala.language.postfixOps\nimport scala.sys.process._\n\nclass MIITxTester(dut: MIITx, frame: EthernetFrame) extends Tester(dut) {\n // Shifting of discrete numbers for clarity\n var byteAddr = 0\n // poke(dut.io.startTx, true)\n poke(dut.io.miiChannel.clk, 0)\n step(3)\n // poke(dut.io.startTx, false)\n println(\"-- Testing the preamble\")\n while(byteAddr < frame.preamble.length){\n if(peek(dut.io.ready) == 1){\n poke(dut.io.macDataDv, true)\n poke(dut.io.macData, BigInt(frame.preamble(byteAddr)))\n byteAddr+=1\n }\n peek(dut.serializeByteToNibble.selHi)\n peek(dut.serializeByteToNibble.selLo)\n poke(dut.io.miiChannel.clk, 0)\n step(1)\n poke(dut.io.macDataDv, false)\n step(2)\n poke(dut.io.miiChannel.clk, 1)\n step(3)\n }\n while(peek(dut.io.ready) == 0){\n poke(dut.io.miiChannel.clk, 0)\n step(3)\n poke(dut.io.miiChannel.clk, 1)\n step(3)\n }\n // poke(dut.io.endTx, true)\n poke(dut.io.miiChannel.clk, 0)\n step(1)\n // poke(dut.io.endTx, true)\n step(2)\n poke(dut.io.miiChannel.clk, 1)\n step(3)\n poke(dut.io.miiChannel.clk, 0)\n step(3)\n poke(dut.io.miiChannel.clk, 1)\n step(3)\n expect(dut.io.miiChannel.dv, false, \"Expecting an idle bus\")\n expect(dut.serializeByteToNibble.io.done, true, \"Expecting the serializer to have finished\")\n}\n\nobject MIITxTester extends App {\n private val pathToVCD = \"generated/\" + this.getClass.getSimpleName.dropRight(1)\n private val nameOfVCD = this.getClass.getSimpleName.dropRight(7) + \".vcd\"\n\n try {\n chiselMainTest(Array(\"--genHarness\", \"--test\", \"--backend\", \"c\",\n \"--compile\", \"--vcd\", \"--targetDir\", \"generated/\" + this.getClass.getSimpleName.dropRight(1)),\n", "right_context": "", "groundtruth": " () => Module(new MIITx())) {\n dut => new MIITxTester(dut, EthernetTesting.mockupPTPEthFrameOverIpUDP)\n }\n } finally {\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/test/scala/ethcontroller/protocols/EthernetTesting.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.protocols\n\nobject EthernetTesting {\n\n val mockupPTPEthFrameDHCP = new DefaultEthFrame {\n override val dstMac: Array[Byte] = EthernetUtils.toBytes(0xff, 0xff, 0xff, 0xff, 0xff, 0xff)\n override val srcMac: Array[Byte] = EthernetUtils.toBytes(0x80, 0xce, 0x62, 0xd8, 0xc7, 0x39)\n override val ethType: Array[Byte] = EthernetUtils.toBytes(0x08, 0x00)\n override val ipHeader: Array[Byte] = EthernetUtils.toBytes(0x45, 0x10, 0x01, 0x48, 0x00, 0x00, 0x00, 0x00,\n 0x80, 0x11, 0x39, 0x96, 0x00, 0x00, 0x00, 0x00,\n 0xff, 0xff, 0xff, 0xff)\n override val udpHeader: Array[Byte] = EthernetUtils.toBytes(0x00, 0x44, 0x00, 0x43, 0x01, 0x34, 0x5c, 0xec)\n //Should be ignored\n override val ptpHeader: Array[Byte] = EthernetUtils.toBytes(PTP_FOLLOW_UP_TYPE, 0x02, 0x00, 0x2C, 0x00, 0x00, 0x00, 0x00,\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n 0x00, 0x00, 0x00, 0x00, 0xE4, 0xAF, 0xA1, 0x30,\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x55, 0x55,\n 0x00, 0x00)\n override val ptpBody: Array[Byte] = EthernetUtils.toBytes(0x54, 0x32, 0x11, 0x11, 0x55, 0x55, 0xAA, 0xAA)\n override val ptpSuffix: Array[Byte] = EthernetUtils.toBytes(0x00)\n override val fcs: Array[Byte] = EthernetUtils.toBytes(0x00)\n override val igp: Array[Byte] = EthernetUtils.toBytes(0x00)\n override val data: Array[Byte] = ipHeader ++ udpHeader ++ ptpHeader ++ ptpBody ++ ptpSuffix ++ fcs ++ igp\n }\n val mockupPTPVLANFrameOverIpUDP = new DefaultEthFrame {\n override val dstMac: Array[Byte] = EthernetUtils.toBytes(0x01, 0x00, 0x5E, 0x00, 0x01, 0x81)\n override val srcMac: Array[Byte] = EthernetUtils.toBytes(0x01, 0x00, 0x5E, 0x00, 0x01, 0x81)\n override val ethType: Array[Byte] = EthernetUtils.toBytes(0x81, 0x00, 0x01, 0x11, 0x08, 0x00)\n override val ipHeader: Array[Byte] = EthernetUtils.toBytes(0x45, 0x00, 0x00, 0x48, 0x00, 0x5D, 0x40, 0x00,\n 0x01, 0x11, 0x29, 0x68, 0xC0, 0xA8, 0x01, 0x01,\n 0xE0, 0x00, 0x01, 0x81)\n override val udpHeader: Array[Byte] = EthernetUtils.toBytes(0x01, 0x3F, 0x01, 0x3F, 0x00, 0x34, 0x00, 0x00)\n override val ptpHeader: Array[Byte] = EthernetUtils.toBytes(PTP_FOLLOW_UP_TYPE, 0x02, 0x00, 0x2C, 0x00, 0x00, 0x00, 0x00,\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n 0x00, 0x00, 0x00, 0x00, 0xE4, 0xAF, 0xA1, 0x30,\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x55, 0x55,\n 0x00, 0x00)\n override val ptpBody: Array[Byte] = EthernetUtils.toBytes(0x54, 0x32, 0x11, 0x11, 0x55, 0x55, 0xAA, 0xAA)\n override val ptpSuffix: Array[Byte] = EthernetUtils.toBytes(0x00)\n override val fcs: Array[Byte] = EthernetUtils.toBytes(0x00)\n override val igp: Array[Byte] = EthernetUtils.toBytes(0x00)\n override val data: Array[Byte] = ipHeader ++ udpHeader ++ ptpHeader ++ ptpBody ++ ptpSuffix ++ fcs ++ igp\n }\n val mockupPTPEthFrameOverIpUDP = new DefaultEthFrame {\n override val dstMac: Array[Byte] = EthernetUtils.toBytes(0x01, 0x00, 0x5E, 0x00, 0x01, 0x81)\n override val srcMac: Array[Byte] = EthernetUtils.toBytes(0x01, 0x00, 0x5E, 0x00, 0x01, 0x81)\n override val ethType: Array[Byte] = EthernetUtils.toBytes(0x08, 0x00)\n override val ipHeader: Array[Byte] = EthernetUtils.toBytes(0x45, 0x00, 0x00, 0x48, 0x00, 0x5D, 0x40, 0x00,\n 0x01, 0x11, 0x29, 0x68, 0xC0, 0xA8, 0x01, 0x01,\n 0xE0, 0x00, 0x01, 0x81)\n override val udpHeader: Array[Byte] = EthernetUtils.toBytes(0x01, 0x3F, 0x01, 0x3F, 0x00, 0x34, 0x00, 0x00)\n override val ptpHeader: Array[Byte] = EthernetUtils.toBytes(PTP_FOLLOW_UP_TYPE, 0x02, 0x00, 0x2C, 0x00, 0x00, 0x00, 0x00,\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n 0x00, 0x00, 0x00, 0x00, 0xE4, 0xAF, 0xA1, 0x30,\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x55, 0x55,\n 0x00, 0x00)\n override val ptpBody: Array[Byte] = EthernetUtils.toBytes(0x54, 0x32, 0x11, 0x11, 0x55, 0x55, 0xAA, 0xAA)\n override val ptpSuffix: Array[Byte] = EthernetUtils.toBytes(0x00)\n override val fcs: Array[Byte] = EthernetUtils.toBytes(0x00)\n override val igp: Array[Byte] = EthernetUtils.toBytes(0x00)\n override val data: Array[Byte] = ipHeader ++ udpHeader ++ ptpHeader ++ ptpBody ++ ptpSuffix ++ fcs ++ igp\n }\n val mockupTTEPCFFrame = new DefaultEthFrame {\n override val dstMac: Array[Byte] = EthernetUtils.toBytes(0xAB, 0xAD, 0xBA, 0xBE, 0x0F, 0xCE)\n override val srcMac: Array[Byte] = EthernetUtils.toBytes(0x00, 0x11, 0x22, 0x33, 0x44, 0x55)\n override val ethType: Array[Byte] = EthernetUtils.toBytes(0x89, 0x1D)\n override val data: Array[Byte] = EthernetUtils.toBytes(0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x02, 0x00,\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1b, 0xc0, 0x00, 0x00)\n }\n\n class DefaultEthFrame extends EthernetFrame {\n override val preamble: Array[Byte] = EthernetUtils.toBytes(0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xD5)\n override val dstMac: Array[Byte] = Array.emptyByteArray\n override val srcMac: Array[Byte] = Array.emptyByteArray\n override val ethType: Array[Byte] = Array.emptyByteArray\n override val ipHeader: Array[Byte] = Array.emptyByteArray\n override val udpHeader: Array[Byte] = Array.emptyByteArray\n override val ptpHeader: Array[Byte] = Array.emptyByteArray\n override val ptpBody: Array[Byte] = Array.emptyByteArray\n", "right_context": "\n}", "groundtruth": " override val ptpSuffix: Array[Byte] = Array.emptyByteArray\n override val fcs: Array[Byte] = Array.emptyByteArray\n override val igp: Array[Byte] = Array.emptyByteArray\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/test/scala/ethcontroller/utils/DeserializerTester.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.utils\n\nimport Chisel._\nimport ethcontroller.protocols.{EthernetFrame, EthernetTesting}\n\nimport scala.language.postfixOps\nimport scala.sys.process._\n\nclass DeserializerTester(dut: Deserializer, frame: EthernetFrame) extends Tester(dut) {\n // Shifting of discrete numbers for clarity\n poke(dut.io.en, true)\n for (i <- frame.preambleNibbles) {\n poke(dut.io.shiftIn, i)\n", "right_context": " expect(dut.io.shiftOut, frame.PREAMBLE_END)\n poke(dut.io.en, false)\n step(1)\n poke(dut.io.clr, true)\n step(1)\n expect(dut.countReg, 8 / 4 - 1)\n expect(dut.shiftReg, 0)\n expect(dut.doneReg, false)\n}\n\nobject DeserializerTester extends App {\n private val pathToVCD = \"generated/\" + this.getClass.getSimpleName.dropRight(1)\n private val nameOfVCD = this.getClass.getSimpleName.dropRight(7) + \".vcd\"\n\n try {\n chiselMainTest(Array(\"--genHarness\", \"--test\", \"--backend\", \"c\",\n \"--compile\", \"--vcd\", \"--targetDir\", \"generated/\" + this.getClass.getSimpleName.dropRight(1)),\n () => Module(new Deserializer(false, 4, 8))) {\n dut => new DeserializerTester(dut, EthernetTesting.mockupPTPEthFrameOverIpUDP)\n }\n } finally {\n \"gtkwave \" + pathToVCD + \"/\" + nameOfVCD + \" \" + pathToVCD + \"/\" + \"view.sav\" !\n }\n}\n", "groundtruth": " peek(dut.io.shiftOut)\n peek(dut.io.done)\n step(1)\n", "crossfile_context": ""}
	{"task_id": "an-ethernet-controller", "path": "an-ethernet-controller/src/test/scala/ethcontroller/utils/SerializerTester.scala", "left_context": "// See README.md for license details.\n\npackage ethcontroller.utils\n\nimport Chisel._\nimport ethcontroller.protocols.{EthernetFrame, EthernetTesting}\n\nimport scala.language.postfixOps\nimport scala.sys.process._\n\nclass SerializerTester(dut: Serializer, frame: EthernetFrame) extends Tester(dut) {\n // Shifting of discrete numbers for clarity\n poke(dut.io.en, true)\n for (i <- frame.preamble) {\n step(1)\n poke(dut.io.load, true)\n poke(dut.io.shiftIn, i.toInt)\n step(1)\n poke(dut.io.load, false)\n do {\n step(1)\n } while (peek(dut.io.done) == 0)\n peek(dut.io.shiftOut)\n }\n expect(dut.io.done, true)\n expect(dut.io.shiftOut, frame.PREAMBLE_END)\n step(1)\n poke(dut.io.en, false)\n expect(dut.countReg, 8 / 4 - 1)\n expect(dut.shiftReg, 0)\n expect(dut.doneReg, false)\n}\n\nobject SerializerTester extends App {\n private val pathToVCD = \"generated/\" + this.getClass.getSimpleName.dropRight(1)\n private val nameOfVCD = this.getClass.getSimpleName.dropRight(7) + \".vcd\"\n\n try {\n chiselMainTest(Array(\"--genHarness\", \"--test\", \"--backend\", \"c\",\n \"--compile\", \"--vcd\", \"--targetDir\", \"generated/\" + this.getClass.getSimpleName.dropRight(1)),\n", "right_context": " }\n}", "groundtruth": " () => Module(new Serializer(false, 8, 4))) {\n dut => new SerializerTester(dut, EthernetTesting.mockupPTPEthFrameOverIpUDP)\n }\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/ALU.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chisel3.util.{is, switch}\nimport chiselv.Instruction._\n\nclass ALUPort(bitWidth: Int = 32) extends Bundle {\n val inst = Input(Instruction())\n val a = Input(UInt(bitWidth.W))\n val b = Input(UInt(bitWidth.W))\n val x = Output(UInt(bitWidth.W))\n}\nclass ALU(bitWidth: Int = 32) extends Module {\n val io = IO(new ALUPort(bitWidth))\n val out = WireDefault(0.U(bitWidth.W))\n\n // For RV32I the shift amount is 5 bits, for RV64I is 6 bits\n", "right_context": "\n switch(io.inst) {\n // Arithmetic\n is(ADD, ADDI)(out := io.a + io.b)\n is(SUB)(out := io.a - io.b)\n // Shifts\n is(SRA, SRAI)(out := (io.a.asSInt >> io.b(shamt, 0)).asUInt) // Signed\n is(SRL, SRLI)(out := io.a >> io.b(shamt, 0))\n is(SLL, SLLI)(out := io.a << io.b(shamt, 0))\n // Logical\n is(AND, ANDI)(out := io.a & io.b)\n is(OR, ORI)(out := io.a \| io.b)\n is(XOR, XORI)(out := io.a ^ io.b)\n // Compare\n is(SLT, SLTI)(out := Mux(io.a.asSInt < io.b.asSInt, 1.U, 0.U)) // Signed\n is(SLTU, SLTIU)(out := Mux(io.a < io.b, 1.U, 0.U))\n // Auxiliary\n is(EQ)(out := Mux(io.a === io.b, 1.U, 0.U))\n is(NEQ)(out := Mux(io.a =/= io.b, 1.U, 0.U))\n is(GTE)(out := Mux(io.a.asSInt >= io.b.asSInt, 1.U, 0.U))\n is(GTEU)(out := Mux(io.a >= io.b, 1.U, 0.U))\n }\n\n io.x := out\n}\n", "groundtruth": " val shamt = (if (bitWidth == 32) 5 else if (bitWidth == 64) 6 else 0) - 1\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/Blink.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chisel3.util.Counter\n\n/*\n The blinking LED module.\n \n @constructor\n * creates a new blinking LED module that flashes every second.\n * @param freq\n * the frequency of the core in Hertz.\n * @param startOn\n * if true, the LED is initially on.\n * @param io_led0\n * (Output) is the led output\n */\nclass Blinky(freq: Int, startOn: Boolean = false) extends Module {\n val io = IO(new Bundle {\n val led0 = Output(Bool())\n })\n\n // Blink leds every second (start on)\n val led = RegInit(startOn.B)\n val (_, counterWrap) = Counter(true.B, freq / 2)\n", "right_context": "}\n", "groundtruth": " when(counterWrap) {\n led := ~led\n }\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/CPUSingleCycle.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chisel3.experimental.Analog\nimport chisel3.util.{Cat, Fill, is, switch}\nimport chiselv.Instruction._\n\nclass CPUSingleCycle(\n cpuFrequency: Int,\n entryPoint: Long,\n bitWidth: Int = 32,\n instructionMemorySize: Int = 1 * 1024,\n dataMemorySize: Int = 1 * 1024,\n numGPIO: Int = 8,\n ) extends Module {\n val io = IO(new Bundle {\n val GPIO0External = Analog(numGPIO.W) // GPIO external port\n\n val UART0Port = Flipped(new UARTPort) // UART0 data port\n val SysconPort = Flipped(new SysconPort(bitWidth))\n val instructionMemPort = Flipped(new InstructionMemPort(bitWidth, instructionMemorySize))\n val dataMemPort = Flipped(new MemoryPortDual(bitWidth, dataMemorySize))\n })\n\n val stall = WireDefault(false.B)\n\n // Instantiate and initialize the Register Bank\n val registerBank = Module(new RegisterBank(bitWidth))\n registerBank.io.writeEnable := false.B\n registerBank.io.regwr_data := 0.U\n registerBank.io.stall := stall\n\n // Instantiate and initialize the Program Counter\n val PC = Module(new ProgramCounter(bitWidth, entryPoint))\n PC.io.writeEnable := false.B\n PC.io.dataIn := 0.U\n PC.io.writeAdd := false.B\n\n // Instantiate and initialize the ALU\n val ALU = Module(new ALU(bitWidth))\n ALU.io.inst := ERR_INST\n ALU.io.a := 0.U\n ALU.io.b := 0.U\n\n // Instantiate and initialize the Instruction Decoder\n val decoder = Module(new Decoder(bitWidth))\n decoder.io.op := 0.U\n\n // Instantiate and initialize the Memory IO Manager\n val memoryIOManager = Module(new MemoryIOManager(bitWidth, dataMemorySize))\n memoryIOManager.io.MemoryIOPort.readRequest := false.B\n memoryIOManager.io.MemoryIOPort.writeRequest := false.B\n memoryIOManager.io.MemoryIOPort.readAddr := 0.U\n memoryIOManager.io.MemoryIOPort.writeAddr := 0.U\n memoryIOManager.io.MemoryIOPort.writeData := 0.U\n memoryIOManager.io.MemoryIOPort.dataSize := 0.U\n memoryIOManager.io.MemoryIOPort.writeMask := 0.U\n // Connect MMIO to the devices\n memoryIOManager.io.DataMemPort <> io.dataMemPort\n memoryIOManager.io.UART0Port <> io.UART0Port\n memoryIOManager.io.SysconPort <> io.SysconPort\n\n // Instantiate and connect GPIO\n val GPIO0 = Module(new GPIO(bitWidth, numGPIO))\n memoryIOManager.io.GPIO0Port <> GPIO0.io.GPIOPort\n if (numGPIO > 0) {\n GPIO0.io.externalPort <> io.GPIO0External\n }\n\n // Instantiate and connect the Timer\n val timer0 = Module(new Timer(bitWidth, cpuFrequency))\n memoryIOManager.io.Timer0Port <> timer0.io\n\n // --------------- CPU Control --------------- //\n // State of the CPU Stall\n stall := memoryIOManager.io.stall\n when(!stall) {\n // If CPU is stalled, do not advance PC\n PC.io.writeEnable := true.B\n PC.io.dataIn := PC.io.PC4\n }\n\n // Connect PC output to instruction memory\n when(io.instructionMemPort.ready) {\n io.instructionMemPort.readAddr := PC.io.PC\n }.otherwise(\n io.instructionMemPort.readAddr := DontCare\n )\n\n // Connect the instruction memory to the decoder\n decoder.io.op := io.instructionMemPort.readData\n\n // Connect the decoder output to register bank inputs\n registerBank.io.regwr_addr := decoder.io.rd\n registerBank.io.rs1_addr := decoder.io.rs1\n registerBank.io.rs2_addr := decoder.io.rs2\n\n // ----- CPU Operations ----- //\n\n // ALU Operations\n when(decoder.io.toALU) {\n ALU.io.inst := decoder.io.inst\n ALU.io.a := registerBank.io.rs1\n ALU.io.b := Mux(\n decoder.io.use_imm,\n decoder.io.imm.asUInt,\n registerBank.io.rs2,\n )\n\n registerBank.io.writeEnable := true.B\n registerBank.io.regwr_data := ALU.io.x\n }\n\n // Branch Operations\n when(decoder.io.branch) {\n ALU.io.a := registerBank.io.rs1\n ALU.io.b := registerBank.io.rs2\n switch(decoder.io.inst) {\n is(BEQ)(ALU.io.inst := EQ)\n is(BNE)(ALU.io.inst := NEQ)\n is(BLT)(ALU.io.inst := SLT)\n is(BGE)(ALU.io.inst := GTE)\n is(BLTU)(ALU.io.inst := SLTU)\n is(BGEU)(ALU.io.inst := GTEU)\n }\n when(ALU.io.x === 1.U) {\n PC.io.writeEnable := true.B\n PC.io.writeAdd := true.B\n PC.io.dataIn := decoder.io.imm.asUInt\n }\n }\n\n // Jump Operations\n when(decoder.io.jump) {\n // Write next instruction address to rd\n registerBank.io.writeEnable := true.B\n // Use the ALU to get the result\n ALU.io.inst := ADD\n ALU.io.a := PC.io.PC\n ALU.io.b := 4.U\n registerBank.io.regwr_data := ALU.io.x\n\n PC.io.writeEnable := true.B\n when(decoder.io.inst === JAL) {\n // Set PC to jump address\n PC.io.writeAdd := true.B\n PC.io.dataIn := decoder.io.imm.asUInt\n }\n when(decoder.io.inst === JALR) {\n // Set PC to jump address\n PC.io.dataIn := Cat(\n (registerBank.io.rs1 + decoder.io.imm.asUInt)(31, 1),\n 0.U,\n )\n }\n }\n\n // LUI\n when(decoder.io.inst === LUI) {\n registerBank.io.writeEnable := true.B\n registerBank.io.regwr_data := decoder.io.imm.asUInt\n }\n\n // AUIPC\n when(decoder.io.inst === AUIPC) {\n registerBank.io.writeEnable := true.B\n ALU.io.inst := ADD\n ALU.io.a := PC.io.PC\n ALU.io.b :=\n decoder.io.imm.asUInt\n registerBank.io.regwr_data := ALU.io.x\n }\n\n // Loads & Stores\n when(decoder.io.is_load \|\| decoder.io.is_store) {\n // Use the ALU to get the resulting address\n ALU.io.inst := ADD\n ALU.io.a := registerBank.io.rs1\n ALU.io.b := decoder.io.imm.asUInt\n\n memoryIOManager.io.MemoryIOPort.writeAddr := ALU.io.x\n memoryIOManager.io.MemoryIOPort.readAddr := ALU.io.x\n }\n\n when(decoder.io.is_load) {\n val dataSize = WireDefault(0.U(2.W)) // Data size, 1 = byte, 2 = halfword, 3 = word\n val dataOut = WireDefault(0.U(32.W))\n\n // Load Word\n", "right_context": " dataOut := Cat(\n Fill(16, memoryIOManager.io.MemoryIOPort.readData(15)),\n memoryIOManager.io.MemoryIOPort.readData(15, 0),\n )\n }\n // Load Halfword Unsigned\n when(decoder.io.inst === LHU) {\n dataSize := 2.U\n dataOut := Cat(Fill(16, 0.U), memoryIOManager.io.MemoryIOPort.readData(15, 0))\n }\n // Load Byte\n when(decoder.io.inst === LB) {\n dataSize := 1.U\n dataOut := Cat(\n Fill(24, memoryIOManager.io.MemoryIOPort.readData(7)),\n memoryIOManager.io.MemoryIOPort.readData(7, 0),\n )\n }\n // Load Byte Unsigned\n when(decoder.io.inst === LBU) {\n dataSize := 1.U\n dataOut := Cat(Fill(24, 0.U), memoryIOManager.io.MemoryIOPort.readData(7, 0))\n }\n memoryIOManager.io.MemoryIOPort.readRequest := decoder.io.is_load\n memoryIOManager.io.MemoryIOPort.dataSize := dataSize\n registerBank.io.writeEnable := true.B\n registerBank.io.regwr_data := dataOut\n }\n\n when(decoder.io.is_store) {\n // Define if operation is a load or store\n memoryIOManager.io.MemoryIOPort.writeRequest := decoder.io.is_store\n\n // Stores\n val dataOut = WireDefault(0.U(32.W))\n val dataSize = WireDefault(0.U(2.W)) // Data size, 1 = byte, 2 = halfword, 3 = word\n\n // Store Word\n when(decoder.io.inst === SW) {\n dataOut := registerBank.io.rs2\n dataSize := 3.U\n }\n // Store Halfword\n when(decoder.io.inst === SH) {\n dataOut := Cat(Fill(16, 0.U), registerBank.io.rs2(15, 0))\n dataSize := 2.U\n }\n // Store Byte\n when(decoder.io.inst === SB) {\n dataOut := Cat(Fill(24, 0.U), registerBank.io.rs2(7, 0))\n dataSize := 1.U\n }\n memoryIOManager.io.MemoryIOPort.dataSize := dataSize\n memoryIOManager.io.MemoryIOPort.writeData := dataOut\n }\n}\n", "groundtruth": " when(decoder.io.inst === LW) {\n dataSize := 3.U\n dataOut := memoryIOManager.io.MemoryIOPort.readData\n }\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/Constants.scala", "left_context": "package chiselv\n\nimport chisel3.ChiselEnum\n\nobject Instruction extends ChiselEnum {\n val ERR_INST,\n // RV32I\n ADD, ADDI, SUB, LUI, AUIPC, // Arithmetic\n SLL, SLLI, SRL, SRLI, SRA, SRAI, // Shifts\n AND, ANDI, OR, ORI, XOR, XORI, // Logical\n SLT, SLTI, SLTU, SLTIU, // Compare\n BEQ, BNE, BLT, BGE, BLTU, BGEU, // Branches\n JAL, JALR, // Jump & Link\n FENCE, FENCEI, // Sync\n ECALL, EBREAK, // Environment\n CSRRW, CSRRS, CSRRC, CSRRWI, CSRRSI, CSRRCI, // CSR\n LB, LH, LBU, LHU, LW, // Loads\n SB, SH, SW, // Stores\n EQ, NEQ, GTE, GTEU // Not instructions but auxiliaries\n = Value\n}\n\n", "right_context": "", "groundtruth": "object InstructionType extends ChiselEnum {\n val IN_ERR, INST_R, INST_I, INST_S, INST_B, INST_U, INST_J, INST_Z = Value\n}\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/DataMemory.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chisel3.util.experimental.loadMemoryFromFileInline\nimport chisel3.util.log2Ceil\n\nclass MemoryPortDual(val bitWidth: Int, val addressSize: Long) extends Bundle {\n val readAddress = Input(UInt(log2Ceil(addressSize).W))\n val readData = Output(UInt(bitWidth.W))\n val writeAddress = Input(UInt(log2Ceil(addressSize).W))\n val writeData = Input(UInt(bitWidth.W))\n val writeMask = Input(UInt((bitWidth / 8).W))\n val dataSize = Input(UInt(2.W))\n val writeEnable = Input(Bool())\n}\nclass DualPortRAM(\n bitWidth: Int = 32,\n sizeBytes: Long = 1,\n memoryFile: String = \"\",\n debugMsg: Boolean = false,\n ) extends Module {\n val words = sizeBytes / bitWidth\n val io = IO(new MemoryPortDual(bitWidth, sizeBytes))\n\n if (debugMsg) {\n println(s\"Dual-port Memory Parameters:\")\n println(s\" Words: $words\")\n println(s\" Size: \" + words * bitWidth + \" bytes\")\n println(s\" Bit width: $bitWidth bit\")\n println(s\" Addr Width: \" + io.readAddress.getWidth + \" bit\")\n }\n\n val mem = SyncReadMem(words, UInt(bitWidth.W))\n\n // Divide memory address by 4 to get the word due to pc+4 addressing\n val readAddress = io.readAddress >> 2\n val writeAddress = io.writeAddress >> 2\n\n if (memoryFile.trim().nonEmpty) {\n", "right_context": " loadMemoryFromFileInline(mem, memoryFile)\n }\n\n io.readData := mem.read(readAddress)\n\n when(io.writeEnable === true.B) {\n mem.write(writeAddress, io.writeData)\n }\n}\n", "groundtruth": " if (debugMsg) println(s\" Load memory file: \" + memoryFile)\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/Decoder.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chisel3.util._\nimport chiselv.Instruction._\nimport chiselv.InstructionType._\n\nclass DecoderPort(bitWidth: Int = 32) extends Bundle {\n val op = Input(UInt(bitWidth.W)) // Op is the 32 bit instruction read received for decoding\n val inst = Output(Instruction()) // Instruction is the decoded instruction\n val rd = Output(UInt(5.W)) // Rd is the 5 bit destiny register\n val rs1 = Output(UInt(5.W)) // Rs1 is the 5 bit source register 1\n val rs2 = Output(UInt(5.W)) // Rs2 is the 5 bit source register 2\n val imm = Output(SInt(bitWidth.W)) // Imm is the 32 bit immediate\n val toALU = Output(Bool()) // ToALU is a flag to indicate if the instruction is to be executed in the ALU\n val branch = Output(Bool()) // Branch is a flag to indicate if the instruction should jump and link. Update PC\n val use_imm = Output(Bool()) // Use_imm is a flag to indicate if the instruction has an immediate\n val jump = Output(Bool()) // jump is a flag to indicate if the instruction has is a jump\n val is_load = Output(Bool()) // is_load is a flag to indicate if the instruction has a load from memory\n val is_store = Output(Bool()) // is_store is a flag to indicate if the instruction has a store to memory\n}\n\nclass Decoder(bitWidth: Int = 32) extends Module {\n val io = IO(new DecoderPort(bitWidth))\n\n val signals =\n ListLookup(\n io.op,\n // format: off\n List( IN_ERR, ERR_INST, false.B, false.B, false.B, false.B, false.B, false.B), // Default values\n Array(\n /* inst_type, inst to_alu branch use_imm jump is_load is_store /\n // Arithmetic\n BitPat(\"b0000000??????????000?????0110011\") -> List(INST_R, ADD, true.B, false.B, false.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????000?????0010011\") -> List(INST_I, ADDI, true.B, false.B, true.B, false.B, false.B, false.B),\n BitPat(\"b0100000??????????000?????0110011\") -> List(INST_R, SUB, true.B, false.B, false.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????????????0110111\") -> List(INST_U, LUI, false.B, false.B, true.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????????????0010111\") -> List(INST_U, AUIPC, false.B, false.B, true.B, false.B, false.B, false.B),\n // Shifts\n BitPat(\"b0000000??????????001?????0110011\") -> List(INST_R, SLL, true.B, false.B, false.B, false.B, false.B, false.B),\n BitPat(\"b0000000??????????001?????0010011\") -> List(INST_I, SLLI, true.B, false.B, true.B, false.B, false.B, false.B),\n BitPat(\"b0000000??????????101?????0110011\") -> List(INST_R, SRL, true.B, false.B, false.B, false.B, false.B, false.B),\n BitPat(\"b0000000??????????101?????0010011\") -> List(INST_I, SRLI, true.B, false.B, true.B, false.B, false.B, false.B),\n BitPat(\"b0100000??????????101?????0110011\") -> List(INST_R, SRA, true.B, false.B, false.B, false.B, false.B, false.B),\n BitPat(\"b0100000??????????101?????0010011\") -> List(INST_I, SRAI, true.B, false.B, true.B, false.B, false.B, false.B),\n // Logical\n BitPat(\"b0000000??????????100?????0110011\") -> List(INST_R, XOR, true.B, false.B, false.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????100?????0010011\") -> List(INST_I, XORI, true.B, false.B, true.B, false.B, false.B, false.B),\n BitPat(\"b0000000??????????110?????0110011\") -> List(INST_R, OR, true.B, false.B, false.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????110?????0010011\") -> List(INST_I, ORI, true.B, false.B, true.B, false.B, false.B, false.B),\n BitPat(\"b0000000??????????111?????0110011\") -> List(INST_R, AND, true.B, false.B, false.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????111?????0010011\") -> List(INST_I, ANDI, true.B, false.B, true.B, false.B, false.B, false.B),\n // Compare\n BitPat(\"b0000000??????????010?????0110011\") -> List(INST_R, SLT, true.B, false.B, false.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????010?????0010011\") -> List(INST_I, SLTI, true.B, false.B, true.B, false.B, false.B, false.B),\n BitPat(\"b0000000??????????011?????0110011\") -> List(INST_R, SLTU, true.B, false.B, false.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????011?????0010011\") -> List(INST_I, SLTIU, true.B, false.B, true.B, false.B, false.B, false.B),\n // Branches\n BitPat(\"b?????????????????000?????1100011\") -> List(INST_B, BEQ, false.B, true.B, true.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????001?????1100011\") -> List(INST_B, BNE, false.B, true.B, true.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????100?????1100011\") -> List(INST_B, BLT, false.B, true.B, true.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????101?????1100011\") -> List(INST_B, BGE, false.B, true.B, true.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????110?????1100011\") -> List(INST_B, BLTU, false.B, true.B, true.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????111?????1100011\") -> List(INST_B, BGEU, false.B, true.B, true.B, false.B, false.B, false.B),\n // Jump & link\n BitPat(\"b?????????????????????????1101111\") -> List(INST_J, JAL, false.B, false.B, true.B, true.B, false.B, false.B),\n BitPat(\"b?????????????????000?????1100111\") -> List(INST_I, JALR, false.B, false.B, true.B, true.B, false.B, false.B),\n // Sync\n BitPat(\"b0000????????00000000000000001111\") -> List(INST_I, FENCE, false.B, false.B, false.B, false.B, false.B, false.B),\n BitPat(\"b00000000000000000000001000001111\") -> List(INST_I, FENCEI, false.B, false.B, true.B, false.B, false.B, false.B),\n // Environment\n BitPat(\"b00000000000000000000000001110011\") -> List(INST_I, ECALL, false.B, false.B, false.B, false.B, false.B, false.B),\n BitPat(\"b00000000000100000000000001110011\") -> List(INST_I, EBREAK, false.B, false.B, false.B, false.B, false.B, false.B),\n // CSR\n BitPat(\"b?????????????????001?????1110011\") -> List(INST_I, CSRRW, false.B, false.B, false.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????010?????1110011\") -> List(INST_I, CSRRS, false.B, false.B, false.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????011?????1110011\") -> List(INST_I, CSRRC, false.B, false.B, false.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????101?????1110011\") -> List(INST_I, CSRRWI, false.B, false.B, true.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????110?????1110011\") -> List(INST_I, CSRRSI, false.B, false.B, true.B, false.B, false.B, false.B),\n BitPat(\"b?????????????????111?????1110011\") -> List(INST_I, CSRRCI, false.B, false.B, true.B, false.B, false.B, false.B),\n // Loads\n BitPat(\"b?????????????????000?????0000011\") -> List(INST_I, LB, false.B, false.B, true.B, false.B, true.B, false.B),\n BitPat(\"b?????????????????001?????0000011\") -> List(INST_I, LH, false.B, false.B, true.B, false.B, true.B, false.B),\n BitPat(\"b?????????????????100?????0000011\") -> List(INST_I, LBU, false.B, false.B, true.B, false.B, true.B, false.B),\n BitPat(\"b?????????????????101?????0000011\") -> List(INST_I, LHU, false.B, false.B, true.B, false.B, true.B, false.B),\n BitPat(\"b?????????????????010?????0000011\") -> List(INST_I, LW, false.B, false.B, true.B, false.B, true.B, false.B),\n // Stores\n BitPat(\"b?????????????????000?????0100011\") -> List(INST_S, SB, false.B, false.B, true.B, false.B, false.B, true.B),\n BitPat(\"b?????????????????001?????0100011\") -> List(INST_S, SH, false.B, false.B, true.B, false.B, false.B, true.B),\n BitPat(\"b?????????????????010?????0100011\") -> List(INST_S, SW, false.B, false.B, true.B, false.B, false.B, true.B),\n )\n ) // format: on\n\n io.rd := 0.U\n io.rs1 := 0.U\n io.rs2 := 0.U\n io.imm := 0.S\n io.inst := signals(1)\n io.toALU := signals(2)\n io.branch := signals(3)\n io.use_imm := signals(4)\n io.jump := signals(5)\n io.is_load := signals(6)\n io.is_store := signals(7)\n\n switch(signals(0)) {\n is(INST_R) {\n io.rd := io.op(11, 7)\n io.rs1 := io.op(19, 15)\n io.rs2 := io.op(24, 20)\n }\n is(INST_I) {\n io.rd := io.op(11, 7)\n io.rs1 := io.op(19, 15)\n io.imm := ImmGenerator(INST_I, io.op)\n }\n is(INST_S) {\n io.rs1 := io.op(19, 15)\n io.rs2 := io.op(24, 20)\n io.imm := ImmGenerator(INST_S, io.op)\n }\n is(INST_B) {\n io.rs1 := io.op(19, 15)\n io.rs2 := io.op(24, 20)\n io.imm := ImmGenerator(INST_B, io.op)\n }\n is(INST_U) {\n io.rd := io.op(11, 7)\n io.imm := ImmGenerator(INST_U, io.op)\n }\n is(INST_J) {\n io.rd := io.op(11, 7)\n io.imm := ImmGenerator(INST_J, io.op)\n }\n }\n\n /\n ImmGenerator generates the immadiate value depending on the instruction\n * type\n \n @param regType\n * is the instruction type from `Constants.scala`\n * @return\n * the imm value\n */\n def ImmGenerator(regType: InstructionType.Type, inst: UInt): SInt = regType match {\n", "right_context": " case INST_Z => Cat(Fill(27, 0.U), inst(19, 15)).asSInt // for csri\n case _ => 0.S\n }\n}\n", "groundtruth": " case INST_R => 0.S\n case INST_I => Cat(Fill(20, inst(31)), inst(31, 20)).asSInt\n case INST_S => Cat(Fill(20, inst(31)), inst(31, 25), inst(11, 7)).asSInt\n case INST_B => Cat(Fill(19, inst(31)), inst(31), inst(7), inst(30, 25), inst(11, 8), 0.U(1.W)).asSInt\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/GPIO.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chisel3.experimental.Analog\nimport chisel3.util.HasBlackBoxInline // For Analog type\n\nclass GPIOPort(bitWidth: Int = 32) extends Bundle {\n val dataIn = Input(UInt(bitWidth.W))\n val valueOut = Output(UInt(bitWidth.W))\n val directionOut = Output(UInt(bitWidth.W))\n val writeValue = Input(Bool())\n val writeDirection = Input(Bool())\n val stall = Output(Bool()) // >1 => Stall, 0 => Run\n}\n\nclass GPIO(bitWidth: Int = 32, numGPIO: Int = 8) extends Module {\n require(\n numGPIO <= bitWidth,\n \"Number of GPIOs must be less than or equal to the bitwidth, if needed, create another GPIO bank.\",\n )\n val io = IO(new Bundle {\n val GPIOPort = new GPIOPort(bitWidth)\n val externalPort = Analog(numGPIO.W)\n })\n\n val GPIO = RegInit(0.U(bitWidth.W))\n val direction = RegInit(0.U(bitWidth.W)) // 0 = input, 1 = output\n\n io.GPIOPort.stall := false.B\n io.GPIOPort.directionOut := direction\n\n // Only instantiate GPIO external interface if needed\n // this avoids using Verilator backend on tests that don't need it\n if (numGPIO > 0) {\n val InOut = Module(new GPIOInOut(numGPIO))\n io.GPIOPort.valueOut := InOut.io.dataOut\n InOut.io.dataIn := GPIO\n InOut.io.dir := direction\n io.externalPort <> InOut.io.dataIO\n } else {\n io.GPIOPort.valueOut := 0.U\n io.externalPort := DontCare\n }\n\n when(io.GPIOPort.writeValue) {\n GPIO := io.GPIOPort.dataIn\n }\n when(io.GPIOPort.writeDirection) {\n direction := io.GPIOPort.dataIn\n }\n}\n\nclass GPIOInOut(numGPIO: Int) extends BlackBox with HasBlackBoxInline {\n val io = IO(new Bundle {\n val dataIn = Input(UInt(numGPIO.W))\n val dataOut = Output(UInt(numGPIO.W))\n val dir = Input(UInt(numGPIO.W))\n val dataIO = Analog(numGPIO.W)\n })\n setInline(\n \"GPIOInOut.v\",\n s\"\"\"\|// This module is inspired by Lucas Teske's Riscow digital port\n \|// https://github.com/racerxdl/riskow/blob/main/devices/digital_port.v\n \|//\n \|module GPIOInOut (\n \| inout [${numGPIO - 1}:0] dataIO,\n \| input [${numGPIO - 1}:0] dataIn,\n", "right_context": " \| input [${numGPIO - 1}:0] dir);\n \|\n \| generate\n \| genvar idx;\n \| for(idx = 0; idx < $numGPIO; idx = idx+1) begin: register\n \| `ifdef SIMULATION\n \| assign dataIO[idx] = dir[idx] ? dataIn[idx] : 1'b0;\n \| `else\n \| assign dataIO [idx]= dir[idx] ? dataIn[idx] : 1'bZ;\n \| `endif\n \| end\n \| endgenerate\n \| assign dataOut = dataIO;\n \|\n \|endmodule\n \|\"\"\".stripMargin,\n )\n}\n", "groundtruth": " \| output [${numGPIO - 1}:0] dataOut,\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/InstructionMemory.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chisel3.util.experimental.loadMemoryFromFileInline\nimport chisel3.util.log2Ceil\n\nclass InstructionMemPort(val bitWidth: Int, val sizeBytes: Long) extends Bundle {\n val readAddr = Input(UInt(log2Ceil(sizeBytes).W))\n val readData = Output(UInt(bitWidth.W))\n val ready = Output(Bool())\n}\n\nclass InstructionMemory(\n bitWidth: Int = 32,\n sizeBytes: Long = 1,\n memoryFile: String = \"\",\n ) extends Module {\n val words = sizeBytes / bitWidth\n val io = IO(new InstructionMemPort(bitWidth, sizeBytes))\n\n val mem = Mem(words, UInt(bitWidth.W))\n // Divide memory address by 4 to get the word due to pc+4 addressing\n val readAddress = io.readAddr >> 2\n", "right_context": " io.ready := true.B\n}\n", "groundtruth": " if (memoryFile.trim().nonEmpty) {\n loadMemoryFromFileInline(mem, memoryFile)\n }\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/MemoryIOManager.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chisel3.util.{Cat, Fill, is, log2Ceil, switch}\n\n/* Memory Map\n \n 0x0000_0000 - 0x0000_00FF: Reserved\n * 0x0000_0100 - 0x0000_0FFF: Debug\n * 0x0000_1000 - 0x0000_1FFF: Syscon\n * 0x0000_2000 - 0x0000_FFFF: Reserved\n * 0x0003_0000 - 0x0003_FFFF: ROM (64KB)\n * 0x0001_0000 - 0x2FFF_FFFF: Reserved\n * 0x3000_0000 - 0x3000_0FFF: UART0\n * 0x00 (TX Write)\n * 0x04 (RX Read)\n * 0x0C (Status Read) [txFull\|rxFull\|txEmpty\|rxEmpty]\n * 0x10 (Clock Divisor Read/Write)\n * 0x3000_1000 - 0x3000_1FFF: GPIO0\n * 0x00 (direction - 0: input, 1: output)\n * 0x04 (value - 0: low, 1: high)\n * 0x3000_2000 - 0x3000_2FFF: PWM0\n * 0x3000_3000 - 0x3000_3FFF: Timer0\n * 0x00 (32 bit value in miliseconds)\n * 0x3000_4000 - 0x3FFF_FFFF: Reserved\n * 0x4000_0000 - 0x4FFF_FFFF: Reserved\n * 0x5000_0000 - 0x7000_0000: Reserved\n * 0x8000_0000 - 0x8FFF_FFFF: On-chip memory RAM\n * 0x9000_0000 - 0x9FFF_FFFF: Reserved\n /\n\nclass MMIOPort(val bitWidth: Int, val addressSize: Long) extends Bundle {\n val writeRequest = Input(Bool())\n val readRequest = Input(Bool())\n val readAddr = Input(UInt(log2Ceil(addressSize).W))\n val readData = Output(UInt(bitWidth.W))\n val writeAddr = Input(UInt(log2Ceil(addressSize).W))\n val writeData = Input(UInt(bitWidth.W))\n val writeMask = Input(UInt((bitWidth / 8).W))\n val dataSize = Input(UInt(2.W))\n}\n\nclass MemoryIOManager(bitWidth: Int = 32, sizeBytes: Long = 1024) extends Module {\n val io = IO(new Bundle {\n val MemoryIOPort = new MMIOPort(bitWidth, scala.math.pow(2, bitWidth).toLong)\n val GPIO0Port = Flipped(new GPIOPort(bitWidth))\n val Timer0Port = Flipped(new TimerPort(bitWidth))\n val UART0Port = Flipped(new UARTPort)\n val DataMemPort = Flipped(new MemoryPortDual(bitWidth, sizeBytes))\n val SysconPort = Flipped(new SysconPort(bitWidth))\n val stall = Output(Bool())\n })\n\n val dataOut = WireDefault(0.U(bitWidth.W))\n val readAddress = io.MemoryIOPort.readAddr\n val writeAddress = io.MemoryIOPort.writeAddr\n\n // Initialize IO\n io.GPIO0Port.dataIn := 0.U\n io.GPIO0Port.writeValue := false.B\n io.GPIO0Port.writeDirection := false.B\n\n io.Timer0Port.dataIn := 0.U\n io.Timer0Port.writeEnable := false.B\n\n io.UART0Port.txQueue.valid := false.B\n io.UART0Port.txQueue.bits := 0.U\n io.UART0Port.rxQueue.ready := false.B\n io.UART0Port.clockDivisor.bits := 0.U\n io.UART0Port.clockDivisor.valid := false.B\n\n io.DataMemPort.writeEnable := false.B\n io.DataMemPort.writeData := 0.U\n io.DataMemPort.readAddress := 0.U\n io.DataMemPort.writeAddress := 0.U\n io.DataMemPort.dataSize := 0.U\n io.DataMemPort.writeMask := 0.U\n\n io.SysconPort.Address := 0.U\n\n // Stall Management\n val stallLatency = WireDefault(0.U(4.W))\n val stallEnable = WireDefault(false.B)\n val DACK = RegInit(0.U(2.W))\n DACK := Mux(\n DACK > 0.U,\n DACK - 1.U,\n Mux(io.MemoryIOPort.readRequest \|\| io.MemoryIOPort.writeRequest, stallLatency, 0.U),\n )\n io.stall := (io.MemoryIOPort.readRequest \|\| io.MemoryIOPort.writeRequest) && DACK =/= 1.U && stallEnable\n\n / --- Syscon --- /\n when(readAddress(31, 12) === 0x0000_1L.U && io.MemoryIOPort.readRequest) {\n io.SysconPort.Address := readAddress(11, 0)\n dataOut := io.SysconPort.DataOut\n }\n\n / --- UART0 --- /\n when(readAddress(31, 12) === 0x3000_0L.U \|\| writeAddress(31, 12) === 0x3000_0L.U) {\n // Reads\n when(io.MemoryIOPort.readRequest) {\n when(readAddress(7, 0) === 0x04.U) {\n / RX /\n when(io.UART0Port.rxQueue.valid) {\n io.UART0Port.rxQueue.ready := true.B\n dataOut := io.UART0Port.rxQueue.bits\n }\n }\n / Status /\n .elsewhen(readAddress(7, 0) === 0x0c.U) {\n dataOut := Cat(io.UART0Port.txFull, io.UART0Port.rxFull, io.UART0Port.txEmpty, io.UART0Port.rxEmpty)\n }\n / Invalid /\n .otherwise(dataOut := 0.U)\n }\n // Writes (TX)\n when(io.MemoryIOPort.writeRequest) {\n when(writeAddress(7, 0) === 0x00.U) {\n / TX /\n io.UART0Port.txQueue.valid := true.B\n io.UART0Port.txQueue.bits := io.MemoryIOPort.writeData(7, 0)\n }\n / clock divisor /\n .elsewhen(writeAddress(7, 0) === 0x10.U) {\n io.UART0Port.clockDivisor.valid := true.B\n io.UART0Port.clockDivisor.bits := io.MemoryIOPort.writeData(7, 0)\n }\n }\n }\n\n // GPIO0\n when(readAddress(31, 12) === 0x3000_1L.U \|\| writeAddress(31, 12) === 0x3000_1L.U) {\n // Reads\n when(io.MemoryIOPort.readRequest) {\n // -- Direction\n when(readAddress(7, 0) === 0x00.U) {\n dataOut := io.GPIO0Port.directionOut\n }\n // -- Value\n .elsewhen(readAddress(7, 0) === 0x04.U) {\n dataOut := io.GPIO0Port.valueOut\n }\n .otherwise(dataOut := 0.U)\n }\n // Writes\n when(io.MemoryIOPort.writeRequest) {\n // -- Direction\n when(writeAddress(7, 0) === 0x00.U) {\n io.GPIO0Port.writeDirection := io.MemoryIOPort.writeRequest\n }\n // -- Value\n .elsewhen(writeAddress(7, 0) === 0x04.U) {\n io.GPIO0Port.writeValue := io.MemoryIOPort.writeRequest\n }\n io.GPIO0Port.dataIn := io.MemoryIOPort.writeData\n }\n\n }\n\n / --- PWM0 --- /\n when(readAddress(31, 12) === 0x3000_2L.U \|\| writeAddress(31, 12) === 0x3000_2L.U) {\n dataOut := 0.U\n }\n\n / --- Timer0 --- /\n when(readAddress(31, 12) === 0x3000_3L.U \|\| writeAddress(31, 12) === 0x3000_3L.U) {\n when(io.MemoryIOPort.writeRequest) {\n io.Timer0Port.writeEnable := io.MemoryIOPort.writeRequest\n io.Timer0Port.dataIn := io.MemoryIOPort.writeData\n }\n when(io.MemoryIOPort.readRequest) {\n dataOut := io.Timer0Port.dataOut\n }\n }\n\n / --- Data Memory --- /\n when(readAddress(31, 28) === 0x8.U \|\| writeAddress(31, 28) === 0x8.U) {\n // Stall core for 1 cycle\n stallLatency := 1.U\n stallEnable := true.B\n io.DataMemPort.readAddress := Cat(Fill(4, 0.U), readAddress(27, 0))\n\n switch(io.MemoryIOPort.dataSize) {\n is(3.U)(dataOut := io.DataMemPort.readData) // Read word\n is(2.U) { // Read halfword\n switch(io.DataMemPort.readAddress(1).asUInt) {\n is(1.U)(dataOut := Cat(Fill(16, 0.U), io.DataMemPort.readData(31, 16).asUInt)) // Read half word 1\n is(0.U)(dataOut := Cat(Fill(16, 0.U), io.DataMemPort.readData(15, 0).asUInt)) // Read half word 0\n }\n }\n is(1.U) { // Write byte\n switch(io.DataMemPort.readAddress(1, 0)) {\n is(3.U)(dataOut := Cat(Fill(24, 0.U), io.DataMemPort.readData(31, 24).asUInt)) // Read byte 3\n is(2.U)(dataOut := Cat(Fill(24, 0.U), io.DataMemPort.readData(23, 16).asUInt)) // Read byte 2\n is(1.U)(dataOut := Cat(Fill(24, 0.U), io.DataMemPort.readData(15, 8).asUInt)) // Read byte 1\n is(0.U)(dataOut := Cat(Fill(24, 0.U), io.DataMemPort.readData(7, 0).asUInt)) // Read byte 0\n }\n }\n }\n\n when(io.MemoryIOPort.writeRequest) {\n when(!io.stall) {\n val dataToWrite = WireDefault(0.U(bitWidth.W))\n val writeMask = WireDefault(0.U(4.W))\n\n io.DataMemPort.writeAddress := Cat(Fill(4, 0.U), writeAddress(27, 0))\n io.DataMemPort.writeEnable := io.MemoryIOPort.writeRequest\n\n switch(io.MemoryIOPort.dataSize) {\n is(3.U) { // Write word\n dataToWrite := io.MemoryIOPort.writeData\n writeMask := \"b1111\".U\n", "right_context": " writeMask := \"b0011\".U\n }\n }\n }\n is(1.U) { // Write byte\n switch(io.DataMemPort.writeAddress(1, 0)) {\n is(3.U) { // Write byte 3\n dataToWrite := Cat(io.MemoryIOPort.writeData(7, 0).asUInt, Fill(24, 0.U))\n writeMask := \"b1000\".U\n }\n is(2.U) { // Write byte 2\n dataToWrite := Cat(Fill(8, 0.U), io.MemoryIOPort.writeData(7, 0).asUInt, Fill(16, 0.U))\n writeMask := \"b0100\".U\n }\n is(1.U) { // Write byte 2\n dataToWrite := Cat(Fill(16, 0.U), io.MemoryIOPort.writeData(7, 0).asUInt, Fill(8, 0.U))\n writeMask := \"b0010\".U\n }\n is(0.U) { // Write byte 0\n dataToWrite := Cat(Fill(24, 0.U), io.MemoryIOPort.writeData(7, 0).asUInt)\n writeMask := \"b0001\".U\n }\n }\n }\n }\n\n val dataIn = Cat(\n Mux(writeMask(3), dataToWrite(3 8 + 7, 3 * 8), io.DataMemPort.readData(3 * 8 + 7, 3 * 8)),\n Mux(writeMask(2), dataToWrite(2 * 8 + 7, 2 * 8), io.DataMemPort.readData(2 * 8 + 7, 2 * 8)),\n Mux(writeMask(1), dataToWrite(1 * 8 + 7, 1 * 8), io.DataMemPort.readData(1 * 8 + 7, 1 * 8)),\n Mux(writeMask(0), dataToWrite(0 * 8 + 7, 0 * 8), io.DataMemPort.readData(0 * 8 + 7, 0 * 8)),\n )\n io.DataMemPort.writeData := dataIn\n dataOut := dataIn\n }\n }\n }\n\n io.MemoryIOPort.readData := dataOut\n}\n", "groundtruth": " }\n is(2.U) { // Write halfword\n switch(io.DataMemPort.writeAddress(1).asUInt) {\n is(1.U) { // Write half word 1\n dataToWrite := Cat(io.MemoryIOPort.writeData(15, 0).asUInt, Fill(16, 0.U))\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/PLLBlackBox.scala", "left_context": "package chiselv\n\nimport scala.io.Source\n\nimport chisel3._\nimport chisel3.util.HasBlackBoxInline\n\nclass PLL0(board: String) extends BlackBox with HasBlackBoxInline {\n val io = IO(new Bundle {\n val clki = Input(Clock())\n val clko = Output(Clock());\n", "right_context": "", "groundtruth": " val lock = Output(Clock())\n })\n\n val filename = \"pll_\" + board + \".v\"\n val verilog = Source.fromResource(filename).getLines().mkString(\"\\n\")\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/ProgramCounter.scala", "left_context": "package chiselv\n\nimport chisel3._\n\nclass PCPort(bitWidth: Int = 32) extends Bundle {\n val dataIn = Input(UInt(bitWidth.W))\n", "right_context": " val writeAdd = Input(Bool()) // 1 => Add dataIn to PC, 0 => Set dataIn to PC\n}\n\nclass ProgramCounter(regWidth: Int = 32, entryPoint: Long = 0) extends Module {\n val io = IO(new PCPort(regWidth))\n\n val pc = RegInit(entryPoint.U(regWidth.W))\n when(io.writeEnable) {\n pc := Mux(io.writeAdd, (pc.asSInt + io.dataIn.asSInt).asUInt, io.dataIn)\n }\n io.PC4 := pc + 4.U\n io.PC := pc\n}\n", "groundtruth": " val PC = Output(UInt(bitWidth.W))\n val PC4 = Output(UInt(bitWidth.W))\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/RVFI_Wrapper.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chisel3.util.{is, switch}\nimport circt.stage.ChiselStage\nimport mainargs.{Leftover, ParserForMethods, arg, main}\n\n// Chisel Bundle implementation of RISC-V Formal Interface (RVFI)\nclass RVFIPort extends Bundle {\n val valid = Output(Bool())\n val order = Output(UInt(64.W))\n val insn = Output(UInt(32.W))\n val trap = Output(Bool())\n val halt = Output(Bool())\n val intr = Output(Bool())\n val ixl = Output(UInt(2.W))\n val mode = Output(UInt(2.W))\n val rs1_addr = Output(UInt(5.W))\n val rs1_rdata = Output(UInt(32.W))\n val rs2_addr = Output(UInt(5.W))\n val rs2_rdata = Output(UInt(32.W))\n val rd_addr = Output(UInt(5.W))\n val rd_wdata = Output(UInt(32.W))\n val pc_rdata = Output(UInt(32.W))\n val pc_wdata = Output(UInt(32.W))\n val mem_addr = Output(UInt(32.W))\n val mem_rmask = Output(UInt(4.W))\n val mem_wmask = Output(UInt(4.W))\n val mem_rdata = Output(UInt(32.W))\n val mem_wdata = Output(UInt(32.W))\n}\n\nclass RVFICPUWrapper(\n cpuFrequency: Int = 50000000,\n bitWidth: Int = 32,\n instructionMemorySize: Int = 64 * 1024,\n dataMemorySize: Int = 64 * 1024,\n ) extends CPUSingleCycle(\n cpuFrequency = cpuFrequency,\n entryPoint = 0x0,\n bitWidth = bitWidth,\n instructionMemorySize = instructionMemorySize,\n dataMemorySize = dataMemorySize,\n numGPIO = 0,\n ) {\n val rvfi = IO(new RVFIPort) // RVFI interface for RISCV-Formal\n\n // RVFI Interface\n val rvfi_valid = RegInit(false.B)\n val rvfi_order = RegInit(0.U(64.W))\n val rvfi_insn = RegInit(0.U(32.W))\n\n val rvfi_halt = RegInit(false.B)\n\n val rvfi_intr = RegInit(false.B)\n val rvfi_mode = RegInit(3.U(2.W))\n\n val rvfi_mem_size_mask = WireDefault(0.U(2.W))\n switch(memoryIOManager.io.DataMemPort.dataSize) {\n is(1.U)(rvfi_mem_size_mask := 1.U)\n is(2.U)(rvfi_mem_size_mask := 3.U)\n is(3.U)(rvfi_mem_size_mask := 15.U)\n }\n\n // Connect RVFI interface outputs\n rvfi_valid := !reset.asBool && !stall\n when(rvfi_valid) {\n rvfi_order := rvfi_order + 1.U\n }\n rvfi.valid := rvfi_valid\n rvfi.order := rvfi_order\n", "right_context": " rvfi.rs1_rdata := registerBank.io.rs1\n rvfi.rs2_addr := registerBank.io.rs2_addr\n rvfi.rs2_rdata := registerBank.io.rs2\n rvfi.rd_addr := registerBank.io.regwr_addr\n rvfi.rd_wdata := registerBank.io.regwr_data\n\n rvfi.pc_rdata := PC.io.PC\n rvfi.pc_wdata := Mux(\n PC.io.writeAdd,\n (PC.io.PC.asSInt + PC.io.dataIn.asSInt).asUInt,\n PC.io.PC4,\n )\n\n rvfi.mem_addr := Mux(decoder.io.is_load \|\| decoder.io.is_store, ALU.io.x, 0.U)\n rvfi.mem_rdata := Mux(decoder.io.is_load, memoryIOManager.io.DataMemPort.readData, 0.U)\n rvfi.mem_rmask := Mux(decoder.io.is_load, rvfi_mem_size_mask, 0.U)\n\n rvfi.mem_wdata := Mux(decoder.io.is_store, memoryIOManager.io.DataMemPort.writeData, 0.U)\n rvfi.mem_wmask := Mux(decoder.io.is_store, rvfi_mem_size_mask, 0.U)\n\n rvfi.mode := rvfi_mode\n rvfi.trap := false.B\n when(decoder.io.inst === Instruction.ERR_INST) {\n rvfi.trap := true.B\n }\n\n rvfi.halt := rvfi_halt\n rvfi.intr := rvfi_intr\n rvfi.ixl := 1.U\n}\n\n// This is the Topmodule used in RISCV-Formal\nclass RVFI(\n bitWidth: Int = 32\n ) extends Module {\n val io = IO(new Bundle {\n val imem_addr = Output(UInt(bitWidth.W))\n val imem_ready = Input(Bool())\n val imem_rdata = Input(UInt(bitWidth.W))\n\n val dmem_rdata = Input(UInt(bitWidth.W))\n val dmem_raddr = Output(UInt(bitWidth.W))\n val dmem_waddr = Output(UInt(bitWidth.W))\n val dmem_wdata = Output(UInt(bitWidth.W))\n val dmem_wen = Output(Bool())\n })\n val rvfi = IO(new RVFIPort) // RVFI interface for RISCV-Formal\n\n // Instantiate the wrapped CPU with RVFI interface\n val CPU = Module(\n new RVFICPUWrapper(bitWidth)\n )\n\n // Initialize unused IO\n CPU.io.UART0Port.rxQueue.bits := 0.U\n CPU.io.UART0Port.rxEmpty := true.B\n CPU.io.UART0Port.txQueue.ready := true.B\n CPU.io.UART0Port.txFull := false.B\n CPU.io.UART0Port.txEmpty := true.B\n CPU.io.UART0Port.rxFull := false.B\n CPU.io.UART0Port.rxQueue.valid := false.B\n CPU.io.SysconPort.DataOut := 0.U\n\n // Connect RVFI port\n rvfi <> CPU.rvfi\n\n // Connect instruction memory\n io.imem_addr := CPU.io.instructionMemPort.readAddr\n CPU.io.instructionMemPort.readData := io.imem_rdata\n CPU.io.instructionMemPort.ready := io.imem_ready\n\n // Connect data memory\n io.dmem_waddr := CPU.io.dataMemPort.writeAddress\n io.dmem_wdata := CPU.io.dataMemPort.writeData\n io.dmem_wen := CPU.io.dataMemPort.writeEnable\n\n io.dmem_raddr := CPU.io.dataMemPort.readAddress\n CPU.io.dataMemPort.readData := io.dmem_rdata\n}\n\nobject RVFI {\n @main\n def run(@arg(short = 'c', doc = \"Chisel arguments\") chiselArgs: Leftover[String]) =\n // Generate SystemVerilog\n ChiselStage.emitSystemVerilogFile(\n new RVFI,\n chiselArgs.value.toArray,\n Array(\n // Removes debug information from the generated Verilog\n \"--strip-debug-info\",\n // Disables reg and memory randomization on initialization\n \"--disable-all-randomization\",\n // Creates memories with write masks in a single reg. Ref. https://github.com/llvm/circt/pull/4275\n \"--lower-memories\",\n // Avoids \"unexpected TOK_AUTOMATIC\" errors in Yosys. Ref. https://github.com/llvm/circt/issues/4751\n \"--lowering-options=disallowLocalVariables,disallowPackedArrays\",\n // Splits the generated Verilog into multiple files\n // \"--split-verilog\",\n // Generates the Verilog files in the specified directory\n \"-o=./generated/Toplevel_RVFI.sv\",\n ),\n )\n\n def main(args: Array[String]): Unit =\n ParserForMethods(this).runOrExit(args.toIndexedSeq)\n}\n", "groundtruth": " rvfi.insn := decoder.io.op\n\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/RegisterBank.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chisel3.util.log2Ceil\n\nclass RegisterBankPort(bitWidth: Int = 32) extends Bundle {\n val rs1 = Output(UInt(bitWidth.W))\n val rs2 = Output(UInt(bitWidth.W))\n val rs1_addr = Input(UInt(log2Ceil(bitWidth).W))\n val rs2_addr = Input(UInt(log2Ceil(bitWidth).W))\n", "right_context": " val stall = Input(Bool()) // >1 => Stall, 0 => Run\n}\n\nclass RegisterBank(numRegs: Int = 32, regWidth: Int = 32) extends Module {\n val io = IO(new RegisterBankPort(regWidth))\n\n val regs = RegInit(VecInit(Seq.fill(numRegs)(0.U(regWidth.W))))\n regs(0) := 0.U // Register x0 is always 0\n\n io.rs1 := regs(io.rs1_addr)\n io.rs2 := regs(io.rs2_addr)\n when(io.writeEnable && io.regwr_addr =/= 0.U && !io.stall) {\n regs(io.regwr_addr) := io.regwr_data\n }\n}\n", "groundtruth": " val regwr_addr = Input(UInt(log2Ceil(bitWidth).W))\n val regwr_data = Input(UInt(bitWidth.W))\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/SOC.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chisel3.experimental.Analog\n\nclass SOC(\n cpuFrequency: Int,\n entryPoint: Long,\n bitWidth: Int = 32,\n instructionMemorySize: Int = 1 * 1024,\n dataMemorySize: Int = 1 * 1024,\n memoryFile: String = \"\",\n ramFile: String = \"\",\n numGPIO: Int = 8,\n ) extends Module {\n val io = IO(new Bundle {\n val led0 = Output(Bool()) // LED 0 is the heartbeat\n val GPIO0External = Analog(numGPIO.W) // GPIO external port\n val UART0SerialPort = new UARTSerialPort // UART0 serial port\n })\n\n // Heartbeat LED - Keep on if reached an error\n val blink = Module(new Blinky(cpuFrequency))\n io.led0 := blink.io.led0\n\n // Instantiate and initialize the Instruction memory\n val instructionMemory = Module(new InstructionMemory(bitWidth, instructionMemorySize, memoryFile))\n instructionMemory.io.readAddr := 0.U\n\n // Instantiate and initialize the Data memory\n val dataMemory = Module(new DualPortRAM(bitWidth, dataMemorySize, ramFile))\n dataMemory.io.writeEnable := false.B\n dataMemory.io.writeData := 0.U\n dataMemory.io.readAddress := 0.U\n dataMemory.io.writeAddress := 0.U\n dataMemory.io.dataSize := 0.U\n dataMemory.io.writeMask := 0.U\n\n // Instantiate and connect the UART\n val fifoLength = 128\n val rxOverclock = 16\n val UART0 = Module(new Uart(fifoLength, rxOverclock))\n UART0.io.serialPort <> io.UART0SerialPort\n\n // Instantiate the Syscon Module\n val syscon = Module(new Syscon(32, cpuFrequency, numGPIO, entryPoint, instructionMemorySize, dataMemorySize))\n\n // Instantiate our core\n val core = Module(\n new CPUSingleCycle(cpuFrequency, entryPoint, bitWidth, instructionMemorySize, dataMemorySize, numGPIO)\n )\n\n // Connect the core to the devices\n core.io.instructionMemPort <> instructionMemory.io\n core.io.dataMemPort <> dataMemory.io\n core.io.UART0Port <> UART0.io.dataPort\n core.io.SysconPort <> syscon.io\n", "right_context": "", "groundtruth": " if (numGPIO > 0) {\n core.io.GPIO0External <> io.GPIO0External\n }\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/Syscon.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chisel3.util.{is, switch}\n\n", "right_context": " clockFreq: Long,\n numGPIO0: Int,\n bootAddr: Long,\n romSize: Int,\n ramSize: Int,\n ) extends Module {\n val io = IO(new SysconPort(bitWidth))\n\n val dataOut = WireDefault(0.U(bitWidth.W))\n\n switch(io.Address) {\n is(0x0L.U)(dataOut := 0xbaad_cafeL.U)\n // Clock frequency - (0x0000_1008)\n is(0x8L.U)(dataOut := clockFreq.asUInt)\n // Has UART0 - (0x0000_1010)\n is(0x10L.U)(dataOut := 1.U)\n // Has GPIO0 - (0x0000_1018)\n is(0x18L.U)(dataOut := 1.U)\n // Has PWM0 - (0x0000_1020)\n is(0x20L.U)(dataOut := 0.U)\n // Has Timer0 - (0x0000_1024)\n is(0x24L.U)(dataOut := 1.U)\n // Num GPIOs in GPIO0 - (0x0000_1028)\n is(0x28L.U)(dataOut := numGPIO0.asUInt)\n // Boot io.address - (0x0000_102c)\n is(0x2cL.U)(dataOut := bootAddr.asUInt)\n // ROM Size - (0x0000_1030)\n is(0x30L.U)(dataOut := romSize.asUInt)\n // RAM Size - (0x0000_1034)\n is(0x34L.U)(dataOut := ramSize.asUInt)\n }\n\n io.DataOut := dataOut\n}\n", "groundtruth": "class SysconPort(val bitWidth: Int) extends Bundle {\n val Address = Input(UInt(12.W))\n val DataOut = Output(UInt(bitWidth.W))\n}\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/Timer.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chisel3.util.Counter\n\nclass TimerPort(bitWidth: Int = 32) extends Bundle {\n val dataIn = Input(UInt(bitWidth.W))\n val dataOut = Output(UInt(bitWidth.W))\n val writeEnable = Input(Bool())\n val stall = Output(Bool()) // >1 => Stall, 0 => Run\n}\n\nclass Timer(bitWidth: Int = 32, cpuFrequency: Int) extends Module {\n val io = IO(new TimerPort(bitWidth))\n\n val counter = RegInit(0.U(bitWidth.W))\n\n when(io.writeEnable) {\n counter := io.dataIn\n }.otherwise {\n // Count up in milliseconds\n val (_, counterWrap) = Counter(true.B, cpuFrequency / 1000)\n", "right_context": " io.stall := false.B\n}\n", "groundtruth": " when(counterWrap) {\n counter := counter + 1.U\n }\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/Toplevel.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chisel3.experimental.Analog\nimport circt.stage.ChiselStage\nimport mainargs.{Leftover, ParserForMethods, arg, main}\n\n// Project Top level\nclass Toplevel(\n board: String,\n invReset: Boolean = true,\n cpuFrequency: Int,\n ) extends Module {\n val io = FlatIO(new Bundle {\n val led0 = Output(Bool()) // LED 0 is the heartbeat\n val UART0 = new UARTSerialPort // UART 0\n val GPIO0 = Analog(8.W) // GPIO 0\n })\n\n // Instantiate PLL module based on board\n val pll = Module(new PLL0(board))\n pll.io.clki := clock\n // Define if reset should be inverted based on board switch\n", "right_context": "\n // Instantiate the Core connecting using the PLL clock\n withClockAndReset(pll.io.clko, customReset) {\n val bitWidth = 32\n val instructionMemorySize = 64 * 1024\n val dataMemorySize = 64 * 1024\n val numGPIO = 8\n\n val SOC =\n Module(\n new SOC(\n cpuFrequency = cpuFrequency,\n entryPoint = 0x00000000,\n bitWidth = bitWidth,\n instructionMemorySize = instructionMemorySize,\n dataMemorySize = dataMemorySize,\n memoryFile = \"progload.mem\",\n ramFile = \"progload-RAM.mem\",\n numGPIO = numGPIO,\n )\n )\n\n // Connect IO\n io.led0 <> SOC.io.led0\n io.GPIO0 <> SOC.io.GPIO0External\n io.UART0 <> SOC.io.UART0SerialPort\n }\n}\n\n// The Main object extending App to generate the Verilog code.\nobject Toplevel {\n @main\n def run(\n // Parse command line arguments and extract required parameters\n @arg(short = 'b', doc = \"FPGA Board to use\") board: String = \"bypass\",\n @arg(short = 'r', doc = \"FPGA Board have inverted reset\") invreset: Boolean = false,\n @arg(short = 'f', doc = \"CPU Frequency to run core\") cpufreq: Int = 50000000,\n @arg(short = 'c', doc = \"Chisel arguments\") chiselArgs: Leftover[String],\n ) =\n // Generate SystemVerilog\n ChiselStage.emitSystemVerilogFile(\n new Toplevel(board, invreset, cpufreq),\n chiselArgs.value.toArray,\n Array(\n // Removes debug information from the generated Verilog\n \"--strip-debug-info\",\n // Disables reg and memory randomization on initialization\n \"--disable-all-randomization\",\n // Creates memories with write masks in a single reg. Ref. https://github.com/llvm/circt/pull/4275\n \"--lower-memories\",\n // Avoids \"unexpected TOK_AUTOMATIC\" errors in Yosys. Ref. https://github.com/llvm/circt/issues/4751\n \"--lowering-options=disallowLocalVariables,disallowPackedArrays\",\n ),\n )\n\n def main(args: Array[String]): Unit =\n ParserForMethods(this).runOrExit(args.toIndexedSeq)\n}\n", "groundtruth": " val customReset = if (invReset) ~reset.asBool else reset\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/src/Uart.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chisel3.util._\n\n/\n A simple TTL serial module. Idle is high. Start bits are low, stop bits\n * are high and we send each byte out LSB first. We only implement 8n1,\n * ie 1 start bit, no parity and 1 stop bit. There is no flow control, so\n * we might overflow the RX fifo if the rxQueue consumer can't keep up.\n \n We oversample RX. clockDivisor is set as follows:\n \n clockDivisor = (clock_freq / (baudrate * rxOverclock)) - 1\n \n When programming the divider, software currently assumes we overclock 16x.\n \n Also note that if the input clock frequency is low enough then the errors\n * introduced by oversampling might be significant. Eg at 10MHz, 115200 baud,\n * 16x oversampling we have almost 8% error and the UART fails to work.\n \n This file has been created by Anton Blanchard on Chiselwatt repository at:\n * https://github.com/antonblanchard/chiselwatt\n /\n\nclass UARTSerialPort extends Bundle {\n val rx = Input(UInt(1.W))\n val tx = Output(UInt(1.W))\n}\n\nclass UARTPort extends Bundle {\n val rxQueue = Decoupled(UInt(8.W))\n val txQueue = Flipped(Decoupled(UInt(8.W)))\n val rxEmpty = Output(Bool())\n val txEmpty = Output(Bool())\n val rxFull = Output(Bool())\n val txFull = Output(Bool())\n val clockDivisor = Flipped(Valid(UInt(8.W)))\n}\n\nclass Uart(val fifoLength: Int, val rxOverclock: Int) extends Module {\n val io = IO(new Bundle {\n val serialPort = new UARTSerialPort\n val dataPort = new UARTPort\n })\n\n require(isPow2(rxOverclock))\n\n val sampleClk = RegInit(0.U(1.W))\n val sampleClkCounter = RegInit(0.U(8.W))\n val clockDivisor = RegInit(0.U(8.W))\n\n when(io.dataPort.clockDivisor.valid) {\n clockDivisor := io.dataPort.clockDivisor.bits\n }\n\n val txQueue = Module(new Queue(UInt(8.W), fifoLength))\n val rxQueue = Module(new Queue(UInt(8.W), fifoLength))\n\n io.dataPort.rxEmpty := rxQueue.io.count === 0.U\n io.dataPort.txEmpty := txQueue.io.count === 0.U\n io.dataPort.rxFull := rxQueue.io.count === fifoLength.U\n io.dataPort.txFull := txQueue.io.count === fifoLength.U\n\n val uartEnabled = clockDivisor.orR\n\n when(uartEnabled) {\n when(sampleClkCounter === clockDivisor) {\n sampleClk := 1.U\n sampleClkCounter := 0.U\n }.otherwise {\n sampleClk := 0.U\n sampleClkCounter := sampleClkCounter + 1.U\n }\n }.otherwise {\n sampleClk := 0.U\n sampleClkCounter := 0.U\n }\n\n /\n * Our TX clock needs to match our baud rate. This means we need to\n * further divide sampleClk by rxOverclock.\n /\n val (txCounterValue, txCounterWrap) = Counter(sampleClk === 1.U, rxOverclock)\n val txClk = txCounterWrap\n\n / TX /\n val sTxIdle :: sTxTx :: sTxStop :: Nil = Enum(3)\n val txState = RegInit(sTxIdle)\n val txByte = Reg(UInt(8.W))\n val txByteBit = Reg(UInt(3.W))\n / RS232 idle state is high /\n val tx = RegInit(1.U(1.W))\n\n txQueue.io.deq.ready := false.B\n\n / We run the tx state machine off the txClk /\n when(txClk === 1.U) {\n switch(txState) {\n is(sTxIdle) {\n / Does the FIFO contain data? /\n when(txQueue.io.deq.valid) {\n txQueue.io.deq.ready := true.B\n txByte := txQueue.io.deq.bits\n txByteBit := 0.U\n txState := sTxTx\n / Send start bit /\n tx := 0.U\n }.otherwise {\n tx := 1.U\n }\n }\n\n is(sTxTx) {\n when(txByteBit === 7.U) {\n txState := sTxStop\n }\n tx := txByte(txByteBit)\n txByteBit := txByteBit + 1.U\n }\n\n is(sTxStop) {\n txState := sTxIdle\n / Send stop bit /\n tx := 1.U\n }\n }\n }\n\n io.serialPort.tx := tx\n\n / RX /\n val sRxIdle :: sRxStart :: sRxRx :: sRxStop :: sRxError1 :: sRxError2 :: Nil =\n Enum(6)\n val rxState = RegInit(sRxIdle)\n val rxCounter = RegInit(0.U(log2Ceil(rxOverclock).W))\n val rxByte = RegInit(VecInit(Seq.fill(8)(0.U(1.W))))\n val rxByteBit = RegInit(0.U(3.W))\n\n rxQueue.io.enq.bits := 0.U\n rxQueue.io.enq.valid := false.B\n\n / Synchronize the input to avoid any metastability issues /\n val rx = RegNext(RegNext(RegNext(io.serialPort.rx)))\n\n when(sampleClk === 1.U) {\n switch(rxState) {\n is(sRxIdle) {\n when(rx === 0.U) {\n rxState := sRxStart\n rxCounter := 1.U\n rxByte := Seq.fill(8)(0.U)\n rxByteBit := 0.U\n }\n }\n\n is(sRxStart) {\n rxCounter := rxCounter + 1.U\n / We should be at the middle of the start bit /\n when(rxCounter === (rxOverclock / 2).U) {\n rxCounter := 1.U\n rxState := sRxRx\n }\n }\n\n is(sRxRx) {\n rxCounter := rxCounter + 1.U\n when(rxCounter === 0.U) {\n when(rxByteBit === 7.U) {\n rxState := sRxStop\n }\n rxByte(rxByteBit) := rx\n rxByteBit := rxByteBit + 1.U\n }\n }\n\n is(sRxStop) {\n rxCounter := rxCounter + 1.U\n when(rxCounter === 0.U) {\n / Ensure the stop bit is high /\n", "right_context": " }\n }\n\n /\n * We might not have synchronised on a start bit. Delay 2 bits on\n * each error so we eventually line up with the start bit.\n /\n is(sRxError1) {\n / Delay one bit /\n rxCounter := rxCounter + 1.U\n when(rxCounter === 0.U) {\n rxState := sRxError2\n }\n }\n\n is(sRxError2) {\n / Delay another bit /\n rxCounter := rxCounter + 1.U\n when(rxCounter === 0.U) {\n rxState := sRxIdle\n }\n }\n }\n }\n\n rxQueue.io.deq <> io.dataPort.rxQueue\n txQueue.io.enq <> io.dataPort.txQueue\n}\n", "groundtruth": " when(rx === 1.U) {\n / We might overflow the queue if we can't keep up */\n rxQueue.io.enq.bits := rxByte.reverse.reduce(_ ## _)\n rxQueue.io.enq.valid := true.B\n rxState := sRxIdle\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/test/src/ALUSpec.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chiseltest._\nimport com.carlosedp.riscvassembler.ObjectUtils.NumericManipulation\nimport org.scalatest._\n\nimport Instruction._\nimport flatspec._\nimport matchers._\n\nclass ALUSpec extends AnyFlatSpec with ChiselScalatestTester with should.Matchers {\n val one = BigInt(1)\n val max = (one << 32) - one\n val min_signed = one << 32 - 1\n val max_signed = (one << 32 - 1) - one\n val cases =\n Array[BigInt](1, 2, 4, 123, -1, -2, -4, 0, 0x7fffffffL, 0x80000000L, max, min_signed, max_signed) ++ Seq.fill(10)(\n BigInt(scala.util.Random.nextInt())\n )\n\n it should \"ADD\" in {\n testCycle(ADD)\n }\n it should \"ADDI\" in {\n testCycle(ADDI)\n }\n it should \"SUB\" in {\n testCycle(SUB)\n }\n it should \"AND\" in {\n testCycle(AND)\n }\n it should \"ANDI\" in {\n testCycle(ANDI)\n }\n it should \"OR\" in {\n testCycle(OR)\n }\n it should \"ORI\" in {\n testCycle(ORI)\n }\n it should \"XOR\" in {\n testCycle(XOR)\n }\n it should \"XORI\" in {\n testCycle(XORI)\n }\n it should \"SRA\" in {\n testCycle(SRA)\n }\n it should \"SRAI\" in {\n testCycle(SRAI)\n }\n it should \"SRL\" in {\n testCycle(SRL)\n }\n it should \"SRLI\" in {\n testCycle(SRLI)\n }\n it should \"SLL\" in {\n testCycle(SLL)\n }\n it should \"SLLI\" in {\n testCycle(SLLI)\n }\n it should \"SLT\" in {\n testCycle(SLT)\n }\n it should \"SLTI\" in {\n testCycle(SLTI)\n }\n it should \"SLTU\" in {\n testCycle(SLTU)\n }\n it should \"SLTIU\" in {\n testCycle(SLTIU)\n }\n it should \"EQ\" in {\n testCycle(EQ)\n }\n it should \"NEQ\" in {\n testCycle(NEQ)\n }\n it should \"GT\" in {\n testCycle(GTE)\n }\n it should \"GTU\" in {\n testCycle(GTEU)\n }\n // --------------------- Test Helpers ---------------------\n def aluHelper(\n a: BigInt,\n b: BigInt,\n op: Type,\n ): BigInt =\n op match {\n case ADD \| ADDI => (a + b).to32Bit\n case SUB => a - b\n case AND \| ANDI => a & b\n case OR \| ORI => a \| b\n case XOR \| XORI => a ^ b\n case SRA \| SRAI => a.toInt >> (b.toInt & 0x1f)\n case SRL \| SRLI => a.toInt >>> b.toInt\n case SLL \| SLLI => a.toInt << b.toInt\n case SLT \| SLTI => if (a.toInt < b.toInt) 1 else 0\n case SLTU \| SLTIU => if (a.to32Bit < b.to32Bit) 1 else 0\n case EQ => if (a.to32Bit == b.to32Bit) 1 else 0\n case NEQ => if (a.to32Bit != b.to32Bit) 1 else 0\n", "right_context": " case GTEU => if (a.to32Bit >= b.to32Bit) 1 else 0\n case _ => 0 // Never happens\n }\n\n def testDut(\n i: BigInt,\n j: BigInt,\n out: BigInt,\n op: Type,\n dut: ALU,\n ) = {\n // print(s\"Inputs: $i $op $j \| Test result should be ${aluHelper(i, j, op)} \| \")\n dut.io.inst.poke(op)\n dut.io.a.poke(i.to32Bit)\n dut.io.b.poke(j.to32Bit)\n dut.clock.step()\n dut.io.x.peekInt() should be(out)\n }\n def testCycle(\n op: Type\n ) =\n test(new ALU) { c =>\n cases.foreach { i =>\n cases.foreach { j =>\n testDut(i, j, aluHelper(i, j, op).to32Bit, op, c)\n }\n }\n }\n\n def toUInt(\n i: BigInt\n ) = i.to32Bit.asUInt(32.W)\n}\n", "groundtruth": " case GTE => if (a.toInt >= b.toInt) 1 else 0\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/test/src/CPUDemoAppsSpec.scala", "left_context": "package chiselv\n\nimport chiseltest._\nimport chiseltest.experimental._\nimport org.scalatest._\n\nimport flatspec._\nimport matchers._\n\n// Extend the SOC module to add the observer for sub-module signals\nclass SOCWrapperDemo(\n cpuFrequency: Int,\n bitWidth: Int,\n instructionMemorySize: Int,\n memorySize: Int,\n memoryFile: String,\n ramFile: String,\n numGPIO: Int,\n // baudRate: Int,\n ) extends SOC(\n cpuFrequency,\n entryPoint = 0,\n bitWidth,\n instructionMemorySize,\n memorySize,\n memoryFile,\n ramFile,\n numGPIO,\n ) {\n val registers = expose(core.registerBank.regs)\n val pc = expose(core.PC.pc)\n}\n\nclass CPUDemoAppsSpec extends AnyFlatSpec with ChiselScalatestTester with should.Matchers {\n val cpuFrequency = 10000\n val bitWidth = 32\n val instructionMemorySize = 64 * 1024\n val memorySize = 64 * 1024\n\n def defaultDut(\n memoryfile: String,\n ramFile: String = \"\",\n ) =\n test(\n new SOCWrapperDemo(\n cpuFrequency,\n bitWidth,\n instructionMemorySize,\n memorySize,\n memoryfile,\n ramFile,\n 8,\n // 1200,\n )\n )\n .withAnnotations(\n Seq(\n WriteVcdAnnotation,\n VerilatorBackendAnnotation,\n )\n )\n\n behavior of \"GPIODemo\"\n it should \"lit a LED connected to GPIO from gcc program\" in {\n val filename = \"./gcc/simpleLED/main.mem\"\n defaultDut(filename) { c =>\n c.clock.setTimeout(10000)\n c.clock.step(1) // Step from initial PC\n while (c.pc.peekInt() != 0x0)\n c.clock.step(1)\n }\n }\n\n it should \"blink LED connected to GPIO0 from gcc program\" in {\n val filename = \"./gcc/blinkLED/main-rom.mem\"\n", "right_context": " it should \"print to UART0 from gcc program\" in {\n val filename = \"./gcc/helloUART/main-rom.mem\"\n val filename_ram = \"./gcc/helloUART/main-ram.mem\"\n defaultDut(filename, filename_ram) { c =>\n c.clock.setTimeout(30000)\n c.clock.step(25000)\n // while (c.pc.peekInt() != 0x90) { // 0x90 is the address of _halt\n // c.clock.step(1)\n // }\n }\n }\n}\n", "groundtruth": " defaultDut(filename) { c =>\n c.clock.setTimeout(3000)\n c.clock.step(2000)\n }\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/test/src/CPUSingleCycleAppsSpec.scala", "left_context": "package chiselv\n\nimport chiseltest._\nimport chiseltest.experimental._\nimport org.scalatest._\n\nimport flatspec._\nimport matchers._\n\n// Extend the Control module to add the observer for sub-module signals\nclass CPUSingleCycleWrapperApps(memoryFile: String) extends SOC(\n cpuFrequency = 25000000,\n entryPoint = 0,\n bitWidth = 32,\n instructionMemorySize = 1 * 1024,\n dataMemorySize = 1 * 1024,\n memoryFile = memoryFile,\n numGPIO = 0,\n ) {\n val registers = expose(core.registerBank.regs)\n val pc = expose(core.PC.pc)\n val memWriteAddr = expose(core.memoryIOManager.io.MemoryIOPort.writeAddr)\n val memWriteData = expose(core.memoryIOManager.io.MemoryIOPort.writeData)\n val memReadAddr = expose(core.memoryIOManager.io.MemoryIOPort.readAddr)\n val memReadData = expose(core.memoryIOManager.io.MemoryIOPort.readData)\n}\n\nclass CPUSingleCycleAppsSpec extends AnyFlatSpec with ChiselScalatestTester with should.Matchers {\n val writeLatency = 2\n val readLatency = 1\n\n def defaultDut(memoryfile: String) =\n test(new CPUSingleCycleWrapperApps(memoryFile = memoryfile))\n .withAnnotations(\n Seq(\n WriteVcdAnnotation\n )\n )\n\n it should \"load instructions from file to write to all registers with ADDI\" in {\n val filename = \"./gcc/test/test_addi.mem\"\n defaultDut(filename) { c =>\n c.clock.setTimeout(0)\n val results = List.fill(8)(List(0, 1000, 3000, 2000)).flatten\n for ((i, r) <- 0 until 31 zip results) {\n c.registers(i).peekInt() should be(r)\n c.clock.step(1)\n }\n c.clock.step(20)\n }\n }\n\n it should \"load program and end with 25 (0x19) in mem address 100 (0x64)\" in {\n val filename = \"./gcc/test/test_book.mem\"\n defaultDut(filename) { c =>\n c.clock.setTimeout(0)\n c.clock.step(1) // addi\n c.registers(2).peekInt() should be(5)\n c.clock.step(1) // addi\n c.registers(3).peekInt() should be(12)\n c.clock.step(1) // addi\n c.registers(7).peekInt() should be(3)\n c.clock.step(1) // lui\n c.registers(6).peekInt() should be(0x80000000L)\n c.clock.step(1) // or\n c.registers(4).peekInt() should be(7)\n c.clock.step(1) // and\n c.registers(5).peekInt() should be(4)\n c.clock.step(1) // add\n c.registers(5).peekInt() should be(11)\n c.clock.step(1) // beq (skip)\n c.clock.step(1) // slt\n c.registers(4).peekInt() should be(0)\n c.clock.step(1) // beq (skip next addi)\n c.clock.step(1) // slt\n c.registers(4).peekInt() should be(1)\n c.clock.step(1) // add\n c.registers(7).peekInt() should be(12)\n c.clock.step(1) // sub\n c.registers(7).peekInt() should be(7)\n // Check Memory write at address 0x80000000\n c.memWriteAddr.peekInt() should be(0x80000000L)\n c.memWriteData.peekInt() should be(7)\n", "right_context": " c.memReadData.peekInt() should be(7)\n c.clock.step(1 + readLatency) // lw\n c.registers(2).peekInt() should be(7)\n c.clock.step(1) // add\n c.registers(9).peekInt() should be(18)\n c.clock.step(1) // jal (skip next addi)\n c.clock.step(1) // add\n c.registers(2).peekInt() should be(25)\n // // Check Memory address 0x80000000 + 100 (0x64)\n c.memWriteAddr.peekInt() should be(0x80000000L + 0x64)\n c.memWriteData.peekInt() should be(25)\n c.clock.step(1 + writeLatency) // sw\n\n // Add some padding at the end\n c.clock.step(10)\n }\n }\n\n it should \"loop thru ascii table writing to 0x3000_0000 region\" in {\n val filename = \"./gcc/test/test_ascii.mem\"\n defaultDut(filename) { c =>\n c.clock.setTimeout(0)\n c.clock.step(1)\n c.registers(1).peekInt() should be(40)\n c.clock.step(1)\n c.registers(2).peekInt() should be(33)\n c.clock.step(1)\n c.registers(3).peekInt() should be(126)\n c.clock.step(1)\n c.registers(4).peekInt() should be(0x3000_0000)\n\n for (i <- 33 until 127) {\n // Check memory write at address 0x30000000\n c.memWriteAddr.peekInt() should be(0x30000000L)\n c.memWriteData.peekInt() should be(i)\n c.clock.step(1) // sb (no latency to write 0x30000000 region)\n c.clock.step(1) // addi\n c.clock.step(1) // bge\n }\n c.clock.step(10)\n }\n }\n}\n", "groundtruth": " c.clock.step(1 + writeLatency) // sw\n // Check Memory read at address 0x80000000\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/test/src/CPUSingleCycleIOSpec.scala", "left_context": "package chiselv\n\nimport chiseltest._\nimport chiseltest.experimental._\nimport com.carlosedp.riscvassembler.RISCVAssembler\nimport org.scalatest._\n\nimport flatspec._\nimport matchers._\n\n// Extend the Control module to add the observer for sub-module signals\nclass CPUSingleCycleIOWrapper(memoryFile: String) extends SOC(\n cpuFrequency = 25000000,\n entryPoint = 0,\n bitWidth = 32,\n instructionMemorySize = 1 * 1024,\n dataMemorySize = 1 * 1024,\n memoryFile = memoryFile,\n numGPIO = 8,\n ) {\n val registers = expose(core.registerBank.regs)\n val pc = expose(core.PC.pc)\n val memWriteAddr = expose(core.memoryIOManager.io.MemoryIOPort.writeAddr)\n val memWriteData = expose(core.memoryIOManager.io.MemoryIOPort.writeData)\n val memReadAddr = expose(core.memoryIOManager.io.MemoryIOPort.readAddr)\n val memReadData = expose(core.memoryIOManager.io.MemoryIOPort.readData)\n\n val GPIO0_value = expose(core.GPIO0.GPIO)\n val GPIO0_direction = expose(core.GPIO0.direction)\n val timerCounter = expose(core.timer0.counter)\n}\n\nclass CPUSingleCycleIOSpec\n extends AnyFlatSpec\n with ChiselScalatestTester\n with BeforeAndAfterEach\n with BeforeAndAfterAll\n with should.Matchers {\n val cpuFrequency = 25000000\n val ms = cpuFrequency / 1000\n var memoryfile: os.Path = _\n val tmpdir = os.pwd / \"tmphex\"\n\n override def beforeAll(): Unit =\n os.makeDir.all(tmpdir)\n override def afterAll(): Unit =\n scala.util.Try(os.remove(tmpdir))\n override def beforeEach(): Unit =\n memoryfile = tmpdir / (scala.util.Random.alphanumeric.filter(_.isLetter).take(15).mkString + \".hex\")\n override def afterEach(): Unit =\n os.remove.all(memoryfile)\n\n def defaultDut(prog: String) = {\n val hex = RISCVAssembler.fromString(prog)\n os.write(memoryfile, hex)\n test(new CPUSingleCycleIOWrapper(memoryFile = memoryfile.toString))\n .withAnnotations(\n Seq(\n WriteVcdAnnotation,\n VerilatorBackendAnnotation, // GPIO needs Verilator backend\n )\n )\n }\n\n it should \"write to GPIO0\" in {\n val prog = \"\"\"\n lui x1, 0x30001\n addi x5, x0, -1\n addi x3, x3, 1\n addi x4, x0, 7\n sw x5, 0(x1)\n add x2, x2, x3\n sw x2, 4(x1)\n jal x0, -8\n \"\"\"\n defaultDut(prog) { c =>\n c.clock.setTimeout(0)\n c.registers(1).peekInt() should be(0)\n c.registers(2).peekInt() should be(0)\n c.registers(3).peekInt() should be(0)\n c.registers(4).peekInt() should be(0)\n c.clock.step(1) // lui\n c.registers(1).peekInt() should be(0x30001000L)\n c.clock.step(1) // addi\n c.registers(5).peekInt() should be(0xffffffffL)\n c.clock.step(1) // addi\n c.registers(3).peekInt() should be(1)\n c.clock.step(1) // addi\n c.registers(4).peekInt() should be(7)\n // Check memory address 0x30001000L for direction (GPIO0)\n c.memWriteAddr.peekInt() should be(0x30001000L)\n c.memWriteData.peekInt() should be(0xffffffffL)\n c.clock.step(1) // sw\n c.clock.step(1) // add\n c.GPIO0_direction.peekInt() should be(0xffffffffL)\n c.registers(2).peekInt() should be(1)\n c.memWriteAddr.peekInt() should be(0x30001004L)\n c.memWriteData.peekInt() should be(1)\n c.clock.step(1) // sw\n c.GPIO0_value.peekInt() should be(1)\n c.clock.step(1) // jal\n c.clock.step(1) // add\n c.registers(2).peekInt() should be(2)\n c.memWriteAddr.peekInt() should be(0x30001004L)\n c.memWriteData.peekInt() should be(2)\n c.clock.step(1) // sw\n c.GPIO0_value.peekInt() should be(2)\n }\n }\n\n behavior of \"Timer\"\n it should \"read timer and wait for 2 ms\" in {\n val prog = \"\"\"\n main: lui x1, 0x30003\n addi x2, x0, 2\n wait: lw x3, 0(x1)\n bne x2, x3, -4\n cont: addi x4, x0, 1\n \"\"\"\n defaultDut(prog) { c =>\n c.clock.setTimeout(0)\n c.registers(1).peekInt() should be(0)\n c.registers(2).peekInt() should be(0)\n c.registers(3).peekInt() should be(0)\n c.timerCounter.peekInt() should be(0)\n c.clock.step(1) // lui\n c.registers(1).peekInt() should be(0x30003000L)\n c.clock.step(1) // addi\n c.registers(2).peekInt() should be(2)\n // Check read from memory address 0x30003000L\n c.memReadAddr.peekInt() should be(0x30003000L)\n c.memReadData.peekInt() should be(0)\n c.clock.step(1) // lw\n", "right_context": "\n it should \"reset timer after 1ms and wait for 1 ms\" in {\n val prog = \"\"\"\n main: lui x1, 0x30003\n addi x2, x0, 1\n wait: lw x3, 0(x1)\n bne x2, x3, -4\n cont: sw x0, 0(x1)\n wait2: lw x3, 0(x1)\n bne x2, x3, -4\n cont2: addi x3, x0, 2\n \"\"\"\n defaultDut(prog) { c =>\n c.clock.setTimeout(0)\n c.registers(1).peekInt() should be(0)\n c.registers(2).peekInt() should be(0)\n c.registers(3).peekInt() should be(0)\n c.timerCounter.peekInt() should be(0)\n c.clock.step(1) // lui\n c.registers(1).peekInt() should be(0x30003000L)\n c.clock.step(1) // addi\n c.registers(2).peekInt() should be(1)\n // Check read from memory address 0x30003000L\n c.memReadAddr.peekInt() should be(0x30003000L)\n c.memReadData.peekInt() should be(0)\n c.registers(3).peekInt() should be(0)\n c.clock.step(ms) // wait 1ms\n c.timerCounter.peekInt() should be(1)\n c.registers(3).peekInt() should be(1)\n c.clock.step(1)\n c.clock.step(1)\n c.clock.step(1) // sw\n // Check write to memory address 0x30003000L (reset)\n c.memWriteAddr.peekInt() should be(0x30003000L)\n c.memWriteData.peekInt() should be(0)\n c.timerCounter.peekInt() should be(0)\n c.registers(3).peekInt() should be(0)\n c.clock.step(ms) // wait 1ms\n c.timerCounter.peekInt() should be(1)\n c.clock.step(1) // lw\n c.clock.step(1) // bne\n c.clock.step(1) // addi\n c.registers(3).peekInt() should be(2)\n }\n }\n}\n", "groundtruth": " c.registers(3).peekInt() should be(0)\n c.clock.step(1) // bne\n c.clock.step(2 * ms) // wait 2ms\n c.timerCounter.peekInt() should be(2)\n c.registers(3).peekInt() should be(2)\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/test/src/CPUSingleCycleInstructionSpec.scala", "left_context": "package chiselv\n\nimport chiseltest._\nimport chiseltest.experimental._\nimport com.carlosedp.riscvassembler.RISCVAssembler\nimport org.scalatest._\n\nimport flatspec._\nimport matchers._\n\n// Extend the Control module to add the observer for sub-module signals\nclass CPUSingleCycleInstWrapper(memoryFile: String) extends SOC(\n cpuFrequency = 25000000,\n entryPoint = 0,\n bitWidth = 32,\n instructionMemorySize = 1 * 1024,\n dataMemorySize = 1 * 1024,\n memoryFile = memoryFile,\n numGPIO = 0,\n ) {\n val registers = expose(core.registerBank.regs)\n val pc = expose(core.PC.pc)\n val memWriteAddr = expose(core.memoryIOManager.io.MemoryIOPort.writeAddr)\n val memWriteData = expose(core.memoryIOManager.io.MemoryIOPort.writeData)\n val memReadAddr = expose(core.memoryIOManager.io.MemoryIOPort.readAddr)\n val memReadData = expose(core.memoryIOManager.io.MemoryIOPort.readData)\n}\n\nclass CPUSingleCycleInstructionSpec\n extends AnyFlatSpec\n with ChiselScalatestTester\n with BeforeAndAfterEach\n with BeforeAndAfterAll\n with should.Matchers {\n val memReadLatency = 1\n val memWriteLatency = 1\n var memoryfile: os.Path = _\n val tmpdir = os.pwd / \"tmphex\"\n\n override def beforeAll(): Unit =\n os.makeDir.all(tmpdir)\n override def afterAll(): Unit =\n scala.util.Try(os.remove(tmpdir))\n override def beforeEach(): Unit =\n memoryfile = tmpdir / (scala.util.Random.alphanumeric.filter(_.isLetter).take(15).mkString + \".hex\")\n override def afterEach(): Unit =\n os.remove.all(memoryfile)\n\n def defaultDut(prog: String) = {\n // Generate the hex file from asm source\n val hex = RISCVAssembler.fromString(prog)\n os.write(memoryfile, hex)\n test(new CPUSingleCycleInstWrapper(memoryfile.relativeTo(os.pwd).toString))\n .withAnnotations(\n Seq(\n WriteVcdAnnotation\n )\n )\n }\n\n it should \"validate ADD/ADDI instructions\" in {\n val prog = \"\"\"\n addi x1, x1, 1\n addi x2, x2, 1\n add x3, x1, x2\n \"\"\"\n defaultDut(prog) { c =>\n c.clock.setTimeout(0)\n c.registers(1).peekInt() should be(0)\n c.registers(2).peekInt() should be(0)\n c.registers(3).peekInt() should be(0)\n c.clock.step(1)\n c.registers(1).peekInt() should be(1)\n c.clock.step(1)\n c.registers(2).peekInt() should be(1)\n c.clock.step(1)\n c.registers(3).peekInt() should be(2)\n }\n }\n\n it should \"validate Branch instructions\" in {\n val prog = \"\"\"\n addi x1, x0, 4\n addi x2, x0, 4\n addi x3, x0, 2\n beq x1, x2, +8\n jal x0, 0\n bne x2, x3, +8\n jal x0, 0\n blt x3, x2, +8\n jal x0, 0\n bge x2, x3, +8\n jal x0, 0\n \"\"\"\n defaultDut(prog) { c =>\n c.clock.setTimeout(0)\n c.registers(1).peekInt() should be(0x0)\n c.registers(2).peekInt() should be(0x0)\n c.registers(3).peekInt() should be(0x0)\n c.clock.step(1)\n c.registers(1).peekInt() should be(4)\n c.clock.step(1)\n c.registers(2).peekInt() should be(4)\n c.clock.step(1)\n c.registers(3).peekInt() should be(2)\n c.pc.peekInt() should be(0x0c)\n c.clock.step(1)\n c.pc.peekInt() should be(0x14)\n c.clock.step(1)\n c.pc.peekInt() should be(0x1c)\n c.clock.step(1)\n c.pc.peekInt() should be(0x24)\n c.clock.step(1)\n c.pc.peekInt() should be(0x2c)\n }\n }\n\n it should \"validate JAL/JALR instructions\" in {\n val prog = \"\"\"\n", "right_context": " c.pc.peekInt() should be(8)\n c.registers(1).peekInt() should be(4)\n c.clock.step(1) // jalr\n c.pc.peekInt() should be(2048)\n c.registers(2).peekInt() should be(0xc)\n }\n }\n\n it should \"validate LUI instruction\" in {\n val prog = \"\"\"\n lui x2, 0xc0000\n \"\"\"\n defaultDut(prog) { c =>\n c.clock.setTimeout(0)\n c.registers(2).peekInt() should be(0x00000000L)\n c.clock.step(1)\n c.registers(2).peekInt() should be(0xc0000000L)\n }\n }\n\n it should \"validate AUIPC instruction\" in {\n val prog = \"\"\"\n auipc x2, 4096\n auipc x3, 4096\n \"\"\"\n defaultDut(prog) { c =>\n c.clock.setTimeout(0)\n c.registers(2).peekInt() should be(0x00000000L)\n c.clock.step(1)\n c.registers(2).peekInt() should be(0x01000000L)\n c.clock.step(1)\n c.registers(3).peekInt() should be(0x01000004L)\n }\n }\n\n it should \"validate SW instruction\" in {\n val prog = \"\"\"\n lui x1, 0x80000\n addi x1, x1, 20\n addi x2, x0, 291\n sw x2, 0(x1)\n lw x3, 0(x1)\n \"\"\"\n defaultDut(prog) { c =>\n c.registers(1).peekInt() should be(0)\n c.clock.step(1) // lui\n c.registers(1).peekInt() should be(0x80000000L)\n c.clock.step(1) // addi\n c.registers(1).peekInt() should be(0x80000014L)\n c.clock.step(1) // addi\n c.registers(2).peekInt() should be(0x123)\n // Check memory address 0x14 with offset\n c.memWriteAddr.peekInt() should be(0x80000000L + 0x14)\n c.memWriteData.peekInt() should be(0x123)\n c.clock.step(1 + memWriteLatency) // sw\n // Check memory address 0x14 with offset\n c.memReadAddr.peekInt() should be(0x80000000L + 0x14)\n c.memReadData.peekInt() should be(0x123)\n c.clock.step(2 + memReadLatency) // lw\n c.registers(3).peekInt() should be(0x123)\n }\n }\n\n it should \"validate SH instruction\" in {\n val prog = \"\"\"\n lui x1, 0x80000\n lui x2, 0x12345\n addi x2, x2, 1656\n addi x3, x3, -1\n sw x3, 48(x1) // Memory offset 48 (0x30) should be 0xffffffff\n sh x2, 52(x1) // Memory offset 52 (0x34) should be 0x00005678\n sh x2, 48(x1) // Memory offset 48 (0x30) should be 0xffff5678\n sh x2, 54(x1) // Memory offset 52 (0x34) should be 0x56785678\n lw x4, 48(x1) // x4 should be 0xffff5678\n lw x5, 52(x1) // x5 should be 0x56785678\n \"\"\"\n defaultDut(prog) { c =>\n c.registers(1).peekInt() should be(0)\n c.clock.step(1) // lui\n c.registers(1).peekInt() should be(0x80000000L)\n c.clock.step(1) // lui\n c.registers(2).peekInt() should be(0x12345000L)\n c.clock.step(1) // addi\n c.registers(2).peekInt() should be(0x12345678L)\n c.clock.step(1) // addi\n c.registers(3).peekInt() should be(0xffffffffL)\n // Check memory address offset 0x30\n c.memWriteAddr.peekInt() should be(0x80000000L + 0x30)\n c.memWriteData.peekInt() should be(0xffffffffL)\n c.clock.step(1 + memWriteLatency) // sw\n // Check memory address offset 0x34\n c.memWriteAddr.peekInt() should be(0x80000000L + 0x34)\n c.memWriteData.peekInt() should be(0x5678L)\n c.clock.step(1 + memWriteLatency) // sh\n // Check memory address 0x30\n c.memWriteAddr.peekInt() should be(0x80000000L + 0x30)\n c.memWriteData.peekInt() should be(0x5678L)\n c.clock.step(1 + memWriteLatency) // sh\n // Check memory address offset 0x34\n c.memWriteAddr.peekInt() should be(0x80000000L + 0x36)\n c.memWriteData.peekInt() should be(0x5678L)\n c.clock.step(1 + memWriteLatency) // sh\n // Check memory address 0x30\n c.clock.step(1) // lw - stall\n c.memReadAddr.peekInt() should be(0x80000000L + 0x30)\n c.memReadData.peekInt() should be(0xffff5678L)\n c.clock.step(1) // lw\n c.clock.step(1) // lw - stall\n c.registers(4).peekInt() should be(0xffff5678L)\n // Check memory address 0x34\n c.memReadAddr.peekInt() should be(0x80000000L + 0x34)\n c.memReadData.peekInt() should be(0x56785678L)\n c.clock.step(1) // lw\n c.registers(5).peekInt() should be(0x56785678L)\n c.clock.step(10) // padding\n }\n }\n\n it should \"validate SB instruction\" in {\n val prog = \"\"\"\n lui x1, 0x80000\n lui x2, 0x12345\n addi x2, x2, 1656\n addi x3, x3, -1\n sw x3, 48(x1) // Memory offset 48 (0x30) should be 0xffffffff\n sb x2, 52(x1) // Memory offset 52 (0x34) should be 0x00000078\n sb x2, 48(x1) // Memory offset 48 (0x30) should be 0xffffff78\n sb x2, 54(x1) // Memory offset 52 (0x34) should be 0x00780078\n sb x2, 51(x1) // Memory offset 51 (0x33) should be 0x78ffff78\n lw x4, 48(x1) // x4 should be 0x78ffff78\n lw x5, 52(x1) // x5 should be 0x00780078\n \"\"\"\n defaultDut(prog) { c =>\n c.registers(1).peekInt() should be(0)\n c.clock.step(1) // lui\n c.registers(1).peekInt() should be(0x80000000L)\n c.clock.step(1) // lui\n c.registers(2).peekInt() should be(0x12345000L)\n c.clock.step(1) // addi\n c.registers(2).peekInt() should be(0x12345678L)\n c.clock.step(1) // addi\n c.registers(3).peekInt() should be(0xffffffffL)\n // Check memory address offset 0x30\n c.memWriteAddr.peekInt() should be(0x80000000L + 0x30)\n c.memWriteData.peekInt() should be(0xffffffffL)\n c.clock.step(1 + memWriteLatency) // sw\n // Check memory address offset 0x34\n c.memWriteAddr.peekInt() should be(0x80000000L + 0x34)\n c.memWriteData.peekInt() should be(0x78L)\n c.clock.step(1 + memWriteLatency) // sb\n // Check memory address 0x30\n c.memWriteAddr.peekInt() should be(0x80000000L + 0x30)\n c.memWriteData.peekInt() should be(0x78L)\n c.clock.step(1 + memWriteLatency) // sb\n // Check memory address offset 0x34\n c.memWriteAddr.peekInt() should be(0x80000000L + 0x36)\n c.memWriteData.peekInt() should be(0x78L)\n c.clock.step(1 + memWriteLatency) // sb\n // Check memory address offset 0x33\n c.memWriteAddr.peekInt() should be(0x80000000L + 0x33)\n c.memWriteData.peekInt() should be(0x78L)\n c.clock.step(1 + memWriteLatency) // sb\n // Check memory address 0x30\n c.memReadAddr.peekInt() should be(0x80000000L + 0x30)\n c.clock.step(1) // lw\n c.memReadData.peekInt() should be(0x78ffff78L)\n c.clock.step(1) // lw\n c.registers(4).peekInt() should be(0x78ffff78L)\n // Check memory address 0x34\n c.memReadAddr.peekInt() should be(0x80000000L + 0x34)\n c.clock.step(1) // lw\n c.memReadData.peekInt() should be(0x00780078L)\n c.clock.step(1) // lw\n c.registers(5).peekInt() should be(0x00780078L)\n c.clock.step(10) // padding\n }\n }\n\n it should \"validate LW instruction\" in {\n val prog = \"\"\"\n lui x1, 0xf0f0f\n addi x1, x1, 240\n lui x2, 0x80000\n sw x1, 0(x2)\n lw x3, 0(x2)\n \"\"\"\n defaultDut(prog) { c =>\n c.registers(1).peekInt() should be(0)\n c.clock.step(1) // lui\n c.registers(1).peekInt() should be(0xf0f0f000L)\n c.clock.step(1) // addi\n c.registers(1).peekInt() should be(0xf0f0f0f0L)\n c.clock.step(1) // lui\n c.registers(2).peekInt() should be(0x80000000L)\n // Check memory write at address 0x80000000L\n c.memWriteAddr.peekInt() should be(0x80000000L)\n c.memWriteData.peekInt() should be(0xf0f0f0f0L)\n c.clock.step(1 + memWriteLatency) // sw\n // Check memory read at address 0x20 (32)\n c.memReadAddr.peekInt() should be(0x80000000L)\n c.memReadData.peekInt() should be(0xf0f0f0f0L)\n c.clock.step(1 + memReadLatency) // lw\n // Check loaded data\n c.registers(3).peekInt() should be(0xf0f0f0f0L)\n c.clock.step(5) // Paddding\n }\n }\n\n it should \"validate LH instruction\" in {\n val prog = \"\"\"\n lui x1, 0xffff1\n addi x1, x1, 564\n lui x2, 0x80000\n sw x1, 0(x2)\n lh x3, 0(x2)\n lh x4, 2(x2)\n \"\"\"\n defaultDut(prog) { c =>\n c.registers(1).peekInt() should be(0)\n c.clock.step(1)\n c.registers(1).peekInt() should be(0xffff1000L)\n c.clock.step(1)\n c.registers(1).peekInt() should be(0xffff1234L)\n c.clock.step(1)\n c.registers(2).peekInt() should be(0x80000000L)\n // Check memory write at address 0x80000000L\n c.memWriteAddr.peekInt() should be(0x80000000L)\n c.memWriteData.peekInt() should be(0xffff1234L)\n c.clock.step(1 + memWriteLatency) // sw\n // Check memory read at address 0x80000000L\n c.memReadAddr.peekInt() should be(0x80000000L)\n c.memReadData.peekInt() should be(0x00001234L)\n c.clock.step(1 + memReadLatency) // lh\n // Check loaded data\n c.registers(3).peekInt() should be(0x00001234L)\n // Check memory read at address 0x80000002L\n c.memReadAddr.peekInt() should be(0x80000000L + 0x2)\n c.memReadData.peekInt() should be(0x0000ffffL)\n c.clock.step(1 + memReadLatency) // lh\n c.registers(4).peekInt() should be(0xffffffffL)\n c.clock.step(5) // Paddding\n }\n }\n\n it should \"validate LHU instruction\" in {\n val prog = \"\"\"\n lui x1, 0xffff1\n addi x1, x1, 564\n lui x2, 0x80000\n sw x1, 0(x2)\n lhu x3, 0(x2)\n lhu x4, 2(x2)\n \"\"\"\n defaultDut(prog) { c =>\n c.registers(1).peekInt() should be(0)\n c.clock.step(1)\n c.registers(1).peekInt() should be(0xffff1000L)\n c.clock.step(1)\n c.registers(1).peekInt() should be(0xffff1234L)\n c.clock.step(1)\n c.registers(2).peekInt() should be(0x80000000L)\n // Check memory write at address 0x80000000L\n c.memWriteAddr.peekInt() should be(0x80000000L)\n c.memWriteData.peekInt() should be(0xffff1234L)\n c.clock.step(1 + memWriteLatency) // sw\n // Check memory read at address 0x80000000L\n c.memReadAddr.peekInt() should be(0x80000000L)\n c.memReadData.peekInt() should be(0x00001234L)\n c.clock.step(1 + memReadLatency) // lh\n // Check loaded data\n c.registers(3).peekInt() should be(0x00001234L)\n // Check memory read at address 0x80000002L\n c.memReadAddr.peekInt() should be(0x80000000L + 0x2)\n c.memReadData.peekInt() should be(0x0000ffffL)\n c.clock.step(1 + memReadLatency) // lh\n c.registers(4).peekInt() should be(0x0000ffffL)\n c.clock.step(5) // Paddding\n }\n }\n\n it should \"validate LB instruction\" in {\n val prog = \"\"\"\n lui x1, 0xabcde\n addi x1, x1, 0x123\n lui x2, 0x80000\n sw x1, 0(x2)\n lb x3, 0(x2)\n lb x4, 1(x2)\n lb x5, 2(x2)\n lb x6, 3(x2)\n \"\"\"\n defaultDut(prog) { c =>\n c.registers(1).peekInt() should be(0)\n c.clock.step(1)\n c.registers(1).peekInt() should be(0xabcde000L)\n c.clock.step(1)\n c.registers(1).peekInt() should be(0xabcde123L)\n c.clock.step(1)\n c.registers(2).peekInt() should be(0x80000000L)\n // Check memory write at address 0x80000000L\n c.memWriteAddr.peekInt() should be(0x80000000L)\n c.memWriteData.peekInt() should be(0xabcde123L)\n c.clock.step(1 + memWriteLatency) // sw\n // Check memory read at address 0x80000000L\n c.memReadAddr.peekInt() should be(0x80000000L)\n c.memReadData.peekInt() should be(0x23L)\n c.clock.step(1 + memReadLatency) // lb (offset 0)\n c.registers(3).peekInt() should be(0x00000023L)\n // Check memory read at address 0x80000001L\n c.memReadAddr.peekInt() should be(0x80000001L)\n c.memReadData.peekInt() should be(0xe1L)\n c.clock.step(1 + memReadLatency) // lb (offset 1)\n c.registers(4).peekInt() should be(0xffffffe1L)\n // Check memory read at address 0x80000002L\n c.memReadAddr.peekInt() should be(0x80000002L)\n c.memReadData.peekInt() should be(0xcdL)\n c.clock.step(1 + memReadLatency) // lb (offset 2)\n c.registers(5).peekInt() should be(0xffffffcdL)\n // Check memory read at address 0x80000003L\n c.memReadAddr.peekInt() should be(0x80000003L)\n c.memReadData.peekInt() should be(0xabL)\n c.clock.step(1 + memReadLatency) // lb (offset 3)\n c.registers(6).peekInt() should be(0xffffffabL)\n // Check loaded data\n c.clock.step(5) // Paddding\n }\n }\n\n it should \"validate LBU instruction\" in {\n val prog = \"\"\"\n lui x1, 0xabcde\n addi x1, x1, 0x123\n lui x2, 0x80000\n sw x1, 0(x2)\n lbu x3, 0(x2)\n lbu x4, 1(x2)\n lbu x5, 2(x2)\n lbu x6, 3(x2)\n \"\"\"\n defaultDut(prog) { c =>\n c.registers(1).peekInt() should be(0)\n c.clock.step(1)\n c.registers(1).peekInt() should be(0xabcde000L)\n c.clock.step(1)\n c.registers(1).peekInt() should be(0xabcde123L)\n c.clock.step(1)\n c.registers(2).peekInt() should be(0x80000000L)\n // Check memory write at address 0x80000000L\n c.memWriteAddr.peekInt() should be(0x80000000L)\n c.memWriteData.peekInt() should be(0xabcde123L)\n c.clock.step(1 + memWriteLatency) // sw\n // Check memory read at address 0x80000000L\n c.memReadAddr.peekInt() should be(0x80000000L)\n c.memReadData.peekInt() should be(0x23L)\n c.clock.step(1 + memReadLatency) // lb (offset 0)\n c.registers(3).peekInt() should be(0x00000023L)\n // Check memory read at address 0x80000001L\n c.memReadAddr.peekInt() should be(0x80000001L)\n c.memReadData.peekInt() should be(0xe1L)\n c.clock.step(1 + memReadLatency) // lb (offset 1)\n c.registers(4).peekInt() should be(0x000000e1L)\n // Check memory read at address 0x80000002L\n c.memReadAddr.peekInt() should be(0x80000002L)\n c.memReadData.peekInt() should be(0xcdL)\n c.clock.step(1 + memReadLatency) // lb (offset 2)\n c.registers(5).peekInt() should be(0x000000cdL)\n // Check memory read at address 0x80000003L\n c.memReadAddr.peekInt() should be(0x80000003L)\n c.memReadData.peekInt() should be(0xabL)\n c.clock.step(1 + memReadLatency) // lb (offset 3)\n c.registers(6).peekInt() should be(0x000000abL)\n // Check loaded data\n c.clock.step(5) // Paddding\n }\n }\n}\n", "groundtruth": " jal x1, +8\n nop\n jalr x2, x1, +2044\n \"\"\"\n defaultDut(prog) { c =>\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/test/src/DecoderSpec.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chiseltest._\nimport com.carlosedp.riscvassembler.RISCVAssembler\nimport org.scalatest._\n\nimport Instruction._\nimport flatspec._\nimport matchers._\n\nclass DecoderSpec extends AnyFlatSpec with ChiselScalatestTester with should.Matchers {\n behavior of \"Decoder - Aritmetic\"\n\n it should \"Decode an ADD instruction (type R)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"add x1, x2, x3\"))\n c.clock.step()\n validateResult(c, ADD, 1, 2, 3, 0, true, false)\n }\n }\n it should \"Decode an ADDI instruction (type I)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"addi x1, x2, 5\"))\n c.clock.step()\n validateResult(c, ADDI, 1, 2, 0, 5, true, false, true)\n }\n }\n it should \"Decode an SUB instruction (type R)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"sub x1, x2, x3\"))\n c.clock.step()\n validateResult(c, SUB, 1, 2, 3, 0, true, false)\n }\n }\n it should \"Decode an LUI instruction (type U)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"lui x23, 0x12345\"))\n c.clock.step()\n validateResult(c, LUI, 23, 0, 0, 305418240, false, false, true)\n }\n }\n it should \"Decode an AUIPC instruction (type U)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"auipc x23, 0x12345\"))\n c.clock.step()\n validateResult(c, AUIPC, 23, 0, 0, 305418240, false, false, true)\n }\n }\n\n behavior of \"Decoder - Shifts\"\n\n it should \"Decode an SLL instruction (type R)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"sll x1, x2, x3\"))\n c.clock.step()\n validateResult(c, SLL, 1, 2, 3, 0, true, false)\n }\n }\n it should \"Decode an SLLI instruction (type I)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"slli x1, x2, 5\"))\n c.clock.step()\n validateResult(c, SLLI, 1, 2, 0, 5, true, false, true)\n }\n }\n it should \"Decode an SRL instruction (type R)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"srl x1, x2, x3\"))\n c.clock.step()\n validateResult(c, SRL, 1, 2, 3, 0, true, false)\n }\n }\n it should \"Decode an SRLI instruction (type I)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"srli x1, x2, 5\"))\n c.clock.step()\n validateResult(c, SRLI, 1, 2, 0, 5, true, false, true)\n }\n }\n it should \"Decode an SRA instruction (type R)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"sra x1, x2, x3\"))\n c.clock.step()\n validateResult(c, SRA, 1, 2, 3, 0, true, false)\n }\n }\n it should \"Decode an SRAI instruction (type I)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"srai x1, x2, 1\"))\n c.clock.step()\n validateResult(c, SRAI, 1, 2, 0, 1025, true, false, true)\n }\n }\n\n behavior of \"Decoder - Logical\"\n\n it should \"Decode an AND instruction (type R)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"and x1, x2, x3\"))\n c.clock.step()\n validateResult(c, AND, 1, 2, 3, 0, true, false)\n }\n }\n it should \"Decode an ANDI instruction (type I)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"andi x7, x24, -1\"))\n c.clock.step()\n validateResult(c, ANDI, 7, 24, 0, -1, true, false, true)\n }\n }\n it should \"Decode an OR instruction (type R)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"or x1, x2, x3\"))\n c.clock.step()\n validateResult(c, OR, 1, 2, 3, 0, true, false)\n }\n }\n it should \"Decode an ORI instruction (type I)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"ori x7, x24, -1\"))\n c.clock.step()\n validateResult(c, ORI, 7, 24, 0, -1, true, false, true)\n }\n }\n it should \"Decode an XOR instruction (type R)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"xor x1, x2, x3\"))\n c.clock.step()\n validateResult(c, XOR, 1, 2, 3, 0, true, false)\n }\n }\n it should \"Decode an XORI instruction (type I)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"xori x7, x24, -1\"))\n c.clock.step()\n validateResult(c, XORI, 7, 24, 0, -1, true, false, true)\n }\n }\n\n behavior of \"Decoder - Compare\"\n\n it should \"Decode an SLT instruction (type R)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"slt x1, x2, x3\"))\n c.clock.step()\n validateResult(c, SLT, 1, 2, 3, 0, true, false)\n }\n }\n it should \"Decode an SLTI instruction (type I)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"slti x7, x24, -1\"))\n c.clock.step()\n validateResult(c, SLTI, 7, 24, 0, -1, true, false, true)\n }\n }\n it should \"Decode an SLTU instruction (type R)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"sltu x1, x2, x3\"))\n c.clock.step()\n validateResult(c, SLTU, 1, 2, 3, 0, true, false)\n }\n }\n it should \"Decode an SLTIU instruction (type I)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"sltiu x7, x24, -1\"))\n c.clock.step()\n validateResult(c, SLTIU, 7, 24, 0, -1, true, false, true)\n }\n }\n\n behavior of \"Decoder - Branches\"\n\n it should \"Decode an BEQ instruction (type B)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"beq x21, x10, -1366\"))\n c.clock.step()\n validateResult(c, BEQ, 0, 21, 10, -1366, false, true, true)\n }\n }\n it should \"Decode an BNE instruction (type B)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"bne x21, x10, -1366\"))\n c.clock.step()\n validateResult(c, BNE, 0, 21, 10, -1366, false, true, true)\n }\n }\n it should \"Decode an BLT instruction (type B)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"blt x21, x10, -1366\"))\n c.clock.step()\n validateResult(c, BLT, 0, 21, 10, -1366, false, true, true)\n }\n }\n it should \"Decode an BGE instruction (type B)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"bge x21, x10, -1366\"))\n c.clock.step()\n validateResult(c, BGE, 0, 21, 10, -1366, false, true, true)\n }\n }\n it should \"Decode an BLTU instruction (type B)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"bltu x21, x10, -1366\"))\n c.clock.step()\n validateResult(c, BLTU, 0, 21, 10, -1366, false, true, true)\n }\n }\n it should \"Decode an BGEU instruction (type B)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"bgeu x21, x10, -1366\"))\n c.clock.step()\n validateResult(c, BGEU, 0, 21, 10, -1366, false, true, true)\n }\n }\n\n behavior of \"Decoder - Jumps\"\n\n it should \"Decode an JAL instruction (type J)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"jal x21, -699052\"))\n c.clock.step()\n validateResult(c, JAL, 21, 0, 0, -699052, false, false, true, true)\n }\n }\n it should \"Decode an JALR instruction (type I)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"jalr x21, x1, 1234\"))\n c.clock.step()\n validateResult(c, JALR, 21, 1, 0, 1234, false, false, true, true)\n }\n }\n\n behavior of \"Decoder - Loads/Stores\"\n\n it should \"Decode an LB instruction (type I)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"lb x1, 16(x2)\"))\n c.clock.step()\n validateResult(c, LB, 1, 2, 0, 16, false, false, true, false, true, false)\n }\n }\n it should \"Decode an LH instruction (type I)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"lh x1, 16(x2)\"))\n c.clock.step()\n validateResult(c, LH, 1, 2, 0, 16, false, false, true, false, true, false)\n }\n }\n it should \"Decode an LBU instruction (type I)\" in {\n", "right_context": " }\n it should \"Decode an LHU instruction (type I)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"lhu x1, 16(x2)\"))\n c.clock.step()\n validateResult(c, LHU, 1, 2, 0, 16, false, false, true, false, true, false)\n }\n }\n it should \"Decode an LW instruction (type I)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"lw x1, 16(x2)\"))\n c.clock.step()\n validateResult(c, LW, 1, 2, 0, 16, false, false, true, false, true, false)\n }\n }\n it should \"Decode an SB instruction (type S)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"sb x10, -81(x21)\"))\n c.clock.step()\n validateResult(c, SB, 0, 21, 10, -81, false, false, true, false, false, true)\n }\n }\n it should \"Decode an SH instruction (type S)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"sh x10, -81(x21)\"))\n c.clock.step()\n validateResult(c, SH, 0, 21, 10, -81, false, false, true, false, false, true)\n }\n }\n it should \"Decode an SW instruction (type S)\" in {\n test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"sw x10, -81(x21)\"))\n c.clock.step()\n validateResult(c, SW, 0, 21, 10, -81, false, false, true, false, false, true)\n }\n }\n\n // --------------------- Test Helpers ---------------------\n\n def makeBin(\n in: String\n ): UInt = {\n val bin = RISCVAssembler.binOutput(in)\n (\"b\" + bin).U\n }\n\n def validateResult(\n c: Decoder,\n inst: Instruction.Type,\n rd: Int,\n rs1: Int,\n rs2: Int,\n imm: Int,\n toALU: Boolean = false,\n branch: Boolean = false,\n use_imm: Boolean = false,\n jump: Boolean = false,\n load: Boolean = false,\n store: Boolean = false,\n ) = {\n c.io.inst.expect(inst)\n c.io.rd.peekInt() should be(rd)\n c.io.rs1.peekInt() should be(rs1)\n c.io.rs2.peekInt() should be(rs2)\n c.io.imm.peekInt() should be(imm)\n c.io.toALU.peekBoolean() should be(toALU)\n c.io.branch.peekBoolean() should be(branch)\n c.io.use_imm.peekBoolean() should be(use_imm)\n c.io.jump.peekBoolean() should be(jump)\n c.io.is_load.peekBoolean() should be(load)\n c.io.is_store.peekBoolean() should be(store)\n }\n}\n", "groundtruth": " test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"lbu x1, 16(x2)\"))\n c.clock.step()\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/test/src/GPIOSpec.scala", "left_context": "package chiselv\n\nimport chiseltest._\nimport chiseltest.experimental.expose\nimport com.carlosedp.riscvassembler.ObjectUtils._\nimport org.scalatest._\n\nimport flatspec._\nimport matchers._\n\nclass GPIOWrapper(bitWidth: Int = 32, numGPIO: Int = 8) extends GPIO(bitWidth, numGPIO) {\n val obs_GPIO = expose(GPIO)\n val obs_DIRECTION = expose(direction)\n}\nclass GPIOSpec extends AnyFlatSpec with ChiselScalatestTester with should.Matchers {\n def defaultDut =\n test(new GPIOWrapper(32, 8)).withAnnotations(\n Seq(\n WriteVcdAnnotation,\n VerilatorBackendAnnotation,\n )\n", "right_context": " c.obs_GPIO.peekInt() should be(0)\n c.obs_DIRECTION.peekInt() should be(0)\n }\n }\n\n it should \"write direction then read\" in {\n defaultDut { c =>\n c.io.GPIOPort.writeDirection.poke(true)\n c.io.GPIOPort.dataIn.poke(\"10101010\".b)\n c.clock.step()\n c.obs_DIRECTION.peekInt() should be(\"10101010\".b)\n c.io.GPIOPort.directionOut.peekInt() should be(\"10101010\".b)\n }\n }\n\n it should \"write IO data then read\" in {\n defaultDut { c =>\n c.io.GPIOPort.writeValue.poke(true)\n c.io.GPIOPort.dataIn.poke(\"11111111\".b)\n c.clock.step()\n c.obs_GPIO.peekInt() should be(\"11111111\".b)\n c.io.GPIOPort.writeDirection.poke(true)\n c.io.GPIOPort.dataIn.poke(\"01010101\".b)\n c.clock.step()\n c.io.GPIOPort.valueOut.peekInt() should be(\"01010101\".b)\n c.clock.step(5)\n }\n }\n\n // Doesn't work since we can't poke the analog port\n //\n // it should \"read IO data from input\" in {\n // defaultDut(){ c =>\n // c.io.GPIOPort.dataOut.peekInt() should be(0)\n // c.io.GPIOPort.dir.poke(0.U) // Read input\n // // c.InOut.io.dataIO.poke(1.U) // Write to input pin\n // c.clock.step()\n // c.io.GPIOPort.dataOut.peekInt() should be(1)\n // }\n // }\n\n}\n", "groundtruth": " )\n\n it should \"read GPIO output and direction as 0 when initialized\" in {\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/test/src/MemorySpec.scala", "left_context": "package chiselv\n\nimport chiseltest._\nimport org.scalatest._\n\nimport flatspec._\nimport matchers._\n\nclass MemorySpec extends AnyFlatSpec with ChiselScalatestTester with should.Matchers {\n\n it should \"write and read from address\" in {\n test(new DualPortRAM(32, 1 * 1024)).withAnnotations(\n Seq(\n WriteVcdAnnotation\n )\n ) { c =>\n c.io.writeEnable.poke(true)\n c.io.writeAddress.poke(1)\n c.io.writeData.poke(1234)\n c.clock.step(1)\n c.io.readAddress.poke(1)\n c.clock.step(2)\n c.io.readData.peekInt() should be(1234)\n }\n }\n it should \"not allow write to address\" in {\n test(new DualPortRAM(32, 1 * 1024)) { c =>\n c.io.writeAddress.poke(0x00000010)\n c.io.readAddress.poke(0x00000010)\n c.clock.step()\n c.io.writeData.poke(1234)\n c.clock.step()\n c.io.readData.peekInt() should be(0)\n }\n }\n\n it should \"write data and follow with a read in same address\" in {\n test(new DualPortRAM(32, 64 * 1024)) { c =>\n val addressOffset = 0x0000100L\n val addresses = Seq(0x0L, 0x0010L, 0x0d00L, 0x1000L, 0x2000L, 0x8000L, 0xe000L)\n val values = Seq(0, 1, 0x0000_cafeL, 0xbaad_cafeL, 0xffff_ffffL)\n", "right_context": " c.io.readData.peekInt() should be(value)\n }\n }\n c.clock.step(10)\n }\n }\n\n behavior of \"InstructionMemory\"\n it should \"load from file and read multiple instructions\" in {\n val filename = \"MemorySpecTestFile.hex\"\n // Create memory test file with 32bit address space\n val file = os.pwd / \"MemorySpecTestFile.hex\"\n os.remove(file)\n os.write(file, \"00010203\\r\\n08090A0B\\r\\nDEADBEEF\\r\\n07060504\\r\\n\")\n test(new InstructionMemory(32, 16 * 1024, filename)).withAnnotations(Seq(WriteVcdAnnotation)) { c =>\n c.io.readAddr.poke(0)\n c.clock.step()\n c.io.readData.peekInt() should be(0x00010203L)\n c.io.readAddr.poke(4)\n c.clock.step()\n c.io.readData.peekInt() should be(0x08090a0bL)\n c.io.readAddr.poke(8)\n c.clock.step()\n c.io.readData.peekInt() should be(0xdeadbeefL)\n c.io.readAddr.poke(12)\n c.clock.step()\n c.clock.step()\n c.io.readData.peekInt() should be(0x07060504L)\n c.io.readAddr.poke(1)\n c.clock.step()\n }\n os.remove.all(file)\n }\n}\n", "groundtruth": " addresses.foreach { address =>\n values.foreach { value =>\n c.io.writeEnable.poke(true)\n c.io.writeAddress.poke(addressOffset + address)\n c.io.readAddress.poke(addressOffset + address)\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/test/src/ProgramCounterSpec.scala", "left_context": "package chiselv\n\nimport chiseltest._\nimport org.scalatest._\n\nimport flatspec._\nimport matchers._\n\nclass ProgramCounterSpec extends AnyFlatSpec with ChiselScalatestTester with should.Matchers {\n\n it should \"initialize to 0\" in {\n test(new ProgramCounter) { c =>\n c.io.PC.peekInt() should be(0)\n }\n }\n it should \"initialize to 0x00400000\" in {\n test(new ProgramCounter(entryPoint = 0x00400000)) { c =>\n c.io.PC.peekInt() should be(0x00400000L)\n }\n }\n it should \"walk 4 bytes\" in {\n test(new ProgramCounter) { c =>\n c.io.PC.peekInt() should be(0)\n c.io.PC4.peekInt() should be(4)\n", "right_context": " c.io.writeEnable.poke(true)\n c.io.dataIn.poke(c.io.PC4.peek())\n<TARGET>\n c.io.PC.peekInt() should be(4)\n }\n }\n it should \"jump to 0xbaddcafe (write)\" in {\n test(new ProgramCounter) { c =>\n c.io.writeEnable.poke(true)\n c.io.dataIn.poke(0xbaddcafeL)\n c.clock.step()\n c.io.PC.peekInt() should be(0xbaddcafeL)\n }\n }\n it should \"add 32 to PC ending up in 40\" in {\n test(new ProgramCounter) { c =>\n c.io.writeEnable.poke(true)\n c.io.dataIn.poke(8)\n c.clock.step()\n c.io.PC.peekInt() should be(8)\n c.io.writeAdd.poke(true)\n c.io.dataIn.poke(32)\n c.clock.step()\n c.io.PC.peekInt() should be(40)\n }\n }\n}\n", "groundtruth": " c.clock.step()\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/test/src/RegisterBankSpec.scala", "left_context": "package chiselv\n\nimport scala.util.Random\nimport chisel3._\nimport chiseltest._\nimport org.scalatest._\n\nimport flatspec._\nimport matchers._\n\nclass RegisterBankSpec extends AnyFlatSpec with ChiselScalatestTester with should.Matchers {\n\n it should \"have x0 equal to 0\" in {\n", "right_context": " c.io.writeEnable.poke(true)\n c.io.regwr_addr.poke(0.U)\n c.io.regwr_data.poke(123.U)\n c.clock.step()\n c.io.rs1_addr.peekInt() should be(0)\n }\n }\n it should \"not write if not enabled\" in {\n test(new RegisterBank) { c =>\n c.io.rs1_addr.poke(1)\n c.io.regwr_addr.poke(1)\n c.io.regwr_data.poke(123.U)\n c.clock.step()\n c.io.rs1.expect(0.U)\n }\n }\n it should \"write all other registers and read values as expected\" in {\n test(new RegisterBank).withAnnotations(Seq(WriteVcdAnnotation)) { c =>\n val one = BigInt(1)\n val max = (one << 32) - one\n val cases = Array[BigInt](1, 2, 4, 123, 0, 0x7fffffffL, max) ++ Seq.fill(10)(\n BigInt(Random.nextLong(max.toLong))\n )\n Random.shuffle(1 to 31).foreach { i =>\n cases.foreach { v =>\n c.io.writeEnable.poke(true)\n c.clock.step()\n c.io.regwr_addr.poke(i)\n c.io.regwr_data.poke(v.U)\n c.io.rs2_addr.poke(i)\n c.clock.step()\n c.io.writeEnable.poke(false)\n c.clock.step()\n c.io.rs2.expect(v)\n }\n }\n c.clock.step(10)\n }\n }\n}\n", "groundtruth": " test(new RegisterBank) { c =>\n c.io.rs1_addr.poke(0.U)\n c.io.rs1.expect(0.U)\n }\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/test/src/SysconSpec.scala", "left_context": "package chiselv\n\nimport chiseltest._\nimport org.scalatest._\n\nimport flatspec._\nimport matchers._\n\nclass SysconSpec extends AnyFlatSpec with ChiselScalatestTester with should.Matchers {\n\n def defaultDut =\n test(new Syscon(32, 50000000, 8, 0L, 64 * 1024, 64 * 1024)).withAnnotations(\n Seq(\n WriteVcdAnnotation\n )\n )\n\n it should \"read dummy value from Syscon 0x0\" in {\n defaultDut { c =>\n c.io.Address.poke(0x00)\n c.clock.step()\n c.io.DataOut.peekInt() should be(0xbaad_cafeL)\n }\n }\n it should \"read clock speed from Syscon\" in {\n defaultDut { c =>\n c.io.Address.poke(0x08)\n c.clock.step()\n c.io.DataOut.peekInt() should be(50000000)\n }\n }\n it should \"check if UART0 is available in Syscon\" in {\n defaultDut { c =>\n c.io.Address.poke(0x10)\n<TARGET>\n it should \"check if GPIO0 is available in Syscon\" in {\n defaultDut { c =>\n c.io.Address.poke(0x18)\n", "right_context": " it should \"check num of GPIO0s in Syscon\" in {\n defaultDut { c =>\n c.io.Address.poke(0x28)\n c.clock.step()\n c.io.DataOut.peekInt() should be(8)\n }\n }\n it should \"check if Timer0 is available in Syscon\" in {\n defaultDut { c =>\n c.io.Address.poke(0x24)\n c.clock.step()\n c.io.DataOut.peekInt() should be(1)\n }\n }\n it should \"check RAM size in Syscon\" in {\n defaultDut { c =>\n c.io.Address.poke(0x34)\n c.clock.step()\n c.io.DataOut.peekInt() should be(64 * 1024)\n }\n }\n}\n", "groundtruth": " c.clock.step()\n c.io.DataOut.peekInt() should be(1)\n }\n }\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/test/src/TimerSpec.scala", "left_context": "package chiselv\n\nimport chiseltest._\nimport chiseltest.experimental._\nimport org.scalatest._\nimport chiselv.Timer\n\nimport flatspec._\nimport matchers._\n\nclass TimerWrapper(bitWidth: Int = 32, cpuFrequency: Int) extends Timer(bitWidth, cpuFrequency) {\n val obs_counter = expose(counter)\n}\nclass TimerSpec extends AnyFlatSpec with ChiselScalatestTester with should.Matchers {\n\n val cpuFrequency = 25000000\n def defaultDut =\n test(new TimerWrapper(32, cpuFrequency)).withAnnotations(\n Seq(\n // WriteVcdAnnotation\n )\n )\n\n val ms = cpuFrequency / 1000\n it should \"read timer after 1ms\" in {\n defaultDut { c =>\n c.clock.setTimeout(0)\n", "right_context": " it should \"reset timer after 3ms and continue counting\" in {\n defaultDut { c =>\n c.clock.setTimeout(0)\n c.clock.step(3 * ms)\n c.obs_counter.peekInt() should be(3)\n c.io.dataOut.peekInt() should be(3)\n c.io.writeEnable.poke(true)\n c.io.dataIn.poke(0)\n c.clock.step()\n c.io.writeEnable.poke(false)\n c.obs_counter.peekInt() should be(0)\n c.obs_counter.peekInt() should be(0)\n c.clock.step(ms)\n c.io.dataOut.peekInt() should be(1)\n c.obs_counter.peekInt() should be(1)\n }\n }\n}\n", "groundtruth": " c.io.dataOut.peekInt() should be(0)\n c.obs_counter.peekInt() should be(0)\n c.clock.step(ms)\n c.io.dataOut.peekInt() should be(1)\n", "crossfile_context": ""}
	{"task_id": "chiselv", "path": "chiselv/chiselv/test/src/UartSpec.scala", "left_context": "package chiselv\n\nimport chisel3._\nimport chiseltest._\nimport org.scalatest._\n\nimport flatspec._\nimport matchers._\n\n/\n This file has been provided by Anton Blanchard's Chiselwatt repository at:\n * https://github.com/antonblanchard/chiselwatt\n /\n\nclass UartSpec extends AnyFlatSpec with ChiselScalatestTester with should.Matchers {\n val rxOverclock = 16\n val fpgaClock = 15000000\n val baudRate = 115200\n val divider = Math.round(1.0f fpgaClock / (baudRate * rxOverclock) - 1)\n\n", "right_context": "\n private def rxOne(u: Uart, c: UInt) = {\n /* Start bit /\n u.io.serialPort.rx.poke(0.U)\n clockSerial(u.clock)\n\n /\n * This doesn't work:\n * c.pad(8).asBools.foreach({cc =>\n /\n c.asBools.foreach { cc =>\n u.io.serialPort.rx.poke(cc)\n clockSerial(u.clock)\n }\n\n / Have to do this instead: /\n u.io.serialPort.rx.poke(0.U)\n clockSerial(u.clock)\n\n / Stop bit */\n u.io.serialPort.rx.poke(1.U)\n clockSerial(u.clock)\n }\n\n it should \"pass a unit test\" in {\n test(new Uart(64, rxOverclock)).withAnnotations(Seq(WriteVcdAnnotation)) { u =>\n u.clock.setTimeout(10000)\n\n u.io.dataPort.clockDivisor.valid.poke(true.B)\n u.io.dataPort.clockDivisor.bits.poke(divider.U)\n\n u.io.dataPort.rxQueue.ready.poke(false.B)\n\n val testChars = Seq(\"h41\".U, \"h6E\".U, \"h74\".U, \"h6F\".U, \"h6E\".U)\n\n testChars.foreach(c => rxOne(u, c))\n\n u.io.dataPort.rxQueue.ready.poke(true.B)\n testChars.foreach { c =>\n u.io.dataPort.rxQueue.valid.expect(true.B)\n u.io.dataPort.rxQueue.bits.expect(c)\n u.clock.step()\n }\n u.io.dataPort.rxQueue.ready.poke(false.B)\n\n u.io.dataPort.rxFull.expect(false.B)\n u.io.dataPort.txFull.expect(false.B)\n\n rxOne(u, \"h5a\".U)\n u.io.dataPort.rxFull.expect(false.B)\n (0 to 64).foreach(_ => rxOne(u, \"h5a\".U))\n u.io.dataPort.rxFull.expect(true.B)\n\n u.io.dataPort.txQueue.bits.poke(\"h75\".U)\n u.io.dataPort.txQueue.valid.poke(true.B)\n u.clock.step()\n u.io.dataPort.txFull.expect(false.B)\n (0 to 64).foreach(_ => u.clock.step())\n u.io.dataPort.txFull.expect(true.B)\n }\n }\n}\n", "groundtruth": " def clockSerial(clk: Clock) = clk.step(fpgaClock / baudRate)\n", "crossfile_context": ""}