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File size: 39,815 Bytes
d6720f3 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 | {"file": "gbaHD/hdl/borderGen.vhd", "target_type": "entity_declaration", "cursor_line": 9, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " generic(\n xMin : integer;\n"}
{"file": "gbaHD/hdl/captureGBA.vhd", "target_type": "process_statement", "cursor_line": 112, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " process( clk ) is\n begin\n if rising_edge( clk ) then\n if ( colorMode = '1' ) then\n redPxlOut <= redGBACol;\n"}
{"file": "gbaHD/hdl/commTransceiver.vhd", "target_type": "process_statement", "cursor_line": 179, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " elsif ( curPacket( packetBits - 1 downto packetBits - prefixLen ) = osdState_prefix ) then\n osdActive <= curPacket( 0 );\n osdState( 6 downto 0 ) <= curPacket( 7 downto 1 );\n"}
{"file": "gbaHD/hdl/drp.vhd", "target_type": "process_statement", "cursor_line": 623, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " process( clk ) is\n begin\n if ( rising_edge( clk ) ) then\n if ( fsmSingleValCur = applyMask ) then\n maskedVal <= ( nextMask and doSig ) or ( nextVal and not( nextMask ) ) ;\n"}
{"file": "gbaHD/hdl/font5x7.vhd", "target_type": "architecture_body", "cursor_line": 91, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " ind := offset + x;\n \n charPxl <= font( char )( ind );\n end if;\n end if;\n"}
{"file": "gbaHD/hdl/fracDiv.vhd", "target_type": "process_statement", "cursor_line": 38, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " end if;\n \n cnt <= tmpCnt;\n end if;\n"}
{"file": "gbaHD/hdl/gbaShaderApprox.vhd", "target_type": "architecture_body", "cursor_line": 56, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " case gbaRed is \n when \"00000\" => baseRed <= \"00000000\";\n when \"00001\" => baseRed <= \"00000001\";\n when \"00010\" => baseRed <= \"00000101\";\n when \"00011\" => baseRed <= \"00001000\";\n"}
{"file": "gbaHD/hdl/gbaShader_new.vhd", "target_type": "entity_declaration", "cursor_line": 10, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity gbaColorCorrNew is\n port(\n gbaRed : in std_logic_vector( 4 downto 0 );\n gbaGreen : in std_logic_vector( 4 downto 0 );\n"}
{"file": "gbaHD/hdl/lineBuffer.vhd", "target_type": "process_statement", "cursor_line": 95, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " readSel( i ) <= '0';\n end if;\n end loop;\n end process;\n"}
{"file": "gbaHD/hdl/lineCache.vhd", "target_type": "entity_declaration", "cursor_line": 14, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " rst : in std_logic;\n"}
{"file": "gbaHD/hdl/osd.vhd", "target_type": "process_statement", "cursor_line": 171, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " mainMenu( SMOOTHFIELDY )( SMOOTHFIELDX + 2 ) <= 6;\n end if;\n \n if ( pixelGrid_int = '1' ) then\n if ( bgrid_int = '1' ) then\n"}
{"file": "gbaHD/hdl/padOverlay.vhd", "target_type": "architecture_body", "cursor_line": 71, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\nsignal butUp, butDown, butLeft, butRight, butA, butB, butL, butR,\n butStart, butSelect : std_logic;\n\n"}
{"file": "gbaHD/hdl/singeLineBuffer.vhd", "target_type": "entity_declaration", "cursor_line": 20, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " redDataIn : in std_logic_vector( 7 downto 0 );\n blueDataIn : in std_logic_vector( 7 downto 0 );\n greenDataIn : in std_logic_vector( 7 downto 0 );\n \n"}
{"file": "gbaHD/hdl/smooth.vhd", "target_type": "case_statement", "cursor_line": 316, "target_nlines": 2, "node_depth": 12, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "else", "sequence_of_statements", "case_statement", "case_statement_alternative", "sequence_of_statements", "case_statement"], "target": " rOut <= smoothOut( 0 )( 3 )( 0 );\n gOut <= smoothOut( 0 )( 3 )( 1 );\n"}
{"file": "HD-64/development/firmware/vicii/bad_line_detect.vhdl", "target_type": "architecture_body", "cursor_line": 64, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\n\tp_detect : process(clk) is\n\t\tvariable v_enable : std_wire;\n"}
{"file": "HD-64/development/firmware/vicii/border.vhdl", "target_type": "entity_declaration", "cursor_line": 46, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\typos : in t_ppos;\n\treg : in t_regs;\n\n\to_vbrd : out std_wire;\n"}
{"file": "HD-64/development/firmware/vicii/bus_latch.vhdl", "target_type": "entity_declaration", "cursor_line": 42, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "(\n\tclk : in std_wire; -- must be twice the video clock (16 times ph0)\n\trst : in std_wire;\n\n"}
{"file": "HD-64/development/firmware/vicii/bus_logger.vhdl", "target_type": "architecture_body", "cursor_line": 81, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\tsignal data_in : std_word(c_bit_width - 1 downto 0);\n\tsignal push_in : std_wire;\n"}
{"file": "HD-64/development/firmware/vicii/dot_clock.vhdl", "target_type": "process_statement", "cursor_line": 144, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\t\to_clk <= '0';\n\t\t\tend if;\n\t\tend if;\n"}
{"file": "HD-64/development/firmware/vicii/graphics_gen.vhdl", "target_type": "case_statement", "cursor_line": 340, "target_nlines": 3, "node_depth": 15, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "case_statement"], "target": "\t\t\t\t\t\twhen MODE_STD_TEXT =>\n\t\t\t\t\t\t\to_colr <= x\"0\"; -- BLACK\n\t\t\t\t\t\twhen MODE_MCL_TEXT =>\n"}
{"file": "HD-64/development/firmware/vicii/graphics_mux.vhdl", "target_type": "entity_declaration", "cursor_line": 62, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\ti_sprt_prio : in std_wire;\n\ti_sprt_colr : in t_colr;\n"}
{"file": "HD-64/development/firmware/vicii/registers.vhdl", "target_type": "architecture_body", "cursor_line": 191, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\t\tend if;\n\t\tend if;\n\tend process;\n\nend architecture;\n"}
{"file": "HD-64/development/firmware/vicii/sprites.vhdl", "target_type": "entity_declaration", "cursor_line": 54, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\n\ti_data : in std_word(7 downto 0);\n\to_prio : out std_wire;\n\to_actv : out std_wire;\n\to_colr : out t_colr\n"}
{"file": "HD-64/development/firmware/vicii/strobe.vhdl", "target_type": "entity_declaration", "cursor_line": 50, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "port\n(\n\tclk : in std_wire;\n"}
{"file": "HD-64/development/firmware/vicii/sync_flex.vhdl", "target_type": "process_statement", "cursor_line": 147, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\typos <= h65_ypos;\n\t\t\tspecs <= c_vic_h65_specs;\n\n"}
{"file": "HD-64/development/firmware/vicii/vic_passive.vhdl", "target_type": "entity_declaration", "cursor_line": 59, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t-- vic detection\n\tvic_type : out t_vic_type;\n"}
{"file": "HD-64/development/firmware/vicii/vic_pkg.vhdl", "target_type": "constant_declaration", "cursor_line": 44, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "constant_declaration"], "target": "\tconstant c_xpos_bits : positive := bits_for_range(c_max_xlen);\n"}
{"file": "HD-64/development/firmware/vicii/video_matrix.vhdl", "target_type": "process_statement", "cursor_line": 191, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\n\t\t\trst_1r <= rst;\n\t\t\tif rst_1r then\n"}
{"file": "HD-64/development/firmware/vicii/xy_sync.vhdl", "target_type": "case_statement", "cursor_line": 160, "target_nlines": 1, "node_depth": 15, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "case_statement"], "target": "\t\t\t\t\t\t\tend if;\n"}
{"file": "RPU/tests/rpu_core_tb.vhd", "target_type": "process_statement", "cursor_line": 544, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "begin\nif rising_edge(cEng_core) then\n count12MHz_stable <= count12MHz;\nend if;\nend process;\n"}
{"file": "RPU/tests/tb_alu_int32_div.vhd", "target_type": "entity_declaration", "cursor_line": 37, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity alu_int32_div_tb is\n-- Port ( );\nend alu_int32_div_tb;\n"}
{"file": "RPU/tests/tb_unit_alu_RV32I_01.vhd", "target_type": "process_statement", "cursor_line": 130, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " wait for I_clk_period*2;\n\n I_dataA <= X\"00000001\";\n\t\tI_dataB <= X\"00000006\";\n"}
{"file": "RPU/tests/tb_unit_decoder_RV32_01.vhd", "target_type": "process_statement", "cursor_line": 96, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " begin\n\t\tI_clk <= '0';\n\t\twait for I_clk_period/2;\n\t\tI_clk <= '1';\n\t\twait for I_clk_period/2;\n"}
{"file": "RPU/vhdl/alu_int32_div.vhd", "target_type": "architecture_body", "cursor_line": 56, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " constant STATE_IDLE : integer := 0;\n constant STATE_INFLIGHTU : integer := 1;\n constant STATE_COMPLETE : integer := 2;\n\n"}
{"file": "RPU/vhdl/constants.vhd", "target_type": "constant_declaration", "cursor_line": 226, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "constant_declaration"], "target": "constant EXCEPTION_STORE_AMO_PAGE_FAULT: std_logic_vector(XLEN32M1 downto 0):= X\"0000000f\";\n"}
{"file": "RPU/vhdl/control_unit.vhd", "target_type": "process_statement", "cursor_line": 114, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " interrupt_was_inactive <= '0';\n interrupt_state <= \"001\";\n next_s_state <= \"0000001\"; --F\n"}
{"file": "RPU/vhdl/core.vhd", "target_type": "entity_declaration", "cursor_line": 36, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " I_int_data : in STD_LOGIC_VECTOR(31 downto 0);\n I_int : in STD_LOGIC;\n O_int_ack : out STD_LOGIC;\n\n -- memory interface\n"}
{"file": "RPU/vhdl/csr_unit.vhd", "target_type": "process_statement", "cursor_line": 155, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " csr_instret <= std_logic_vector(unsigned(csr_instret) + 1);\n end if;\n"}
{"file": "RPU/vhdl/lint_unit.vhd", "target_type": "process_statement", "cursor_line": 101, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " actual_int <= '1';\n actual_int_data <= I_int_data1;\n int1_ack <= '1';\n elsif I_enMask(2) = '1' and I_int2 = '1' and int2_ack = '0' then\n actual_int <= '1';\n"}
{"file": "RPU/vhdl/mem_controller.vhd", "target_type": "architecture_body", "cursor_line": 109, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " end if;\n elsif state = 2 then\n cmd <= '0';\n state <= 0;\n"}
{"file": "RPU/vhdl/pc_unit.vhd", "target_type": "process_statement", "cursor_line": 45, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\tbegin\n\t\tif rising_edge(I_clk) then\n\t\t\tcase I_nPCop is\n"}
{"file": "RPU/vhdl/register_set.vhd", "target_type": "entity_declaration", "cursor_line": 36, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " O_dataA : out STD_LOGIC_VECTOR (XLENM1 downto 0);-- regRS1 data out\n O_dataB : out STD_LOGIC_VECTOR (XLENM1 downto 0) -- regRS2 data out\n"}
{"file": "RPU/vhdl/unit_alu_RV32_I.vhd", "target_type": "case_statement", "cursor_line": 142, "target_nlines": 1, "node_depth": 15, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "if_statement", "elsif", "sequence_of_statements", "case_statement", "case_statement_alternative", "sequence_of_statements", "case_statement"], "target": " when F3_OPIMM_SLTIU =>\n"}
{"file": "RPU/vhdl/unit_decoder_RV32I.vhd", "target_type": "entity_declaration", "cursor_line": 39, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " O_memOp : out STD_LOGIC_VECTOR(4 downto 0); -- Memory operation \n O_csrOP : out STD_LOGIC_VECTOR(4 downto 0); -- CSR operations\n O_csrAddr : out STD_LOGIC_VECTOR(11 downto 0); -- CSR address\n O_trapExit : out STD_LOGIC; -- request to exit trap handler\n"}
{"file": "T13x/klessydra-t1-3th/PKG_RiscV_Klessydra.vhd", "target_type": "constant_declaration", "cursor_line": 383, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "constant_declaration"], "target": " constant SYSTEM : std_logic_vector(6 downto 0) := \"1110011\";\r\n"}
{"file": "T13x/klessydra-t1-3th/RTL-Accumulator.vhd", "target_type": "process_statement", "cursor_line": 141, "target_nlines": 2, "node_depth": 9, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "for_generate_statement", "generate_statement_body", "if_generate_statement", "if_generate", "generate_statement_body", "process_statement"], "target": " dsp_out_accum_results(f) <= std_logic_vector(unsigned(accum_partial_results_stg_1(f)(15 downto 0)) + \n unsigned(accum_partial_results_stg_1(f)(31 downto 16)) +\n"}
{"file": "T13x/klessydra-t1-3th/RTL-CSR_Unit.vhd", "target_type": "case_statement", "cursor_line": 832, "target_nlines": 5, "node_depth": 23, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "for_generate_statement", "generate_statement_body", "process_statement", "sequence_of_statements", "if_statement", "elsif", "sequence_of_statements", "if_statement", "elsif", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "case_statement", "case_statement_alternative", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "case_statement"], "target": " if(rs1(instr_word_IE) /= 0) then\r\n MHPMCOUNTER9(h) <= (MHPMCOUNTER9(h) or csr_wdata_i);\r\n end if;\r\n when CSRRC|CSRRCI =>\r\n csr_rdata_o_replicated(h) <= MHPMCOUNTER9(h);\r\n"}
{"file": "T13x/klessydra-t1-3th/RTL-DSP_Unit.vhd", "target_type": "process_statement", "cursor_line": 1802, "target_nlines": 5, "node_depth": 6, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "for_generate_statement", "generate_statement_body", "process_statement"], "target": " h := g; -- set the spm rd/wr ports equal to the \"for-loop\"\n elsif multithreaded_accl_en = 0 then\n h := f; -- set the spm rd/wr ports equal to the \"for-generate\" \n end if;\n -- Addition in SIMD Virtual Parallelism is executed here, if the carries are blocked, we will have a chain of 8-bit or 16-bit adders, else we have 32-bit adders\n"}
{"file": "T13x/klessydra-t1-3th/RTL-Debug_Unit.vhd", "target_type": "process_statement", "cursor_line": 165, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " end if;\r\n when others =>\r\n null;\r\n"}
{"file": "T13x/klessydra-t1-3th/RTL-ID_STAGE.vhd", "target_type": "case_statement", "cursor_line": 253, "target_nlines": 3, "node_depth": 18, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "elsif", "sequence_of_statements", "if_statement", "else", "sequence_of_statements", "case_statement", "case_statement_alternative", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "case_statement"], "target": " case FUNCT3_wires is\n when ADD => --ADD instruction\n decoded_instruction_IE <= ADD7_pattern;\n"}
{"file": "T13x/klessydra-t1-3th/RTL-IE_STAGE.vhd", "target_type": "process_statement", "cursor_line": 1043, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " pass_BLTU <= '1';\n else\n pass_BGEU <= '1';\n end if;\n end if;\n"}
{"file": "T13x/klessydra-t1-3th/RTL-IF_STAGE.vhd", "target_type": "process_statement", "cursor_line": 68, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " begin\n if busy_ID = '0' then\n instr_req_o <= '1';\n else\n instr_req_o <= '0';\n"}
{"file": "T13x/klessydra-t1-3th/RTL-Load_Store_Unit.vhd", "target_type": "case_statement", "cursor_line": 265, "target_nlines": 2, "node_depth": 12, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "elsif", "sequence_of_statements", "if_statement", "elsif", "sequence_of_statements", "case_statement"], "target": " misaligned_err <= '1';\n elsif load_err = '1' then -- AAA move to data_valid_waiting stage\n"}
{"file": "T13x/klessydra-t1-3th/RTL-Processing_Pipeline.vhd", "target_type": "case_statement", "cursor_line": 1690, "target_nlines": 4, "node_depth": 15, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "if_generate_statement", "if_generate", "generate_statement_body", "process_statement", "sequence_of_statements", "if_statement", "elsif", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "case_statement"], "target": " if decoded_instruction_LS(KMEMLD_bit_position) = '1' then\r\n write(row0, string'(\" kmemld x\"));\r\n end if;\r\n\r\n"}
{"file": "T13x/klessydra-t1-3th/RTL-Program_Counter_unit.vhd", "target_type": "entity_declaration", "cursor_line": 64, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " mepc_incremented_pc : out array_2D(THREAD_POOL_SIZE - 1 downto 0)(31 downto 0);\r\n mepc_interrupt_pc : out array_2D(THREAD_POOL_SIZE - 1 downto 0)(31 downto 0);\r\n irq_pending : out std_logic_vector(THREAD_POOL_SIZE - 1 downto 0);\r\n clk_i : in std_logic;\r\n"}
{"file": "T13x/klessydra-t1-3th/RTL-Registerfile.vhd", "target_type": "entity_declaration", "cursor_line": 57, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\tMUL_WB : in std_logic_vector(31 downto 0);\n\tLS_WB : in std_logic_vector(31 downto 0);\n\tinstr_word_LS_WB : in std_logic_vector(31 downto 0);\n\tinstr_word_IE_WB : in std_logic_vector(31 downto 0);\n\tharc_LS_WB : in integer range THREAD_POOL_SIZE-1 downto 0;\n"}
{"file": "T13x/klessydra-t1-3th/RTL-Scratchpad_Memory.vhd", "target_type": "entity_declaration", "cursor_line": 29, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " Addr_Width : natural;\n SIMD : natural;\n --------------------------------\n ACCL_NUM : natural;\n"}
{"file": "T13x/klessydra-t1-3th/RTL-Scratchpad_Memory_Interface.vhd", "target_type": "process_statement", "cursor_line": 206, "target_nlines": 4, "node_depth": 6, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "for_generate_statement", "generate_statement_body", "process_statement"], "target": " sc_addr_wr(h)(l) <= (others => '0');\n sc_data_wr(h)(l) <= (others => '0');\n end loop;\n rd_offset(h) <= (others => (others => '0'));\n"}
{"file": "T13x/klessydra-t1-3th/STR-Klessydra_top.vhd", "target_type": "process_statement", "cursor_line": 548, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " begin\r\n if rst_ni = '0' then\r\n elsif rising_edge(clk_i) then\r\n pc_except_value <= pc_except_value_wire; -- AAA verify if it is working for DSP and LSU (not verified yet)\r\n"}
{"file": "deniser/hdl/denise.vhdl", "target_type": "case_statement", "cursor_line": 395, "target_nlines": 2, "node_depth": 6, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "case_statement"], "target": " when \"000\" => v.d.bplen := \"000000\";\n when \"001\" => v.d.bplen := \"000001\";\n"}
{"file": "deniser/hdl/joyquad.vhdl", "target_type": "architecture_body", "cursor_line": 36, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "architecture rtl of joyquad is\n type reg_t is record\n d : unsigned(7 downto 0);\n v : std_ulogic;\n vq : std_ulogic;\n"}
{"file": "deniser/hdl/ocs.vhdl", "target_type": "constant_declaration", "cursor_line": 33, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "constant_declaration"], "target": " constant RGA_DIWSTRT : addr_t := x\"08E\";\n"}
{"file": "deniser/hdl/portable/inferred/oddr.vhdl", "target_type": "entity_declaration", "cursor_line": 21, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity oddr is\n port (\n"}
{"file": "deniser/hdl/portable/machxo3d/oddr.vhdl", "target_type": "entity_declaration", "cursor_line": 27, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " d1 : in std_ulogic;\n q : out std_ulogic\n );\nend;\n"}
{"file": "deniser/hdl/priv.vhdl", "target_type": "case_statement", "cursor_line": 163, "target_nlines": 1, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "sequence_of_statements", "case_statement"], "target": " when x\"156\" => s.spr(2).datb:= '1';\n"}
{"file": "deniser/hdl/sim/rga_bfm.vhdl", "target_type": "if_statement", "cursor_line": 80, "target_nlines": 1, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "procedure_body", "sequence_of_statements", "if_statement"], "target": " if cmd.log < LOG_DEBUG then return; end if;\n"}
{"file": "deniser/hdl/sim/rga_bfm_impl.vhdl", "target_type": "case_statement", "cursor_line": 72, "target_nlines": 3, "node_depth": 8, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "loop_statement", "sequence_of_statements", "case_statement"], "target": " deni.drd <= (others => 'Z') after 20 ns;\n else\n rgacmd.rdata <= deno.drd;\n"}
{"file": "deniser/hdl/sim/tb.vhdl", "target_type": "entity_declaration", "cursor_line": 25, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity tb is\nend;\n"}
{"file": "deniser/hdl/sim/tbtest.vhdl", "target_type": "entity_declaration", "cursor_line": 32, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity test is\nend;\n"}
{"file": "deniser/hdl/sim/text.vhdl", "target_type": "variable_declaration", "cursor_line": 27, "target_nlines": 1, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "procedure_body", "declarative_part", "variable_declaration"], "target": " variable l : line;\n"}
{"file": "deniser/hdl/syncer.vhdl", "target_type": "entity_declaration", "cursor_line": 28, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " q : out std_ulogic\n"}
{"file": "deniser/hdl/test/joy0.vhdl", "target_type": "process_statement", "cursor_line": 9, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " rga_write(rgacmd, RGA_DIWSTRT, x\"2c81\");\n"}
{"file": "deniser/hdl/test/wb0.vhdl", "target_type": "architecture_body", "cursor_line": 13, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\n rga_write(rgacmd, RGA_COLOR00, x\"0000\");\n rga_write(rgacmd, RGA_COLOR01, x\"0111\");\n rga_write(rgacmd, RGA_COLOR02, x\"0222\");\n"}
{"file": "deniser/hdl/top.vhdl", "target_type": "entity_declaration", "cursor_line": 35, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " m0v : in std_ulogic;\n m0h : in std_ulogic;\n"}
{"file": "fphdl/env_c.vhdl", "target_type": "package_body", "cursor_line": 14, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "package_body"], "target": " begin\n report \"Procedure STOP called with status: \" & INTEGER'image(STATUS)\n severity failure;\n"}
{"file": "fphdl/fixed_float_types_c.vhdl", "target_type": "package_declaration", "cursor_line": 29, "target_nlines": 1, "node_depth": 1, "node_path": ["design_file", "package_declaration"], "target": " type round_type is (round_nearest, -- Default, nearest LSB '0'\n"}
{"file": "fphdl/fixed_noresize.vhdl", "target_type": "variable_declaration", "cursor_line": 4064, "target_nlines": 1, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "procedure_body", "declarative_part", "variable_declaration"], "target": " variable result : ufixed (VALUE'range);\n"}
{"file": "fphdl/fixed_pkg_c.vhdl", "target_type": "case_statement", "cursor_line": 6935, "target_nlines": 3, "node_depth": 6, "node_path": ["design_file", "design_unit", "package_body", "declarative_part", "procedure_body", "sequence_of_statements", "case_statement"], "target": " when '9' => result := x\"9\"; good := true;\n when 'A' | 'a' => result := x\"A\"; good := true;\n when 'B' | 'b' => result := x\"B\"; good := true;\n"}
{"file": "fphdl/fixed_synth.vhdl", "target_type": "process_statement", "cursor_line": 110, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " variable outarray : cry_type; -- array for output\n variable in1array, in2array : cry_type; -- array for input\n"}
{"file": "fphdl/float_noround_pkg.vhdl", "target_type": "case_statement", "cursor_line": 2946, "target_nlines": 3, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "sequence_of_statements", "case_statement"], "target": " fpresult := neg_zerofp (fraction_width => fraction_width-guard,\n exponent_width => exponent_width);\n when others =>\n"}
{"file": "fphdl/float_pkg_c.vhdl", "target_type": "case_statement", "cursor_line": 1513, "target_nlines": 5, "node_depth": 8, "node_path": ["design_file", "package_body", "declarative_part", "procedure_body", "sequence_of_statements", "if_statement", "else", "sequence_of_statements", "case_statement"], "target": " when round_inf =>\n round := remainder(2) and not isign;\n when round_neginf =>\n round := remainder(2) and isign;\n when others =>\n"}
{"file": "fphdl/float_synth.vhdl", "target_type": "process_statement", "cursor_line": 545, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " outarray(0) := not (in1reg3);\n when \"001\" =>\n outarray(0) := in1reg3 and in2reg3;\n when \"010\" =>\n"}
{"file": "fphdl/numeric_std_additions.vhdl", "target_type": "case_statement", "cursor_line": 2147, "target_nlines": 2, "node_depth": 10, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "sequence_of_statements", "if_statement", "else", "sequence_of_statements", "loop_statement", "sequence_of_statements", "case_statement"], "target": " when x\"5\" => result(i+1) := '5';\n when x\"6\" => result(i+1) := '6';\n"}
{"file": "fphdl/numeric_std_unsigned_c.vhdl", "target_type": "function_body", "cursor_line": 1482, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_body", "declarative_part", "function_body"], "target": " function \\?<\\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is\r\n begin\r\n return \\?<\\ (UNSIGNED(L), UNSIGNED(R));\r\n end function \\?<\\;\r\n"}
{"file": "fphdl/standard_additions_c.vhdl", "target_type": "case_statement", "cursor_line": 1996, "target_nlines": 5, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "sequence_of_statements", "case_statement"], "target": " and (tvar < roundvar and tvar > -roundvar) then\n-- and ((bvalue-roundvar) = real(frcptr)) then\n write (L, frcptr); -- Just a short integer, write it.\n elsif (exp >= dwidth) or (exp < -4) then\n -- in \"e\" format (modified)\n"}
{"file": "fphdl/standard_textio_additions_c.vhdl", "target_type": "case_statement", "cursor_line": 122, "target_nlines": 5, "node_depth": 6, "node_path": ["design_file", "design_unit", "package_body", "declarative_part", "procedure_body", "sequence_of_statements", "case_statement"], "target": " when '6' => result := x\"6\"; good := true;\n when '7' => result := x\"7\"; good := true;\n when '8' => result := x\"8\"; good := true;\n when '9' => result := x\"9\"; good := true;\n when 'A' | 'a' => result := x\"A\"; good := true;\n"}
{"file": "fphdl/std_logic_1164_additions.vhdl", "target_type": "case_statement", "cursor_line": 1456, "target_nlines": 4, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "procedure_body", "sequence_of_statements", "case_statement"], "target": " when '0' => result := o\"0\"; good := true;\n when '1' => result := o\"1\"; good := true;\n when '2' => result := o\"2\"; good := true;\n when '3' => result := o\"3\"; good := true;\n"}
{"file": "fphdl/test_fixed_synth.vhdl", "target_type": "entity_declaration", "cursor_line": 9, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity test_fixed_synth is\n generic (\n quiet : boolean := false); -- make the simulation quiet\nend entity test_fixed_synth;\n"}
{"file": "fphdl/test_float_synth.vhdl", "target_type": "process_statement", "cursor_line": 132, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " if (not stop_clock) then\n"}
{"file": "haddoc2/lib/hdl/ConvLayer.vhd", "target_type": "architecture_body", "cursor_line": 123, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " generic map (\n BITWIDTH => BITWIDTH,\n IMAGE_WIDTH => IMAGE_WIDTH,\n KERNEL_SIZE => KERNEL_SIZE,\n NB_IN_FLOWS => NB_IN_FLOWS\n"}
{"file": "haddoc2/lib/hdl/DisplayLayer.vhd", "target_type": "architecture_body", "cursor_line": 40, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "begin\n out_data <= in_data(to_integer(unsigned(sel)));\n out_dv <= in_dv;\n out_fv <= in_fv;\n"}
{"file": "haddoc2/lib/hdl/DotProduct.vhd", "target_type": "architecture_body", "cursor_line": 101, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " out_valid => s_out_valid\n );\n out_dv <= s_out_valid;\n out_fv <= s_out_valid;\n\n"}
{"file": "haddoc2/lib/hdl/InputLayer.vhd", "target_type": "process_statement", "cursor_line": 45, "target_nlines": 1, "node_depth": 7, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "if_generate_statement", "if_generate", "generate_statement_body", "process_statement"], "target": " out_fv <= in_fv;\n"}
{"file": "haddoc2/lib/hdl/MCM.vhd", "target_type": "process_statement", "cursor_line": 51, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " if (in_valid = '1') then\n mcm_loop : for i in 0 to DOT_PRODUCT_SIZE - 1 loop\n out_data(i) <= KERNEL_VALUE(i) * in_data(i);\n"}
{"file": "haddoc2/lib/hdl/MOA.vhd", "target_type": "architecture_body", "cursor_line": 80, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\n elsif(rising_edge(clk)) then\n if (enable = '1') then\n"}
{"file": "haddoc2/lib/hdl/NeighExtractor.vhd", "target_type": "entity_declaration", "cursor_line": 70, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " enable : in std_logic;\n in_data : in std_logic_vector((BITWIDTH-1) downto 0);\n in_dv : in std_logic;\n"}
{"file": "haddoc2/lib/hdl/PoolLayer.vhd", "target_type": "architecture_body", "cursor_line": 92, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " in_data => in_data(i),\n"}
{"file": "haddoc2/lib/hdl/TanhLayer.vhd", "target_type": "entity_declaration", "cursor_line": 11, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " SUM_WIDTH : integer\n );\n port(\n in_data : in std_logic_vector (SUM_WIDTH-1 downto 0);\n"}
{"file": "haddoc2/lib/hdl/Taps.vhd", "target_type": "entity_declaration", "cursor_line": 39, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\n port (\n clk : in std_logic;\n"}
{"file": "haddoc2/lib/hdl/TensorExtractor.vhd", "target_type": "architecture_body", "cursor_line": 70, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " port map (\n"}
{"file": "haddoc2/lib/hdl/cnn_types.vhd", "target_type": "constant_declaration", "cursor_line": 35, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "constant_declaration"], "target": " constant V2 : integer := SCALE_FACTOR - 10;\n"}
{"file": "haddoc2/lib/hdl/maxPool.vhd", "target_type": "entity_declaration", "cursor_line": 23, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity maxPool is\n generic(\n BITWIDTH : integer;\n IMAGE_WIDTH : integer;\n"}
{"file": "haddoc2/lib/hdl/poolH.vhd", "target_type": "entity_declaration", "cursor_line": 16, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " enable : in std_logic;\n"}
{"file": "haddoc2/lib/hdl/poolV.vhd", "target_type": "process_statement", "cursor_line": 96, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " end if;\n"}
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