Datasets:
File size: 194,508 Bytes
d6720f3 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 | {"file": "General-CNN-Accelerator/CNN_Accelerator_Vivado_project/Accelerator.gen/sources_1/ip/div_gen_0/sim/div_gen_0.vhd", "target_type": "entity_declaration", "cursor_line": 60, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " PORT (\n aclk : IN STD_LOGIC;\n"}
{"file": "fos/compilation_flow/pr_flow/static/ultra96v1_128bit/PR_module.vhd", "target_type": "entity_declaration", "cursor_line": 53, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " m_axi_gmem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ADDR_WIDTH-1 downto 0);\n"}
{"file": "fos/compilation_flow/pr_flow/static/ultra96v1_32bit/PR_module.vhd", "target_type": "entity_declaration", "cursor_line": 79, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " s_axi_control_WREADY : OUT STD_LOGIC;\n s_axi_control_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_DATA_WIDTH-1 downto 0);\n s_axi_control_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_DATA_WIDTH/8-1 downto 0);\n s_axi_control_ARVALID : IN STD_LOGIC;\n s_axi_control_ARREADY : OUT STD_LOGIC;\n"}
{"file": "cpu_for_nscscc2022_single/thinpad_top.srcs/sources_1/new/Nova132A/lib/cache_bank/misc/blk_mem_gen_v8_4.vhd", "target_type": "architecture_body", "cursor_line": 147, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "architecture xilinx of blk_mem_gen_v8_4_4 is\n begin\n end \narchitecture xilinx;\n"}
{"file": "cpu_for_nscscc2022_single/thinpad_top.srcs/sources_1/new/Nova132A/lib/cache_bank/synth/cache_bank.vhd", "target_type": "architecture_body", "cursor_line": 74, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " GENERIC (\n C_FAMILY : STRING;\n C_XDEVICEFAMILY : STRING;\n"}
{"file": "cpu_for_nscscc2022_single/thinpad_top.srcs/sources_1/new/Nova132A/lib/dcache_tag/synth/dcache_tag.vhd", "target_type": "architecture_body", "cursor_line": 156, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " C_HAS_WE => 1,\n C_MEM_INIT_FILE => \"no_coe_file_loaded\",\n"}
{"file": "acSLAM/HW/rtl/Heapsort/ip/src/fifo_generator_0/fifo_generator_0.vho", "target_type": "component_instantiation_statement", "cursor_line": 82, "target_nlines": 2, "node_depth": 1, "node_path": ["design_file", "component_instantiation_statement"], "target": " rd_en => rd_en,\n dout => dout,\n"}
{"file": "acSLAM/HW/rtl/Heapsort/ip/src/fifo_generator_0/synth/fifo_generator_0.vhd", "target_type": "entity_declaration", "cursor_line": 68, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " overflow : OUT STD_LOGIC;\n empty : OUT STD_LOGIC;\n wr_rst_busy : OUT STD_LOGIC;\n rd_rst_busy : OUT STD_LOGIC\n );\n"}
{"file": "acSLAM/HW/rtl/Heapsort/src/fifo_generator_0/fifo_generator_0.vho", "target_type": "design_file", "cursor_line": 58, "target_nlines": 1, "node_depth": 0, "node_path": ["design_file"], "target": " srst : IN STD_LOGIC;\n"}
{"file": "acSLAM/HW/rtl/Heapsort/src/fifo_generator_0/synth/fifo_generator_0.vhd", "target_type": "entity_declaration", "cursor_line": 65, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " rd_en : IN STD_LOGIC;\n dout : OUT STD_LOGIC_VECTOR(291 DOWNTO 0);\n full : OUT STD_LOGIC;\n overflow : OUT STD_LOGIC;\n empty : OUT STD_LOGIC;\n"}
{"file": "AppleIISd/VHDL/AddressDecoder.vhd", "target_type": "process_statement", "cursor_line": 108, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " a_int <= \"0000\";\n elsif rising_edge(CLK) then\n ndev_sel_int <= NDEV_SEL;\n nio_sel_int <= NIO_SEL;\n nio_stb_int <= NIO_STB;\n"}
{"file": "AppleIISd/VHDL/AddressDecoder_Test.vhd", "target_type": "process_statement", "cursor_line": 117, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " if counter = 7 then\n"}
{"file": "AppleIISd/VHDL/AppleIISd.vhd", "target_type": "entity_declaration", "cursor_line": 46, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " NWE : out std_logic;\r\n PHI0 : in std_logic;\r\n NRESET : in std_logic;\r\n RNW : in std_logic;\r\n"}
{"file": "AppleIISd/VHDL/AppleIISd_Test.vhd", "target_type": "process_statement", "cursor_line": 146, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " CLK_process :process\n begin\n\t\tCLK <= '0';\n"}
{"file": "AppleIISd/VHDL/SpiController.vhd", "target_type": "process_statement", "cursor_line": 209, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " data_out(0) <= slavesel;\n data_out(3 downto 1) <= (others => '0');\n data_out(4) <= sdhc;\n"}
{"file": "FPGA-I2C-Minion/I2C_minion.vhd", "target_type": "process_statement", "cursor_line": 123, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " -- Delay SCL and SDA by 1 clock cycle\n scl_prev_reg <= scl_internal;\n sda_prev_reg <= sda_internal;\n"}
{"file": "FPGA-I2C-Minion/I2C_minion_TB_001_ideal.vhd", "target_type": "process_statement", "cursor_line": 84, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " begin\n if rising_edge(clk) then\n if data_valid = '1' then\n data_from_master_reg <= data_from_master;\n end if;\n"}
{"file": "FPGA-I2C-Minion/I2C_minion_TB_002_noisy_scl.vhd", "target_type": "process_statement", "cursor_line": 136, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " if ENDSIM = false then\n uniform(seed1, seed2, rand_sda); -- generate random number\n sda_spike_should_happen := rand_sda;\n uniform(seed1, seed2, rand_sda); -- generate random number\n"}
{"file": "FPGA-I2C-Minion/debounce.vhd", "target_type": "entity_declaration", "cursor_line": 22, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " clk : in std_logic);\nend entity debounce;\n"}
{"file": "FPGA-I2C-Minion/txt_util.vhd", "target_type": "case_statement", "cursor_line": 380, "target_nlines": 5, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "sequence_of_statements", "case_statement"], "target": " when 'D' => l := 'd';\n when 'E' => l := 'e';\n when 'F' => l := 'f';\n when 'G' => l := 'g';\n when 'H' => l := 'h';\n"}
{"file": "FPGA-Speech-Recognition/VHDL/Voice_Recognition.vhd", "target_type": "case_statement", "cursor_line": 288, "target_nlines": 5, "node_depth": 9, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "elsif", "sequence_of_statements", "case_statement"], "target": "\t\t\t\t\t\tend if;\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\tstate_one <= '1';\r\n\t\t\t\t\t \tstate_two <= '1';\r\n\t\t\t\t\t \tstate_three <= '1';\r\n"}
{"file": "FPGA-Speech-Recognition/VHDL/uart.vhd", "target_type": "process_statement", "cursor_line": 46, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " if (RST = '1') then\r\n uart_ticks <= 0;\r\n uart_clk_en <= '0';\r\n elsif (uart_ticks = divider_value-1) then\r\n uart_ticks <= 0;\r\n"}
{"file": "FPGA-Speech-Recognition/VHDL/uart_parity.vhd", "target_type": "process_statement", "cursor_line": 47, "target_nlines": 1, "node_depth": 7, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "if_generate_statement", "if_generate", "generate_statement_body", "process_statement"], "target": " PARITY_OUT <= parity_temp;\r\n"}
{"file": "FPGA-Speech-Recognition/VHDL/uart_rx.vhd", "target_type": "process_statement", "cursor_line": 123, "target_nlines": 5, "node_depth": 7, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "if_generate_statement", "if_generate", "generate_statement_body", "process_statement"], "target": " uart_rx_parity_check_reg : process (CLK)\r\n begin\r\n if (rising_edge(CLK)) then\r\n if (RST = '1') then\r\n rx_parity_error <= '0';\r\n"}
{"file": "FPGA-Speech-Recognition/VHDL/uart_tx.vhd", "target_type": "process_statement", "cursor_line": 159, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " tx_pstate <= idle;\r\n else\r\n"}
{"file": "NTSC-composite-encoder/vhdl/image_rom.vhdl", "target_type": "entity_declaration", "cursor_line": 43, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\tPORT\n\t(\n\t\taddress\t\t: IN STD_LOGIC_VECTOR (15 DOWNTO 0);\n\t\tclock\t\t: IN STD_LOGIC := '1';\n\t\tq\t\t: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)\n"}
{"file": "NTSC-composite-encoder/vhdl/ntsc_composite_top_de2.vhdl", "target_type": "entity_declaration", "cursor_line": 32, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\tvga_clk : out std_logic;\n\tvga_g : out std_logic_vector(9 downto 0);\n\tvga_blank : out std_logic;\n"}
{"file": "NTSC-composite-encoder/vhdl/ntsc_sync_generator.vhdl", "target_type": "entity_declaration", "cursor_line": 30, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity ntsc_sync_generator is Port ( \n\tclk_50 : in std_logic;\n\treset : in std_logic;\n"}
{"file": "NTSC-composite-encoder/vhdl/palette.vhdl", "target_type": "entity_declaration", "cursor_line": 29, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity palette is Port ( \n index : in std_logic_vector(3 downto 0);\n luma : out std_logic_vector(10 downto 0);\n"}
{"file": "NTSC-composite-encoder/vhdl/sine_rom.vhdl", "target_type": "entity_declaration", "cursor_line": 45, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\taddress\t\t: IN STD_LOGIC_VECTOR (10 DOWNTO 0);\n\t\tclock\t\t: IN STD_LOGIC := '1';\n\t\tq\t\t: OUT STD_LOGIC_VECTOR (8 DOWNTO 0)\n\t);\nEND sine_rom;\n"}
{"file": "Spiking_NN_RGB_FPGA/VHDL/control.vhd", "target_type": "entity_declaration", "cursor_line": 17, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\t\ths_out\t\t: out std_logic;\r\n\t\t\tde_out\t\t: out std_logic);\r\n"}
{"file": "Spiking_NN_RGB_FPGA/VHDL/gen_input.vhd", "target_type": "architecture_body", "cursor_line": 56, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\tif (to_integer(unsigned(random)) < g_st) then\r\n\t\t\tg_sp <= '1';\r\n"}
{"file": "Spiking_NN_RGB_FPGA/VHDL/neuron.vhd", "target_type": "architecture_body", "cursor_line": 76, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\telse\r\n\t\t\ttmp_sum_1 <= 0;\r\n\t\tend if;\r\n\r\n\t\tif sp_2 = '1' then\r\n"}
{"file": "Spiking_NN_RGB_FPGA/VHDL/sim_snn_rgb.vhd", "target_type": "entity_declaration", "cursor_line": 19, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity sim_snn_rgb is\nend sim_snn_rgb;\n"}
{"file": "Spiking_NN_RGB_FPGA/VHDL/snn_rgb.vhd", "target_type": "architecture_body", "cursor_line": 109, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " v_th => v_th)\r\n port map( clk => clk,\r\n"}
{"file": "VGA-Text-Generator/VGA-Text-Generator.srcs/sources_1/new/Font_Rom.vhd", "target_type": "entity_declaration", "cursor_line": 35, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\taddr: in integer;\n"}
{"file": "VGA-Text-Generator/VGA-Text-Generator.srcs/sources_1/new/Pixel_On_Text.vhd", "target_type": "process_statement", "cursor_line": 86, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " -- If current pixel is in the horizontal range of text\n if horzCoord >= position.x and horzCoord < position.x + (FONT_WIDTH * textlength) then\n"}
{"file": "VGA-Text-Generator/VGA-Text-Generator.srcs/sources_1/new/Pixel_On_Text2.vhd", "target_type": "process_statement", "cursor_line": 90, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " inYRange := true;\n end if;\n \n -- need to check if the pixel is on for text\n if inXRange and inYRange then\n"}
{"file": "VGA-Text-Generator/VGA-Text-Generator.srcs/sources_1/new/commonPak.vhd", "target_type": "constant_declaration", "cursor_line": 70, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "constant_declaration"], "target": "\tconstant init_type_outArbiterPort: type_outArbiterPort := (dataWaiting => false, data => (others => '0'), dataWritten => false);\n"}
{"file": "VGA-Text-Generator/VGA-Text-Generator.srcs/sources_1/new/wrapper.vhd", "target_type": "entity_declaration", "cursor_line": 28, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " yCoord: in std_logic_vector(11 downto 0);\n pixOn: out std_logic\n );\n"}
{"file": "spi-to-axi-bridge/src/spi2axi.vhd", "target_type": "case_statement", "cursor_line": 341, "target_nlines": 4, "node_depth": 12, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "if_statement", "else", "sequence_of_statements", "case_statement"], "target": " elsif spi_tx_byte_idx = 9 then\n spi_tx_byte := axi_rdata(7 downto 0);\n else\n -- Read status byte:\n"}
{"file": "spi-to-axi-bridge/tb/tb_spi2axi.vhd", "target_type": "entity_declaration", "cursor_line": 45, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " generic(\n SPI_CPOL : natural range 0 to 1 := 0; -- SPI clock polarity\n"}
{"file": "spi-to-axi-bridge/tb/tb_spi2axi_operation.vhd", "target_type": "architecture_body", "cursor_line": 143, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " variable status : std_logic_vector(7 downto 0);\n\n alias s_axi_awvalid_mask is << signal .tb_spi2axi.s_axi_awvalid_mask : std_logic >>;\n alias s_axi_arvalid_mask is << signal .tb_spi2axi.s_axi_arvalid_mask : std_logic >>;\n"}
{"file": "spi-to-axi-bridge/tb/tb_spi2axi_overrun.vhd", "target_type": "process_statement", "cursor_line": 128, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " end loop;\n assert tx_byte_idx = tx_bytes'length severity failure;\n --\n"}
{"file": "spi-to-axi-bridge/tb/tb_spi2axi_testctrl.vhd", "target_type": "entity_declaration", "cursor_line": 45, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " );\n port(\n -- Record Interfaces\n"}
{"file": "uart/source/generic_fifo.vhd", "target_type": "entity_declaration", "cursor_line": 12, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " clock : in std_logic;\n reset : in std_logic;\n write_data : in std_logic_vector(FIFO_WIDTH-1 downto 0);\n read_data : out std_logic_vector(FIFO_WIDTH-1 downto 0);\n"}
{"file": "uart/source/loopback.vhd", "target_type": "process_statement", "cursor_line": 138, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " fifo_data_in <= uart_data_out;\n end if;\n -- Clear transmission request strobe upon acknowledge.\n"}
{"file": "uart/source/tb_uart.vhd", "target_type": "process_statement", "cursor_line": 153, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " readline(input_file, data_line);\n read(data_line, data, read_ok);\n local_data <= to_stdlogicvector(data);\n"}
{"file": "uart/source/top.vhd", "target_type": "entity_declaration", "cursor_line": 12, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " clock_frequency : positive\n"}
{"file": "uart/source/uart.vhd", "target_type": "process_statement", "cursor_line": 158, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " elsif uart_rx_data_sr(1) = '0' and uart_rx_filter > 0 then\n uart_rx_filter <= uart_rx_filter - 1;\n end if;\n -- set the rx bit.\n if uart_rx_filter = 3 then\n"}
{"file": "FPGA-Class-D-Amplifier/PWM_Modulator.vhd", "target_type": "entity_declaration", "cursor_line": 15, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " mod_in : in signed (4 downto 0);\r\n mod_in_vld : in std_logic;\r\n \r\n pwm_p : out std_logic := '0';\r\n pwm_n : out std_logic := '0'\r\n"}
{"file": "FPGA-Class-D-Amplifier/UpSampler.vhd", "target_type": "process_statement", "cursor_line": 120, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\tend if;\t\t\t\r\n"}
{"file": "FPGA-Class-D-Amplifier/audiosystem.vhd", "target_type": "process_statement", "cursor_line": 164, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "process (i2s_l_in, gain)\r\nbegin\r\n\tl_in <= shift_left(resize(i2s_l_in,32), to_integer(gain));\r\nend process;\r\n"}
{"file": "FPGA-Class-D-Amplifier/i2s_rxtx.vhd", "target_type": "process_statement", "cursor_line": 48, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\telsif (bclk_edge = b\"01\") then\n\t\tframesync <= '0';\n\tend if;\n \n"}
{"file": "FPGA-Class-D-Amplifier/noiseshaper.vhd", "target_type": "process_statement", "cursor_line": 65, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "process (mul_inp_1, mul_inp_2)\r\nbegin\r\n\t--multiply and do right-shift by 15 (fixed-point mult with 32-bit int and q1.15 value)\r\n mul_result <= resize(shift_right(mul_inp_1*mul_inp_2,15),32);\r\nend process;\r\n"}
{"file": "FPGA-Class-D-Amplifier/top.vhd", "target_type": "architecture_body", "cursor_line": 53, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " i2s_bclk : out std_logic;\r\n i2s_lr : out std_logic;\r\n i2s_din : in std_logic; \r\n\r\n"}
{"file": "ZynqBTC/hls/ip/hdl/vhdl/sha256_final.vhd", "target_type": "process_statement", "cursor_line": 735, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " end if; \n end process;\n"}
{"file": "ZynqBTC/hls/ip/hdl/vhdl/sha256_top.vhd", "target_type": "process_statement", "cursor_line": 618, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " end if; \n end process;\n"}
{"file": "ZynqBTC/hls/ip/hdl/vhdl/sha256_transform.vhd", "target_type": "process_statement", "cursor_line": 357, "target_nlines": 2, "node_depth": 1, "node_path": ["ERROR", "process_statement"], "target": " begin\n if (ap_clk'event and ap_clk = '1') then\n"}
{"file": "ZynqBTC/hls/ip/hdl/vhdl/sha256_transform_k.vhd", "target_type": "entity_declaration", "cursor_line": 22, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " clk : in std_logic\n ); \nend entity; \n"}
{"file": "ZynqBTC/hls/ip/hdl/vhdl/sha256_transform_m.vhd", "target_type": "entity_declaration", "cursor_line": 18, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " mem_size : integer := 64\n ); \n port (\n"}
{"file": "ZynqBTC/hls/ip/hdl/vhdl/sha256_update.vhd", "target_type": "process_statement", "cursor_line": 311, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " else \n ap_ready <= ap_const_logic_0;\n"}
{"file": "bit-serial/bit.vhd", "target_type": "case_statement", "cursor_line": 447, "target_nlines": 1, "node_depth": 12, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "case_statement", "case_statement_alternative", "sequence_of_statements", "if_statement", "else", "sequence_of_statements", "case_statement"], "target": "\t\t\t\t\tf.choice <= STORE after delay;\n"}
{"file": "bit-serial/peripherals.vhd", "target_type": "entity_declaration", "cursor_line": 31, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\ti, a: in std_ulogic;\n\t\to: out std_ulogic;\n \t\toe, ie, ae: in std_ulogic);\n"}
{"file": "bit-serial/tb.vhd", "target_type": "process_statement", "cursor_line": 163, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\twhile (count < cfg.clocks or cfg.forever) and halt = '0' loop\n\t\t\tclk <= '1';\n\t\t\twait for clock_period / 2;\n"}
{"file": "bit-serial/top.vhd", "target_type": "entity_declaration", "cursor_line": 19, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\tdebug: natural := 0; -- will not synthesize if greater than zero (debug off = 0)\n\t\tuart_use_cfg: boolean := false;\n\t\tuart_fifo_depth: natural := 0\n"}
{"file": "bit-serial/uart.vhd", "target_type": "architecture_body", "cursor_line": 678, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\tif rst = '1' and g.asynchronous_reset then\n\t\t\treset;\n\t\telsif rising_edge(clk) then\n\t\t\tif rst = '1' and not g.asynchronous_reset then\n"}
{"file": "bit-serial/util.vhd", "target_type": "process_statement", "cursor_line": 243, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\tbegin\n\t\tif rising_edge(clk) then\n\t\t\tif dwe = '1' then\n\t\t\t\tram(to_integer(unsigned(addr))) := din;\n\t\t\tend if;\n"}
{"file": "formal_hw_verification/alu/alu.vhd", "target_type": "case_statement", "cursor_line": 51, "target_nlines": 5, "node_depth": 9, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "elsif", "sequence_of_statements", "case_statement"], "target": " when c_sub =>\n v_result := std_logic_vector(unsigned('0' & DinA_i) -\n unsigned('0' & DinB_i));\n when c_and => v_result := ('0', DinA_i and DinB_i);\n when c_or => v_result := ('0', DinA_i or DinB_i);\n"}
{"file": "formal_hw_verification/counter/counter.vhd", "target_type": "process_statement", "cursor_line": 48, "target_nlines": 4, "node_depth": 7, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "if_generate_statement", "if_generate", "generate_statement_body", "process_statement"], "target": " AFTER_RESET : process (all) is\n begin\n if (not Reset_n_i) then\n RESET_DATA : assert unsigned(Data_o) = to_unsigned(InitVal, Data_o'length);\n"}
{"file": "formal_hw_verification/fifo/fifo.vhd", "target_type": "process_statement", "cursor_line": 104, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " if (Wen_i = '0' and s_almost_empty) then\n Empty_o <= '1';\n end if;\n Full_o <= '0';\n end if;\n"}
{"file": "formal_hw_verification/fwft_fifo/fwft_fifo.vhd", "target_type": "entity_declaration", "cursor_line": 18, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " Din_i : in std_logic_vector(Width-1 downto 0);\n Full_o : out std_logic;\n"}
{"file": "formal_hw_verification/vai_fifo/vai_fifo.vhd", "target_type": "architecture_body", "cursor_line": 65, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\n Accept_o <= not s_full;\n Valid_o <= not s_empty;\n\n\n"}
{"file": "formal_hw_verification/vai_reg/vai_reg.vhd", "target_type": "process_statement", "cursor_line": 240, "target_nlines": 2, "node_depth": 7, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "if_generate_statement", "if_generate", "generate_statement_body", "process_statement"], "target": " end if;\n end process AFTER_RESET;\n"}
{"file": "ipxact2systemverilog/example/output/example2_vhd_pkg.vhd", "target_type": "case_statement", "cursor_line": 86, "target_nlines": 2, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "sequence_of_statements", "case_statement"], "target": " when \"10\" => r:=c;\n when \"11\" => r:=d;\n"}
{"file": "ipxact2systemverilog/example/output/example_vhd_pkg.vhd", "target_type": "case_statement", "cursor_line": 267, "target_nlines": 3, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "sequence_of_statements", "case_statement"], "target": " case v is\n when \"00\" => r:=chimp;\n when \"01\" => r:=gorilla;\n"}
{"file": "ipxact2systemverilog/example/output_default/example_vhd_pkg.vhd", "target_type": "case_statement", "cursor_line": 220, "target_nlines": 4, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "sequence_of_statements", "case_statement"], "target": " when \"00\" => r:=chimp;\n when \"01\" => r:=gorilla;\n when \"10\" => r:=phb;\n when others => r:=chimp; -- error\n"}
{"file": "ipxact2systemverilog/example/output_no_default/example_vhd_pkg.vhd", "target_type": "case_statement", "cursor_line": 297, "target_nlines": 4, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "sequence_of_statements", "case_statement"], "target": " when \"01\" => r:=gorilla;\n when \"10\" => r:=chimp;\n when others => r:=phb; -- error\n end case;\n"}
{"file": "ipxact2systemverilog/example/tb/tb_vhd.vhd", "target_type": "process_statement", "cursor_line": 106, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " variable expected_value : std_ulogic_vector(width-1 downto 0);\n variable test_passed : boolean;\n variable temp_addr : std_ulogic_vector(addressWidth-1 downto 0);\n"}
{"file": "ipxact2systemverilog/example/tb/vhd_dut.vhd", "target_type": "architecture_body", "cursor_line": 28, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "architecture rtl of vhd_dut is\n signal registers_i_i : example_in_record_type;\n"}
{"file": "lfsr-vhdl/lfsr.vhd", "target_type": "process_statement", "cursor_line": 276, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\trout <= ra after delay;\n\t\traddr <= (others => '0') after delay;\n\t\traddr(npc'range) <= npc after delay;\n"}
{"file": "lfsr-vhdl/system.vhd", "target_type": "process_statement", "cursor_line": 82, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\tprocess (clk) begin\n\t\tif rising_edge(clk) then\n\t\t\tprint_debug_info;\n\t\tend if;\n\tend process;\n"}
{"file": "lfsr-vhdl/tb.vhd", "target_type": "entity_declaration", "cursor_line": 28, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\ten_non_io_tb: boolean := false; -- Do not generate UART, talk directly to `system.vhd` which is faster\n"}
{"file": "lfsr-vhdl/top.vhd", "target_type": "entity_declaration", "cursor_line": 29, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "--\t\trst: in std_ulogic;\n\t\thalted: out std_ulogic;\n\t\tblocked: out std_ulogic;\n\t\t-- synthesis translate_on\n"}
{"file": "lfsr-vhdl/uart.vhd", "target_type": "process_statement", "cursor_line": 141, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\tcase state is\n"}
{"file": "lfsr-vhdl/util.vhd", "target_type": "entity_declaration", "cursor_line": 195, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\taddr: in std_ulogic_vector(addr_length - 1 downto 0);\n\t\tdin: in std_ulogic_vector(data_length - 1 downto 0);\n"}
{"file": "vgg16-on-Zynq/vgg16.srcs/sources_1/ip/blk_mem_gen_0/misc/blk_mem_gen_v8_4.vhd", "target_type": "entity_declaration", "cursor_line": 57, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " C_HAS_MUX_OUTPUT_REGS_B : integer := 0;\n C_MUX_PIPELINE_STAGES : integer := 0;\n C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;\n C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;\n"}
{"file": "vgg16-on-Zynq/vgg16.srcs/sources_1/ip/blk_mem_gen_0/synth/blk_mem_gen_0.vhd", "target_type": "entity_declaration", "cursor_line": 60, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " PORT (\n"}
{"file": "vgg16-on-Zynq/vgg16.srcs/sources_1/ip/blk_mem_gen_1/misc/blk_mem_gen_v8_4.vhd", "target_type": "entity_declaration", "cursor_line": 95, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');\n doutb : out std_logic_vector(c_read_width_b - 1 downto 0);\n injectsbiterr : in std_logic := '0';\n injectdbiterr : in std_logic := '0';\n eccpipece : in std_logic := '0';\n"}
{"file": "vgg16-on-Zynq/vgg16.srcs/sources_1/ip/blk_mem_gen_1/synth/blk_mem_gen_1.vhd", "target_type": "entity_declaration", "cursor_line": 67, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)\n"}
{"file": "vgg16-on-Zynq/vgg16.srcs/sources_1/ip/mult_gen_0/sim/mult_gen_0.vhd", "target_type": "architecture_body", "cursor_line": 70, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " ATTRIBUTE DowngradeIPIdentifiedWarnings OF mult_gen_0_arch: ARCHITECTURE IS \"yes\";\n"}
{"file": "vgg16-on-Zynq/vgg16.srcs/sources_1/ip/mult_gen_0/synth/mult_gen_0.vhd", "target_type": "architecture_body", "cursor_line": 93, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " );\n PORT (\n"}
{"file": "FPGA-Vision/FPGA-Design/lane.vhd", "target_type": "entity_declaration", "cursor_line": 24, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " vs_out : out std_logic; -- corresponding to video-in\r\n hs_out : out std_logic;\r\n de_out : out std_logic;\r\n r_out : out std_logic_vector(7 downto 0);\r\n g_out : out std_logic_vector(7 downto 0);\r\n"}
{"file": "FPGA-Vision/FPGA-Design/lane_g_matrix.vhd", "target_type": "architecture_body", "cursor_line": 65, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " data_out <= sum*sum;\r\n\r\nend process;\r\n\r\n"}
{"file": "FPGA-Vision/FPGA-Design/lane_g_root_IP.vhd", "target_type": "entity_declaration", "cursor_line": 46, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\taddress\t\t: IN STD_LOGIC_VECTOR (12 DOWNTO 0);\r\n"}
{"file": "FPGA-Vision/FPGA-Design/lane_linemem.vhd", "target_type": "entity_declaration", "cursor_line": 14, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " reset : in std_logic;\r\n write_en : in std_logic;\r\n data_in : in std_logic_vector(23 downto 0);\r\n data_out : out std_logic_vector(23 downto 0));\r\nend lane_linemem;\r\n"}
{"file": "FPGA-Vision/FPGA-Design/lane_sobel.vhd", "target_type": "entity_declaration", "cursor_line": 18, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " data_out : out std_logic_vector(23 downto 0));\r\nend lane_sobel;\r\n"}
{"file": "FPGA-Vision/FPGA-Design/lane_sync.vhd", "target_type": "entity_declaration", "cursor_line": 18, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " vs_in : in std_logic;\r\n hs_in : in std_logic;\r\n de_in : in std_logic;\r\n vs_out : out std_logic;\r\n"}
{"file": "FPGA-Vision/FPGA-Design/sim_lane.vhd", "target_type": "process_statement", "cursor_line": 215, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " assert false\n report \"MISMATCH in simulation at position x=\" & integer'image(x_pos) & \" y=\" & integer'image(y_pos)\n severity note;\n end if;\n end if;\n"}
{"file": "FPGA_GigabitTx/hdl/add_crc32.vhd", "target_type": "entity_declaration", "cursor_line": 17, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " data_valid_in : in STD_LOGIC := '0';\n data_enable_in : in STD_LOGIC;\n data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');\n"}
{"file": "FPGA_GigabitTx/hdl/add_preamble.vhd", "target_type": "architecture_body", "cursor_line": 31, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " data_enable_out <= '0';\n if data_enable_in = '1' then\n"}
{"file": "FPGA_GigabitTx/hdl/byte_data.vhd", "target_type": "entity_declaration", "cursor_line": 13, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity byte_data is\r\n"}
{"file": "FPGA_GigabitTx/hdl/gigabit_test.vhd", "target_type": "case_statement", "cursor_line": 344, "target_nlines": 1, "node_depth": 9, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "case_statement"], "target": " when \"1110\" => max_count <= to_unsigned( 1_249,27); -- 100,000 packets per second\r\n"}
{"file": "FPGA_GigabitTx/hdl/rgmii_rx.vhd", "target_type": "entity_declaration", "cursor_line": 37, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " link_1000mb : out STD_LOGIC;\n link_full_duplex : out STD_LOGIC;\n"}
{"file": "FPGA_GigabitTx/hdl/rgmii_tx.vhd", "target_type": "process_statement", "cursor_line": 111, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " doutclk(1) <= '0';\n else \n"}
{"file": "FPGA_GigabitTx/testbench/tb_gigabit_test.vhd", "target_type": "process_statement", "cursor_line": 89, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "clk_proc: process\n begin\n clk100MHz <= '0';\n wait for 5 ns;\n clk100MHz <= '1';\n"}
{"file": "FPGA_image_process/isp_base/isp_base.ip_user_files/ip/shift_RAM_3X3_8bit/shift_RAM_3X3_8bit.vho", "target_type": "design_file", "cursor_line": 61, "target_nlines": 3, "node_depth": 0, "node_path": ["design_file"], "target": " );\nEND COMPONENT;\n-- COMP_TAG_END ------ End COMPONENT Declaration ------------\n"}
{"file": "FPGA_image_process/isp_base/isp_base.ip_user_files/ip/shift_RAM_3X3_8bit/shift_RAM_3X3_8bit_stub.vhdl", "target_type": "architecture_body", "cursor_line": 25, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "architecture stub of shift_RAM_3X3_8bit is\nattribute syn_black_box : boolean;\nattribute black_box_pad_pin : string;\n"}
{"file": "FPGA_image_process/isp_base/isp_base.srcs/sources_1/ip/shift_RAM_3X3_8bit/shift_RAM_3X3_8bit.vho", "target_type": "component_instantiation_statement", "cursor_line": 69, "target_nlines": 5, "node_depth": 1, "node_path": ["design_file", "component_instantiation_statement"], "target": "your_instance_name : shift_RAM_3X3_8bit\n PORT MAP (\n D => D,\n CLK => CLK,\n SCLR => SCLR,\n"}
{"file": "FPGA_image_process/isp_base/isp_base.srcs/sources_1/ip/shift_RAM_3X3_8bit/shift_RAM_3X3_8bit_sim_netlist.vhdl", "target_type": "entity_declaration", "cursor_line": 861, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " attribute C_DEFAULT_DATA of shift_RAM_3X3_8bit_c_shift_ram_v12_0_12 : entity is \"00000000\";\n attribute C_DEPTH : integer;\n"}
{"file": "FPGA_image_process/isp_base/isp_base.srcs/sources_1/ip/shift_RAM_3X3_8bit/shift_RAM_3X3_8bit_stub.vhdl", "target_type": "architecture_body", "cursor_line": 30, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "attribute x_core_info : string;\nattribute x_core_info of stub : architecture is \"c_shift_ram_v12_0_12,Vivado 2018.3\";\nbegin\n"}
{"file": "FPGA_image_process/isp_base/isp_base.srcs/sources_1/ip/shift_RAM_3X3_8bit/sim/shift_RAM_3X3_8bit.vhd", "target_type": "architecture_body", "cursor_line": 136, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " C_HAS_SSET => 0,\n"}
{"file": "FPGA_image_process/isp_base/isp_base.srcs/sources_1/ip/shift_RAM_3X3_8bit/synth/shift_RAM_3X3_8bit.vhd", "target_type": "entity_declaration", "cursor_line": 62, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " CLK : IN STD_LOGIC;\n SCLR : IN STD_LOGIC;\n Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)\n );\n"}
{"file": "Z80-512K/CPLD/Z80_512K.vhd", "target_type": "entity_declaration", "cursor_line": 40, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\twdog_led\t: out std_logic;\t\t\t\t\t\t\t\t-- WDOG - output for resetting the watchdog and driving the LED\r\n \t\trst_n\t\t: in std_logic;\t\t\t\t\t\t\t\t-- RESET - reset input, disables memory paging, watchdog\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t-- and sets divisor value to '1' (active low)\r\n\t\trom_cs_n\t: out std_logic;\t\t\t\t\t\t\t\t-- ROM_CS - ROM chip select output (active low)\r\n"}
{"file": "Z80-512K/CPLD/d_ff_rst.vhd", "target_type": "process_statement", "cursor_line": 40, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\tq <= '0';\t\t\t\t\t\t\t\t\t\t-- Reset if rst_n is active\r\n\t\telsif rising_edge(clk) then \r\n q <= d;\t\t\t\t\t\t\t\t\t\t\t-- Write data on the rising edge of clk\r\n\t\tend if;\r\n\tend process;\r\n"}
{"file": "Z80-512K/CPLD/divide_by_2.vhd", "target_type": "process_statement", "cursor_line": 41, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " begin\r\n\t\tif rising_edge(clk) then\r\n\t\t\tq <= d;\r\n\t\tend if;\r\n\tend process;\r\n"}
{"file": "Z80-512K/CPLD/divide_by_3.vhd", "target_type": "architecture_body", "cursor_line": 46, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\tend process;\r\nend architecture behavioral;"}
{"file": "Z80-512K/CPLD/page_reg_4x6.vhd", "target_type": "entity_declaration", "cursor_line": 31, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\twraddress\t: in std_logic_vector (1 downto 0); -- Input (write) address\r\n\t\twren\t\t\t: in std_logic;\t\t\t\t\t\t\t-- Write enable\r\n\t\trden\t\t\t: in std_logic;\t\t\t\t\t\t\t-- Read enable (register outputs \"000000\" when rden is inactive)\r\n\t\tq\t\t\t\t: out std_logic_vector (5 downto 0)\t-- Data (read) output\r\n );\r\n"}
{"file": "Z80-512K/CPLD/register_6.vhd", "target_type": "process_statement", "cursor_line": 38, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " begin\r\n\t\tif rst_n = '0' then\r\n\t\t\tq <= \"000000\";\t\t\t\t\t\t\t\t\t-- Reset if rst_n is active\r\n"}
{"file": "Z80-512K/CPLD/uart_freq_divider.vhd", "target_type": "entity_declaration", "cursor_line": 28, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity uart_freq_divider is\r\n port\r\n (\r\n\t\tdivisor\t: in std_logic_vector(4 downto 0);\t-- Divisor value\r\n clk_in\t: in std_logic;\t\t\t\t\t\t\t-- Clock input\r\n"}
{"file": "fpga_bitcoin_miner/FPGA/sha256d.srcs/sim_1/new/sha256d_tb.vhd", "target_type": "process_statement", "cursor_line": 123, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " elsif rising_edge(clk) then\n count <= count + 1;\n feedback <= '1';\n"}
{"file": "fpga_bitcoin_miner/FPGA/sha256d.srcs/sources_1/bd/soc/hdl/soc_wrapper.vhd", "target_type": "entity_declaration", "cursor_line": 16, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " ARST_AVL_N : out STD_LOGIC_VECTOR ( 0 to 0 );\n CLK_AVL : out STD_LOGIC;\n"}
{"file": "fpga_bitcoin_miner/FPGA/sha256d.srcs/sources_1/new/miner_top.vhd", "target_type": "case_statement", "cursor_line": 238, "target_nlines": 2, "node_depth": 15, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "elsif", "sequence_of_statements", "if_statement", "elsif", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "case_statement"], "target": " srst <= avl_writedata(0);\n when 1 =>\n"}
{"file": "fpga_bitcoin_miner/FPGA/sha256d.srcs/sources_1/new/pulse_cdc.vhd", "target_type": "process_statement", "cursor_line": 43, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " elsif rising_edge(CLK_OUT) then\n toggle_sr <= toggle_sr(toggle_sr'high - 1 downto 0) & toggle;\n end if;\n end process;\n"}
{"file": "fpga_bitcoin_miner/FPGA/sha256d.srcs/sources_1/new/sha256_digester.vhd", "target_type": "entity_declaration", "cursor_line": 13, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity sha256_digester is\n port (\n CLK : in std_logic;\n ARST_N : in std_logic;\n"}
{"file": "fpga_bitcoin_miner/FPGA/sha256d.srcs/sources_1/new/sha256_transform.vhd", "target_type": "process_statement", "cursor_line": 160, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " if (feedback = '0') then\n HASH(C_WORD_SIZE - 1 downto 0) <= std_logic_vector(unsigned(STATE(C_WORD_SIZE - 1 downto 0)) + unsigned(state_out_slv(C_NUM_DIGESTERS - 1)(C_WORD_SIZE - 1 downto 0)));\n HASH(2*C_WORD_SIZE - 1 downto C_WORD_SIZE) <= std_logic_vector(unsigned(STATE(2*C_WORD_SIZE - 1 downto C_WORD_SIZE)) + unsigned(state_out_slv(C_NUM_DIGESTERS - 1)(2*C_WORD_SIZE - 1 downto C_WORD_SIZE)));\n HASH(3*C_WORD_SIZE - 1 downto 2*C_WORD_SIZE) <= std_logic_vector(unsigned(STATE(3*C_WORD_SIZE - 1 downto 2*C_WORD_SIZE)) + unsigned(state_out_slv(C_NUM_DIGESTERS - 1)(3*C_WORD_SIZE - 1 downto 2*C_WORD_SIZE)));\n"}
{"file": "fpga_bitcoin_miner/FPGA/sha256d.srcs/sources_1/new/sha256d_wrapper.vhd", "target_type": "case_statement", "cursor_line": 135, "target_nlines": 1, "node_depth": 12, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "elsif", "sequence_of_statements", "if_statement", "else", "sequence_of_statements", "case_statement"], "target": " if (startup_rounds_count < C_NUM_STARTUP_ROUNDS) then\n"}
{"file": "vic64-t9k/fpga/src/lib/t65/T65.vhd", "target_type": "process_statement", "cursor_line": 415, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " if Inc_S = '1' then\r\n S <= S + 1;\r\n end if;\r\n if Dec_S = '1' and (RstCycle = '0' or Mode = \"00\") then -- Decrement during reset - 6502 only?\r\n"}
{"file": "vic64-t9k/fpga/src/lib/t65/T65_ALU.vhd", "target_type": "case_statement", "cursor_line": 267, "target_nlines": 4, "node_depth": 6, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "case_statement"], "target": " P_Out(Flag_Z) <= '0';\r\n end if;\r\n when ALU_OP_ANC=>\r\n P_Out(Flag_N) <= Q_t(7);\r\n"}
{"file": "vic64-t9k/fpga/src/lib/t65/T65_MCode.vhd", "target_type": "case_statement", "cursor_line": 408, "target_nlines": 4, "node_depth": 12, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "case_statement", "case_statement_alternative", "sequence_of_statements", "case_statement", "case_statement_alternative", "sequence_of_statements", "case_statement"], "target": " when Cycle_1 =>\r\n Jump <= \"01\";\r\n when others =>\r\n end case;\r\n"}
{"file": "vic64-t9k/fpga/src/lib/t65/T65_Pack.vhd", "target_type": "case_statement", "cursor_line": 160, "target_nlines": 5, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "sequence_of_statements", "case_statement"], "target": " return Cycle_1;\r\n when Cycle_1=>\r\n return Cycle_2;\r\n when Cycle_2=>\r\n return Cycle_3;\r\n"}
{"file": "vic64-t9k/fpga/src/lib/vicii/fpga64_rgbcolor.vhd", "target_type": "case_statement", "cursor_line": 50, "target_nlines": 4, "node_depth": 6, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "case_statement"], "target": "\t\twhen X\"C\" => r <= X\"7b\"; g <= X\"7b\"; b <= X\"7b\";\r\n\t\twhen X\"D\" => r <= X\"a9\"; g <= X\"ff\"; b <= X\"9f\";\r\n\t\twhen X\"E\" => r <= X\"70\"; g <= X\"6d\"; b <= X\"eb\";\r\n\t\twhen X\"F\" => r <= X\"b2\"; g <= X\"b2\"; b <= X\"b2\";\r\n"}
{"file": "vic64-t9k/fpga/src/lib/vicii/video_vicII_656x.vhd", "target_type": "process_statement", "cursor_line": 666, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\t\tend if;\n\t\t\t\tif MDMA(2) and (vicCycle = cycleSpriteB) and (sprite = 0) then\n\t\t\t\t\tbaSprite26 <= '0';\n"}
{"file": "vic64-t9k/fpga/src/main/vicii_top.vhd", "target_type": "entity_declaration", "cursor_line": 40, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " r : out unsigned(7 downto 0);\n g : out unsigned(7 downto 0);\n b : out unsigned(7 downto 0);\n"}
{"file": "MicroPET/CPLD/ClockVGA10M.vhd", "target_type": "architecture_body", "cursor_line": 146, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\n\t-- count 6 qclk cycles = ~8 MHz, then transform into clk1m/2m/4m\n\tcpu_cnt1_p: process(reset, cpu_cnt1, memclk_int)\n\tbegin\n"}
{"file": "MicroPET/CPLD/ClockVGA12M.vhd", "target_type": "case_statement", "cursor_line": 163, "target_nlines": 5, "node_depth": 9, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "elsif", "sequence_of_statements", "case_statement"], "target": "\t\t\twhen \"1001\" => \n\t\t\t\tclk4m <= '1';\n\t\t\twhen others =>\n\t\t\t\tnull;\n\t\t\tend case;\n"}
{"file": "MicroPET/CPLD/MapperPET.vhd", "target_type": "architecture_body", "cursor_line": 254, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\t\t\tand petio ='1' else \n\t\t\t'0';\n\t\t\t\n\tffsel <= '0' when avalid='0' else\n\t\t\t'1' when low64k ='1' \n"}
{"file": "MicroPET/CPLD/MapperPET4032.vhd", "target_type": "process_statement", "cursor_line": 122, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\telsif (rising_edge(qclk) and phi2='0') then\n--\t\t\tif (forceb0= '1') then\n--\t\t\t\tbankl <= (others => '0');\n--\t\t\telse\n\t\t\t\tbankl <= D;\n"}
{"file": "MicroPET/CPLD/SPI.vhd", "target_type": "process_statement", "cursor_line": 107, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\t\tDOUT(4) <= cpha;\n\t\t\t\tDOUT(3) <= '0';\n\t\t\t\tDOUT(2 downto 0) <= sel(2 downto 0);\n"}
{"file": "MicroPET/CPLD/Top.vhd", "target_type": "process_statement", "cursor_line": 873, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\telse\n\t\t\t\tif (ipl_cnt = \"111111111111\") then\n\t\t\t\t\tipl_next <= '1';\n"}
{"file": "MicroPET/CPLD/VideoVGA.vhd", "target_type": "process_statement", "cursor_line": 197, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\tvid_p: process(chr40, chr80, pxl40, pxl80, qclk)\n"}
{"file": "MicroPET/CPLD/VideoVGA4032.vhd", "target_type": "process_statement", "cursor_line": 547, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\tvpagelo <= x\"00\";\n\t\telsif (falling_edge(phi2)\n"}
{"file": "PYNQ_softmax/src/softmax_pynq.srcs/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_1/sim/bd_48ac_psr_aclk_0.vhd", "target_type": "architecture_body", "cursor_line": 74, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "ARCHITECTURE bd_48ac_psr_aclk_0_arch OF bd_48ac_psr_aclk_0 IS\n ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;\n"}
{"file": "PYNQ_softmax/src/softmax_pynq.srcs/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_1/synth/bd_48ac_psr_aclk_0.vhd", "target_type": "architecture_body", "cursor_line": 134, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " C_EXT_RESET_HIGH => '0',\n C_AUX_RESET_HIGH => '0',\n C_NUM_BUS_RST => 1,\n C_NUM_PERP_RST => 1,\n"}
{"file": "PYNQ_softmax/src/softmax_pynq.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd", "target_type": "entity_declaration", "cursor_line": 84, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " prmry_resetn : in std_logic ; --\n prmry_in : in std_logic ; --\n"}
{"file": "PYNQ_softmax/src/softmax_pynq.srcs/sources_1/bd/design_1/ipshared/f86a/hdl/proc_sys_reset_v5_0_vh_rfs.vhd", "target_type": "process_statement", "cursor_line": 1096, "target_nlines": 1, "node_depth": 6, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "for_generate_statement", "generate_statement_body", "process_statement"], "target": " asr_lpf(k) <= asr_lpf(k-1);\n"}
{"file": "PYNQ_softmax/src/softmax_pynq.srcs/sources_1/imports/div_pipe_r4_arch2/cond_add.vhd", "target_type": "architecture_body", "cursor_line": 25, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " anAdder: process (sel,op_a,op_b)\n begin\n if sel = '1' then\n outp <= op_a + op_b;\n else\n"}
{"file": "PYNQ_softmax/src/softmax_pynq.srcs/sources_1/imports/div_pipe_r4_arch2/div_r4_pipe.vhd", "target_type": "architecture_body", "cursor_line": 97, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " cell: nr_r4_half_cell port map( op_r => rem_in(i),\n op_y => reg_Y(i), op_3y => reg_3Y(i),\n"}
{"file": "PYNQ_softmax/src/softmax_pynq.srcs/sources_1/imports/div_pipe_r4_arch2/mypack.vhd", "target_type": "constant_declaration", "cursor_line": 7, "target_nlines": 1, "node_depth": 3, "node_path": ["design_file", "package_declaration", "declarative_part", "constant_declaration"], "target": " constant YBITS :INTEGER := 64;\n"}
{"file": "PYNQ_softmax/src/softmax_pynq.srcs/sources_1/imports/div_pipe_r4_arch2/nr_r4_cel.vhd", "target_type": "architecture_body", "cursor_line": 29, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " sr <= op_r(YBITS);\n op_4r <= op_r(YBITS-1 downto 0) & x_1 & x_0; \n"}
{"file": "HDLab-FPGA-Development-Board/Example-Projects/VHDL_Module/DFF/DFF.vhd", "target_type": "entity_declaration", "cursor_line": 35, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " Q: out std_logic_vector(7 downto 0);\r\n clk: in std_logic;\r\n reset: in std_logic;\r\n rx_done_tick : in std_logic );\r\nend DFF;\r\n"}
{"file": "HDLab-FPGA-Development-Board/Example-Projects/VHDL_Module/HEX_TO_SSEG/HEX TO SSEG7.vhd", "target_type": "process_statement", "cursor_line": 59, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "when \"01\" =>\r\nan <= \"1101\";\r\nhex <= hex1;\r\ndp <= dp_in(1);\r\nwhen \"10\" =>\r\n"}
{"file": "HDLab-FPGA-Development-Board/Example-Projects/VHDL_Module/I2C/I2C_CLK.vhd", "target_type": "process_statement", "cursor_line": 39, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "process (clk,reset)\r\nbegin\r\nif(reset= '0')then \r\nr_reg <= (others => '0');\r\nelsif(clk'event and clk='1')then\r\n"}
{"file": "HDLab-FPGA-Development-Board/Example-Projects/VHDL_Module/I2C/I2C_MASTER.vhd", "target_type": "architecture_body", "cursor_line": 200, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "dir_next <= '1';\r\n"}
{"file": "HDLab-FPGA-Development-Board/Example-Projects/VHDL_Module/I2C/I2C_MASTER_MODULE.vhd", "target_type": "entity_declaration", "cursor_line": 35, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "reset_av : out std_logic;\r\nscl : inout std_logic;\r\nsda : inout std_logic;\r\n"}
{"file": "HDLab-FPGA-Development-Board/Example-Projects/VHDL_Module/I2C/bof.vhd", "target_type": "architecture_body", "cursor_line": 40, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "architecture Behavioral of bof is\r\nbegin\r\nbi <= sig_out when dir = '1' else 'Z';\r\nsig_in <= bi; \r\nend Behavioral;\r\n"}
{"file": "HDLab-FPGA-Development-Board/Example-Projects/VHDL_Module/I2C/timer.vhd", "target_type": "entity_declaration", "cursor_line": 5, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity timer is\ngeneric (N:integer :=3);\nPORT(\nclk,reset: in std_logic;\nQ : out std_logic_vector(N-1 downto 0)\n"}
{"file": "HDLab-FPGA-Development-Board/Example-Projects/VHDL_Module/TIMER/TIMER.vhd", "target_type": "entity_declaration", "cursor_line": 7, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "PORT( \r\nclk,reset: in std_logic;\r\n"}
{"file": "HDLab-FPGA-Development-Board/Example-Projects/VHDL_Module/UART/UART.vhd", "target_type": "process_statement", "cursor_line": 187, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\t\trx_clk_en\t<=\t'1';\n\t\t\t\tcounter\t\t:=\t0;\n\t\t\telse\n"}
{"file": "JSON-for-VHDL/examples/Boards0.vhdl", "target_type": "entity_declaration", "cursor_line": 13, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\tClock\t: in\tSTD_LOGIC;\n\t\tReset\t: in\tSTD_LOGIC;\n\t\tLED\t\t: out\tSTD_LOGIC_VECTOR (7 downto 0)\n"}
{"file": "JSON-for-VHDL/examples/Boards1.vhdl", "target_type": "architecture_body", "cursor_line": 37, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\tvariable StringWriter\t\t: T_UINT16;\n"}
{"file": "JSON-for-VHDL/examples/Boards2.vhdl", "target_type": "architecture_body", "cursor_line": 39, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\tjsonStringClear(StringBuffer, StringWriter);\n"}
{"file": "JSON-for-VHDL/examples/Boards_VUnit.vhdl", "target_type": "architecture_body", "cursor_line": 54, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " info(\"RAW generic: \" & tb_cfg);\n if run(\"stringified JSON generic\") then\n"}
{"file": "JSON-for-VHDL/examples/Encodings_VUnit.vhdl", "target_type": "entity_declaration", "cursor_line": 7, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity tb_encodings is\n generic (runner_cfg : string);\nend entity;\n"}
{"file": "JSON-for-VHDL/src/Encodings.pkg.vhdl", "target_type": "variable_declaration", "cursor_line": 31, "target_nlines": 1, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "declarative_part", "variable_declaration"], "target": " variable result: string (1 to str'length * 2);\n"}
{"file": "JSON-for-VHDL/src/JSON.ctx.vhdl", "target_type": "design_file", "cursor_line": 51, "target_nlines": 3, "node_depth": 0, "node_path": ["design_file"], "target": " use JSON.json.jsonIsNumber;\nend context;\n"}
{"file": "JSON-for-VHDL/src/JSON.pkg.vhdl", "target_type": "case_statement", "cursor_line": 1158, "target_nlines": 4, "node_depth": 10, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "sequence_of_statements", "loop_statement", "sequence_of_statements", "case_statement", "case_statement_alternative", "sequence_of_statements", "case_statement"], "target": "\t\t\t\t\t\t\t\tResult.Content(ContentWriter)\t\t\t\t\t:= CurrentChar;\n\t\t\t\t\t\t\twhen 'e' | 'E' =>\n\t\t\t\t\t\t\t\tContentWriter\t\t\t\t\t\t\t\t\t\t\t\t\t:= ContentWriter + 1;\n\t\t\t\t\t\t\t\tResult.Content(ContentWriter)\t\t\t\t\t:= CurrentChar;\n"}
{"file": "JSON-for-VHDL/tests/JSONTestSuite/TopLevel.vhdl", "target_type": "entity_declaration", "cursor_line": 9, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity TopLevel is\nend entity;\n"}
{"file": "PipelineC/examples/arty/arty.srcs/sources_1/ip/ddr3_0/ddr3_0/user_design/rtl/ddr3_0_mig_sim.vhd", "target_type": "signal_declaration", "cursor_line": 1142, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "declarative_part", "signal_declaration"], "target": " signal dbg_bit : std_logic_vector(8 downto 0);\n"}
{"file": "PipelineC/examples/arty/arty.srcs/sources_1/ip/ddr3_0/ddr3_0.vho", "target_type": "component_instantiation_statement", "cursor_line": 151, "target_nlines": 4, "node_depth": 1, "node_path": ["design_file", "component_instantiation_statement"], "target": " app_rd_data_valid => app_rd_data_valid,\n app_rdy => app_rdy,\n app_wdf_rdy => app_wdf_rdy,\n app_sr_req => app_sr_req,\n"}
{"file": "PipelineC/examples/arty/board.vhd", "target_type": "entity_declaration", "cursor_line": 25, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " uart_rxd_out : out std_logic;\n uart_txd_in : in std_logic;\n ja : inout std_logic_vector(7 downto 0);\n jb : inout std_logic_vector(7 downto 0);\n"}
{"file": "PipelineC/examples/aws-fpga-dma/pipelinec_dma_pcis_slv.vhd", "target_type": "process_statement", "cursor_line": 105, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t--\t\tResponse\n\taxi_bid <= o.pcis.write.resp.bid ;\n\taxi_bresp <= o.pcis.write.resp.bresp ;\n\taxi_bvalid <= o.pcis.write.resp.bvalid ;\n\t--\t\tReady\n"}
{"file": "PipelineC/src/vhdl/ieee/ieee_proposed.fixed_float_types.vhdl", "target_type": "package_declaration", "cursor_line": 27, "target_nlines": 3, "node_depth": 1, "node_path": ["design_file", "package_declaration"], "target": " -- and FE_TOWARDZERO floating point rounding macros.\n\n type round_type is (round_nearest, -- Default, nearest LSB '0'\n"}
{"file": "PipelineC/src/vhdl/ieee/ieee_proposed.fixed_pkg.vhdl", "target_type": "case_statement", "cursor_line": 6907, "target_nlines": 4, "node_depth": 6, "node_path": ["design_file", "design_unit", "package_body", "declarative_part", "procedure_body", "sequence_of_statements", "case_statement"], "target": " when others =>\n assert not ISSUE_ERROR\n report fixed_pkg'instance_name\n & \"OREAD Error: Read a '\" & c &\n"}
{"file": "PipelineC/src/vhdl/ieee/ieee_proposed.float_pkg.vhdl", "target_type": "case_statement", "cursor_line": 3866, "target_nlines": 2, "node_depth": 14, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "sequence_of_statements", "if_statement", "else", "sequence_of_statements", "if_statement", "else", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "case_statement"], "target": " when round_neginf =>\n if arg_int /= 0 and result (exponent_width) = '1' then\n"}
{"file": "PipelineC/src/vhdl/pipelinec_async_fifo_fwft.vhd", "target_type": "process_statement", "cursor_line": 184, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "if rising_edge(out_clk) then\n wr_ptr_gray_sync1_reg <= wr_ptr_gray_reg;\n wr_ptr_gray_sync2_reg <= wr_ptr_gray_sync1_reg;\n"}
{"file": "PipelineC/src/vhdl/pipelinec_fifo_fwft.vhd", "target_type": "architecture_body", "cursor_line": 114, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\n pipe_ready <= '1';\n valid_out <= valid_out_pipe;\n"}
{"file": "ZYNQ-PYNQ-Z2-Gobang/repo/my-library/TRNG/sim/trng.vhd", "target_type": "architecture_body", "cursor_line": 55, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " --invertor 2\n inv_lut2: LUT1\n generic map (init => X\"1\")\n port map (\n I0 => delay2,\n"}
{"file": "ZYNQ-PYNQ-Z2-Gobang/repo/my-library/TRNG/src/trng.vhd", "target_type": "entity_declaration", "cursor_line": 11, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity Ring_osc_3 is\n port ( clk : in STD_LOGIC;\n D_out : out STD_LOGIC\n );\nend Ring_osc_3;\n"}
{"file": "ZYNQ-PYNQ-Z2-Gobang/repo/my-library/gobang_1.0/ipshared/67d8/misc/blk_mem_gen_v8_4.vhd", "target_type": "entity_declaration", "cursor_line": 74, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " C_EN_SAFETY_CKT : integer := 0;\n C_DISABLE_WARN_BHV_RANGE : integer := 0;\n C_COUNT_36K_BRAM : string := \"\";\n"}
{"file": "ZYNQ-PYNQ-Z2-Gobang/repo/my-library/gobang_1.0/src/design_gobang_blk_mem_gen_0_0/design_gobang_blk_mem_gen_0_0.vho", "target_type": "component_instantiation_statement", "cursor_line": 71, "target_nlines": 4, "node_depth": 1, "node_path": ["design_file", "component_instantiation_statement"], "target": " clka => clka,\n ena => ena,\n addra => addra,\n douta => douta\n"}
{"file": "ZYNQ-PYNQ-Z2-Gobang/repo/my-library/gobang_1.0/src/design_gobang_blk_mem_gen_0_0/synth/design_gobang_blk_mem_gen_0_0.vhd", "target_type": "entity_declaration", "cursor_line": 61, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " clka : IN STD_LOGIC;\n ena : IN STD_LOGIC;\n addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);\n douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)\n );\n"}
{"file": "ZYNQ-PYNQ-Z2-Gobang/repo/my-library/uart/src/fifo_rx/fifo_rx.vho", "target_type": "component_declaration", "cursor_line": 55, "target_nlines": 3, "node_depth": 1, "node_path": ["design_file", "component_declaration"], "target": "COMPONENT fifo_rx\n PORT (\n clk : IN STD_LOGIC;\n"}
{"file": "ZYNQ-PYNQ-Z2-Gobang/repo/my-library/uart/src/fifo_rx/synth/fifo_rx.vhd", "target_type": "entity_declaration", "cursor_line": 62, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " srst : IN STD_LOGIC;\n din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);\n"}
{"file": "ZYNQ-PYNQ-Z2-Gobang/repo/my-library/uart/src/fifo_tx/fifo_tx.vho", "target_type": "component_instantiation_statement", "cursor_line": 75, "target_nlines": 4, "node_depth": 1, "node_path": ["design_file", "component_instantiation_statement"], "target": " clk => clk,\n srst => srst,\n din => din,\n wr_en => wr_en,\n"}
{"file": "ZYNQ-PYNQ-Z2-Gobang/repo/my-library/uart/src/fifo_tx/synth/fifo_tx.vhd", "target_type": "entity_declaration", "cursor_line": 68, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " empty : OUT STD_LOGIC\n );\n"}
{"file": "boxlambda/gw/ip/dfx_controller/dfx_controller_0.vho", "target_type": "component_declaration", "cursor_line": 55, "target_nlines": 1, "node_depth": 1, "node_path": ["design_file", "component_declaration"], "target": " PORT (\n"}
{"file": "boxlambda/gw/ip/dfx_controller/dfx_controller_0_sim_netlist.vhdl", "target_type": "architecture_body", "cursor_line": 393, "target_nlines": 4, "node_depth": 2, "node_path": ["ERROR", "design_unit", "architecture_body"], "target": " D => \\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.srst_d2\\,\n Q => \\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.srst_d3\\,\n R => '0'\n );\n"}
{"file": "boxlambda/gw/ip/dfx_controller/dfx_controller_0_stub.vhdl", "target_type": "architecture_body", "cursor_line": 70, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "attribute syn_black_box of stub : architecture is true;\n"}
{"file": "boxlambda/gw/ip/dfx_controller/hdl/lib_cdc_v1_0_rfs.vhd", "target_type": "entity_declaration", "cursor_line": 87, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " (C_VECTOR_WIDTH - 1 downto 0) ; --\n prmry_ack : out std_logic ;\n --\n"}
{"file": "boxlambda/gw/ip/dfx_controller/hdl/lib_pkg_v1_0_rfs.vhd", "target_type": "variable_declaration", "cursor_line": 269, "target_nlines": 1, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "declarative_part", "variable_declaration"], "target": " variable i : integer := 0; \n"}
{"file": "boxlambda/gw/ip/dfx_controller/hdl/lib_srl_fifo_v1_0_rfs.vhd", "target_type": "architecture_body", "cursor_line": 1020, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " FIFO_Read => FIFO_Read,\n Data_Out => Data_Out,\n FIFO_Full => FIFO_Full,\n FIFO_Empty => FIFO_Empty,\n Addr => Addr,\n"}
{"file": "boxlambda/gw/ip/dfx_controller/sim/dfx_controller_0.vhd", "target_type": "entity_declaration", "cursor_line": 95, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " s_axi_reg_bready : IN STD_LOGIC;\n"}
{"file": "boxlambda/gw/ip/dfx_controller/synth/dfx_controller_0.vhd", "target_type": "architecture_body", "cursor_line": 185, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " ATTRIBUTE X_INTERFACE_INFO OF m_axi_mem_arprot: SIGNAL IS \"xilinx.com:interface:aximm:1.0 M_AXI_MEM ARPROT\";\n ATTRIBUTE X_INTERFACE_INFO OF m_axi_mem_arready: SIGNAL IS \"xilinx.com:interface:aximm:1.0 M_AXI_MEM ARREADY\";\n ATTRIBUTE X_INTERFACE_INFO OF m_axi_mem_arsize: SIGNAL IS \"xilinx.com:interface:aximm:1.0 M_AXI_MEM ARSIZE\";\n ATTRIBUTE X_INTERFACE_INFO OF m_axi_mem_aruser: SIGNAL IS \"xilinx.com:interface:aximm:1.0 M_AXI_MEM ARUSER\";\n ATTRIBUTE X_INTERFACE_INFO OF m_axi_mem_arvalid: SIGNAL IS \"xilinx.com:interface:aximm:1.0 M_AXI_MEM ARVALID\";\n"}
{"file": "boxlambda/gw/ip/ila/ila_0_stub.vhdl", "target_type": "entity_declaration", "cursor_line": 16, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " Port ( \n clk : in STD_LOGIC;\n"}
{"file": "vhdl-hdmi-out/rtl/clock_gen.vhd", "target_type": "entity_declaration", "cursor_line": 23, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " );\nend clock_gen;\n"}
{"file": "vhdl-hdmi-out/rtl/hdmi_out.vhd", "target_type": "entity_declaration", "cursor_line": 16, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " RESOLUTION : string := \"HD1080P\"; -- HD1080P, HD720P, SVGA, VGA\n GEN_PATTERN : boolean := false; -- generate pattern or objects\n GEN_PIX_LOC : boolean := true; -- generate location counters for x / y coordinates\n OBJECT_SIZE : natural := 16; -- size of the objects. should be higher than 11\n"}
{"file": "vhdl-hdmi-out/rtl/objectbuffer.vhd", "target_type": "process_statement", "cursor_line": 118, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " rgb <= wall_rgb;\n elsif ball_on='1' then\n rgb <= ball_rgb;\n elsif box_on='1' then\n"}
{"file": "vhdl-hdmi-out/rtl/pattern_generator.vhd", "target_type": "process_statement", "cursor_line": 33, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " case state is\n when s0 =>\n"}
{"file": "vhdl-hdmi-out/rtl/rgb2tmds.vhd", "target_type": "entity_declaration", "cursor_line": 11, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " );\n port(\n -- reset and clocks\n"}
{"file": "vhdl-hdmi-out/rtl/serializer.vhd", "target_type": "architecture_body", "cursor_line": 116, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "-- OSERDESE2 is an encrypted IP, so convert that to\n-- OSERDESE1 (6-series serdes)\nfors6: if SERIES6 = true generate\n"}
{"file": "vhdl-hdmi-out/rtl/timing_generator.vhd", "target_type": "architecture_body", "cursor_line": 85, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " H_POL => '1',\n V_POL => '1',\n ACTIVE => '1'\n );\n\n"}
{"file": "vhdl-hdmi-out/rtl/tmds_encoder.vhd", "target_type": "process_statement", "cursor_line": 38, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " if din(i) = '1' then\n c := c + 1;\n end if;\n"}
{"file": "vhdl-hdmi-out/sim/tb_hdmi_out.vhd", "target_type": "process_statement", "cursor_line": 50, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " wait for clk_period/2;\n clk <= not clk;\n --end loop;\n"}
{"file": "FPGA-OV2640/FPGA-cameral/FPGA-cameral.ip_user_files/ip/blk_mem_gen_0/blk_mem_gen_0.vho", "target_type": "component_declaration", "cursor_line": 63, "target_nlines": 5, "node_depth": 1, "node_path": ["design_file", "component_declaration"], "target": " enb : IN STD_LOGIC;\n addrb : IN STD_LOGIC_VECTOR(18 DOWNTO 0);\n doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)\n );\nEND COMPONENT;\n"}
{"file": "FPGA-OV2640/FPGA-cameral/FPGA-cameral.ip_user_files/ip/blk_mem_gen_0/blk_mem_gen_0_stub.vhdl", "target_type": "entity_declaration", "cursor_line": 24, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " addrb : in STD_LOGIC_VECTOR ( 18 downto 0 );\n doutb : out STD_LOGIC_VECTOR ( 11 downto 0 )\n );\n\n"}
{"file": "FPGA-OV2640/FPGA-cameral/FPGA-cameral.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl", "target_type": "architecture_body", "cursor_line": 24, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "architecture stub of clk_wiz_0 is\n"}
{"file": "FPGA-OV2640/FPGA-cameral/FPGA-cameral.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0.vho", "target_type": "component_declaration", "cursor_line": 60, "target_nlines": 3, "node_depth": 1, "node_path": ["design_file", "component_declaration"], "target": " addra : IN STD_LOGIC_VECTOR(18 DOWNTO 0);\n dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);\n clkb : IN STD_LOGIC;\n"}
{"file": "FPGA-OV2640/FPGA-cameral/FPGA-cameral.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0_sim_netlist.vhdl", "target_type": "architecture_body", "cursor_line": 33229, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " enb => enb,\n"}
{"file": "FPGA-OV2640/FPGA-cameral/FPGA-cameral.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0_stub.vhdl", "target_type": "entity_declaration", "cursor_line": 22, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " clkb : in STD_LOGIC;\n enb : in STD_LOGIC;\n addrb : in STD_LOGIC_VECTOR ( 18 downto 0 );\n"}
{"file": "FPGA-OV2640/FPGA-cameral/FPGA-cameral.srcs/sources_1/ip/blk_mem_gen_0/misc/blk_mem_gen_v8_3.vhd", "target_type": "entity_declaration", "cursor_line": 74, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " C_EN_SAFETY_CKT : integer := 0;\n"}
{"file": "FPGA-OV2640/FPGA-cameral/FPGA-cameral.srcs/sources_1/ip/blk_mem_gen_0/synth/blk_mem_gen_0.vhd", "target_type": "architecture_body", "cursor_line": 284, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " C_READ_WIDTH_B => 12,\n C_WRITE_DEPTH_B => 307200,\n C_READ_DEPTH_B => 307200,\n C_ADDRB_WIDTH => 19,\n C_HAS_MEM_OUTPUT_REGS_A => 0,\n"}
{"file": "FPGA-OV2640/FPGA-cameral/FPGA-cameral.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl", "target_type": "architecture_body", "cursor_line": 41, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;\n signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;\n"}
{"file": "FPGA-OV2640/FPGA-cameral/FPGA-cameral.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl", "target_type": "entity_declaration", "cursor_line": 15, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity clk_wiz_0 is\n Port ( \n clk_in1 : in STD_LOGIC;\n clk_out1 : out STD_LOGIC;\n clk_out2 : out STD_LOGIC\n"}
{"file": "LibreSDRB210/LibreSDR/libresdr_b210.gen/fifo_4k_2clk/ip/fifo_4k_2clk/fifo_4k_2clk_sim_netlist.vhdl", "target_type": "architecture_body", "cursor_line": 1227, "target_nlines": 1, "node_depth": 2, "node_path": ["ERROR", "design_unit", "architecture_body"], "target": " D => syncstages_ff(2),\n"}
{"file": "LibreSDRB210/LibreSDR/libresdr_b210.gen/fifo_4k_2clk/ip/fifo_4k_2clk/fifo_4k_2clk_stub.vhdl", "target_type": "architecture_body", "cursor_line": 40, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "attribute x_core_info : string;\nattribute x_core_info of stub : architecture is \"fifo_generator_v13_2_10,Vivado 2024.1\";\nbegin\n"}
{"file": "LibreSDRB210/LibreSDR/libresdr_b210.gen/fifo_4k_2clk/ip/fifo_4k_2clk/synth/fifo_4k_2clk.vhd", "target_type": "entity_declaration", "cursor_line": 63, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " rd_clk : IN STD_LOGIC;\n"}
{"file": "LibreSDRB210/LibreSDR/libresdr_b210.gen/fifo_short_2clk/ip/fifo_short_2clk/fifo_short_2clk_sim_netlist.vhdl", "target_type": "architecture_body", "cursor_line": 73, "target_nlines": 3, "node_depth": 2, "node_path": ["ERROR", "design_unit", "architecture_body"], "target": " PRE => src_arst,\n Q => arststages_ff(0)\n );\n"}
{"file": "LibreSDRB210/LibreSDR/libresdr_b210.gen/fifo_short_2clk/ip/fifo_short_2clk/fifo_short_2clk_stub.vhdl", "target_type": "entity_declaration", "cursor_line": 29, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " );\n\nend fifo_short_2clk;\n"}
{"file": "LibreSDRB210/LibreSDR/libresdr_b210.gen/fifo_short_2clk/ip/fifo_short_2clk/synth/fifo_short_2clk.vhd", "target_type": "entity_declaration", "cursor_line": 67, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);\n full : OUT STD_LOGIC;\n empty : OUT STD_LOGIC;\n rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);\n"}
{"file": "LibreSDRB210/LibreSDR/libresdr_b210.gen/gen_clks/ip/gen_clks/gen_clks_sim_netlist.vhdl", "target_type": "architecture_body", "cursor_line": 76, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " );\nclkout1_buf: unisim.vcomponents.BUFG\n port map (\n"}
{"file": "LibreSDRB210/LibreSDR/libresdr_b210.gen/gen_clks/ip/gen_clks/gen_clks_stub.vhdl", "target_type": "entity_declaration", "cursor_line": 22, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " locked : out STD_LOGIC;\n"}
{"file": "LibreSDRB210/LibreSDR/libresdr_b210.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl", "target_type": "entity_declaration", "cursor_line": 153, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " port (\n clk_out_200M : out STD_LOGIC;\n locked : out STD_LOGIC;\n"}
{"file": "LibreSDRB210/LibreSDR/libresdr_b210.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl", "target_type": "entity_declaration", "cursor_line": 19, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " locked : out STD_LOGIC;\n clk_in1_10M : in STD_LOGIC\n );\n"}
{"file": "ZYNQ7010-7020_AD9363/firmware/source project/pluto-7010clg400-user-ip/pluto/pluto.srcs/sources_1/bd/system/ip/system_axi_iic_main_0/synth/system_axi_iic_main_0.vhd", "target_type": "architecture_body", "cursor_line": 154, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\";\n"}
{"file": "ZYNQ7010-7020_AD9363/firmware/source project/pluto-7010clg400-user-ip/pluto/pluto.srcs/sources_1/bd/system/ip/system_fir_decimator_0/util_fir_dec.srcs/sources_1/ip/fir_decim/synth/fir_decim.vhd", "target_type": "entity_declaration", "cursor_line": 59, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "ENTITY fir_decim IS\n"}
{"file": "ZYNQ7010-7020_AD9363/firmware/source project/pluto-7010clg400-user-ip/pluto/pluto.srcs/sources_1/bd/system/ip/system_fir_interpolator_0/util_fir_int.srcs/sources_1/ip/fir_interp/synth/fir_interp.vhd", "target_type": "architecture_body", "cursor_line": 85, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " C_NUM_FILTS : INTEGER;\n C_NUM_TAPS : INTEGER;\n"}
{"file": "ZYNQ7010-7020_AD9363/firmware/source project/pluto-7010clg400-user-ip/pluto/pluto.srcs/sources_1/bd/system/ip/system_sys_rstgen_0/synth/system_sys_rstgen_0.vhd", "target_type": "entity_declaration", "cursor_line": 72, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "END system_sys_rstgen_0;\n"}
{"file": "ZYNQ7010-7020_AD9363/firmware/source project/pluto-7010clg400-user-ip/pluto/pluto.srcs/sources_1/bd/system/ipshared/0513/hdl/lib_pkg_v1_0_rfs.vhd", "target_type": "variable_declaration", "cursor_line": 329, "target_nlines": 1, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "declarative_part", "variable_declaration"], "target": " variable abs_int : natural;\n"}
{"file": "ZYNQ7010-7020_AD9363/firmware/source project/pluto-7010clg400-user-ip/pluto/pluto.srcs/sources_1/bd/system/ipshared/304c/hdl/axi_iic_v2_0_vh_rfs.vhd", "target_type": "process_statement", "cursor_line": 4734, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " or tx_under_prev_i = '1' then\n"}
{"file": "ZYNQ7010-7020_AD9363/firmware/source project/pluto-7010clg400-user-ip/pluto/pluto.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd", "target_type": "process_statement", "cursor_line": 2575, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\t end if;\n\n when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or\n"}
{"file": "ZYNQ7010-7020_AD9363/firmware/source project/pluto-7010clg400-user-ip/pluto/pluto.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd", "target_type": "process_statement", "cursor_line": 518, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " if (Lpf_reset = '1') then\n core <= '1';\n"}
{"file": "ZYNQ7010-7020_AD9363/firmware/source project/pluto-7010clg400-user-ip/pluto/pluto.srcs/sources_1/bd/system/ipshared/a040/hdl/interrupt_control_v3_1_vh_rfs.vhd", "target_type": "process_statement", "cursor_line": 1160, "target_nlines": 4, "node_depth": 7, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "if_generate_statement", "if_generate", "generate_statement_body", "process_statement"], "target": " ipif_interrupt_PROCESS: process(ip_interrupt_or, ipif_glbl_irpt_enable_reg)\n begin\n ipif_interrupt <= ip_interrupt_or and ipif_glbl_irpt_enable_reg;\n end process ipif_interrupt_PROCESS;\n"}
{"file": "ZYNQ7010-7020_AD9363/firmware/source project/pluto-7010clg400-user-ip/pluto/pluto.srcs/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd", "target_type": "entity_declaration", "cursor_line": 85, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " prmry_in : in std_logic ; --\n prmry_vect_in : in std_logic_vector --\n (C_VECTOR_WIDTH - 1 downto 0) ; --\n"}
{"file": "forth-cpu/core.vhd", "target_type": "process_statement", "cursor_line": 295, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\tvariable addr_n: std_ulogic_vector(addr'range) := (others => '0');\n\tbegin\n\t\taddr_n := priority(irc_n, not lowest_interrupt_first);\n\t\taddr_o <= addr_n after g.delay;\n\t\tif select_bit(mask_n, addr_n) = '1' then\n"}
{"file": "forth-cpu/h2.vhd", "target_type": "process_statement", "cursor_line": 239, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\tend if;\n\t\tend if;\n\tend process;\n"}
{"file": "forth-cpu/kbd.vhd", "target_type": "entity_declaration", "cursor_line": 492, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\tps2_data: in std_ulogic; -- data signal from PS/2 keyboard\n\t\tps2_code_new: out std_ulogic; -- flag that new PS/2 code is available on ps2_code bus\n\t\tps2_code: out std_ulogic_vector(7 downto 0)); -- code received from PS/2\nend entity;\n"}
{"file": "forth-cpu/ram.vhd", "target_type": "architecture_body", "cursor_line": 104, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\tport map(\n\t\t\tclk => clk,\n\t\t\trst => rst,\n\t\t\twe => mem_data_i_we,\n"}
{"file": "forth-cpu/tb.vhd", "target_type": "process_statement", "cursor_line": 228, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\treport \"clk_process end\";\n\t\twait;\n\tend process;\n"}
{"file": "forth-cpu/timer.vhd", "target_type": "process_statement", "cursor_line": 101, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\tif count = unsigned(compare) and enabled = '1' then\n"}
{"file": "forth-cpu/top.vhd", "target_type": "entity_declaration", "cursor_line": 39, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\tbtnc: in std_ulogic := 'X'; -- button centre\n\t\tbtnl: in std_ulogic := 'X'; -- button left\n"}
{"file": "forth-cpu/uart.vhd", "target_type": "entity_declaration", "cursor_line": 689, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity uart_tx is\n\tgeneric (g: common_generics; N: positive; format: std_ulogic_vector(7 downto 0) := uart_8N1);\n"}
{"file": "forth-cpu/util.vhd", "target_type": "process_statement", "cursor_line": 3676, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\tduration: process begin wait for simulation_us; stop <= true; wait; end process;\n"}
{"file": "forth-cpu/vga.vhd", "target_type": "entity_declaration", "cursor_line": 1438, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\tload: in std_ulogic;\n\t\tce: in std_ulogic;\n\t\tdo: out std_ulogic := '0';\n\t\tdi: in std_ulogic_vector(N - 1 downto 0));\nend entity;\n"}
{"file": "muhammadaldacher/MSc_Courses_SJSU/EE178 - Digital Design with FPGA/LABs _ Project/LAB6_Line Drawing Algorithm/lab6.srcs/sources_1/ip/framebuffer/framebuffer.vho", "target_type": "component_instantiation_statement", "cursor_line": 81, "target_nlines": 4, "node_depth": 1, "node_path": ["design_file", "component_instantiation_statement"], "target": " douta => douta,\n clkb => clkb,\n web => web,\n addrb => addrb,\n"}
{"file": "muhammadaldacher/MSc_Courses_SJSU/EE178 - Digital Design with FPGA/LABs _ Project/LAB6_Line Drawing Algorithm/lab6.srcs/sources_1/ip/framebuffer/framebuffer_sim_netlist.vhdl", "target_type": "architecture_body", "cursor_line": 1371, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " INIT_19 => X\"0000000000000000000000000000000000000000000000000000000000000000\",\n INIT_1A => X\"0000000000000000000000000000000000000000000000000000000000000000\",\n INIT_1B => X\"0000000000000000000000000000000000000000000000000000000000000000\",\n INIT_1C => X\"0000000000000000000000000000000000000000000000000000000000000000\",\n INIT_1D => X\"0000000000000000000000000000000000000000000000000000000000000000\",\n"}
{"file": "muhammadaldacher/MSc_Courses_SJSU/EE178 - Digital Design with FPGA/LABs _ Project/LAB6_Line Drawing Algorithm/lab6.srcs/sources_1/ip/framebuffer/framebuffer_stub.vhdl", "target_type": "architecture_body", "cursor_line": 35, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "attribute black_box_pad_pin of stub : architecture is \"clka,wea[0:0],addra[15:0],dina[3:0],douta[3:0],clkb,web[0:0],addrb[14:0],dinb[7:0],doutb[7:0]\";\r\nattribute x_core_info : string;\r\nattribute x_core_info of stub : architecture is \"blk_mem_gen_v8_3_3,Vivado 2016.2\";\r\nbegin\r\nend;\r\n"}
{"file": "muhammadaldacher/MSc_Courses_SJSU/EE178 - Digital Design with FPGA/LABs _ Project/LAB6_Line Drawing Algorithm/lab6.srcs/sources_1/ip/framebuffer/misc/blk_mem_gen_v8_3.vhd", "target_type": "architecture_body", "cursor_line": 147, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "architecture xilinx of blk_mem_gen_v8_3_3 is\n begin\n end \narchitecture xilinx;\n"}
{"file": "muhammadaldacher/MSc_Courses_SJSU/EE178 - Digital Design with FPGA/LABs _ Project/LAB6_Line Drawing Algorithm/lab6.srcs/sources_1/ip/framebuffer/synth/framebuffer.vhd", "target_type": "entity_declaration", "cursor_line": 66, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " clkb : IN STD_LOGIC;\n web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);\n addrb : IN STD_LOGIC_VECTOR(14 DOWNTO 0);\n dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);\n doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)\n"}
{"file": "muhammadaldacher/MSc_Courses_SJSU/EE178 - Digital Design with FPGA/LABs _ Project/LAB8_Digital Analog Clock Project/EE178_FinalProject.srcs/sources_1/ip/framebuffer/framebuffer.vho", "target_type": "design_file", "cursor_line": 73, "target_nlines": 3, "node_depth": 0, "node_path": ["design_file"], "target": "\n------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\nyour_instance_name : framebuffer\n"}
{"file": "muhammadaldacher/MSc_Courses_SJSU/EE178 - Digital Design with FPGA/LABs _ Project/LAB8_Digital Analog Clock Project/EE178_FinalProject.srcs/sources_1/ip/framebuffer/framebuffer_sim_netlist.vhdl", "target_type": "architecture_body", "cursor_line": 2425, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\\prim_noinit.ram\\: entity work.\\framebuffer_blk_mem_gen_prim_wrapper__parameterized0\\\n port map (\n DOADO(0) => DOADO(0),\n DOBDO(1 downto 0) => DOBDO(1 downto 0),\n"}
{"file": "muhammadaldacher/MSc_Courses_SJSU/EE178 - Digital Design with FPGA/LABs _ Project/LAB8_Digital Analog Clock Project/EE178_FinalProject.srcs/sources_1/ip/framebuffer/framebuffer_stub.vhdl", "target_type": "entity_declaration", "cursor_line": 25, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );\r\n doutb : out STD_LOGIC_VECTOR ( 7 downto 0 )\r\n );\r\n\r\n"}
{"file": "muhammadaldacher/MSc_Courses_SJSU/EE178 - Digital Design with FPGA/LABs _ Project/LAB8_Digital Analog Clock Project/EE178_FinalProject.srcs/sources_1/ip/framebuffer/misc/blk_mem_gen_v8_3.vhd", "target_type": "architecture_body", "cursor_line": 147, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "architecture xilinx of blk_mem_gen_v8_3_3 is\n begin\n end \narchitecture xilinx;\n"}
{"file": "muhammadaldacher/MSc_Courses_SJSU/EE178 - Digital Design with FPGA/LABs _ Project/LAB8_Digital Analog Clock Project/EE178_FinalProject.srcs/sources_1/ip/framebuffer/synth/framebuffer.vhd", "target_type": "architecture_body", "cursor_line": 132, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;\n C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;\n C_USE_SOFTECC : INTEGER;\n"}
{"file": "spi-fpga/examples/common/btn_debounce.vhd", "target_type": "process_statement", "cursor_line": 59, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " if (SAMPLE_EN = '1') then\n btn_raw_sample_reg <= btn_raw_sync_reg2; \n end if;\n end if;\n"}
{"file": "spi-fpga/examples/common/clk_en_gen.vhd", "target_type": "process_statement", "cursor_line": 61, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " clk_en_1k_reg <= '0';\n elsif (rising_edge(CLK)) then\n clk_en_1k_reg <= clk_en_1k_comb;\n end if;\n end process;\n"}
{"file": "spi-fpga/examples/common/rst_sync.vhd", "target_type": "architecture_body", "cursor_line": 32, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " attribute PRESERVE of meta_reg : signal is TRUE;\n attribute PRESERVE of reset_reg : signal is TRUE;\n\nbegin\n"}
{"file": "spi-fpga/examples/common/sseg_driver.vhd", "target_type": "case_statement", "cursor_line": 70, "target_nlines": 2, "node_depth": 6, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "case_statement"], "target": " sseg_dp <= not DOTS(2);\n sseg_anode <= \"1011\";\n"}
{"file": "spi-fpga/examples/loopback/spi_loopback.vhd", "target_type": "process_statement", "cursor_line": 265, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " s_dout_reg_p : process (CLK, reset)\n begin\n if (reset = '1') then\n s_dout_reg <= (others => '0');\n"}
{"file": "spi-fpga/examples/spirit_level/spirit_level_cyc1000.vhd", "target_type": "architecture_body", "cursor_line": 49, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " rst_btn <= not RST_BTN_N;\n\n rst_sync_i : entity work.RST_SYNC\n"}
{"file": "spi-fpga/rtl/spi_master.vhd", "target_type": "case_statement", "cursor_line": 328, "target_nlines": 3, "node_depth": 6, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "case_statement"], "target": " second_edge_en <= '0';\n rx_data_vld <= '0';\n\n"}
{"file": "spi-fpga/rtl/spi_slave.vhd", "target_type": "architecture_body", "cursor_line": 125, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " bit_cnt_max <= '1' when (bit_cnt = WORD_SIZE-1) else '0';\n\n -- -------------------------------------------------------------------------\n -- LAST BIT FLAG REGISTER\n -- -------------------------------------------------------------------------\n"}
{"file": "spi-fpga/sim/spi_master_tb.vhd", "target_type": "process_statement", "cursor_line": 114, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " clk_gen_p : process\n begin\n CLK <= '0';\n wait for CLK_PERIOD/2;\n CLK <= '1';\n"}
{"file": "spi-fpga/sim/spi_slave_tb.vhd", "target_type": "process_statement", "cursor_line": 216, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " if (v_test_done = '1') then\n wait for 100*CLK_PERIOD;\n sim_done <= '1';\n report \"======== SIMULATION SUCCESSFULLY COMPLETED! ========\";\n wait;\n"}
{"file": "MandelbrotInVHDL/FPGA-VHDL/Example3.vhd", "target_type": "entity_declaration", "cursor_line": 19, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " USB_StreamSLWR_n : out std_logic;\n USB_StreamFX2Rdy : in std_logic;\n USB_StreamData : inout std_logic_vector(15 downto 0);\n"}
{"file": "MandelbrotInVHDL/FPGA-VHDL/Mandelbrot.vhd", "target_type": "process_statement", "cursor_line": 396, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " output_offset <= (others => '0');\n output_number <= X\"00\";\n elsif rising_edge(clk) then\n -- In the previous phase, we've set the 'overflow' flag.\n"}
{"file": "MandelbrotInVHDL/FPGA-VHDL/MyTypes.vhd", "target_type": "constant_declaration", "cursor_line": 16, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "constant_declaration"], "target": " constant integerPart : integer := 6;\n"}
{"file": "MandelbrotInVHDL/FPGA-VHDL/pipeline_types.vhd", "target_type": "constant_declaration", "cursor_line": 12, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "constant_declaration"], "target": " constant depth : integer := 7;\n"}
{"file": "MandelbrotInVHDL/FPGA-VHDL/testFinallyWorks.vhd", "target_type": "process_statement", "cursor_line": 158, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\tUSB_StreamCLK <= '0';\n\t\twait for USB_StreamCLK_period/2;\n\t\tUSB_StreamCLK <= '1';\n\t\twait for USB_StreamCLK_period/2;\n end process;\n"}
{"file": "MandelbrotInVHDL/GHDL/src/custom_fixed_point_types.vhdl", "target_type": "constant_declaration", "cursor_line": 13, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "constant_declaration"], "target": " constant integerPart : integer := 6;\n"}
{"file": "MandelbrotInVHDL/GHDL/src/mandelbrot.vhdl", "target_type": "process_statement", "cursor_line": 411, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " -- (2xy)\n XYpXY_reg <= resize(scalb(XY_reg, 1), XYpXY_reg);\n\n -- Debugging the computations.\n -- if is_used_slot(2) = '1' then\n"}
{"file": "MandelbrotInVHDL/GHDL/src/pipeline_types.vhdl", "target_type": "subtype_declaration", "cursor_line": 19, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "subtype_declaration"], "target": " subtype iterations is unsigned(7 downto 0);\n"}
{"file": "MandelbrotInVHDL/GHDL/tb/mandel_tb.vhdl", "target_type": "entity_declaration", "cursor_line": 14, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity mandel_tb is\nend mandel_tb;\n"}
{"file": "MandelbrotInVHDL/ieee_proposed/fixed_float_types_c.vhd", "target_type": "package_declaration", "cursor_line": 20, "target_nlines": 4, "node_depth": 1, "node_path": ["design_file", "package_declaration"], "target": " type fixed_round_style_type is (fixed_round, fixed_truncate);\n \n type fixed_overflow_style_type is (fixed_saturate, fixed_wrap);\n\n"}
{"file": "MandelbrotInVHDL/ieee_proposed/fixed_pkg_c.vhd", "target_type": "case_statement", "cursor_line": 6893, "target_nlines": 3, "node_depth": 6, "node_path": ["design_file", "design_unit", "package_body", "declarative_part", "procedure_body", "sequence_of_statements", "case_statement"], "target": " assert not ISSUE_ERROR\n report fixed_pkg'instance_name\n & \"OREAD Error: Read a '\" & c &\n"}
{"file": "NN_RGB_FPGA/FPGA_generate/config.vhd", "target_type": "constant_declaration", "cursor_line": 16, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "constant_declaration"], "target": "\tconstant connnectionRange : constIntArray (3 downto 0) := (12,10,3,0);\n"}
{"file": "NN_RGB_FPGA/FPGA_generate/control.vhd", "target_type": "architecture_body", "cursor_line": 22, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "architecture behave of control is\r\n\r\n\r\n type delay_array is array (1 to delay) of std_logic;\r\n"}
{"file": "NN_RGB_FPGA/FPGA_generate/multiplier.vhd", "target_type": "architecture_body", "cursor_line": 29, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "end behave;"}
{"file": "NN_RGB_FPGA/FPGA_generate/neuron.vhd", "target_type": "entity_declaration", "cursor_line": 14, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " port ( clk : in std_logic;\n\t\t\t\tinputsIn : in input;\n\t\t\t\toutput : out integer range 0 to 255);\n"}
{"file": "NN_RGB_FPGA/FPGA_generate/nn_rgb.vhd", "target_type": "entity_declaration", "cursor_line": 35, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " clk_o : out std_logic; -- output clock (do not modify)\r\n led : out std_logic_vector(2 downto 0)); -- not supported by remote lab\r\nend nn_rgb;\r\n"}
{"file": "NN_RGB_FPGA/FPGA_generate/sigmoid_IP.vhd", "target_type": "entity_declaration", "cursor_line": 45, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t(\n\t\taddress\t\t: IN STD_LOGIC_VECTOR (11 DOWNTO 0);\n\t\tclock\t\t: IN STD_LOGIC := '1';\n"}
{"file": "NN_RGB_FPGA/FPGA_plain/control.vhd", "target_type": "architecture_body", "cursor_line": 26, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " signal vs_delay : delay_array;\r\n signal hs_delay : delay_array;\r\n signal de_delay : delay_array;\r\n\r\n"}
{"file": "NN_RGB_FPGA/FPGA_plain/neuron.vhd", "target_type": "entity_declaration", "cursor_line": 12, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " w2 : integer;\n w3 : integer;\n"}
{"file": "NN_RGB_FPGA/FPGA_plain/nn_rgb.vhd", "target_type": "entity_declaration", "cursor_line": 17, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " enable_in : in std_logic_vector(2 downto 0); -- three slide switches\r\n -- video in\r\n"}
{"file": "NN_RGB_FPGA/FPGA_plain/sigmoid_IP.vhd", "target_type": "entity_declaration", "cursor_line": 48, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\tq\t\t: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)\r\n\t);\r\n"}
{"file": "NN_RGB_FPGA/FPGA_plain/sim_nn_rgb.vhd", "target_type": "process_statement", "cursor_line": 190, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " write (l_sim, y_size);\n writeline(response_file, l_sim); \n write (l_sim, string'(\"255\")); -- maximum value\n writeline(response_file, l_sim); \n \n"}
{"file": "SiaFpgaMiner/Blake2bMinerCore.vhd", "target_type": "architecture_body", "cursor_line": 155, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " C1_in(0)(2) <= kIV(2); -- V10\r\n C1_in(0)(3) <= kIV(3); -- V11\r\n D1_in(0)(0) <= kIV(4) xor (x\"00000000000000\" & kMsgLen); -- V12\r\n D1_in(0)(1) <= kIV(5); -- V13\r\n"}
{"file": "SiaFpgaMiner/Example/Clocking_K7.vhd", "target_type": "architecture_body", "cursor_line": 47, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " CLKFBOUT_PHASE : real := 0.0;\n REF_JITTER1 : real := 0.100;\n"}
{"file": "SiaFpgaMiner/Example/SiaMinerUart.vhd", "target_type": "entity_declaration", "cursor_line": 20, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " aRun : in std_logic;\r\n"}
{"file": "SiaFpgaMiner/Example/SiaMinerUart_tb.vhd", "target_type": "entity_declaration", "cursor_line": 10, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity SiaMinerUart_tb is end SiaMinerUart_tb;\n"}
{"file": "SiaFpgaMiner/Example/UartGetWork.vhd", "target_type": "process_statement", "cursor_line": 159, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " txState <= LoadByte;\n"}
{"file": "SiaFpgaMiner/MixG_FlopPipe_4.vhd", "target_type": "process_statement", "cursor_line": 71, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\n -- These last FIFO flops could be implemented outside for flexibility\n -- (consider last round). There is no B because it is buffered in by\n -- the next MixG on the pipeline.\n A3 <= A2;\n"}
{"file": "SiaFpgaMiner/PkgBlake2b.vhd", "target_type": "constant_declaration", "cursor_line": 14, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "constant_declaration"], "target": " constant kHashLen : unsigned(7 downto 0) := x\"20\"; -- 32 bytes\r\n"}
{"file": "SiaFpgaMiner/QuadG.vhd", "target_type": "entity_declaration", "cursor_line": 17, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " A_in : in U64Array_t(3 downto 0);\r\n B_in : in U64Array_t(3 downto 0);\r\n C_in : in U64Array_t(3 downto 0);\r\n"}
{"file": "SiaFpgaMiner/Testbench/Blake2bMinerCore_tb.vhd", "target_type": "entity_declaration", "cursor_line": 12, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity SiaMinerPiped_tb is\n generic (runner_cfg : string);\nend SiaMinerPiped_tb;\n"}
{"file": "SiaFpgaMiner/Testbench/MixG_tb.vhd", "target_type": "entity_declaration", "cursor_line": 9, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity MixG_tb is end MixG_tb;\n"}
{"file": "SiaFpgaMiner/Testbench/PkgTestVectors.vhd", "target_type": "constant_declaration", "cursor_line": 64, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "constant_declaration"], "target": " constant kStdTestNonce : unsigned(63 downto 0) := x\"0000000000000000\";\n"}
{"file": "openfpga-asteroids/src/fpga/core/rtl/T65.vhd", "target_type": "case_statement", "cursor_line": 367, "target_nlines": 3, "node_depth": 18, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "case_statement"], "target": "\t\t\t\t\t\tP(Flag_D) <= '0';\n\t\t\t\t\twhen \"111\" =>\n\t\t\t\t\t\tP(Flag_D) <= '1';\n"}
{"file": "openfpga-asteroids/src/fpga/core/rtl/T65_ALU.vhd", "target_type": "case_statement", "cursor_line": 215, "target_nlines": 3, "node_depth": 6, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "case_statement"], "target": "\t\t\tQ_t := \"0\" & BusA(7 downto 1);\n\t\t\tP_Out(Flag_C) <= BusA(0);\n\t\twhen \"1011\" =>\n"}
{"file": "openfpga-asteroids/src/fpga/core/rtl/T65_MCode.vhd", "target_type": "case_statement", "cursor_line": 167, "target_nlines": 1, "node_depth": 6, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "case_statement"], "target": "\t\t\twhen \"10\" =>\n"}
{"file": "openfpga-asteroids/src/fpga/core/rtl/T65_Pack.vhd", "target_type": "constant_declaration", "cursor_line": 63, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "constant_declaration"], "target": "\tconstant Flag_Z : integer := 1;\n"}
{"file": "openfpga-asteroids/src/fpga/core/rtl/asteroids.vhd", "target_type": "process_statement", "cursor_line": 904, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\n\n-- if (sum(8) = '0') then\n AUDIO_OUT <= sum(7 downto 0);\n"}
{"file": "openfpga-asteroids/src/fpga/core/rtl/asteroids_dw.vhd", "target_type": "process_statement", "cursor_line": 166, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " p_cnt_compare_comb : process(pcount,lcount)\n begin\n hterm <= (pcount = (PIXEL_PER_LINE(10 downto 0) - \"1\"));\n vterm <= (lcount = (LINE_PER_FRAME( 9 downto 0) - \"1\"));\n end process;\n"}
{"file": "openfpga-asteroids/src/fpga/core/rtl/asteroids_ram.vhd", "target_type": "process_statement", "cursor_line": 91, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " p_we : process(RW_L, CS_L, ENA)\n begin\n we <= (not CS_L) and (not RW_L) and ENA;\n end process;\n"}
{"file": "openfpga-asteroids/src/fpga/core/rtl/asteroids_top.vhd", "target_type": "architecture_body", "cursor_line": 157, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " LANG\t\t\t\t\t=> LANG,\n\t\tSHIPS\t\t\t\t\t=> SHIPS,\n"}
{"file": "openfpga-asteroids/src/fpga/core/rtl/asteroids_vg.vhd", "target_type": "entity_declaration", "cursor_line": 57, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " C_DOUT : out std_logic_vector( 7 downto 0);\n C_RW_L : in std_logic;\n VMEM_L : in std_logic;\n\n DMA_GO_L : in std_logic;\n"}
{"file": "openfpga-asteroids/src/fpga/core/rtl/dpram.vhd", "target_type": "architecture_body", "cursor_line": 37, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\tclock_enable_output_a => \"BYPASS\",\n"}
{"file": "openfpga-asteroids/src/fpga/core/rtl/ram_1k.vhd", "target_type": "architecture_body", "cursor_line": 74, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\twidth_byteena_a\t\t: NATURAL\n"}
{"file": "uart-for-fpga/examples/common/rst_sync.vhd", "target_type": "architecture_body", "cursor_line": 43, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " meta_reg <= '0';\n reset_reg <= meta_reg;\n end if;\n"}
{"file": "uart-for-fpga/examples/loopback/uart_loopback_cyc1000.vhd", "target_type": "entity_declaration", "cursor_line": 22, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " PARITY_BIT : string := \"none\"; -- legal values: \"none\", \"even\", \"odd\", \"mark\", \"space\"\n USE_DEBOUNCER : boolean := True -- enable/disable debouncer\n );\n"}
{"file": "uart-for-fpga/examples/uart2wb/uart2wb_fpga_cyc1000.vhd", "target_type": "process_statement", "cursor_line": 105, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " wb_dout <= debug_reg;\n when others =>\n"}
{"file": "uart-for-fpga/examples/uart2wb/uart2wbm.vhd", "target_type": "architecture_body", "cursor_line": 51, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\n signal uart_dout : std_logic_vector(7 downto 0);\n signal uart_dout_vld : std_logic;\n signal uart_din : std_logic_vector(7 downto 0);\n signal uart_din_vld : std_logic;\n"}
{"file": "uart-for-fpga/rtl/comp/uart_clk_div.vhd", "target_type": "entity_declaration", "cursor_line": 15, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " Generic (\n DIV_MAX_VAL : integer := 16;\n"}
{"file": "uart-for-fpga/rtl/comp/uart_debouncer.vhd", "target_type": "process_statement", "cursor_line": 49, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " all_bits_or_l : for i in 0 to SHREG_DEPTH-1 loop\n or_var := or_var or input_shreg(i);\n end loop;\n output_reg_rst <= not or_var;\n end process;\n"}
{"file": "uart-for-fpga/rtl/comp/uart_parity.vhd", "target_type": "architecture_body", "cursor_line": 40, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " PARITY_OUT <= parity_temp;\n end process;\n end generate;\n\n"}
{"file": "uart-for-fpga/rtl/comp/uart_rx.vhd", "target_type": "process_statement", "cursor_line": 97, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " end if;\n"}
{"file": "uart-for-fpga/rtl/comp/uart_tx.vhd", "target_type": "process_statement", "cursor_line": 201, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " when databits =>\n tx_ready <= '0';\n tx_data_out_sel <= \"10\";\n tx_bit_count_en <= '1';\n tx_clk_div_clr <= '0';\n"}
{"file": "uart-for-fpga/rtl/uart.vhd", "target_type": "process_statement", "cursor_line": 81, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " if (rising_edge(CLK)) then\n uart_rxd_meta_n <= not UART_RXD;\n uart_rxd_synced_n <= uart_rxd_meta_n;\n end if;\n end process;\n"}
{"file": "uart-for-fpga/sim/uart_tb.vhd", "target_type": "process_statement", "cursor_line": 154, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " RST <= '1';\n wait for CLK_PERIOD*3;\n RST <= '0';\n"}
{"file": "MIPS-processor/adder.vhd", "target_type": "entity_declaration", "cursor_line": 12, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\tport (\n\t\tx,y: in std_logic_vector(31 downto 0);\n\t\tz: out std_logic_vector(31 downto 0)\n"}
{"file": "MIPS-processor/alu.vhd", "target_type": "entity_declaration", "cursor_line": 19, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\tin_1, in_2: std_logic_vector(31 downto 0);\n\t\talu_control_fuct: in std_logic_vector(3 downto 0);\n\t\tzero: out std_logic;\n\t\talu_result: out std_logic_vector(31 downto 0)\n"}
{"file": "MIPS-processor/alu_control.vhd", "target_type": "entity_declaration", "cursor_line": 18, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity alu_control is\n\tport (\n\t\tfunct: in std_logic_vector(5 downto 0);\n"}
{"file": "MIPS-processor/control.vhd", "target_type": "entity_declaration", "cursor_line": 23, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\treg_dest,jump, branch, mem_read, mem_to_reg, mem_write, alu_src, reg_write: out std_logic;\n"}
{"file": "MIPS-processor/instruction_memory.vhd", "target_type": "process_statement", "cursor_line": 77, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " variable char : character:='0'; \n"}
{"file": "MIPS-processor/main.vhd", "target_type": "architecture_body", "cursor_line": 84, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\t\talu_control_fuct: out std_logic_vector(3 downto 0)\n\t\t);\n\tend component;\n"}
{"file": "MIPS-processor/memory.vhd", "target_type": "entity_declaration", "cursor_line": 12, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity memory is\n"}
{"file": "MIPS-processor/mux.vhd", "target_type": "architecture_body", "cursor_line": 20, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "architecture beh of mux is\n\tbegin\n\tz <= x when (s='0') else y;\nend beh;\n"}
{"file": "MIPS-processor/pc.vhd", "target_type": "architecture_body", "cursor_line": 27, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\tprocess(ck)\n\t\tbegin\n"}
{"file": "MIPS-processor/registers.vhd", "target_type": "entity_declaration", "cursor_line": 14, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity registers is \n\tport (\n ck: in std_logic;\n\t\treg_write: in std_logic;\n"}
{"file": "MIPS-processor/shifter.vhd", "target_type": "architecture_body", "cursor_line": 22, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\n\tbegin\n\ttemp <= std_logic_vector(resize(unsigned(x), n2)); -- This is required if you want to increase or decease the number of bits\n\ty <= std_logic_vector(shift_left(signed(temp), k));\n"}
{"file": "MIPS-processor/sign_extend.vhd", "target_type": "architecture_body", "cursor_line": 19, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "architecture beh of sign_extend is\n\tbegin\n\ty <= std_logic_vector(resize(signed(x), y'length));\nend beh;\n"}
{"file": "gnss-baseband/gpsif_config_asic.vhd", "target_type": "design_file", "cursor_line": 8, "target_nlines": 5, "node_depth": 0, "node_path": ["design_file"], "target": " end for;\n for all : bist_RF2\n use configuration work.bist_rf2_asic;\n end for;\n end for;\n"}
{"file": "gnss-baseband/gpsif_config_fpga.vhd", "target_type": "design_file", "cursor_line": 7, "target_nlines": 3, "node_depth": 0, "node_path": ["design_file"], "target": " use configuration work.bist_rf1_inferred;\n end for;\n for all : bist_RF2\n"}
{"file": "gnss-baseband/gpsif_config_sim.vhd", "target_type": "design_file", "cursor_line": 18, "target_nlines": 4, "node_depth": 0, "node_path": ["design_file"], "target": " for arch\n for g : gpsif\n use configuration work.gpsif_sim;\n end for;\n"}
{"file": "gnss-baseband/gpsif_pkg.vhd", "target_type": "case_statement", "cursor_line": 498, "target_nlines": 5, "node_depth": 8, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "sequence_of_statements", "case_statement", "case_statement_alternative", "sequence_of_statements", "case_statement"], "target": " case b(0) is\n when '0' => ci := '0'; sc4 := (others => '0'); -- *(+1)\n when '1' => sc := not sc; -- *(+3) ( 3 = 4 - 1)\n when others =>\n end case;\n"}
{"file": "gnss-baseband/gpsif_sub_pkg.vhd", "target_type": "constant_declaration", "cursor_line": 22, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "constant_declaration"], "target": "constant NULL_DMA_REQ : dma_req_t := ( req => (others => '0') );\n"}
{"file": "gnss-baseband/gpsif_top.vhd", "target_type": "entity_declaration", "cursor_line": 176, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity gpsif_top is\n generic ( GPSIF_NC : integer := 7;\n ANGLE_INI_OLD : boolean := false );\n port (\n clk : in std_logic;\n"}
{"file": "gnss-baseband/rbus_pkg.vhd", "target_type": "constant_declaration", "cursor_line": 9, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "constant_declaration"], "target": "constant RNG_CH_GPS : integer := 1;\n"}
{"file": "gnss-baseband/tests/gpsif_db_tb.vhd", "target_type": "entity_declaration", "cursor_line": 12, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity gpsif_db_tb is\nend entity;\n"}
{"file": "gnss-baseband/tests/gpsif_tb.vhd", "target_type": "process_statement", "cursor_line": 108, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " variable LI : line;\n variable input : std_logic_vector(1 downto 0);\n begin\n -- gps signal input\n input_loop: while true loop\n"}
{"file": "gnss-baseband/tests/gpsif_tb_pkg.vhd", "target_type": "variable_declaration", "cursor_line": 31, "target_nlines": 1, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "procedure_body", "declarative_part", "variable_declaration"], "target": " variable LI : line;\n"}
{"file": "gnss-baseband/tests/gpsob/gpsif_tb_gpsob.vhd", "target_type": "process_statement", "cursor_line": 100, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " end if;\n readline(FI, LI);\n read(LI, input(1 downto 0));\n gps_d <= input;\n"}
{"file": "gnss-baseband/tools/tests/tap/test_pkg.vhd", "target_type": "case_statement", "cursor_line": 70, "target_nlines": 4, "node_depth": 7, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "sequence_of_statements", "loop_statement", "sequence_of_statements", "case_statement"], "target": " case s(i) is\n when LF | CR => s_no_eol(i) := '_';\n when others => s_no_eol(i) := s(i);\n end case;\n"}
{"file": "neoapple2/neoapple2/hdl/PS2_Ctrl.vhd", "target_type": "architecture_body", "cursor_line": 138, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " end case;\n\n --Scan_Err <= '0'; -- to create an on-purpose error on Scan_Err !\n\n end if;\n"}
{"file": "neoapple2/neoapple2/hdl/Z1_TOP.vhd", "target_type": "architecture_body", "cursor_line": 215, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " read_key => read_key,\r\n-- AN => LEDG(7 downto 4),\r\n GAMEPORT => GAMEPORT,\r\n"}
{"file": "neoapple2/neoapple2/hdl/apple2.vhd", "target_type": "case_statement", "cursor_line": 145, "target_nlines": 3, "node_depth": 12, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "case_statement", "case_statement_alternative", "sequence_of_statements", "case_statement", "case_statement_alternative", "sequence_of_statements", "case_statement"], "target": " when x\"3\" => -- C030 - C03F\n SPEAKER_SELECT <= '1';\n when x\"4\" =>\n"}
{"file": "neoapple2/neoapple2/hdl/character_rom.vhd", "target_type": "entity_declaration", "cursor_line": 9, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " clk : in std_logic;\n dout : out unsigned(4 downto 0));\n"}
{"file": "neoapple2/neoapple2/hdl/cpu6502.vhd", "target_type": "process_statement", "cursor_line": 1490, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\twhen cycleIndirect =>\n"}
{"file": "neoapple2/neoapple2/hdl/disk_ii.vhd", "target_type": "process_statement", "cursor_line": 170, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " variable new_phase : integer;\n variable rel_phase : std_logic_vector(3 downto 0);\n begin\n if rising_edge(CLK_14M) then\n if reset = '1' then\n"}
{"file": "neoapple2/neoapple2/hdl/disk_ii_rom.vhd", "target_type": "process_statement", "cursor_line": 52, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " begin\n if rising_edge(clk) then\n dout <= ROM(TO_INTEGER(addr));\n"}
{"file": "neoapple2/neoapple2/hdl/keyboard.vhd", "target_type": "process_statement", "cursor_line": 110, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " if state = NORMAL_KEY then\n latched_code <= code ;\n key_pressed <= '1';\n end if;\n"}
{"file": "neoapple2/neoapple2/hdl/main_roms.vhd", "target_type": "entity_declaration", "cursor_line": 9, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " dout : out unsigned(7 downto 0));\n"}
{"file": "neoapple2/neoapple2/hdl/timing_generator.vhd", "target_type": "process_statement", "cursor_line": 78, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " end if;\n"}
{"file": "neoapple2/neoapple2/hdl/timing_testbench.vhd", "target_type": "entity_declaration", "cursor_line": 5, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity timing_testbench is\n \nend timing_testbench;\n"}
{"file": "neoapple2/neoapple2/hdl/video_generator.vhd", "target_type": "process_statement", "cursor_line": 155, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " hires_delayed <= graph_shiftreg(0);\n end if;\n end process; \n"}
{"file": "neppielight/averager.vhd", "target_type": "entity_declaration", "cursor_line": 15, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " clk_pixel : IN std_logic;\n"}
{"file": "neppielight/dvid_in/dvid_gearbox.vhd", "target_type": "process_statement", "cursor_line": 56, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " joined <= data_in & joined(joined'high downto 5) ;\n else\n joined <= (data_in xor \"11111\") & joined(joined'high downto 5) ;\n end if;\n"}
{"file": "neppielight/dvid_in/dvid_in.vhd", "target_type": "architecture_body", "cursor_line": 297, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " -- We've just seen a sync codeword, so restart the counter\n -- This means that we are in sync\n ------------------------------------------------------------\n since_sync <= (others => '0');\n"}
{"file": "neppielight/dvid_in/dvid_input_channel.vhd", "target_type": "process_statement", "cursor_line": 153, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " else\n sync_seen <= '0';\n end if;\n end if;\n end process;\n"}
{"file": "neppielight/dvid_in/serialiser_in.vhd", "target_type": "entity_declaration", "cursor_line": 17, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " clk_input : in STD_LOGIC;\n strobe : in STD_LOGIC;\n ser_data : out STD_LOGIC_VECTOR (4 downto 0);\n ser_input : in STD_LOGIC);\nend input_serialiser;\n"}
{"file": "neppielight/dvid_in/tmds_decode.vhd", "target_type": "architecture_body", "cursor_line": 60, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " data_out(3) <= sometimes_inverted(3) XNOR sometimes_inverted(2);\n"}
{"file": "neppielight/dvid_out/dvid_out.vhd", "target_type": "process_statement", "cursor_line": 136, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " ser_in_clock <= \"00000\";\n"}
{"file": "neppielight/dvid_out/dvid_out_clocking.vhd", "target_type": "entity_declaration", "cursor_line": 28, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " clk_x1 : out STD_LOGIC; \n clk_x2 : out STD_LOGIC; \n clk_x10 : out STD_LOGIC; \n serdes_strobe : out STD_LOGIC); \nend dvid_out_clocking;\n"}
{"file": "neppielight/dvid_out/output_serialiser.vhd", "target_type": "entity_declaration", "cursor_line": 15, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " strobe : in STD_LOGIC;\n ser_data : in STD_LOGIC_VECTOR (4 downto 0);\n ser_output : out STD_LOGIC);\nend output_serialiser;\n"}
{"file": "neppielight/dvid_out/tmds_encoder.vhd", "target_type": "case_statement", "cursor_line": 79, "target_nlines": 3, "node_depth": 12, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "case_statement"], "target": " case c is \n when \"00\" => encoded <= \"1101010100\";\n when \"01\" => encoded <= \"0010101011\";\n"}
{"file": "neppielight/neppielight.vhd", "target_type": "architecture_body", "cursor_line": 31, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\tvsync : IN std_logic; \n\t\ttmds_out_p : OUT std_logic_vector(3 downto 0);\n\t\ttmds_out_n : OUT std_logic_vector(3 downto 0)\n\t\t);\n"}
{"file": "neppielight/spiout.vhd", "target_type": "process_statement", "cursor_line": 45, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " \t sck_s <= sck_counter(11);\n"}
{"file": "Basys3/Projects/GPIO/src/hdl/GPIO_Demo.vhd", "target_type": "process_statement", "cursor_line": 431, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\tstrIndex <= strIndex + 1;\n\t\tend if;\n\tend if;\nend process;\n"}
{"file": "Basys3/Projects/GPIO/src/hdl/MouseCtl.vhd", "target_type": "process_statement", "cursor_line": 388, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "begin\n if clk'EVENT AND clk = '1' then\n if reset_periodic_check_cnt = '1' then\n periodic_check_cnt <= 0;\n elsif periodic_check_cnt = (CHECK_PERIOD_CLOCKS - 1) then \n"}
{"file": "Basys3/Projects/GPIO/src/hdl/MouseDisplay.vhd", "target_type": "process_statement", "cursor_line": 218, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " else\n enable_mouse_display <= '0';\n end if;\n end if;\n"}
{"file": "Basys3/Projects/GPIO/src/hdl/Ps2Interface.vhd", "target_type": "process_statement", "cursor_line": 696, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " if(delay_100us_counter_enable = '1') then\n"}
{"file": "Basys3/Projects/GPIO/src/hdl/UART_TX_CTRL.vhd", "target_type": "entity_declaration", "cursor_line": 44, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " DATA : in STD_LOGIC_VECTOR (7 downto 0);\n CLK : in STD_LOGIC;\n READY : out STD_LOGIC;\n UART_TX : out STD_LOGIC);\nend UART_TX_CTRL;\n"}
{"file": "Basys3/Projects/GPIO/src/hdl/clk_wiz_0.vhd", "target_type": "entity_declaration", "cursor_line": 75, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "port\n (-- Clock in ports\n clk_in1 : in std_logic;\n -- Clock out ports\n clk_out1 : out std_logic\n"}
{"file": "Basys3/Projects/GPIO/src/hdl/clk_wiz_0_clk_wiz.vhd", "target_type": "entity_declaration", "cursor_line": 78, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " -- Clock out ports\n clk_out1 : out std_logic\n );\n"}
{"file": "Basys3/Projects/GPIO/src/hdl/debouncer.vhd", "target_type": "process_statement", "cursor_line": 79, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\tif (sig_cntrs_ary(index) = CNTR_MAX) then\n"}
{"file": "Basys3/Projects/GPIO/src/hdl/vga_ctrl.vhd", "target_type": "process_statement", "cursor_line": 367, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " h_cntr_reg_dly <= h_cntr_reg;\n"}
{"file": "Basys3/Projects/XADC_Demo/src/hdl/UART_TX_CTRL.vhd", "target_type": "process_statement", "cursor_line": 92, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\t\t\ttxState <= RDY;\n\t\t\t\telse\n\t\t\t\t\ttxState <= LOAD_BIT;\n\t\t\t\tend if;\n\t\t\tend if;\n"}
{"file": "Basys3/Projects/XADC_Demo/src/ip/xadc_wiz_0_1/xadc_wiz_0.vhd", "target_type": "architecture_body", "cursor_line": 89, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " signal FLOAT_VCCINT_ALARM : std_logic;\n signal FLOAT_USER_TEMP_ALARM : std_logic;\n signal FLOAT_VBRAM_ALARM : std_logic;\n signal FLOAT_MUXADDR : std_logic_vector (4 downto 0);\n signal aux_channel_p : std_logic_vector (15 downto 0);\n"}
{"file": "Basys3/Projects/XADC_Demo/src/ip/xadc_wiz_0_1/xadc_wiz_0_funcsim.vhdl", "target_type": "architecture_body", "cursor_line": 140, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " VAUXP(10) => '0',\n VAUXP(9) => '0',\n VAUXP(8) => '0',\n"}
{"file": "Basys3/Projects/XADC_Demo/src/ip/xadc_wiz_0_1/xadc_wiz_0_stub.vhdl", "target_type": "entity_declaration", "cursor_line": 23, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " dclk_in : in STD_LOGIC;\n vauxp6 : in STD_LOGIC;\n vauxn6 : in STD_LOGIC;\n vauxp7 : in STD_LOGIC;\n"}
{"file": "XJTU-Tripler/hpu_core/fpga/hpu_reg_version/hpu_reg_version.srcs/sources_1/bd/ps_block/ip/ps_block_axi_bram_ctrl_0_0/ps_block_axi_bram_ctrl_0_0_sim_netlist.vhdl", "target_type": "architecture_body", "cursor_line": 1423, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " I2 => ua_narrow_load1_carry_n_6,\n I3 => s_axi_araddr_0_sn_1,\n I4 => \\GEN_NARROW_CNT.narrow_bram_addr_inc_d1_reg\\,\n I5 => Q(0),\n"}
{"file": "XJTU-Tripler/hpu_core/fpga/hpu_reg_version/hpu_reg_version.srcs/sources_1/bd/ps_block/ip/ps_block_axi_bram_ctrl_0_0/ps_block_axi_bram_ctrl_0_0_stub.vhdl", "target_type": "entity_declaration", "cursor_line": 54, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " bram_rst_a : out STD_LOGIC;\n"}
{"file": "XJTU-Tripler/hpu_core/fpga/hpu_reg_version/hpu_reg_version.srcs/sources_1/bd/ps_block/ip/ps_block_axi_bram_ctrl_0_0/sim/ps_block_axi_bram_ctrl_0_0.vhd", "target_type": "architecture_body", "cursor_line": 142, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);\n"}
{"file": "XJTU-Tripler/hpu_core/fpga/hpu_reg_version/hpu_reg_version.srcs/sources_1/bd/ps_block/ip/ps_block_axi_bram_ctrl_0_0/synth/ps_block_axi_bram_ctrl_0_0.vhd", "target_type": "entity_declaration", "cursor_line": 78, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " s_axi_bid : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);\n s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);\n"}
{"file": "XJTU-Tripler/hpu_core/fpga/hpu_reg_version/hpu_reg_version.srcs/sources_1/bd/ps_block/ip/ps_block_rst_ps8_0_100M_0/ps_block_rst_ps8_0_100M_0_sim_netlist.vhdl", "target_type": "architecture_body", "cursor_line": 103, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " R => '0'\n );\n"}
{"file": "XJTU-Tripler/hpu_core/fpga/hpu_reg_version/hpu_reg_version.srcs/sources_1/bd/ps_block/ip/ps_block_rst_ps8_0_100M_0/ps_block_rst_ps8_0_100M_0_stub.vhdl", "target_type": "entity_declaration", "cursor_line": 24, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );\n interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );\n peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )\n );\n"}
{"file": "XJTU-Tripler/hpu_core/fpga/hpu_reg_version/hpu_reg_version.srcs/sources_1/bd/ps_block/ip/ps_block_rst_ps8_0_100M_0/sim/ps_block_rst_ps8_0_100M_0.vhd", "target_type": "architecture_body", "cursor_line": 142, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " bus_struct_reset => bus_struct_reset,\n peripheral_reset => peripheral_reset,\n interconnect_aresetn => interconnect_aresetn,\n peripheral_aresetn => peripheral_aresetn\n"}
{"file": "XJTU-Tripler/hpu_core/fpga/hpu_reg_version/hpu_reg_version.srcs/sources_1/bd/ps_block/ip/ps_block_rst_ps8_0_100M_0/synth/ps_block_rst_ps8_0_100M_0.vhd", "target_type": "architecture_body", "cursor_line": 78, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " GENERIC (\n C_FAMILY : STRING;\n C_EXT_RST_WIDTH : INTEGER;\n C_AUX_RST_WIDTH : INTEGER;\n"}
{"file": "XJTU-Tripler/hpu_core/fpga/hpu_reg_version/hpu_reg_version.srcs/sources_1/bd/ps_block/ip/ps_block_zynq_ultra_ps_e_0_0/ps_block_zynq_ultra_ps_e_0_0_sim_netlist.vhdl", "target_type": "entity_declaration", "cursor_line": 6331, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " maxigp0_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );\n maxigp0_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );\n"}
{"file": "XJTU-Tripler/hpu_core/fpga/hpu_reg_version/hpu_reg_version.srcs/sources_1/bd/ps_block/ip/ps_block_zynq_ultra_ps_e_0_0/ps_block_zynq_ultra_ps_e_0_0_stub.vhdl", "target_type": "entity_declaration", "cursor_line": 77, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " saxigp2_bvalid : out STD_LOGIC;\n saxigp2_bready : in STD_LOGIC;\n saxigp2_arid : in STD_LOGIC_VECTOR ( 5 downto 0 );\n saxigp2_araddr : in STD_LOGIC_VECTOR ( 48 downto 0 );\n"}
{"file": "XJTU-Tripler/hpu_core/fpga/hpu_reg_version/hpu_reg_version.srcs/sources_1/bd/ps_block/ipshared/6db1/hdl/axi_bram_ctrl_v4_0_rfs.vhd", "target_type": "process_statement", "cursor_line": 20833, "target_nlines": 4, "node_depth": 10, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "if_generate_statement", "if_generate", "generate_statement_body", "if_generate_statement", "if_generate", "generate_statement_body", "process_statement"], "target": " REG_SYNDROME: process (S_AXI_AClk)\n begin \n if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then \n syndrome_r <= syndrome_ns; \n"}
{"file": "XJTU-Tripler/hpu_core/fpga/hpu_reg_version/hpu_reg_version.srcs/sources_1/bd/ps_block/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd", "target_type": "entity_declaration", "cursor_line": 75, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " -- 1 is single bit input\n C_FLOP_INPUT : integer range 0 to 1 := 0 ;\n C_VECTOR_WIDTH : integer range 0 to 64 := 32 ;\n C_MTBF_STAGES : integer range 0 to 6 := 2 \n -- Vector Data witdth\n"}
{"file": "XJTU-Tripler/hpu_core/fpga/hpu_reg_version/hpu_reg_version.srcs/sources_1/bd/ps_block/ipshared/f86a/hdl/proc_sys_reset_v5_0_vh_rfs.vhd", "target_type": "process_statement", "cursor_line": 362, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " --elsif Chip_Reset_Req_d3='1' then\n -- from_sys <= '0';\n elsif (Core = '0') then\n from_sys <='0';\n"}
{"file": "Zybo-Z7-20-pcam-5c/repo/local/ip/AXI_BayerToRGB/hdl/AXI_BayerToRGB.vhd", "target_type": "process_statement", "cursor_line": 205, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " sLineBufferWrite <= '0';\n"}
{"file": "Zybo-Z7-20-pcam-5c/repo/local/ip/AXI_BayerToRGB/hdl/LineBuffer.vhd", "target_type": "process_statement", "cursor_line": 65, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "process (PixelClk)\n"}
{"file": "Zybo-Z7-20-pcam-5c/repo/local/ip/AXI_GammaCorrection/hdl/AXI_GammaCorrection.vhd", "target_type": "process_statement", "cursor_line": 422, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " if aAxiLiteReset_n = '0' then\n axi_bvalid <= '0';\n"}
{"file": "Zybo-Z7-20-pcam-5c/repo/local/ip/AXI_GammaCorrection/hdl/StoredGammaCoefs.vhd", "target_type": "process_statement", "cursor_line": 396, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " elsif rGammaFactor = \"010\" then -- Gamma Factor = 1 / 1.5\n rStoredData <= rStoredCoefs1_5(to_integer(unsigned(rReadAddr)));\n elsif rGammaFactor = \"011\" then -- Gamma Factor = 1 / 1.8\n rStoredData <= rStoredCoefs1_8(to_integer(unsigned(rReadAddr)));\n"}
{"file": "Zybo-Z7-20-pcam-5c/repo/local/ip/AXI_GammaCorrection/src/design_1/hdl/design_1_wrapper.vhd", "target_type": "entity_declaration", "cursor_line": 29, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " S_AXI_0_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );\n"}
{"file": "Zybo-Z7-20-pcam-5c/repo/local/ip/AXI_GammaCorrection/src/design_1/ip/design_1_AXI_GammaCorrection_0_0/sim/design_1_AXI_GammaCorrection_0_0.vhd", "target_type": "architecture_body", "cursor_line": 198, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " m_axis_video_tuser => m_axis_video_tuser,\n m_axis_video_tlast => m_axis_video_tlast,\n"}
{"file": "Zybo-Z7-20-pcam-5c/repo/local/ip/AXI_GammaCorrection/src/design_1/ip/design_1_axi4stream_vip_0_0/design_1_axi4stream_vip_0_0_sim_netlist.vhdl", "target_type": "entity_declaration", "cursor_line": 122, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " attribute NotValidForBitStream of design_1_axi4stream_vip_0_0 : entity is true;\n attribute CHECK_LICENSE_TYPE : string;\n attribute CHECK_LICENSE_TYPE of design_1_axi4stream_vip_0_0 : entity is \"design_1_axi4stream_vip_0_0,axi4stream_vip_v1_1_3_top,{}\";\n attribute DowngradeIPIdentifiedWarnings : string;\n attribute DowngradeIPIdentifiedWarnings of design_1_axi4stream_vip_0_0 : entity is \"yes\";\n"}
{"file": "Zybo-Z7-20-pcam-5c/repo/local/ip/AXI_GammaCorrection/src/design_1/ip/design_1_axi4stream_vip_0_0/design_1_axi4stream_vip_0_0_stub.vhdl", "target_type": "entity_declaration", "cursor_line": 23, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " s_axis_tuser : in STD_LOGIC_VECTOR ( 0 to 0 )\n );\n"}
{"file": "Zybo-Z7-20-pcam-5c/repo/local/ip/AXI_GammaCorrection/src/design_1/ip/design_1_axi4stream_vip_1_0/design_1_axi4stream_vip_1_0_sim_netlist.vhdl", "target_type": "architecture_body", "cursor_line": 110, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " m_axis_tvalid <= \\<const0>\\;\n"}
{"file": "Zybo-Z7-20-pcam-5c/repo/local/ip/AXI_GammaCorrection/src/design_1/ip/design_1_axi4stream_vip_1_0/design_1_axi4stream_vip_1_0_stub.vhdl", "target_type": "entity_declaration", "cursor_line": 18, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " aresetn : in STD_LOGIC;\n"}
{"file": "Zybo-Z7-20-pcam-5c/src/hdl/DVIClocking.vhd", "target_type": "architecture_body", "cursor_line": 68, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " generic map (\n kPolarity => '0')\n port map (\n aRst => aLockedIn,\n"}
{"file": "Zybo-Z7-20-pcam-5c/src/hdl/SyncAsync.vhd", "target_type": "entity_declaration", "cursor_line": 54, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity SyncAsync is\n Generic (\n"}
{"file": "Zybo-Z7-20-pcam-5c/src/hdl/SyncAsyncReset.vhd", "target_type": "entity_declaration", "cursor_line": 61, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " OutClk : in STD_LOGIC;\n"}
{"file": "flexray-interceptor/can_pkg.vhd", "target_type": "package_declaration", "cursor_line": 4, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "package_declaration"], "target": "package can is\n type message is record\n"}
{"file": "flexray-interceptor/can_rx.vhd", "target_type": "entity_declaration", "cursor_line": 7, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " clk : in std_ulogic; -- Clock 8x higher than can bitrate\n rst : in std_ulogic;\n rx : in std_ulogic;\n debug : out std_ulogic;\n\n"}
{"file": "flexray-interceptor/can_tx.vhd", "target_type": "process_statement", "cursor_line": 148, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " begin\n if rst = '1' then\n prev_ready <= '0';\n send_req <= '0';\n"}
{"file": "flexray-interceptor/divider.vhd", "target_type": "entity_declaration", "cursor_line": 7, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " );\n\n port(\n clk : in std_ulogic;\n rst : in std_ulogic;\n"}
{"file": "flexray-interceptor/flexray_interceptor.vhd", "target_type": "process_statement", "cursor_line": 60, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " bus_1_idle_counter := 0;\n tx_en_1 <= '0';\n"}
{"file": "flexray-interceptor/flexray_pkg.vhd", "target_type": "package_declaration", "cursor_line": 15, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "package_declaration"], "target": " end record message;\nend package flexray;\n"}
{"file": "flexray-interceptor/flexray_rx.vhd", "target_type": "architecture_body", "cursor_line": 106, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " in_tss := '1';\n"}
{"file": "flexray-interceptor/flexray_torque_intercept.vhd", "target_type": "architecture_body", "cursor_line": 237, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " end if;\n\n"}
{"file": "flexray-interceptor/joystick_decoder.vhd", "target_type": "architecture_body", "cursor_line": 20, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " rx : in std_ulogic;\n tx : out std_ulogic;\n debug : out std_ulogic;\n msg : out work.can.message;\n ready : out std_ulogic);\n"}
{"file": "flexray-interceptor/main_clock.vhd", "target_type": "architecture_body", "cursor_line": 125, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\t\tareset\t: IN STD_LOGIC ;\n\t\t\tinclk\t: IN STD_LOGIC_VECTOR (1 DOWNTO 0);\n\t\t\tclk\t: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);\n"}
{"file": "flexray-interceptor/pwm_driver.vhd", "target_type": "process_statement", "cursor_line": 22, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " elsif rising_edge(clk) then\n"}
{"file": "flexray-interceptor/simulation/modelsim/can_generator.vhd", "target_type": "architecture_body", "cursor_line": 73, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "wait for 1980 ns;\nchannel_0 <= '0';\nwait for 10020 ns;\n"}
{"file": "flexray-interceptor/simulation/modelsim/flexray_generator.vhd", "target_type": "entity_declaration", "cursor_line": 4, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity flexray_generator is\n port (channel_0 : out std_ulogic);\nend entity flexray_generator;\n"}
{"file": "fmcw3/fpga/fmcw3/fmcw3.srcs/sim_1/new/adc_sim.vhd", "target_type": "entity_declaration", "cursor_line": 34, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity adc_sim is\nend adc_sim;\n"}
{"file": "fmcw3/fpga/fmcw3/fmcw3.srcs/sim_1/new/control_tb.vhd", "target_type": "process_statement", "cursor_line": 67, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "begin\n clk <= '0';\n wait for clk_period/2;\n clk <= '1';\n wait for clk_period/2;\n"}
{"file": "fmcw3/fpga/fmcw3/fmcw3.srcs/sim_1/new/fmcw3_top_tb.vhd", "target_type": "process_statement", "cursor_line": 156, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " clk <= '1';\n wait for clk_period/2;\n"}
{"file": "fmcw3/fpga/fmcw3/fmcw3.srcs/sim_1/new/spi_tb.vhd", "target_type": "process_statement", "cursor_line": 66, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " wait until ack = '1';\n write <= '0';\n wait for clk_period;\n"}
{"file": "fmcw3/fpga/fmcw3/fmcw3.srcs/sim_1/new/usb_sync_tb.vhd", "target_type": "process_statement", "cursor_line": 124, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "begin\n clk <= '0';\n"}
{"file": "fmcw3/fpga/fmcw3/fmcw3.srcs/sources_1/new/adc.vhd", "target_type": "entity_declaration", "cursor_line": 34, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " data_a : out STD_LOGIC_VECTOR (15 downto 0);\n data_b : out STD_LOGIC_VECTOR (15 downto 0);\n valid : out STD_LOGIC);\nend adc;\n"}
{"file": "fmcw3/fpga/fmcw3/fmcw3.srcs/sources_1/new/control.vhd", "target_type": "case_statement", "cursor_line": 136, "target_nlines": 5, "node_depth": 9, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "elsif", "sequence_of_statements", "case_statement"], "target": " end if;\n end if;\n \n when others =>\n state := S_START;\n"}
{"file": "fmcw3/fpga/fmcw3/fmcw3.srcs/sources_1/new/downsampler.vhd", "target_type": "process_statement", "cursor_line": 120, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " end loop;\n \nend if;\n"}
{"file": "fmcw3/fpga/fmcw3/fmcw3.srcs/sources_1/new/fmcw3_top.vhd", "target_type": "entity_declaration", "cursor_line": 54, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " adf_le : out STD_LOGIC;\n adf_clk : out STD_LOGIC;\n"}
{"file": "fmcw3/fpga/fmcw3/fmcw3.srcs/sources_1/new/sample_packer.vhd", "target_type": "process_statement", "cursor_line": 170, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " end if;\n \n if clear_buffer = '1' then\n write_pointer <= (others => '0');\n read_pointer <= (others => '0');\n"}
{"file": "fmcw3/fpga/fmcw3/fmcw3.srcs/sources_1/new/spi.vhd", "target_type": "process_statement", "cursor_line": 153, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "if rising_edge(clk) then\n pipe_le(0) <= spi_le_int;\n"}
{"file": "fmcw3/fpga/fmcw3/fmcw3.srcs/sources_1/new/sweep_timer.vhd", "target_type": "entity_declaration", "cursor_line": 33, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " rst : in STD_LOGIC;\n adf_done : in STD_LOGIC;\n sample_valid : out STD_LOGIC;\n"}
{"file": "fmcw3/fpga/fmcw3/fmcw3.srcs/sources_1/new/usb_sync.vhd", "target_type": "process_statement", "cursor_line": 181, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\trx_fifo_rddone <= '0';\n \n"}
{"file": "mce2vga/cga_genlock.vhd", "target_type": "case_statement", "cursor_line": 412, "target_nlines": 4, "node_depth": 18, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "case_statement"], "target": "\t\t\t\t\t\tcase(rgb) is\n\t\t\t\t\t\t\twhen \"101000\" => pixel <= \"100100\"; -- BROWN\n\t\t\t\t\t\t\twhen others => pixel <= rgb; \n\t\t\t\t\t\tend case;\n"}
{"file": "mce2vga/ctrl_params.vhd", "target_type": "process_statement", "cursor_line": 197, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\t\t\t\tend if;\t\t\t\t\t\t\n\t\t\t\t\tend if;\t\n\t\t\t\telse\n\t\t\t\t\tpeak := 128*1024;\n"}
{"file": "mce2vga/dual_ram_in.vhd", "target_type": "process_statement", "cursor_line": 45, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\tif (rdaddress < 405) then\n\t\t\t\tq(7 downto 0) <= ram(to_integer(rdaddress & '0')); \n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n"}
{"file": "mce2vga/dual_ram_out.vhd", "target_type": "process_statement", "cursor_line": 39, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\t\telse\n\t\t\t\t\tq <= ram(to_integer(rdaddress(9 downto 1))) (15 downto 8); \n\t\t\t\tend if;\n"}
{"file": "mce2vga/ega_genlock.vhd", "target_type": "process_statement", "cursor_line": 170, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\tbegin\n\t\tif (rising_edge(clk)) then\n\t\t\tif (enable = '1') then\t\t\n\t\t\t\tif (hcount(2 downto 0) = \"111\") then\n\t\t\t\t\tpixel <= pr & sr & pg & sg & pb & sb;\n"}
{"file": "mce2vga/hgc_genlock.vhd", "target_type": "architecture_body", "cursor_line": 136, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\t\tend if;\n\t\tend if;\n"}
{"file": "mce2vga/mda_genlock.vhd", "target_type": "entity_declaration", "cursor_line": 28, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\tmax_col\t\t\t\t: out unsigned(9 downto 0);\n\t\tmax_row\t\t\t\t: out unsigned(9 downto 0);\n\t\t\n\t\tsamples\t\t\t\t: in unsigned(2 downto 0);\n"}
{"file": "mce2vga/osd_rom.vhd", "target_type": "entity_declaration", "cursor_line": 9, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\t\tdata \t\t: out std_logic\n\t\t );\n"}
{"file": "mce2vga/pll1.vhd", "target_type": "entity_declaration", "cursor_line": 44, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\tPORT\n"}
{"file": "mce2vga/pll2.vhd", "target_type": "entity_declaration", "cursor_line": 46, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\tinclk0\t\t: IN STD_LOGIC := '0';\n\t\tc0\t\t: OUT STD_LOGIC ;\n\t\tc1\t\t: OUT STD_LOGIC ;\n\t\tc2\t\t: OUT STD_LOGIC \n\t);\n"}
{"file": "mce2vga/sram.vhd", "target_type": "entity_declaration", "cursor_line": 38, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\twren\t\t\t\t: out std_logic;\n\t\trd_req\t\t\t: in std_logic;\n\t\trd_ack\t\t\t: out std_logic;\n"}
{"file": "mce2vga/sync_level.vhd", "target_type": "process_statement", "cursor_line": 224, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\tend if;\n\t\t\t\n\t\telse\t\t\t\n"}
{"file": "mce2vga/vga_video.vhd", "target_type": "process_statement", "cursor_line": 495, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\tend if;\n"}
{"file": "rgb2vga/vhdl/altiobuf.vhd", "target_type": "architecture_body", "cursor_line": 136, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "END RTL;\n"}
{"file": "rgb2vga/vhdl/dac_counter.vhd", "target_type": "entity_declaration", "cursor_line": 43, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "ENTITY dac_counter IS\n\tPORT\n\t(\n\t\taclr\t\t: IN STD_LOGIC ;\n\t\tclock\t\t: IN STD_LOGIC ;\n"}
{"file": "rgb2vga/vhdl/genlock.vhd", "target_type": "process_statement", "cursor_line": 760, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\tif (rising_edge(clock_pixel)) then\t\t\n\t\t--wait until (clock_pixel'event and clock_pixel='1' and hcount(2 downto 0) = dac_step); \n"}
{"file": "rgb2vga/vhdl/input_detect.vhd", "target_type": "process_statement", "cursor_line": 59, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\t\thcount := hcount + 1;\n\t\t\telse\n\t\t\t\tvideo_active <= '1';\n\t\t\tend if;\n\t\t\t\n"}
{"file": "rgb2vga/vhdl/pll_coco3.vhd", "target_type": "entity_declaration", "cursor_line": 43, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "ENTITY pll_coco3 IS\n\tPORT\n"}
{"file": "rgb2vga/vhdl/pll_speccy.vhd", "target_type": "entity_declaration", "cursor_line": 44, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t(\n\t\tinclk0\t\t: IN STD_LOGIC := '0';\n\t\tc0\t\t: OUT STD_LOGIC ;\n"}
{"file": "rgb2vga/vhdl/ram2.vhd", "target_type": "architecture_body", "cursor_line": 73, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\toperation_mode\t\t: STRING;\n\t\toutdata_aclr_b\t\t: STRING;\n\t\toutdata_reg_b\t\t: STRING;\n\t\tpower_up_uninitialized\t\t: STRING;\n\t\twidthad_a\t\t: NATURAL;\n"}
{"file": "rgb2vga/vhdl/sdram.vhd", "target_type": "entity_declaration", "cursor_line": 19, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\tpixelIn\t\t: in unsigned(15 downto 0);\t\t\n\t\trowStoreNr\t: in unsigned(9 downto 0); \n\t\tcolStoreNr\t: buffer unsigned(9 downto 0); \n\t\trowStoreReq\t: in std_logic;\n"}
{"file": "rgb2vga/vhdl/simulation/modelsim/rgb2vga.vho", "target_type": "entity_declaration", "cursor_line": 55, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\tDIFFGn : IN std_logic;\n"}
{"file": "rgb2vga/vhdl/simulation/modelsim/rgb2vga_6_1200mv_0c_slow.vho", "target_type": "entity_declaration", "cursor_line": 64, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\tD0 : OUT std_logic;\n\tD1 : OUT std_logic;\n\tD2 : OUT std_logic;\n\tVGAR0 : OUT std_logic;\n\tVGAR1 : OUT std_logic;\n"}
{"file": "rgb2vga/vhdl/simulation/modelsim/rgb2vga_6_1200mv_85c_slow.vho", "target_type": "entity_declaration", "cursor_line": 74, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\tVGAG2 : OUT std_logic;\n"}
{"file": "rgb2vga/vhdl/simulation/modelsim/rgb2vga_min_1200mv_0c_fast.vho", "target_type": "entity_declaration", "cursor_line": 73, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\tVGAR2 : OUT std_logic;\n"}
{"file": "rgb2vga/vhdl/vgaout.vhd", "target_type": "process_statement", "cursor_line": 108, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "h_sync: process (clock_vga, hcount)\nvariable row : integer range 0 to 1024;\nbegin\n\tif (rising_edge(clock_vga)) then \n\t hsync <= '1';\t\t\t\t\n"}
{"file": "zynq_tdc/AXITDC/sim/controlTb.vhd", "target_type": "case_statement", "cursor_line": 116, "target_nlines": 2, "node_depth": 9, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "case_statement"], "target": " run <= '1';\n end if;\n"}
{"file": "zynq_tdc/AXITDC/sim/counterTb.vhd", "target_type": "process_statement", "cursor_line": 52, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " p_SyncClkGen : process\n begin\n"}
{"file": "zynq_tdc/AXITDC/sim/encoderTb.vhd", "target_type": "entity_declaration", "cursor_line": 18, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity encoderTb is\nend encoderTb;\n"}
{"file": "zynq_tdc/AXITDC/src/AXITDC.vhd", "target_type": "entity_declaration", "cursor_line": 34, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " Port (\n \n s_axi_aclk : IN STD_LOGIC;\n s_axi_aresetn : IN STD_LOGIC;\n \n"}
{"file": "zynq_tdc/AXITDC/src/MyPkg.vhd", "target_type": "subtype_declaration", "cursor_line": 21, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "subtype_declaration"], "target": " subtype sl is std_logic;\n"}
{"file": "zynq_tdc/AXITDC/src/TDCchannel.vhd", "target_type": "architecture_body", "cursor_line": 114, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " );\n \n control:\n entity work.control(rtl)\n generic map (\n"}
{"file": "zynq_tdc/AXITDC/src/adderTreeLegacy.vhd", "target_type": "process_statement", "cursor_line": 78, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " \n result := resize(op1, BITS+1) + resize(op2, BITS+1); -- adder output\n \n offsetOut := i*(BITS+1); -- result offset within ouput vector\n"}
{"file": "zynq_tdc/AXITDC/src/control.vhd", "target_type": "process_statement", "cursor_line": 124, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " we_e <= x\"FF\";\n data_e <= (others => '0');\n addr_cnt <= addr_cnt + 1;\n \n"}
{"file": "zynq_tdc/AXITDC/src/counter.vhd", "target_type": "process_statement", "cursor_line": 39, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " process(clk)\n begin\n if rising_edge(clk) then\n count <= count + 1;\n"}
{"file": "zynq_tdc/AXITDC/src/delayLine.vhd", "target_type": "process_statement", "cursor_line": 118, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " end if;\n end process;\n"}
{"file": "zynq_tdc/AXITDC/src/encoder.vhd", "target_type": "process_statement", "cursor_line": 142, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " if rising_edge(clk) then\n ones <= sum;\n validOut <= valid; \n"}
{"file": "zynq_tdc/AXITDC/src/risingEdgeDetector.vhd", "target_type": "architecture_body", "cursor_line": 38, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " if rising_edge(clk) then\n q <= sig_i;\n end if;\n"}
{"file": "zynq_tdc/AXITDC/src/sync.vhd", "target_type": "architecture_body", "cursor_line": 59, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " C => target_clk,\n CE => '1',\n CLR => '0',\n D => asyn\n"}
{"file": "Designing-a-Custom-AXI-Slave-Peripheral/axi_rc_servo_controller_v2_00_a/axi_rc_servo_controller_v2_00_a.sim/sim_1/behav/Servo_Controller_Testbench.vhd", "target_type": "architecture_body", "cursor_line": 52, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "begin\n while (not sim_end) loop\n\t clk <= '0';\n\t wait for (clk_period / 2);\n"}
{"file": "Designing-a-Custom-AXI-Slave-Peripheral/axi_rc_servo_controller_v2_00_a/axi_rc_servo_controller_v2_00_a.sim/sim_1/behav/clock_divider_Testbench.vhd", "target_type": "entity_declaration", "cursor_line": 6, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "ENTITY clock_divider_testbench IS\nEND clock_divider_testbench;\n"}
{"file": "Designing-a-Custom-AXI-Slave-Peripheral/axi_rc_servo_controller_v2_00_a/axi_rc_servo_controller_v2_00_a.srcs/sim_1/imports/new/axi_rc_servo_controller_tb.vhd", "target_type": "entity_declaration", "cursor_line": 7, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "ENTITY axi_rc_servo_controller_testbench IS\nEND axi_rc_servo_controller_testbench;\n"}
{"file": "Designing-a-Custom-AXI-Slave-Peripheral/axi_rc_servo_controller_v2_00_a/axi_rc_servo_controller_v2_00_a.srcs/sim_1/imports/testbench_files/AXI_ADDRESS_CONTROL_CHANNEL_model.vhd", "target_type": "case_statement", "cursor_line": 66, "target_nlines": 4, "node_depth": 6, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "case_statement"], "target": " when idle =>\n next_state <= idle;\n if go = '1' then\n next_state <= running;\n"}
{"file": "Designing-a-Custom-AXI-Slave-Peripheral/axi_rc_servo_controller_v2_00_a/axi_rc_servo_controller_v2_00_a.srcs/sim_1/imports/testbench_files/AXI_READ_DATA_CHANNEL_model.vhd", "target_type": "entity_declaration", "cursor_line": 14, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\tPORT\n\t\t(\n\t\t-- User signals\n\t\tclk\t\t\t: in STD_LOGIC;\n resetn : in STD_LOGIC;\n"}
{"file": "Designing-a-Custom-AXI-Slave-Peripheral/axi_rc_servo_controller_v2_00_a/axi_rc_servo_controller_v2_00_a.srcs/sim_1/imports/testbench_files/AXI_WRITE_DATA_CHANNEL_model.vhd", "target_type": "entity_declaration", "cursor_line": 23, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\t-- AXI write data channel signals\n\t\tWDATA\t\t\t: out STD_LOGIC_VECTOR(31 downto 0);\n\t\tWSTRB\t\t\t: out STD_LOGIC_VECTOR(3 downto 0);\n"}
{"file": "Designing-a-Custom-AXI-Slave-Peripheral/axi_rc_servo_controller_v2_00_a/axi_rc_servo_controller_v2_00_a.srcs/sim_1/imports/testbench_files/AXI_WRITE_RESPONSE_CHANNEL_model.vhd", "target_type": "architecture_body", "cursor_line": 42, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " end if;\nend process;\n\n\n"}
{"file": "Designing-a-Custom-AXI-Slave-Peripheral/axi_rc_servo_controller_v2_00_a/axi_rc_servo_controller_v2_00_a.srcs/sim_1/imports/testbench_files/Servo_Controller_Testbench.vhd", "target_type": "process_statement", "cursor_line": 51, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "servo_clk_gen : process\nbegin\n while (not sim_end) loop\n\t clk <= '0';\n"}
{"file": "Designing-a-Custom-AXI-Slave-Peripheral/axi_rc_servo_controller_v2_00_a/axi_rc_servo_controller_v2_00_a.srcs/sim_1/imports/testbench_files/clock_divider_Testbench.vhd", "target_type": "entity_declaration", "cursor_line": 6, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "ENTITY clock_divider_testbench IS\nEND clock_divider_testbench;\n"}
{"file": "Designing-a-Custom-AXI-Slave-Peripheral/axi_rc_servo_controller_v2_00_a/axi_rc_servo_controller_v2_00_a.srcs/sim_1/new/AXI_lite_master_transaction_model.vhd", "target_type": "process_statement", "cursor_line": 129, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": " current_state <= next_state;\n end if;\n end if;\n"}
{"file": "Designing-a-Custom-AXI-Slave-Peripheral/axi_rc_servo_controller_v2_00_a/axi_rc_servo_controller_v2_00_a.srcs/sources_1/imports/vhdl/axi_rc_servo_controller.vhd", "target_type": "case_statement", "cursor_line": 156, "target_nlines": 1, "node_depth": 6, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "case_statement"], "target": "\t\t\tnext_state <= idle;\n"}
{"file": "Designing-a-Custom-AXI-Slave-Peripheral/axi_rc_servo_controller_v2_00_a/axi_rc_servo_controller_v2_00_a.srcs/sources_1/imports/vhdl/clock_divider.vhd", "target_type": "entity_declaration", "cursor_line": 19, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\tslow_clk : out std_logic;\n\t\tslow_rst : out std_logic\n"}
{"file": "Designing-a-Custom-AXI-Slave-Peripheral/axi_rc_servo_controller_v2_00_a/axi_rc_servo_controller_v2_00_a.srcs/sources_1/imports/vhdl/servo_controller.vhd", "target_type": "process_statement", "cursor_line": 120, "target_nlines": 2, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\telse\n\t\t\tcontrol_counter <= control_counter + 1;\n"}
{"file": "Designing-a-Custom-AXI-Slave-Peripheral/axi_rc_servo_controller_v2_00_a/axi_rc_servo_controller_v2_00_a.srcs/sources_1/imports/vhdl/servo_controller_functions_pkg.vhd", "target_type": "variable_declaration", "cursor_line": 26, "target_nlines": 1, "node_depth": 5, "node_path": ["design_file", "package_body", "declarative_part", "function_body", "declarative_part", "variable_declaration"], "target": " variable val: integer := 1;\n"}
{"file": "Pacman-TangNano9k/efinix/T80/T80.vhd", "target_type": "case_statement", "cursor_line": 694, "target_nlines": 4, "node_depth": 15, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "elsif", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "case_statement"], "target": "\t\t\t\t\tDO <= Save_Mux;\r\n\t\t\t\twhen \"11000\" =>\r\n\t\t\t\t\tSP(7 downto 0) <= unsigned(Save_Mux);\r\n\t\t\t\twhen \"11001\" =>\r\n"}
{"file": "Pacman-TangNano9k/efinix/T80/T80_ALU.vhd", "target_type": "architecture_body", "cursor_line": 213, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\t\t\tF_Out(Flag_S) <= F_In(Flag_S);\r\n\t\t\t\tF_Out(Flag_Z) <= F_In(Flag_Z);\r\n"}
{"file": "Pacman-TangNano9k/efinix/T80/T80_MCode.vhd", "target_type": "case_statement", "cursor_line": 878, "target_nlines": 2, "node_depth": 15, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "case_statement", "case_statement_alternative", "sequence_of_statements", "case_statement", "case_statement_alternative", "sequence_of_statements", "case_statement", "case_statement_alternative", "sequence_of_statements", "case_statement"], "target": "\t\t\t\t\tSet_BusB_To(2 downto 1) <= IR(5 downto 4);\r\n\t\t\t\twhen others =>\r\n"}
{"file": "Pacman-TangNano9k/efinix/T80/T80_Pack.vhd", "target_type": "component_declaration", "cursor_line": 95, "target_nlines": 4, "node_depth": 4, "node_path": ["design_file", "design_unit", "package_declaration", "declarative_part", "component_declaration"], "target": "\t\tTS : out std_logic_vector(2 downto 0);\r\n\t\tIntCycle_n : out std_logic;\r\n\t\tIntE : out std_logic;\r\n\t\tStop : out std_logic\r\n"}
{"file": "Pacman-TangNano9k/efinix/T80/T80_Reg.vhd", "target_type": "process_statement", "cursor_line": 97, "target_nlines": 5, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\t\tif WEH = '1' then\r\n\t\t\t\t\tRegsH(to_integer(unsigned(AddrA))) <= DIH;\r\n\t\t\t\tend if;\r\n\t\t\t\tif WEL = '1' then\r\n\t\t\t\t\tRegsL(to_integer(unsigned(AddrA))) <= DIL;\r\n"}
{"file": "Pacman-TangNano9k/efinix/T80/T80_RegX.vhd", "target_type": "entity_declaration", "cursor_line": 78, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\tDOBH : out std_logic_vector(7 downto 0);\r\n\t\tDOBL : out std_logic_vector(7 downto 0);\r\n\t\tDOCH : out std_logic_vector(7 downto 0);\r\n"}
{"file": "Pacman-TangNano9k/efinix/T80/T80sed.vhd", "target_type": "architecture_body", "cursor_line": 172, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\t\t\tif TState = \"010\" and Wait_n = '1' then\r\n\t\t\t\t\tDI_Reg <= DI;\r\n"}
{"file": "Pacman-TangNano9k/tangnano9k/src/T80/T80.vhd", "target_type": "case_statement", "cursor_line": 525, "target_nlines": 4, "node_depth": 21, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement", "sequence_of_statements", "if_statement", "elsif", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "if_statement", "else", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "if_statement", "else", "sequence_of_statements", "case_statement"], "target": "\t\t\t\t\t\t\tend if;\r\n\t\t\t\t\t\twhen others =>\r\n\t\t\t\t\t\t\tA <= std_logic_vector(PC);\r\n\t\t\t\t\t\tend case;\r\n"}
{"file": "Pacman-TangNano9k/tangnano9k/src/T80/T80_ALU.vhd", "target_type": "entity_declaration", "cursor_line": 77, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\tFlag_P : integer := 2;\r\n\t\tFlag_X : integer := 3;\r\n"}
{"file": "Pacman-TangNano9k/tangnano9k/src/T80/T80_MCode.vhd", "target_type": "case_statement", "cursor_line": 165, "target_nlines": 2, "node_depth": 9, "node_path": ["design_file", "design_unit", "architecture_body", "declarative_part", "function_body", "sequence_of_statements", "if_statement", "if", "sequence_of_statements", "case_statement"], "target": "\t\t\tcase cc is\r\n\t\t\twhen \"000\" => return F(7) = '0'; -- NZ\r\n"}
{"file": "Pacman-TangNano9k/tangnano9k/src/T80/T80_Pack.vhd", "target_type": "package_declaration", "cursor_line": 161, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "package_declaration"], "target": "\t\tCall : out std_logic;\r\n\t\tRstP : out std_logic;\r\n"}
{"file": "Pacman-TangNano9k/tangnano9k/src/T80/T80_Reg.vhd", "target_type": "architecture_body", "cursor_line": 103, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\t\tend if;\r\n"}
{"file": "Pacman-TangNano9k/tangnano9k/src/T80/T80_RegX.vhd", "target_type": "architecture_body", "cursor_line": 129, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\tReg1L : RAM16X1D\r\n\t\t\tport map(\r\n\t\t\tDPO => DOBL(i),\r\n\t\t\tSPO => DOAL(i),\r\n"}
{"file": "Pacman-TangNano9k/tangnano9k/src/T80/T80sed.vhd", "target_type": "entity_declaration", "cursor_line": 87, "target_nlines": 5, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\tRD_n : out std_logic;\r\n\t\tWR_n : out std_logic;\r\n\t\tRFSH_n : out std_logic;\r\n\t\tHALT_n : out std_logic;\r\n\t\tBUSAK_n : out std_logic;\r\n"}
{"file": "flearadio/rtl/generic/FMPLL_Loop_filter.vhd", "target_type": "architecture_body", "cursor_line": 27, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\tprocess(CLK, RESET)\n\tbegin \n\t\tif (RESET='1') then\n\t\t\tD1 <= (others => '0');\n"}
{"file": "flearadio/rtl/generic/FMPLL_NCO.vhd", "target_type": "process_statement", "cursor_line": 287, "target_nlines": 1, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "process(CLK, RESET)\n"}
{"file": "flearadio/rtl/generic/FMPLL_phase_detector.vhd", "target_type": "process_statement", "cursor_line": 118, "target_nlines": 3, "node_depth": 4, "node_path": ["design_file", "design_unit", "architecture_body", "concurrent_statement_part", "process_statement"], "target": "\t\t\tif (input2(4)='1') then\n\t\t\t\tpart5 <= (others => '0');\n\t\t\telse\n"}
{"file": "flearadio/rtl/generic/FMPLL_top.vhd", "target_type": "entity_declaration", "cursor_line": 16, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\t\tfmin : IN std_logic_vector(7 downto 0);\n\t\tdmout : OUT std_logic_vector (11 DOWNTO 0)\n\t);\nEND circuit ;\n"}
{"file": "flearadio/rtl/generic/FleaFPGA_FM_Radio.vhd", "target_type": "entity_declaration", "cursor_line": 49, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": " Sampler_D: in STD_LOGIC; -- Result from integrated comparator for GPIO1/10\n\n push_button1: in STD_LOGIC; -- RF Local oscillator frequency increase \n"}
{"file": "flearadio/rtl/generic/Simple_FIR.vhd", "target_type": "architecture_body", "cursor_line": 44, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\td0 <= data_in(11)&data_in(11)& data_in(11)&data_in(11)&data_in;\n\t\td1 <= d0;\n\t\td2 <= d1;\n\t\td3 <= d2;\n"}
{"file": "flearadio/rtl/generic/Simple_FIR_8bit.vhd", "target_type": "entity_declaration", "cursor_line": 17, "target_nlines": 3, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity FIR8 is\nport(clock : in std_logic;\n\treset : in std_logic; \n"}
{"file": "flearadio/rtl/generic/simple_PWM.vhd", "target_type": "entity_declaration", "cursor_line": 50, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\tpwm_value: in unsigned (11 downto 0); -- PWM value input reg\n PWM_Q: out std_logic -- PWM output pin\n"}
{"file": "flearadio/rtl/lattice/FleaFPGA_2v5_toplevel.vhd", "target_type": "architecture_body", "cursor_line": 156, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": "\t\tpush_button2 => n_pb2\n ); \r\n\nend architecture;\r\n"}
{"file": "flearadio/rtl/lattice/RF_PLL.vhd", "target_type": "entity_declaration", "cursor_line": 14, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "entity RF_PLL is\n port (\n"}
{"file": "flearadio/rtl/lattice/lfxp2_pll_25M_50M_8M33.vhd", "target_type": "architecture_body", "cursor_line": 78, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " attribute NGD_DRC_MASK of Structure : architecture is 1;\n\nbegin\n -- component instantiation statements\n"}
{"file": "flearadio/rtl/lattice/lfxp2_pll_50M_360M_10M.vhd", "target_type": "entity_declaration", "cursor_line": 20, "target_nlines": 1, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "end lfxp2_pll_50M_360M_10M;\n"}
{"file": "flearadio/rtl/lattice/lfxp2_rf_pll.vhd", "target_type": "architecture_body", "cursor_line": 19, "target_nlines": 4, "node_depth": 2, "node_path": ["design_file", "design_unit", "architecture_body"], "target": " clk_25M <= clki;\n pll_25M_50M_8M33: entity work.lfxp2_pll_25M_50M_8M33\n port map (\n clk => clk_25M,\n"}
{"file": "flearadio/rtl/lattice/ulx2s_toplevel.vhd", "target_type": "entity_declaration", "cursor_line": 45, "target_nlines": 2, "node_depth": 2, "node_path": ["design_file", "design_unit", "entity_declaration"], "target": "\tflash_so: in std_logic;\n\tflash_cen, flash_sck, flash_si: out std_logic;\n"}
|