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d6720f3 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 | {"task_id": "tiny-tpu-old", "path": "tiny-tpu-old/src/accumulator.sv", "left_context": "`default_nettype none\n`timescale 1ns/1ns\n\nmodule accumulator (\n input wire clk,\n input wire reset,\n input wire valid,\n input wire [7:0] acc_in,\n\n output reg [7:0] acc_mem_0, // Output for the first memory location\n output reg [7:0] acc_mem_1, // Output for the second memory location\n output reg full // Flag to indicate when the accumulator is full\n);\n\n // Define a register array to store multiple accumulated values\n reg [7:0] acc_mem [0:1]; // Changed to 2 entries\n reg [1:0] index; // Index to manage storage locations\n integer i; // Declare integer outside of the always block\n\n // Implement a state machine for this maybe??\n always @(posedge clk or posedge reset) begin\n if (reset) begin\n", "right_context": " acc_mem[i] <= 0;\n end\n\n index <= 0;\n full <= 0;\n acc_mem_0 <= 0;\n acc_mem_1 <= 0; \n\n end else begin\n // Nothing starts until valid (compute) flag is set! \n // Valid flag must be held high for compute to finish!\n if (valid && acc_in != 0) begin\n\n if (index < 2) begin\n acc_mem[index] <= acc_in;\n index <= index + 1;\n end else begin\n acc_mem_0 <= acc_mem[0]; \n acc_mem_1 <= acc_mem[1];\n full <= 1; \n end\n\n end \n end\n end\n\nendmodule\n", "groundtruth": " for (i = 0; i < 2; i = i + 1) begin\n", "crossfile_context": ""}
{"task_id": "tiny-tpu-old", "path": "tiny-tpu-old/src/control_unit.sv", "left_context": "`default_nettype none\n`timescale 1ns/1ns\n\nmodule control_unit (\n input wire fetch_ins,\n input wire [7:0] ui_in, \n input wire [3:0] dma_address,\n\n input wire clk,\n input wire reset,\n input wire start, \n output reg [4:0] base_address,\n output reg load_input,\n output reg load_weight,\n output reg valid,\n output reg store,\n output reg ext\n);\n\n // Instruction definitions\n localparam [7:0] NO_OP = 16'b000_00000;\n localparam [7:0] LOAD_ADDR = 16'b001_00000;\n localparam [7:0] LOAD_WEIGHT = 16'b010_00000;\n localparam [7:0] LOAD_INPUTS = 16'b011_00000;\n localparam [7:0] COMPUTE = 16'b100_00000;\n localparam [7:0] STORE = 16'b101_00000;\n localparam [7:0] EXT = 16'b111_000000;\n\n // FSM states for interal instruction dispatch\n typedef enum reg [1:0] {IDLE, FETCH, EXECUTE, FINISH} state_t;\n state_t state = IDLE;\n\n // Instruction memory\n reg [7:0] instruction_mem [0:9]; // Adjust the size as needed.\n reg [7:0] instruction; // Instruction register\n\n integer instruction_pointer;\n integer compute_cycle_counter; // Counter for compute cycles\n\n // READ instruction data from host computer\n always @(posedge clk or posedge reset) begin \n if (fetch_ins) begin\n instruction_mem[dma_address] <= ui_in; \n end\n end\n\n // Instruction decoding and control signal generation block\n always @(*) begin\n if (reset) begin // i think this creates a latch error i think. need to do the (!reset) method (look at the tt priv repo)\n base_address = 0;\n load_weight = 0;\n load_input = 0;\n valid = 0;\n store = 0;\n ext = 0;\n // instruction = 0;\n end else begin\n load_weight = 0; // clears register for this flag so its only on for two cycles\n load_input = 0;\n ext = 0;\n store = 0; \n // Dispatch\n case (instruction[7:5])\n 3'b001: base_address = instruction[4:0]; // LOAD_ADDR\n 3'b010: load_weight = 1; // LOAD_WEIGHT\n 3'b011: load_input = 1; // LOAD_INPUTS\n 3'b100: valid = 1; // VALID (COMPUTE)\n 3'b101: store = 1; // STORE\n 3'b111: ext = 1; \n default: ; // NO_OP or unrecognized instruction\n endcase\n end\n end\n\n // State transition and instruction execution block\n always @(posedge clk or posedge reset) begin\n if (reset) begin\n state <= IDLE;\n instruction_pointer <= 0;\n compute_cycle_counter <= 0;\n instruction <= 0;\n end else begin\n case (state)\n IDLE: begin\n if (start) state <= FETCH;\n end\n FETCH: begin\n instruction <= instruction_mem[instruction_pointer];\n state <= EXECUTE;\n end\n EXECUTE: begin // Program is running here!\n case (instruction)\n COMPUTE: begin\n if (compute_cycle_counter < 4) begin\n compute_cycle_counter <= compute_cycle_counter + 1;\n end else begin\n compute_cycle_counter <= 0;\n instruction_pointer <= instruction_pointer + 1;\n state <= FETCH;\n end\n end\n NO_OP: state <= FINISH;\n default: begin\n instruction_pointer <= instruction_pointer + 1;\n", "right_context": " end\n endcase\n end\n FINISH: begin // triggered on NOP instruction\n // valid <= 0; // i want to add this but gotta keep blocking and non blocking mutually excl.\n state <= FINISH;\n end\n default: state <= IDLE;\n endcase\n end\n end\n\n\nendmodule\n", "groundtruth": " state <= FETCH;\n", "crossfile_context": ""}
{"task_id": "tiny-tpu-old", "path": "tiny-tpu-old/src/dma.sv", "left_context": "`default_nettype none\n`timescale 1ns/1ns\n\nmodule dma ( \n // INPUTS\n input clk, \n input reset, \n input wire [7:0] uio_in, \n // OUTPUTS\n output wire fetch_w,\n output wire fetch_inp,\n output wire fetch_ins,\n output wire start,\n", "right_context": " assign start = (uio_in[7:5] == 3'b100) ? 1 : 0; \n assign dma_address = uio_in[3:0];\n\nendmodule\n", "groundtruth": " output wire [3:0] dma_address\n);\n\n // Combinational logic for outputs\n", "crossfile_context": ""}
{"task_id": "tiny-tpu-old", "path": "tiny-tpu-old/src/input_setup.sv", "left_context": "`default_nettype none\n`timescale 1ns/1ns\n\nmodule input_setup(\n input wire clk,\n input wire reset,\n input wire valid,\n\n input wire [7:0] a11,\n input wire [7:0] a12,\n input wire [7:0] a21,\n input wire [7:0] a22,\n\n output reg [7:0] a_in1,\n output reg [7:0] a_in2\n);\n // n + 1 cells for each row (to accommodate zero-padding)\n reg [7:0] augmented_activation_row1 [0:2];\n reg [7:0] augmented_activation_row2 [0:2];\n reg [2:0] counter;\n integer i;\n\n typedef enum reg [1:0] {IDLE, READ, WRITE} state_t;\n state_t state = IDLE;\n\n always @(posedge clk or posedge reset) begin\n if (reset) begin\n for (i = 0; i < 3; i = i + 1) begin\n augmented_activation_row1[i] <= 8'b0;\n augmented_activation_row2[i] <= 8'b0;\n end\n", "right_context": " IDLE: begin\n if (valid) begin\n state <= READ;\n end\n a_in1 <= 8'b0;\n a_in2 <= 8'b0;\n end\n READ: begin\n if (counter == 0) begin\n augmented_activation_row1[0] <= a11;\n augmented_activation_row1[1] <= a12;\n augmented_activation_row1[2] <= 8'b0;\n\n augmented_activation_row2[0] <= 8'b0;\n augmented_activation_row2[1] <= a21;\n augmented_activation_row2[2] <= a22;\n state <= WRITE;\n end\n end\n WRITE: begin\n if (counter < 3) begin\n a_in1 <= augmented_activation_row1[counter];\n a_in2 <= augmented_activation_row2[counter];\n counter <= counter + 1;\n end else begin\n state <= IDLE; \n counter <= 3'b0;\n end\n end\n \n endcase\n\n end\n end\nendmodule\n", "groundtruth": " counter <= 3'b0;\n a_in1 <= 8'b0;\n a_in2 <= 8'b0;\n state <= IDLE; \n", "crossfile_context": ""}
{"task_id": "tiny-tpu-old", "path": "tiny-tpu-old/src/mmu.sv", "left_context": "`default_nettype none\n`timescale 1ns/1ns\n\nmodule mmu (\n input wire clk,\n input wire reset,\n input wire load_weight, // Signal to load weight\n input wire valid, // Valid signal indicating new data is available\n\n input wire [7:0] a_in1, // Input A for PE(0,0)\n input wire [7:0] a_in2, // Input A for PE(1,0)\n\n input wire [7:0] weight1, // Weight for PE(0,0)\n input wire [7:0] weight2, // Weight for PE(0,1)\n input wire [7:0] weight3, // Weight for PE(1,0)\n input wire [7:0] weight4, // Weight for PE(1,1)\n\n // these values need to be stored in a register in matrix format\n output wire [7:0] acc_out1, // Accumulated value from PE(1,0)\n output wire [7:0] acc_out2 // Accumulated value from PE(1,1)\n);\n // Internal signals for connections between PEs\n wire [7:0] a_inter_01, a_inter_11;\n wire [7:0] acc_inter_00, acc_inter_01;\n\n // Instantiate PE(0,0)\n processing_element PE00 (\n .clk(clk),\n .reset(reset),\n", "right_context": " .a_out(a_inter_01),\n .acc_out(acc_inter_00)\n );\n\n // Instantiate PE(0,1)\n processing_element PE01 (\n .clk(clk),\n .reset(reset),\n .load_weight(load_weight),\n .valid(valid),\n .a_in(a_inter_01),\n .weight(weight3),\n .acc_in(8'b0), // Top-right corner has no accumulated input\n .a_out(), // no output\n .acc_out(acc_inter_01)\n );\n\n // Instantiate PE(1,0)\n processing_element PE10 (\n .clk(clk),\n .reset(reset),\n .load_weight(load_weight),\n .valid(valid),\n .a_in(a_in2),\n .weight(weight2),\n .acc_in(acc_inter_00), // Bottom-left corner gets accumulated input from PE(0,0)\n .a_out(a_inter_11),\n .acc_out(acc_out1)\n );\n\n // Instantiate PE(1,1)\n processing_element PE11 (\n .clk(clk),\n .reset(reset),\n .load_weight(load_weight),\n .valid(valid),\n .a_in(a_inter_11),\n .weight(weight4),\n .acc_in(acc_inter_01), // Bottom-right corner gets accumulated input from PE(0,1)\n .a_out(), // no output\n .acc_out(acc_out2)\n );\n\nendmodule\n", "groundtruth": " .load_weight(load_weight),\n .valid(valid),\n .a_in(a_in1),\n", "crossfile_context": ""}
{"task_id": "tiny-tpu-old", "path": "tiny-tpu-old/src/processing_element.sv", "left_context": "`default_nettype none\n`timescale 1ns/1ns\n\nmodule processing_element (\n input wire clk,\n input wire reset,\n input wire load_weight, // Signal to load weight\n input wire valid, // Valid signal indicating new data is available\n\n input wire [7:0] a_in, // Input A from left neighbor\n input wire [7:0] weight, // Weight input\n input wire [7:0] acc_in, // Accumulated value from the PE above\n", "right_context": " always @(posedge clk or posedge reset) begin\n if (reset) begin\n \n a_out <= 8'b0;\n acc_out <= 8'b0;\n weight_reg <= 8'b0;\n\n end else begin\n\n if (load_weight) begin\n weight_reg <= weight;\n end \n\n if (valid) begin // means compute!\n acc_out <= acc_in + (a_in * weight_reg);\n a_out <= a_in;\n end\n\n end\n end\nendmodule\n", "groundtruth": "\n output reg [7:0] a_out, // Output A to right neighbor\n output reg [7:0] acc_out // Accumulated value to the PE below\n);\n", "crossfile_context": ""}
{"task_id": "tiny-tpu-old", "path": "tiny-tpu-old/src/tpu.sv", "left_context": "`default_nettype none\n`timescale 1ns/1ns\n\nmodule tpu (\n // INPUTS\n input wire clk,\n input wire reset,\n input wire [7:0] ui_in, // TODO: perhaps create an assign statement to COMBINE both ui_in and uio_in so i can have a 16 bit bus??? \n input wire [7:0] uio_in, \n // OUTPUTS \n output wire [7:0] uo_out // this is uo_out (should rename to uo_out)\n);\n\n // Internal signals which connect dma controller flags to memory devices (data select flags)\n wire start; \n wire fetch_w;\n wire fetch_inp; \n wire fetch_ins; \n wire [3:0] dma_address;\n\n // \"Zero-buffered\" staggered \"x\" value matrix data transfer from input setup into mmu\n wire [7:0] a_in1;\n wire [7:0] a_in2;\n\n // Internal signals for control unit\n wire [4:0] base_address; // this is the address decoded from the ISA (ran from program mem)\n wire load_weight;\n wire load_input;\n wire valid;\n wire store;\n wire ext;\n\n // Internal signals for accumulated values from the systolic array\n wire [7:0] systolic_acc_out1;\n wire [7:0] systolic_acc_out2;\n\n // Flags from each accumulator which go high when they're full \n wire acc1_full;\n wire acc2_full;\n\n // Internal signals for weights from memory\n wire [7:0] weight1;\n wire [7:0] weight2;\n wire [7:0] weight3;\n wire [7:0] weight4;\n\n // Internal signals for output matrix individual row vectors to unified buffer\n wire [7:0] acc1_mem_0_to_ub;\n wire [7:0] acc1_mem_1_to_ub;\n wire [7:0] acc2_mem_0_to_ub;\n wire [7:0] acc2_mem_1_to_ub;\n\n // Internal signals for activation inputs from unified buffer\n wire [7:0] out_ub_to_input_setup_00;\n wire [7:0] out_ub_to_input_setup_01;\n wire [7:0] out_ub_to_input_setup_10;\n wire [7:0] out_ub_to_input_setup_11;\n\n // Instantiate direct memory controller \n dma dma ( \n // .ui_in(ui_in) delete this after -> keep it here for testing \n // INPUTS\n .clk(clk),\n .reset(reset),\n .uio_in(uio_in),\n // OUTPUTS\n .fetch_w(fetch_w),\n .fetch_inp(fetch_inp),\n .fetch_ins(fetch_ins),\n .start(start), \n .dma_address(dma_address)\n );\n\n // Instantiate the control unit\n control_unit cu (\n .fetch_ins(fetch_ins),\n .ui_in(ui_in),\n .dma_address(dma_address),\n\n .start(start),\n .clk(clk),\n .reset(reset),\n .load_weight(load_weight),\n .base_address(base_address),\n .load_input(load_input),\n .valid(valid),\n .store(store),\n .ext(ext)\n );\n\n // Instantiate the weight memory\n weight_memory wm (\n .fetch_w(fetch_w),\n .ui_in(ui_in),\n .dma_address(dma_address), \n\n .clk(clk),\n .reset(reset),\n .load_weight(load_weight),\n .addr(base_address),\n .weight1(weight1),\n .weight2(weight2),\n .weight3(weight3),\n .weight4(weight4)\n );\n\n input_setup is (\n .clk(clk),\n .reset(reset),\n .valid(valid),\n\n .a11(out_ub_to_input_setup_00),\n .a12(out_ub_to_input_setup_01),\n .a21(out_ub_to_input_setup_10),\n .a22(out_ub_to_input_setup_11),\n\n .a_in1(a_in1),\n .a_in2(a_in2)\n );\n\n // Instantiate the systolic array\n mmu systolic_array_inst (\n .clk(clk),\n .reset(reset),\n .load_weight(load_weight),\n .valid(valid),\n .a_in1(a_in1),\n .a_in2(a_in2),\n .weight1(weight1),\n .weight2(weight2),\n .weight3(weight3),\n .weight4(weight4),\n .acc_out1(systolic_acc_out1),\n .acc_out2(systolic_acc_out2)\n );\n\n // Instantiate the first accumulator\n accumulator acc1 (\n .clk(clk),\n .reset(reset),\n .valid(valid),\n .acc_in(systolic_acc_out1),\n .acc_mem_0(acc1_mem_0_to_ub),\n .acc_mem_1(acc1_mem_1_to_ub),\n .full(acc1_full)\n );\n\n // Instantiate the second accumulator\n accumulator acc2 (\n .clk(clk),\n", "right_context": " .valid(valid),\n .acc_in(systolic_acc_out2),\n .acc_mem_0(acc2_mem_0_to_ub),\n .acc_mem_1(acc2_mem_1_to_ub),\n .full(acc2_full)\n );\n\n // Instantiate the unified buffer\n unified_buffer ub (\n // INPUTS\n .ext(ext), // flag for dispatching data out of chip\n .store(store),\n .fetch_inp(fetch_inp),\n .ui_in(ui_in), \n .clk(clk),\n .reset(reset),\n .load_input(load_input),\n .full_acc1(acc1_full), // Only store when accumulator is full\n .full_acc2(acc2_full), // Only store when accumulator is full\n .acc1_mem_0(acc1_mem_0_to_ub),\n .acc1_mem_1(acc1_mem_1_to_ub),\n .acc2_mem_0(acc2_mem_0_to_ub),\n .acc2_mem_1(acc2_mem_1_to_ub),\n .addr(base_address),\n .dma_address(dma_address),\n // OUTPUTS\n .out_ub_00(out_ub_to_input_setup_00),\n .out_ub_01(out_ub_to_input_setup_01),\n .out_ub_10(out_ub_to_input_setup_10),\n .out_ub_11(out_ub_to_input_setup_11),\n .final_out(uo_out) // bus of output data wires\n );\n\nendmodule\n", "groundtruth": " .reset(reset),\n", "crossfile_context": ""}
{"task_id": "tiny-tpu-old", "path": "tiny-tpu-old/src/tt_um_tpu.sv", "left_context": "`default_nettype none\n`timescale 1ns/1ns\n\n// This module is literally just a wrapper to ensure i meet tinytapeout specifications. \n\nmodule tt_um_tpu (\n input wire [7:0] ui_in, // Dedicated inputs (make this data input)\n output wire [7:0] uo_out, // Dedicated outputs\n\n // 8 physical pins \n input wire [7:0] uio_in, // IOs: Input path (make this flag input)\n output wire [7:0] uio_out, // IOs: Output path \n \n output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)\n input wire ena, // always 1 when the design is powered, so you can ignore it\n input wire clk, // clock\n", "right_context": ");\n // wire reset = ~rst_n;\n assign uio_oe = 8'b0000_0000;\n\n tpu tpu (\n // INPUTS\n .clk(clk),\n .reset(reset),\n .ui_in(ui_in), \n .uio_in(uio_in), \n // OUTPUTS\n .uo_out(uo_out) \n ); \n\nendmodule", "groundtruth": " input wire reset // rst_n - low to reset --> // TODO: rename back to rst_n!\n", "crossfile_context": ""}
{"task_id": "tiny-tpu-old", "path": "tiny-tpu-old/src/unified_buffer.sv", "left_context": "`default_nettype none\n`timescale 1ns/1ns\n\nmodule unified_buffer (\n input wire fetch_inp,\n input wire [7:0] ui_in, \n input wire [3:0] dma_address,\n\n input wire clk,\n input wire reset,\n\n input wire full_acc1, // full flag from accumulator 1\n input wire full_acc2, // full flag from accumulator 2\n\n input wire [4:0] addr, // address to input to\n input wire load_input, // flag for loading input from own memory to input_setup buffer\n\n", "right_context": "\n // triggered on write operation \n output reg [7:0] out_ub_00,\n output reg [7:0] out_ub_01,\n output reg [7:0] out_ub_10,\n output reg [7:0] out_ub_11,\n\n output reg [7:0] final_out\n);\n\n typedef enum reg [1:0] {IDLE, WRITE_TO_HOST} state_t; // this is for taking product matrix out of chip\n state_t state = IDLE;\n\n parameter MEM_SIZE = 16;\n reg [7:0] unified_mem [0:MEM_SIZE-1];\n reg [4:0] memory_pointer; // Addressable up to 32 bits\n integer i;\n\n\n reg [4:0] addr_pointer; \n reg [4:0] end_addr; \n\n always @(posedge clk or posedge reset) begin\n if (reset) begin\n for (i = 0; i < MEM_SIZE; i = i + 1) begin\n unified_mem[i] <= 8'b0;\n end\n out_ub_00 <= 8'b0;\n out_ub_01 <= 8'b0;\n out_ub_10 <= 8'b0;\n out_ub_11 <= 8'b0;\n final_out <= 8'b0;\n end_addr <= 5'b0; \n addr_pointer <= 5'b0;\n end else begin\n // READ FROM MEMORY (perhaps put this into the FSM?)\n if (load_input) begin\n out_ub_00 <= unified_mem[addr]; \n out_ub_01 <= unified_mem[addr + 1]; \n out_ub_10 <= unified_mem[addr + 2]; \n out_ub_11 <= unified_mem[addr + 3]; \n end\n\n // STORE HOST COMPUTER VALUES TO MEMORY (perhaps put this into the FSM?)\n if (fetch_inp) begin\n unified_mem[dma_address] <= ui_in;\n end\n\n // STORE PRODUCT MATRIX TO MEMORY (perhaps put this into the FSM?)\n if (store && full_acc1 && full_acc2) begin \n unified_mem[addr] <= acc1_mem_0;\n unified_mem[addr + 1] <= acc1_mem_1;\n unified_mem[addr + 2] <= acc2_mem_0;\n unified_mem[addr + 3] <= acc2_mem_1;\n end\n\n // State machine for handling product matrix output\n case (state)\n IDLE: begin\n final_out <= 8'b0; \n end_addr <= 5'b0; \n addr_pointer <= 5'b0;\n if (ext) begin // flag for writing product matrix to output\n state <= WRITE_TO_HOST;\n addr_pointer <= addr; \n end_addr <= addr + 4; \n end \n end\n WRITE_TO_HOST: begin\n if (addr_pointer < end_addr) begin\n final_out <= unified_mem[addr_pointer];\n addr_pointer <= addr_pointer + 1; \n end else begin\n state <= IDLE; \n end\n end\n endcase\n \n end\n end\nendmodule\n", "groundtruth": " input wire store, // flag for storing data from accumulators to unified buffer\n input wire ext, // flag for output to host computer\n\n input wire [7:0] acc1_mem_0,\n", "crossfile_context": ""}
{"task_id": "tiny-tpu-old", "path": "tiny-tpu-old/src/weight_memory.sv", "left_context": "`default_nettype none\n`timescale 1ns/1ns\n\nmodule weight_memory (\n input wire fetch_w, \n input wire [7:0] ui_in, \n input wire [3:0] dma_address,\n\n input wire clk,\n input wire reset,\n input wire load_weight, \n input wire [4:0] addr, // 5 bit address but only need 3 of those bits to address 8 cells. \n output reg [7:0] weight1,\n output reg [7:0] weight2,\n output reg [7:0] weight3,\n output reg [7:0] weight4\n);\n reg [7:0] memory [0:7]; // Simple memory to store weights (only 8 addresses)\n integer i;\n \n always @(posedge clk or posedge reset) begin\n if (reset) begin\n for (i = 0; i < 8; i++) begin\n memory[i] <= 8'b0;\n end\n weight1 <= 8'b0;\n weight2 <= 8'b0;\n weight3 <= 8'b0;\n", "right_context": " weight2 <= memory[addr + 1];\n weight3 <= memory[addr + 2];\n weight4 <= memory[addr + 3];\n\n end \n end\nendmodule\n", "groundtruth": " weight4 <= 8'b0;\n\n end else if (fetch_w) begin // READ data into weight memory \n memory[dma_address] <= ui_in;\n", "crossfile_context": ""}
{"task_id": "tiny-tpu-old", "path": "tiny-tpu-old/test/dump_acc.sv", "left_context": "", "right_context": "", "groundtruth": "module dump();\n initial begin\n $dumpfile (\"acc.vcd\");\n $dumpvars (0, accumulator);\n", "crossfile_context": ""}
{"task_id": "tiny-tpu-old", "path": "tiny-tpu-old/test/dump_dma.sv", "left_context": "module dump();\n initial begin\n $dumpfile (\"dma.vcd\");\n $dumpvars (0, dma);\n\n $dumpvars(0, dma.test_storage[0]);\n $dumpvars(0, dma.test_storage[1]);\n", "right_context": " end\nendmodule\n", "groundtruth": " $dumpvars(0, dma.test_storage[2]);\n $dumpvars(0, dma.test_storage[3]);\n\n $dumpvars(0, dma.test_storage[4]);\n", "crossfile_context": ""}
{"task_id": "tiny-tpu-old", "path": "tiny-tpu-old/test/dump_is.sv", "left_context": "module dump();\n initial begin\n $dumpfile (\"is.vcd\");\n $dumpvars (0, input_setup);\n", "right_context": "", "groundtruth": " #1;\n end\nendmodule\n", "crossfile_context": ""}
{"task_id": "tiny-tpu-old", "path": "tiny-tpu-old/test/dump_mmu.sv", "left_context": "", "right_context": " end\nendmodule\n", "groundtruth": "module dump();\n initial begin\n $dumpfile (\"mmu.vcd\");\n", "crossfile_context": ""}
{"task_id": "tiny-tpu-old", "path": "tiny-tpu-old/test/dump_tpu.sv", "left_context": "module dump();\n initial begin\n $dumpfile (\"tpu.vcd\");\n", "right_context": "", "groundtruth": " $dumpvars (0, tpu);\n #1;\n end\nendmodule\n", "crossfile_context": ""}
{"task_id": "tiny-tpu-old", "path": "tiny-tpu-old/test/dump_tt_um_tpu.sv", "left_context": "module dump();\n", "right_context": "", "groundtruth": " initial begin\n $dumpfile (\"tt_um_tpu.vcd\");\n $dumpvars (0, tt_um_tpu);\n #1;\n end\n", "crossfile_context": ""}
{"task_id": "tiny-tpu-old", "path": "tiny-tpu-old/test/dump_weight_memory.sv", "left_context": "module dump();\n initial begin\n $dumpfile (\"wm.vcd\");\n $dumpvars (0, weight_memory);\n\n\n $dumpvars (0, weight_memory.memory[0]);\n $dumpvars (0, weight_memory.memory[1]);\n $dumpvars (0, weight_memory.memory[2]);\n", "right_context": "\n // these are just to ensure that the memory doesnt go here\n $dumpvars (0, weight_memory.memory[4]);\n $dumpvars (0, weight_memory.memory[5]);\n #1;\n end\nendmodule\n", "groundtruth": " $dumpvars (0, weight_memory.memory[3]);\n", "crossfile_context": ""}
{"task_id": "usb20dev", "path": "usb20dev/rtl/usb.sv", "left_context": "//==============================================================================\n// USB 2.0 FS Device controller core\n//\n// References:\n// - Universal Serial Bus Specification Revision 2.0\n// - UTMI specification, version 1.05.\n// - USB 101: An Introduction to Universal Serial Bus 2.0 (AN57294)\n// - USB in a Nutshell\n// - USB Made Simple\n//\n//------------------------------------------------------------------------------\n// [usb20dev] 2018 Eden Synrez <esynr3z@gmail.com>\n//==============================================================================\n\nimport usb_pkg::*;\n\nmodule usb (\n input logic clk_48m, // Clock 48 MHz\n input logic rst, // Asynchronous reset\n\n usb_fe_if.ctrl fe_ctrl // USB frontend control\n);\n\nusb_sie_if sie_bus();\n\nusb_sie sie(\n .clk (clk_48m), // i: Clock\n .rst (rst), // i: Asynchronous reset\n .fe_ctrl (fe_ctrl), // if: USB frontend control\n .sie_bus (sie_bus.sie) // if: SIE Data Bus\n);\n\n", "right_context": "", "groundtruth": "endmodule : usb\n", "crossfile_context": ""}
{"task_id": "usb20dev", "path": "usb20dev/rtl/usb_crc16.sv", "left_context": "//==============================================================================\n// USB CRC16 calculation and checking. Parallel load with serializer inside.\n//\n// Polynomial:\n// G(X) = X^16 + X^15 + + X^2 + 1\n// Bit representation:\n// 1000000000000101\n//\n//------------------------------------------------------------------------------\n// [usb20dev] 2018 Eden Synrez <esynr3z@gmail.com>\n//==============================================================================\n\nimport usb_pkg::*;\n\nmodule usb_crc16(\n input logic clk, // Clock\n input logic rst, // Asynchronous reset\n\n input bus8_t data, // Input data\n input logic wr, // Data write strobe\n input logic clear, // Init CRC with default value\n output logic busy, // CRC is being calculated\n output bus16_t crc // CRC data\n);\n\n//-----------------------------------------------------------------------------\n// Data serializer\n//-----------------------------------------------------------------------------\nbus8_t dbyte;\nlogic dbit;\nlogic [2:0] dbit_cnt;\n\nalways_ff @(posedge clk or posedge rst)\nbegin\n if (rst)\n busy <= 1'b0;\n else if (wr)\n busy <= 1'b1;\n else if (dbit_cnt == '1)\n busy <= 1'b0;\nend\n\nalways_ff @(posedge clk or posedge rst)\nbegin\n if (rst)\n dbyte <= 'h0;\n else if (wr)\n dbyte <= data;\n else if (busy)\n dbyte <= {1'b0, dbyte[7:1]};\nend\n\nalways_ff @(posedge clk or posedge rst)\nbegin\n if (rst)\n dbit_cnt <= '0;\n else if (busy)\n dbit_cnt <= dbit_cnt + 1;\n else\n dbit_cnt <= '0;\nend\n\nassign dbit = dbyte[0];\n\n//-----------------------------------------------------------------------------\n// CRC5 calculation and checking\n//-----------------------------------------------------------------------------\nlogic crc_in;\nlogic [15:0] crc_next;\nlogic crc_en;\n\nassign crc_in = dbit^crc[15];\nassign crc_next = {crc[14]^crc_in, crc[13:2], crc[1]^crc_in, crc[0], crc_in};\n", "right_context": " else if (busy)\n crc <= crc_next;\n else if (clear)\n crc <= '1;\nend\n\nendmodule : usb_crc16\n", "groundtruth": "\nalways_ff @(posedge clk or posedge rst)\nbegin\n", "crossfile_context": ""}
{"task_id": "usb20dev", "path": "usb20dev/rtl/usb_crc5.sv", "left_context": "//==============================================================================\n// USB CRC5 calculation and checking. Parallel load with serializer inside.\n//\n// Polynomial:\n// G(X) = X^5 + X^2 + 1\n// Bit representation:\n// 00101\n//\n//------------------------------------------------------------------------------\n// [usb20dev] 2018 Eden Synrez <esynr3z@gmail.com>\n//==============================================================================\n\nimport usb_pkg::*;\n\nmodule usb_crc5(\n input logic clk, // Clock\n input logic rst, // Asynchronous reset\n\n input bus8_t data, // Input data\n input logic wr, // Data write strobe\n input logic clear, // Init CRC with default value\n output logic busy, // CRC is being calculated\n output logic [4:0] crc // CRC data\n);\n\n", "right_context": " if (rst)\n busy <= 1'b0;\n else if (wr)\n busy <= 1'b1;\n else if (dbit_cnt == '1)\n busy <= 1'b0;\nend\n\nalways_ff @(posedge clk or posedge rst)\nbegin\n if (rst)\n dbyte <= 'h0;\n else if (wr)\n dbyte <= data;\n else if (busy)\n dbyte <= {1'b0, dbyte[7:1]};\nend\n\nalways_ff @(posedge clk or posedge rst)\nbegin\n if (rst)\n dbit_cnt <= '0;\n else if (busy)\n dbit_cnt <= dbit_cnt + 1;\n else\n dbit_cnt <= '0;\nend\n\nassign dbit = dbyte[0];\n\n//-----------------------------------------------------------------------------\n// CRC5 calculation and checking\n//-----------------------------------------------------------------------------\nlogic crc_in;\nlogic [4:0] crc_next;\nlogic crc_en;\n\nassign crc_en = busy;\nassign crc_in = dbit^crc[4];\nassign crc_next = {crc[3], crc[2], crc[1]^crc_in, crc[0], crc_in};\n\nalways_ff @(posedge clk or posedge rst)\nbegin\n if (rst)\n crc <= '1;\n else if (crc_en)\n crc <= crc_next;\n else if (clear)\n crc <= '1;\nend\n\nendmodule : usb_crc5\n", "groundtruth": "//-----------------------------------------------------------------------------\n// Data serializer\n//-----------------------------------------------------------------------------\nbus8_t dbyte;\nlogic dbit;\n", "crossfile_context": ""}
{"task_id": "usb20dev", "path": "usb20dev/rtl/usb_fe_if.sv", "left_context": "//==============================================================================\n// Interface to USB \"analog\" frontend\n//\n//------------------------------------------------------------------------------\n// [usb20dev] 2018 Eden Synrez <esynr3z@gmail.com>\n//==============================================================================\n\ninterface usb_fe_if ();\n\nlogic dp_rx; // USB Data+ input\nlogic dn_rx; // USB Data- input\nlogic dp_tx; // USB Data+ output\nlogic dn_tx; // USB Data- output\nlogic tx_oen; // USB Data output enable\nlogic pu; // USB Data+ pullup control\n\nmodport ctrl (\n input dp_rx,\n input dn_rx,\n output dp_tx,\n output dn_tx,\n", "right_context": " output pu\n);\n\n// Analog frontend imitation\n//\n// .---------------- pu\n// |\n// .--.\n// | |\n// | | .----------> dp_rx\n// | | | .\n// '--' | /|\n// | | / |\n// dp <--------o----o---. |<--- dp_tx\n// \\ |\n// dn <--------. ^\\|\n// | | '\n// | .------ tx_oen\n// | | .\n// | v/|\n// | / |\n// '----o---. |<--- dn_tx\n// | \\ |\n// | \\|\n// | '\n// '----------> dn_rx\n\nwire dn; // USB D- line\nwire dp; // USB D+ line\n\nassign dp = tx_oen ? dp_tx : 1'bz;\nassign dn = tx_oen ? dn_tx : 1'bz;\nassign dp_rx = dp;\nassign dn_rx = dn;\n\nmodport phy (\n output pu,\n inout dn,\n inout dp\n);\n\nendinterface : usb_fe_if\n", "groundtruth": " output tx_oen,\n", "crossfile_context": ""}
{"task_id": "usb20dev", "path": "usb20dev/rtl/usb_pkg.sv", "left_context": "//==============================================================================\n// Package with global USB types and parameters\n//\n//------------------------------------------------------------------------------\n// [usb20dev] 2018 Eden Synrez <esynr3z@gmail.com>\n//==============================================================================\n\npackage usb_pkg;\n\n//-----------------------------------------------------------------------------\n// Types\n//-----------------------------------------------------------------------------\ntypedef logic [7:0] bus8_t;\ntypedef logic [15:0] bus16_t;\n", "right_context": "\ntypedef enum logic [1:0] {\n USB_LS_SE0 = 2'b00,\n USB_LS_J = 2'b01,\n USB_LS_K = 2'b10,\n USB_LS_SE1 = 2'b11\n} usb_line_state_t;\n\n//-----------------------------------------------------------------------------\n// Parameters\n//-----------------------------------------------------------------------------\nparameter USB_STUFF_BITS_N = 6;\nparameter bus8_t USB_SYNC_VAL = 'h80;\n\nparameter usb_line_state_t [7:0] USB_SYNC_PATTERN = {\n USB_LS_K, USB_LS_J, USB_LS_K, USB_LS_J,\n USB_LS_K, USB_LS_J, USB_LS_K, USB_LS_K\n};\nparameter usb_line_state_t [2:0] USB_EOP_PATTERN = {\n USB_LS_SE0, USB_LS_SE0, USB_LS_J\n};\n\nparameter logic [4:0] USB_CRC5_VALID = 5'b01100;\nparameter bus16_t USB_CRC16_VALID = 16'b1000000000001101;\n\nendpackage : usb_pkg\n", "groundtruth": "typedef logic [31:0] bus32_t;\n", "crossfile_context": ""}
{"task_id": "usb20dev", "path": "usb20dev/rtl/usb_sie.sv", "left_context": "//==============================================================================\n// USB Serial Interface Engine with 8 bit interface\n//\n// Main functions:\n// - Bit stuffing / unstuffing\n// - NRZI encoding / decoding\n// - SYNC and EOP handling\n// - Serial-Parallel / Parallel-Serial Conversion\n//\n// Based on:\n// - UTMI specification, version 1.05.\n// - Universal Serial Bus Specification Revision 2.0, Ch. 7\n//\n//------------------------------------------------------------------------------\n// [usb20dev] 2018 Eden Synrez <esynr3z@gmail.com>\n//==============================================================================\n\nimport usb_pkg::*;\n\nmodule usb_sie (\n input logic clk, // Clock\n input logic rst, // Asynchronous reset\n\n usb_fe_if.ctrl fe_ctrl, // USB frontend control\n\n usb_sie_if.sie sie_bus // SIE Data Bus\n);\n\n//-----------------------------------------------------------------------------\n// Receive side\n//-----------------------------------------------------------------------------\nusb_sie_rx rx (\n .clk (clk), // i: Clock\n .rst (rst), // i: Asynchronous reset\n\n .dn_rx (fe_ctrl.dn_rx), // i: USB Data- input\n .dp_rx (fe_ctrl.dp_rx), // i: USB Data+ input\n\n .tx_active (sie_bus.tx_active), // i: Transmit state machine is active\n .rx_data (sie_bus.rx_data), // o: Received USB data\n .rx_valid (sie_bus.rx_valid), // o: rx_data bus has valid data\n .rx_active (sie_bus.rx_active), // o: Receive state machine is active (from detecting SYNC to detecting EOP)\n .rx_error (sie_bus.rx_error), // o: Receive error detection (bitstuff error)\n", "right_context": "//-----------------------------------------------------------------------------\n// Transmit side\n//-----------------------------------------------------------------------------\nusb_sie_tx tx (\n .clk (clk), // i: Clock\n .rst (rst), // i: Asynchronous reset\n\n .dp_tx (fe_ctrl.dp_tx), // o: USB Data+ output\n .dn_tx (fe_ctrl.dn_tx), // o: USB Data- output\n .tx_oen (fe_ctrl.tx_oen), // o: USB Data output enable\n\n .tx_data (sie_bus.tx_data), // i: USB data to transmit\n .tx_valid (sie_bus.tx_valid), // i: Data on tx_data bus is valid\n .tx_ready (sie_bus.tx_ready), // o: SIE ready to load transmit data into holding registers\n .tx_active (sie_bus.tx_active) // o: Transmit state machine is active (from SYNC sending start to EOP sending end)\n);\n\n// FIXME: fix pullup control\nassign fe_ctrl.pu = 1'b1;\n\nendmodule : usb_sie\n", "groundtruth": " .bus_reset (sie_bus.reset) // o: Bus reset active\n);\n", "crossfile_context": ""}
{"task_id": "usb20dev", "path": "usb20dev/rtl/usb_sie_if.sv", "left_context": "//==============================================================================\n// SIE interface signals\n//\n//------------------------------------------------------------------------------\n// [usb20dev] 2018 Eden Synrez <esynr3z@gmail.com>\n//==============================================================================\n\nimport usb_pkg::*;\n\ninterface usb_sie_if ();\n\nlogic reset; // USB line reset active\n\nbus8_t tx_data; // USB data to transmit\nlogic tx_valid; // Data on tx_data bus is valid\nlogic tx_ready; // SIE ready to load transmit data into holding registers\nlogic tx_active; // Transmit state machine is active (from SYNC sending start to EOP sending end)\n\n// Example of packet transmission\n// .---------------------------------.\n// tx_valid | |\n// -----' '-----------------------\n// ----. .--. .--------------. .----------------------------------\n// tx_data xxx X B0 X BYTE1 X BYTE2\n// ----' '--' '--------------' '----------------------------------\n// .-. .-. .-.\n// tx_ready | | | | | |\n// --------' '--------------' '-------' '-------------------------\n// .-----------------------------------------------.\n// tx_active | |\n// ------------' '--\n// .-------. .-------. .-------. .-------. .---.\n// D+/D- ----IDLE-----< SYNC X BYTE0 X BYTE1 X BYTE2 X EOP >---\n// '-------' '-------' '-------' '-------' '---'\n\nbus8_t rx_data; // Received USB data\nlogic rx_valid; // rx_data bus has valid data\nlogic rx_active; // Receive state machine is active (from detecting SYNC to detecting EOP)\nlogic rx_error; // Receive error detection (bitstuff error)\n\n// Example of packet reception\n// .-------. .-------. .-------. .-------. .---.\n// D+/D- --IDLE--< SYNC X BYTE0 X BYTE1 X BYTE2 X EOP >--IDLE--\n// '-------' '-------' '-------' '-------' '---'\n// .-----------------------------------.\n// rx_active | |\n// -------------------' '-------\n// ---------------------------. .-------. .-------. .-------------\n// xxx X BYTE0 X BYTE1 X BYTE2\n// rx_data ---------------------------' '-------' '-------' '-------------\n// .-. .-. .-.\n// | | | | | |\n// rx_valid ----------------------------' '-------' '-------' '------------\n// .-.\n// | |\n// rx_error ------------------------------------------' '------------------\n// NOTE: rx_error can be asserted in any time bitstuff error occured.\n// PE should ignore the whole packet after that.\n\n// Serial Interface Engine side\nmodport sie (\n output reset,\n\n input tx_data,\n input tx_valid,\n output tx_ready,\n output tx_active,\n\n output rx_data,\n output rx_valid,\n output rx_active,\n", "right_context": ");\n\n// Protocol Engine side\nmodport pe (\n input reset,\n\n output tx_data,\n output tx_valid,\n input tx_ready,\n input tx_active,\n\n input rx_data,\n input rx_valid,\n input rx_active,\n input rx_error\n);\n\nendinterface : usb_sie_if\n", "groundtruth": " output rx_error\n", "crossfile_context": ""}
{"task_id": "usb20dev", "path": "usb20dev/rtl/usb_sie_rx.sv", "left_context": "//==============================================================================\n// SIE receive side:\n// - data recovery from line states\n// - NRZI decoder\n// - bit unstuffer\n// - receive FSM\n//\n//------------------------------------------------------------------------------\n// [usb20dev] 2018 Eden Synrez <esynr3z@gmail.com>\n//==============================================================================\n\nimport usb_pkg::*;\n\nmodule usb_sie_rx (\n input logic clk, // Clock\n input logic rst, // Asynchronous reset\n\n // Frontend rx\n input logic dn_rx, // USB Data- input\n input logic dp_rx, // USB Data+ input\n\n // SIE rx\n input logic tx_active, // Transmit state machine is active\n output bus8_t rx_data, // USB data output bus\n output logic rx_valid, // rx_data bus has valid data\n output logic rx_active, // Receive state machine is active\n output logic rx_error, // Receive error detection\n output logic bus_reset // Bus reset active\n);\n\nlocalparam LINE_STATE_HIST_LEN = 3;\n\n//-----------------------------------------------------------------------------\n// Line state recovery\n//-----------------------------------------------------------------------------\n// Double-flop synchronization for input data lines\nlogic [3:0] line_pair_ff;\nusb_line_state_t line_pair;\nusb_line_state_t line_state_curr;\nlogic line_trans;\nlogic line_idle;\nlogic detect_eop;\n\nalways_ff @(posedge clk)\nbegin\n if (rst)\n line_pair_ff <= {USB_LS_J, USB_LS_J};\n else\n line_pair_ff <= {line_pair_ff[1:0], dn_rx, dp_rx};\nend\n\nassign line_pair = usb_line_state_t'(line_pair_ff[3:2]);\n\n// We dont use true diff pair, so we have to handle data transition moments\n// and change line state one clock after transition.\n// It is supposed, that transition period is shorter than sample clock period.\n\nalways_ff @(posedge clk or posedge rst)\nbegin\n if (rst)\n line_trans <= 1'b0;\n else if ((line_state_curr != line_pair) && !line_trans)\n line_trans <= 1'b1;\n else\n line_trans <= 1'b0;\nend\n\nalways_ff @(posedge clk or posedge rst)\nbegin\n if (rst)\n line_state_curr <= USB_LS_J;\n else if (line_trans)\n line_state_curr <= line_pair;\nend\n\n// Generate valid signal in the middle of each bit\nlogic [1:0] line_phase_cnt;\nlogic line_state_valid;\n\nalways_ff @(posedge clk or posedge rst)\nbegin\n if (rst)\n line_phase_cnt <= '0;\n else if (line_trans)\n line_phase_cnt <= '0;\n else\n line_phase_cnt <= line_phase_cnt + 'b1;\nend\n\nassign line_state_valid = (line_phase_cnt == 'b1) ? 1'b1 : 1'b0;\n\n// Push line states to the history buffer for NRZI decoding and EOP detection\nusb_line_state_t [LINE_STATE_HIST_LEN-1:0] line_state_hist;\n\nalways_ff @(posedge clk or posedge rst)\nbegin\n for (int i = 0; i < LINE_STATE_HIST_LEN; i++) begin\n if (rst)\n line_state_hist[i] <= USB_LS_J;\n else if (line_state_valid && (i == 0)) begin\n line_state_hist[i] <= line_state_curr;\n end else if (line_state_valid) begin\n line_state_hist[i] <= line_state_hist[i-1];\n end\n end\nend\n\nassign detect_eop = (line_state_hist == USB_EOP_PATTERN);\n\n//-----------------------------------------------------------------------------\n// NRZI decoder\n//-----------------------------------------------------------------------------\nlogic dec_nrzi_bit;\nlogic dec_nrzi_valid;\n\nalways_comb\nbegin\n if ((line_state_hist[1] == USB_LS_J) &&\n (line_state_hist[0] == USB_LS_J)) begin\n dec_nrzi_bit = 1'b1;\n dec_nrzi_valid = line_state_valid;\n end else if ((line_state_hist[1] == USB_LS_J) &&\n (line_state_hist[0] == USB_LS_K)) begin\n dec_nrzi_bit = 1'b0;\n dec_nrzi_valid = line_state_valid;\n end else if ((line_state_hist[1] == USB_LS_K) &&\n (line_state_hist[0] == USB_LS_J)) begin\n dec_nrzi_bit = 1'b0;\n dec_nrzi_valid = line_state_valid;\n end else if ((line_state_hist[1] == USB_LS_K) &&\n (line_state_hist[0] == USB_LS_K)) begin\n dec_nrzi_bit = 1'b1;\n dec_nrzi_valid = line_state_valid;\n end else begin\n dec_nrzi_bit = 1'b0;\n dec_nrzi_valid = 1'b0;\n end\nend\n\n//-----------------------------------------------------------------------------\n// Bit unstuffer\n//-----------------------------------------------------------------------------\nlogic [USB_STUFF_BITS_N-1:0] unstuff_shift;\nlogic unstuff_event;\nlogic unstuff_error;\n\nalways_ff @(posedge clk or posedge rst)\nbegin\n if (rst)\n unstuff_shift <= '0;\n else if (dec_nrzi_valid)\n unstuff_shift <= {unstuff_shift[USB_STUFF_BITS_N-2:0], dec_nrzi_bit};\nend\n\nassign unstuff_event = (unstuff_shift == '1);\nassign unstuff_error = unstuff_event && (dec_nrzi_bit != 1'b0);\n\n//-----------------------------------------------------------------------------\n// Data bitstream control\n//-----------------------------------------------------------------------------\nlogic data_bit;\nlogic data_bit_valid;\nbus8_t data_shift;\nlogic detect_sync;\n\nassign data_bit = dec_nrzi_bit;\nassign data_bit_valid = dec_nrzi_valid && (!unstuff_event || line_idle) && (!tx_active);\n\nalways_ff @(posedge clk or posedge rst)\nbegin\n if (rst)\n data_shift <= '1;\n else if (detect_eop)\n data_shift <= '1;\n else if (data_bit_valid)\n data_shift <= {data_bit, data_shift[7:1]};\nend\n\n// SYNC and Idle detection\nassign detect_sync = (data_shift == USB_SYNC_VAL);\n\nalways_ff @(posedge clk or posedge rst)\nbegin\n if (rst)\n line_idle <= 1'b1;\n else if (detect_sync && line_idle)\n line_idle <= 1'b0;\n else if (detect_eop)\n line_idle <= 1'b1;\nend\n\n//-----------------------------------------------------------------------------\n// Receive state machine\n//-----------------------------------------------------------------------------\nenum logic [2:0] {\n RX_WAIT_S,\n STRIP_SYNC_S,\n RX_DATA_S,\n STRIP_EOP_S,\n ERROR_S,\n ABORT_S,\n TERMINATE_S,\n XXX_S = 'x\n} fsm_state, fsm_next;\n\nalways_ff @(posedge clk or posedge rst)\nbegin\n if (rst)\n fsm_state <= RX_WAIT_S;\n else\n fsm_state <= fsm_next;\nend\n\nalways_comb\nbegin\n fsm_next = XXX_S;\n case (fsm_state)\n RX_WAIT_S : begin\n if (detect_sync && (!tx_active))\n fsm_next = STRIP_SYNC_S;\n else\n fsm_next = RX_WAIT_S;\n end\n\n STRIP_SYNC_S : begin\n fsm_next = RX_DATA_S;\n end\n\n RX_DATA_S : begin\n if (unstuff_error)\n fsm_next = ERROR_S;\n else if (detect_eop)\n fsm_next = STRIP_EOP_S;\n else\n fsm_next = RX_DATA_S;\n end\n\n STRIP_EOP_S : begin\n fsm_next = RX_WAIT_S;\n end\n\n ERROR_S : begin\n fsm_next = ABORT_S;\n end\n\n ABORT_S : begin\n if (line_idle)\n fsm_next = TERMINATE_S;\n else\n fsm_next = ABORT_S;\n end\n\n TERMINATE_S : begin\n fsm_next = RX_WAIT_S;\n end\n endcase\nend\n\nlogic [3:0] data_bit_cnt;\nbus8_t data_hold;\nlogic data_valid;\nlogic data_active;\nlogic data_error;\n\nalways_ff @(posedge clk or posedge rst)\nbegin\n if (rst) begin\n data_bit_cnt <= '0;\n data_hold <= '0;\n data_valid <= 1'b0;\n data_active <= 1'b0;\n data_error <= 1'b0;\n end else begin\n case (fsm_state)\n RX_WAIT_S : begin\n data_bit_cnt <= '0;\n end\n\n STRIP_SYNC_S : begin\n data_active <= 1'b1;\n end\n\n RX_DATA_S : begin\n // count shifted data bits\n if (data_bit_valid) begin\n if (data_bit_cnt == 'd8)\n data_bit_cnt <= 'd1;\n else\n data_bit_cnt <= data_bit_cnt + 1;\n end\n // hold data when byte accumulated\n if (data_bit_cnt == 'd8) begin\n data_hold <= data_shift;\n data_valid <= 1'b1;\n end else\n data_valid <= 1'b0;\n end\n", "right_context": "\n ERROR_S : begin\n data_error = 1'b1;\n end\n\n ABORT_S : begin\n data_valid = 1'b0;\n data_error = 1'b0;\n end\n\n TERMINATE_S : begin\n data_active = 1'b0;\n end\n endcase\n end\nend\n\n// Data valid should be a pulse for FS\nlogic data_valid_ff;\nlogic data_valid_pulse;\n\nalways_ff @(posedge clk or posedge rst)\nbegin\n if (rst) begin\n data_valid_ff <= 1'b0;\n end else begin\n data_valid_ff <= data_valid;\n end\nend\n\nassign data_valid_pulse = data_valid && (!data_valid_ff);\n\n//-----------------------------------------------------------------------------\n// Bus reset detection\n//-----------------------------------------------------------------------------\nlogic line_reset;\nbus8_t line_reset_cnt;\n\nalways_ff @(posedge clk or posedge rst)\nbegin\n if (rst)\n line_reset_cnt <= '0;\n else if (!line_reset && (line_state_hist[0] == USB_LS_SE0))\n line_reset_cnt <= line_reset_cnt + 'b1;\n else\n line_reset_cnt <= '0;\nend\n\nalways_ff @(posedge clk or posedge rst)\nbegin\n if (rst)\n line_reset <= 1'b0;\n else if (!line_reset && (line_reset_cnt == '1))\n line_reset <= 1'b1;\n else if (line_reset && (line_state_hist[0] != USB_LS_SE0))\n line_reset <= 1'b0;\nend\n\n//-----------------------------------------------------------------------------\n// Outputs registering stage\n//-----------------------------------------------------------------------------\nalways_ff @(posedge clk or posedge rst)\nbegin\n if (rst) begin\n rx_data <= '0;\n rx_valid <= 1'b0;\n rx_active <= 1'b0;\n rx_error <= 1'b0;\n bus_reset <= 1'b0;\n end else begin\n rx_data <= data_hold;\n rx_valid <= data_valid_pulse;\n rx_active <= data_active;\n rx_error <= data_error;\n bus_reset <= line_reset;\n end\nend\n\nendmodule : usb_sie_rx\n", "groundtruth": "\n STRIP_EOP_S : begin\n data_valid = 'b0;\n", "crossfile_context": ""}
{"task_id": "usb20dev", "path": "usb20dev/rtl/usb_sie_tx.sv", "left_context": "//==============================================================================\n// SIE transmit side:\n// - NRZI encoder\n// - bit stuffer\n// - data to line states convert\n// - transmit FSM\n//\n//------------------------------------------------------------------------------\n// [usb20dev] 2018 Eden Synrez <esynr3z@gmail.com>\n//==============================================================================\n\nimport usb_pkg::*;\n\nmodule usb_sie_tx (\n input logic clk, // Clock\n input logic rst, // Asynchronous reset\n\n // Frontend tx\n output logic dp_tx, // USB Data+ output\n output logic dn_tx, // USB Data- output\n output logic tx_oen, // USB Data output enable\n\n // SIE tx\n input bus8_t tx_data, // USB data input bus\n input logic tx_valid, // Transmit data on tx_data bus is valid\n output logic tx_ready, // UTM ready to load transmit data into holding registers\n output logic tx_active // Transmit state machine is active (from SYNC sending start to EOP sending end)\n);\n\n//-----------------------------------------------------------------------------\n// Transmit state machine\n//-----------------------------------------------------------------------------\nlogic data_hold_full;\nlogic data_oen;\nlogic data_se0;\n\nenum logic [2:0] {\n TX_WAIT_S,\n SEND_SYNC_S,\n TX_DATA_LOAD_S,\n", "right_context": "\nalways_ff @(posedge clk or posedge rst)\nbegin\n if (rst)\n fsm_state <= TX_WAIT_S;\n else\n fsm_state <= fsm_next;\nend\n\nalways_comb\nbegin\n fsm_next = XXX_S;\n case (fsm_state)\n TX_WAIT_S : begin\n if (tx_valid)\n fsm_next = SEND_SYNC_S;\n else\n fsm_next = TX_WAIT_S;\n end\n\n SEND_SYNC_S : begin\n fsm_next = TX_DATA_LOAD_S;\n end\n\n TX_DATA_LOAD_S : begin\n if ((!tx_valid) && (!data_oen))\n fsm_next = TX_WAIT_S;\n else\n fsm_next = TX_DATA_WAIT_S;\n end\n\n TX_DATA_WAIT_S : begin\n if (!data_hold_full)\n fsm_next = TX_DATA_LOAD_S;\n else\n fsm_next = TX_DATA_WAIT_S;\n end\n endcase\nend\n\nlogic data_shift_last;\nlogic [3:0] data_bit_cnt;\nbus8_t data_hold;\nbus8_t data_shift;\nlogic data_bit_strobe;\nlogic stuff_event;\n\nalways_ff @(posedge clk or posedge rst)\nbegin\n if (rst) begin\n data_bit_cnt <= '0;\n data_hold <= '0;\n data_shift <= '0;\n data_oen <= 1'b0;\n data_shift_last <= 1'b0;\n data_hold_full <= 1'b0;\n tx_ready <= 1'b0;\n data_se0 <= 1'b0;\n end else begin\n case (fsm_state)\n TX_WAIT_S : begin\n data_bit_cnt <= 'd0;\n data_shift_last <= 1'b0;\n end\n\n SEND_SYNC_S : begin\n data_shift <= USB_SYNC_VAL;\n end\n\n TX_DATA_LOAD_S : begin\n if (tx_valid) begin\n data_hold <= tx_data;\n data_hold_full <= 1'b1;\n tx_ready <= 1'b1;\n end else if (!tx_valid && data_oen) begin\n data_hold <= 'd0;\n data_hold_full <= 1'b1;\n tx_ready <= 1'b0;\n data_shift_last <= 1'b1;\n end\n end\n\n TX_DATA_WAIT_S : begin\n tx_ready <= 1'b0;\n\n // data shifting on every strobe\n if (data_bit_strobe) begin\n data_shift <= data_shift >> 1;\n data_bit_cnt <= data_bit_cnt + 1;\n if (data_se0 && (data_bit_cnt == 'd12))\n data_hold_full <= 1'b0;\n end else if (data_bit_cnt == 'd8) begin\n data_shift <= data_hold;\n data_hold_full <= 1'b0;\n if (!data_shift_last)\n data_bit_cnt <= 'd0;\n end\n\n // data output enable should be active till last se0 of eop have been transmitted\n if (data_bit_strobe)\n data_oen <= (data_se0 && (data_bit_cnt == 'd12)) ? 1'b0 : 1'b1;\n\n // signalling that last bit of last byte transmitted and next will be se0 of eop\n if ((data_bit_cnt == 'd10) && data_shift_last && (!stuff_event)) begin\n data_se0 <= 1'b1;\n end else if (data_bit_strobe && data_se0 && (data_bit_cnt == 'd12)) begin\n data_se0 <= 1'b0;\n end\n end\n endcase\n end\nend\n\nlogic data_bit;\nlogic [1:0] data_bit_phase_cnt;\nlogic data_bit_valid;\n\nalways_ff @(posedge clk or posedge rst)\nbegin\n if (rst)\n data_bit_phase_cnt <= '1;\n else if (!data_oen)\n data_bit_phase_cnt <= '1;\n else\n data_bit_phase_cnt <= data_bit_phase_cnt + 'b1;\nend\n\nassign data_bit_valid = (data_bit_phase_cnt == '1);\n\nalways_ff @(posedge clk or posedge rst)\nbegin\n if (rst)\n data_bit <= 1'b0;\n else if (!data_oen)\n data_bit <= 1'b0;\n else if (data_bit_strobe)\n data_bit <= data_shift[0];\nend\n\nassign data_bit_strobe = data_bit_valid && (!stuff_event);\n\n//-----------------------------------------------------------------------------\n// Bit stuffer\n//-----------------------------------------------------------------------------\nlogic [USB_STUFF_BITS_N-1:0] stuff_shift;\nlogic stuff_bit;\nlogic stuff_bit_valid;\n\nalways_ff @(posedge clk or posedge rst)\nbegin\n if (rst)\n stuff_shift <= '0;\n else if (data_bit_valid)\n stuff_shift <= {stuff_shift[USB_STUFF_BITS_N-2:0], stuff_event? 1'b0 : data_bit};\nend\n\nassign stuff_event = (stuff_shift == '1);\n\nalways_ff @(posedge clk or posedge rst)\nbegin\n if (rst) begin\n stuff_bit <= 1'b0;\n stuff_bit_valid <= 1'b0;\n end else if (!data_oen) begin\n stuff_bit <= 1'b0;\n stuff_bit_valid <= 1'b0;\n end else begin\n stuff_bit <= stuff_event? 1'b0 : data_bit;\n stuff_bit_valid <= data_bit_valid;\n end\nend\n\n//-----------------------------------------------------------------------------\n// NRZI encoder\n//-----------------------------------------------------------------------------\nlogic enc_nrzi_bit;\n\nalways_ff @(posedge clk or posedge rst)\nbegin\n if (rst)\n enc_nrzi_bit <= 1'b1;\n else if (!data_oen)\n enc_nrzi_bit <= 1'b1;\n else if (stuff_bit_valid && (stuff_bit == 1'b0))\n enc_nrzi_bit <= ~enc_nrzi_bit;\nend\n\n//-----------------------------------------------------------------------------\n// Data to line states converter\n//-----------------------------------------------------------------------------\nalways_ff @(posedge clk or posedge rst)\nbegin\n if (rst)\n {dn_tx, dp_tx} <= USB_LS_J;\n else if (!data_oen)\n {dn_tx, dp_tx} <= USB_LS_J;\n else if (stuff_bit_valid && data_se0)\n {dn_tx, dp_tx} <= USB_LS_SE0;\n else if (stuff_bit_valid)\n {dn_tx, dp_tx} <= {!enc_nrzi_bit, enc_nrzi_bit};\nend\n\n// Output enable expander - to drive J one bit time after EOP transmitted\nlogic [3:0] data_oen_ff;\n\nalways_ff @(posedge clk or posedge rst)\nbegin\n if (rst)\n data_oen_ff <= '0;\n else\n data_oen_ff <= {data_oen_ff[2:0], data_oen};\nend\n\nalways_ff @(posedge clk or posedge rst)\nbegin\n if (rst)\n tx_oen <= 1'b0;\n else\n tx_oen <= |data_oen_ff;\nend\n\nassign tx_active = tx_oen;\n\nendmodule : usb_sie_tx\n", "groundtruth": " TX_DATA_WAIT_S,\n XXX_S = 'x\n", "crossfile_context": ""}
{"task_id": "usb20dev", "path": "usb20dev/verif/helpers/usb_host_beh.sv", "left_context": "//==============================================================================\n// USB 2.0 FS Host behavioral model\n//\n//------------------------------------------------------------------------------\n// [usb20dev] 2018 Eden Synrez <esynr3z@gmail.com>\n//==============================================================================\n\nimport usb_pkg::*;\n\nmodule usb_host_beh (\n // USB lines\n usb_fe_if.phy phy\n);\n\n//-----------------------------------------------------------------------------\n// Parameters and defines\n//-----------------------------------------------------------------------------\n", "right_context": "localparam USB_RAW_BITS = USB_RAW_BYTES*8;\n\n//-----------------------------------------------------------------------------\n// Connections\n//-----------------------------------------------------------------------------\nlogic dp_tx, dn_tx;\nwire dp_rx, dn_rx;\n\npullup (phy.dp);\npulldown(phy.dn);\n\nassign phy.dp = dp_tx;\nassign phy.dn = dn_tx;\nassign dp_rx = phy.dp;\nassign dn_rx = phy.dn;\n\ninitial\nbegin\n send_raw_nondrive();\nend\n\n//-----------------------------------------------------------------------------\n// Raw line control tasks\n//-----------------------------------------------------------------------------\ntask wait_interpacket_delay;\nbegin\n #`USB_PERIOD_DEL;\n #`USB_PERIOD_DEL;\n #`USB_PERIOD_DEL;\n #`USB_PERIOD_DEL;\n #`USB_PERIOD_DEL;\n #`USB_PERIOD_DEL;\nend\nendtask : wait_interpacket_delay\n\ntask send_raw_bit(\n input logic dp,\n input logic dn\n);\nbit jit_sel;\nbegin\n jit_sel = $urandom_range(0,1);\n\n if (jit_sel) begin\n dp_tx <= dp;\n #`USB_PHASE_DEL dn_tx <= dn;\n end else begin\n dn_tx <= dn;\n #`USB_PHASE_DEL dp_tx <= dp;\n end\n\n #`USB_PERIOD_DEL;\nend\nendtask : send_raw_bit\n\ntask send_raw_nondrive;\nbegin\n send_raw_bit(1'bz, 1'bz);\nend\nendtask : send_raw_nondrive\n\ntask send_raw_k;\nbegin\n send_raw_bit(0, 1);\nend\nendtask : send_raw_k\n\ntask send_raw_j;\nbegin\n send_raw_bit(1, 0);\nend\nendtask : send_raw_j\n\ntask send_raw_se0;\nbegin\n send_raw_bit(0, 0);\nend\nendtask : send_raw_se0\n\ntask send_raw_packet(\n input logic [USB_RAW_BITS-1:0] data,\n input int len\n);\nbit enc_nrzi_bit;\nint stuff_bit_cnt;\nbegin\n //Sync\n send_raw_k();\n send_raw_j();\n send_raw_k();\n send_raw_j();\n send_raw_k();\n send_raw_j();\n send_raw_k();\n send_raw_k();\n\n enc_nrzi_bit = 0;\n stuff_bit_cnt = 1;\n\n for (int i = 0; i < len*8; i++) begin\n // NRZI encoding\n if (!data[i])\n enc_nrzi_bit = !enc_nrzi_bit;\n send_raw_bit(enc_nrzi_bit, !enc_nrzi_bit);\n\n // Bit stuffing\n if (data[i])\n stuff_bit_cnt++;\n else\n stuff_bit_cnt = 0;\n\n if (stuff_bit_cnt >= USB_STUFF_BITS_N) begin\n stuff_bit_cnt = 0;\n enc_nrzi_bit = !enc_nrzi_bit;\n send_raw_bit(enc_nrzi_bit, !enc_nrzi_bit);\n end\n end\n\n // EOP\n send_raw_se0();\n send_raw_se0();\n send_raw_j();\n send_raw_nondrive();\n wait_interpacket_delay();\nend\nendtask : send_raw_packet\n\ntask receive_raw_packet (\n output logic [USB_RAW_BITS-1:0] data,\n output int len\n);\nusb_line_state_t [7:0] line_state_hist;\nint unstuff_cnt;\nint bit_cnt;\nlogic [USB_RAW_BITS-1:0] bit_data;\nbegin\n bit_cnt = 0;\n bit_data = '0;\n line_state_hist = {8{USB_LS_J}};\n\n // wait for sync pattern\n while (line_state_hist != USB_SYNC_PATTERN) begin\n line_state_hist = {line_state_hist[6:0], usb_line_state_t'({dn_rx, dp_rx})};\n #`USB_PERIOD_DEL;\n end\n\n unstuff_cnt = 1; // SYNC has 1 in the end\n\n // get data\n while (line_state_hist[2:0] != USB_EOP_PATTERN) begin\n line_state_hist = {line_state_hist[6:0], usb_line_state_t'({dn_rx, dp_rx})};\n\n if (line_state_hist[2:0] == USB_EOP_PATTERN) begin\n if (line_state_hist[3] == USB_LS_SE0)\n $display(\"%0d, W: %m: Warning, EOP must have 2 se0 bits!\", $time);\n break;\n end\n else if (line_state_hist[0] == USB_LS_SE0) begin\n //continue;\n end else if (unstuff_cnt == USB_STUFF_BITS_N) begin\n if (line_state_hist[0] == line_state_hist[1])\n $display(\"%0d, W: %m: Warning, should be '0' after 6 '1's!\", $time);\n unstuff_cnt = 0;\n end else begin // regular data bit\n bit_cnt = bit_cnt + 1;\n // NRZI decoding and bit stuffing control\n if (line_state_hist[0] == line_state_hist[1]) begin\n bit_data = {1'b1, bit_data[USB_RAW_BITS-1:1]};\n unstuff_cnt = unstuff_cnt + 1;\n end else begin\n bit_data = {1'b0, bit_data[USB_RAW_BITS-1:1]};\n unstuff_cnt = 0;\n end\n end\n\n #`USB_PERIOD_DEL;\n end\n\n // shift lsb to the array bottom\n bit_data = bit_data >> (USB_RAW_BITS - bit_cnt);\n\n data = bit_data;\n len = bit_cnt/8;\n if (bit_cnt%8 != 0)\n $display(\"%0d, W: %m: Warning, number of bits is not multiple of 8!\", $time);\n\n wait_interpacket_delay();\nend\nendtask : receive_raw_packet\n\ntask send_reset;\nbegin\n send_raw_se0();\n #10ms;\n send_raw_j();\n send_raw_nondrive();\nend\nendtask : send_reset\n\nlogic [4:0] crc5 = '1;\ntask step_crc5(\n input [7:0] dbyte,\n output [4:0] crc_o\n);\nconst bit [4:0] crc5_poly = 5'b00101;\nbegin\n for (int i = 0; i < 8; i++)\n begin\n if (crc5[4] ^ dbyte[i])\n crc5 = (crc5 << 1) ^ crc5_poly;\n else\n crc5 = crc5 << 1;\n end\n crc_o = crc5;\nend\nendtask : step_crc5\n\ntask valid_crc5(\n input [4:0] crc5,\n output valid\n);\nconst bit [4:0] crc5_res = USB_CRC5_VALID;\nbegin\n valid = (crc5_res == crc5);\nend\nendtask : valid_crc5\n\nlogic [15:0] crc16 = '1;\ntask step_crc16(\n input [7:0] dbyte,\n output [15:0] crc_o\n);\nconst bit [15:0] crc16_poly = 16'b1000000000000101;\nbegin\n for (int i = 0; i < 8; i++)\n begin\n if (crc16[15] ^ dbyte[i])\n crc16 = (crc16 << 1) ^ crc16_poly;\n else\n crc16 = crc16 << 1;\n end\n crc_o = crc16;\nend\nendtask : step_crc16\n\ntask valid_crc16(\n input [15:0] crc16,\n output valid\n);\nconst bit [15:0] crc16_res = USB_CRC16_VALID;\nbegin\n valid = (crc16_res == crc16);\nend\nendtask : valid_crc16\n\nendmodule : usb_host_beh\n", "groundtruth": "// USB FS 12.000 Mb/s +-0.25% (+-208ps)\nlocalparam USB_PERIOD = 83333; // ps\nlocalparam USB_JIT = 100; // ps\n`define USB_PERIOD_DEL ((USB_PERIOD + ($urandom_range(0, USB_JIT*2) - USB_JIT))/1000.0)\n", "crossfile_context": ""}
{"task_id": "usb20dev", "path": "usb20dev/verif/helpers/usb_sie_vip.sv", "left_context": "//==============================================================================\n// SIE Verification IP\n//\n//------------------------------------------------------------------------------\n// [usb20dev] 2018 Eden Synrez <esynr3z@gmail.com>\n//==============================================================================\n\nimport usb_pkg::*;\n\nmodule usb_sie_vip (\n input logic clk, // Clock\n input logic rst, // Asynchronous reset\n\n usb_sie_if.pe sie_bus // SIE Data Bus\n);\n\n//-----------------------------------------------------------------------------\n// Parameters and defines\n//-----------------------------------------------------------------------------\nlocalparam SIE_RAW_BYTES = 1024;\n\n//-----------------------------------------------------------------------------\n// Connections and init\n//-----------------------------------------------------------------------------\ninitial\nbegin\n sie_bus.tx_data = '0;\n sie_bus.tx_valid = '0;\nend\n\n//-----------------------------------------------------------------------------\n// Data control tasks\n//-----------------------------------------------------------------------------\ntask send_data(\n input bit [SIE_RAW_BYTES-1:0][7:0] data, // Data bytes\n input int len // Data bytes total\n);\nbegin\n @(posedge clk);\n for (int i = 0; i < len; i++) begin\n", "right_context": " while(!sie_bus.tx_ready)\n @(posedge clk);\n end\n @(posedge clk);\n sie_bus.tx_valid = 1'b0;\nend\nendtask : send_data\n\ntask receive_data(\n output logic [SIE_RAW_BYTES-1:0][7:0] data, // Data bytes\n output int len // Data bytes total\n);\nbegin\n data = 0;\n len = 0;\n wait(sie_bus.rx_active);\n while(sie_bus.rx_active) begin\n @(posedge clk);\n if (sie_bus.rx_active && sie_bus.rx_valid) begin\n data[len] = sie_bus.rx_data;\n len++;\n end\n if (sie_bus.rx_error)\n $display(\"%0d, W: %m: Warning, rx_error is active!\", $time);\n end\nend\nendtask : receive_data\n\ntask detect_reset;\nbegin\n while(!sie_bus.reset)\n @(posedge clk);\n $display(\"%0d, I: %m: Bus reset detected\", $time);\n\n while(sie_bus.reset)\n @(posedge clk);\n $display(\"%0d, I: %m: Bus reset released\", $time);\nend\nendtask : detect_reset\n\nendmodule : usb_sie_vip\n", "groundtruth": " sie_bus.tx_data = data[i];\n sie_bus.tx_valid = 1'b1;\n", "crossfile_context": ""}
{"task_id": "usb20dev", "path": "usb20dev/verif/testbenches/crc/tb.sv", "left_context": "//==============================================================================\n// Testbench body for CRC test\n//\n//------------------------------------------------------------------------------\n// [usb20dev] 2018 Eden Synrez <esynr3z@gmail.com>\n//==============================================================================\n\n`include \"../testbenches/tb_header.svh\"\n\n//-----------------------------------------------------------------------------\n// DUT top\n//-----------------------------------------------------------------------------\nusb_fe_if usb_fe();\n\nlogic [7:0] dut_data = '0;\nlogic dut_wr = 1'b0;\nlogic dut_clear = 1'b0;\nlogic dut_busy;\nlogic [4:0] dut_crc;\n\nusb_crc5 dut (\n", "right_context": " .rst (~tb_rst_n),\n .data (dut_data),\n .wr (dut_wr),\n .clear (dut_clear),\n .busy (dut_busy),\n .crc (dut_crc)\n);\n\nusb_host_beh host_beh (\n .phy (usb_fe.phy)\n);\n\n//`define STOP_TIME 100ms // Time when test stops\n`define TEST_DESCR \"CRC test: compare CRC5 and CRC16 calculation on Host and Device\"\n`define DATA_TOTAL 16\n\n//-----------------------------------------------------------------------------\n// Testbench body\n//-----------------------------------------------------------------------------\nlogic [4:0] crc5_val;\nlogic [7:0] data_in [`DATA_TOTAL-1:0];\nlogic [4:0] data_crc5_host [`DATA_TOTAL-1:0];\nlogic [4:0] data_crc5_dev [`DATA_TOTAL-1:0];\n\ninitial\nbegin : tb_body\n tb_err = 0; // no errors\n\n //Reset\n wait(tb_rst_n);\n\n //Test start\n #100ns tb_busy = 1;\n\n for (int i = 0; i < `DATA_TOTAL; i++) begin\n data_in[i] = $urandom();\n end\n\n $display(\"%0d, I: %m: Host calculate CRC5\", $time);\n for (int i = 0; i < `DATA_TOTAL; i++) begin\n #10ns host_beh.step_crc5(data_in[i], crc5_val);\n #1ns data_crc5_host[i] = host_beh.crc5;\n end\n\n $display(\"%0d, I: %m: Device calculate CRC5\", $time);\n for (int i = 0; i < `DATA_TOTAL; i++) begin\n @(posedge tb_clk);#1ns;\n dut_data = data_in[i];\n dut_wr = 1'b1;\n @(posedge tb_clk);#1ns;\n dut_wr = 1'b0;\n @(posedge tb_clk);\n wait(!dut_busy);\n @(posedge tb_clk);#1ns;\n data_crc5_dev[i] = dut_crc;\n end\n\n $display(\"%0d, I: %m: Compare results\", $time);\n for (int i = 0; i < `DATA_TOTAL; i++) begin\n if (data_crc5_dev[i] != data_crc5_host[i])\n tb_err++;\n end\n\n //Test end\n #3us tb_busy = 0;\nend\n\n`include \"../testbenches/tb_footer.svh\"\n", "groundtruth": " .clk (tb_clk),\n", "crossfile_context": ""}
{"task_id": "usb20dev", "path": "usb20dev/verif/testbenches/example/tb.sv", "left_context": "//==============================================================================\n// Testbench body\n//\n//------------------------------------------------------------------------------\n// [usb20dev] 2018 Eden Synrez <esynr3z@gmail.com>\n//==============================================================================\n\n`include \"../testbenches/tb_header.svh\"\n`include \"../testbenches/tb_dut_usb.svh\"\n\n`define STOP_TIME 50ms // Time when test stops\n`define TEST_DESCR \"Example test of USB that do nothing\"\n\n//-----------------------------------------------------------------------------\n// Testbench body\n//-----------------------------------------------------------------------------\ninitial\nbegin : tb_body\n //Reset\n wait(tb_rst_n);\n\n //Test start\n #100ns tb_busy = 1;\n\n $display(\"Super-druper test starts doing something...\");\n #1ms;\n $display(\"Still doing...\");\n #1ms;\n $display(\"Oh, enough\");\n\n tb_err = 0; // no errors\n\n //Test end\n #100ns tb_busy = 0;\nend\n\n", "right_context": "", "groundtruth": "`include \"../testbenches/tb_footer.svh\"\n", "crossfile_context": ""}
{"task_id": "usb20dev", "path": "usb20dev/verif/testbenches/sie/tb.sv", "left_context": "//==============================================================================\n// Testbench body for SIE test\n//\n//------------------------------------------------------------------------------\n// [usb20dev] 2018 Eden Synrez <esynr3z@gmail.com>\n//==============================================================================\n\n`include \"../testbenches/tb_header.svh\"\n\n//-----------------------------------------------------------------------------\n// DUT top\n//-----------------------------------------------------------------------------\nusb_fe_if usb_fe();\nusb_sie_if usb_sie_bus();\n\nusb_sie dut (\n .clk (tb_clk),\n .rst (~tb_rst_n),\n .fe_ctrl (usb_fe.ctrl),\n .sie_bus (usb_sie_bus.sie)\n);\n\nusb_host_beh host_beh (\n .phy (usb_fe.phy)\n);\n\nusb_sie_vip sie_vip (\n .clk (tb_clk),\n .rst (~tb_rst_n),\n .sie_bus (usb_sie_bus.pe)\n);\n\n//`define STOP_TIME 100ms // Time when test stops\n`define TEST_DESCR \"SIE test - receive, transmit and special cases\"\n`define RND_CYCLES 1000\n\n//-----------------------------------------------------------------------------\n// Testbench body\n//-----------------------------------------------------------------------------\nparameter X_PACKET_LEN = 67;\n\nclass packet_tester_t;\n rand integer tx_len;\n rand reg [X_PACKET_LEN-1:0][7:0] tx_data;\n\n integer rx_len;\n reg [X_PACKET_LEN-1:0][7:0] rx_data;\n\n constraint LegalOrder\n {\n solve tx_len before tx_data;\n }\n constraint LegalConfig\n {\n tx_len >3; tx_len < X_PACKET_LEN;\n\n foreach(tx_data[i])\n if (i >= tx_len)\n tx_data[i] == 'b0;\n }\n\n function new();\n tx_len = 0;\n tx_data = 0;\n rx_len = 0;\n rx_data = 0;\n endfunction : new\n\n function bit is_len_eq();\n is_len_eq = 1;\n if (tx_len !== rx_len) begin\n $display(\"%0d, E: %m: Error, tx_len and rx_len are not equal!\", $time);\n is_len_eq = 0;\n end\n endfunction : is_len_eq\n\n function bit is_data_eq();\n", "right_context": "\n for (int i = 0; i < tx_len; i++) begin\n if(tx_data[i] !== rx_data[i]) begin\n $display(\"%0d, E: %m: Error, packets are not equal!\", $time);\n $display(\"\\ttx_data[%0d] = 0x%0x; rx_data[%0d] = 0x%0x\", i, tx_data[i], i, rx_data[i]);\n is_data_eq = 0;\n end\n end\n endfunction : is_data_eq\n\nendclass : packet_tester_t\n\ninitial\nbegin : tb_body\n packet_tester_t ptester = new;\n\n tb_err = 0; // no errors\n\n //Reset\n wait(tb_rst_n);\n\n //Test start\n #100ns tb_busy = 1;\n\n $display(\"%0d, I: %m: VIP --> SIE --> Host\", $time);\n for (int i = 0; i < `RND_CYCLES; i++) begin : crv_tx\n ptester.randomize();\n $display(\"%0d, I: %m: Cycle %0d, %0d bytes to transmit\", $time, i, ptester.tx_len);\n\n fork\n tb.sie_vip.send_data(ptester.tx_data, ptester.tx_len);\n tb.host_beh.receive_raw_packet(ptester.rx_data, ptester.rx_len);\n join\n\n if (!ptester.is_len_eq())\n tb_err++;\n else if (!ptester.is_data_eq())\n tb_err++;\n end : crv_tx\n\n $display(\"%0d, I: %m: VIP <-- SIE <-- Host\", $time);\n for (int i = 0; i < `RND_CYCLES; i++) begin : crv_rx\n ptester.randomize();\n $display(\"%0d, I: %m: Cycle %0d, %0d bytes to receive\", $time, i, ptester.tx_len);\n\n fork\n tb.host_beh.send_raw_packet(ptester.tx_data, ptester.tx_len);\n tb.sie_vip.receive_data(ptester.rx_data, ptester.rx_len);\n join\n\n if (!ptester.is_len_eq())\n tb_err++;\n else if (!ptester.is_data_eq())\n tb_err++;\n end : crv_rx\n\n $display(\"%0d, I: %m: Host applying Reset\", $time);\n fork\n tb.host_beh.send_reset();\n tb.sie_vip.detect_reset();\n join\n\n //Test end\n #3us tb_busy = 0;\nend\n\n`include \"../testbenches/tb_footer.svh\"\n", "groundtruth": " is_data_eq = 1;\n", "crossfile_context": ""}
{"task_id": "usb20dev", "path": "usb20dev/verif/testbenches/tb_dut_usb.svh", "left_context": "//-----------------------------------------------------------------------------\n// DUT top\n//-----------------------------------------------------------------------------\nusb_fe_if usb_fe();\n\n", "right_context": " .clk_48m (tb_clk),\n .rst (~tb_rst_n),\n .fe_ctrl (usb_fe.ctrl)\n);\n\nusb_host_beh host_beh (\n .phy (usb_fe.phy)\n);", "groundtruth": "usb dut (\n", "crossfile_context": ""}
{"task_id": "usb20dev", "path": "usb20dev/verif/testbenches/tb_footer.svh", "left_context": "//==============================================================================\n// Testbench footer with some common tesbench control\n//\n//------------------------------------------------------------------------------\n// [usb20dev] 2018 Eden Synrez <esynr3z@gmail.com>\n//==============================================================================\n\n// After the end of tb.sv file ...\n\n//-----------------------------------------------------------------------------\n// Testbench control\n//-----------------------------------------------------------------------------\ninitial\nbegin : tb_ctrl\n $display(\"### Test started ###\");\n $display(\"Test description: %s\\n\", `TEST_DESCR);\n wait(tb_busy);\n wait(!tb_busy);\n #10;\n if (tb_err)\n $display(\"\\n### Test FAIL ###\");\n else\n $display(\"\\n### Test OK ###\");\n $stop;\nend\n\n//-----------------------------------------------------------------------------\n// Testbench stop\n//-----------------------------------------------------------------------------\n`ifdef STOP_TIME\n\ninitial\nbegin : tb_stop\n", "right_context": " $stop;\nend\n\n`endif //STOP_TIME\n\nendmodule : tb\n", "groundtruth": " #(`STOP_TIME);\n", "crossfile_context": ""}
{"task_id": "usb20dev", "path": "usb20dev/verif/testbenches/tb_header.svh", "left_context": "//==============================================================================\n// Testbench header with common code\n//\n//------------------------------------------------------------------------------\n// [usb20dev] 2018 Eden Synrez <esynr3z@gmail.com>\n//==============================================================================\n\n// Include all helper tools\n`include \"../helpers/usb_host_beh.sv\"\n`include \"../helpers/usb_sie_vip.sv\"\n\n`timescale 1ns/1ps\n\n`define PERIOD_48MHz 20.8333ns\n`define CLK_PERIOD `PERIOD_48MHz\n`define RST_DELAY_TIME 100ns\n\nmodule tb();\n\nbit tb_busy = 0;\nbit tb_err = 0;\n\n//-----------------------------------------------------------------------------\n// Clock and reset\n//-----------------------------------------------------------------------------\n", "right_context": "logic tb_rst_n = 0;\n\nalways\nbegin\n #(`CLK_PERIOD/2);\n tb_clk <= ~tb_clk;\nend\n\ninitial\nbegin\n #(`RST_DELAY_TIME) tb_rst_n <= 1;\nend\n\n// To be continued in tb.sv file ...\n", "groundtruth": "logic tb_clk = 0;\n", "crossfile_context": ""}
{"task_id": "UVM_Verification", "path": "UVM_Verification/rcc_agent.sv", "left_context": "/*\n\n*/\n\nclass rcc_agent extends uvm_agent;\n\t`uvm_component_utils(rcc_agent)\n\n", "right_context": "\tuvm_analysis_port #(rcc_transaction) mon2scb;\n\n\trcc_sequencer rcc_seqr;\n\trcc_driver rcc_drvr;\n\trcc_monitor rcc_mtr;\n\n\tfunction new(string name, uvm_component parent);\n\t\tsuper.new(name, parent);\n\tendfunction: new\n\n\tfunction void build_phase(uvm_phase phase);\n\t\tsuper.build_phase(phase);\n\t\tmon2ref = new(\"mon2ref\", this);\n\t\tmon2scb = new(\"mon2scb\", this);\n\n\t\trcc_seqr = rcc_sequencer::type_id::create(.name(\"rcc_seqr\"), .parent(this));\n\t\trcc_drvr = rcc_driver::type_id::create(.name(\"rcc_drvr\"), .parent(this));\n\t\trcc_mtr = rcc_monitor::type_id::create(.name(\"rcc_mtr\"), .parent(this));\n\n\tendfunction: build_phase\n\n\tfunction void connect_phase(uvm_phase phase);\n\t\tsuper.connect_phase(phase);\n\n\t\t// connect the analysis port of monitor to analysis port of agent\n\t\trcc_mtr.mon2ref.connect(mon2ref);\n\t\trcc_mtr.mon2scb.connect(mon2scb);\n\n\t\t// connect driver seq_item_port to sequencer seq_item_export\n\t\trcc_drvr.seq_item_port.connect(rcc_seqr.seq_item_export);\n\n\tendfunction: connect_phase\n\nendclass: rcc_agent\n", "groundtruth": "\tuvm_analysis_port #(rcc_transaction) mon2ref;\n", "crossfile_context": ""}
{"task_id": "UVM_Verification", "path": "UVM_Verification/rcc_assertions.sv", "left_context": "/*\n* Assertion module for the RCC block\n*\n*/\n\n\nmodule rcc_assertions(rcc_if intf);\n\n\n always begin\n //forever begin\n @(posedge intf.clk)\n if(intf.reset == 1)\n assert (intf.dout == 8'hff)\n else\n //$stop;\n $display(\"ERROR: dout is not correctly initialized to reset value: %h\", intf.dout);\n\n assert(intf.dout_flag == 1'b1)\n else\n $display(\"%b ERROR: dout_flag is not correctly initialized at reset\", intf.dout_flag);\n\n end\n\n\n// adding the concurrent assertions\n\n\n property din_rcc_clk;\n @(posedge intf.clk) \n", "right_context": " end\n\n\n// need to use non-overlapped operator //\n/* property digclk_doutflag;\n @(posedge intf.clk)\n disable iff (intf.reset) $changed(intf.dout_flag) |=> $rose(intf.digit_clk);\n endproperty\n\n dout_flag_check: assert property (digclk_doutflag) else begin\n $error(\"ERROR-------------- digit clock %t\", $time);\n end*/\n\nendmodule //assertion\n", "groundtruth": " disable iff (intf.reset) $rose(intf.rcc_clk) |=> !$isunknown(intf.din);\n endproperty\n\n", "crossfile_context": ""}
{"task_id": "UVM_Verification", "path": "UVM_Verification/rcc_config.sv", "left_context": "class rcc_configuration extends uvm_object;\n\t`uvm_object_utils(rcc_configuration)\n\n\tfunction new(string name = \"\");\n", "right_context": "\tendfunction: new\n\nendclass: rcc_configuration\n", "groundtruth": "\t\tsuper.new(name);\n", "crossfile_context": ""}
{"task_id": "UVM_Verification", "path": "UVM_Verification/rcc_driver.sv", "left_context": "/*\n* Driver communicates with the DUT at pin level.\n* It receives the stimulus from the sequencer in form of transactions\n* Within Driver synchroization betwen sequencer and driver takes place via handshaking\n*/\n\nclass rcc_driver extends uvm_driver#(rcc_transaction);\n\t`uvm_component_utils(rcc_driver)\n\n\t// virtual interface declaration\n\tvirtual rcc_if vif;\n\n uvm_analysis_port #(rcc_transaction) din_cov;\n uvm_analysis_port #(rcc_transaction) addrs_cov;\n\n rcc_transaction cov_din_tx;\n rcc_transaction cov_addr_tx;\n\n\n\tfunction new(string name, uvm_component parent);\n\t\tsuper.new(name, parent);\n\n\tendfunction\n\n\tfunction void build_phase(uvm_phase phase);\n\t\tsuper.build_phase(phase);\n\n din_cov = new(\"din_cov\", this);\n addrs_cov = new(\"addrs_cov\", this);\n\n cov_din_tx = rcc_transaction::type_id::create(\"cov_din_tx\", this);\n cov_addr_tx = rcc_transaction::type_id::create(\"cov_addr_tx\", this);\n\n\t // get the virtual interface handle that was stored in the uvm_config_db\n\t // and assign it to the local vif field\n", "right_context": "\t\t\t`uvm_fatal(\"No Vif\", {\"virtual interface must be set for: \", get_full_name(), \".vif\"});\n\n\tendfunction: build_phase\n\n bit [3:0] g_address, digcnt, qcnt;\n bit [15:0] g_din;\n\n\t// using sequence_item_port connect with sequencer\n\t// get the transaction and then drive the DUT\n\ttask run_phase(uvm_phase phase);\n\n\t\treset(); // reset task\n\t\tforever\n\t\t\tbegin\n\n\t\t\t\trcc_transaction rcc_tx;\n\t\t\t\tseq_item_port.get_next_item(rcc_tx); // get the transaction from sequencer\n\t\t\t\tdigcnt = rcc_tx.digcnt;\n seq_item_port.item_done();\n\n\t\t\t\trepeat(digcnt)\n\t\t\t\t\tbegin\n\t\t\t\t\t\trepeat(4) // wait for 4 clock edges //\n\t\t\t\t\t \t\t@(posedge vif.clk);\n\n\t\t\t\t\t\tg_address = 0;\n\n seq_item_port.get_next_item(rcc_tx); \n\t\t\t\t\t\tg_din = rcc_tx.g_din;\n\t\t\t\t\tseq_item_port.item_done();\n\n\t\t\t\t\tcov_din_tx.g_din = g_din; // for din coverage\n\t\t\t\t\tdin_cov.write(cov_din_tx);\n\n\t\t\t\t\t\trepeat(8) // for 8 registers write the data //\n\t\t\t\t\t\t\tbegin\n\n\t\t\t\t\t\t\t\twrite_it;\n g_address = g_address +1;\n\t\t\t\t\t\t\t//if(rcc_tx.randomize())\n\t\t\t\t\t\t\tseq_item_port.get_next_item(rcc_tx);\n // g_din = rcc_tx.g_din;\n\t\t\t\t\t\t\tseq_item_port.item_done();\n\n\t\t\t\t\t\t\tseq_item_port.get_next_item(rcc_tx);\n g_din = rcc_tx.g_din;\n\t\t\t\t\t\t\tseq_item_port.item_done();\n\t\t\t\t\t\t\t//$display(\"input: %h\", g_din);\n \t\t\t\t\t\t\t\t\n\n \t\tcov_din_tx.g_din = g_din; // for din coverage\n \t\tdin_cov.write(cov_din_tx);\n \n\n\t\t\t\t\t\t\tend\n \t\t//cov_din_tx.g_din = g_din; // for din coverage\n \t\t//din_cov.write(cov_din_tx);\n\t\t\t\t\t\twrite_it;\n\t\t\t\t\t\tg_address = 0;\n \n\n\t\t\t\t\t\trepeat(160)\n\t\t\t\t\t\t @(posedge vif.clk);\n\t\t\t\t\tend //digcnt\n\n\t\t\t\t\t//if(rcc_tx.randomize())\n seq_item_port.get_next_item(rcc_tx);\n\t\t\t\t\tqcnt = rcc_tx.qcnt;\n seq_item_port.item_done();\n\n\t\t\t\t\trepeat(qcnt)\n\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\trepeat(4)\n\t\t\t\t\t\t\t @(posedge vif.clk);\n\n\t\t\t\t\t\t\tg_address = 0;\n\t\t\t\t\t\t\tg_din = 0;\n\n //seq_item_port.get_next_item(rcc_tx);\n\t\t\t\t\t\t\t//rcc_tx.g_din = g_din;\n // seq_item_port.item_done();\n\n\n\t\t\t\t\t\t\trepeat(8)\n\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t write_it;\n\t\t\t\t\t\t\t\t g_address = g_address +1;\n\t\t\t\t\t\t\t\tend\n\n\t\t\t\t\t\t\twrite_it;\n\t\t\t\t\t\t\tg_address = 0;\n\n\t\t\t\t\t\t\trepeat(160)\n\t\t\t\t\t\t\t @(posedge vif.clk);\n\n\t\t\t\t\t\tend //qcnt\n\t\t\t\t\t//seq_item_port.item_done(); // transaction complete\n\n\t\t\t\t\tend //forever loop\n\nendtask // run_phase\n\n\ttask write_it();\n\t@(posedge vif.clk);\n\tvif.address <= g_address;\n\tvif.din <= g_din;\n\n cov_addr_tx.g_address = g_address; // for addrs coverage\n addrs_cov.write(cov_addr_tx);\n\n\t@(posedge vif.clk);\n\tvif.rcc_clk <= 1;\n\t@(posedge vif.clk);\n\tvif.rcc_clk <= 0;\n\t@(posedge vif.clk);\n\tvif.din <= 'bz;\n endtask\n\n\n\n //bit [8:0] [15:0] temp;\n // reset task, Resets the interface signals to default/initial values\n task reset();\n\n vif.test_mode = 0;\n vif.scan_in0 = 0;\n vif.scan_in1 = 0;\n vif.scan_en = 0;\n\n vif.din = 16'h0000;\n vif.address = 4'h0;\n\n vif.rcc_clk = 1'b0;\n vif.reset = 1'b0;\n// assertion checks\n //vif.dout = 8'haa;\n // vif.dout_flag = 1'b0;\n\n @(negedge vif.clk);\n @(negedge vif.clk);\n vif.reset = 1;\n\n $display(\"----------- RESET START------\");\n @(negedge vif.clk);\n @(negedge vif.clk);\n\n vif.reset = 0;\n $display(\"------------ RESET ENDS-----------\");\n endtask\n\n\nendclass: rcc_driver\n\n\n", "groundtruth": "\t\t if(!uvm_config_db#(virtual rcc_if)::get(this, \"\", \"vif\", vif))\n", "crossfile_context": ""}
{"task_id": "UVM_Verification", "path": "UVM_Verification/rcc_environment.sv", "left_context": "class rcc_environment extends uvm_env;\n\t`uvm_component_utils(rcc_environment)\n\n\trcc_agent rcc_agnt; // DUT out\n ref_pred rcc_ref_pred; // Ref out\n\trcc_scoreboard rcc_scb; // compare both outputs\n rcc_in_coverage rcc_cov;\n rcc_out_coverage rcc_out_cov;\n \n\n\tfunction new(string name, uvm_component parent);\n\t\tsuper.new(name, parent);\n\tendfunction: new\n\n\tfunction void build_phase(uvm_phase phase);\n\t\tsuper.build_phase(phase);\n\t\trcc_agnt = rcc_agent::type_id::create(.name(\"rcc_agnt\"), .parent(this));\n\t\trcc_scb = rcc_scoreboard::type_id::create(.name(\"rcc_scb\"), .parent(this));\n\t\trcc_ref_pred = ref_pred::type_id::create(.name(\"rcc_ref_pred\"), .parent(this));\n", "right_context": " rcc_out_cov = rcc_out_coverage::type_id::create(.name(\"rcc_out_cov\"), .parent(this));\n\n\tendfunction: build_phase\n\n\t// Connect_phase\n\tfunction void connect_phase(uvm_phase phase);\n\t\tsuper.connect_phase(phase);\n\n\t\trcc_agnt.mon2scb.connect(rcc_scb.out_dut);\n\t\trcc_agnt.mon2ref.connect(rcc_ref_pred.analysis_export);\n rcc_ref_pred.ref2scb.connect(rcc_scb.out_ref);\n\n rcc_agnt.rcc_drvr.din_cov.connect(rcc_cov.cov_din); // coverage analysis connection\n rcc_agnt.rcc_drvr.addrs_cov.connect(rcc_cov.cov_addr); // coverage analysis connection\n\n\t\trcc_agnt.mon2scb.connect(rcc_out_cov.out_dut_cov); // coverage analysis connection\n rcc_ref_pred.ref2scb.connect(rcc_out_cov.out_ref_cov); // coverage analysis connection\n\n\tendfunction\n\nendclass: rcc_environment\n", "groundtruth": " rcc_cov = rcc_in_coverage::type_id::create(.name(\"rcc_cov\"), .parent(this));\n", "crossfile_context": ""}
{"task_id": "UVM_Verification", "path": "UVM_Verification/rcc_if.sv", "left_context": "/*\n* RCC interface\n*/\ninterface rcc_if;\n\n bit reset, clk;\n\n bit rcc_clk;\n\n logic [3:0] address;\n\n", "right_context": "\n bit digit_clk;\n\n logic [7:0] dout;\n\n logic dout_flag;\n\n bit test_mode;\n\n bit scan_in0, scan_in1, scan_en;\n\n bit scan_out0, scan_out1;\n\n\nendinterface:rcc_if\n\n\n", "groundtruth": " logic [15:0] din;\n", "crossfile_context": ""}
{"task_id": "UVM_Verification", "path": "UVM_Verification/rcc_in_coverage.sv", "left_context": "class rcc_in_coverage extends uvm_component;\n `uvm_component_utils(rcc_in_coverage)\n\n virtual rcc_if vif;\n\n uvm_analysis_export #(rcc_transaction) cov_din;\n uvm_analysis_export #(rcc_transaction) cov_addr;\n\n uvm_tlm_analysis_fifo #(rcc_transaction) cov_din_fifo;\n", "right_context": "\n rcc_transaction seq_din;\n rcc_transaction seq_addr;\n\n rcc_transaction seq_in;\n rcc_transaction seq_ad;\n\n covergroup din_rtl; // @(posedge vif.clk);\n cover_point_din_rtl: coverpoint seq_in.g_din {option.auto_bin_max = 65535;}\n endgroup\n\n covergroup addr_rtl; //@(posedge vif.rcc_clk);\n\n cover_point_addr_rtl: coverpoint seq_ad.g_address{ bins addrs_0 = {0};\n bins addrs_1 = {1};\n bins addrs_2 = {2};\n bins addrs_3 = {3};\n bins addrs_4 = {4};\n bins addrs_5 = {5};\n bins addrs_6 = {6};\n bins addrs_7 = {7};\n ignore_bins ig = {[8:15]};\n }\n\n endgroup\n\n\n function new(string name = \"\", uvm_component parent);\n super.new(name, parent);\n din_rtl = new();\n addr_rtl = new();\n endfunction\n\n function void build_phase(uvm_phase phase);\n super.build_phase(phase);\n\n if(!uvm_config_db#(virtual rcc_if)::get(this, \"\", \"vif\", vif))\n\t `uvm_fatal(\"No Vif\", {\"virtual interface must be set for: \", get_full_name(), \".vif\"});\n\n seq_in = rcc_transaction::type_id::create(\"seq_in\", this);\n seq_ad = rcc_transaction::type_id::create(\"seq_ad\", this);\n\n cov_din = new(\"cov_din\", this);\n cov_addr = new(\"cov_addr\", this);\n\n cov_din_fifo = new(\"cov_din_fifo\", this);\n cov_addr_fifo = new(\"cov_addr_fifo\", this);\n\n seq_din = rcc_transaction::type_id::create(\"seq_din\", this);\n seq_addr = rcc_transaction::type_id::create(\"seq_addr\", this);\n endfunction\n\n function void connect_phase(uvm_phase phase);\n cov_din.connect(cov_din_fifo.analysis_export);\n cov_addr.connect(cov_addr_fifo.analysis_export);\n endfunction\n\n task run_phase(uvm_phase phase);\n fork\n din_coverage();\n addr_coverage();\n join_none\n\n endtask\n\n task din_coverage;\n forever begin\n @(posedge vif.clk)\n cov_din_fifo.get(seq_din);\n seq_in.g_din = seq_din.g_din;\n //$display(\"cov input : %h\\n\", seq_in.g_din);\n din_rtl.sample();\n // $display(\"input cov: %f\\n\", din_rtl.get_coverage());\n end\n endtask\n\n task addr_coverage;\n forever begin\n @(posedge vif.rcc_clk)\n cov_addr_fifo.get(seq_addr);\n seq_ad.g_address = seq_addr.g_address;\n //$display(\"cov input : %h\\n\", seq_ad.g_address);\n addr_rtl.sample();\n // $display(\"input address cov: %f\\n\", addr_rtl.get_coverage());\n end\n\n endtask\n\n\nendclass\n\n\n", "groundtruth": " uvm_tlm_analysis_fifo #(rcc_transaction) cov_addr_fifo;\n", "crossfile_context": ""}
{"task_id": "UVM_Verification", "path": "UVM_Verification/rcc_monitor.sv", "left_context": "// Monitor Class\n// It receives the response from the DUT and converts the signal level response into transactions\n// sends the transactions to various other testbench components\n\nclass rcc_monitor extends uvm_monitor;\n\t`uvm_component_utils(rcc_monitor)\n\n\t// declare the interface\n\tvirtual rcc_if vif;\n\trcc_transaction rcc_tx;\n\n\t// Analysis Ports\n\tuvm_analysis_port#(rcc_transaction) mon2ref;\n\tuvm_analysis_port#(rcc_transaction) mon2scb;\n\n\tfunction new(string name, uvm_component parent);\n\t\tsuper.new(name, parent);\n\tendfunction: new\n\n\tfunction void build_phase(uvm_phase phase);\n\t\tsuper.build_phase(phase);\n\n\tmon2ref = new(\"mon2ref\", this);\n\tmon2scb = new(\"mon2scb\", this);\n\n\t// get the virtual interface handle from config database\n\tif(!uvm_config_db#(virtual rcc_if)::get(this, \"\", \"vif\", vif))\n", "right_context": "\tendfunction: build_phase\n\nbit [15:0] array_data [9];\ninteger i= 0;\ninteger j;\n\n\ttask run_phase(uvm_phase phase);\n\t\tfork\n\t\tsample_input();\n\t\tsample_output();\n\t\tjoin\n\n\tendtask\n\n\n\ttask sample_input;\n\t\tforever\n\t\t\tbegin\n\t\t\trcc_transaction data_collect;\n\t\t\tdata_collect = rcc_transaction::type_id::create(\"data_collect\", this);\n\t\t\t\t@(posedge vif.rcc_clk)\n\t\t\t\t\tdata_collect.g_din = vif.din;\n\t\t\t\tmon2ref.write(data_collect);\n\n\t\t\t\t\n\t\t\tend //forever loop\n\tendtask // sample_input\n\n\ttask sample_output;\n\t\tforever\n\t\t\tbegin\n\n\t\t\t\trcc_transaction data_collect_out;\n\t\t\t\tdata_collect_out = rcc_transaction::type_id::create(\"data_collect_out\", this);\n\n\t\t\t\t@(posedge vif.digit_clk)\n\t\t\t\t\tdata_collect_out.dout = vif.dout;\n\t\t\t// Send the data through analysis port\n\t\t\t\tmon2scb.write(data_collect_out);\n\n\t\t\t\t\n\t\t\tend //forever loop\n\tendtask // sample_output\n\nendclass\n\n", "groundtruth": " `uvm_fatal(\"No Vif\", {\"virtual interface must be set for: \", get_full_name(), \".vif\"});\n", "crossfile_context": ""}
{"task_id": "UVM_Verification", "path": "UVM_Verification/rcc_out_coverage.sv", "left_context": "// Monitor takes the input from the reference model via a mailbox and checks DUT with ref. model\n//\n\nclass rcc_out_coverage extends uvm_component;\n\t`uvm_component_utils(rcc_out_coverage)\n\t\n\tvirtual rcc_if vif;\n\t\n\tuvm_analysis_export #(rcc_transaction) out_dut_cov;\n uvm_analysis_export #(rcc_transaction) out_ref_cov;\n\n\tuvm_tlm_analysis_fifo #(rcc_transaction) dut_cov_fifo;\n\tuvm_tlm_analysis_fifo #(rcc_transaction) ref_cov_fifo;\n\t\n\trcc_transaction dut_trans_cov;\n rcc_transaction ref_trans_cov;\n \n bit count_min = 0;\n int watermark_count = 10;\n \t\n\tbit [7:0] refmdl_dout;\n\tbit [7:0] rtl_dout;\n \n //declare coun for rtl digits\n int dut_1 = 0;\n int dut_2 = 0;\n int dut_3 = 0;\n int dut_a = 0;\n int dut_4 = 0;\n int dut_5 = 0;\n int dut_6 = 0;\n int dut_b = 0;\n int dut_7 = 0;\n int dut_8 = 0;\n int dut_9 = 0;\n int dut_c = 0;\n int dut_star = 0;\n int dut_0 = 0;\n int dut_pound = 0;\n int dut_d = 0;\n\n\n //declare coun for ref model digits\n int ref_1 = 0;\n int ref_2 = 0;\n int ref_3 = 0;\n int ref_a = 0;\n int ref_4 = 0;\n int ref_5 = 0;\n int ref_6 = 0;\n int ref_b = 0;\n int ref_7 = 0;\n int ref_8 = 0;\n int ref_9 = 0;\n int ref_c = 0;\n int ref_star = 0;\n int ref_0 = 0;\n int ref_pound = 0;\n int ref_d = 0;\n \n // coverage\n covergroup output_coverage; // @(posedge vif.digit_clk);\n\n cover_point_dout_rtl: coverpoint rtl_dout { bins dout_rtl_0 = {48}; // 48 is decimal 0\n bins dout_rtl_1 = {49};\n bins dout_rtl_2 = {50};\n bins dout_rtl_3 = {51};\n bins dout_rtl_4 = {52};\n bins dout_rtl_5 = {53};\n bins dout_rtl_6 = {54};\n bins dout_rtl_7 = {55};\n bins dout_rtl_8 = {56};\n bins dout_rtl_9 = {57};\n bins dout_rtl_a = {97};\n bins dout_rtl_b = {98};\n bins dout_rtl_c = {99};\n bins dout_rtl_d = {100};\n bins dout_rtl_star = {42};\n bins dout_rtl_pound = {35};\n ignore_bins ig_rtl = {[1:34], [36:41], [43:47], [58:96],[101:255]};\n }\n\n cover_point_out_ref: coverpoint refmdl_dout { bins out_ref_0 = {48};\n bins out_ref_1 = {49};\n bins out_ref_2 = {50};\n bins out_ref_3 = {51};\n bins out_ref_4 = {52};\n bins out_ref_5 = {53};\n bins out_ref_6 = {54};\n bins out_ref_7 = {55};\n bins out_ref_8 = {56};\n bins out_ref_9 = {57};\n bins out_ref_a = {97};\n bins out_ref_b = {98};\n bins out_ref_c = {99};\n bins out_ref_d = {100};\n bins out_ref_star = {42};\n", "right_context": " ignore_bins ig_ref = {[1:34], [36:41], [43:47], [58:96],[101:255]};\n }\n\n // cross coverage between ASCII digit produced by RTL and ref model\n cross_rtl_ref_out: cross cover_point_dout_rtl, cover_point_out_ref\n {\n bins cross_out_0 = binsof (cover_point_dout_rtl) intersect {48};\n bins cross_out_1 = binsof (cover_point_dout_rtl) intersect {49};\n bins cross_out_2 = binsof (cover_point_dout_rtl) intersect {50};\n bins cross_out_3 = binsof (cover_point_dout_rtl) intersect {51};\n bins cross_out_4 = binsof (cover_point_dout_rtl) intersect {52};\n bins cross_out_5 = binsof (cover_point_dout_rtl) intersect {53};\n bins cross_out_6 = binsof (cover_point_dout_rtl) intersect {54};\n bins cross_out_7 = binsof (cover_point_dout_rtl) intersect {55};\n bins cross_out_8 = binsof (cover_point_dout_rtl) intersect {56};\n bins cross_out_9 = binsof (cover_point_dout_rtl) intersect {57};\n bins cross_out_a = binsof (cover_point_dout_rtl) intersect {97};\n bins cross_out_b = binsof (cover_point_dout_rtl) intersect {98};\n bins cross_out_c = binsof (cover_point_dout_rtl) intersect {99};\n bins cross_out_d = binsof (cover_point_dout_rtl) intersect {100};\n bins cross_out_star = binsof (cover_point_dout_rtl) intersect {42};\n bins cross_out_pound = binsof (cover_point_dout_rtl) intersect {35};\n\n }\n\n endgroup //output_coverage\n\n\n\n // cross coverage for digit counts\n covergroup cross_digit_count; // @(posedge vif.digit_clk);\n\n cross_ref_1: coverpoint ref_1{option.auto_bin_max = 1;}\n cross_ref_2: coverpoint ref_2{option.auto_bin_max = 1;}\n cross_ref_3: coverpoint ref_3{option.auto_bin_max = 1;}\n cross_ref_4: coverpoint ref_4{option.auto_bin_max = 1;}\n cross_ref_5: coverpoint ref_5{option.auto_bin_max = 1;}\n cross_ref_6: coverpoint ref_6{option.auto_bin_max = 1;}\n cross_ref_7: coverpoint ref_7{option.auto_bin_max = 1;}\n cross_ref_8: coverpoint ref_8{option.auto_bin_max = 1;}\n cross_ref_9: coverpoint ref_9{option.auto_bin_max = 1;}\n cross_ref_0: coverpoint ref_0{option.auto_bin_max = 1;}\n cross_ref_a: coverpoint ref_a{option.auto_bin_max = 1;}\n cross_ref_b: coverpoint ref_b{option.auto_bin_max = 1;}\n cross_ref_c: coverpoint ref_c{option.auto_bin_max = 1;}\n cross_ref_d: coverpoint ref_d{option.auto_bin_max = 1;}\n cross_ref_star: coverpoint ref_star{option.auto_bin_max = 1;}\n cross_ref_pound: coverpoint ref_pound{option.auto_bin_max = 1;}\n\n\n cross_rtl_1: coverpoint dut_1{option.auto_bin_max = 1;}\n cross_rtl_2: coverpoint dut_2{option.auto_bin_max = 1;}\n cross_rtl_3: coverpoint dut_3{option.auto_bin_max = 1;}\n cross_rtl_4: coverpoint dut_4{option.auto_bin_max = 1;}\n cross_rtl_5: coverpoint dut_5{option.auto_bin_max = 1;}\n cross_rtl_6: coverpoint dut_6{option.auto_bin_max = 1;}\n cross_rtl_7: coverpoint dut_7{option.auto_bin_max = 1;}\n cross_rtl_8: coverpoint dut_8{option.auto_bin_max = 1;}\n cross_rtl_9: coverpoint dut_9{option.auto_bin_max = 1;}\n cross_rtl_0: coverpoint dut_0{option.auto_bin_max = 1;}\n cross_rtl_a: coverpoint dut_a{option.auto_bin_max = 1;}\n cross_rtl_b: coverpoint dut_b{option.auto_bin_max = 1;}\n cross_rtl_c: coverpoint dut_c{option.auto_bin_max = 1;}\n cross_rtl_d: coverpoint dut_d{option.auto_bin_max = 1;}\n cross_rtl_star: coverpoint dut_star{option.auto_bin_max = 1;}\n cross_rtl_pound: coverpoint dut_pound{option.auto_bin_max = 1;}\n\n\n digit_1: cross cross_ref_1, cross_rtl_1;\n digit_2: cross cross_ref_2, cross_rtl_2;\n digit_3: cross cross_ref_3, cross_rtl_3;\n digit_4: cross cross_ref_4, cross_rtl_4;\n digit_5: cross cross_ref_5, cross_rtl_5;\n digit_6: cross cross_ref_6, cross_rtl_6;\n digit_7: cross cross_ref_7, cross_rtl_7;\n digit_8: cross cross_ref_8, cross_rtl_8;\n digit_9: cross cross_ref_9, cross_rtl_9;\n digit_0: cross cross_ref_0, cross_rtl_0;\n digit_a: cross cross_ref_a, cross_rtl_a;\n digit_b: cross cross_ref_b, cross_rtl_b;\n digit_c: cross cross_ref_c, cross_rtl_c;\n digit_d: cross cross_ref_d, cross_rtl_d;\n digit_star: cross cross_ref_star, cross_rtl_star;\n digit_pound: cross cross_ref_pound, cross_rtl_pound;\n\n\n endgroup // cross_digit_count\n \n \n \n function new(string name= \"\", uvm_component parent);\n\t\tsuper.new(name, parent);\n\t\t\toutput_coverage = new();\n\t\t\tcross_digit_count = new();\n\tendfunction\n\t\n\tfunction void build_phase(uvm_phase phase);\n\t\tsuper.build_phase(phase);\n \tout_dut_cov = new(\"out_dut_cov\", this);\n \tout_ref_cov = new(\"out_ref_cov\", this);\n\n \t\t\tdut_cov_fifo = new(\"dut_cov_fifo\", this);\n\t\t\tref_cov_fifo = new(\"ref_cov_fifo\", this);\n\n\t\t\tdut_trans_cov = rcc_transaction::type_id::create(\"dut_trans_cov\", this);\n\t\t\tref_trans_cov = rcc_transaction::type_id::create(\"ref_trans_cov\", this);\n\n\t// get the virtual interface handle that was stored in the uvm_config_db\n\t// and assign it to the local vif field\n\t\t\tif(!uvm_config_db#(virtual rcc_if)::get(this, \"\", \"vif\", vif))\n\t\t\t\t`uvm_fatal(\"No Vif\", {\"virtual interface must be set for: \", get_full_name(), \".vif\"});\n\n\tendfunction: build_phase\n\t\n\tfunction void connect_phase(uvm_phase phase);\n\t\tout_dut_cov.connect(dut_cov_fifo.analysis_export);\n\t\tout_ref_cov.connect(ref_cov_fifo.analysis_export);\n\tendfunction: connect_phase\n\n \n \n\ttask run_phase(uvm_phase phase);\n\t\tforever begin\n\t\t\t@(posedge vif.digit_clk)\n\t\t\t\tdut_cov_fifo.get(dut_trans_cov);\n ref_cov_fifo.get(ref_trans_cov);\n \n rtl_dout = dut_trans_cov.dout;\n refmdl_dout = ref_trans_cov.dout;\n \n // $display(\"rtl_dout; %c\\n\", rtl_dout);\n // $display(\"refmdl_dout; %c\", refmdl_dout);\n\t\t\t\n\t\t\t\tif(rtl_dout == \"1\") dut_1 += 1;\n\t\t\t\telse if(rtl_dout == \"2\") dut_2 += 1;\n\t\t\t\telse if(rtl_dout == \"3\") dut_3 += 1;\n\t\t\t\telse if(rtl_dout == \"a\") dut_a += 1;\n\t\t\t\telse if(rtl_dout == \"4\") dut_4 += 1;\n\t\t\t\telse if(rtl_dout == \"5\") dut_5 += 1;\n\t\t\t\telse if(rtl_dout == \"6\") dut_6 += 1;\n\t\t\t\telse if(rtl_dout == \"b\") dut_b += 1;\n\t\t\t\telse if(rtl_dout == \"7\") dut_7 += 1;\n\t\t\t\telse if(rtl_dout == \"8\") dut_8 += 1;\n\t\t\t\telse if(rtl_dout == \"9\") dut_9 += 1;\n\t\t\t\telse if(rtl_dout == \"c\") dut_c += 1;\n\t\t\t\telse if(rtl_dout == \"*\") dut_star += 1;\n\t\t\t\telse if(rtl_dout == \"0\") dut_0 += 1;\n\t\t\t\telse if(rtl_dout == \"#\") dut_pound += 1;\n\t\t\t\telse if(rtl_dout == \"d\") dut_d += 1;\n\n\n\n\t\t\t\tif(refmdl_dout == \"1\") ref_1 += 1;\n\t\t\t\telse if(refmdl_dout == \"2\") ref_2 += 1;\n\t\t\t\telse if(refmdl_dout == \"3\") ref_3 += 1;\n\t\t\t\telse if(refmdl_dout == \"a\") ref_a += 1;\n\t\t\t\telse if(refmdl_dout == \"4\") ref_4 += 1;\n\t\t\t\telse if(refmdl_dout == \"5\") ref_5 += 1;\n\t\t\t\telse if(refmdl_dout == \"6\") ref_6 += 1;\n\t\t\t\telse if(refmdl_dout == \"b\") ref_b += 1;\n\t\t\t\telse if(refmdl_dout == \"7\") ref_7 += 1;\n\t\t\t\telse if(refmdl_dout == \"8\") ref_8 += 1;\n\t\t\t\telse if(refmdl_dout == \"9\") ref_9 += 1;\n\t\t\t\telse if(refmdl_dout == \"c\") ref_c += 1;\n\t\t\t\telse if(refmdl_dout == \"*\") ref_star += 1;\n\t\t\t\telse if(refmdl_dout == \"0\") ref_0 += 1;\n\t\t\t\telse if(refmdl_dout == \"#\") ref_pound += 1;\n\t\t\t\telse if(refmdl_dout == \"d\") ref_d += 1;\n\t\t\t\t\n\t\t\t\tcross_digit_count.sample;\n\t\t\t\toutput_coverage.sample;\n\n\n/*$display(\"--------- dut_1 count = %d\", dut_1 );\n$display(\"--------- dut_2 count = %d\", dut_2 );\n$display(\"--------- dut_3 count = %d\", dut_3 );\n$display(\"--------- dut_a count = %d\", dut_a );\n$display(\"--------- dut_4 count = %d\", dut_4 );\n$display(\"--------- dut_5 count = %d\", dut_5 );\n$display(\"--------- dut_6 count = %d\", dut_6 );\n$display(\"--------- dut_b count = %d\", dut_b );\n$display(\"--------- dut_7 count = %d\", dut_7 );\n$display(\"--------- dut_8 count = %d\", dut_8 );\n$display(\"--------- dut_9 count = %d\", dut_9 );\n$display(\"--------- dut_c count = %d\", dut_c );\n$display(\"--------- dut_d count = %d\", dut_d );\n$display(\"--------- dut_star count = %d\", dut_star );\n$display(\"--------- dut_0 count = %d\", dut_0 );\n$display(\"--------- dut_pound count = %d\\n\", dut_pound );\n\n$display(\"--------- Count from REF Model ---------------\\n\");\n \n$display(\"--------- ref_1 count = %d\", ref_1 );\n$display(\"--------- ref_2 count = %d\", ref_2 );\n$display(\"--------- ref_3 count = %d\", ref_3 );\n$display(\"--------- ref_a count = %d\", ref_a );\n$display(\"--------- ref_4 count = %d\", ref_4 );\n$display(\"--------- ref_5 count = %d\", ref_5 );\n$display(\"--------- ref_6 count = %d\", ref_6 );\n$display(\"--------- ref_b count = %d\", ref_b );\n$display(\"--------- ref_7 count = %d\", ref_7 );\n$display(\"--------- ref_8 count = %d\", ref_8 );\n$display(\"--------- ref_9 count = %d\", ref_9 );\n$display(\"--------- ref_c count = %d\", ref_c );\n$display(\"--------- ref_d count = %d\", ref_d );\n$display(\"--------- ref_star count = %d\", ref_star );\n$display(\"--------- ref_0 count = %d\", ref_0 );\n$display(\"--------- ref_pound count = %d\", ref_pound );*/\n\n//$display(\"--------- dut_9 count = %d\", dut_9 );\n// Watermark check\n\n\n if(dut_1 >= watermark_count && dut_2 >= watermark_count && dut_3 >= watermark_count && dut_4 >= watermark_count && dut_5 >= watermark_count && dut_6 >= watermark_count && dut_7 >= watermark_count &&dut_8 >= watermark_count && dut_9 >= watermark_count && dut_0 >= watermark_count && dut_a >= watermark_count && dut_b >= watermark_count && dut_c >= watermark_count && dut_d >= watermark_count && dut_star >= watermark_count && dut_pound >= watermark_count) \n\nbegin\n\n count_min = 1;\n\nend\n\n if(count_min)\n begin\n\n $display(\"------Watermark of\", \" %d \",watermark_count, \"reached for every digit----------\");\n $finish;\n\n end\n\t\t\t\n\t\t\tend// forever\n\t\t\n\tendtask\n\n\n\nendclass\n", "groundtruth": " bins out_ref_pound = {35};\n", "crossfile_context": ""}
{"task_id": "UVM_Verification", "path": "UVM_Verification/rcc_pkg.sv", "left_context": "", "right_context": "\timport uvm_pkg::*;\n//`include \"rcc_assertions.sv\"\n\t`include \"rcc_sequencer.sv\"\n `include \"rcc_in_coverage.sv\"\n `include \"rcc_out_coverage.sv\"\n\t`include \"rcc_driver.sv\"\n\t`include\"rcc_monitor.sv\"\n\t`include \"rcc_agent.sv\"\n\t`include \"ref_pred.sv\"\n\t`include \"rcc_scoreboard.sv\"\n\t`include \"rcc_config.sv\"\n\t`include \"rcc_environment.sv\"\n\t`include \"rcc_test.sv\"\n \nendpackage: rcc_pkg\n", "groundtruth": "package rcc_pkg;\n", "crossfile_context": ""}
{"task_id": "UVM_Verification", "path": "UVM_Verification/rcc_scoreboard.sv", "left_context": "// Checker receives the output from the Ref. Model and the output from DUT\n// It compares both the outputs\n// In this way it perform DUT vs Ref model verification\n\n\nclass rcc_scoreboard extends uvm_scoreboard;\n\t`uvm_component_utils(rcc_scoreboard)\n\n\n\tuvm_analysis_export #(rcc_transaction) out_dut;\n", "right_context": "\n\tuvm_tlm_analysis_fifo #(rcc_transaction) dut_fifo;\n\tuvm_tlm_analysis_fifo #(rcc_transaction) ref_fifo;\n\t\n\t//logic [7:0] dut_output, ref_output;\n\t\n\tvirtual rcc_if vif;\n \n\t\trcc_transaction dut_trans;\n rcc_transaction ref_trans;\n\n\tfunction new(string name= \"\", uvm_component parent);\n\t\tsuper.new(name, parent);\n\tendfunction\n\t\n\tfunction void build_phase(uvm_phase phase);\n\t\tsuper.build_phase(phase);\n out_dut = new(\"out_dut\", this);\n out_ref = new(\"out_ref\", this);\n\n \t\tdut_fifo\t\t= new(\"dut_fifo\", this);\n\t\tref_fifo\t\t= new(\"ref_fifo\", this);\n\ndut_trans = rcc_transaction::type_id::create(\"dut_trans\", this);\nref_trans = rcc_transaction::type_id::create(\"ref_trans\", this);\n\n\t// get the virtual interface handle that was stored in the uvm_config_db\n\t// and assign it to the local vif field\n\t\tif(!uvm_config_db#(virtual rcc_if)::get(this, \"\", \"vif\", vif))\n\t\t\t`uvm_fatal(\"No Vif\", {\"virtual interface must be set for: \", get_full_name(), \".vif\"});\n\n\tendfunction: build_phase\n\n\tfunction void connect_phase(uvm_phase phase);\n\t\tout_dut.connect(dut_fifo.analysis_export);\n\t\tout_ref.connect(ref_fifo.analysis_export);\n\tendfunction: connect_phase\n\n\t\n\ttask run_phase(uvm_phase phase);\n\n\t forever begin\n\n @(posedge vif.digit_clk)\n\n dut_fifo.get(dut_trans);\n ref_fifo.get(ref_trans);\n\n // using assertion to check the ref model and dut output\n assert(dut_trans.dout == ref_trans.dout)\n // $display(\"SUCCESS %c %c %d \\n\", dut_trans.dout, ref_trans.dout, $time);\n else\n $error(\"ERROR %c %c %d \\n\", dut_trans.dout, ref_trans.dout, $time);\n\t end// forever\n \n\n\tendtask\n\nendclass\n\n", "groundtruth": " uvm_analysis_export #(rcc_transaction) out_ref;\n", "crossfile_context": ""}
{"task_id": "UVM_Verification", "path": "UVM_Verification/rcc_sequencer.sv", "left_context": "/*\n* UVM has separate class hierarchy for data (stimulus)\n*/\n\n/*\n* We use transactions to communicate between components\n* Its a higher abstraction layer than signal level information\n*/\n\n// user defined transaction extends uvm_sequence_item\nclass rcc_transaction extends uvm_sequence_item;\n\t`uvm_object_utils(rcc_transaction)\n\n\trand bit [15:0] g_din;\n\trand bit [3:0] digcnt;\n\trand bit [3:0] qcnt;\n\tbit [7:0] dout; // need for output checking\n bit [3:0] g_address;\n\n\tfunction new(string name = \"\");\n\t\tsuper.new(name);\n\tendfunction: new\n\nendclass: rcc_transaction\n\n\n//---------------------------------------------------------------------------------------//\n\n\n/*\n* After we have created the transaction, we will create a sequence\n*/\n\nclass rcc_sequence_child extends uvm_sequence#(rcc_transaction);\n\t`uvm_object_utils(rcc_sequence_child)\n\n rcc_transaction rcc_tx;\n\n", "right_context": "\t\tsuper.new(name);\n\tendfunction: new\n\n// body defines the behavior of the sequence\n\ttask body();\n\n\t\t\t rcc_tx = rcc_transaction::type_id::create(\"rcc_tx\");\n\t\t//repeat(9)\n\t\t//begin\n\t\t\tstart_item(rcc_tx);\n if(rcc_tx.randomize())\n\t\t\t//assert(rcc_tx.randomize());\n\t\t\tfinish_item(rcc_tx);\n\t\t\t\n\t\t//end\n\tendtask: body\n\nendclass: rcc_sequence_child\n\n\nclass rcc_sequencer extends uvm_sequencer#(rcc_transaction);\n\t`uvm_object_utils(rcc_sequencer)\n\n\tfunction new(string name = \"\");\n\t\tsuper.new(name);\n\tendfunction: new\n\nendclass: rcc_sequencer\n\n\n// this is top level sequenc that we start from uvm test class, which inturn creates \n//different sequence objects of child sequence. \n\nclass rcc_sequence extends uvm_sequence#(rcc_transaction);\n\t`uvm_object_utils(rcc_sequence)\n\n //rcc_transaction rcc_tx;\n rcc_sequencer rcc_seqr; // handle to sequencer\n\n\tfunction new(string name = \"\");\n\t\tsuper.new(name);\n\tendfunction: new\n\n// body defines the behavior of the sequence\n\ttask body();\n\n forever begin\n rcc_sequence_child seq;\n seq = rcc_sequence_child::type_id::create(\"seq\"); // create child sequence object\n\n if(!seq.randomize())\n `uvm_error(get_type_name(), \"Failed to randomize sequence\")\n//$display(\"First here: %d \\n\", $time);\n seq.start(rcc_seqr, this);\n//$display(\"end here: %d \\n\", $time);\n end\n\tendtask: body\n\nendclass: rcc_sequence\n\n\n", "groundtruth": "\tfunction new(string name = \"\");\n", "crossfile_context": ""}
{"task_id": "UVM_Verification", "path": "UVM_Verification/rcc_tb_top.sv", "left_context": "`include \"uvm_macros.svh\"\n`include \"rcc_pkg.sv\"\n`include \"rcc_if.sv\"\n\nmodule test;\n\n import uvm_pkg::*;\n\n\t// this package includes all our class definetion\n import rcc_pkg::*;\n\n\n import \"DPI\" function int sim_start_time();\n import \"DPI\" function void start_day_date();\n import \"DPI\" function void digit_gen_time(int dig_time);\n\n int sim_start;\n int sim_finish_time, execution_time;\n\n\t// instantiate the interface in top level module\n rcc_if intf();\n\n", "right_context": "\n\t// connect the DUT with the interface\n\tresults_conv top(\n\t\t .clk(intf.clk),\n\t\t .reset(intf.reset),\n\t\t .test_mode(intf.test_mode),\n\t\t .rcc_clk(intf.rcc_clk),\n\t\t .address(intf.address),\n\t\t .din(intf.din),\n\t\t .digit_clk(intf.digit_clk),\n\t\t .dout(intf.dout),\n\t`ifdef NETLIST\n\t\t .dout_flag(intf.dout_flag),\n\t\t .scan_in0(intf.scan_in0),\n\t\t .scan_in1(intf.scan_in1),\n\t\t .scan_en(intf.scan_en)\n\t`else\n\t\t .dout_flag(intf.dout_flag)\n\t`endif\n\t\t );\n\n\n rcc_assertions ass_rcc(intf);\n\n\tinitial begin\n\t\t//Registers the Interface in the configuration block so that other\n\t\t//blocks can use it\n\t\t// we pass the virtual interface using config database\n\t\tuvm_config_db #(virtual rcc_if)::set(null, \"*\", \"vif\", intf);\n\n\t\t// execute the test\n\t\trun_test();\n\tend\t\n\n initial begin\n $timeformat(-9, 2, \"ns\", 16);\n $set_coverage_db_name(\"results_conv\");\n `ifdef SDFSCAN\n $sdf_annotate(\"sdf/results_cov_tsmc18_scan.sdf\", test.top);\n `endif\n end\n\n\tinitial begin\n\t\tintf.clk <= 1'b0;\n\tend\n\n\talways begin\n\t\t#25 intf.clk = ~intf.clk;\n\tend\n\n// wall time\n initial begin\n sim_start = sim_start_time();\n $display(\"-----------------------------------------------------\\n\");\n\n $display(\"----------------SIMULATION STARTS AT: ----------------------------\\n\");\n start_day_date();\n end\n\n// final block that is executed at the end of the simulation\n// print other useful information like coverage results, finish wall time\n final begin\n sim_finish_time = sim_start_time();\n execution_time = sim_finish_time - sim_start;\n\n $display(\"-----------------------------------------------------\\n\");\n $display(\"Total Execution Time in days/hours/minutes/seconds is: \");\n digit_gen_time(execution_time);\n\n // print coverage at the end of simulation\n $display(\"din coverage for RTL = %f \", cov_in.din_rtl.get_coverage() );\n $display(\"address coverage for RTL = %f\\n \", cov_in.addr_rtl.get_coverage());\n\n $display(\"RTL dout coverage for RTL = %f \", cov_out.output_coverage.cover_point_dout_rtl.get_coverage() );\n $display(\"Ref Model dout coverage for RTL = %f\\n \", cov_out.output_coverage.cover_point_out_ref.get_coverage() );\n\n $display(\"dout cross coverage for RTL = %f \", cov_out.output_coverage.cross_rtl_ref_out.get_coverage() );\n\n $display(\"digit count cross coverage = %f\\n \", cov_out.cross_digit_count.get_coverage() );\n\n $display(\"\\n------------SIMULATION ENDS AT: -----------------\");\n start_day_date();\n $display(\"----------------END------------------\");\n end\n\n\nendmodule\n", "groundtruth": " // coverage instance for coverage result display\n rcc_in_coverage cov_in;\n", "crossfile_context": ""}
{"task_id": "UVM_Verification", "path": "UVM_Verification/rcc_test.sv", "left_context": "/*\n* test case for the RCC. It extends uvm_test base class\n* 1) it drives the sequence by connecting the sequence with sequencer\n* 2) create the env block\n*/\n\nclass rcc_test extends uvm_test;\n\t//register the class name with uvm factory\n\t`uvm_component_utils(rcc_test)\n\n\t//instantiate the env\n\trcc_environment rcc_env;\n\n\tfunction new(string name = \"rcc_test\", uvm_component parent = null);\n\t\tsuper.new(name, parent);\n\tendfunction: new\n\n\t// UVM build_phase\n\tfunction void build_phase (uvm_phase phase);\n\t\tsuper.build_phase(phase);\n\t\trcc_env = rcc_environment::type_id::create(.name(\"rcc_env\"), .parent(this));\n\tendfunction: build_phase\n\n\t// UVM run_phase\n", "right_context": "\t\t// declare instance of sequence\n\t\trcc_sequence rcc_seq;\n\t\t// create the sequence\n\t\trcc_seq = rcc_sequence::type_id::create(\"rcc_seq\");\n assert(rcc_seq.randomize());\n\n\t\tphase.raise_objection(.obj(this));\n\t\t// test will call start() method of the sequence to initialte the execution of the sequence\n\t\t// and the argument is the sequencer on which sequence is going to start\n\t\trcc_seq.start(rcc_env.rcc_agnt.rcc_seqr, null);\n\t\tphase.drop_objection(.obj(this));\n\n\tendtask: run_phase\nendclass: rcc_test\n", "groundtruth": "\ttask run_phase(uvm_phase phase);\n", "crossfile_context": ""}
{"task_id": "UVM_Verification", "path": "UVM_Verification/ref_pred.sv", "left_context": "// class that receives the data from agent and pass it to C-reference model\n// and gets output returned from C-ref model\n\n // dpi imports\n import \"DPI-C\" function int input_arg( int array[8]);\n\n\nclass ref_pred extends uvm_subscriber #(rcc_transaction);\n `uvm_component_utils(ref_pred)\n\n // Analysis port for sending the ref model output to scoreboard\n uvm_analysis_port#(rcc_transaction) ref2scb;\n\n integer i= 0;\n integer j = 0;\n integer array_data[8];\n", "right_context": "\n\n rcc_transaction ref_output;\n//ref_output = rcc_transaction::type_id::create(\"ref_output\", this);\n\n function new(string name = \"\", uvm_component parent);\n super.new(name, parent);\n endfunction\n\n function void build_phase(uvm_phase phase);\n super.build_phase(phase);\n\n ref2scb = new(\"ref2scb\", this);\n\nref_output = rcc_transaction::type_id::create(\"ref_output\", this);\n\n endfunction\n\n\n function void write(rcc_transaction t);\n\n\n\t\tif(i <= 7) array_data[i] = t.g_din;\n\n\t\t i = i+1;\n\n\t\tif(i == 9) \n\t \tbegin\n \t\t\tref_out = input_arg(array_data);\n//$display(\"-------ref_out : %c\\n\", ref_out);\n ref_output.dout = ref_out;\nref2scb.write(ref_output);\n // send the ref_out to scoreboard\n //ref2scb.write(ref_out);\n\t i = 0;\n\t\t for(j = 0; j< 8; j++)\n begin\n\t\t array_data[j] = 0;\n\t\t end\n end\n\n endfunction\n\n /*task run_phase(uvm_phase phase);\n \n // forever begin\n//$display(\"----------array_data = %h\", array_data[0]);\n//$display(\"----------------HERE---------------------\\n\");\n//$display(\"-----------------------ref_out: %c \\n\", ref_out);\n ref2scb.write(ref_output);\n // end\n endtask */\n\n\nendclass\n\n\n/*------ debug --------------------------------------\n$display(\"----------array_data = %h\", array_data[0]);\n$display(\"----------array_data = %h\", array_data[1]);\n$display(\"----------array_data = %h\", array_data[2]);\n$display(\"----------array_data = %h\", array_data[3]);\n$display(\"----------array_data = %h\", array_data[4]);\n$display(\"----------array_data = %h\", array_data[5]);\n$display(\"----------array_data = %h\", array_data[6]);\n$display(\"----------array_data = %h\", array_data[7]);\n//$display(\"----------array_data = %h\", array_data[8]);\n--------------------------------------------------------*/\n", "groundtruth": " integer ref_out;\n", "crossfile_context": ""}
{"task_id": "UVM_Verification", "path": "UVM_Verification/results_conv.v", "left_context": "\n/*\n *\n * Author: Mark A. Indovina\n * Rochester, NY, USA\n *\n */\n\n\nmodule results_conv (\n clk,\n reset,\n rcc_clk,\n address,\n din,\n digit_clk,\n dout,\n dout_flag,\n test_mode,\n scan_in0,\n scan_in1,\n scan_en,\n scan_out0,\n scan_out1\n ) ;\n\n/*\n *\n * Results Character Conversion (RCC)\n * processes a computed frequency spectrum to\n * determine if a valid DTMF digit can be found\n *\n */\n\ninput\n clk, // system clock\n reset, // system reset\n rcc_clk ; // data input write strobe\n\ninput [3:0]\n address ; // holding register address bus\n\ninput [15:0]\n din ; // data input bus\n\noutput\n digit_clk ; // data output write strobe\n\noutput [7:0]\n dout ; // data output bus\n\noutput\n dout_flag ; // data output change flag\n\ninput\n test_mode,\t\t // test mode control\n scan_in0, // test scan mode data input, chain 1\n scan_in1, // test scan mode data input, chain 2\n scan_en; // test scan mode enable\n\noutput\n scan_out0, // test scan mode data output, chain 1\n scan_out1; // test scan mode data output, chain 2\n\nreg\n digit_clk,\n dout_flag,\n go,\n gt,\n ok,\n clear_flag,\n seen_quiet,\n start_gt,\n gt_done,\n clear_gt,\n start_ct,\n ct_done,\n clear_ct;\n\nreg [2:0]\n low,\n high ;\n\nreg [4:0]\n state,\n save_state;\n\nreg [2:0]\n gt_state,\n ct_state;\n\nreg [7:0]\n dout,\n out_p1, // two stage pipeline for digit/ quiet framing; I should\n out_p2; // have used dout as part of the pipeline to save area...\n\nreg [15:0]\n r697,\n r770,\n r852,\n r941,\n r1209,\n r1336,\n r1477,\n r1633,\n low_mag,\n high_mag,\n opa,\n opb,\n opc,\n opd ;\n\n`include \"include/results_conv.h\"\n\nwire flag_reset = (reset | clear_flag) & !test_mode ;\n\nalways @(negedge rcc_clk or posedge flag_reset)\n if (flag_reset)\n go <= 0 ;\n else\n go <= address[3] ;\n\nalways @(negedge rcc_clk)\ncase (address[3:0])\n `R_697 : r697 <= din ;\n `R_770 : r770 <= din ;\n `R_852 : r852 <= din ;\n `R_941 : r941 <= din ;\n `R_1209 : r1209 <= din ;\n `R_1336 : r1336 <= din ;\n `R_1477 : r1477 <= din ;\n `R_1633 : r1633 <= din ;\nendcase\n\nalways @(posedge reset or posedge clk)\nbegin : rcc_machine\n if (reset)\n begin\n digit_clk \t\t<= 0 ;\n dout_flag \t\t<= 1 ;\n clear_flag \t<= 0 ;\n seen_quiet \t<= 1 ;\n out_p1 \t\t<= 0 ;\n out_p2 \t\t<= 8'hff ;\n low\t\t\t<= 0 ;\n high \t\t\t<= 0 ;\n low_mag\t\t<= 0 ;\n high_mag\t\t<= 0 ;\n opa\t\t\t<= 0 ;\n opb\t\t\t<= 0 ;\n opc\t\t\t<= 0 ;\n opd\t\t\t<= 0 ;\n start_gt\t\t<= 0 ;\n clear_gt\t\t<= 0 ;\n start_ct\t\t<= 0 ;\n clear_ct\t\t<= 0 ;\n dout \t\t\t<= 8'hff ;\n state\t\t\t<= `IDLE ;\n save_state\t\t<= `IDLE ;\n end\n else\n begin\n case (state)\n `IDLE : begin\n if (go)\n begin\n low \t\t<= 3'b100 ;\n high \t\t<= 3'b100 ;\n clear_flag \t<= 1 ;\n out_p2 \t\t<= out_p1 ; // digit pipeline\n //gt_comp( r697, r770, r852, r941 ) ;\n opa <= r697 ;\n opb <= r770 ;\n opc <= r852 ;\n opd <= r941 ;\n start_gt <= 1 ;\n save_state \t<= `F1 ;\n state \t<= `GT_WAIT ;\n end\n else\n begin\n state\t<= `IDLE ;\n end\n end\n `F1 : begin\n clear_flag \t<= 0 ;\n if (gt)\n begin\n low \t<= {1'b0, `V_697} ;\n low_mag <= r697 ;\n end\n //gt_comp( r770, r697, r852, r941 ) ;\n opa <= r770 ;\n opb <= r697 ;\n opc <= r852 ;\n opd <= r941 ;\n start_gt <= 1 ;\n save_state \t<= `F2 ;\n state \t<= `GT_WAIT ;\n end\n `F2 : begin\n if (gt)\n begin\n low \t<= {1'b0, `V_770} ;\n low_mag <= r770 ;\n end\n //gt_comp( r852, r697, r770, r941 ) ;\n opa <= r852 ;\n opb <= r697 ;\n opc <= r770 ;\n opd <= r941 ;\n start_gt <= 1 ;\n save_state \t<= `F3 ;\n state \t<= `GT_WAIT ;\n end\n `F3 : begin\n if (gt)\n begin\n low \t<= {1'b0, `V_852} ;\n low_mag <= r852 ;\n end\n //gt_comp( r941, r697, r770, r852 ) ;\n opa <= r941 ;\n opb <= r697 ;\n opc <= r770 ;\n opd <= r852 ;\n start_gt <= 1 ;\n save_state \t<= `F4 ;\n state \t<= `GT_WAIT ;\n end\n `F4 : begin\n if (gt)\n begin\n low \t<= {1'b0, `V_941} ;\n low_mag <= r941 ;\n end\n //gt_comp( r1209, r1336, r1477, r1633 ) ;\n opa <= r1209 ;\n opb <= r1336 ;\n opc <= r1477 ;\n opd <= r1633 ;\n start_gt <= 1 ;\n save_state \t<= `F5 ;\n state \t<= `GT_WAIT ;\n end\n `F5 : begin\n if (gt)\n begin\n high \t <= {1'b0, `V_1209} ;\n high_mag <= r1209 ;\n end\n //gt_comp( r1336, r1209, r1477, r1633 ) ;\n opa <= r1336 ;\n opb <= r1209 ;\n opc <= r1477 ;\n opd <= r1633 ;\n start_gt <= 1 ;\n save_state \t<= `F6 ;\n state \t<= `GT_WAIT ;\n end\n `F6 : begin\n if (gt)\n begin\n high \t <= {1'b0, `V_1336} ;\n high_mag <= r1336 ;\n end\n //gt_comp( r1477, r1209, r1336, r1633 ) ;\n opa <= r1477 ;\n opb <= r1209 ;\n opc <= r1336 ;\n opd <= r1633 ;\n start_gt <= 1 ;\n save_state \t<= `F7 ;\n state \t<= `GT_WAIT ;\n end\n `F7 : begin\n if (gt)\n begin\n high \t<= {1'b0, `V_1477} ;\n high_mag<= r1477 ;\n end\n //gt_comp( r1633, r1209, r1336, r1477 ) ;\n opa <= r1633 ;\n opb <= r1209 ;\n opc <= r1336 ;\n opd <= r1477 ;\n start_gt <= 1 ;\n save_state \t<= `F8 ;\n state \t<= `GT_WAIT ;\n end\n `F8 : begin\n if (gt)\n begin\n high \t <= {1'b0, `V_1633} ;\n high_mag <= r1633 ;\n end\n state \t <= `CHECK ;\n end\n // did we find both frequencies?\n `CHECK : begin\n if (!low[2] && !high[2])\n begin\n //check_twist( low_mag, high_mag ) ;\n opa <= low_mag ;\n opb <= high_mag ;\n start_ct <= 1 ;\n save_state \t<= `OK ;\n state \t<= `CT_WAIT ;\n end\n else\n begin\n out_p1 <= `NO_DIGIT ;\n state <= `CHARACTER ;\n end\n end\n\n `OK : begin\n if (ok)\n begin\n case ({low[1:0], high[1:0]})\n key_1[3:0] : out_p1 <= val_key_1 ;\n key_2[3:0] : out_p1 <= val_key_2 ;\n key_3[3:0] : out_p1 <= val_key_3 ;\n key_a[3:0] : out_p1 <= val_key_a ;\n key_4[3:0] : out_p1 <= val_key_4 ;\n key_5[3:0] : out_p1 <= val_key_5 ;\n key_6[3:0] : out_p1 <= val_key_6 ;\n key_b[3:0] : out_p1 <= val_key_b ;\n key_7[3:0] : out_p1 <= val_key_7 ;\n key_8[3:0] : out_p1 <= val_key_8 ;\n key_9[3:0] : out_p1 <= val_key_9 ;\n key_c[3:0] : out_p1 <= val_key_c ;\n key_star[3:0] : out_p1 <= val_key_star ;\n key_0[3:0] : out_p1 <= val_key_0 ;\n key_pound[3:0] : out_p1 <= val_key_pound ;\n key_d[3:0] : out_p1 <= val_key_d ;\n default : out_p1 <= `NO_DIGIT ;\n endcase\n state \t<= `CHARACTER ;\n end\n else\n begin\n out_p1 <= `NO_DIGIT ;\n state <= `CHARACTER ;\n end\n end\n // should we output a new digit?\n // need to see two frames worth for timing...\n `CHARACTER : begin\n if (out_p1 == out_p2)\n begin\n // quiet tone?\n if (out_p2 == `NO_DIGIT)\n begin\n seen_quiet \t<= 1 ;\n state <= `IDLE ;\n end\n else\n begin\n if (seen_quiet)\n begin\n seen_quiet \t<= 0 ;\n state\t<= `P1 ;\n", "right_context": " end\n // toggle msb for each new char...\n `P1 : begin\n dout \t\t<= { 1'b0, out_p2[6:0] } ;\n dout_flag \t<= ~dout_flag ;\n state\t<= `P2 ;\n end\n `P2 : begin\n digit_clk <= 1 ;\n state\t<= `P3 ;\n end\n `P3 : begin\n digit_clk <= 0 ;\n state\t<= `IDLE ;\n end\n // wait for greater_than to finish\n `GT_WAIT : begin\n if (gt_done)\n begin\n start_gt <= 0 ;\n clear_gt <= 1 ;\n state <= `GT_FINISH ;\n end\n else\n state <= `GT_WAIT ;\n end\n `GT_FINISH : begin\n clear_gt <= 0 ;\n state <= save_state ;\n end\n // wait for check_twist to finish\n `CT_WAIT : begin\n if (ct_done)\n begin\n start_ct <= 0 ;\n clear_ct <= 1 ;\n state <= `CT_FINISH ;\n end\n else\n state <= `CT_WAIT ;\n end\n `CT_FINISH : begin\n clear_ct <= 0 ;\n state <= save_state ;\n end\n default : \tstate \t<= `IDLE ;\n endcase\n end\nend // rcc_machine\n\n//\n// 16 bit \"greater-than\" comparision\n// we'll build our own pipelined comparitor here\n// (we want to force resource sharring...)\n//\n\nreg [16:0]\n cmpb,\n cmpc,\n cmpd ;\n\nalways @(posedge reset or posedge clk)\nbegin : gt_comp\n if (reset)\n begin\n cmpb \t<= 0 ;\n cmpc \t<= 0 ;\n cmpd \t<= 0 ;\n gt \t\t<= 0 ;\n gt_done\t<= 0 ;\n gt_state <= `GT_IDLE ;\n end\n else\n begin\n case (gt_state)\n `GT_IDLE : begin\n if (start_gt)\n gt_state <= `GEN_B ;\n else\n gt_state <= `GT_IDLE ;\n end\n `GEN_B : begin\n cmpb <= opb - opa ;\n gt_state <= `GEN_C ;\n end\n `GEN_C : begin\n cmpc <= opc - opa ;\n gt_state <= `GEN_D ;\n end\n `GEN_D : begin\n cmpd <= opd - opa ;\n gt_state <= `GT ;\n end\n `GT : begin\n gt <= cmpb[16] & cmpc[16] & cmpd[16] ;\n gt_state <= `GT_DONE ;\n end\n `GT_DONE : begin\n gt_done <= 1 ;\n gt_state <= `GT_CLEAR ;\n end\n `GT_CLEAR : begin\n if (clear_gt)\n begin\n gt_done <= 0 ;\n gt_state <= `GT_IDLE ;\n end\n else\n gt_state <= `GT_CLEAR ;\n end\n default : \tgt_state <= `GT_IDLE ;\n endcase\n end\nend\n\n//\n// check the twist between the frequencies,\n// constrain to +/- 12dB for the now...\n//\n\nreg [16:0]\n cmpf,\n cmpr ;\n\nalways @(posedge reset or posedge clk)\nbegin : check_twist\n if (reset)\n begin\n cmpf \t<= 0 ;\n cmpr \t<= 0 ;\n ok \t\t<= 0 ;\n ct_done\t<= 0 ;\n ct_state <= `CT_IDLE ;\n end\n else\n begin\n case (ct_state)\n `CT_IDLE : begin\n if (start_ct)\n ct_state <= `GEN_F ;\n else\n ct_state <= `GT_IDLE ;\n end\n `GEN_F : begin\n cmpf <= opa - opb ;\n ct_state <= `GEN_R ;\n end\n `GEN_R : begin\n if (cmpf[16]) // high freq is larger\n begin\n cmpf <= opa - {2'b0, opb[15:2]} ;\n cmpr <= opb - opa ;\n ct_state <= `CT ;\n end\n else // low freq is larger\n begin\n cmpf <= opb - {2'b0, opa[15:2]} ;\n cmpr <= opa - opb ;\n ct_state <= `CT ;\n end\n end\n `CT : begin\n ok <= (~cmpf[16]) && (~cmpr[16]) ;\n ct_state <= `CT_DONE ;\n end\n `CT_DONE : begin\n ct_done <= 1 ;\n ct_state <= `CT_CLEAR ;\n end\n `CT_CLEAR : begin\n if (clear_ct)\n begin\n ct_done <= 0 ;\n ct_state <= `CT_IDLE ;\n end\n else\n ct_state <= `CT_CLEAR ;\n end\n default :\tct_state <= `CT_IDLE ;\n endcase\n end\nend\n\nendmodule // results_conv\n", "groundtruth": " end\n else\n state <= `IDLE ;\n end\n", "crossfile_context": ""}
{"task_id": "UVM_Verification", "path": "UVM_Verification/results_conv_test.sv", "left_context": "\n/*\n *\n * Author: Mark A. Indovina\n * Rochester, NY, USA\n *\n */\n\n\n`timescale 1ns / 1ns\n\nmodule test;\n\nwire digit_clk;\n\nreg clk, rcc_clk, reset, test_mode;\n\nwire dout_flag;\nwire [7:0] dout;\nwire [7:0] dout_char = dout & 8'h7f ;\n\nreg [3:0] g_address, address, digcnt, qcnt;\nreg [15:0] g_din, din;\nreg scan_in0, scan_in1, scan_en;\n\nresults_conv top (\n .clk(clk),\n .reset(reset),\n .test_mode(test_mode),\n .rcc_clk(rcc_clk),\n .address(address),\n .din(din),\n .digit_clk(digit_clk),\n .dout(dout),\n`ifdef NETLIST\n .dout_flag(dout_flag),\n .scan_in0(scan_in0),\n .scan_in1(scan_in1),\n .scan_en(scan_en)\n`else\n .dout_flag(dout_flag)\n`endif\n ) ;\n\n\ninitial\nbegin\n $timeformat(-9,2,\"ns\", 16);\n`ifdef SDFSCAN\n $sdf_annotate(\"sdf/results_conv_tsmc18_scan.sdf\", test.top);\n`endif\n test_mode = 0;\n scan_in0 = 0;\n scan_in1 = 0;\n scan_en = 0;\n\n address[3:0] = 4'b0000;\n g_address[3:0] = 4'b0000;\n\n clk = 1'b0;\n din[15:0] = 16'b0000000000000000;\n", "right_context": " reset = 1'b1;\n @(negedge clk) ;\n @(negedge clk) ;\n reset = 1'b0;\n\n repeat (1024)\n begin\n digcnt = $urandom ;\n repeat (digcnt)\n begin\n repeat (4)\n @(posedge clk);\n g_address = 0 ;\n g_din = $urandom ;\n repeat (8)\n begin\n write_it ;\n g_address = g_address + 1 ;\n g_din = $urandom ;\n end\n write_it ;\n g_address = 0 ;\n repeat (160)\n @(posedge clk) ;\n end\n qcnt = $urandom ;\n repeat (qcnt)\n begin\n repeat (4)\n @(posedge clk);\n g_address = 0 ;\n g_din = 0 ;\n repeat (8)\n begin\n write_it ;\n g_address = g_address + 1 ;\n end\n write_it ;\n g_address = 0 ;\n repeat (160)\n @(posedge clk) ;\n end\n end\n $stop ;\nend\n\nalways #25 clk = ~clk ;\n\n\nalways @(posedge digit_clk)\nbegin\n #0 ;\n $display( \"Time: %t\", $time, \", Digit Clock: %b\", digit_clk, \", Digit: \\\"%c\\\"\", dout, \", Dout Flag: %b\", dout_flag );\nend\n\ntask write_it ;\n begin\n @(posedge clk) ;\n address <= g_address ;\n din <= g_din ;\n @(posedge clk)\n rcc_clk <= 1 ;\n @(posedge clk)\n rcc_clk <= 0 ;\n @(posedge clk) ;\n din <= 'bz ;\n end\nendtask\n\nendmodule\n", "groundtruth": " g_din[15:0] = 16'b0000000000000000;\n\n rcc_clk = 1'b0;\n test_mode = 1'b0;\n", "crossfile_context": ""}
{"task_id": "UVM_Verification", "path": "UVM_Verification/results_conv_test.v", "left_context": "\n/*\n *\n * Author: Mark A. Indovina\n * Rochester, NY, USA\n *\n */\n\n\n`timescale 1ns / 1ns\n\nmodule test;\n\nwire digit_clk;\n\nreg clk, rcc_clk, reset, test_mode;\n\nwire dout_flag;\nwire [7:0] dout;\nwire [7:0] dout_char = dout & 8'h7f ;\n\nreg [3:0] g_address, address, digcnt, qcnt;\nreg [15:0] g_din, din;\nreg scan_in0, scan_in1, scan_en;\n\nresults_conv top (\n .clk(clk),\n .reset(reset),\n .test_mode(test_mode),\n .rcc_clk(rcc_clk),\n .address(address),\n .din(din),\n .digit_clk(digit_clk),\n .dout(dout),\n`ifdef NETLIST\n .dout_flag(dout_flag),\n .scan_in0(scan_in0),\n .scan_in1(scan_in1),\n .scan_en(scan_en)\n`else\n .dout_flag(dout_flag)\n`endif\n ) ;\n\n\ninitial\nbegin\n $timeformat(-9,2,\"ns\", 16);\n`ifdef SDFSCAN\n $sdf_annotate(\"sdf/results_conv_tsmc18_scan.sdf\", test.top);\n`endif\n test_mode = 0;\n scan_in0 = 0;\n scan_in1 = 0;\n scan_en = 0;\n\n address[3:0] = 4'b0000;\n g_address[3:0] = 4'b0000;\n\n clk = 1'b0;\n din[15:0] = 16'b0000000000000000;\n g_din[15:0] = 16'b0000000000000000;\n\n rcc_clk = 1'b0;\n test_mode = 1'b0;\n reset = 1'b0;\n @(negedge clk) ;\n @(negedge clk) ;\n reset = 1'b1;\n @(negedge clk) ;\n @(negedge clk) ;\n reset = 1'b0;\n\n repeat (1024)\n begin\n digcnt = $random ;\n repeat (digcnt)\n begin\n repeat (4)\n @(posedge clk);\n g_address = 0 ;\n g_din = $random ;\n repeat (8)\n begin\n write_it ;\n g_address = g_address + 1 ;\n g_din = $random ;\n end\n write_it ;\n g_address = 0 ;\n repeat (160)\n @(posedge clk) ;\n end\n qcnt = $random ;\n repeat (qcnt)\n begin\n repeat (4)\n @(posedge clk);\n g_address = 0 ;\n g_din = 0 ;\n repeat (8)\n begin\n write_it ;\n g_address = g_address + 1 ;\n end\n write_it ;\n g_address = 0 ;\n repeat (160)\n @(posedge clk) ;\n end\n end\n $stop ;\nend\n\nalways #25 clk = ~clk ;\n\n\n", "right_context": " $display( \"Time: %t\", $time, \", Digit Clock: %b\", digit_clk, \", Digit: \\\"%c\\\"\", dout, \", Dout Flag: %b\", dout_flag );\nend\n\ntask write_it ;\n begin\n @(posedge clk) ;\n address <= g_address ;\n din <= g_din ;\n @(posedge clk)\n rcc_clk <= 1 ;\n @(posedge clk)\n rcc_clk <= 0 ;\n @(posedge clk) ;\n din <= 'bz ;\n end\nendtask\n\nendmodule\n", "groundtruth": "always @(posedge digit_clk)\nbegin\n", "crossfile_context": ""}
{"task_id": "easyUVM", "path": "easyUVM/adder.sv", "left_context": "module adder(input_if.port inter, output_if.port out_inter, output state);\n enum logic [1:0] {INITIAL,WAIT,SEND} state;\n \n always_ff @(posedge inter.clk)\n if(inter.rst) begin\n inter.ready <= 0;\n out_inter.data <= 'x;\n out_inter.valid <= 0;\n state <= INITIAL;\n end\n else case(state)\n", "right_context": " WAIT: begin\n if(inter.valid) begin\n inter.ready <= 0;\n out_inter.data <= inter.A + inter.B;\n out_inter.valid <= 1;\n state <= SEND;\n end\n end\n \n SEND: begin\n if(out_inter.ready) begin\n out_inter.valid <= 0;\n inter.ready <= 1;\n state <= WAIT;\n end\n end\n endcase\nendmodule: adder\n", "groundtruth": " INITIAL: begin\n inter.ready <= 1;\n state <= WAIT;\n", "crossfile_context": ""}
{"task_id": "easyUVM", "path": "easyUVM/agent.sv", "left_context": "class agent extends uvm_agent;\n sequencer sqr;\n driver drv;\n monitor mon;\n\n uvm_analysis_port #(packet_in) item_collected_port;\n\n `uvm_component_utils(agent)\n\n function new(string name = \"agent\", uvm_component parent = null);\n super.new(name, parent);\n item_collected_port = new(\"item_collected_port\", this);\n endfunction\n\n virtual function void build_phase(uvm_phase phase);\n super.build_phase(phase);\n mon = monitor::type_id::create(\"mon\", this);\n sqr = sequencer::type_id::create(\"sqr\", this);\n", "right_context": " endfunction\n\n virtual function void connect_phase(uvm_phase phase);\n super.connect_phase(phase);\n mon.item_collected_port.connect(item_collected_port);\n drv.seq_item_port.connect(sqr.seq_item_export);\n endfunction\nendclass: agent\n", "groundtruth": " drv = driver::type_id::create(\"drv\", this);\n", "crossfile_context": ""}
{"task_id": "easyUVM", "path": "easyUVM/agent_out.sv", "left_context": "class agent_out extends uvm_agent;\n driver_out drv;\n monitor_out mon;\n\n uvm_analysis_port #(packet_out) item_collected_port;\n\n `uvm_component_utils(agent_out)\n\n", "right_context": " super.new(name, parent);\n item_collected_port = new(\"item_collected_port\", this);\n endfunction\n\n virtual function void build_phase(uvm_phase phase);\n super.build_phase(phase);\n mon = monitor_out::type_id::create(\"mon_out\", this);\n drv = driver_out::type_id::create(\"drv_out\", this);\n endfunction\n\n virtual function void connect_phase(uvm_phase phase);\n super.connect_phase(phase);\n mon.item_collected_port.connect(item_collected_port);\n endfunction\nendclass: agent_out\n", "groundtruth": " function new(string name = \"agent_out\", uvm_component parent = null);\n", "crossfile_context": ""}
{"task_id": "easyUVM", "path": "easyUVM/comparator.sv", "left_context": "class comparator #(type T = packet_out) extends uvm_scoreboard;\n typedef comparator #(T) this_type;\n `uvm_component_param_utils(this_type)\n\n const static string type_name = \"comparator #(T)\";\n\n uvm_put_imp #(T, this_type) from_refmod;\n uvm_analysis_imp #(T, this_type) from_dut;\n\n typedef uvm_built_in_converter #( T ) convert; \n\n int m_matches, m_mismatches;\n T exp;\n bit free;\n event compared, end_of_simulation;\n\n function new(string name, uvm_component parent);\n super.new(name, parent);\n from_refmod = new(\"from_refmod\", this);\n from_dut = new(\"from_dut\", this);\n m_matches = 0;\n m_mismatches = 0;\n exp = new(\"exp\");\n free = 1;\n endfunction\n\n virtual function string get_type_name();\n return type_name;\n endfunction\n\n task run_phase(uvm_phase phase);\n phase.raise_objection(this);\n @(end_of_simulation);\n phase.drop_objection(this);\n endtask\n\n virtual task put(T t);\n if(!free) @compared;\n exp.copy(t);\n free = 0;\n \n @compared;\n free = 1;\n endtask\n\n virtual function bit try_put(T t);\n if(free) begin\n exp.copy(t);\n free = 0;\n return 1;\n end\n else return 0;\n endfunction\n\n virtual function bit can_put();\n return free;\n endfunction\n\n virtual function void write(T rec);\n if (free)\n", "right_context": " \n if(!(exp.compare(rec))) begin\n uvm_report_warning(\"Comparator Mismatch\", \"\");\n m_mismatches++;\n end\n else begin\n uvm_report_info(\"Comparator Match\", \"\");\n m_matches++;\n end\n \n if(m_matches+m_mismatches > 100)\n -> end_of_simulation;\n \n -> compared;\n endfunction\nendclass\n", "groundtruth": " uvm_report_fatal(\"No expect transaction to compare with\", \"\");\n", "crossfile_context": ""}
{"task_id": "easyUVM", "path": "easyUVM/driver.sv", "left_context": "typedef virtual input_if input_vif;\n\nclass driver extends uvm_driver #(packet_in);\n `uvm_component_utils(driver)\n input_vif vif;\n event begin_record, end_record;\n\n function new(string name = \"driver\", uvm_component parent = null);\n super.new(name, parent);\n endfunction\n\n virtual function void build_phase(uvm_phase phase);\n super.build_phase(phase);\n", "right_context": " endfunction\n\n virtual task run_phase(uvm_phase phase);\n super.run_phase(phase);\n fork\n reset_signals();\n get_and_drive(phase);\n record_tr();\n join\n endtask\n\n virtual protected task reset_signals();\n wait (vif.rst === 1);\n forever begin\n vif.valid <= '0;\n vif.A <= 'x;\n vif.B <= 'x;\n @(posedge vif.rst);\n end\n endtask\n\n virtual protected task get_and_drive(uvm_phase phase);\n wait(vif.rst === 1);\n @(negedge vif.rst);\n @(posedge vif.clk);\n \n forever begin\n seq_item_port.get(req);\n -> begin_record;\n drive_transfer(req);\n end\n endtask\n\n virtual protected task drive_transfer(packet_in tr);\n vif.A = tr.A;\n vif.B = tr.B;\n vif.valid = 1;\n\n @(posedge vif.clk)\n \n while(!vif.ready)\n @(posedge vif.clk);\n \n -> end_record;\n @(posedge vif.clk); //hold time\n vif.valid = 0;\n @(posedge vif.clk);\n endtask\n\n virtual task record_tr();\n forever begin\n @(begin_record);\n begin_tr(req, \"driver\");\n @(end_record);\n end_tr(req);\n end\n endtask\nendclass\n", "groundtruth": " assert(uvm_config_db#(input_vif)::get(this, \"\", \"vif\", vif));\n", "crossfile_context": ""}
{"task_id": "easyUVM", "path": "easyUVM/driver_out.sv", "left_context": "typedef virtual output_if output_vif;\n\nclass driver_out extends uvm_driver #(packet_out);\n `uvm_component_utils(driver_out)\n output_vif vif;\n\n function new(string name = \"driver_out\", uvm_component parent = null);\n super.new(name, parent);\n endfunction\n\n virtual function void build_phase(uvm_phase phase);\n super.build_phase(phase);\n", "right_context": " endfunction\n\n virtual task run_phase(uvm_phase phase);\n super.run_phase(phase);\n fork\n reset_signals();\n drive(phase);\n join\n endtask\n\n virtual protected task reset_signals();\n wait (vif.rst === 1);\n forever begin\n vif.ready <= '0;\n @(posedge vif.rst);\n end\n endtask\n\n virtual protected task drive(uvm_phase phase);\n wait(vif.rst === 1);\n @(negedge vif.rst);\n forever begin\n @(posedge vif.clk);\n vif.ready <= 1;\n end\n endtask\nendclass\n", "groundtruth": " assert(uvm_config_db#(output_vif)::get(this, \"\", \"vif\", vif));\n", "crossfile_context": ""}
{"task_id": "easyUVM", "path": "easyUVM/env.sv", "left_context": "class env extends uvm_env;\n agent mst;\n refmod rfm;\n agent_out slv;\n comparator #(packet_out) comp; \n uvm_tlm_analysis_fifo #(packet_in) to_refmod;\n\n `uvm_component_utils(env)\n\n function new(string name, uvm_component parent = null);\n super.new(name, parent);\n to_refmod = new(\"to_refmod\", this); \n endfunction\n\n virtual function void build_phase(uvm_phase phase);\n super.build_phase(phase);\n mst = agent::type_id::create(\"mst\", this);\n slv = agent_out::type_id::create(\"slv\", this);\n rfm = refmod::type_id::create(\"rfm\", this);\n comp = comparator#(packet_out)::type_id::create(\"comp\", this);\n endfunction\n\n virtual function void connect_phase(uvm_phase phase);\n super.connect_phase(phase);\n // Connect MST to FIFO\n mst.item_collected_port.connect(to_refmod.analysis_export);\n \n // Connect FIFO to REFMOD\n", "right_context": " \n //Connect scoreboard\n rfm.out.connect(comp.from_refmod);\n slv.item_collected_port.connect(comp.from_dut);\n endfunction\n\n virtual function void end_of_elaboration_phase(uvm_phase phase);\n super.end_of_elaboration_phase(phase);\n endfunction\n \n virtual function void report_phase(uvm_phase phase);\n super.report_phase(phase);\n `uvm_info(get_type_name(), $sformatf(\"Reporting matched %0d\", comp.m_matches), UVM_NONE)\n if (comp.m_mismatches) begin\n `uvm_error(get_type_name(), $sformatf(\"Saw %0d mismatched samples\", comp.m_mismatches))\n end\n endfunction\nendclass\n", "groundtruth": " rfm.in.connect(to_refmod.get_export);\n", "crossfile_context": ""}
{"task_id": "easyUVM", "path": "easyUVM/input_if.sv", "left_context": "interface input_if(input clk, rst);\n logic [31:0] A, B;\n logic valid, ready;\n \n", "right_context": "endinterface\n\n", "groundtruth": " modport port(input clk, rst, A, B, valid, output ready);\n", "crossfile_context": ""}
{"task_id": "easyUVM", "path": "easyUVM/monitor.sv", "left_context": "class monitor extends uvm_monitor;\n input_vif vif;\n event begin_record, end_record;\n packet_in tr;\n uvm_analysis_port #(packet_in) item_collected_port;\n `uvm_component_utils(monitor)\n \n", "right_context": " super.new(name, parent);\n item_collected_port = new (\"item_collected_port\", this);\n endfunction\n\n virtual function void build_phase(uvm_phase phase);\n super.build_phase(phase);\n assert(uvm_config_db#(input_vif)::get(this, \"\", \"vif\", vif));\n tr = packet_in::type_id::create(\"tr\", this);\n endfunction\n\n virtual task run_phase(uvm_phase phase);\n super.run_phase(phase);\n fork\n collect_transactions(phase);\n record_tr();\n join\n endtask\n\n virtual task collect_transactions(uvm_phase phase);\n wait(vif.rst === 1);\n @(negedge vif.rst);\n \n forever begin\n do begin\n @(posedge vif.clk);\n end while (vif.valid === 0 || vif.ready === 0);\n -> begin_record;\n \n tr.A = vif.A;\n tr.B = vif.B;\n item_collected_port.write(tr);\n\n @(posedge vif.clk);\n -> end_record;\n end\n endtask\n\n virtual task record_tr();\n forever begin\n @(begin_record);\n begin_tr(tr, \"monitor\");\n @(end_record);\n end_tr(tr);\n end\n endtask\nendclass\n", "groundtruth": " function new(string name, uvm_component parent);\n", "crossfile_context": ""}
{"task_id": "easyUVM", "path": "easyUVM/monitor_out.sv", "left_context": "class monitor_out extends uvm_monitor;\n `uvm_component_utils(monitor_out)\n", "right_context": " event begin_record, end_record;\n packet_out tr;\n uvm_analysis_port #(packet_out) item_collected_port;\n \n function new(string name, uvm_component parent);\n super.new(name, parent);\n item_collected_port = new (\"item_collected_port\", this);\n endfunction\n\n virtual function void build_phase(uvm_phase phase);\n super.build_phase(phase);\n assert(uvm_config_db#(output_vif)::get(this, \"\", \"vif\", vif));\n tr = packet_out::type_id::create(\"tr\", this);\n endfunction\n\n virtual task run_phase(uvm_phase phase);\n super.run_phase(phase);\n fork\n collect_transactions(phase);\n record_tr();\n join\n endtask\n\n virtual task collect_transactions(uvm_phase phase);\n wait(vif.rst === 1);\n @(negedge vif.rst);\n \n forever begin\n do begin\n @(posedge vif.clk);\n end while (vif.valid === 0 || vif.ready === 0);\n -> begin_record;\n \n tr.data = vif.data;\n item_collected_port.write(tr);\n\n @(posedge vif.clk);\n -> end_record;\n end\n endtask\n\n virtual task record_tr();\n forever begin\n @(begin_record);\n begin_tr(tr, \"monitor_out\");\n @(end_record);\n end_tr(tr);\n end\n endtask\nendclass\n", "groundtruth": " output_vif vif;\n", "crossfile_context": ""}
{"task_id": "easyUVM", "path": "easyUVM/output_if.sv", "left_context": "", "right_context": " logic [31:0] data;\n logic valid, ready;\n \n modport port(input clk, rst, output valid, data, ready);\nendinterface\n\n", "groundtruth": "interface output_if(input clk, rst);\n", "crossfile_context": ""}
{"task_id": "easyUVM", "path": "easyUVM/packet_in.sv", "left_context": "class packet_in extends uvm_sequence_item;\n rand integer A;\n rand integer B;\n\n `uvm_object_utils_begin(packet_in)\n `uvm_field_int(A, UVM_ALL_ON|UVM_HEX)\n", "right_context": " `uvm_object_utils_end\n\n function new(string name=\"packet_in\");\n super.new(name);\n endfunction: new\nendclass: packet_in\n", "groundtruth": " `uvm_field_int(B, UVM_ALL_ON|UVM_HEX)\n", "crossfile_context": ""}
{"task_id": "easyUVM", "path": "easyUVM/packet_out.sv", "left_context": "class packet_out extends uvm_sequence_item;\n integer data;\n\n `uvm_object_utils_begin(packet_out)\n `uvm_field_int(data, UVM_ALL_ON|UVM_HEX)\n `uvm_object_utils_end\n\n", "right_context": " super.new(name);\n endfunction: new\nendclass: packet_out\n", "groundtruth": " function new(string name=\"packet_out\");\n", "crossfile_context": ""}
{"task_id": "easyUVM", "path": "easyUVM/refmod.sv", "left_context": "import \"DPI-C\" context function int sum(int a, int b);\n\nclass refmod extends uvm_component;\n `uvm_component_utils(refmod)\n \n packet_in tr_in;\n packet_out tr_out;\n integer a, b;\n uvm_get_port #(packet_in) in;\n uvm_put_port #(packet_out) out;\n \n function new(string name = \"refmod\", uvm_component parent);\n super.new(name, parent);\n in = new(\"in\", this);\n out = new(\"out\", this);\n endfunction\n \n virtual function void build_phase(uvm_phase phase);\n super.build_phase(phase);\n", "right_context": " endfunction: build_phase\n \n virtual task run_phase(uvm_phase phase);\n super.run_phase(phase);\n \n forever begin\n in.get(tr_in);\n tr_out.data = sum(tr_in.A, tr_in.B);\n out.put(tr_out);\n end\n endtask: run_phase\nendclass: refmod\n", "groundtruth": " tr_out = packet_out::type_id::create(\"tr_out\", this);\n", "crossfile_context": ""}
{"task_id": "easyUVM", "path": "easyUVM/sequence_in.sv", "left_context": "class sequence_in extends uvm_sequence #(packet_in);\n `uvm_object_utils(sequence_in)\n\n function new(string name=\"sequence_in\");\n super.new(name);\n endfunction: new\n\n task body;\n packet_in tx;\n\n forever begin\n tx = packet_in::type_id::create(\"tx\");\n start_item(tx);\n", "right_context": " finish_item(tx);\n end\n endtask: body\nendclass: sequence_in\n\n", "groundtruth": " assert(tx.randomize());\n", "crossfile_context": ""}
{"task_id": "easyUVM", "path": "easyUVM/sequencer.sv", "left_context": "", "right_context": " `uvm_component_utils(sequencer)\n\n function new (string name = \"sequencer\", uvm_component parent = null);\n super.new(name, parent);\n endfunction\nendclass: sequencer\n", "groundtruth": "class sequencer extends uvm_sequencer #(packet_in);\n", "crossfile_context": ""}
{"task_id": "easyUVM", "path": "easyUVM/simple_test.sv", "left_context": "class simple_test extends uvm_test;\n env env_h;\n", "right_context": "\n `uvm_component_utils(simple_test)\n\n function new(string name, uvm_component parent = null);\n super.new(name, parent);\n endfunction\n\n virtual function void build_phase(uvm_phase phase);\n super.build_phase(phase);\n env_h = env::type_id::create(\"env_h\", this);\n seq = sequence_in::type_id::create(\"seq\", this);\n endfunction\n \n task run_phase(uvm_phase phase);\n seq.start(env_h.mst.sqr);\n endtask: run_phase\n\nendclass\n", "groundtruth": " sequence_in seq;\n", "crossfile_context": ""}
{"task_id": "easyUVM", "path": "easyUVM/top.sv", "left_context": "import uvm_pkg::*;\n`include \"uvm_macros.svh\"\n`include \"./input_if.sv\"\n`include \"./output_if.sv\"\n`include \"./adder.sv\"\n`include \"./packet_in.sv\"\n`include \"./packet_out.sv\"\n`include \"./sequence_in.sv\"\n`include \"./sequencer.sv\"\n`include \"./driver.sv\"\n`include \"./driver_out.sv\"\n`include \"./monitor.sv\"\n`include \"./monitor_out.sv\"\n`include \"./agent.sv\"\n`include \"./agent_out.sv\"\n`include \"./refmod.sv\"\n`include \"./comparator.sv\"\n`include \"./env.sv\"\n`include \"./simple_test.sv\"\n\n//Top\nmodule top;\n logic clk;\n logic rst;\n \n initial begin\n clk = 0;\n rst = 1;\n #22 rst = 0;\n \n end\n \n always #5 clk = !clk;\n", "right_context": " input_if in(clk, rst);\n output_if out(clk, rst);\n \n adder sum(in, out, state);\n\n initial begin\n `ifdef INCA\n $recordvars();\n `endif\n `ifdef VCS\n $vcdpluson;\n `endif\n `ifdef QUESTA\n $wlfdumpvars();\n set_config_int(\"*\", \"recording_detail\", 1);\n `endif\n \n uvm_config_db#(input_vif)::set(uvm_root::get(), \"*.env_h.mst.*\", \"vif\", in);\n uvm_config_db#(output_vif)::set(uvm_root::get(), \"*.env_h.slv.*\", \"vif\", out);\n \n run_test(\"simple_test\");\n end\nendmodule\n", "groundtruth": " \n logic [1:0] state;\n", "crossfile_context": ""}
{"task_id": "svreal", "path": "svreal/svreal/svreal.sv", "left_context": "`ifndef __SVREAL_SV__\n`define __SVREAL_SV__\n\n// include files for Berkeley HardFloat if needed\n`ifdef HARD_FLOAT\n `include \"HardFloat_consts.vi\"\n\n `ifndef HARD_FLOAT_CONTROL\n `define HARD_FLOAT_CONTROL `flControl_tininessAfterRounding\n `endif\n `ifndef HARD_FLOAT_ROUNDING\n `define HARD_FLOAT_ROUNDING `round_near_even\n `endif\n`endif\n\n// fixed-point representation defaults\n// (can override by defining them externally)\n\n`ifndef SHORT_WIDTH_REAL\n `define SHORT_WIDTH_REAL 18\n`endif\n\n`ifndef LONG_WIDTH_REAL\n `define LONG_WIDTH_REAL 25\n`endif\n\n// configuration for Berkeley HardFloat, if used\n\n`ifndef HARD_FLOAT_EXP_WIDTH\n `define HARD_FLOAT_EXP_WIDTH 8\n`endif\n\n`ifndef HARD_FLOAT_SIG_WIDTH\n `define HARD_FLOAT_SIG_WIDTH 23\n`endif\n\n`define HARD_FLOAT_WIDTH (1+(`HARD_FLOAT_EXP_WIDTH)+(`HARD_FLOAT_SIG_WIDTH))\n\n`define HARD_FLOAT_SIGN_BIT ((`HARD_FLOAT_SIG_WIDTH)+(`HARD_FLOAT_EXP_WIDTH))\n\n// declare a more generic version of $clog2 that supports\n// real number inputs, which is needed to automatically\n// compute exponents. the the value returned is\n// int(ceil(log2(x)))\nfunction int clog2_math(input real x);\n clog2_math = 0;\n if (x > 0) begin\n while (x < (2.0**(clog2_math))) begin\n clog2_math = clog2_math - 1;\n end\n while (x > (2.0**(clog2_math))) begin\n clog2_math = clog2_math + 1;\n end\n end\nendfunction\n\n`define CALC_EXP(range, width) (clog2_math((real'(range))/((2.0**((width)-1))-1.0)))\n\n`define MAX_MATH(a, b) \\\n (((a) > (b)) ? (a) : (b))\n\n`define MIN_MATH(a, b) \\\n (((a) < (b)) ? (a) : (b))\n\n`define ABS_MATH(a) \\\n (((a) > 0) ? (a) : (-(a)))\n\n`define FIXED_TO_FLOAT(significand, exponent) \\\n ((significand)*(2.0**(exponent)))\n\n`define FLOAT_TO_FIXED(value, exponent) \\\n ((real'(value))*(2.0**(-(exponent))))\n\n// convert the HardFloat recoded format to a real number\nfunction real recfn2real(input logic [((`HARD_FLOAT_EXP_WIDTH)+(`HARD_FLOAT_SIG_WIDTH)):0] in);\n // recoded format\n logic rec_sign;\n logic [(`HARD_FLOAT_EXP_WIDTH):0] rec_exp;\n logic [((`HARD_FLOAT_SIG_WIDTH)-2):0] rec_sig;\n logic [2:0] rec_exp_top;\n\n // double-precision format\n logic dbl_sign;\n logic [10:0] dbl_exp;\n logic [51:0] dbl_sig;\n logic [63:0] dbl_bits;\n\n // deconstruct input\n rec_sign = in[`HARD_FLOAT_SIGN_BIT];\n rec_exp = in[((`HARD_FLOAT_SIGN_BIT)-1):((`HARD_FLOAT_SIGN_BIT)-1-((`HARD_FLOAT_EXP_WIDTH)+1)+1)];\n rec_sig = in[((`HARD_FLOAT_SIG_WIDTH)-2):0];\n rec_exp_top = rec_exp[(`HARD_FLOAT_EXP_WIDTH):((`HARD_FLOAT_EXP_WIDTH)-3+1)];\n\n // walk through various cases\n if (rec_exp_top == 3'b000) begin\n // zero\n dbl_sign = rec_sign;\n dbl_exp = 0;\n dbl_sig = 0;\n end else if (rec_exp_top == 3'b110) begin\n // infinities\n dbl_sign = rec_sign;\n dbl_exp = '1;\n dbl_sig = '0;\n end else if (rec_exp_top == 3'b111) begin\n // NaNs\n dbl_sign = rec_sign;\n dbl_exp = '1;\n dbl_sig = '1;\n end else if (rec_exp < ((2**((`HARD_FLOAT_EXP_WIDTH)-1))+2)) begin\n // TODO: implement subnormal (treated as zero for now)\n dbl_sign = rec_sign;\n dbl_exp = 0;\n dbl_sig = 0;\n end else begin\n // normal\n dbl_sign = rec_sign;\n dbl_exp = rec_exp\n - ((2**((`HARD_FLOAT_EXP_WIDTH)-1))+1) // remove recoding offset\n - ((2**((`HARD_FLOAT_EXP_WIDTH)-1))-1) // remove exponent bias\n + 1023; // apply exponent bias\n if (((`HARD_FLOAT_SIG_WIDTH)-1) < 52) begin\n // zero-pad\n dbl_sig = rec_sig << (52-((`HARD_FLOAT_SIG_WIDTH)-1));\n end else begin\n // truncate\n dbl_sig = rec_sig >> (((`HARD_FLOAT_SIG_WIDTH)-1)-52);\n end\n end\n\n // assign the output\n dbl_bits = {dbl_sign, dbl_exp, dbl_sig};\n recfn2real = $bitstoreal(dbl_bits);\nendfunction\n\n`define REC_FN_TO_REAL(value) recfn2real(value)\n\n// convert a real number to the HardFloat recoded format\nfunction logic [((`HARD_FLOAT_EXP_WIDTH)+(`HARD_FLOAT_SIG_WIDTH)):0] real2recfn(input real in);\n // double-precision format\n logic dbl_sign;\n logic [10:0] dbl_exp;\n logic [51:0] dbl_sig;\n logic [63:0] dbl_bits;\n\n // recoded format\n logic rec_sign;\n int rec_exp_int;\n logic [(`HARD_FLOAT_EXP_WIDTH):0] rec_exp;\n logic [((`HARD_FLOAT_SIG_WIDTH)-2):0] rec_sig;\n\n // deconstruct input\n dbl_bits = $realtobits(in);\n dbl_sign = dbl_bits[63];\n dbl_exp = dbl_bits[62:52];\n dbl_sig = dbl_bits[51:0];\n\n if (dbl_exp == 0) begin\n // zero or subnormal\n // TODO: handle subnormal properly\n rec_sign = dbl_sign;\n rec_exp = '0;\n rec_sig = '0;\n end else if (dbl_exp == 11'h7FF) begin\n if (dbl_sig == 0) begin\n // infinities\n rec_sign = dbl_sign;\n rec_exp = {3'b110, {((`HARD_FLOAT_EXP_WIDTH)-2){1'b0}}};\n rec_sig = '0;\n end else begin\n // NaNs\n rec_sign = dbl_sign;\n rec_exp = {3'b111, {((`HARD_FLOAT_EXP_WIDTH)-2){1'b0}}};\n rec_sig = '0;\n end\n end else begin\n // normal\n rec_sign = dbl_sign;\n rec_exp_int = dbl_exp\n - 1023 // remove exponent bias\n + ((2**((`HARD_FLOAT_EXP_WIDTH)-1))-1) // apply exponent bias\n + ((2**((`HARD_FLOAT_EXP_WIDTH)-1))+1); // apply recoding bias\n if (rec_exp_int < ((2**((`HARD_FLOAT_EXP_WIDTH)-1))+2)) begin\n // TODO: handle case where input is normal but output is subnormal\n // for now the output is simply zero\n rec_exp = '0;\n rec_sig = '0;\n end else if (rec_exp_int > ((3*(2**((`HARD_FLOAT_EXP_WIDTH)-1)))-1)) begin\n // Exponent is too large to be represented, so treat as an infinity\n rec_exp = {3'b110, {((`HARD_FLOAT_EXP_WIDTH)-2){1'b0}}};\n rec_sig = '0;\n end else begin\n rec_exp = rec_exp_int;\n if (((`HARD_FLOAT_SIG_WIDTH)-1) > 52) begin\n // zero-pad (lossless)\n rec_sig = dbl_sig << (((`HARD_FLOAT_SIG_WIDTH)-1)-52);\n end else begin\n // truncate (lossy)\n rec_sig = dbl_sig >> (52-((`HARD_FLOAT_SIG_WIDTH)-1));\n end\n end\n end\n\n // assign the output\n real2recfn = {rec_sign, rec_exp, rec_sig};\nendfunction\n\n`define REAL_TO_REC_FN(value) real2recfn(value)\n\n// real number parameters\n// width and exponent are only used for the fixed-point\n// representation\n\n`define RANGE_PARAM_REAL(name) ``name``_range_val\n\n`define WIDTH_PARAM_REAL(name) ``name``_width_val\n\n`define EXPONENT_PARAM_REAL(name) ``name``_exponent_val\n\n`define PRINT_FORMAT_REAL(name) \\\n $display(`\"``name``: {width=%0d, exponent=%0d, range=%0f}`\", `WIDTH_PARAM_REAL(name), `EXPONENT_PARAM_REAL(name), `RANGE_PARAM_REAL(name))\n\n// real number representation type\n\n`define DATA_TYPE_REAL(width_expr) \\\n `ifdef FLOAT_REAL \\\n real \\\n `elsif HARD_FLOAT \\\n logic [(`HARD_FLOAT_SIGN_BIT):0] \\\n `else \\\n logic signed [((width_expr)-1):0] \\\n `endif\n \n// module ports\n\n`define DECL_REAL(port) \\\n parameter real `RANGE_PARAM_REAL(port) = 0, \\\n parameter integer `WIDTH_PARAM_REAL(port) = 0, \\\n parameter integer `EXPONENT_PARAM_REAL(port) = 0\n\n`define PASS_REAL(port, name) \\\n .`RANGE_PARAM_REAL(port)(`RANGE_PARAM_REAL(name)), \\\n .`WIDTH_PARAM_REAL(port)(`WIDTH_PARAM_REAL(name)), \\\n .`EXPONENT_PARAM_REAL(port)(`EXPONENT_PARAM_REAL(name))\n\n`define PORT_REAL(port) \\\n `ifdef FLOAT_REAL \\\n `DATA_TYPE_REAL(`WIDTH_PARAM_REAL(port)) port \\\n `else \\\n wire `DATA_TYPE_REAL(`WIDTH_PARAM_REAL(port)) port \\\n `endif\n\n`define INPUT_REAL(port) input `PORT_REAL(port)\n\n`define OUTPUT_REAL(port) output `PORT_REAL(port)\n\n// Displaying real number signals\n\n`define TO_REAL(name) \\\n `ifdef FLOAT_REAL \\\n (name) \\\n `elsif HARD_FLOAT \\\n (`REC_FN_TO_REAL(name)) \\\n `else \\\n\t\t(`FIXED_TO_FLOAT((name), (`EXPONENT_PARAM_REAL(name)))) \\\n `endif\n\n`define PRINT_REAL(name) \\\n $display(`\"``name``=%0f`\", `TO_REAL(name))\n\n// force a real number\n\n`define FROM_REAL(expr, name) \\\n `ifdef FLOAT_REAL \\\n (expr) \\\n `elsif HARD_FLOAT \\\n (`REAL_TO_REC_FN(expr)) \\\n `else \\\n\t\t(`FLOAT_TO_FIXED((expr), (`EXPONENT_PARAM_REAL(name)))) \\\n `endif\n\n`define FORCE_REAL(expr, name) \\\n name = `FROM_REAL(expr, name)\n\n// assert that real number is within specified range\n\n`define ASSERTION_REAL(in_name) \\\n assertion_real #( \\\n `PASS_REAL(in, in_name), \\\n .name(`\"``in_name```\") \\\n ) assertion_real_``in_name``_i ( \\\n .in(in_name) \\\n )\n\n// creating real numbers\n// the data type declaration comes first so that directives like mark_debug\n// and dont_touch can be used\n\n`define MAKE_FORMAT_REAL(name, range_expr, width_expr, exponent_expr) \\\n `DATA_TYPE_REAL(width_expr) name; \\\n localparam real `RANGE_PARAM_REAL(name) = range_expr; \\\n localparam integer `WIDTH_PARAM_REAL(name) = width_expr; \\\n localparam integer `EXPONENT_PARAM_REAL(name) = exponent_expr \\\n `ifdef RANGE_ASSERTIONS \\\n ; `ASSERTION_REAL(name) \\\n `endif\n\n`define REAL_FROM_WIDTH_EXP(name, width_expr, exponent_expr) \\\n `MAKE_FORMAT_REAL(name, 2.0**((width_expr)+(exponent_expr)-1), width_expr, exponent_expr)\n\n// copying real number format\n\n`define GET_FORMAT_REAL(in_name) \\\n `DATA_TYPE_REAL(`WIDTH_PARAM_REAL(in_name))\n\n`define COPY_FORMAT_REAL(in_name, out_name) \\\n `MAKE_FORMAT_REAL(out_name, `RANGE_PARAM_REAL(in_name), `WIDTH_PARAM_REAL(in_name), `EXPONENT_PARAM_REAL(in_name))\n\n// negation\n// note that since the range of a fixed-point number is defined as +/- |range|, the negation of \n// the fixed point numbers can always be represented in the original format.\n\n`define NEGATE_INTO_REAL(in_name, out_name) \\\n negate_real #( \\\n `PASS_REAL(in, in_name), \\\n `PASS_REAL(out, out_name) \\\n ) negate_real_``out_name``_i ( \\\n .in(in_name), \\\n .out(out_name) \\\n ) \n\n`define NEGATE_REAL(in_name, out_name) \\\n `COPY_FORMAT_REAL(in_name, out_name); \\\n `NEGATE_INTO_REAL(in_name, out_name)\n\n// absolute value\n\n`define ABS_INTO_REAL(in_name, out_name) \\\n abs_real #( \\\n `PASS_REAL(in, in_name), \\\n `PASS_REAL(out, out_name) \\\n ) abs_real_``out_name``_i ( \\\n .in(in_name), \\\n .out(out_name) \\\n ) \n\n`define ABS_REAL(in_name, out_name) \\\n `COPY_FORMAT_REAL(in_name, out_name); \\\n `ABS_INTO_REAL(in_name, out_name)\n\n// construct real number from range\n// the following four macros depend on clog2_math\n\n`define MAKE_GENERIC_REAL(name, range_expr, width_expr) \\\n `MAKE_FORMAT_REAL(name, range_expr, width_expr, `CALC_EXP(range_expr, width_expr))\n\n`define MAKE_SHORT_REAL(name, range_expr) \\\n `MAKE_GENERIC_REAL(name, range_expr, `SHORT_WIDTH_REAL)\n\n`define MAKE_LONG_REAL(name, range_expr) \\\n `MAKE_GENERIC_REAL(name, range_expr, `LONG_WIDTH_REAL)\n\n`define MAKE_REAL(name, range_expr) \\\n `MAKE_LONG_REAL(name, range_expr)\n \n// assigning real numbers\n// note that the negative version of each number will already have be assigned when\n// out_name was defined\n\n`define ASSIGN_REAL(in_name, out_name) \\\n assign_real #( \\\n `PASS_REAL(in, in_name), \\\n `PASS_REAL(out, out_name) \\\n ) assign_real_``out_name``_i ( \\\n .in(in_name), \\\n .out(out_name) \\\n ) \n\n// real constants\n// range is skewed just a bit higher to make sure that the \n// fixed-point representation falls within the range\n\n`define ASSIGN_CONST_REAL(const_expr, name) \\\n assign name = `FROM_REAL(const_expr, name)\n\n`define CONST_RANGE_REAL(const_expr) \\\n (1.01*`ABS_MATH(const_expr))\n\n`define MAKE_GENERIC_CONST_REAL(const_expr, name, width_expr) \\\n `MAKE_GENERIC_REAL(name, `CONST_RANGE_REAL(const_expr), width_expr); \\\n `ASSIGN_CONST_REAL(const_expr, name)\n\n`define MAKE_SHORT_CONST_REAL(const_expr, name) \\\n `MAKE_GENERIC_CONST_REAL(const_expr, name, `SHORT_WIDTH_REAL)\n\n`define MAKE_LONG_CONST_REAL(const_expr, name) \\\n `MAKE_GENERIC_CONST_REAL(const_expr, name, `LONG_WIDTH_REAL)\n\n`define MAKE_CONST_REAL(const_expr, name) \\\n `MAKE_LONG_CONST_REAL(const_expr, name)\n\n// multiplication of two variables\n\n`define MUL_INTO_REAL(a_name, b_name, c_name) \\\n mul_real #( \\\n `PASS_REAL(a, a_name), \\\n `PASS_REAL(b, b_name), \\\n `PASS_REAL(c, c_name) \\\n ) mul_real_``c_name``_i ( \\\n .a(a_name), \\\n .b(b_name), \\\n .c(c_name) \\\n )\n \n`define MUL_REAL_GENERIC(a_name, b_name, c_name, c_width) \\\n `MAKE_GENERIC_REAL(c_name, `RANGE_PARAM_REAL(a_name)*`RANGE_PARAM_REAL(b_name), c_width); \\\n `MUL_INTO_REAL(a_name, b_name, c_name)\n\n`define MUL_REAL(a_name, b_name, c_name) \\\n `MUL_REAL_GENERIC(a_name, b_name, c_name, `LONG_WIDTH_REAL)\n\n// multiplication of a constant and variable\n\n`define MUL_CONST_INTO_REAL_GENERIC(const_expr, in_name, out_name, const_width) \\\n `MAKE_GENERIC_CONST_REAL(const_expr, zzz_tmp_``out_name``, const_width); \\\n `MUL_INTO_REAL(zzz_tmp_``out_name``, in_name, out_name)\n\n`define MUL_CONST_INTO_REAL(const_expr, in_name, out_name) \\\n `MUL_CONST_INTO_REAL_GENERIC(const_expr, in_name, out_name, `SHORT_WIDTH_REAL)\n\n`define MUL_CONST_REAL_GENERIC(const_expr, in_name, out_name, const_width, out_width) \\\n `MAKE_GENERIC_REAL(out_name, `CONST_RANGE_REAL(const_expr)*`RANGE_PARAM_REAL(in_name), out_width); \\\n `MUL_CONST_INTO_REAL_GENERIC(const_expr, in_name, out_name, const_width)\n\n`define MUL_CONST_REAL(const_expr, in_name, out_name) \\\n `MUL_CONST_REAL_GENERIC(const_expr, in_name, out_name, `SHORT_WIDTH_REAL, `LONG_WIDTH_REAL)\n\n// generic addition or subtraction\n\n`define ADD_SUB_INTO_REAL(opcode_value, a_name, b_name, c_name) \\\n add_sub_real #( \\\n `PASS_REAL(a, a_name), \\\n `PASS_REAL(b, b_name), \\\n `PASS_REAL(c, c_name), \\\n\t\t.opcode(opcode_value) \\\n ) add_sub_real_``c_name``_i ( \\\n .a(a_name), \\\n .b(b_name), \\\n .c(c_name) \\\n )\n\n// addition of two variables\n\n`define ADD_OPCODE_REAL 0\n\n`define ADD_INTO_REAL(a_name, b_name, c_name) \\\n `ADD_SUB_INTO_REAL(`ADD_OPCODE_REAL, a_name, b_name, c_name)\n\n`define ADD_REAL_GENERIC(a_name, b_name, c_name, c_width) \\\n `MAKE_GENERIC_REAL(c_name, `RANGE_PARAM_REAL(a_name) + `RANGE_PARAM_REAL(b_name), c_width); \\\n `ADD_INTO_REAL(a_name, b_name, c_name)\n\n`define ADD_REAL(a_name, b_name, c_name) \\\n `ADD_REAL_GENERIC(a_name, b_name, c_name, `LONG_WIDTH_REAL)\n \n// addition of a constant and a variable\n\n`define ADD_CONST_INTO_REAL_GENERIC(const_expr, in_name, out_name, const_width) \\\n `MAKE_GENERIC_CONST_REAL(const_expr, zzz_tmp_``out_name``, const_width); \\\n `ADD_INTO_REAL(zzz_tmp_``out_name``, in_name, out_name)\n\n`define ADD_CONST_INTO_REAL(const_expr, in_name, out_name) \\\n `ADD_CONST_INTO_REAL_GENERIC(const_expr, in_name, out_name, `LONG_WIDTH_REAL)\n\n`define ADD_CONST_REAL_GENERIC(const_expr, in_name, out_name, const_width, out_width) \\\n `MAKE_GENERIC_REAL(out_name, `CONST_RANGE_REAL(const_expr) + `RANGE_PARAM_REAL(in_name), out_width); \\\n `ADD_CONST_INTO_REAL_GENERIC(const_expr, in_name, out_name, const_width)\n\n`define ADD_CONST_REAL(const_expr, in_name, out_name) \\\n `ADD_CONST_REAL_GENERIC(const_expr, in_name, out_name, `LONG_WIDTH_REAL, `LONG_WIDTH_REAL)\n\n// addition of three variables\n\n`define ADD3_INTO_REAL_GENERIC(a_name, b_name, c_name, d_name, tmp_width) \\\n `ADD_REAL_GENERIC(a_name, b_name, zzz_tmp_``d_name``, tmp_width); \\\n `ADD_INTO_REAL(zzz_tmp_``d_name``, c_name, d_name)\n\n`define ADD3_INTO_REAL(a_name, b_name, c_name, d_name) \\\n `ADD3_INTO_REAL_GENERIC(a_name, b_name, c_name, d_name, `LONG_WIDTH_REAL)\n\n`define ADD3_REAL_GENERIC(a_name, b_name, c_name, d_name, tmp_width, d_width) \\\n `MAKE_GENERIC_REAL(d_name, `RANGE_PARAM_REAL(a_name) + `RANGE_PARAM_REAL(b_name) + `RANGE_PARAM_REAL(c_name), d_width); \\\n `ADD3_INTO_REAL_GENERIC(a_name, b_name, c_name, d_name, tmp_width)\n\n`define ADD3_REAL(a_name, b_name, c_name, d_name) \\\n `ADD3_REAL_GENERIC(a_name, b_name, c_name, d_name, `LONG_WIDTH_REAL, `LONG_WIDTH_REAL)\n\n// subtraction of two variables\n\n`define SUB_OPCODE_REAL 1\n\n`define SUB_INTO_REAL(a_name, b_name, c_name) \\\n `ADD_SUB_INTO_REAL(`SUB_OPCODE_REAL, a_name, b_name, c_name)\n\n`define SUB_REAL_GENERIC(a_name, b_name, c_name, c_width) \\\n `MAKE_GENERIC_REAL(c_name, `RANGE_PARAM_REAL(a_name) + `RANGE_PARAM_REAL(b_name), c_width); \\\n `SUB_INTO_REAL(a_name, b_name, c_name)\n\n`define SUB_REAL(a_name, b_name, c_name) \\\n `SUB_REAL_GENERIC(a_name, b_name, c_name, `LONG_WIDTH_REAL)\n\n// conditional assignment\n\n`define ITE_INTO_REAL(cond_name, true_name, false_name, out_name) \\\n ite_real #( \\\n `PASS_REAL(true, true_name), \\\n `PASS_REAL(false, false_name), \\\n `PASS_REAL(out, out_name) \\\n ) ite_real_``out_name``_i ( \\\n .cond(cond_name), \\\n .true(true_name), \\\n .false(false_name), \\\n .out(out_name) \\\n )\n\n`define ITE_REAL_GENERIC(cond_name, true_name, false_name, out_name, out_width) \\\n `MAKE_GENERIC_REAL(out_name, `MAX_MATH(`RANGE_PARAM_REAL(true_name), `RANGE_PARAM_REAL(false_name)), out_width); \\\n `ITE_INTO_REAL(cond_name, true_name, false_name, out_name)\n\n`define ITE_REAL(cond_name, true_name, false_name, out_name) \\\n `ITE_REAL_GENERIC(cond_name, true_name, false_name, out_name, `LONG_WIDTH_REAL) \\\n\n// generic comparison\n\n`define COMP_INTO_REAL(opcode_value, a_name, b_name, c_name) \\\n comp_real #( \\\n `PASS_REAL(a, a_name), \\\n `PASS_REAL(b, b_name), \\\n .opcode(opcode_value) \\\n ) comp_real_``c_name``_i ( \\\n .a(a_name), \\\n .b(b_name), \\\n .c(c_name) \\\n )\n\n// greater than\n\n`define GT_OPCODE_REAL 0\n\n`define GT_INTO_REAL(a_name, b_name, c_name) \\\n `COMP_INTO_REAL(`GT_OPCODE_REAL, a_name, b_name, c_name)\n\n`define GT_REAL(a_name, b_name, c_name) \\\n logic c_name; \\\n `GT_INTO_REAL(a_name, b_name, c_name)\n\n// greater than or equal to\n\n`define GE_OPCODE_REAL 1\n\n`define GE_INTO_REAL(a_name, b_name, c_name) \\\n `COMP_INTO_REAL(`GE_OPCODE_REAL, a_name, b_name, c_name)\n\n`define GE_REAL(a_name, b_name, c_name) \\\n logic c_name; \\\n `GE_INTO_REAL(a_name, b_name, c_name)\n\n// less than\n\n`define LT_OPCODE_REAL 2\n\n`define LT_INTO_REAL(a_name, b_name, c_name) \\\n `COMP_INTO_REAL(`LT_OPCODE_REAL, a_name, b_name, c_name)\n\n`define LT_REAL(a_name, b_name, c_name) \\\n logic c_name; \\\n `LT_INTO_REAL(a_name, b_name, c_name)\n\n// less than or equal to\n\n`define LE_OPCODE_REAL 3\n\n`define LE_INTO_REAL(a_name, b_name, c_name) \\\n `COMP_INTO_REAL(`LE_OPCODE_REAL, a_name, b_name, c_name)\n\n`define LE_REAL(a_name, b_name, c_name) \\\n logic c_name; \\\n `LE_INTO_REAL(a_name, b_name, c_name)\n\n// equal to\n\n`define EQ_OPCODE_REAL 4\n\n`define EQ_INTO_REAL(a_name, b_name, c_name) \\\n `COMP_INTO_REAL(`EQ_OPCODE_REAL, a_name, b_name, c_name)\n\n`define EQ_REAL(a_name, b_name, c_name) \\\n logic c_name; \\\n `EQ_INTO_REAL(a_name, b_name, c_name)\n\n// not equal to\n\n`define NE_OPCODE_REAL 5\n\n`define NE_INTO_REAL(a_name, b_name, c_name) \\\n `COMP_INTO_REAL(`NE_OPCODE_REAL, a_name, b_name, c_name)\n\n`define NE_REAL(a_name, b_name, c_name) \\\n logic c_name; \\\n `NE_INTO_REAL(a_name, b_name, c_name)\n\n// max of two variables\n\n`define MAX_INTO_REAL(a_name, b_name, c_name) \\\n `GT_REAL(a_name, b_name, zzz_tmp_``c_name``); \\\n `ITE_INTO_REAL(zzz_tmp_``c_name``, a_name, b_name, c_name)\n\n`define MAX_REAL_GENERIC(a_name, b_name, c_name, c_width) \\\n `MAKE_GENERIC_REAL(c_name, `MAX_MATH(`RANGE_PARAM_REAL(a_name), `RANGE_PARAM_REAL(b_name)), c_width); \\\n `MAX_INTO_REAL(a_name, b_name, c_name)\n\n`define MAX_REAL(a_name, b_name, c_name) \\\n `MAX_REAL_GENERIC(a_name, b_name, c_name, `LONG_WIDTH_REAL)\n\n// min of two variables\n\n`define MIN_INTO_REAL(a_name, b_name, c_name) \\\n `LT_REAL(a_name, b_name, zzz_tmp_``c_name``); \\\n `ITE_INTO_REAL(zzz_tmp_``c_name``, a_name, b_name, c_name)\n\n`define MIN_REAL_GENERIC(a_name, b_name, c_name, c_width) \\\n `MAKE_GENERIC_REAL(c_name, `MAX_MATH(`RANGE_PARAM_REAL(a_name), `RANGE_PARAM_REAL(b_name)), c_width); \\\n `MIN_INTO_REAL(a_name, b_name, c_name)\n\n`define MIN_REAL(a_name, b_name, c_name) \\\n `MIN_REAL_GENERIC(a_name, b_name, c_name, `LONG_WIDTH_REAL)\n\n// conversion from real number to integer\n// note that this always rounds down, regardless of whether HARD_FLOAT\n// is used or not.\n\n`define REAL_TO_INT(in_name, int_width_expr, out_name) \\\n `ifdef FLOAT_REAL \\\n logic signed[((int_width_expr)-1):0] out_name; \\\n assign out_name = $floor(in_name) \\\n `elsif HARD_FLOAT \\\n logic signed[((int_width_expr)-1):0] out_name; \\\n recFNToIN #( \\\n .expWidth(`HARD_FLOAT_EXP_WIDTH), \\\n .sigWidth(`HARD_FLOAT_SIG_WIDTH), \\\n .intWidth(int_width_expr) \\\n ) recFNToIN_``out_name``_i ( \\\n .control(`HARD_FLOAT_CONTROL), \\\n .in(in_name), \\\n .roundingMode(`round_min), \\\n .signedOut(1'b1), \\\n .out(out_name), \\\n .intExceptionFlags() \\\n ) \\\n `else \\\n `REAL_FROM_WIDTH_EXP(out_name, int_width_expr, 0); \\\n `ASSIGN_REAL(in_name, out_name) \\\n `endif\n\n`define REAL_INTO_INT(in_name, int_width_expr, out_name) \\\n `REAL_TO_INT(in_name, int_width_expr, zzz_tmp_``out_name``); \\\n assign out_name = zzz_tmp_``out_name``\n \n// conversion from integer to real number\n\n`define INT_TO_REAL(in_name, int_width_expr, out_name) \\\n `REAL_FROM_WIDTH_EXP(out_name, int_width_expr, 0); \\\n `ifdef FLOAT_REAL \\\n assign out_name = 1.0*(in_name) \\\n `elsif HARD_FLOAT \\\n iNToRecFN #( \\\n .intWidth(int_width_expr), \\\n .expWidth(`HARD_FLOAT_EXP_WIDTH), \\\n .sigWidth(`HARD_FLOAT_SIG_WIDTH) \\\n ) iNToRecFN_``out_name``_i ( \\\n .control(`HARD_FLOAT_CONTROL), \\\n .signedIn(1'b1), \\\n .in(in_name), \\\n .roundingMode(`HARD_FLOAT_ROUNDING), \\\n .out(out_name), \\\n .exceptionFlags() \\\n ) \\\n `else \\\n assign out_name = in_name \\\n `endif\n \n`define INT_INTO_REAL(in_name, int_width_expr, out_name) \\\n `INT_TO_REAL(in_name, int_width_expr, zzz_tmp_``out_name``); \\\n `ASSIGN_REAL(zzz_tmp_``out_name``, out_name)\n\n// get the width of an integer\n\n`define MEAS_UINT_WIDTH_INTO(in_name, in_width_expr, out_name, out_width_expr) \\\n meas_uint_width #( \\\n .in_width(in_width_expr), \\\n .out_width(out_width_expr) \\\n ) meas_uint_width_``out_name`` ( \\\n .in(in_name), \\\n .out(out_name) \\\n )\n\n`define MEAS_UINT_WIDTH(in_name, in_width_expr, out_name, out_width_expr) \\\n logic [((out_width_expr)-1):0] out_name; \\\n `MEAS_UINT_WIDTH_INTO(in_name, in_width_expr, out_name, out_width_expr)\n\n// compressing an integer into a real number using an approximately logarithmic mapping\n\n`define COMPRESS_UINT_INTO(in_name, in_width_expr, out_name) \\\n compress_uint #( \\\n .in_width(in_width_expr), \\\n `PASS_REAL(out, out_name) \\\n ) compress_uint_``out_name``_i ( \\\n .in(in_name), \\\n .out(out_name) \\\n )\n\n`define COMPRESS_UINT(in_name, in_width_expr, out_name) \\\n `MAKE_REAL(out_name, ((in_width_expr)+1)); \\\n `COMPRESS_UINT_INTO(in_name, in_width_expr, out_name)\n\n// memory\n\n`define DFF_INTO_REAL(d_name, q_name, rst_name, clk_name, cke_name, init_expr) \\\n dff_real #( \\\n `PASS_REAL(d, d_name), \\\n `PASS_REAL(q, q_name), \\\n .init(init_expr) \\\n ) dff_real_``q_name``_i ( \\\n .d(d_name), \\\n .q(q_name), \\\n .rst(rst_name), \\\n .clk(clk_name), \\\n .cke(cke_name) \\\n )\n\n`define DFF_REAL(d_name, q_name, rst_name, clk_name, cke_name, init_expr) \\\n `COPY_FORMAT_REAL(d_name, q_name); \\\n `DFF_INTO_REAL(d_name, q_name, rst_name, clk_name, cke_name, init_expr)\n\n// synchronous ROM\n// note that the data_bits_expr input is ignored when HARD_FLOAT is defined, because HARD_FLOAT\n// signals always have width HARD_FLOAT_WIDTH. this makes it easier to swap between default\n// operation (fixed-point) and HARD_FLOAT\n\n`define SYNC_ROM_INTO_REAL(addr_name, out_name, clk_name, ce_name, addr_bits_expr, data_bits_expr, file_path_expr, data_expt_expr) \\\n sync_rom_real #( \\\n `PASS_REAL(out, out_name), \\\n .addr_bits(addr_bits_expr), \\\n .data_bits( \\\n `ifdef HARD_FLOAT \\\n `HARD_FLOAT_WIDTH \\\n `else \\\n data_bits_expr \\\n `endif \\\n ), \\\n .data_expt(data_expt_expr), \\\n .file_path(file_path_expr) \\\n ) sync_rom_real_``out_name``_i ( \\\n .addr(addr_name), \\\n .out(out_name), \\\n .clk(clk_name), \\\n .ce(ce_name) \\\n )\n\n`define SYNC_ROM_REAL(addr_name, out_name, clk_name, ce_name, addr_bits_expr, data_bits_expr, file_path_expr, data_expt_expr) \\\n `REAL_FROM_WIDTH_EXP(out_name, data_bits_expr, data_expt_expr); \\\n `SYNC_ROM_INTO_REAL(addr_name, out_name, clk_name, ce_name, addr_bits_expr, data_bits_expr, file_path_expr, data_expt_expr)\n\n// synchronous RAM\n// note that the data_bits_expr input is ignored when HARD_FLOAT is defined, because HARD_FLOAT\n// signals always have width HARD_FLOAT_WIDTH. this makes it easier to swap between default\n// operation (fixed-point) and HARD_FLOAT\n\n`define SYNC_RAM_INTO_REAL(addr_name, din_name, out_name, clk_name, ce_name, we_name, addr_bits_expr, data_bits_expr, data_expt_expr) \\\n sync_ram_real #( \\\n `PASS_REAL(out, out_name), \\\n .addr_bits(addr_bits_expr), \\\n .data_bits( \\\n `ifdef HARD_FLOAT \\\n `HARD_FLOAT_WIDTH \\\n `else \\\n data_bits_expr \\\n `endif \\\n ), \\\n .data_expt(data_expt_expr) \\\n ) sync_ram_real_``out_name``_i ( \\\n .addr(addr_name), \\\n .din(din_name), \\\n .out(out_name), \\\n .clk(clk_name), \\\n .ce(ce_name), \\\n .we(we_name) \\\n )\n\n`define SYNC_RAM_REAL(addr_name, din_name, out_name, clk_name, ce_name, we_name, addr_bits_expr, data_bits_expr, data_expt_expr) \\\n `REAL_FROM_WIDTH_EXP(out_name, data_bits_expr, data_expt_expr); \\\n `SYNC_RAM_INTO_REAL(addr_name, din_name, out_name, clk_name, ce_name, we_name, addr_bits_expr, data_bits_expr, data_expt_expr)\n\n// synchronous RAM\n\n// interface functions\n\n// range is not included as a parameter since there is no\n// way to read it out of the interface; as a result the \n// maximum range for the width and exponent must be used\n\n`define INTF_DECL_REAL(name) \\\n parameter integer `WIDTH_PARAM_REAL(name)=0, \\\n parameter integer `EXPONENT_PARAM_REAL(name)=0\n\n`define REAL_INTF_PARAMS(name, width_expr, exponent_expr) \\\n .`WIDTH_PARAM_REAL(name)(width_expr), \\\n .`EXPONENT_PARAM_REAL(name)(exponent_expr)\n\n`define INTF_FORMAT_REAL(name) ``name``_format_signal\n\n `define INTF_MAKE_REAL(name) \\\n `DATA_TYPE_REAL(`WIDTH_PARAM_REAL(name)) name; \\\n logic [((`WIDTH_PARAM_REAL(name))+(`EXPONENT_PARAM_REAL(name))-1):(`EXPONENT_PARAM_REAL(name))] `INTF_FORMAT_REAL(name)\n \n`define INTF_WIDTH_REAL(name) ($size(`INTF_FORMAT_REAL(name)))\n\n`define INTF_EXPONENT_REAL(name) ($low(`INTF_FORMAT_REAL(name)))\n\n`define INTF_RANGE_REAL(name) (2.0**($high(`INTF_FORMAT_REAL(name))))\n\n`define INTF_PASS_REAL(port, name) \\\n .`WIDTH_PARAM_REAL(port)(`INTF_WIDTH_REAL(name)), \\\n .`EXPONENT_PARAM_REAL(port)(`INTF_EXPONENT_REAL(name)), \\\n .`RANGE_PARAM_REAL(port)(`INTF_RANGE_REAL(name))\n\n`define INTF_ALIAS_REAL(path, name) \\\n `MAKE_FORMAT_REAL(name, `INTF_RANGE_REAL(path), `INTF_WIDTH_REAL(path), `INTF_EXPONENT_REAL(path))\n\n`define INTF_INPUT_TO_REAL(path, name) \\\n `INTF_ALIAS_REAL(path, name); \\\n assign name = path\n\n`define INTF_OUTPUT_TO_REAL(path, name) \\\n `INTF_ALIAS_REAL(path, name); \\\n assign path = name\n\n// modport-related functions\n\n`define MODPORT_IN_REAL(name) \\\n input name, \\\n input `INTF_FORMAT_REAL(name)\n\n`define MODPORT_OUT_REAL(name) \\\n output name, \\\n input `INTF_FORMAT_REAL(name)\n\n// print a real number (interface version)\n\n`define INTF_TO_REAL(name) \\\n `ifdef FLOAT_REAL \\\n (name) \\\n `elsif HARD_FLOAT \\\n (`REC_FN_TO_REAL(name)) \\\n `else \\\n (`FIXED_TO_FLOAT((name), `INTF_EXPONENT_REAL(name))) \\\n `endif\n \n`define INTF_PRINT_REAL(name) \\\n $display(`\"``name``=%0f`\", `INTF_TO_REAL(name))\n\n// force a real number (interface version)\n\n`define INTF_FROM_REAL(expr, name) \\\n `ifdef FLOAT_REAL \\\n (expr) \\\n `elsif HARD_FLOAT \\\n (`REAL_TO_REC_FN(expr)) \\\n `else \\\n\t\t(`FLOAT_TO_FIXED((expr), `INTF_EXPONENT_REAL(name))) \\\n `endif\n\n`define INTF_FORCE_REAL(expr, name) \\\n name = `INTF_FROM_REAL(expr, name)\n\n// module definitions\n\nmodule assertion_real #(\n `DECL_REAL(in),\n parameter name = \"name\"\n) (\n `INPUT_REAL(in)\n);\n\n localparam real min = -(`RANGE_PARAM_REAL(in));\n localparam real max = +(`RANGE_PARAM_REAL(in));\n\n always @(in) begin\n if (!((min <= `TO_REAL(in)) && (`TO_REAL(in) <= max))) begin\n $display(\"Real number %s with value %f out of range (%f to %f).\", name, `TO_REAL(in), min, max);\n $fatal;\n end\n end\n\nendmodule\n\nmodule assign_real #(\n `DECL_REAL(in),\n `DECL_REAL(out)\n) (\n `INPUT_REAL(in),\n `OUTPUT_REAL(out)\n);\n `ifdef FLOAT_REAL\n assign out = in;\n `elsif HARD_FLOAT\n assign out = in;\n `else\n localparam integer lshift = `EXPONENT_PARAM_REAL(in) - `EXPONENT_PARAM_REAL(out);\n \n generate\n if (lshift >= 0) begin\n assign out = in <<< (+lshift);\n end else begin\n assign out = in >>> (-lshift);\n end\n endgenerate\n `endif\nendmodule\n\nmodule add_sub_real #(\n `DECL_REAL(a),\n `DECL_REAL(b),\n `DECL_REAL(c),\n\tparameter integer opcode=0\n) (\n `INPUT_REAL(a),\n `INPUT_REAL(b),\n `OUTPUT_REAL(c)\n);\n`ifndef HARD_FLOAT\n `COPY_FORMAT_REAL(c, a_aligned);\n `COPY_FORMAT_REAL(c, b_aligned);\n\n `ASSIGN_REAL(a, a_aligned);\n `ASSIGN_REAL(b, b_aligned);\n\n generate\n if (opcode == `ADD_OPCODE_REAL) begin\n assign c = a_aligned + b_aligned;\n end else if (opcode == `SUB_OPCODE_REAL) begin\n assign c = a_aligned - b_aligned;\n end else begin\n initial begin\n $display(\"ERROR: Invalid opcode.\");\n $finish;\n end\n end\n endgenerate\n`else\n logic subOp;\n assign subOp = (opcode == `SUB_OPCODE_REAL) ? 1'b1 : 1'b0;\n\n addRecFN #(\n .expWidth(`HARD_FLOAT_EXP_WIDTH),\n .sigWidth(`HARD_FLOAT_SIG_WIDTH)\n ) addRecFN_i (\n .control(`HARD_FLOAT_CONTROL),\n .subOp(subOp),\n .a(a),\n .b(b),\n .roundingMode(`HARD_FLOAT_ROUNDING),\n .out(c),\n .exceptionFlags()\n );\n`endif\nendmodule\n\nmodule negate_real #(\n `DECL_REAL(in),\n `DECL_REAL(out)\n) (\n `INPUT_REAL(in),\n `OUTPUT_REAL(out)\n);\n`ifndef HARD_FLOAT\n // align the input to the output format\n `COPY_FORMAT_REAL(out, in_aligned);\n `ASSIGN_REAL(in, in_aligned);\n\n // assign the output\n assign out = -in_aligned;\n`else\n assign out = {~in[`HARD_FLOAT_SIGN_BIT], in[((`HARD_FLOAT_SIGN_BIT)-1):0]};\n`endif\nendmodule\n\nmodule abs_real #(\n `DECL_REAL(in),\n `DECL_REAL(out)\n) (\n `INPUT_REAL(in),\n `OUTPUT_REAL(out)\n);\n`ifndef HARD_FLOAT\n // align the input to the output format\n `COPY_FORMAT_REAL(out, in_aligned);\n `ASSIGN_REAL(in, in_aligned);\n\n // assign the output\n assign out = (in_aligned > 0) ? in_aligned : -in_aligned;\n`else\n assign out = {1'b0, in[((`HARD_FLOAT_SIGN_BIT)-1):0]};\n`endif\nendmodule\n\nmodule mul_real #(\n `DECL_REAL(a),\n `DECL_REAL(b),\n `DECL_REAL(c)\n) (\n `INPUT_REAL(a),\n `INPUT_REAL(b),\n `OUTPUT_REAL(c)\n);\n`ifndef HARD_FLOAT\n // create wire to hold product result\n `MAKE_FORMAT_REAL(\n prod,\n `RANGE_PARAM_REAL(a) * `RANGE_PARAM_REAL(b),\n `WIDTH_PARAM_REAL(a) + `WIDTH_PARAM_REAL(b),\n `EXPONENT_PARAM_REAL(a) + `EXPONENT_PARAM_REAL(b)\n );\n\n // compute product\n assign prod = a * b;\n\n // assign result to output (which will left/right shift if necessary)\n `ASSIGN_REAL(prod, c);\n`else\n mulRecFN #(\n .expWidth(`HARD_FLOAT_EXP_WIDTH),\n .sigWidth(`HARD_FLOAT_SIG_WIDTH)\n ) mulRecFN_i (\n .control(`HARD_FLOAT_CONTROL),\n .a(a),\n .b(b),\n .roundingMode(`HARD_FLOAT_ROUNDING),\n .out(c),\n .exceptionFlags()\n );\n`endif\nendmodule\n\nmodule comp_real #(\n `DECL_REAL(a),\n `DECL_REAL(b),\n parameter integer opcode=0\n) (\n `INPUT_REAL(a),\n `INPUT_REAL(b),\n output wire logic c\n);\n`ifndef HARD_FLOAT\n // compute the minimum of the two exponents and align both inputs to it\n\n localparam integer min_exponent = `MIN_MATH(`EXPONENT_PARAM_REAL(a), `EXPONENT_PARAM_REAL(b));\n\n `REAL_FROM_WIDTH_EXP(a_aligned, (`WIDTH_PARAM_REAL(a))+(`EXPONENT_PARAM_REAL(a))-min_exponent, min_exponent);\n `REAL_FROM_WIDTH_EXP(b_aligned, (`WIDTH_PARAM_REAL(b))+(`EXPONENT_PARAM_REAL(b))-min_exponent, min_exponent);\n\n `ASSIGN_REAL(a, a_aligned);\n `ASSIGN_REAL(b, b_aligned);\n\n generate\n if (opcode == `GT_OPCODE_REAL) begin\n assign c = (a_aligned > b_aligned) ? 1'b1 : 1'b0;\n end else if (opcode == `GE_OPCODE_REAL) begin\n assign c = (a_aligned >= b_aligned) ? 1'b1 : 1'b0;\n end else if (opcode == `LT_OPCODE_REAL) begin\n assign c = (a_aligned < b_aligned) ? 1'b1 : 1'b0;\n end else if (opcode == `LE_OPCODE_REAL) begin\n assign c = (a_aligned <= b_aligned) ? 1'b1 : 1'b0;\n end else if (opcode == `EQ_OPCODE_REAL) begin\n assign c = (a_aligned == b_aligned) ? 1'b1 : 1'b0;\n end else if (opcode == `NE_OPCODE_REAL) begin\n assign c = (a_aligned != b_aligned) ? 1'b1 : 1'b0;\n end else begin\n initial begin\n $display(\"ERROR: Invalid opcode.\");\n $finish;\n end\n end\n endgenerate\n`else\n logic lt, eq, gt;\n\n compareRecFN #(\n .expWidth(`HARD_FLOAT_EXP_WIDTH),\n .sigWidth(`HARD_FLOAT_SIG_WIDTH)\n ) compareRecFN_i (\n .a(a),\n .b(b),\n .signaling(1'b0),\n .lt(lt),\n .eq(eq),\n .gt(gt),\n .unordered(),\n .exceptionFlags()\n );\n\n generate\n if (opcode == `GT_OPCODE_REAL) begin\n assign c = gt;\n end else if (opcode == `GE_OPCODE_REAL) begin\n assign c = gt | eq;\n end else if (opcode == `LT_OPCODE_REAL) begin\n assign c = lt;\n end else if (opcode == `LE_OPCODE_REAL) begin\n assign c = lt | eq;\n end else if (opcode == `EQ_OPCODE_REAL) begin\n assign c = eq;\n end else if (opcode == `NE_OPCODE_REAL) begin\n assign c = ~eq;\n end else begin\n initial begin\n $display(\"ERROR: Invalid opcode.\");\n $finish;\n end\n end\n endgenerate\n`endif\nendmodule\n\nmodule ite_real #(\n `DECL_REAL(true),\n `DECL_REAL(false),\n `DECL_REAL(out)\n) (\n input wire logic cond,\n `INPUT_REAL(true),\n `INPUT_REAL(false),\n `OUTPUT_REAL(out)\n);\n `COPY_FORMAT_REAL(out, true_aligned);\n `COPY_FORMAT_REAL(out, false_aligned);\n\n `ASSIGN_REAL(true, true_aligned);\n `ASSIGN_REAL(false, false_aligned);\n\n assign out = (cond == 1'b1) ? true_aligned : false_aligned;\nendmodule\n\nmodule dff_real #(\n `DECL_REAL(d),\n `DECL_REAL(q),\n\tparameter real init=0\n) (\n `INPUT_REAL(d),\n `OUTPUT_REAL(q),\n input wire logic rst,\n input wire logic clk,\n input wire logic cke\n);\n // \"var\" for memory is kept internal\n // so that all ports are \"wire\" type nets\n `COPY_FORMAT_REAL(q, q_mem);\n `ASSIGN_REAL(q_mem, q);\n\n // align input to output\n `COPY_FORMAT_REAL(q, d_aligned);\n `ASSIGN_REAL(d, d_aligned);\n \n // align initial value to output format\n `COPY_FORMAT_REAL(q, init_aligned);\n\t`ASSIGN_CONST_REAL(init, init_aligned); \n \n // main DFF logic\n always @(posedge clk) begin\n if (rst == 1'b1) begin\n q_mem <= init_aligned;\n end else if (cke == 1'b1) begin\n q_mem <= d_aligned;\n end else begin\n q_mem <= q;\n end\n end \nendmodule\n\nmodule sync_rom_real #(\n `DECL_REAL(out),\n parameter integer addr_bits=1,\n parameter integer data_bits=1,\n parameter integer data_expt=1,\n parameter file_path=\"\"\n) (\n input wire logic [(addr_bits-1):0] addr,\n `OUTPUT_REAL(out),\n input wire logic clk,\n input wire logic ce\n);\n // load the ROM\n logic signed [(data_bits-1):0] rom [0:((2**addr_bits)-1)];\n initial begin\n $readmemb(file_path, rom);\n end\n\n // read from the ROM\n logic signed [(data_bits-1):0] data;\n always @(posedge clk) begin\n if (ce) begin\n data <= rom[addr];\n end\n end\n\n // Assign to output. We have to explicitly handle FLOAT_REAL case\n // because ROM data is always stored with fixed-point formatting,\n // even when FLOAT_REAL is defined.\n `ifdef FLOAT_REAL\n assign out = `FIXED_TO_FLOAT(data, data_expt);\n `elsif HARD_FLOAT\n assign out = data;\n `else\n localparam `RANGE_PARAM_REAL(data) = 2.0**(data_bits+data_expt-1);\n localparam `WIDTH_PARAM_REAL(data) = data_bits;\n localparam `EXPONENT_PARAM_REAL(data) = data_expt;\n `ASSIGN_REAL(data, out);\n `endif\nendmodule\n\n// adapted from the example on page 119-120 here:\n// https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug901-vivado-synthesis.pdf\n\nmodule sync_ram_real #(\n `DECL_REAL(out),\n parameter integer addr_bits=1,\n parameter integer data_bits=1,\n parameter integer data_expt=1\n) (\n input wire logic [(addr_bits-1):0] addr,\n input wire logic signed [(data_bits-1):0] din,\n `OUTPUT_REAL(out),\n input wire logic clk,\n input wire logic ce,\n input wire logic we\n);\n // memory contents\n logic signed [(data_bits-1):0] ram [0:((2**addr_bits)-1)];\n\n // RAM I/O\n logic signed [(data_bits-1):0] data;\n always @(posedge clk) begin\n if (ce) begin\n if (we) begin\n ram[addr] <= din;\n end\n data <= ram[addr];\n end\n end\n\n // Assign to output. We have to explicitly handle FLOAT_REAL case\n // because ROM data is always stored with fixed-point formatting,\n // even when FLOAT_REAL is defined.\n `ifdef FLOAT_REAL\n assign out = `FIXED_TO_FLOAT(data, data_expt);\n `elsif HARD_FLOAT\n assign out = data;\n `else\n localparam `RANGE_PARAM_REAL(data) = 2.0**(data_bits+data_expt-1);\n localparam `WIDTH_PARAM_REAL(data) = data_bits;\n localparam `EXPONENT_PARAM_REAL(data) = data_expt;\n `ASSIGN_REAL(data, out);\n `endif\nendmodule\n\n// measuring the width of an integer\n\nmodule meas_uint_width #(\n parameter integer in_width=1,\n parameter integer out_width=1\n) (\n input wire [(in_width-1):0] in,\n output reg [(out_width-1):0] out\n);\n integer i;\n always @(*) begin\n if (in == 0) begin\n out = 0;\n end else begin\n for (i=0; i<in_width; i=i+1) begin\n if (in[i]) begin\n out = i + 1;\n end\n end\n end\n end\nendmodule\n\n// Compressing an integer\n// TODO: handle \"inf\" case for HARD_FLOAT\n\nmodule compress_uint #(\n parameter integer in_width=1,\n `DECL_REAL(out)\n) (\n input wire [(in_width-1):0] in,\n `OUTPUT_REAL(out)\n);\n `ifdef FLOAT_REAL\n real x, y;\n always @(in) begin\n if (in == 0.0) begin\n x = 0.0;\n y = 0.0;\n end else begin\n x = $floor($ln(1.0*in)/$ln(2.0)) + 1.0;\n y = ((1.0*in)/(2.0**(x-1.0))) - 1.0;\n end\n end\n assign out = x + y;\n `elsif HARD_FLOAT\n // make signed version of the input, as needed by INT_TO_REAL\n logic signed [in_width:0] in_signed;\n assign in_signed = {1'b0, in};\n `INT_TO_REAL(in_signed, (in_width+1), in_as_float);\n\n // extract exponent and significand (the sign is unused)\n logic sign;\n logic [(`HARD_FLOAT_EXP_WIDTH):0] exp;\n logic [((`HARD_FLOAT_SIG_WIDTH)-2):0] fract;\n assign {sign, exp, fract} = in_as_float;\n\n // represent the width as a floating-point number\n localparam integer count_width = $clog2(in_width+1);\n localparam [(`HARD_FLOAT_EXP_WIDTH):0] exp_bias =\n ((2**((`HARD_FLOAT_EXP_WIDTH)-1))+1) + // recoding bias\n ((2**((`HARD_FLOAT_EXP_WIDTH)-1))-1); // exponent bias\n logic signed [count_width:0] count_signed;\n assign count_signed = exp - exp_bias;\n `INT_TO_REAL(count_signed, (count_width+1), exp_as_float);\n\n // convert the fractional part to a floating-point number\n", "right_context": " assign fract_as_float = {1'b0, exp_bias, fract};\n\n // add the two together\n `ADD_REAL(exp_as_float, fract_as_float, result);\n\n // special handling for zero\n assign out = (in==0) ? 0 : result;\n `else\n // numbers of bits needed to represent the input width\n localparam integer count_width = $clog2(in_width+1);\n\n // number of bits needed to represent the output\n localparam integer data_width = 1 + count_width + (in_width-1);\n\n // measure the input width, which can be 0 through in_width, inclusive\n `MEAS_UINT_WIDTH(in, in_width, count, count_width);\n\n // re-align input\n logic [(in_width-2):0] aligned;\n assign aligned = in << (in_width-count);\n\n // format signals into a fixed-point signal\n `MAKE_FORMAT_REAL(data, (in_width+1), data_width, (-in_width+1));\n assign data = {1'b0, count, aligned};\n\n // assign output\n `ASSIGN_REAL(data, out);\n `endif\nendmodule\n\n`endif // `ifndef __SVREAL_SV__\n", "groundtruth": " `MAKE_REAL(fract_as_float, in_width+1);\n", "crossfile_context": ""}
{"task_id": "svreal", "path": "svreal/tests/test_arith.sv", "left_context": "`timescale 1ns / 1ps\n\n`include \"svreal.sv\"\n\nmodule test_arith(\n // generic inputs\n input real a_i,\n input real b_i,\n // operators\n output real min_o,\n output real max_o,\n output real add_o,\n output real sub_o,\n", "right_context": " output real neg_o,\n output real abs_o\n);\n // create a_i input\n `REAL_FROM_WIDTH_EXP(a_int, 16, -8);\n assign `FORCE_REAL(a_i, a_int);\n\n // create b_i input\n `REAL_FROM_WIDTH_EXP(b_int, 17, -9);\n assign `FORCE_REAL(b_i, b_int);\n\n // min\n `MIN_REAL_GENERIC(a_int, b_int, min_int, 20);\n assign min_o = `TO_REAL(min_int);\n\n // max\n `MAX_REAL_GENERIC(a_int, b_int, max_int, 21);\n assign max_o = `TO_REAL(max_int);\n\n // add\n `ADD_REAL_GENERIC(a_int, b_int, add_int, 22);\n assign add_o = `TO_REAL(add_int);\n\n // sub\n `SUB_REAL_GENERIC(a_int, b_int, sub_int, 23);\n assign sub_o = `TO_REAL(sub_int);\n\n // mul\n `MUL_REAL_GENERIC(a_int, b_int, mul_int, 24);\n assign mul_o = `TO_REAL(mul_int);\n\n // negate\n `NEGATE_REAL(a_int, neg_int);\n assign neg_o = `TO_REAL(neg_int);\n\n // absolute value\n `ABS_REAL(a_int, abs_int);\n assign abs_o = `TO_REAL(abs_int);\nendmodule", "groundtruth": " output real mul_o,\n", "crossfile_context": ""}
{"task_id": "svreal", "path": "svreal/tests/test_clog2.sv", "left_context": "`timescale 1ns/1ps\n\n`include \"svreal.sv\"\n\nmodule test_clog2(\n input real in_,\n", "right_context": "", "groundtruth": " output signed [31:0] out\n);\n assign out = clog2_math(in_);\nendmodule\n", "crossfile_context": ""}
{"task_id": "svreal", "path": "svreal/tests/test_comp.sv", "left_context": "`timescale 1ns / 1ps\n\n`include \"svreal.sv\"\n\nmodule test_comp(\n // generic inputs\n input real a_i,\n input real b_i,\n // comparisons\n output lt_o,\n output le_o,\n output gt_o,\n output ge_o,\n output eq_o,\n output ne_o\n);\n // create a_i input\n `REAL_FROM_WIDTH_EXP(a_int, 16, -8);\n assign `FORCE_REAL(a_i, a_int);\n\n // create b_i input\n `REAL_FROM_WIDTH_EXP(b_int, 17, -9);\n assign `FORCE_REAL(b_i, b_int);\n\n // comparisons\n `LT_INTO_REAL(a_int, b_int, lt_o);\n `LE_INTO_REAL(a_int, b_int, le_o);\n `GT_INTO_REAL(a_int, b_int, gt_o);\n `GE_INTO_REAL(a_int, b_int, ge_o);\n", "right_context": "", "groundtruth": " `EQ_INTO_REAL(a_int, b_int, eq_o);\n `NE_INTO_REAL(a_int, b_int, ne_o);\nendmodule", "crossfile_context": ""}
{"task_id": "svreal", "path": "svreal/tests/test_compress_uint.sv", "left_context": "`timescale 1ns/1ps\n\n`include \"svreal.sv\"\n\n`ifndef WIDTH\n `define WIDTH 8\n`endif\n\nmodule test_compress_uint (\n input [((`WIDTH)-1):0] in_,\n output real out\n", "right_context": "", "groundtruth": ");\n `COMPRESS_UINT(in_, (`WIDTH), val);\n assign out = `TO_REAL(val);\nendmodule\n", "crossfile_context": ""}
{"task_id": "svreal", "path": "svreal/tests/test_const.sv", "left_context": "`timescale 1ns / 1ps\n\n`include \"svreal.sv\"\n\nmodule test_const #(\n parameter real a_const=0.0,\n parameter real b_const=0.0,\n parameter real c_const=0.0\n) (\n output real a_o,\n input real b_i,\n output real b_o,\n input real c_i,\n output real c_o\n", "right_context": " assign b_o = `TO_REAL(b_o_int);\n\n // produce c_o output\n `MAKE_REAL(c_i_int, 10);\n assign `FORCE_REAL(c_i, c_i_int);\n `ADD_CONST_REAL(c_const, c_i_int, c_o_int);\n assign c_o = `TO_REAL(c_o_int);\nendmodule\n", "groundtruth": ");\n // produce a_o output\n `MAKE_CONST_REAL(a_const, a_const_int);\n assign a_o = `TO_REAL(a_const_int);\n\n", "crossfile_context": ""}
{"task_id": "svreal", "path": "svreal/tests/test_conv.sv", "left_context": "`timescale 1ns / 1ps\n\n`include \"svreal.sv\"\n\nmodule test_conv(\n // real to integer\n input real r2i_i,\n output signed [7:0] r2i_o,\n // integer to real\n input signed [7:0] i2r_i,\n output real i2r_o\n);\n // create r2i_i input\n `REAL_FROM_WIDTH_EXP(r2i_int, 16, -8);\n", "right_context": " `REAL_INTO_INT(r2i_int, 8, r2i_o);\n\n // integer to real\n `INT_TO_REAL(i2r_i, 8, i2r_int);\n assign i2r_o = `TO_REAL(i2r_int);\nendmodule", "groundtruth": " assign `FORCE_REAL(r2i_i, r2i_int);\n\n", "crossfile_context": ""}
{"task_id": "svreal", "path": "svreal/tests/test_dff.sv", "left_context": "`timescale 1ns / 1ps\n\n`include \"svreal.sv\"\n\n", "right_context": " input rst_i,\n input clk_i,\n input cke_i\n);\n // create data input\n `REAL_FROM_WIDTH_EXP(d_int, 16, -8);\n assign `FORCE_REAL(d_i, d_int);\n\n // create data output\n `REAL_FROM_WIDTH_EXP(q_int, 17, -9);\n assign q_o = `TO_REAL(q_int);\n\n // instantiate DFF\n `DFF_INTO_REAL(d_int, q_int, rst_i, clk_i, cke_i, init);\nendmodule\n", "groundtruth": "module test_dff #(\n parameter real init=0.0\n) (\n", "crossfile_context": ""}
{"task_id": "svreal", "path": "svreal/tests/test_float.sv", "left_context": "`timescale 1ns/1ps\n\n`include \"svreal.sv\"\n\nmodule test_float;\n real inf, nan; // will be assigned during test\n\n `MAKE_REAL(x, 10); // range is arbitrary for floating point...\n\n real out;\n assign out = `TO_REAL(x);\n\n task check_equals(input real a, input real b);\n if (a == b) begin\n $display(\"%e == %e\", a, b);\n end else begin\n $error(\"%e != %e\", a, b);\n end\n endtask\n\n task check_tol(input real meas, input real expct, input real tol);\n if (((expct-tol)<meas) && (meas<(expct+tol))) begin\n $display(\"%e is close to %e\", meas, expct);\n end else begin\n $error(\"%e is not close to %e\", meas, expct);\n end\n endtask\n\n function isnan(input real a);\n logic [63:0] data;\n data = $realtobits(a);\n", "right_context": " return 1;\n end else begin\n return 0;\n end\n endfunction\n\n initial begin\n // inf and nan need to be assigned like this because\n // Xcelium will error out if we just did inf = 1e1000\n inf = $bitstoreal(64'h7FF0000000000000);\n nan = $bitstoreal(64'h7FF8000000000000);\n\n `FORCE_REAL(0.0, x);\n #1;\n check_equals(out, 0.0);\n #1;\n\n `FORCE_REAL(1.23, x);\n #1;\n check_tol(out, 1.23, 1e-5);\n #1;\n\n `FORCE_REAL(-4.56, x);\n #1;\n check_tol(out, -4.56, 1e-5);\n #1;\n\n `FORCE_REAL(1e15, x);\n #1;\n check_tol(out, 1e15, 1e9);\n #1;\n\n `FORCE_REAL(1e-15, x);\n #1;\n check_tol(out, 1e-15, 1e-20);\n #1;\n\n `FORCE_REAL(1e-40, x); // double can represent this but not the recoded format\n #1;\n check_equals(out, 0.0);\n #1;\n\n `FORCE_REAL(1e-100, x); // double can represent this but not the recoded format\n #1;\n check_equals(out, 0.0);\n #1;\n\n `FORCE_REAL(1e-315, x); // subnormal for double; too small for recoded format\n #1;\n check_equals(out, 0.0);\n #1;\n\n `FORCE_REAL(1e-400, x); // too small for double and recoded format\n #1;\n check_equals(out, 0.0);\n #1;\n\n `FORCE_REAL(inf, x);\n #1;\n check_equals(out, inf);\n #1;\n\n `FORCE_REAL(-inf, x);\n #1;\n check_equals(out, -inf);\n #1;\n\n `FORCE_REAL(nan, x);\n #1;\n if (isnan(out)) begin\n $display(\"out is nan\");\n end else begin\n $error(\"out is not nan\");\n end\n #1;\n\n `FORCE_REAL(1e100, x);\n #1;\n check_equals(out, inf);\n #1;\n\n `FORCE_REAL(-1e100, x);\n #1;\n check_equals(out, -inf);\n #1;\n\n $finish;\n end\nendmodule\n", "groundtruth": " if ((data[62:52] == 11'h7ff) && (data[51:0] != 0)) begin\n", "crossfile_context": ""}
{"task_id": "svreal", "path": "svreal/tests/test_hier.sv", "left_context": "`timescale 1ns / 1ps\n\n`include \"svreal.sv\"\n\nmodule level3 #(\n `DECL_REAL(a),\n `DECL_REAL(b),\n `DECL_REAL(c)\n) (\n `INPUT_REAL(a),\n `INPUT_REAL(b),\n `OUTPUT_REAL(c)\n);\n `MUL_INTO_REAL(a, b, c);\nendmodule\n\nmodule level2 #(\n `DECL_REAL(a),\n `DECL_REAL(b),\n `DECL_REAL(c)\n) (\n `INPUT_REAL(a),\n `INPUT_REAL(b),\n `OUTPUT_REAL(c)\n);\n level3 #(\n `PASS_REAL(a, a),\n", "right_context": " `PASS_REAL(c, c)\n ) inner (\n .a(a),\n .b(b),\n .c(c)\n );\nendmodule\n\nmodule level1 #(\n `DECL_REAL(a),\n `DECL_REAL(b),\n `DECL_REAL(c)\n) (\n `INPUT_REAL(a),\n `INPUT_REAL(b),\n `OUTPUT_REAL(c)\n);\n level2 #(\n `PASS_REAL(a, a),\n `PASS_REAL(b, b),\n `PASS_REAL(c, c)\n ) inner (\n .a(a),\n .b(b),\n .c(c)\n );\nendmodule\n\nmodule test_hier(\n input real a_i,\n input real b_i,\n output real c_o\n);\n // create a_int signal\n `REAL_FROM_WIDTH_EXP(a_int, 16, -8);\n assign `FORCE_REAL(a_i, a_int);\n\n // create b_int signal\n `REAL_FROM_WIDTH_EXP(b_int, 17, -9);\n assign `FORCE_REAL(b_i, b_int);\n\n // create c_int signal\n `REAL_FROM_WIDTH_EXP(c_int, 18, -10);\n assign c_o = `TO_REAL(c_int);\n\n level1 #(\n `PASS_REAL(a, a_int),\n `PASS_REAL(b, b_int),\n `PASS_REAL(c, c_int)\n ) inner (\n .a(a_int),\n .b(b_int),\n .c(c_int)\n );\nendmodule\n", "groundtruth": " `PASS_REAL(b, b),\n", "crossfile_context": ""}
{"task_id": "svreal", "path": "svreal/tests/test_iface.sv", "left_context": "`timescale 1ns/1ps\n\n`include \"svreal.sv\"\n\nmodule test_iface(\n input real a_i,\n input real b_i,\n output real c_o\n);\n // create a_int interface\n svreal #(`REAL_INTF_PARAMS(value, 16, -8)) a_int ();\n assign `INTF_FORCE_REAL(a_i, a_int.value);\n\n // create b_int interface\n svreal #(`REAL_INTF_PARAMS(value, 17, -9)) b_int ();\n assign `INTF_FORCE_REAL(b_i, b_int.value);\n", "right_context": " level1 inner (\n .a(a_int),\n .b(b_int),\n .c(c_int)\n );\nendmodule\n", "groundtruth": "\n // create c_int interface\n svreal #(`REAL_INTF_PARAMS(value, 18, -10)) c_int ();\n", "crossfile_context": ""}
{"task_id": "svreal", "path": "svreal/tests/test_iface_core.sv", "left_context": "`timescale 1ns/1ps\n\n`include \"svreal.sv\"\n\ninterface svreal #(\n `INTF_DECL_REAL(value)\n);\n `INTF_MAKE_REAL(value);\n modport in(`MODPORT_IN_REAL(value));\n modport out(`MODPORT_OUT_REAL(value));\nendinterface\n\nmodule level4 #(\n `DECL_REAL(a),\n `DECL_REAL(b),\n `DECL_REAL(c)\n) (\n `INPUT_REAL(a),\n `INPUT_REAL(b),\n `OUTPUT_REAL(c)\n);\n `MUL_INTO_REAL(a, b, c);\nendmodule\n\nmodule level3 (svreal.in a, svreal.in b, svreal.out c);\n generate\n `ifndef INTF_USE_LOCAL\n level4 #(\n `INTF_PASS_REAL(a, a.value),\n `INTF_PASS_REAL(b, b.value),\n `INTF_PASS_REAL(c, c.value)\n ) inner (\n .a(a.value),\n .b(b.value),\n .c(c.value)\n );\n `else\n `INTF_INPUT_TO_REAL(a.value, a_value);\n `INTF_INPUT_TO_REAL(b.value, b_value);\n `INTF_OUTPUT_TO_REAL(c.value, c_value);\n level4 #(\n `PASS_REAL(a, a_value),\n `PASS_REAL(b, b_value),\n `PASS_REAL(c, c_value)\n ) inner (\n .a(a_value),\n .b(b_value),\n .c(c_value)\n );\n `endif\n endgenerate\nendmodule\n\nmodule level2 (svreal.in a, svreal.in b, svreal.out c);\n level3 inner(.a(a), .b(b), .c(c));\nendmodule\n\n", "right_context": "", "groundtruth": "module level1 (svreal.in a, svreal.in b, svreal.out c);\n level2 inner(.a(a), .b(b), .c(c));\nendmodule\n", "crossfile_context": ""}
{"task_id": "svreal", "path": "svreal/tests/test_iface_synth.sv", "left_context": "`timescale 1ns/1ps\n\n`include \"svreal.sv\"\n\nmodule test_iface_synth(\n input logic signed [15:0] a_value,\n input logic signed [16:0] b_value,\n output logic signed [17:0] c_value\n);\n svreal #(`REAL_INTF_PARAMS(value, $size(a_value), -8)) a ();\n svreal #(`REAL_INTF_PARAMS(value, $size(b_value), -9)) b ();\n svreal #(`REAL_INTF_PARAMS(value, $size(c_value), -10)) c ();\n", "right_context": " .b(b),\n .c(c)\n );\nendmodule\n", "groundtruth": "\n assign a.value = a_value;\n assign b.value = b_value;\n assign c_value = c.value;\n", "crossfile_context": ""}
{"task_id": "svreal", "path": "svreal/tests/test_ite.sv", "left_context": "`timescale 1ns / 1ps\n\n`include \"svreal.sv\"\n\nmodule test_ite(\n // generic inputs\n input real a_i,\n", "right_context": " // create a_i input\n `REAL_FROM_WIDTH_EXP(a_int, 16, -8);\n assign `FORCE_REAL(a_i, a_int);\n\n // create b_i input\n `REAL_FROM_WIDTH_EXP(b_int, 17, -9);\n assign `FORCE_REAL(b_i, b_int);\n\n // mux\n `ITE_REAL_GENERIC(cond_i, a_int, b_int, ite_int, 25);\n assign ite_o = `TO_REAL(ite_int);\nendmodule", "groundtruth": " input real b_i,\n // if-then-else\n input cond_i,\n", "crossfile_context": ""}
{"task_id": "svreal", "path": "svreal/tests/test_meas_width.sv", "left_context": "`timescale 1ns/1ps\n\n`include \"svreal.sv\"\n\nmodule test_meas_width (\n", "right_context": "", "groundtruth": " input [7:0] in_,\n output [7:0] out\n);\n `MEAS_UINT_WIDTH_INTO(in_, 8, out, 8);\n", "crossfile_context": ""}
{"task_id": "svreal", "path": "svreal/tests/test_sync_ram.sv", "left_context": "`timescale 1ns / 1ps\n\n`include \"svreal.sv\"\n\nmodule test_sync_ram (\n input [1:0] addr,\n input [((`WIDTH)-1):0] din,\n output real out,\n", "right_context": " input ce,\n input we\n);\n // instantiate the RAM\n `SYNC_RAM_REAL(addr, din, out_int, clk, ce, we, 2, 18, -12);\n\n // wire up the RAM output\n assign out = `TO_REAL(out_int);\nendmodule\n", "groundtruth": " input clk,\n", "crossfile_context": ""}
{"task_id": "svreal", "path": "svreal/tests/test_sync_rom.sv", "left_context": "`timescale 1ns / 1ps\n\n`include \"svreal.sv\"\n\n", "right_context": " assign out = `TO_REAL(out_int);\nendmodule\n", "groundtruth": "module test_sync_rom (\n input [1:0] addr,\n output real out,\n input clk,\n", "crossfile_context": ""}
{"task_id": "svreal", "path": "svreal/tests/test_synth.sv", "left_context": "`timescale 1ns / 1ps\n\n`include \"svreal.sv\"\n\n`define A_WIDTH 16\n`define B_WIDTH 17\n`define I2R_WIDTH 8\n`define R2I_WIDTH 8\n\nmodule test_synth (\n // real-number inputs\n", "right_context": " output wire logic signed [21:0] add_ext,\n output wire logic signed [22:0] sub_ext,\n output wire logic signed [23:0] mul_ext,\n output wire logic signed [24:0] mux_ext,\n // conversion I/O\n input wire logic signed [`I2R_WIDTH-1:0] i2r_i_ext,\n output wire logic signed [`I2R_WIDTH-1:0] i2r_o_ext,\n output wire logic signed [`R2I_WIDTH-1:0] r2i_o_ext,\n // comparison I/O\n output wire logic lt_ext,\n output wire logic le_ext,\n output wire logic gt_ext,\n output wire logic ge_ext,\n // compression I/O\n input wire logic [31:0] compress_i_ext,\n output wire logic [((`LONG_WIDTH_REAL)-1):0] compress_o_ext,\n // control I/O\n input wire logic sel_ext,\n input wire logic rst_ext,\n input wire logic clk_ext,\n input wire logic ce_ext\n);\n // create signals\n `REAL_FROM_WIDTH_EXP(a, $size(a_ext), -8);\n `REAL_FROM_WIDTH_EXP(b, $size(b_ext), -9);\n assign a = a_ext;\n assign b = b_ext;\n\n // min\n `MIN_REAL_GENERIC(a, b, min_o, $size(min_ext));\n assign min_ext = min_o;\n\n // max\n `MAX_REAL_GENERIC(a, b, max_o, $size(max_ext));\n assign max_ext = max_o;\n\n // add\n `ADD_REAL_GENERIC(a, b, add_o, $size(add_ext));\n assign add_ext = add_o;\n\n // sub\n `SUB_REAL_GENERIC(a, b, sub_o, $size(sub_ext));\n assign sub_ext = sub_o;\n\n // mul\n `MUL_REAL_GENERIC(a, b, mul_o, $size(mul_ext));\n assign mul_ext = mul_o;\n\n // mux\n `ITE_REAL_GENERIC(sel_ext, a, b, mux_o, $size(mux_ext));\n assign mux_ext = mux_o;\n\n // negation\n `NEGATE_REAL(a, neg_o);\n assign neg_ext = neg_o;\n\n // absolute value\n `ABS_REAL(a, abs_o);\n assign abs_ext = abs_o;\n\n // integer to real\n `INT_TO_REAL(i2r_i_ext, $size(i2r_i_ext), i2r_o_int);\n assign i2r_o_ext = i2r_o_int;\n\n // real to integer\n `REAL_TO_INT(a, $size(r2i_o_ext), r2i_o_int);\n assign r2i_o_ext = r2i_o_int;\n\n // dff\n `DFF_REAL(a, dff_o, rst_ext, clk_ext, ce_ext, 1.23);\n assign dff_ext = dff_o;\n\n // comparisons\n `LT_INTO_REAL(a, b, lt_ext);\n `LE_INTO_REAL(a, b, le_ext);\n `GT_INTO_REAL(a, b, gt_ext);\n `GE_INTO_REAL(a, b, ge_ext);\n\n // uint compression\n `COMPRESS_UINT(compress_i_ext, $size(compress_i_ext), compress_o);\n assign compress_o_ext = compress_o;\nendmodule\n", "groundtruth": " input wire logic signed [`A_WIDTH-1:0] a_ext,\n input wire logic signed [`B_WIDTH-1:0] b_ext,\n // unary op I/O\n output wire logic signed [`A_WIDTH-1:0] neg_ext,\n output wire logic signed [`A_WIDTH-1:0] abs_ext,\n", "crossfile_context": ""}
{"task_id": "ava-core", "path": "ava-core/rtl/accelerator_pkg.sv", "left_context": "//\n// SPDX-License-Identifier: CERN-OHL-S-2.0+\n//\n// Copyright (C) 2020-21 Embecosm Limited <www.embecosm.com>\n// Contributed by:\n// Matthew Johns <mrj1g17@soton.ac.uk>\n// Byron Theobald <bt4g16@soton.ac.uk>\n//\n// This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY,\n// INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR\n// A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable\n// conditions.\n// Source location: https://github.com/AI-Vector-Accelerator\n//\n\npackage accelerator_pkg;\n\n// Arithmetic operations inside PEs\ntypedef enum logic [3:0] {\n PE_ARITH_ADD,\n PE_ARITH_SUB,\n PE_ARITH_LSHIFT, // left-shift\n PE_ARITH_MUL,\n PE_ARITH_MULADD, // multiply-add\n PE_ARITH_XOR,\n PE_ARITH_RSHIFT_LOG, // logical right-shift\n PE_ARITH_RSHIFT_AR, // arithmetic right-shift\n PE_ARITH_OR,\n PE_ARITH_AND\n} pe_arith_op_t;\n\n// PE output mode\n// PE_OP_MODE_RESULT: pass through arithmetic result\n// PE_OP_MODE_PASS_MAX: pass larger of operands A and B\n// PE_OP_MODE_PASS_MIN: pass smaller of operands A and B\n", "right_context": " PE_OP_MODE_RESULT,\n PE_OP_MODE_PASS_MAX,\n PE_OP_MODE_PASS_MIN\n} pe_output_mode_t;\n\n// PE saturation mode\n// PE_SAT_NONE: not saturation of output\n// PE_SAT: saturate to element width, keep decimal in same position\n// PE_SAT_UPPER: saturate to element width, keeping upper half of result only\ntypedef enum logic [1:0] {\n PE_SAT_NONE,\n PE_SAT,\n PE_SAT_UPPER\n} pe_saturate_mode_t;\n\n// PE operand selection - select B operand for PE\n// PE_OPERAND_VS1: vector from vs1 vector register\n// PE_OPERAND_SCALAR: scalar passed from x-register\n// PE_OPERAND_IMMEDIATE: scalar immediate passed from instruction\n// PE_OPERAND_RIPPLE: configure PEs in ripple mode for reductions\ntypedef enum logic [1:0] {\n PE_OPERAND_VS1,\n PE_OPERAND_SCALAR,\n PE_OPERAND_IMMEDIATE,\n PE_OPERAND_RIPPLE\n} pe_operand_t;\n\n// Source of data written back to vd in vector registers\n// VREG_WB_SRC_ARITH: data output from arithmetic stage\n// VREG_WB_SRC_MEMORY: data retrieved from RAM\n// VREG_WB_SRC_SCALAR: scalar value taken from scalar replicator\ntypedef enum logic [1:0] {\n VREG_WB_SRC_ARITH,\n VREG_WB_SRC_MEMORY,\n VREG_WB_SRC_SCALAR\n} vreg_wb_src_t;\n\n// Source of address of selected vector register\n// VS3_ADDR_SRC_DECODE: address from decoder\n// VS3_ADDR_SRC_VLSU: address from vlsu / address unit\ntypedef enum logic {\n VS3_ADDR_SRC_DECODE,\n VS3_ADDR_SRC_VLSU\n} vreg_addr_src_t;\n\n// Source of data returned to CPU by via apu_result\n// APU_RESULT_SRC_VL: return VL value. For vsetvli\n// APU_RESULT_SRC_VS2_0: return first element of vs2. For vmv.x.s\ntypedef enum logic {\n APU_RESULT_SRC_VL,\n APU_RESULT_SRC_VS2_0\n} apu_result_src_t;\n\n// Major opcodes converted into 2 bits for the vector accelerator\n// parameter V_MAJOR_LOAD_FP = 2'b00;\n// parameter V_MAJOR_STORE_FP = 2'b01;\n// parameter V_MAJOR_OP_V = 2'b10;\n// parameter V_MAJOR_CUSTOM = 2'b11;\nparameter V_MAJOR_LOAD_FP = 7'b0000111;\nparameter V_MAJOR_STORE_FP = 7'b0100111;\nparameter V_MAJOR_OP_V = 7'b1010111;\n// parameter V_MAJOR_CUSTOM = 7'b;\n\n// funct3 bit fields from vector instructions (describe operand/source types)\nparameter V_OPIVV = 3'b000;\nparameter V_OPFVV = 3'b001;\nparameter V_OPMVV = 3'b010;\nparameter V_OPIVI = 3'b011;\nparameter V_OPIVX = 3'b100;\nparameter V_OPFVF = 3'b101;\nparameter V_OPMVX = 3'b110;\nparameter V_OPCFG = 3'b111;\n\n\nendpackage\n", "groundtruth": "typedef enum logic [1:0] {\n", "crossfile_context": ""}
{"task_id": "ava-core", "path": "ava-core/rtl/accelerator_top.sv", "left_context": "//\n// SPDX-License-Identifier: CERN-OHL-S-2.0+\n//\n// Copyright (C) 2020-21 Embecosm Limited <www.embecosm.com>\n// Contributed by:\n// Matthew Johns <mrj1g17@soton.ac.uk>\n// Byron Theobald <bt4g16@soton.ac.uk>\n//\n// This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY,\n// INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR\n// A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable\n// conditions.\n// Source location: https://github.com/AI-Vector-Accelerator\n//\n\n// `include \"defs.sv\"\nimport accelerator_pkg::*;\n\nmodule accelerator_top (\n output logic [31:0] apu_result,\n output logic [4:0] apu_flags_o,\n output logic apu_gnt,\n output logic apu_rvalid,\n input wire clk,\n input wire n_reset,\n input wire apu_req,\n input wire [2:0][31:0] apu_operands_i,\n input wire [5:0] apu_op,\n input wire [14:0] apu_flags_i,\n output wire data_req_o,\n input wire data_gnt_i,\n input wire data_rvalid_i,\n output wire data_we_o,\n output wire [3:0] data_be_o,\n output wire [31:0] data_addr_o,\n output wire [31:0] data_wdata_o,\n input wire [31:0] data_rdata_i,\n output wire core_halt_o\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// OUTPUT VARIABLE DECLARATIONS\n////////////////////////////////////////////////////////////////////////////////\n\n// CSR OUTPUTS\nwire [4:0] vl;\nwire [1:0] vsew;\nwire [1:0] vlmul;\n\n// DECODER OUTPUTS\nwire [31:0] scalar_operand1;\nwire [31:0] scalar_operand2;\nwire [10:0] immediate_operand;\nwire [4:0] vs1_addr;\nwire [4:0] vs2_addr;\nlogic [4:0] vd_addr;\nwire csr_write;\nwire preserve_vl;\nwire set_vl_max;\nwire [1:0] elements_to_write;\nwire [1:0] cycle_count;\nwire vec_reg_write;\nvreg_wb_src_t vd_data_src;\nvreg_addr_src_t vs3_addr_src;\npe_arith_op_t pe_op;\npe_saturate_mode_t saturate_mode;\npe_output_mode_t output_mode;\npe_operand_t operand_select;\nwire [1:0] pe_mul_us;\nwire [1:0] widening;\napu_result_src_t apu_result_select;\nwire unsigned_immediate;\nwire wide_vs1;\n\n// VLSU OUTPUTS\nwire [127:0] vlsu_wdata;\nlogic vec_reg_write_lsu;\nlogic vlsu_done;\nlogic [4:0] vl_next_comb;\n\nlogic vlsu_en;\nlogic vlsu_load;\nlogic vlsu_store;\nlogic vlsu_strided;\nlogic vlsu_ready;\n\n// VECTOR REGISTERS OUTPUTS\nwire [127:0] vs1_data;\nwire [127:0] vs2_data;\nwire [127:0] vs3_data;\n\n// ARITHMETIC STAGE OUTPUTS\nwire [127:0] arith_output;\nwire [127:0] replicated_scalar;\n\n////////////////////////////////////////////////////////////////////////////////\n// MODULE INSTANTIATION\n////////////////////////////////////////////////////////////////////////////////\n\nwire [31:0] apu_operands [2:0];\nassign apu_operands[0] = apu_operands_i[0];\nassign apu_operands[1] = apu_operands_i[1];\nassign apu_operands[2] = apu_operands_i[2];\n\n////////////////////////////////////////\n// CSRs\nvector_csrs vcsrs0 (\n .vl(vl),\n .vsew(vsew),\n .vlmul(vlmul),\n .vl_next_comb(vl_next_comb),\n .clk(clk),\n .n_reset(n_reset),\n .avl_in(scalar_operand1),\n .vtype_in(immediate_operand[4:0]),\n .write(csr_write),\n .saturate_flag(1'b0),\n .preserve_vl(preserve_vl),\n .set_vl_max(set_vl_max)\n);\n\n////////////////////////////////////////\n// DECODER\nvector_decoder vdec0 (\n .apu_rvalid(apu_rvalid),\n .apu_gnt(apu_gnt),\n .scalar_operand1(scalar_operand1),\n .scalar_operand2(scalar_operand2),\n .immediate_operand(immediate_operand),\n .vs1_addr(vs1_addr),\n .vs2_addr(vs2_addr),\n .vd_addr(vd_addr),\n .csr_write(csr_write),\n .preserve_vl(preserve_vl),\n .set_vl_max(set_vl_max),\n .elements_to_write(elements_to_write),\n .cycle_count(cycle_count),\n .vec_reg_write(vec_reg_write),\n .vd_data_src(vd_data_src),\n .vs3_addr_src(vs3_addr_src),\n .pe_op(pe_op),\n .saturate_mode(saturate_mode),\n .output_mode(output_mode),\n .operand_select(operand_select),\n .pe_mul_us(pe_mul_us),\n .widening(widening),\n .apu_result_select(apu_result_select),\n .unsigned_immediate(unsigned_immediate),\n .wide_vs1(wide_vs1),\n .clk(clk),\n .n_reset(n_reset),\n .apu_req(apu_req),\n .apu_operands(apu_operands),\n .apu_op(apu_op),\n .apu_flags_i(apu_flags_i),\n .vl(vl),\n .vsew(vsew),\n .vlsu_en_o(vlsu_en),\n .vlsu_load_o(vlsu_load),\n .vlsu_store_o(vlsu_store),\n .vlsu_strided_o(vlsu_strided),\n .vlsu_ready_i(vlsu_ready),\n .vlsu_done_i(vlsu_done),\n .core_halt_o(core_halt_o)\n);\n\n////////////////////////////////////////\n// VECTOR REGISTERS\nlogic [127:0] vd_data;\nlogic [4:0] vs3_addr, vs3_addr_vlsu;\nalways_comb begin\n case (vd_data_src)\n VREG_WB_SRC_MEMORY:\n", "right_context": " case (vs3_addr_src)\n VS3_ADDR_SRC_DECODE:\n vs3_addr = vd_addr;\n VS3_ADDR_SRC_VLSU:\n vs3_addr = vs3_addr_vlsu;\n default:\n vs3_addr = '0;\n endcase\nend\n\n\nvector_registers vreg0 (\n .vs1_data(vs1_data),\n .vs2_data(vs2_data),\n .vs3_data(vs3_data),\n .vd_data(vd_data),\n .vs1_addr(vs1_addr),\n .vs2_addr(vs2_addr),\n .vd_addr(vs3_addr),\n .vsew(vsew),\n .vlmul(vlmul),\n .elements_to_write(elements_to_write),\n .clk(clk),\n .n_reset(n_reset),\n .write(vec_reg_write | vec_reg_write_lsu ),\n .widening_op(widening[0]),\n .wide_vs1(wide_vs1),\n .load_operation(vlsu_load)\n);\n\n////////////////////////////////////////\n// PEs CONTAINED IN ARITHMETIC STAGE WRAPPER\narith_stage arith_stage0 (\n .arith_output(arith_output),\n .replicated_scalar(replicated_scalar),\n .clk(clk),\n .n_reset(n_reset),\n .vs1_data(vs1_data),\n .vs2_data(vs2_data),\n .vs3_data(vs3_data),\n .scalar_operand(scalar_operand1),\n .imm_operand(immediate_operand[4:0]),\n .elements_to_write(elements_to_write),\n .cycle_count(cycle_count),\n .op(pe_op),\n .saturate_mode(saturate_mode),\n .output_mode(output_mode),\n .operand_select(operand_select),\n .widening(widening),\n .mul_us(pe_mul_us),\n .unsigned_immediate(unsigned_immediate),\n .wide_vs1(wide_vs1),\n .vl(vl),\n .vsew(vsew)\n);\n\n////////////////////////////////////////\n// VLSU\nvector_lsu vlsu0 (\n .clk(clk),\n .n_reset(n_reset),\n\n .vl_i(vl),\n .vsew_i(vsew),\n .vlmul_i(vlmul),\n\n .vlsu_en_i(vlsu_en),\n .vlsu_load_i(vlsu_load),\n .vlsu_store_i(vlsu_store),\n .vlsu_strided_i(vlsu_strided),\n .vlsu_ready_o(vlsu_ready),\n .vlsu_done_o(vlsu_done),\n\n .data_req_o(data_req_o),\n .data_gnt_i(data_gnt_i),\n .data_rvalid_i(data_rvalid_i),\n .data_addr_o(data_addr_o),\n .data_we_o(data_we_o),\n .data_be_o(data_be_o),\n .data_rdata_i(data_rdata_i),\n .data_wdata_o(data_wdata_o),\n\n .cycle_count_i(cycle_count),\n\n .op0_data_i(scalar_operand1),\n .op1_data_i(scalar_operand2),\n\n .vs_wdata_o(vlsu_wdata),\n .vs_rdata_i(vs3_data),\n .vr_addr_i(vd_addr),\n .vs3_addr_o(vs3_addr_vlsu),\n .vr_we_o(vec_reg_write_lsu)\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// RESULT SELECTION - what value to return to CPU\n////////////////////////////////////////////////////////////////////////////////\nlogic [31:0] reg_apu_result;\nassign apu_flags_o = '0;\nassign apu_result = reg_apu_result;\n\n// Updated VL is arriving two cycles too late\nalways_comb begin\n\t reg_apu_result = '0;\n case (apu_result_select)\n APU_RESULT_SRC_VL:\n reg_apu_result = {'0, vl_next_comb};\n APU_RESULT_SRC_VS2_0:\n case (vsew)\n 2'd0: // 8b\n reg_apu_result = { {24{vs2_data[7]}}, vs2_data[7:0] };\n 2'd1: // 16b\n reg_apu_result = { {16{vs2_data[15]}}, vs2_data[15:0] };\n 2'd2:// 32b\n reg_apu_result = vs2_data[31:0];\n endcase\n endcase\nend\n\n\nendmodule\n", "groundtruth": " vd_data = vlsu_wdata;\n VREG_WB_SRC_ARITH:\n vd_data = arith_output;\n VREG_WB_SRC_SCALAR:\n vd_data = replicated_scalar;\n", "crossfile_context": ""}
{"task_id": "ava-core", "path": "ava-core/rtl/address_unit.sv", "left_context": "//\n// SPDX-License-Identifier: CERN-OHL-S-2.0+\n//\n// Copyright (C) 2020-21 Embecosm Limited <www.embecosm.com>\n// Contributed by:\n// Byron Theobald <bt4g16@soton.ac.uk>\n//\n// This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY,\n// INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR\n// A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable\n// conditions.\n// Source location: https://github.com/AI-Vector-Accelerator\n//\n\n/* verilator lint_off ALWCOMBORDER */\nmodule address_unit(\n input logic clk_i, n_rst_i,\n input logic [31:0] base_addr_i,\n input logic [31:0] stride_i,\n input logic [4:0] vl_i,\n input logic [1:0] vsew_i,\n input logic au_start_i,\n input logic au_next_i,\n output logic [3:0] au_be_o,\n output logic [6:0] au_bc_o,\n output logic [31:0] au_addr_o,\n output logic [6:0] vd_offset_o,\n output logic au_valid_o,\n output logic au_ready_o,\n output logic au_final_o);\n\n logic [1:0] ib_select; // Low 2 bits of initial address\n logic [3:0] be_gen;\n \n logic [31:0] next_el_pre, next_el_addr;\n logic [31:0] cycle_addr;\n logic [6:0] cycle_bytes;\n\n typedef enum {RESET, FIRST, CYCLE, WAIT, FINAL} be_state;\n be_state current_state, next_state;\n\n logic signed [6:0] byte_track, byte_track_next;\n logic cycle_load;\n\n assign vd_offset_o = (vl_i << vsew_i) - byte_track;\n\n always_comb begin\n if(au_valid_o) begin // Make sure that all our addresses are word aligned\n au_addr_o = {cycle_addr[31:2], 2'd0};\n au_be_o = be_gen;\n end else begin\n au_addr_o = 32'd0;\n au_be_o = 4'b0000;\n end\n end\n\n always_comb begin\n if(au_start_i)\n byte_track_next = {2'd0, vl_i} << vsew_i; // Bytes dependent on element size\n else if(current_state != CYCLE)\n byte_track_next = byte_track;\n else \n byte_track_next = (byte_track >= cycle_bytes) ? (byte_track - cycle_bytes) : 7'd0;\n end \n\n always_ff @(posedge clk_i, negedge n_rst_i) begin\n if(~n_rst_i)\n byte_track <= 7'd0;\n else \n byte_track <= byte_track_next;\n end\n\n always_ff @(posedge clk_i, negedge n_rst_i) begin\n if(~n_rst_i)\n cycle_addr <= 32'd0;\n else if(au_start_i)\n cycle_addr <= base_addr_i;\n else if(current_state != CYCLE) \n cycle_addr <= cycle_addr;\n else \n cycle_addr <= next_el_addr;\n end\n\n always_ff @(posedge clk_i, negedge n_rst_i) begin\n if(~n_rst_i)\n current_state <= RESET;\n else\n current_state <= next_state;\n end\n\n always_comb begin\n be_gen = 4'b0000;\n case(vsew_i)\n 2'b00 : begin // 8 Bit\n ib_select = cycle_addr[1:0];\n\n if(stride_i > 1) begin\n be_gen[ib_select] = 1'b1;\n\n // Where is our next byte?\n next_el_pre = cycle_addr + stride_i;\n if(next_el_pre[31:2] == cycle_addr[31:2] && byte_track > 1) begin\n be_gen[next_el_pre[1:0]] = 1'b1;\n next_el_addr = next_el_pre + stride_i; // Stride by second element\n end else begin\n next_el_addr = next_el_pre;\n end\n\n // Calculate the number of bytes for cycle\n cycle_bytes = {5'd0, be_gen[3]} + {5'd0, be_gen[2]} + {5'd0, be_gen[1]} + {5'd0, be_gen[0]};\n end else if(stride_i == 1) begin\n be_gen[0] = (ib_select == 0) ? 1 : 0;\n be_gen[1] = (ib_select == 1 || byte_track > 1) ? 1'b1 : 1'b0;\n be_gen[2] = (ib_select == 2 || byte_track > 2) ? 1'b1 : 1'b0;\n be_gen[3] = (ib_select == 3 || byte_track > 3) ? 1'b1 : 1'b0;\n next_el_addr = {cycle_addr[31:2], 2'b0} + 32'd4;\n\n // Calculate the number of bytes for cycle\n cycle_bytes = {5'd0, be_gen[3]} + {5'd0, be_gen[2]} + {5'd0, be_gen[1]} + {5'd0, be_gen[0]}; \n end else if(stride_i == 0) begin\n be_gen[ib_select] = 1'b1;\n cycle_bytes = {2'b0, vl_i}; // Read all bytes in 1 cycle\n end\n end\n 2'b01 : begin // 16 Bit\n ib_select = {cycle_addr[1], 1'b0}; // Force alignment byte 0 or 2\n\n if(stride_i > 2) begin // Always 1 element\n // Always set 2 bytes\n be_gen[ib_select] = 1'b1; \n be_gen[ib_select+1] = 1'b1;\n next_el_addr = {cycle_addr[31:1], 1'b0} + {stride_i[31:1], 1'b0};\n \n // Calculate the number of bytes for cycle\n<TARGET>\n end else if (stride_i == 2) begin // Up to 2 Elements\n be_gen[1:0] = (ib_select == 0) ? 2'b11 : 2'b00;\n be_gen[3:2] = (ib_select == 2 || byte_track > 2) ? 2'b11 : 2'b00;\n next_el_addr = {cycle_addr[31:2], 2'b0} + 32'd4;\n \n // Calculate the number of bytes for cycle\n", "right_context": " end else if (stride_i == 0) begin \n be_gen[ib_select] = 1'b1;\n be_gen[ib_select+1] = 1'b1;\n cycle_bytes = {1'b0, vl_i, 1'b0}; // Read all bytes in 1 cycle\n end\n end\n 2'b10 : begin // 32 Bit\n ib_select = 2'd0; // Force alignment to byte 0\n\n if(stride_i >= 4) begin // Always 1 element\n be_gen = 4'b1111;\n next_el_addr = {cycle_addr[31:2], 2'b0} + {stride_i[31:2], 2'b0}; // stride_i is always a multiple of 4\n \n // Calculate the number of bytes for cycle\n cycle_bytes = {5'd0, be_gen[3]} + {5'd0, be_gen[2]} + {5'd0, be_gen[1]} + {5'd0, be_gen[0]};\n end else if(stride_i == 0) begin\n be_gen = 4'b1111;\n cycle_bytes = {1'b0, vl_i, 1'b0}; // Read all bytes in 1 cycle\n end\n end\n default : $error(\"Invalid VSEW\"); \n endcase\n end\n\n always_comb begin\n cycle_load = 1'b0;\n au_valid_o = 1'b0;\n au_ready_o = 1'b0;\n au_final_o = 1'b0;\n case(current_state)\n RESET: begin\n au_ready_o = 1'b1;\n if(au_start_i)\n next_state = FIRST;\n else\n next_state = RESET;\n end\n FIRST: begin\n au_valid_o = 1'b1;\n if(stride_i != 0) begin\n next_state = WAIT;\n end else begin\n next_state = RESET;\n end\n end\n CYCLE: begin\n au_valid_o = 1'b1;\n if(byte_track_next == 0) begin\n next_state = WAIT;\n end else begin\n cycle_load = 1'b1;\n next_state = WAIT;\n end\n end\n WAIT: begin\n if(au_next_i)\n next_state = CYCLE;\n else if(byte_track_next == 0)\n next_state = FINAL;\n else\n next_state = WAIT;\n end\n FINAL: begin\n au_final_o = 1'b1;\n next_state = RESET;\n end\n endcase\n end\n\n initial begin\n $dumpfile(\"test.vcd\");\n $dumpvars;\n $display(\" Model running...\\n\");\n end\nendmodule\n/* verilator lint_on ALWCOMBORDER */\n", "groundtruth": " cycle_bytes = {5'd0, be_gen[3]} + {5'd0, be_gen[2]} + {5'd0, be_gen[1]} + {5'd0, be_gen[0]};\n", "crossfile_context": ""}
{"task_id": "ava-core", "path": "ava-core/rtl/arith_stage.sv", "left_context": "//\n// SPDX-License-Identifier: CERN-OHL-S-2.0+\n//\n// Copyright (C) 2020-21 Embecosm Limited <www.embecosm.com>\n// Contributed by:\n// Matthew Johns <mrj1g17@soton.ac.uk>\n//\n// This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY,\n// INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR\n// A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable\n// conditions.\n// Source location: https://github.com/AI-Vector-Accelerator\n//\n\n// Module instance to contain the PEs and supporting logic such as input/output\n// selection logic. This is just to tidy up the top-level a bit.\n\nimport accelerator_pkg::*;\n\nmodule arith_stage (\n output logic [127:0] arith_output,\n output logic [127:0] replicated_scalar, // Want this output for vmv.v.i\n input wire clk,\n input wire n_reset,\n input wire [127:0] vs1_data,\n input wire [127:0] vs2_data,\n input wire [127:0] vs3_data,\n input wire [31:0] scalar_operand,\n input wire [4:0] imm_operand,\n input wire [1:0] elements_to_write,\n input wire [1:0] cycle_count,\n input pe_arith_op_t op,\n input pe_saturate_mode_t saturate_mode,\n input pe_output_mode_t output_mode,\n input pe_operand_t operand_select,\n input wire [1:0] widening,\n input wire [1:0] mul_us,\n input wire unsigned_immediate,\n input wire wide_vs1,\n input wire [4:0] vl,\n input wire [1:0] vsew\n);\n\nlogic [31:0] reduction_intermediate_reg;\n\n// logic [127:0] replicated_scalar;\n\nwire [31:0] pe0_out;\nwire [31:0] pe1_out;\nwire [31:0] pe2_out;\nwire [31:0] pe3_out;\n\nlogic [31:0] pe0_b_data;\nlogic [31:0] pe1_b_data;\nlogic [31:0] pe2_b_data;\nlogic [31:0] pe3_b_data;\n\nlogic [31:0] scalar_to_replicate;\n\npe_32b pe0 (\n .out(pe0_out),\n .a(vs2_data[31:0]),\n .b(pe0_b_data),\n .c(vs3_data[31:0]),\n .op(op),\n .vsew(vsew),\n .widening(widening),\n .mul_us(mul_us),\n .saturate_mode(saturate_mode),\n .output_mode(output_mode),\n .wide_b(wide_vs1)\n);\n\npe_32b pe1 (\n .out(pe1_out),\n .a(vs2_data[63:32]),\n .b(pe1_b_data),\n .c(vs3_data[63:32]),\n .op(op),\n .vsew(vsew),\n .widening(widening),\n .mul_us(mul_us),\n .saturate_mode(saturate_mode),\n .output_mode(output_mode),\n .wide_b(wide_vs1)\n);\n\npe_32b pe2 (\n .out(pe2_out),\n .a(vs2_data[95:64]),\n .b(pe2_b_data),\n .c(vs3_data[95:64]),\n .op(op),\n .vsew(vsew),\n .widening(widening),\n .mul_us(mul_us),\n .saturate_mode(saturate_mode),\n .output_mode(output_mode),\n .wide_b(wide_vs1)\n);\n\npe_32b pe3 (\n .out(pe3_out),\n .a(vs2_data[127:96]),\n .b(pe3_b_data),\n .c(vs3_data[127:96]),\n .op(op),\n .vsew(vsew),\n .widening(widening),\n .mul_us(mul_us),\n .saturate_mode(saturate_mode),\n .output_mode(output_mode),\n .wide_b(wide_vs1)\n);\n\nscalar_replicate scalar_rep0 (\n .replicated_out(replicated_scalar),\n .scalar_in(scalar_to_replicate),\n .vsew(vsew),\n .us(1'b0)\n);\n\n// Update the intermediate register used for reduction operations every cycle\nalways_ff @(posedge clk, negedge n_reset)\n if (~n_reset)\n reduction_intermediate_reg <= '0;\n else\n reduction_intermediate_reg <= pe3_out;\n\n////////////////////////////////////////////////////////////////////////////////\n// PE INPUT OPERAND SELECTION\n////////////////////////////////////////////////////////////////////////////////\nalways_comb\nbegin\n scalar_to_replicate = scalar_operand;\n\n case (operand_select)\n PE_OPERAND_VS1:\n begin\n pe0_b_data = vs1_data[31:0];\n pe1_b_data = vs1_data[63:32];\n pe2_b_data = vs1_data[95:64];\n pe3_b_data = vs1_data[127:96];\n end\n PE_OPERAND_SCALAR:\n begin\n pe0_b_data = replicated_scalar[31:0];\n pe1_b_data = replicated_scalar[63:32];\n pe2_b_data = replicated_scalar[95:64];\n pe3_b_data = replicated_scalar[127:96];\n end\n", "right_context": " pe3_b_data = {'0, imm_operand[4:0]};\n end\n else\n begin\n pe0_b_data = {{27{imm_operand[4]}}, imm_operand[4:0]};\n pe1_b_data = {{27{imm_operand[4]}}, imm_operand[4:0]};\n pe2_b_data = {{27{imm_operand[4]}}, imm_operand[4:0]};\n pe3_b_data = {{27{imm_operand[4]}}, imm_operand[4:0]};\n end\n // This line handles a special case - the scalar replicate logic is\n // used for vmv.v.i instructions but the PE is not used. In this\n // case the immediate operand needs to be replicated and returned.\n scalar_to_replicate = {{27{imm_operand[4]}}, imm_operand[4:0]};\n end\n PE_OPERAND_RIPPLE:\n begin\n // For first cycle of reduction operation want to look at vs1[0].\n // For later cycles need the intermediate value from last cycle.\n if (cycle_count == 2'd0)\n pe0_b_data = vs1_data[31:0];\n else\n pe0_b_data = reduction_intermediate_reg;\n pe1_b_data = pe0_out;\n pe2_b_data = pe1_out;\n pe3_b_data = pe2_out;\n end\n endcase\nend\n\n////////////////////////////////////////////////////////////////////////////////\n// PE OUTPUT SELECTION\n////////////////////////////////////////////////////////////////////////////////\nalways_comb\nbegin\n // For reduction operations the output comes from a single PE (the last in\n // the chain), but which PE is last depends on VL.\n if (operand_select == PE_OPERAND_RIPPLE)\n case (vl[1:0])\n 2'd0:\n // Perhaps counterintuitively, if vl[1:0] is zero that means all\n // four elements are being written so want the last PE.\n arith_output = {'0, pe3_out};\n 2'd1:\n arith_output = {'0, pe0_out};\n 2'd2:\n arith_output = {'0, pe1_out};\n 2'd3:\n arith_output = {'0, pe2_out};\n default:\n arith_output = {'0, pe3_out};\n endcase\n else\n arith_output = {pe3_out, pe2_out, pe1_out, pe0_out};\nend\n\n\nendmodule\n", "groundtruth": " PE_OPERAND_IMMEDIATE:\n begin\n if (unsigned_immediate)\n begin\n", "crossfile_context": ""}
{"task_id": "ava-core", "path": "ava-core/rtl/bit_ext.sv", "left_context": "//\n// SPDX-License-Identifier: CERN-OHL-S-2.0+\n//\n// Copyright (C) 2020-21 Embecosm Limited <www.embecosm.com>\n// Contributed by:\n// Byron Theobald <bt4g16@soton.ac.uk>\n//\n// This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY,\n// INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR\n// A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable\n// conditions.\n// Source location: https://github.com/AI-Vector-Accelerator\n//\n\n// W_IN must be smaller than W_OUT\nmodule bit_ext #(parameter W_IN = 8, parameter W_OUT = 12) \n", "right_context": " assign a_out = {{(W_OUT-W_IN){a_in[W_IN-1]}}, a_in};\n\nendmodule\n", "groundtruth": " (input logic signed [W_IN-1:0] a_in, \n output logic signed [W_OUT-1:0] a_out);\n", "crossfile_context": ""}
{"task_id": "ava-core", "path": "ava-core/rtl/mapping_unit.sv", "left_context": "//\n// SPDX-License-Identifier: CERN-OHL-S-2.0+\n//\n// Copyright (C) 2020-21 Embecosm Limited <www.embecosm.com>\n// Contributed by:\n// Byron Theobald <bt4g16@soton.ac.uk>\n//\n// This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY,\n// INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR\n// A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable\n// conditions.\n// Source location: https://github.com/AI-Vector-Accelerator\n//\n\nmodule mapping_unit\n (input logic [127:0] arith_format_o,\n output logic [31:0] memory_format_i,\n input logic [1:0] sew_i,\n input logic [1:0] reg_select);\n\n \n\n\n \n vd_wr_data0 = '{\n vd_data[103:96],\n vd_data[71:64],\n vd_data[39:32],\n vd_data[7:0]\n };\n 2'd1: // 16b\n begin\n vd_wr_data1 = {\n vd_data[111:96],\n vd_data[79:64]\n };\n vd_wr_data0 = {\n vd_data[47:32],\n", "right_context": " };\n end\n 2'd2: // 32b\n begin\n vd_wr_data3 = vd_data[127:96];\n vd_wr_data2 = vd_data[95:64];\n vd_wr_data1 = vd_data[63:32];\n vd_wr_data0 = vd_data[31:0];*/\nendmodule \n", "groundtruth": " vd_data[15:0]\n", "crossfile_context": ""}
{"task_id": "ava-core", "path": "ava-core/rtl/pe_32b.sv", "left_context": "//\n// SPDX-License-Identifier: CERN-OHL-S-2.0+\n//\n// Copyright (C) 2020-21 Embecosm Limited <www.embecosm.com>\n// Contributed by:\n// Matthew Johns <mrj1g17@soton.ac.uk>\n//\n// This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY,\n// INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR\n// A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable\n// conditions.\n// Source location: https://github.com/AI-Vector-Accelerator\n//\n\n// NOTE (Matthew Johns) - there is similarity between parts of this code and the\n// proc_unit.sv module made by me in my third-year project. This is because the\n// functionality is similar and therefore I'm using what I learnt previously.\n\n// `include \"defs.sv\"\nimport accelerator_pkg::*;\n\nmodule pe_32b (\n output logic [31:0] out,\n // output logic flag_saturated // TODO: add this flag for CSRs\n input wire [31:0] a,\n input wire [31:0] b,\n input wire [31:0] c,\n input pe_arith_op_t op,\n input wire [1:0] vsew,\n input wire [1:0] widening, // 2'd1 for widening, 2'd2 for quad widening\n input wire [1:0] mul_us, // Specifies each multiplier input as signed or unsigned\n input pe_saturate_mode_t saturate_mode,\n input pe_output_mode_t output_mode,\n input wire wide_b\n);\n\n// Usually input \"a\" is vs2, input \"b\" is vs1 and \"c\" is vs3/vd. (This is for\n// most standard arithmetic operations)\n\nlogic signed [32:0] mult_a;\nlogic signed [32:0] mult_b;\nlogic signed [65:0] mult_wide;\nlogic signed [32:0] selected_mult_out;\n\nlogic [32:0] add_out;\nlogic [32:0] add_a;\nlogic [32:0] add_b;\nlogic [32:0] addend;\n\n// Intermediate before saturation/ReLU\n// Has to be 33 bits to give at least one bit for saturation\nlogic [32:0] arith_result;\n\nlogic macc;\nlogic subtract;\n\n// Instantiate sign extension module for inputs a, b and c\nwire [31:0] sign_ext_a;\nwire [31:0] sign_ext_b;\nwire [31:0] sign_ext_c;\nvw_sign_ext se0 (\n .sign_ext_a(sign_ext_a),\n .sign_ext_b(sign_ext_b),\n .sign_ext_c(sign_ext_c),\n .a(a),\n .b(b),\n .c(c),\n .widening(widening),\n .vsew(vsew),\n .wide_b(wide_b)\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// ARITHMETIC STAGE\n////////////////////////////////////////////////////////////////////////////////\nalways_comb\nbegin\n subtract = 1'b0;\n macc = 1'b0;\n arith_result = '0;\n\n case (op)\n // 4'h0: // Add\n PE_ARITH_ADD:\n arith_result = add_out;\n // 4'h1: // Sub\n PE_ARITH_SUB:\n begin\n arith_result = add_out;\n subtract = 1'b1;\n end\n // 4'h2: // Left-shift\n PE_ARITH_LSHIFT:\n arith_result = {1'b0, (a << b)};\n // 4'h3: // Multiply\n PE_ARITH_MUL:\n arith_result = selected_mult_out;\n // 4'h4: // Multiply-add\n PE_ARITH_MULADD:\n begin\n macc = 1'b1;\n arith_result = add_out;\n end\n // 4'h5: // XOR\n PE_ARITH_XOR:\n arith_result = {1'b0, (a ^ b)};\n // 4'h6: // Right-shift\n PE_ARITH_RSHIFT_LOG:\n arith_result = {1'b0, (a >> b)};\n // 4'h7: // Right-shift (arithmetic)\n PE_ARITH_RSHIFT_AR:\n arith_result = {1'b0, (a >>> b)};\n // 4'h8: // OR\n PE_ARITH_OR:\n arith_result = {1'b0, (a | b)};\n // 4'h9: // AND\n PE_ARITH_AND:\n arith_result = {1'b0, (a & b)};\n endcase\nend\n\nalways_comb\nbegin\n // Multiplier needs to be able to be toggled between signed/unsigned for the\n // individual operands (depending on instructions). Can do this by adding an\n // extra bit to the inputs and sign-extending them for signed operations.\n // Then take the correct number of bits from the bottom.\n if (mul_us[1])\n mult_a = {1'b0, a};\n else\n mult_a = {sign_ext_a[31], sign_ext_a};\n if (mul_us[0])\n mult_b = {1'b0, b};\n else\n mult_b = {sign_ext_b[31], sign_ext_b};\n\n mult_wide = mult_a * mult_b;\n\n // Select adder inputs\n if (macc)\n begin\n add_a = {1'b0, mult_wide[31:0]};\n add_b = {1'b0, c};\n end\n else\n begin\n // Need to sign extend for saturated ops as another bit is gained to be\n // used for saturation.\n // This means instructions are fixed as signed. Would have to split up\n // if wanted to toggle signed/unsigned.\n // For some operations (such as regular addition) sign extension isn't\n // needed. But it doesn't do any harm and simplifies the logic.\n add_a = {sign_ext_a[31], sign_ext_a};\n add_b = {sign_ext_b[31], sign_ext_b};\n end\n\n if (subtract)\n addend = ~add_b + 1'b1;\n else\n addend = add_b;\n add_out = add_a + addend;\n\nend\n\n// Select multiplier output. V spec requires fractional saturating multiplies to\n// take the upper bits for saturation instead of lower bits. Should be able to\n// toggle this as we might need to saturate it and keep lower bits later on\nalways_comb\nbegin\n if (saturate_mode == PE_SAT_UPPER)\n case (vsew)\n 2'd0: // 8b\n selected_mult_out = {{24{1'b0}}, mult_wide[8:0]};\n 2'd1: // 16b\n selected_mult_out = {{16{1'b0}}, mult_wide[16:0]};\n 2'd2: // 32b\n selected_mult_out = mult_wide[32:0];\n default:\n selected_mult_out = mult_wide[32:0];\n endcase\n else\n selected_mult_out = mult_wide[32:0];\nend\n\n////////////////////////////////////////////////////////////////////////////////\n// SATURATE STAGE\n////////////////////////////////////////////////////////////////////////////////\nlogic [31:0] sat_result;\n// Instantiate the saturation blocks. One for each element width. Output is\n// selected from one of them at a time.\nwire [7:0] sat8_result;\nsat_unit #(\n .W_IN(33),\n .W_OUT(8)\n) sat8\n(\n .a_in(arith_result),\n .a_out(sat8_result)\n);\nwire [15:0] sat16_result;\nsat_unit #(\n .W_IN(33),\n .W_OUT(16)\n) sat16\n(\n .a_in(arith_result),\n .a_out(sat16_result)\n);\nwire [31:0] sat32_result;\nsat_unit #(\n .W_IN(33),\n .W_OUT(32)\n) sat32\n(\n .a_in(arith_result),\n .a_out(sat32_result)\n);\n\nalways_comb\nbegin\n sat_result = arith_result[31:0];\n // For widening, need to saturate to next larger element size\n if (widening[0])\n case (vsew)\n", "right_context": " else\n case (vsew)\n 2'd0: // 8b\n sat_result = {'0, sat8_result};\n 2'd1: // 16b\n sat_result = {'0, sat16_result};\n 2'd2: // 32b\n sat_result = sat32_result;\n endcase\nend\n\n////////////////////////////////////////////////////////////////////////////////\n// OUTPUT MODE SELECT\n////////////////////////////////////////////////////////////////////////////////\nalways_comb\nbegin\n out = arith_result[31:0];\n case (output_mode)\n PE_OP_MODE_RESULT:\n if (saturate_mode == PE_SAT_NONE)\n out = arith_result[31:0];\n else\n out = sat_result;\n PE_OP_MODE_PASS_MAX:\n // Will do arithmetic op of a-b. If negative, b is larger so pass b\n if (arith_result[32])\n out = b;\n else\n out = a;\n PE_OP_MODE_PASS_MIN:\n if (arith_result[32])\n out = a;\n else\n out = b;\n // Important point for this: am looking at bit 31 (not 32) because\n // the inputs aren't sign-extended for anything non-saturating.\n endcase\nend\n\nendmodule\n", "groundtruth": " 2'd0: // 8b -> 16b\n sat_result = {'0, sat16_result};\n 2'd1: // 16b -> 32b\n sat_result = sat32_result;\n endcase\n", "crossfile_context": ""}
{"task_id": "ava-core", "path": "ava-core/rtl/relu_bound.sv", "left_context": "//\n// SPDX-License-Identifier: CERN-OHL-S-2.0+\n//\n// Copyright (C) 2020-21 Embecosm Limited <www.embecosm.com>\n// Contributed by:\n// Byron Theobald <bt4g16@soton.ac.uk>\n//\n// This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY,\n// INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR\n// A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable\n// conditions.\n// Source location: https://github.com/AI-Vector-Accelerator\n//\n\nmodule relu_bound\n #(parameter W=8, parameter N=(6<<4)) \n (input logic signed [W-1:0] a, \n output logic [W-2:0] ar);\n\n logic signed [W-1:0] zero = 'd0;\n always_comb begin\n if(a < zero)\n", "right_context": "", "groundtruth": " ar = 0;\n else if (a > N)\n ar = N[6:0];\n else\n ar = a[6:0];\n", "crossfile_context": ""}
{"task_id": "ava-core", "path": "ava-core/rtl/sat_unit.sv", "left_context": "//\n// SPDX-License-Identifier: CERN-OHL-S-2.0+\n//\n// Copyright (C) 2020-21 Embecosm Limited <www.embecosm.com>\n// Contributed by:\n// Byron Theobald <bt4g16@soton.ac.uk>\n//\n// This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY,\n// INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR\n// A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable\n// conditions.\n// Source location: https://github.com/AI-Vector-Accelerator\n//\n\n// W_IN must be larger than W_OUT\nmodule sat_unit #(parameter W_IN = 13, parameter W_OUT = 8) \n (input logic signed [W_IN-1:0] a_in, \n output logic signed [W_OUT-1:0] a_out);\n \n logic signed [W_IN-1:0] max_in = {{(W_IN-W_OUT+1){1'b0}},{(W_OUT-1){1'b1}}}; \n logic signed [W_IN-1:0] min_in = {{(W_IN-W_OUT+1){1'b1}},{(W_OUT-1){1'b0}}};\n logic signed [W_OUT-1:0] max_out = {1'b0,{(W_OUT-1){1'b1}}}; \n", "right_context": "", "groundtruth": " logic signed [W_OUT-1:0] min_out = {1'b1,{(W_OUT-1){1'b0}}};\n\n assign a_out = a_in < min_in ? min_out : (a_in > max_in) ? max_out : a_in[W_OUT-1:0];\n\n //initial $display(\"%d, %d, %d, %d\", max_in, min_in, max_out, min_out);\n", "crossfile_context": ""}
{"task_id": "ava-core", "path": "ava-core/rtl/scalar_replicate.sv", "left_context": "//\n// SPDX-License-Identifier: CERN-OHL-S-2.0+\n//\n// Copyright (C) 2020-21 Embecosm Limited <www.embecosm.com>\n// Contributed by:\n// Matthew Johns <mrj1g17@soton.ac.uk>\n//\n// This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY,\n// INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR\n// A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable\n// conditions.\n// Source location: https://github.com/AI-Vector-Accelerator\n//\n\n// import accelerator_pkg::*;\n\nmodule scalar_replicate (\n output logic [127:0] replicated_out,\n input wire [31:0] scalar_in,\n input wire [1:0] vsew,\n input wire us\n);\n\n// When a scalar operand comes into the accelerator there is only one copy of\n// it. However, each PE needs a copy for it's calculation, so it must be\n// replicated into the right position for each PE. This module does that.\n\nalways_comb\n case (vsew)\n 2'd0: // 8b\n if (us)\n replicated_out = {\n 24'd0,\n scalar_in[7:0],\n 24'd0,\n scalar_in[7:0],\n 24'd0,\n scalar_in[7:0],\n 24'd0,\n scalar_in[7:0]\n };\n else\n replicated_out = {\n {24{scalar_in[7]}},\n scalar_in[7:0],\n {24{scalar_in[7]}},\n scalar_in[7:0],\n {24{scalar_in[7]}},\n scalar_in[7:0],\n {24{scalar_in[7]}},\n scalar_in[7:0]\n };\n 2'd1: // 16b\n if (us)\n replicated_out = {\n 16'd0,\n scalar_in[15:0],\n 16'd0,\n scalar_in[15:0],\n 16'd0,\n scalar_in[15:0],\n 16'd0,\n scalar_in[15:0]\n };\n", "right_context": " scalar_in[15:0]\n };\n 2'd2: // 32b\n replicated_out = {\n {4{scalar_in}}\n };\n default:\n replicated_out = {'0, scalar_in};\n endcase\n\n\nendmodule\n", "groundtruth": " else\n replicated_out = {\n {16{scalar_in[15]}},\n scalar_in[15:0],\n {16{scalar_in[15]}},\n", "crossfile_context": ""}
{"task_id": "ava-core", "path": "ava-core/rtl/tb/tb_bit_ext.sv", "left_context": "//\n// SPDX-License-Identifier: CERN-OHL-S-2.0+\n//\n// Copyright (C) 2020-21 Embecosm Limited <www.embecosm.com>\n// Contributed by:\n// Byron Theobald <bt4g16@soton.ac.uk>\n//\n// This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY,\n// INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR\n// A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable\n// conditions.\n// Source location: https://github.com/AI-Vector-Accelerator\n//\n\n`timescale 1ns/10ps\n\n`include \"bit_ext.sv\"\n\nmodule tb_bit_ext;\n\nlogic signed [7:0] in;\nlogic signed [11:0] out; \nbit_ext #(.W_IN(8), .W_OUT(12)) bit_ext(in, out);\n\ninitial begin\n `ifndef VERILATOR\n $dumpfile(\"bit_ext.vcd\");\n $dumpvars;\n `endif\n\n for(in = -128; in < 127; in++) begin\n", "right_context": " end\n\n $finish;\nend\n\nendmodule\n", "groundtruth": " #1ns $display(\"%d, %d\", in, out);\n", "crossfile_context": ""}
{"task_id": "ava-core", "path": "ava-core/rtl/tb/tb_relu_bound.sv", "left_context": "//\n// SPDX-License-Identifier: CERN-OHL-S-2.0+\n//\n// Copyright (C) 2020-21 Embecosm Limited <www.embecosm.com>\n// Contributed by:\n// Byron Theobald <bt4g16@soton.ac.uk>\n//\n// This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY,\n// INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR\n// A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable\n// conditions.\n// Source location: https://github.com/AI-Vector-Accelerator\n//\n\n`timescale 1ns/10ps\n\n`include \"relu_bound.sv\"\n\nmodule tb_relu_bound;\n\nlogic signed [7:0] in;\nlogic [6:0] out; \nrelu_bound #(.W(8)) rb(in, out);\n\nlogic signed [7:0] i;\n\ninitial begin\n `ifndef VERILATOR\n $dumpfile(\"relu_bound.vcd\");\n $dumpvars;\n `endif\n\n for(in = -128; in < 127; in++) begin\n", "right_context": " end\n\n $finish;\nend\n\nendmodule\n", "groundtruth": " #10ns $display(\"%d, %d\", in, out);\n", "crossfile_context": ""}
{"task_id": "ava-core", "path": "ava-core/rtl/tb/tb_sat_unit.sv", "left_context": "//\n// SPDX-License-Identifier: CERN-OHL-S-2.0+\n//\n// Copyright (C) 2020-21 Embecosm Limited <www.embecosm.com>\n// Contributed by:\n// Byron Theobald <bt4g16@soton.ac.uk>\n//\n// This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY,\n// INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR\n// A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable\n// conditions.\n// Source location: https://github.com/AI-Vector-Accelerator\n//\n\n`timescale 1ns/10ps\n\n`include \"sat_unit.sv\"\n\nmodule tb_sat_unit;\n\nlogic signed [12:0] in;\nlogic signed [7:0] out; \n", "right_context": "\nlogic signed [7:0] i;\n\ninitial begin\n `ifndef VERILATOR\n $dumpfile(\"sat_unit.vcd\");\n $dumpvars;\n `endif\n\n for(in = -256; in < 256; in++) begin\n #1ns $display(\"%d, %d\", in, out);\n end\n\n $finish;\nend\n\nendmodule\n", "groundtruth": "sat_unit #(.W_IN(13), .W_OUT(8)) satu(in, out);\n", "crossfile_context": ""}
{"task_id": "ava-core", "path": "ava-core/rtl/temporary_reg.sv", "left_context": "//\n// SPDX-License-Identifier: CERN-OHL-S-2.0+\n//\n// Copyright (C) 2020-21 Embecosm Limited <www.embecosm.com>\n// Contributed by:\n// Byron Theobald <bt4g16@soton.ac.uk>\n//\n// This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY,\n// INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR\n// A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable\n// conditions.\n// Source location: https://github.com/AI-Vector-Accelerator\n//\n\n// 32-Bit input, byte_position selects the bytes to load.\n// Selected bytes will be packed and loaded into the \n// register starting from byte_loaded\n\nmodule temporary_reg (\n input logic clk_i, n_rst_i,\n input logic byte_enable_valid,\n input logic read_data_valid,\n input logic clear_register,\n input logic [31:0] memory_read_i,\n input logic [3:0] byte_enable_i,\n input logic [6:0] byte_select_i,\n output logic [127:0] wide_vd_o);\n\n logic [3:0] byte_enable_reg;\n\n always_ff @(posedge clk_i, negedge n_rst_i) begin\n if(~n_rst_i)\n byte_enable_reg <= 1'b0;\n else if(byte_enable_valid)\n byte_enable_reg <= byte_enable_i;\n end\n\n // Tempoary register, split into bytes.\n logic [7:0] temp_reg [15:0];\n\n // Split memory read into bytes\n logic [7:0] memory_read_bytes [3:0];\n \n always_comb begin // Split bytes out of word\n memory_read_bytes[0] = memory_read_i[7:0];\n memory_read_bytes[1] = memory_read_i[15:8];\n memory_read_bytes[2] = memory_read_i[23:16];\n memory_read_bytes[3] = memory_read_i[31:24]; \n end\n\n // Packed read bytes, shift higher elements down\n logic [7:0] memory_read_packed [3:0];\n logic [3:0] packed_set;\n\n always_comb begin\n\t\t memory_read_packed = '{default:0};\n packed_set = 4'b0000;\n if(byte_enable_reg[0]) begin\n packed_set[0] = 1'b1;\n memory_read_packed[0] = memory_read_bytes[0];\n end\n if(byte_enable_reg[1]) begin\n casez(packed_set)\n 4'bzzz0 : begin\n packed_set[0] = 1'b1;\n memory_read_packed[0] = memory_read_bytes[1];\n end\n 4'bzzz1 : begin\n packed_set[1] = 1'b1;\n memory_read_packed[1] = memory_read_bytes[1];\n end\n\t\t\t\t\t default: begin\n\t\t\t\t\t\t memory_read_packed[1] = '0;\n\t\t\t\t\t end\n endcase\n end\n if(byte_enable_reg[2]) begin\n casez(packed_set)\n 4'bzz00 : begin\n packed_set[0] = 1'b1;\n memory_read_packed[0] = memory_read_bytes[2];\n end\n 4'bzz01 : begin\n", "right_context": "\t\t\t\t\t end\n endcase\n end\n if(byte_enable_reg[3]) begin\n casez(packed_set)\n 4'bz000 : begin\n packed_set[0] = 1'b1;\n memory_read_packed[0] = memory_read_bytes[3];\n end\n 4'bz001 : begin\n packed_set[1] = 1'b1;\n memory_read_packed[1] = memory_read_bytes[3];\n end\n 4'bz011 : begin\n packed_set[2] = 1'b1;\n memory_read_packed[2] = memory_read_bytes[3];\n end\n 4'bz111 : begin\n packed_set[3] = 1'b1;\n memory_read_packed[3] = memory_read_bytes[3];\n end\n\t\t\t\t\t default: begin\n\t\t\t\t\t\t memory_read_packed[3] = '0;\n\t\t\t\t\t end\n endcase\n end\n end\n\n // Write elements into register\n always_ff @(posedge clk_i, negedge n_rst_i) begin\n if(~n_rst_i) begin\n temp_reg <= '{default: 8'd0}; \n end else if(clear_register) begin \n temp_reg <= '{default: 8'd0};\n end else if(read_data_valid) begin\n if(packed_set[0]) temp_reg[byte_select_i+0] <= memory_read_packed[0];\n if(packed_set[1]) temp_reg[byte_select_i+1] <= memory_read_packed[1];\n if(packed_set[2]) temp_reg[byte_select_i+2] <= memory_read_packed[2];\n if(packed_set[3]) temp_reg[byte_select_i+3] <= memory_read_packed[3];\n end\n end\n\n assign wide_vd_o = {temp_reg[15], temp_reg[14], temp_reg[13], temp_reg[12],\n temp_reg[11], temp_reg[10], temp_reg[ 9], temp_reg[ 8], \n temp_reg[ 7], temp_reg[ 6], temp_reg[ 5], temp_reg[ 4], \n temp_reg[ 3], temp_reg[ 2], temp_reg[ 1], temp_reg[ 0]};\n\nendmodule\n", "groundtruth": " packed_set[1] = 1'b1;\n memory_read_packed[1] = memory_read_bytes[2];\n end\n 4'bzz11 : begin\n packed_set[2] = 1'b1;\n", "crossfile_context": ""}
{"task_id": "ava-core", "path": "ava-core/rtl/vector_csrs.sv", "left_context": "//\n// SPDX-License-Identifier: CERN-OHL-S-2.0+\n//\n// Copyright (C) 2020-21 Embecosm Limited <www.embecosm.com>\n// Contributed by:\n// Matthew Johns <mrj1g17@soton.ac.uk>\n// Byron Theobald <bt4g16@soton.ac.uk>\n//\n// This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY,\n// INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR\n// A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable\n// conditions.\n// Source location: https://github.com/AI-Vector-Accelerator\n//\n\n// NOTE (Matthew Johns) - there is similarity between parts of this code and the\n// csr.sv module made by me in my third-year project. This is because the\n// functionality is similar and therefore I'm using what I learnt previously.\n\nmodule vector_csrs (\n output logic [4:0] vl,\n output logic [1:0] vsew,\n output logic [1:0] vlmul,\n output logic [4:0] vl_next_comb,\n input wire clk,\n input wire n_reset,\n input wire [31:0] avl_in,\n input wire [4:0] vtype_in,\n input wire write,\n input wire saturate_flag,\n input wire preserve_vl,\n input wire set_vl_max\n);\n\n// CSRs included in this implementation:\n// 0x009 vxsat fixed-point saturate flag\n// 0x00A vxrm fixed-point rounding mode (fixed to )\n// 0xC20 vl vector length\n// 0xC21 vtype vector data type register\n// 0xC22 vlenb vector register length in bytes\n// For this accelerator they're separate from the standard CSR file - so we\n// might as well put them in one block of their own, in this order\n\nlogic [31:0] csrs [4:0];\n\nlogic [4:0] vl_next;\nlogic [4:0] max_vl;\nlogic [2:0] per_reg;\n\nalways_ff @(posedge clk, negedge n_reset)\n if (~n_reset)\n begin\n for (int i=0; i<4; i++)\n csrs[i] <= '0;\n // vlenb is read-only, so can assign it at reset\n csrs[4] <= 32'd4;\n end\n else\n begin\n if (write)\n begin\n // vtype will be changed for every vsetvli instruction\n csrs[3] <= {'0, vtype_in};\n\n // Don't always want to write VL, eg. if rd == 0 and rs1 == 0\n // preserve_vl controls when it's left unchanged\n if (~preserve_vl)\n csrs[2] <= {'0 , vl_next};\n end\n end\n\n\nalways_comb\nbegin\n // Spec defines vsew as 3 bits of vtype, but our max element is 32b so the\n // top bit will always be zero and we can just look at the lower two\n vsew = csrs[3][3:2];\n vlmul = csrs[3][1:0];\n\n // If the AVL being suggested in the instruction is larger than max_vl, need\n // to set VL to max_vl. Also do this if set_vl_max asserted\n if ( set_vl_max | (avl_in > max_vl) )\n", "right_context": "assign vl = csrs[2][4:0];\n\n// How many elements fit into a single register for each value of VSEW?\n// Can work this out by dividing vlenb by vsew\nassign per_reg = csrs[4][2:0] >> vtype_in[4:2];\n\n// Max VL value equals the max number of elements per register * LMUL. LMUL is\n// in powers of 2 so can use a shift\nassign max_vl = per_reg << vtype_in[1:0];\n\nassign vl_next_comb = vl_next;\n\nendmodule\n", "groundtruth": " vl_next = max_vl;\n else\n vl_next = avl_in[4:0];\n\nend\n", "crossfile_context": ""}
{"task_id": "ava-core", "path": "ava-core/rtl/vector_decoder.sv", "left_context": "//\n// SPDX-License-Identifier: CERN-OHL-S-2.0+\n//\n// Copyright (C) 2020-21 Embecosm Limited <www.embecosm.com>\n// Contributed by:\n// Matthew Johns <mrj1g17@soton.ac.uk>\n// Byron Theobald <bt4g16@soton.ac.uk>\n//\n// This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY,\n// INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR\n// A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable\n// conditions.\n// Source location: https://github.com/AI-Vector-Accelerator\n//\n\n// `include \"defs.sv\"\nimport accelerator_pkg::*;\n\nmodule vector_decoder (\n output logic apu_rvalid,\n output logic apu_gnt,\n output logic [31:0] scalar_operand1,\n output logic [31:0] scalar_operand2,\n output logic [10:0] immediate_operand,\n output logic [4:0] vs1_addr,\n output logic [4:0] vs2_addr,\n output logic [4:0] vd_addr,\n output logic csr_write,\n output logic preserve_vl,\n output logic set_vl_max,\n output logic [1:0] elements_to_write,\n output logic [1:0] cycle_count,\n output logic vec_reg_write,\n output vreg_wb_src_t vd_data_src,\n output vreg_addr_src_t vs3_addr_src,\n output pe_arith_op_t pe_op,\n output pe_saturate_mode_t saturate_mode,\n output pe_output_mode_t output_mode,\n output pe_operand_t operand_select,\n output logic [1:0] pe_mul_us,\n output logic [1:0] widening,\n output apu_result_src_t apu_result_select,\n output logic unsigned_immediate,\n output logic wide_vs1,\n input wire clk,\n input wire n_reset,\n input wire apu_req,\n input wire [31:0] apu_operands [2:0],\n input wire [5:0] apu_op,\n input wire [14:0] apu_flags_i,\n input wire [4:0] vl,\n input wire [1:0] vsew,\n output logic vlsu_en_o,\n output logic vlsu_load_o,\n output logic vlsu_store_o,\n output logic vlsu_strided_o,\n input logic vlsu_ready_i,\n input logic vlsu_done_i,\n output logic core_halt_o\n);\n\nenum {WAIT, EXEC, VALID} state, next_state;\n\nlogic [1:0] max_cycle_count;\nlogic multi_cycle_instr;\nlogic fix_vd_addr;\n\n// Registers to store values from APU interface during instruction execution\nlogic [31:0] reg_apu_operands [2:0];\nlogic [5:0] reg_apu_op;\nlogic [14:0] reg_apu_flags_i;\n\n// Assign variables for individual parts of instructions for readability\nlogic [2:0] funct3;\nlogic [6:0] major_opcode;\nlogic [5:0] funct6;\nlogic [4:0] source1;\nlogic [4:0] source2;\nlogic [4:0] destination;\nlogic [2:0] mop; // Vector Addressing Mode\nassign funct3 = reg_apu_operands[0][14:12];\nassign major_opcode = reg_apu_operands[0][6:0];\nassign funct6 = reg_apu_operands[0][31:26];\nassign source1 = reg_apu_operands[0][19:15];\nassign source2 = reg_apu_operands[0][24:20];\nassign destination = reg_apu_operands[0][11:7];\nassign mop = funct6[2:0];\n\nassign scalar_operand1 = reg_apu_operands[1];\nassign scalar_operand2 = reg_apu_operands[2];\n\nalways_ff @(posedge clk, negedge n_reset)\n if(~n_reset)\n begin\n state <= WAIT;\n reg_apu_operands <= '{3{'0}};\n reg_apu_op <= '0;\n reg_apu_flags_i <= '0;\n end\n else\n begin\n state <= next_state;\n\n // In wait state, can load data from APU interface ready for the next\n // instruction. Only do this when it's valid, otherwise will screw any\n // invalid instruction checking code\n if ((state == WAIT) & apu_req)\n begin\n reg_apu_operands[0] <= apu_operands[0];\n reg_apu_operands[1] <= apu_operands[1];\n reg_apu_operands[2] <= apu_operands[2];\n reg_apu_op <= apu_op;\n reg_apu_flags_i <= apu_flags_i;\n end\n end\n\nlogic core_halt_ctrl;\n\nassign core_halt_o = core_halt_ctrl;\n\n/*always_ff @(posedge clk, negedge n_reset) begin\n if(~n_reset)\n core_halt_o <= 1'b0;\n else\n core_halt_o <= core_halt_ctrl;\nend*/\n\nalways_comb\nbegin\n apu_rvalid = 1'b0;\n apu_gnt = 1'b0;\n next_state = state;\n core_halt_ctrl = 1'b0;\n\n case (state)\n WAIT:\n begin\n apu_gnt = 1'b1;\n if (apu_req)\n next_state = EXEC;\n", "right_context": " next_state = WAIT;\n end\n EXEC:\n begin\n core_halt_ctrl = 1'b1;\n\n if (vlsu_load_o | vlsu_store_o) begin\n if(vlsu_done_i) begin\n apu_rvalid = 1'b1;\n next_state = WAIT;\n end\n end else if (cycle_count == max_cycle_count) begin\n apu_rvalid = 1'b1;\n next_state = WAIT;\n end\n end\n endcase\nend\n\n// VECTOR REGISTER ADDRESS GENERATION\nalways_ff @(posedge clk, negedge n_reset)\n if (~n_reset)\n begin\n cycle_count <= '0;\n end\n else\n begin\n if (state == WAIT || (vlsu_load_o | vlsu_store_o))\n cycle_count <= '0;\n else\n cycle_count <= cycle_count + 1'b1;\n\n end\n\n\nlogic [3:0] vl_zero_indexed;\n\nalways_comb\nbegin\n // Subtract 1 because if VL=4/8/16 it will want another cycle otherwise\n // Number of loads dependant on SEW (For contiguous 8-bit values)\n // TODO: Determine strided count\n // vl_zero_indexed = (vl - 1'b1) >> (2'd2 - vsew); // Used for memory\n vl_zero_indexed = vl - 1'b1;\n // Elements can be handled 4 at a time so divide VL by 4, or force 0\n max_cycle_count = multi_cycle_instr ? vl_zero_indexed[3:2] : 2'd0;\n\n case (vsew)\n 2'd0: // 8b\n begin\n vs1_addr = source1 + cycle_count;\n vs2_addr = source2 + cycle_count;\n if (fix_vd_addr)\n vd_addr = destination;\n else\n begin\n if(widening[0])\n vd_addr = destination + {cycle_count, 1'b0};\n else\n vd_addr = destination + cycle_count;\n end\n end\n 2'd1: // 16b\n begin\n vs1_addr = source1 + {cycle_count, 1'b0};\n vs2_addr = source2 + {cycle_count, 1'b0};\n if (fix_vd_addr)\n vd_addr = destination;\n else\n vd_addr = destination + {cycle_count, 1'b0};\n end\n default:\n begin\n vs1_addr = source1 + cycle_count;\n vs2_addr = source2 + cycle_count;\n if (fix_vd_addr)\n vd_addr = destination;\n else\n vd_addr = destination + cycle_count;\n end\n endcase\n\n if (funct3 == V_OPCFG)\n immediate_operand = reg_apu_operands[0][30:20];\n else\n immediate_operand = {'0, reg_apu_operands[0][19:15]};\nend\n\nalways_comb\nbegin\n elements_to_write = 2'd0;\n\n if (multi_cycle_instr)\n begin\n if (cycle_count == max_cycle_count)\n if (operand_select == PE_OPERAND_RIPPLE)\n // Reductions only want to write in last cycle to only one element\n elements_to_write = 2'd1;\n else\n // On last cycle, work out how many elements remain\n elements_to_write = vl[1:0];\n else\n elements_to_write = 2'd0;\n end\nend\n\n////////////////////////////////////////////////////////////////////////////////\n// ACCELERATOR CONTROL SIGNALS\nalways_comb\nbegin\n // Assign defaults for when not executing\n csr_write = 1'b0;\n preserve_vl = 1'b0;\n set_vl_max = 1'b0;\n vec_reg_write = 1'b0;\n vd_data_src = VREG_WB_SRC_ARITH;\n vs3_addr_src = VS3_ADDR_SRC_DECODE;\n pe_op = PE_ARITH_ADD;\n operand_select = PE_OPERAND_VS1;\n saturate_mode = PE_SAT_NONE;\n output_mode = PE_OP_MODE_RESULT;\n pe_mul_us = 2'b00;\n widening = 2'b00;\n apu_result_select = APU_RESULT_SRC_VL;\n multi_cycle_instr = 1'b0;\n unsigned_immediate = 1'b0;\n wide_vs1 = 1'b0;\n\n vlsu_en_o = 1'b0;\n vlsu_load_o = 1'b0;\n vlsu_store_o = 1'b0;\n vlsu_strided_o = 1'b0;\n\n // Used to control decoder module itself\n fix_vd_addr = 1'b0;\n\n // Control signals during instruction execution\n if (state == EXEC)\n begin\n if (major_opcode == V_MAJOR_LOAD_FP)\n begin\n if(funct3 == 3'b111) begin\n vd_data_src = VREG_WB_SRC_MEMORY;\n vlsu_en_o = 1'b1;\n vlsu_load_o = 1'b1;\n if(mop == 3'b010) vlsu_strided_o = 1'b1;\n end else $error(\"Unimplemented LOAD_FP instruction\");\n end\n else if (major_opcode == V_MAJOR_STORE_FP)\n begin\n if(funct3 == 3'b111) begin\n vs3_addr_src = VS3_ADDR_SRC_VLSU;\n fix_vd_addr = 1'b1;\n vlsu_en_o = 1'b1;\n vlsu_store_o = 1'b1;\n end else $error(\"Unimplemented STORE_FP instruction\");\n end\n else if (major_opcode == V_MAJOR_OP_V)\n begin\n // Consider vsetvli instructions separately (different format)\n if (funct3 == V_OPCFG)\n begin\n csr_write = 1'b1;\n apu_result_select = APU_RESULT_SRC_VL;\n if (source1 == '0)\n begin\n if (destination == '0)\n preserve_vl = 1'b1;\n else\n set_vl_max = 1'b1;\n end\n end\n else\n begin\n // Look for all other OP-V instructions\n case (funct6)\n\n // vadd, vredsum\n 6'b000000:\n begin\n pe_op = PE_ARITH_ADD;\n vec_reg_write = 1'b1;\n multi_cycle_instr = 1'b1;\n // vadd.vv\n if (funct3 == V_OPIVV)\n operand_select = PE_OPERAND_VS1;\n // vadd.vx\n else if (funct3 == V_OPIVX)\n operand_select = PE_OPERAND_SCALAR;\n else if (funct3 == V_OPMVV) // vredsum\n begin\n operand_select = PE_OPERAND_RIPPLE;\n fix_vd_addr = 1'b1;\n end\n end\n\n // vsub\n 6'b000010:\n begin\n pe_op = PE_ARITH_SUB;\n vec_reg_write = 1'b1;\n multi_cycle_instr = 1'b1;\n end\n\n // vmin\n 6'b000101:\n begin\n pe_op = PE_ARITH_SUB;\n output_mode = PE_OP_MODE_PASS_MIN;\n vec_reg_write = 1'b1;\n multi_cycle_instr = 1'b1;\n // Supports vmin.vv and vmin.vx\n if (funct3 == V_OPIVV)\n operand_select = PE_OPERAND_VS1;\n else if (funct3 == V_OPIVX)\n operand_select = PE_OPERAND_SCALAR;\n end\n\n // vmax, vredmax\n 6'b000111:\n begin\n pe_op = PE_ARITH_SUB;\n vec_reg_write = 1'b1;\n output_mode = PE_OP_MODE_PASS_MAX;\n multi_cycle_instr = 1'b1;\n // vredmax\n if (funct3 == V_OPMVV)\n begin\n fix_vd_addr = 1'b1;\n operand_select = PE_OPERAND_RIPPLE;\n end\n // Supports vmax.vv and vmax.vx\n else if (funct3 == V_OPIVV)\n operand_select = PE_OPERAND_VS1;\n else if (funct3 == V_OPIVX)\n operand_select = PE_OPERAND_SCALAR;\n end\n\n // vand\n 6'b001001:\n begin\n pe_op = PE_ARITH_AND;\n vec_reg_write = 1'b1;\n multi_cycle_instr = 1'b1;\n end\n\n // vor\n 6'b001010:\n begin\n pe_op = PE_ARITH_OR;\n vec_reg_write = 1'b1;\n multi_cycle_instr = 1'b1;\n end\n\n // vxor\n 6'b001011:\n begin\n pe_op = PE_ARITH_XOR;\n vec_reg_write = 1'b1;\n multi_cycle_instr = 1'b1;\n end\n\n // VWXUNARY0 (vmv.x.s)\n 6'b010000:\n begin\n apu_result_select = APU_RESULT_SRC_VS2_0;\n end\n\n // vmv.v\n 6'b010111:\n begin\n vec_reg_write = 1'b1;\n multi_cycle_instr = 1'b1;\n vd_data_src = VREG_WB_SRC_SCALAR;\n // vmv.v.i\n if (funct3 == V_OPIVI)\n operand_select = PE_OPERAND_IMMEDIATE;\n // vmv.v.x\n else if (funct3 == V_OPIVX)\n operand_select = PE_OPERAND_SCALAR;\n end\n\n // vsadd\n 6'b100001:\n begin\n pe_op = PE_ARITH_ADD;\n saturate_mode = PE_SAT;\n vec_reg_write = 1'b1;\n multi_cycle_instr = 1'b1;\n end\n\n // vsll/vmul\n 6'b100101:\n begin\n vec_reg_write = 1'b1;\n multi_cycle_instr = 1'b1;\n if (funct3 == V_OPIVV)\n begin\n pe_op = PE_ARITH_LSHIFT;\n operand_select = PE_OPERAND_VS1;\n end\n else if (funct3 == V_OPIVX)\n begin\n pe_op = PE_ARITH_LSHIFT;\n operand_select = PE_OPERAND_SCALAR;\n end\n else if (funct3 == V_OPIVI)\n begin\n pe_op = PE_ARITH_LSHIFT;\n operand_select = PE_OPERAND_IMMEDIATE;\n end\n else if (funct3 == V_OPMVV)\n begin\n pe_op = PE_ARITH_MUL;\n operand_select = PE_OPERAND_VS1;\n end\n\n end\n\n // vsmul\n 6'b100111:\n begin\n pe_op = PE_ARITH_MUL;\n saturate_mode = PE_SAT_UPPER;\n vec_reg_write = 1'b1;\n multi_cycle_instr = 1'b1;\n if (funct3 == V_OPIVV)\n operand_select = PE_OPERAND_VS1;\n else if (funct3 == V_OPIVX)\n operand_select = PE_OPERAND_SCALAR;\n end\n\n // vsrl\n 6'b101000:\n begin\n pe_op = PE_ARITH_RSHIFT_LOG;\n vec_reg_write = 1'b1;\n multi_cycle_instr = 1'b1;\n if (funct3 == V_OPIVV)\n operand_select = PE_OPERAND_VS1;\n else if (funct3 == V_OPIVX)\n operand_select = PE_OPERAND_SCALAR;\n else if (funct3 == V_OPIVI)\n begin\n unsigned_immediate = 1'b1;\n operand_select = PE_OPERAND_IMMEDIATE;\n end\n end\n\n // vsra\n 6'b101001:\n begin\n pe_op = PE_ARITH_RSHIFT_AR;\n vec_reg_write = 1'b1;\n multi_cycle_instr = 1'b1;\n if (funct3 == V_OPIVV)\n operand_select = PE_OPERAND_VS1;\n else if (funct3 == V_OPIVX)\n operand_select = PE_OPERAND_SCALAR;\n else if (funct3 == V_OPIVI)\n begin\n unsigned_immediate = 1'b1;\n operand_select = PE_OPERAND_IMMEDIATE;\n end\n end\n\n // vwredsum\n 6'b110001:\n begin\n pe_op = PE_ARITH_ADD;\n operand_select = PE_OPERAND_RIPPLE;\n vec_reg_write = 1'b1;\n fix_vd_addr = 1'b1;\n multi_cycle_instr = 1'b1;\n widening = 2'b01;\n wide_vs1 = 1'b1;\n end\n\n // vwmul\n 6'b111011:\n begin\n pe_op = PE_ARITH_MUL;\n vec_reg_write = 1'b1;\n multi_cycle_instr = 1'b1;\n widening = 2'b01;\n if (funct3 == V_OPMVV)\n operand_select = PE_OPERAND_VS1;\n else if (funct3 == V_OPMVX)\n operand_select = PE_OPERAND_SCALAR;\n end\n\n default:\n $error(\"Unsupported vector instruction\");\n\n endcase\n end\n end\n else\n $error(\"Unrecognised major opcode\");\n end\nend\n\nendmodule\n", "groundtruth": " else\n", "crossfile_context": ""}
{"task_id": "ava-core", "path": "ava-core/rtl/vector_lsu.sv", "left_context": "//\n// SPDX-License-Identifier: CERN-OHL-S-2.0+\n//\n// Copyright (C) 2020-21 Embecosm Limited <www.embecosm.com>\n// Contributed by:\n// Matthew Johns <mrj1g17@soton.ac.uk>\n// Byron Theobald <bt4g16@soton.ac.uk>\n//\n// This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY,\n// INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR\n// A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable\n// conditions.\n// Source location: https://github.com/AI-Vector-Accelerator\n//\n\nimport accelerator_pkg::*;\n\nmodule vector_lsu (\n input wire clk,\n input wire n_reset,\n\n // Vector CSR\n input wire [4:0] vl_i,\n input wire [1:0] vsew_i,\n input wire [1:0] vlmul_i,\n\n // VLSU Decoded Control\n input wire vlsu_en_i,\n input wire vlsu_load_i,\n input wire vlsu_store_i,\n input wire vlsu_strided_i,\n output logic vlsu_ready_o,\n output logic vlsu_done_o,\n\n // OBI Memory Master\n output logic data_req_o,\n input logic data_gnt_i,\n input logic data_rvalid_i,\n output logic [31:0] data_addr_o,\n output logic data_we_o,\n output logic [3:0] data_be_o,\n input logic [31:0] data_rdata_i,\n output logic [31:0] data_wdata_o,\n\n input logic [1:0] cycle_count_i,\n \n // Target Data\n input wire [31:0] op0_data_i, // Source (Load) / Destination (Store)\n input wire [31:0] op1_data_i, // Stride\n\n // Wide vector register port\n output logic [127:0] vs_wdata_o,\n input logic [127:0] vs_rdata_i,\n input logic [4:0] vr_addr_i,\n output logic [4:0] vs3_addr_o, // Redirected vector register address\n output logic vr_we_o\n);\n\n logic [31:0] vs_rdata_sel;\n logic [5:0] vsew_size;\n\n logic au_start;\n logic [3:0] au_be;\n logic [6:0] au_bc;\n logic [31:0] au_addr;\n logic au_valid, au_ready;\n logic [6:0] vd_offset;\n\n temporary_reg tr (\n .clk_i (clk), \n .n_rst_i (n_reset),\n .byte_enable_valid (data_req_o),\n .read_data_valid (data_rvalid_i),\n .clear_register (au_start),\n .memory_read_i (data_rdata_i),\n .byte_enable_i (au_be),\n .byte_select_i (vd_offset + {vr_addr_i[1:0], 2'b00}),\n .wide_vd_o (vs_wdata_o)\n );\n\n always_comb begin\n\t\t data_wdata_o = 'd0;\n case(vsew_i)\n 2'd0 : begin\n data_wdata_o = {vs_rdata_i[103:96], vs_rdata_i[71:64], vs_rdata_i[39:32], vs_rdata_i[7:0]};\n end\n 2'd1 : begin\n", "right_context": " 2'd2 : data_wdata_o = vs_rdata_i[95:64];\n 2'd3 : data_wdata_o = vs_rdata_i[127:96]; \n endcase\n end\n endcase\n end\n\n logic [1:0] ib_select; // Low 2 bits of initial address\n logic [3:0] be_gen;\n\n logic [31:0] next_el_pre, next_el_addr;\n logic [31:0] cycle_addr, stride;\n logic [6:0] cycle_bytes;\n\n typedef enum {RESET, LOAD_FIRST, LOAD_CYCLE, LOAD_WAIT, LOAD_FINAL, STORE_CYCLE, STORE_WAIT, STORE_FINAL} be_state;\n be_state current_state, next_state;\n\n logic signed [6:0] byte_track, byte_track_next;\n logic cycle_load, cycle_addr_inc, store_cycles_inc;\n\n logic [2:0] store_cycle_bytes;\n logic [3:0] store_cycle_be;\n logic [2:0] store_cycles, store_cycles_cnt;\n\n assign stride = vlsu_strided_i ? op1_data_i : (32'd1 << vsew_i);\n assign data_addr_o = vlsu_store_i ? ({cycle_addr[31:2], 2'd0} + (store_cycles_cnt << 2)) : {cycle_addr[31:2], 2'd0};\n assign au_be = be_gen;\n assign vd_offset = (vl_i << vsew_i) - byte_track;\n\n always_comb begin\n if(byte_track >= 4)\n store_cycle_be = 4'b1111;\n else if(byte_track >= 3)\n store_cycle_be = 4'b0111;\n else if(byte_track >= 2)\n store_cycle_be = 4'b0011;\n else\n store_cycle_be = 4'b0001;\n\n data_be_o = vlsu_store_i ? store_cycle_be : 4'b1111;\n end \n\n always_comb begin\n if(au_start)\n byte_track_next = {2'd0, vl_i} << vsew_i; // Bytes dependent on element size\n else if(cycle_addr_inc)\n byte_track_next = (byte_track >= cycle_bytes) ? (byte_track - cycle_bytes) : 7'd0;\n else if(store_cycles_inc)\n byte_track_next = byte_track - store_cycle_bytes;\n else \n byte_track_next = byte_track;\n end \n\n always_ff @(posedge clk, negedge n_reset) begin\n if(~n_reset)\n byte_track <= 7'd0;\n else \n byte_track <= byte_track_next;\n end\n\n always_ff @(posedge clk, negedge n_reset) begin\n if(~n_reset)\n cycle_addr <= 32'd0;\n else if(au_start)\n cycle_addr <= op0_data_i;\n else if(cycle_addr_inc) \n cycle_addr <= next_el_addr;\n else \n cycle_addr <= cycle_addr;\n end\n\n assign store_cycles = (vl_i >> 2-vsew_i)+1;\n assign vs3_addr_o = vr_addr_i + store_cycles_cnt;\n always_ff @(posedge clk, negedge n_reset) begin\n if(~n_reset)\n store_cycles_cnt <= 2'd0;\n else if(au_start)\n store_cycles_cnt <= 2'd0;\n else if (store_cycles_inc)\n store_cycles_cnt <= store_cycles_cnt + 2'd1;\n end\n\n always_ff @(posedge clk, negedge n_reset) begin\n if(~n_reset)\n current_state <= RESET;\n else\n current_state <= next_state;\n end\n\n always_comb begin\n be_gen = 4'b0000;\n next_el_pre = '0;\n\t\t cycle_bytes = '0;\n\t\t ib_select = '0;\n\t\t next_el_addr = '0;\n case(vsew_i)\n 2'b00 : begin // 8 Bit\n ib_select = cycle_addr[1:0];\n\n if(stride > 32'd1) begin\n be_gen[ib_select] = 1'b1;\n\n // Where is our next byte?\n next_el_pre = cycle_addr + stride;\n if(next_el_pre[31:2] == cycle_addr[31:2] && byte_track > 1) begin\n be_gen[next_el_pre[1:0]] = 1'b1;\n next_el_addr = next_el_pre + stride; // Stride by second element\n end else begin\n next_el_addr = next_el_pre;\n end\n\n // Calculate the number of bytes for LOAD_CYCLE\n cycle_bytes = {5'd0, be_gen[3]} + {5'd0, be_gen[2]} + {5'd0, be_gen[1]} + {5'd0, be_gen[0]};\n end else if(stride == 1) begin\n be_gen[0] = (ib_select == 32'd0) ? 1 : 0;\n be_gen[1] = (ib_select == 1 || byte_track > 1) ? 1'b1 : 1'b0;\n be_gen[2] = (ib_select == 2 || byte_track > 2) ? 1'b1 : 1'b0;\n be_gen[3] = (ib_select == 3 || byte_track > 3) ? 1'b1 : 1'b0;\n next_el_addr = {cycle_addr[31:2], 2'b0} + 32'd4;\n\n // Calculate the number of bytes for LOAD_CYCLE\n cycle_bytes = {5'd0, be_gen[3]} + {5'd0, be_gen[2]} + {5'd0, be_gen[1]} + {5'd0, be_gen[0]}; \n end else if(stride == 32'd0) begin\n be_gen[ib_select] = 1'b1;\n cycle_bytes = {2'b0, vl_i}; // Read all bytes in 1 LOAD_CYCLE\n end\n end\n 2'b01 : begin // 16 Bit\n ib_select = {cycle_addr[1], 1'b0}; // Force alignment byte 0 or 2\n\n if(stride > 32'd2) begin // Always 1 element\n // Always set 2 bytes\n be_gen[ib_select] = 1'b1; \n be_gen[ib_select+1] = 1'b1;\n next_el_addr = {cycle_addr[31:1], 1'b0} + {stride[31:1], 1'b0};\n \n // Calculate the number of bytes for LOAD_CYCLE\n cycle_bytes = {5'd0, be_gen[3]} + {5'd0, be_gen[2]} + {5'd0, be_gen[1]} + {5'd0, be_gen[0]};\n end else if (stride == 32'd2) begin // Up to 2 Elements\n be_gen[1:0] = (ib_select == 0) ? 2'b11 : 2'b00;\n be_gen[3:2] = (ib_select == 2 || byte_track > 2) ? 2'b11 : 2'b00;\n next_el_addr = {cycle_addr[31:2], 2'b0} + 32'd4;\n \n // Calculate the number of bytes for LOAD_CYCLE\n cycle_bytes = {5'd0, be_gen[3]} + {5'd0, be_gen[2]} + {5'd0, be_gen[1]} + {5'd0, be_gen[0]};\n end else if (stride == 32'd0) begin \n be_gen[ib_select] = 1'b1;\n be_gen[ib_select+1] = 1'b1;\n cycle_bytes = {1'b0, vl_i, 1'b0}; // Read all bytes in 1 LOAD_CYCLE\n end\n end\n 2'b10 : begin // 32 Bit\n ib_select = 2'd0; // Force alignment to byte 0\n\n if(stride >= 32'd4) begin // Always 1 element\n be_gen = 4'b1111;\n next_el_addr = {cycle_addr[31:2], 2'b0} + {stride[31:2], 2'b0}; // stride is always a multiple of 4\n \n // Calculate the number of bytes for LOAD_CYCLE\n cycle_bytes = {5'd0, be_gen[3]} + {5'd0, be_gen[2]} + {5'd0, be_gen[1]} + {5'd0, be_gen[0]};\n end else if(stride == 32'd0) begin\n be_gen = 4'b1111;\n cycle_bytes = {1'b0, vl_i, 1'b0}; // Read all bytes in 1 LOAD_CYCLE\n end\n end\n default : $error(\"Invalid VSEW\"); \n endcase\n end\n\n always_comb begin\n cycle_load = 1'b0;\n data_req_o = 1'b0;\n data_we_o = 1'b0;\n au_start = 1'b0;\n au_ready = 1'b0;\n vlsu_done_o = 1'b0;\n vlsu_ready_o = 1'b0; \n cycle_addr_inc = 1'b0;\n store_cycles_inc = 1'b0;\n vr_we_o = 1'b0;\n case(current_state)\n RESET: begin\n vlsu_ready_o = 1'b1; \n if(vlsu_load_i) begin\n au_start = 1'b1;\n next_state = LOAD_FIRST;\n end else if (vlsu_store_i) begin\n au_start = 1'b1;\n next_state = STORE_CYCLE;\n end else begin\n next_state = RESET;\n end\n end\n LOAD_FIRST: begin\n next_state = LOAD_CYCLE;\n end\n LOAD_CYCLE: begin\n if(byte_track_next == 0) begin\n next_state = LOAD_WAIT;\n end else begin\n data_req_o = 1'b1;\n cycle_load = 1'b1;\n next_state = LOAD_WAIT;\n end\n end\n LOAD_WAIT: begin\n if(data_rvalid_i) begin\n cycle_addr_inc = 1'b1;\n next_state = LOAD_CYCLE;\n end else if(byte_track_next == 0)\n next_state = LOAD_FINAL;\n else\n next_state = LOAD_WAIT;\n end\n LOAD_FINAL: begin\n next_state = RESET;\n vlsu_done_o = 1'b1;\n vr_we_o = 1'b1;\n end\n STORE_CYCLE: begin\n data_req_o = 1'b1;\n data_we_o = 1'b1;\n next_state = STORE_WAIT;\n end\n STORE_WAIT: begin\n if(data_rvalid_i) begin\n if(store_cycles_cnt == store_cycles) begin\n next_state = STORE_FINAL;\n end else begin \n store_cycles_inc = 1'b1;\n next_state = STORE_CYCLE;\n end\n end else begin\n next_state = STORE_WAIT;\n end\n end\n STORE_FINAL: begin\n vlsu_done_o = 1'b1;\n next_state = RESET;\n end\n endcase\n end\n\n\nendmodule\n", "groundtruth": " case(vs3_addr_o[0])\n 1'd0 : data_wdata_o = {vs_rdata_i[47:32], vs_rdata_i[15:0]};\n 1'd1 : data_wdata_o = {vs_rdata_i[111:96], vs_rdata_i[79:64]};\n endcase\n end\n", "crossfile_context": ""}
{"task_id": "ava-core", "path": "ava-core/rtl/vector_registers.sv", "left_context": "//\n// SPDX-License-Identifier: CERN-OHL-S-2.0+\n//\n// Copyright (C) 2020-21 Embecosm Limited <www.embecosm.com>\n// Contributed by:\n// Matthew Johns <mrj1g17@soton.ac.uk>\n// Byron Theobald <bt4g16@soton.ac.uk>\n//\n// This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY,\n// INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR\n// A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable\n// conditions.\n// Source location: https://github.com/AI-Vector-Accelerator\n//\n\nmodule vector_registers (\n output logic [127:0] vs1_data,\n output logic [127:0] vs2_data,\n output logic [127:0] vs3_data,\n input wire [127:0] vd_data,\n input wire [4:0] vs1_addr,\n input wire [4:0] vs2_addr,\n input wire [4:0] vd_addr, // Generally this doubles up as vs3 address\n input wire [1:0] vsew,\n input wire [1:0] vlmul,\n input wire [1:0] elements_to_write,\n input wire clk,\n input wire n_reset,\n input wire write,\n input wire widening_op,\n input wire wide_vs1,\n input logic load_operation\n);\n\nlocalparam VLEN = 32;\n\nlogic [VLEN-1:0] vregs [31:0];\n\n// Addresses for each of the read ports for each operand.\n// Each operand may require up to four read ports.\n// Reason: need 4 elements per operand per cycle to maintain throughput in\n// the 4 PEs. For 8b elements, 4 elements are stored in a single register;\n// however with 32b elements they will be spread across 4 registers (when\n// LMUL > 1). Otherwise SIMD throughput would be tiny.\n// These addresses will be consecutive for each operand. Just want a tidy\n// efficient way of producing them without an adder for each one.\nlogic [4:0] vs1_addr0;\nlogic [4:0] vs1_addr1;\nlogic [4:0] vs1_addr2;\nlogic [4:0] vs1_addr3;\n\nlogic [4:0] vs2_addr0;\nlogic [4:0] vs2_addr1;\nlogic [4:0] vs2_addr2;\nlogic [4:0] vs2_addr3;\n\nlogic [4:0] vd_addr0;\nlogic [4:0] vd_addr1;\nlogic [4:0] vd_addr2;\nlogic [4:0] vd_addr3;\n\n// Structured data to write back to registers\nlogic [VLEN-1:0] vd_wr_data0;\nlogic [VLEN-1:0] vd_wr_data1;\nlogic [VLEN-1:0] vd_wr_data2;\nlogic [VLEN-1:0] vd_wr_data3;\n\n// Unstructured data read from registers\nlogic [VLEN-1:0] vs1_rd_data0;\nlogic [VLEN-1:0] vs1_rd_data1;\nlogic [VLEN-1:0] vs1_rd_data2;\nlogic [VLEN-1:0] vs1_rd_data3;\n\nlogic [VLEN-1:0] vs2_rd_data0;\nlogic [VLEN-1:0] vs2_rd_data1;\nlogic [VLEN-1:0] vs2_rd_data2;\nlogic [VLEN-1:0] vs2_rd_data3;\n\nlogic [VLEN-1:0] vs3_rd_data0;\nlogic [VLEN-1:0] vs3_rd_data1;\nlogic [VLEN-1:0] vs3_rd_data2;\nlogic [VLEN-1:0] vs3_rd_data3;\n\n// Write-enable signals for each write port. Could get away with making wr_en1\n// only 2 bits, as will only write 16b elements. Similarly could make wr_en2 and\n// wr_en3 single bits. But I don't know what that would synthesise to if I did\nlogic [3:0] wr_en0;\nlogic [3:0] wr_en1;\nlogic [3:0] wr_en2;\nlogic [3:0] wr_en3;\n\n// Effective vsew can be modified for widening ops\nlogic [1:0] eff_vsew;\n\n\n// REGISTER WRITE\nalways_ff @(posedge clk, negedge n_reset)\n if (~n_reset)\n vregs <= '{VLEN{'0}};\n else\n begin\n // Don't want to write to v0 (reserved for vector mask)\n if (write & (vd_addr != '0))\n begin\n if (wr_en0[0])\n vregs[vd_addr0][7:0] <= vd_wr_data0[7:0];\n if (wr_en0[1])\n vregs[vd_addr0][15:8] <= vd_wr_data0[15:8];\n if (wr_en0[2])\n vregs[vd_addr0][23:16] <= vd_wr_data0[23:16];\n if (wr_en0[3])\n vregs[vd_addr0][31:24] <= vd_wr_data0[31:24];\n\n if (wr_en1[0])\n vregs[vd_addr1][7:0] <= vd_wr_data1[7:0];\n if (wr_en1[1])\n vregs[vd_addr1][15:8] <= vd_wr_data1[15:8];\n if (wr_en1[2])\n vregs[vd_addr1][23:16] <= vd_wr_data1[23:16];\n if (wr_en1[3])\n vregs[vd_addr1][31:24] <= vd_wr_data1[31:24];\n\n if (wr_en2[0])\n vregs[vd_addr2][7:0] <= vd_wr_data2[7:0];\n if (wr_en2[1])\n vregs[vd_addr2][15:8] <= vd_wr_data2[15:8];\n if (wr_en2[2])\n vregs[vd_addr2][23:16] <= vd_wr_data2[23:16];\n if (wr_en2[3])\n vregs[vd_addr2][31:24] <= vd_wr_data2[31:24];\n\n if (wr_en3[0])\n vregs[vd_addr3][7:0] <= vd_wr_data3[7:0];\n if (wr_en3[1])\n vregs[vd_addr3][15:8] <= vd_wr_data3[15:8];\n if (wr_en3[2])\n vregs[vd_addr3][23:16] <= vd_wr_data3[23:16];\n if (wr_en3[3])\n vregs[vd_addr3][31:24] <= vd_wr_data3[31:24];\n end\n end\n\n\n// REGISTER READ\nassign vs1_rd_data0 = vregs[vs1_addr0];\nassign vs1_rd_data1 = vregs[vs1_addr1];\nassign vs1_rd_data2 = vregs[vs1_addr2];\nassign vs1_rd_data3 = vregs[vs1_addr3];\nassign vs2_rd_data0 = vregs[vs2_addr0];\nassign vs2_rd_data1 = vregs[vs2_addr1];\nassign vs2_rd_data2 = vregs[vs2_addr2];\nassign vs2_rd_data3 = vregs[vs2_addr3];\nassign vs3_rd_data0 = vregs[vd_addr0];\nassign vs3_rd_data1 = vregs[vd_addr1];\nassign vs3_rd_data2 = vregs[vd_addr2];\nassign vs3_rd_data3 = vregs[vd_addr3];\n\n\n// ADDRESS CALCULATION\nalways_comb\nbegin\n // Logic behind this: Need 4 consecutive addresses, but don't want to just\n // have adders for each one to increment the address.\n // This is only useful for LMUL > 1, as for LMUL = 1, only one register will\n // be read anyway. If LMUL > 1, base addresses will always be even. So can\n // add one to it by making last bit 1. Add 2 by making second-last bit 1.\n // Add 3 by doing both.\n // If LMUL = 2 then adding 2 that way won't work, but also it won't be used\n // because only the first 2 registers will be used.\n vs1_addr0 = vs1_addr;\n vs1_addr1 = {vs1_addr[4:1], 1'b1};\n vs1_addr2 = {vs1_addr[4:2], 1'b1, vs1_addr[0]};\n vs1_addr3 = {vs1_addr[4:2], 2'b11};\n\n vs2_addr0 = vs2_addr;\n vs2_addr1 = {vs2_addr[4:1], 1'b1};\n vs2_addr2 = {vs2_addr[4:2], 1'b1, vs2_addr[0]};\n vs2_addr3 = {vs2_addr[4:2], 2'b11};\n\n vd_addr0 = vd_addr;\n vd_addr1 = {vd_addr[4:1], 1'b1};\n vd_addr2 = {vd_addr[4:2], 1'b1, vd_addr[0]};\n vd_addr3 = {vd_addr[4:2], 2'b11};\nend\n\n\n// WRITE-ENABLE GENERATION\nalways_comb\nbegin\n // Note: can ignore LMUL in below cases as LMUL will restrict the max of VL,\n // which will prevent from writing to higher registers than LMUL wants\n if (widening_op)\n case (vsew)\n 2'd0: // 8b -> 16b\n eff_vsew = 2'd1;\n 2'd1: // 16b -> 32b\n eff_vsew = 2'd2;\n default:\n begin\n // Shouldn't come to this\n eff_vsew = vsew;\n $error(\"Widening ops with VSEW=32b are not supported\");\n end\n endcase\n else\n eff_vsew = vsew;\n\n wr_en0 = '0;\n wr_en1 = '0;\n wr_en2 = '0;\n wr_en3 = '0;\n\n if(load_operation) begin\n case (vlmul) \n 2'd0: begin\n case(vd_addr[1:0])\n 2'b00 : wr_en0 = 4'b1111;\n 2'b01 : wr_en1 = 4'b1111;\n 2'b10 : wr_en2 = 4'b1111; \n 2'b11 : wr_en3 = 4'b1111;\n endcase\n end\n 2'd1: begin\n if(vd_addr[1] == 1'b0) begin\n wr_en0 = 4'b1111;\n wr_en1 = 4'b1111;\n end else begin\n wr_en2 = 4'b1111; \n wr_en3 = 4'b1111;\n end\n end\n 2'd2: begin\n wr_en0 = 4'b1111;\n wr_en1 = 4'b1111;\n wr_en2 = 4'b1111;\n wr_en3 = 4'b1111;\n end\n endcase\n end else begin\n case (eff_vsew)\n 2'd0: // 8b\n begin\n // Only interested in first write port\n case (elements_to_write)\n 2'd0: // Write all elements\n wr_en0 = 4'b1111;\n 2'd1:\n wr_en0 = 4'b0001;\n 2'd2:\n wr_en0 = 4'b0011;\n 2'd3:\n wr_en0 = 4'b0111;\n endcase\n end\n 2'd1: // 16b\n begin\n // Only interested in first 2 write ports\n case (elements_to_write)\n 2'd0: // Write all elements\n begin\n wr_en0 = 4'b1111;\n wr_en1 = 4'b1111;\n end\n 2'd1:\n begin\n wr_en0 = 4'b0011;\n end\n 2'd2:\n begin\n wr_en0 = 4'b1111;\n end\n 4'd3:\n begin\n wr_en0 = 4'b1111;\n wr_en1 = 4'b0011;\n end\n endcase\n end\n 2'd2: // 32b\n begin\n // Need to consider all write ports\n // wr_en0 always enabled, otherwise would be writing no elements\n wr_en0 = 4'b1111;\n case (elements_to_write)\n 2'd0: // Write all elements\n begin\n wr_en1 = 4'b1111;\n wr_en2 = 4'b1111;\n wr_en3 = 4'b1111;\n", "right_context": " begin\n wr_en1 = 4'b1111;\n wr_en2 = 4'b1111;\n end\n endcase\n end\n endcase\n end\nend\n\n\n// OUTPUT DATA MAP\n// TODO: consider need for sign extension for VSEW<32b\n// Have to pad the extra space when using smaller elements to give correct\n// alignment into the PEs\nalways_comb\nbegin\n case (vsew)\n 2'd0: // 8b\n begin\n // For vwredsum (theoretically other mixed-width instructions) the B\n // operand (which comes from vs1[0]) is 2*VSEW bits. So treat it as\n // for wider ones.\n if (wide_vs1)\n vs1_data = {\n {16{1'b0}},\n vs1_rd_data1[31:16],\n {16{1'b0}},\n vs1_rd_data1[15:0],\n {16{1'b0}},\n vs1_rd_data0[31:16],\n {16{1'b0}},\n vs1_rd_data0[15:0]\n };\n else\n vs1_data = {\n {24{1'b0}},\n vs1_rd_data0[31:24],\n {24{1'b0}},\n vs1_rd_data0[23:16],\n {24{1'b0}},\n vs1_rd_data0[15:8],\n {24{1'b0}},\n vs1_rd_data0[7:0]\n };\n\n vs2_data = {\n {24{1'b0}},\n vs2_rd_data0[31:24],\n {24{1'b0}},\n vs2_rd_data0[23:16],\n {24{1'b0}},\n vs2_rd_data0[15:8],\n {24{1'b0}},\n vs2_rd_data0[7:0]\n };\n // For widening ops such as MACC, the third operand needs to be the\n // widened width rather than VSEW. Copy the mapping of vs3 from the\n // next largest element. Does not apply to VSEW=32b as widening ops\n // are not supported.\n if (widening_op)\n vs3_data = {\n {16{1'b0}},\n vs3_rd_data1[31:16],\n {16{1'b0}},\n vs3_rd_data1[15:0],\n {16{1'b0}},\n vs3_rd_data0[31:16],\n {16{1'b0}},\n vs3_rd_data0[15:0]\n };\n else\n vs3_data = {\n {24{1'b0}},\n vs3_rd_data0[31:24],\n {24{1'b0}},\n vs3_rd_data0[23:16],\n {24{1'b0}},\n vs3_rd_data0[15:8],\n {24{1'b0}},\n vs3_rd_data0[7:0]\n };\n end\n 2'd1: // 16b\n begin\n if (wide_vs1)\n vs1_data = {\n vs1_rd_data3,\n vs1_rd_data2,\n vs1_rd_data1,\n vs1_rd_data0\n };\n else\n vs1_data = {\n {16{1'b0}},\n vs1_rd_data1[31:16],\n {16{1'b0}},\n vs1_rd_data1[15:0],\n {16{1'b0}},\n vs1_rd_data0[31:16],\n {16{1'b0}},\n vs1_rd_data0[15:0]\n };\n\n vs2_data = {\n {16{1'b0}},\n vs2_rd_data1[31:16],\n {16{1'b0}},\n vs2_rd_data1[15:0],\n {16{1'b0}},\n vs2_rd_data0[31:16],\n {16{1'b0}},\n vs2_rd_data0[15:0]\n };\n if (widening_op)\n vs3_data = {\n vs3_rd_data3,\n vs3_rd_data2,\n vs3_rd_data1,\n vs3_rd_data0\n };\n else\n vs3_data = {\n {16{1'b0}},\n vs3_rd_data1[31:16],\n {16{1'b0}},\n vs3_rd_data1[15:0],\n {16{1'b0}},\n vs3_rd_data0[31:16],\n {16{1'b0}},\n vs3_rd_data0[15:0]\n };\n end\n 2'd2: // 32b\n begin\n vs1_data = {\n vs1_rd_data3,\n vs1_rd_data2,\n vs1_rd_data1,\n vs1_rd_data0\n };\n vs2_data = {\n vs2_rd_data3,\n vs2_rd_data2,\n vs2_rd_data1,\n vs2_rd_data0\n };\n vs3_data = {\n vs3_rd_data3,\n vs3_rd_data2,\n vs3_rd_data1,\n vs3_rd_data0\n };\n end\n default:\n begin\n vs1_data = '0;\n vs2_data = '0;\n vs3_data = '0;\n end\n endcase\nend\n\n\n// INPUT DATA MAP\n// Take wide combined result data from PEs and remove padding\nalways_comb\nbegin\n vd_wr_data3 = '0;\n vd_wr_data2 = '0;\n vd_wr_data1 = '0;\n vd_wr_data0 = '0;\n\n if(load_operation) begin\n case (vlmul) \n 2'd0: begin\n case(vd_addr[1:0])\n 2'b00 : vd_wr_data0 = vd_data[31:0]; \n 2'b01 : vd_wr_data1 = vd_data[63:32]; \n 2'b10 : vd_wr_data2 = vd_data[95:64]; \n 2'b11 : vd_wr_data3 = vd_data[127:96]; \n endcase\n end\n 2'd1: begin\n if(vd_addr[1] == 1'b0) begin\n vd_wr_data1 = vd_data[63:32];\n vd_wr_data0 = vd_data[31:0];\n end else begin\n vd_wr_data3 = vd_data[127:96];\n vd_wr_data2 = vd_data[95:64];\n end\n end\n 2'd2: begin\n vd_wr_data3 = vd_data[127:96];\n vd_wr_data2 = vd_data[95:64];\n vd_wr_data1 = vd_data[63:32];\n vd_wr_data0 = vd_data[31:0];\n end\n endcase\n end else begin\n case (eff_vsew)\n 2'd0: // 8b\n vd_wr_data0 = {\n vd_data[103:96],\n vd_data[71:64],\n vd_data[39:32],\n vd_data[7:0]\n };\n 2'd1: // 16b\n begin\n vd_wr_data1 = {\n vd_data[111:96],\n vd_data[79:64]\n };\n vd_wr_data0 = {\n vd_data[47:32],\n vd_data[15:0]\n };\n end\n 2'd2: // 32b\n begin\n vd_wr_data3 = vd_data[127:96];\n vd_wr_data2 = vd_data[95:64];\n vd_wr_data1 = vd_data[63:32];\n vd_wr_data0 = vd_data[31:0];\n end\n endcase\n end\nend\n\nendmodule", "groundtruth": " end\n // 2'd1: // Not needed, just wr_en0 = '1\n 2'd2:\n begin\n", "crossfile_context": ""}
{"task_id": "ava-core", "path": "ava-core/rtl/vw_sign_ext.sv", "left_context": "//\n// SPDX-License-Identifier: CERN-OHL-S-2.0+\n//\n// Copyright (C) 2020-21 Embecosm Limited <www.embecosm.com>\n// Contributed by:\n// Matthew Johns <mrj1g17@soton.ac.uk>\n// Byron Theobald <bt4g16@soton.ac.uk>\n//\n// This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY,\n// INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR\n// A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable\n// conditions.\n// Source location: https://github.com/AI-Vector-Accelerator\n//\n\n// Variable width sign extension module. Used to sign-extend 3 PE inputs for\n// signed/widening multiplication\n\nmodule vw_sign_ext (\n output logic [31:0] sign_ext_a,\n output logic [31:0] sign_ext_b,\n output logic [31:0] sign_ext_c,\n input wire [31:0] a,\n input wire [31:0] b,\n input wire [31:0] c,\n input wire [1:0] widening, // 2'd1 for 2*widening, 2'd2 for quad widening\n input wire [1:0] vsew,\n input wire wide_b\n);\n\nalways_comb begin\n\t sign_ext_a = '0;\n\t sign_ext_b = '0;\n\t sign_ext_c = '0;\n case(vsew)\n", "right_context": " // operand for each PE is 2*VSEW bits because it is an intermediate\n // result. So treat it as if vsew was twice as large\n if (wide_b)\n sign_ext_b = {{16{b[15]}}, b[15:0]};\n else\n sign_ext_b = {{24{b[7]}}, b[7:0]};\n\n if (widening[0])\n sign_ext_c = {{16{c[15]}}, c[15:0]};\n else if (widening[1])\n sign_ext_c = c;\n else\n sign_ext_c = {{24{c[7]}}, c[7:0]};\n end\n 2'd1: // 16b\n begin\n sign_ext_a = {{16{a[15]}}, a[15:0]};\n\n if (wide_b)\n sign_ext_b = b;\n else\n sign_ext_b = {{16{b[15]}}, b[15:0]};\n\n if (widening[0])\n sign_ext_c = c;\n else if (widening[1])\n $error(\"Trying to quad-widen 16b elements!\");\n else\n sign_ext_c = {{16{c[15]}}, c[15:0]};\n end\n default:\n begin\n sign_ext_a = a;\n sign_ext_b = b;\n sign_ext_c = c;\n end\n endcase\nend\n\t \nendmodule", "groundtruth": " 2'd0: // 8b\n begin\n sign_ext_a = {{24{a[7]}}, a[7:0]};\n", "crossfile_context": ""}
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