Datasets:
File size: 39,619 Bytes
d6720f3 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 | {"file": "tiny-tpu-old/src/accumulator.sv", "target_type": "module_declaration", "cursor_line": 23, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " for (i = 0; i < 2; i = i + 1) begin\n"}
{"file": "tiny-tpu-old/src/control_unit.sv", "target_type": "case_statement", "cursor_line": 105, "target_nlines": 1, "node_depth": 31, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement", "case_item", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " state <= FETCH;\n"}
{"file": "tiny-tpu-old/src/dma.sv", "target_type": "module_declaration", "cursor_line": 14, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " output wire [3:0] dma_address\n);\n\n // Combinational logic for outputs\n"}
{"file": "tiny-tpu-old/src/input_setup.sv", "target_type": "module_declaration", "cursor_line": 32, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " counter <= 3'b0;\n a_in1 <= 8'b0;\n a_in2 <= 8'b0;\n state <= IDLE; \n"}
{"file": "tiny-tpu-old/src/mmu.sv", "target_type": "module_declaration", "cursor_line": 30, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " .load_weight(load_weight),\n .valid(valid),\n .a_in(a_in1),\n"}
{"file": "tiny-tpu-old/src/processing_element.sv", "target_type": "module_declaration", "cursor_line": 13, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n output reg [7:0] a_out, // Output A to right neighbor\n output reg [7:0] acc_out // Accumulated value to the PE below\n);\n"}
{"file": "tiny-tpu-old/src/tpu.sv", "target_type": "module_declaration", "cursor_line": 151, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " .reset(reset),\n"}
{"file": "tiny-tpu-old/src/tt_um_tpu.sv", "target_type": "module_declaration", "cursor_line": 17, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input wire reset // rst_n - low to reset --> // TODO: rename back to rst_n!\n"}
{"file": "tiny-tpu-old/src/unified_buffer.sv", "target_type": "module_declaration", "cursor_line": 18, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input wire store, // flag for storing data from accumulators to unified buffer\n input wire ext, // flag for output to host computer\n\n input wire [7:0] acc1_mem_0,\n"}
{"file": "tiny-tpu-old/src/weight_memory.sv", "target_type": "module_declaration", "cursor_line": 29, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " weight4 <= 8'b0;\n\n end else if (fetch_w) begin // READ data into weight memory \n memory[dma_address] <= ui_in;\n"}
{"file": "tiny-tpu-old/test/dump_acc.sv", "target_type": "module_declaration", "cursor_line": 1, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "module dump();\n initial begin\n $dumpfile (\"acc.vcd\");\n $dumpvars (0, accumulator);\n"}
{"file": "tiny-tpu-old/test/dump_dma.sv", "target_type": "module_declaration", "cursor_line": 8, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " $dumpvars(0, dma.test_storage[2]);\n $dumpvars(0, dma.test_storage[3]);\n\n $dumpvars(0, dma.test_storage[4]);\n"}
{"file": "tiny-tpu-old/test/dump_is.sv", "target_type": "module_declaration", "cursor_line": 5, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " #1;\n end\nendmodule\n"}
{"file": "tiny-tpu-old/test/dump_mmu.sv", "target_type": "module_declaration", "cursor_line": 1, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "module dump();\n initial begin\n $dumpfile (\"mmu.vcd\");\n"}
{"file": "tiny-tpu-old/test/dump_tpu.sv", "target_type": "module_declaration", "cursor_line": 4, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " $dumpvars (0, tpu);\n #1;\n end\nendmodule\n"}
{"file": "tiny-tpu-old/test/dump_tt_um_tpu.sv", "target_type": "module_declaration", "cursor_line": 2, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " initial begin\n $dumpfile (\"tt_um_tpu.vcd\");\n $dumpvars (0, tt_um_tpu);\n #1;\n end\n"}
{"file": "tiny-tpu-old/test/dump_weight_memory.sv", "target_type": "module_declaration", "cursor_line": 10, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " $dumpvars (0, weight_memory.memory[3]);\n"}
{"file": "usb20dev/rtl/usb.sv", "target_type": "module_declaration", "cursor_line": 33, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "endmodule : usb\n"}
{"file": "usb20dev/rtl/usb_crc16.sv", "target_type": "module_declaration", "cursor_line": 74, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\nalways_ff @(posedge clk or posedge rst)\nbegin\n"}
{"file": "usb20dev/rtl/usb_crc5.sv", "target_type": "module_declaration", "cursor_line": 26, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "//-----------------------------------------------------------------------------\n// Data serializer\n//-----------------------------------------------------------------------------\nbus8_t dbyte;\nlogic dbit;\n"}
{"file": "usb20dev/rtl/usb_fe_if.sv", "target_type": "simple_identifier", "cursor_line": 22, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "interface_declaration", "interface_item", "modport_declaration", "modport_item", "modport_ports_declaration", "modport_simple_ports_declaration", "modport_simple_port", "port_identifier", "simple_identifier"], "target": " output tx_oen,\n"}
{"file": "usb20dev/rtl/usb_pkg.sv", "target_type": "primary_literal", "cursor_line": 15, "target_nlines": 1, "node_depth": 10, "node_path": ["source_file", "package_declaration", "package_or_generate_item_declaration", "data_declaration", "type_declaration", "data_type", "packed_dimension", "constant_range", "constant_expression", "constant_primary", "primary_literal"], "target": "typedef logic [31:0] bus32_t;\n"}
{"file": "usb20dev/rtl/usb_sie.sv", "target_type": "module_declaration", "cursor_line": 44, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " .bus_reset (sie_bus.reset) // o: Bus reset active\n);\n"}
{"file": "usb20dev/rtl/usb_sie_if.sv", "target_type": "simple_identifier", "cursor_line": 72, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "interface_declaration", "interface_item", "modport_declaration", "modport_item", "modport_ports_declaration", "modport_simple_ports_declaration", "modport_simple_port", "port_identifier", "simple_identifier"], "target": " output rx_error\n"}
{"file": "usb20dev/rtl/usb_sie_rx.sv", "target_type": "case_statement", "cursor_line": 298, "target_nlines": 3, "node_depth": 22, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "\n STRIP_EOP_S : begin\n data_valid = 'b0;\n"}
{"file": "usb20dev/rtl/usb_sie_tx.sv", "target_type": "module_declaration", "cursor_line": 41, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " TX_DATA_WAIT_S,\n XXX_S = 'x\n"}
{"file": "usb20dev/verif/helpers/usb_host_beh.sv", "target_type": "module_declaration", "cursor_line": 18, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "// USB FS 12.000 Mb/s +-0.25% (+-208ps)\nlocalparam USB_PERIOD = 83333; // ps\nlocalparam USB_JIT = 100; // ps\n`define USB_PERIOD_DEL ((USB_PERIOD + ($urandom_range(0, USB_JIT*2) - USB_JIT))/1000.0)\n"}
{"file": "usb20dev/verif/helpers/usb_sie_vip.sv", "target_type": "module_declaration", "cursor_line": 41, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " sie_bus.tx_data = data[i];\n sie_bus.tx_valid = 1'b1;\n"}
{"file": "usb20dev/verif/testbenches/crc/tb.sv", "target_type": "simple_identifier", "cursor_line": 22, "target_nlines": 1, "node_depth": 4, "node_path": ["source_file", "package_or_generate_item_declaration", "net_declaration", "ERROR", "simple_identifier"], "target": " .clk (tb_clk),\n"}
{"file": "usb20dev/verif/testbenches/example/tb.sv", "target_type": "simple_identifier", "cursor_line": 37, "target_nlines": 1, "node_depth": 1, "node_path": ["ERROR", "simple_identifier"], "target": "`include \"../testbenches/tb_footer.svh\"\n"}
{"file": "usb20dev/verif/testbenches/sie/tb.sv", "target_type": "function_statement", "cursor_line": 78, "target_nlines": 1, "node_depth": 8, "node_path": ["ERROR", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement"], "target": " is_data_eq = 1;\n"}
{"file": "usb20dev/verif/testbenches/tb_dut_usb.svh", "target_type": "simple_identifier", "cursor_line": 6, "target_nlines": 1, "node_depth": 3, "node_path": ["source_file", "package_or_generate_item_declaration", "net_declaration", "simple_identifier"], "target": "usb dut (\n"}
{"file": "usb20dev/verif/testbenches/tb_footer.svh", "target_type": "simple_identifier", "cursor_line": 34, "target_nlines": 1, "node_depth": 11, "node_path": ["source_file", "package_or_generate_item_declaration", "data_declaration", "ERROR", "delay_control", "mintypmax_expression", "expression", "primary", "primary_literal", "simple_text_macro_usage", "text_macro_identifier", "simple_identifier"], "target": " #(`STOP_TIME);\n"}
{"file": "usb20dev/verif/testbenches/tb_header.svh", "target_type": "simple_identifier", "cursor_line": 26, "target_nlines": 1, "node_depth": 6, "node_path": ["ERROR", "module_or_generate_item", "package_or_generate_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "simple_identifier"], "target": "logic tb_clk = 0;\n"}
{"file": "UVM_Verification/rcc_agent.sv", "target_type": "simple_identifier", "cursor_line": 8, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_property", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "simple_identifier"], "target": "\tuvm_analysis_port #(rcc_transaction) mon2ref;\n"}
{"file": "UVM_Verification/rcc_assertions.sv", "target_type": "module_declaration", "cursor_line": 31, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " disable iff (intf.reset) $rose(intf.rcc_clk) |=> !$isunknown(intf.din);\n endproperty\n\n"}
{"file": "UVM_Verification/rcc_config.sv", "target_type": "primary", "cursor_line": 5, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "class_constructor_declaration", "list_of_arguments_parent", "expression", "primary"], "target": "\t\tsuper.new(name);\n"}
{"file": "UVM_Verification/rcc_driver.sv", "target_type": "primary", "cursor_line": 36, "target_nlines": 1, "node_depth": 4, "node_path": ["ERROR", "ERROR", "mintypmax_expression", "expression", "primary"], "target": "\t\t if(!uvm_config_db#(virtual rcc_if)::get(this, \"\", \"vif\", vif))\n"}
{"file": "UVM_Verification/rcc_environment.sv", "target_type": "simple_identifier", "cursor_line": 20, "target_nlines": 1, "node_depth": 17, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "blocking_assignment", "operator_assignment", "expression", "primary", "let_expression", "let_list_of_arguments", "simple_identifier"], "target": " rcc_cov = rcc_in_coverage::type_id::create(.name(\"rcc_cov\"), .parent(this));\n"}
{"file": "UVM_Verification/rcc_if.sv", "target_type": "simple_identifier", "cursor_line": 12, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "interface_declaration", "interface_or_generate_item", "package_or_generate_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "simple_identifier"], "target": " logic [15:0] din;\n"}
{"file": "UVM_Verification/rcc_in_coverage.sv", "target_type": "simple_identifier", "cursor_line": 10, "target_nlines": 1, "node_depth": 8, "node_path": ["ERROR", "class_item", "class_property", "data_declaration", "data_type_or_implicit1", "data_type", "class_type", "class_identifier", "simple_identifier"], "target": " uvm_tlm_analysis_fifo #(rcc_transaction) cov_addr_fifo;\n"}
{"file": "UVM_Verification/rcc_monitor.sv", "target_type": "primary", "cursor_line": 28, "target_nlines": 1, "node_depth": 2, "node_path": ["ERROR", "ERROR", "primary"], "target": " `uvm_fatal(\"No Vif\", {\"virtual interface must be set for: \", get_full_name(), \".vif\"});\n"}
{"file": "UVM_Verification/rcc_out_coverage.sv", "target_type": "simple_identifier", "cursor_line": 98, "target_nlines": 1, "node_depth": 6, "node_path": ["ERROR", "class_item", "class_property", "data_declaration", "data_type_or_implicit1", "data_type", "simple_identifier"], "target": " bins out_ref_pound = {35};\n"}
{"file": "UVM_Verification/rcc_pkg.sv", "target_type": "simple_identifier", "cursor_line": 1, "target_nlines": 1, "node_depth": 3, "node_path": ["source_file", "package_declaration", "package_identifier", "simple_identifier"], "target": "package rcc_pkg;\n"}
{"file": "UVM_Verification/rcc_scoreboard.sv", "target_type": "simple_identifier", "cursor_line": 11, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_property", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "simple_identifier"], "target": " uvm_analysis_export #(rcc_transaction) out_ref;\n"}
{"file": "UVM_Verification/rcc_sequencer.sv", "target_type": "data_type", "cursor_line": 39, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "class_constructor_declaration", "tf_port_list", "tf_port_item1", "data_type_or_implicit1", "data_type"], "target": "\tfunction new(string name = \"\");\n"}
{"file": "UVM_Verification/rcc_tb_top.sv", "target_type": "module_declaration", "cursor_line": 23, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " // coverage instance for coverage result display\n rcc_in_coverage cov_in;\n"}
{"file": "UVM_Verification/rcc_test.sv", "target_type": "data_type", "cursor_line": 25, "target_nlines": 1, "node_depth": 10, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "task_declaration", "task_body_declaration", "tf_port_list", "tf_port_item1", "data_type_or_implicit1", "data_type"], "target": "\ttask run_phase(uvm_phase phase);\n"}
{"file": "UVM_Verification/ref_pred.sv", "target_type": "data_type", "cursor_line": 17, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_property", "data_declaration", "data_type_or_implicit1", "data_type"], "target": " integer ref_out;\n"}
{"file": "UVM_Verification/results_conv.v", "target_type": "case_statement", "cursor_line": 364, "target_nlines": 4, "node_depth": 22, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " end\n else\n state <= `IDLE ;\n end\n"}
{"file": "UVM_Verification/results_conv_test.sv", "target_type": "module_declaration", "cursor_line": 62, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " g_din[15:0] = 16'b0000000000000000;\n\n rcc_clk = 1'b0;\n test_mode = 1'b0;\n"}
{"file": "UVM_Verification/results_conv_test.v", "target_type": "module_declaration", "cursor_line": 118, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "always @(posedge digit_clk)\nbegin\n"}
{"file": "easyUVM/adder.sv", "target_type": "module_declaration", "cursor_line": 12, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " INITIAL: begin\n inter.ready <= 1;\n state <= WAIT;\n"}
{"file": "easyUVM/agent.sv", "target_type": "simple_identifier", "cursor_line": 19, "target_nlines": 1, "node_depth": 18, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "blocking_assignment", "operator_assignment", "expression", "primary", "function_subroutine_call", "subroutine_call", "tf_call", "simple_identifier"], "target": " drv = driver::type_id::create(\"drv\", this);\n"}
{"file": "easyUVM/agent_out.sv", "target_type": "simple_identifier", "cursor_line": 9, "target_nlines": 1, "node_depth": 10, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "class_constructor_declaration", "tf_port_list", "tf_port_item1", "data_type_or_implicit1", "data_type", "simple_identifier"], "target": " function new(string name = \"agent_out\", uvm_component parent = null);\n"}
{"file": "easyUVM/comparator.sv", "target_type": "primary", "cursor_line": 61, "target_nlines": 1, "node_depth": 13, "node_path": ["ERROR", "function_statement_or_null", "function_statement", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "checker_instantiation", "event_expression", "event_expression", "expression", "primary"], "target": " uvm_report_fatal(\"No expect transaction to compare with\", \"\");\n"}
{"file": "easyUVM/driver.sv", "target_type": "primary", "cursor_line": 14, "target_nlines": 1, "node_depth": 2, "node_path": ["ERROR", "ERROR", "primary"], "target": " assert(uvm_config_db#(input_vif)::get(this, \"\", \"vif\", vif));\n"}
{"file": "easyUVM/driver_out.sv", "target_type": "simple_identifier", "cursor_line": 13, "target_nlines": 1, "node_depth": 4, "node_path": ["ERROR", "ERROR", "class_type", "class_identifier", "simple_identifier"], "target": " assert(uvm_config_db#(output_vif)::get(this, \"\", \"vif\", vif));\n"}
{"file": "easyUVM/env.sv", "target_type": "simple_identifier", "cursor_line": 29, "target_nlines": 1, "node_depth": 10, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "function_declaration", "function_body_declaration", "ERROR", "clockvar_expression", "clockvar", "simple_identifier"], "target": " rfm.in.connect(to_refmod.get_export);\n"}
{"file": "easyUVM/input_if.sv", "target_type": "simple_identifier", "cursor_line": 5, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "interface_declaration", "modport_declaration", "modport_item", "modport_ports_declaration", "modport_simple_ports_declaration", "modport_simple_port", "port_identifier", "simple_identifier"], "target": " modport port(input clk, rst, A, B, valid, output ready);\n"}
{"file": "easyUVM/monitor.sv", "target_type": "simple_identifier", "cursor_line": 8, "target_nlines": 1, "node_depth": 8, "node_path": ["ERROR", "class_item", "class_method", "class_constructor_declaration", "tf_port_list", "tf_port_item1", "data_type_or_implicit1", "data_type", "simple_identifier"], "target": " function new(string name, uvm_component parent);\n"}
{"file": "easyUVM/monitor_out.sv", "target_type": "simple_identifier", "cursor_line": 3, "target_nlines": 1, "node_depth": 6, "node_path": ["ERROR", "class_item", "class_property", "data_declaration", "data_type_or_implicit1", "data_type", "simple_identifier"], "target": " output_vif vif;\n"}
{"file": "easyUVM/output_if.sv", "target_type": "simple_identifier", "cursor_line": 1, "target_nlines": 1, "node_depth": 6, "node_path": ["source_file", "interface_declaration", "interface_ansi_header", "list_of_port_declarations", "ansi_port_declaration", "port_identifier", "simple_identifier"], "target": "interface output_if(input clk, rst);\n"}
{"file": "easyUVM/packet_in.sv", "target_type": "simple_identifier", "cursor_line": 7, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "text_macro_usage", "list_of_actual_arguments", "expression", "expression", "primary", "simple_identifier"], "target": " `uvm_field_int(B, UVM_ALL_ON|UVM_HEX)\n"}
{"file": "easyUVM/packet_out.sv", "target_type": "simple_identifier", "cursor_line": 8, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "class_constructor_declaration", "tf_port_list", "tf_port_item1", "port_identifier", "simple_identifier"], "target": " function new(string name=\"packet_out\");\n"}
{"file": "easyUVM/refmod.sv", "target_type": "primary_literal", "cursor_line": 20, "target_nlines": 1, "node_depth": 21, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "blocking_assignment", "operator_assignment", "expression", "primary", "function_subroutine_call", "subroutine_call", "tf_call", "list_of_arguments_parent", "expression", "primary", "primary_literal"], "target": " tr_out = packet_out::type_id::create(\"tr_out\", this);\n"}
{"file": "easyUVM/sequence_in.sv", "target_type": "primary", "cursor_line": 14, "target_nlines": 1, "node_depth": 20, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "task_declaration", "task_body_declaration", "statement_or_null", "statement", "statement_item", "loop_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "simple_immediate_assert_statement", "expression", "primary"], "target": " assert(tx.randomize());\n"}
{"file": "easyUVM/sequencer.sv", "target_type": "simple_identifier", "cursor_line": 1, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_type", "parameter_value_assignment", "list_of_parameter_assignments", "ordered_parameter_assignment", "_ordered_parameter_assignment", "data_type", "simple_identifier"], "target": "class sequencer extends uvm_sequencer #(packet_in);\n"}
{"file": "easyUVM/simple_test.sv", "target_type": "simple_identifier", "cursor_line": 3, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_property", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "simple_identifier"], "target": " sequence_in seq;\n"}
{"file": "easyUVM/top.sv", "target_type": "module_declaration", "cursor_line": 34, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " \n logic [1:0] state;\n"}
{"file": "svreal/svreal/svreal.sv", "target_type": "module_declaration", "cursor_line": 1343, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " `MAKE_REAL(fract_as_float, in_width+1);\n"}
{"file": "svreal/tests/test_arith.sv", "target_type": "module_declaration", "cursor_line": 14, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " output real mul_o,\n"}
{"file": "svreal/tests/test_clog2.sv", "target_type": "module_declaration", "cursor_line": 7, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " output signed [31:0] out\n);\n assign out = clog2_math(in_);\nendmodule\n"}
{"file": "svreal/tests/test_comp.sv", "target_type": "module_declaration", "cursor_line": 30, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " `EQ_INTO_REAL(a_int, b_int, eq_o);\n `NE_INTO_REAL(a_int, b_int, ne_o);\nendmodule"}
{"file": "svreal/tests/test_compress_uint.sv", "target_type": "module_declaration", "cursor_line": 12, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": ");\n `COMPRESS_UINT(in_, (`WIDTH), val);\n assign out = `TO_REAL(val);\nendmodule\n"}
{"file": "svreal/tests/test_const.sv", "target_type": "module_declaration", "cursor_line": 15, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": ");\n // produce a_o output\n `MAKE_CONST_REAL(a_const, a_const_int);\n assign a_o = `TO_REAL(a_const_int);\n\n"}
{"file": "svreal/tests/test_conv.sv", "target_type": "module_declaration", "cursor_line": 15, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " assign `FORCE_REAL(r2i_i, r2i_int);\n\n"}
{"file": "svreal/tests/test_dff.sv", "target_type": "module_declaration", "cursor_line": 5, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "module test_dff #(\n parameter real init=0.0\n) (\n"}
{"file": "svreal/tests/test_float.sv", "target_type": "primary", "cursor_line": 32, "target_nlines": 1, "node_depth": 14, "node_path": ["source_file", "ERROR", "module_or_generate_item", "package_or_generate_item_declaration", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "conditional_statement", "cond_predicate", "expression", "expression", "primary"], "target": " if ((data[62:52] == 11'h7ff) && (data[51:0] != 0)) begin\n"}
{"file": "svreal/tests/test_hier.sv", "target_type": "primary", "cursor_line": 28, "target_nlines": 1, "node_depth": 4, "node_path": ["source_file", "text_macro_usage", "list_of_actual_arguments", "expression", "primary"], "target": " `PASS_REAL(b, b),\n"}
{"file": "svreal/tests/test_iface.sv", "target_type": "module_declaration", "cursor_line": 17, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n // create c_int interface\n svreal #(`REAL_INTF_PARAMS(value, 18, -10)) c_int ();\n"}
{"file": "svreal/tests/test_iface_core.sv", "target_type": "module_declaration", "cursor_line": 58, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "module level1 (svreal.in a, svreal.in b, svreal.out c);\n level2 inner(.a(a), .b(b), .c(c));\nendmodule\n"}
{"file": "svreal/tests/test_iface_synth.sv", "target_type": "module_declaration", "cursor_line": 13, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n assign a.value = a_value;\n assign b.value = b_value;\n assign c_value = c.value;\n"}
{"file": "svreal/tests/test_ite.sv", "target_type": "module_declaration", "cursor_line": 8, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input real b_i,\n // if-then-else\n input cond_i,\n"}
{"file": "svreal/tests/test_meas_width.sv", "target_type": "module_declaration", "cursor_line": 6, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input [7:0] in_,\n output [7:0] out\n);\n `MEAS_UINT_WIDTH_INTO(in_, 8, out, 8);\n"}
{"file": "svreal/tests/test_sync_ram.sv", "target_type": "module_declaration", "cursor_line": 9, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input clk,\n"}
{"file": "svreal/tests/test_sync_rom.sv", "target_type": "module_declaration", "cursor_line": 5, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "module test_sync_rom (\n input [1:0] addr,\n output real out,\n input clk,\n"}
{"file": "svreal/tests/test_synth.sv", "target_type": "module_declaration", "cursor_line": 12, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " input wire logic signed [`A_WIDTH-1:0] a_ext,\n input wire logic signed [`B_WIDTH-1:0] b_ext,\n // unary op I/O\n output wire logic signed [`A_WIDTH-1:0] neg_ext,\n output wire logic signed [`A_WIDTH-1:0] abs_ext,\n"}
{"file": "ava-core/rtl/accelerator_pkg.sv", "target_type": "primary_literal", "cursor_line": 36, "target_nlines": 1, "node_depth": 11, "node_path": ["source_file", "package_declaration", "package_or_generate_item_declaration", "data_declaration", "type_declaration", "data_type", "enum_base_type", "packed_dimension", "constant_range", "constant_expression", "constant_primary", "primary_literal"], "target": "typedef enum logic [1:0] {\n"}
{"file": "ava-core/rtl/accelerator_top.sv", "target_type": "case_statement", "cursor_line": 174, "target_nlines": 5, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " vd_data = vlsu_wdata;\n VREG_WB_SRC_ARITH:\n vd_data = arith_output;\n VREG_WB_SRC_SCALAR:\n vd_data = replicated_scalar;\n"}
{"file": "ava-core/rtl/address_unit.sv", "target_type": "expression", "cursor_line": 135, "target_nlines": 1, "node_depth": 16, "node_path": ["ERROR", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "blocking_assignment", "operator_assignment", "expression", "expression", "expression", "expression", "primary", "concatenation", "expression"], "target": " cycle_bytes = {5'd0, be_gen[3]} + {5'd0, be_gen[2]} + {5'd0, be_gen[1]} + {5'd0, be_gen[0]};\n"}
{"file": "ava-core/rtl/arith_stage.sv", "target_type": "case_statement", "cursor_line": 152, "target_nlines": 4, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " PE_OPERAND_IMMEDIATE:\n begin\n if (unsigned_immediate)\n begin\n"}
{"file": "ava-core/rtl/bit_ext.sv", "target_type": "module_declaration", "cursor_line": 17, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " (input logic signed [W_IN-1:0] a_in, \n output logic signed [W_OUT-1:0] a_out);\n"}
{"file": "ava-core/rtl/mapping_unit.sv", "target_type": "module_declaration", "cursor_line": 39, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " vd_data[15:0]\n"}
{"file": "ava-core/rtl/pe_32b.sv", "target_type": "case_statement", "cursor_line": 225, "target_nlines": 5, "node_depth": 14, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " 2'd0: // 8b -> 16b\n sat_result = {'0, sat16_result};\n 2'd1: // 16b -> 32b\n sat_result = sat32_result;\n endcase\n"}
{"file": "ava-core/rtl/relu_bound.sv", "target_type": "module_declaration", "cursor_line": 23, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " ar = 0;\n else if (a > N)\n ar = N[6:0];\n else\n ar = a[6:0];\n"}
{"file": "ava-core/rtl/sat_unit.sv", "target_type": "module_declaration", "cursor_line": 23, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " logic signed [W_OUT-1:0] min_out = {1'b1,{(W_OUT-1){1'b0}}};\n\n assign a_out = a_in < min_in ? min_out : (a_in > max_in) ? max_out : a_in[W_OUT-1:0];\n\n //initial $display(\"%d, %d, %d, %d\", max_in, min_in, max_out, min_out);\n"}
{"file": "ava-core/rtl/scalar_replicate.sv", "target_type": "case_statement", "cursor_line": 65, "target_nlines": 5, "node_depth": 6, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "case_statement"], "target": " else\n replicated_out = {\n {16{scalar_in[15]}},\n scalar_in[15:0],\n {16{scalar_in[15]}},\n"}
{"file": "ava-core/rtl/tb/tb_bit_ext.sv", "target_type": "primary", "cursor_line": 32, "target_nlines": 1, "node_depth": 9, "node_path": ["ERROR", "module_or_generate_item", "loop_generate_construct", "generate_block", "module_or_generate_item", "udp_instantiation", "udp_instance", "input_terminal", "expression", "primary"], "target": " #1ns $display(\"%d, %d\", in, out);\n"}
{"file": "ava-core/rtl/tb/tb_relu_bound.sv", "target_type": "primary", "cursor_line": 34, "target_nlines": 1, "node_depth": 9, "node_path": ["ERROR", "module_or_generate_item", "loop_generate_construct", "generate_block", "module_or_generate_item", "udp_instantiation", "udp_instance", "input_terminal", "expression", "primary"], "target": " #10ns $display(\"%d, %d\", in, out);\n"}
{"file": "ava-core/rtl/tb/tb_sat_unit.sv", "target_type": "primary", "cursor_line": 23, "target_nlines": 1, "node_depth": 7, "node_path": ["ERROR", "module_or_generate_item", "module_instantiation", "hierarchical_instance", "list_of_port_connections", "ordered_port_connection", "expression", "primary"], "target": "sat_unit #(.W_IN(13), .W_OUT(8)) satu(in, out);\n"}
{"file": "ava-core/rtl/temporary_reg.sv", "target_type": "case_statement", "cursor_line": 84, "target_nlines": 5, "node_depth": 18, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " packed_set[1] = 1'b1;\n memory_read_packed[1] = memory_read_bytes[2];\n end\n 4'bzz11 : begin\n packed_set[2] = 1'b1;\n"}
{"file": "ava-core/rtl/vector_csrs.sv", "target_type": "module_declaration", "cursor_line": 83, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": " vl_next = max_vl;\n else\n vl_next = avl_in[4:0];\n\nend\n"}
{"file": "ava-core/rtl/vector_decoder.sv", "target_type": "case_statement", "cursor_line": 141, "target_nlines": 1, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " else\n"}
{"file": "ava-core/rtl/vector_lsu.sv", "target_type": "case_statement", "cursor_line": 88, "target_nlines": 5, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " case(vs3_addr_o[0])\n 1'd0 : data_wdata_o = {vs_rdata_i[47:32], vs_rdata_i[15:0]};\n 1'd1 : data_wdata_o = {vs_rdata_i[111:96], vs_rdata_i[79:64]};\n endcase\n end\n"}
{"file": "ava-core/rtl/vector_registers.sv", "target_type": "case_statement", "cursor_line": 290, "target_nlines": 4, "node_depth": 27, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement", "case_item", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " end\n // 2'd1: // Not needed, just wr_en0 = '1\n 2'd2:\n begin\n"}
{"file": "ava-core/rtl/vw_sign_ext.sv", "target_type": "case_statement", "cursor_line": 36, "target_nlines": 3, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": " 2'd0: // 8b\n begin\n sign_ext_a = {{24{a[7]}}, a[7:0]};\n"}
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