systemverilog/train.jsonl

{"file": "chipfail-glitcher/chipfail-glitcher.srcs/sources_1/new/uart_tx.v", "target_type": "case_statement", "cursor_line": 106, "target_nlines": 3, "node_depth": 22, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "            begin\n                if(etu_full)\n                begin\n"}
{"file": "CHIPKIT/ip/ahb/AHB_MEM.sv", "target_type": "case_statement", "cursor_line": 60, "target_nlines": 4, "node_depth": 18, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "        0: byte_lane_nxt = 4'b0001; // Byte 0\r\n        1: byte_lane_nxt = 4'b0010; // Byte 1\r\n        2: byte_lane_nxt = 4'b0100; // Byte 2\r\n        3: byte_lane_nxt = 4'b1000; // Byte 3\r\n"}
{"file": "ISP_UVM/frame_monitor.sv", "target_type": "include_compiler_directive", "cursor_line": 1, "target_nlines": 1, "node_depth": 1, "node_path": ["ERROR", "include_compiler_directive"], "target": "`include \"cvFunction.svh\"\n"}
{"file": "JSilicon/sim/jsilicon_tb_top.sv", "target_type": "primary", "cursor_line": 14, "target_nlines": 1, "node_depth": 13, "node_path": ["ERROR", "module_or_generate_item", "initial_construct", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "blocking_assignment", "operator_assignment", "expression", "primary"], "target": "        clk = 0;\n"}
{"file": "vdf-fpga/modular_square/rtl/modular_square_simple.sv", "target_type": "module_declaration", "cursor_line": 74, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "         end\n      end\n   end\n   \n   assign valid_next = running && (valid_count == PIPELINE_DEPTH-1);\n"}
{"file": "10g-low-latency-ethernet/example/hdl/example_10g_eth.sv", "target_type": "module_declaration", "cursor_line": 35, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "module example_10g_eth #(\n    parameter bit SCRAMBLER_BYPASS = 0,\n"}
{"file": "DDR4Sim/src/burst_rw.sv", "target_type": "module_declaration", "cursor_line": 29, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "logic clear_rw_counter = 1'b0; \n"}
{"file": "PDPU/sources/counter_5to3.sv", "target_type": "module_declaration", "cursor_line": 5, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": ");\n    assign sum = x1 ^ x2 ^ x3 ^ x4 ^ cin;\n    assign cout = (x1 ^ x2) & x3 | ~(x1 ^ x2) & x1;\n    assign carry = (x1 ^ x2 ^ x3 ^ x4) & cin | ~(x1 ^ x2 ^ x3 ^ x4) & x4;\nendmodule"}
{"file": "UVM-APB_RAL/tb/reg_rw_test.sv", "target_type": "simple_identifier", "cursor_line": 18, "target_nlines": 1, "node_depth": 11, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "task_declaration", "task_body_declaration", "ERROR", "clockvar_expression", "select1", "member_identifier", "simple_identifier"], "target": "      m_seq.start(m_env.m_agent.m_seqr);\n"}
{"file": "ravenoc/src/ravenoc_wrapper.sv", "target_type": "primary", "cursor_line": 238, "target_nlines": 1, "node_depth": 28, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "loop_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "ERROR", "clockvar_expression", "select1", "bit_select1", "expression", "primary"], "target": "        axi_mosi[i].arlock   = noc_out_arlock;\n"}
{"file": "risc-v-single-cycle/sources_1/new/Alu.sv", "target_type": "case_statement", "cursor_line": 10, "target_nlines": 2, "node_depth": 6, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "case_statement"], "target": "        case (aluControl)\n            4'h0: aluOut <= op1 + op2;\n"}
{"file": "uvm_example/src/uvm/ue_pkg.svh", "target_type": "include_compiler_directive", "cursor_line": 28, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "include_compiler_directive"], "target": "`include \"./test_case/ue_case1_test.sv\"\n"}
{"file": "RISC-V-Pipelined-Processor/RISC-V Pipelined Processor/RISC-V/ThreebyOneMux.sv", "target_type": "module_declaration", "cursor_line": 8, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "    output reg [63:0] out\r\n  );\r\n  always @(*)\r\n"}
{"file": "UART/uart_tx.sv", "target_type": "case_statement", "cursor_line": 80, "target_nlines": 1, "node_depth": 14, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "else begin\n"}
{"file": "proto245/examples/ft2232h_de10lite/hw/sync245.svh", "target_type": "variable_decl_assignment", "cursor_line": 66, "target_nlines": 1, "node_depth": 4, "node_path": ["source_file", "package_or_generate_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment"], "target": "assign ft_din  = ft_data;\n"}
{"file": "Async_FIFO_Verification/tb/SV_OO/tb_classes/tb.svh", "target_type": "simple_identifier", "cursor_line": 37, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "task_declaration", "task_body_declaration", "task_identifier", "task_identifier", "simple_identifier"], "target": "  task execute();\n"}
{"file": "USTC-RVSoC/RTL/cpu/core_bus_wrapper.sv", "target_type": "case_statement", "cursor_line": 90, "target_nlines": 3, "node_depth": 18, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "            3'b100    : if     (rd_addr_lsb==2'b00) o_rdata <= {          24'b0, rdata[ 7: 0]};\r\n                        else if(rd_addr_lsb==2'b01) o_rdata <= {          24'b0, rdata[15: 8]};\r\n                        else if(rd_addr_lsb==2'b10) o_rdata <= {          24'b0, rdata[23:16]};\r\n"}
{"file": "ahb3lite_interconnect/rtl/verilog/ahb3lite_interconnect_slave_priority.sv", "target_type": "module_declaration", "cursor_line": 109, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "          .HI      ( HI             ),\n"}
{"file": "my_verilog_projects/parallel_serial_switch/serial_to_parallel.v", "target_type": "module_declaration", "cursor_line": 7, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\toutput done\n"}
{"file": "systemverilog.io/macros/macros1.sv", "target_type": "simple_identifier", "cursor_line": 15, "target_nlines": 1, "node_depth": 4, "node_path": ["source_file", "text_macro_definition", "text_macro_name", "text_macro_identifier", "simple_identifier"], "target": "`define append_front_1_bad(MOD) \"MOD.master\"\n"}
{"file": "i2c_vip/I2C_tb_files/src/slave_agt_top/slave_agt_top.sv", "target_type": "expression", "cursor_line": 46, "target_nlines": 1, "node_depth": 10, "node_path": ["source_file", "package_or_generate_item_declaration", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "blocking_assignment", "operator_assignment", "expression"], "target": "\tsuper.new(name,parent);\n"}
{"file": "reDIP-SID/gateware/cells_sim/SB_RGBA_DRV.v", "target_type": "module_declaration", "cursor_line": 6, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\tinput RGBLEDEN,\n\tinput RGB0PWM,\n\tinput RGB1PWM,\n\tinput RGB2PWM,\n\toutput RGB0,\n"}
{"file": "CX/2019/bnn.v", "target_type": "module_declaration", "cursor_line": 45, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "      bnn(.req_valid(1'b1), .req_func_id(req_func_id), .req_data0(req_data0), .req_data1(req_data1), .resp_data(resp_data));\n\n    always @(posedge clk) begin\n"}
{"file": "RecoNIC/sim/src/axi_5to2_interconnect_to_sys_mem.sv", "target_type": "continuous_assign", "cursor_line": 514, "target_nlines": 1, "node_depth": 3, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "continuous_assign"], "target": "assign s_axi_rdma_send_write_payload_wready                             = s_axi_wready[C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *1 +: 1];\n"}
{"file": "kria-vitis-platforms/kv260/overlays/dpu_ip/DPUCZDX8G_v4_0_0/inc/arch_def.vh", "target_type": "casting_type", "cursor_line": 26, "target_nlines": 1, "node_depth": 6, "node_path": ["source_file", "ERROR", "net_decl_assignment", "expression", "conditional_expression", "ERROR", "casting_type"], "target": "`pragma protect end_commonblock\n"}
{"file": "redmule/rtl/redmule_castin.sv", "target_type": "module_declaration", "cursor_line": 35, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "localparam int unsigned NARRBITW = fpnew_pkg::fp_width(fpnew_pkg::FP8);\n// localparam int unsigned ZEROBITS = WIDTH - NARRBITW;\nlocalparam int unsigned ZEROBITS = MIN_FMT;\n"}
{"file": "uvm_agents/src/i2c/i2c_master_driver.sv", "target_type": "primary", "cursor_line": 117, "target_nlines": 1, "node_depth": 26, "node_path": ["ERROR", "package_or_generate_item_declaration", "task_declaration", "task_body_declaration", "statement_or_null", "statement", "statement_item", "par_block", "statement_or_null", "statement", "statement_item", "loop_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "par_block", "statement_or_null", "statement", "statement_item", "seq_block", "ERROR", "expression", "primary"], "target": "          else                                           seq_item_port.get_next_item(req); //wait for a sequence item from the sequencer\n"}
{"file": "UH-JLS/RTL_develop_ver/merge.sv", "target_type": "module_declaration", "cursor_line": 41, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "            o_pc[i] <= i_vl[i] ? i_pc[i] : a_pc[i];\r\n            o_zc[i] <= i_vl[i] ? i_zc[i] : a_zc[i];\r\n            o_bv[i] <= i_vl[i] ? i_bv[i] : a_bv[i];\r\n            o_bc[i] <= i_vl[i] ? i_bc[i] : a_bc[i];\r\n        end else if(i_vl[i]) begin\r\n"}
{"file": "csi2_rx/src/csi2_crc_calc.sv", "target_type": "module_declaration", "cursor_line": 104, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "  begin\n    crc_24bit      = main_crc;\n    crc_24bit_prev = main_crc;\n    for( int i = 0; i < 24; i++ )\n      begin\n"}
{"file": "riscv-proc/source/mux4.sv", "target_type": "module_declaration", "cursor_line": 5, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\t\t\t2'b00: y = d0;\r\n\t\t\t2'b01: y = d1;\r\n\t\t\t2'b10: y = d2;\r\n\t\t\t2'b11: y = d3;\r\n\tendcase\r\n"}
{"file": "tinyGPU/Verilog/Testbenches/smcore_tb.sv", "target_type": "module_declaration", "cursor_line": 44, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "    assign memclk=clk;\n\n    //Connections to Instruction Memory\n    wire  [`INSTMEM_ADDR_WIDTH-1:0]   inst_addr;\n"}
{"file": "NiteFury-and-LiteFury/Sample-Projects/Project-0/FPGA/LiteFury/project/project.srcs/sources_1/imports/HDL/CodeBlinker.v", "target_type": "case_statement", "cursor_line": 110, "target_nlines": 1, "node_depth": 30, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "\t\t\t\t\t\tcase (state)\n"}
{"file": "riscv-aia/rtl/aplic_top.sv", "target_type": "module_declaration", "cursor_line": 81, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "      .i_msi_rsp        ( i_msi_rsp          )\n"}
{"file": "AHB-to-APB-Bridge-Verification/Bridge_rtl/ahb_apb_top.v", "target_type": "module_declaration", "cursor_line": 44, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "     apb_controller FSM(Hclk,\r\n                        Hresetn,\r\n                        valid,\r\n"}
{"file": "FM_Radio/rtl/iq_modulator.sv", "target_type": "case_statement", "cursor_line": 36, "target_nlines": 3, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "         begin\n            I <= -to_signed(adc);\n            Q <=  to_signed(adc);\n"}
{"file": "aes128-hdl/src/sv/aes128Pkg.sv", "target_type": "primary_literal", "cursor_line": 112, "target_nlines": 1, "node_depth": 4, "node_path": ["ERROR", "ERROR", "constant_expression", "constant_primary", "primary_literal"], "target": "\t\t\tresult[2][3] = inp[1][3];\n"}
{"file": "register_interface/src/axi_lite_to_reg.sv", "target_type": "module_declaration", "cursor_line": 234, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "  parameter bit DECOUPLE_W = 1\n) (\n  input  logic   clk_i  ,\n  input  logic   rst_ni ,\n"}
{"file": "starshipraider/rtl/MAXWELL/main-fpga/main-fpga.srcs/sources_1/new/ClockSynthesis.sv", "target_type": "module_declaration", "cursor_line": 145, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\t) even_pll (\n"}
{"file": "async_FIFO/sim_uvm/asyncf_down_transaction.sv", "target_type": "primary_literal", "cursor_line": 12, "target_nlines": 1, "node_depth": 10, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "class_constructor_declaration", "tf_port_list", "tf_port_item1", "expression", "primary", "primary_literal"], "target": "   function new(string name = \"asyncf_down_transaction\");\n"}
{"file": "axi-crossbar/rtl/orig.axicb_round_robin_core.sv", "target_type": "module_declaration", "cursor_line": 196, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "    end\n\n    end else if (REQ_NB==8) begin : REQ_8\n\n"}
{"file": "fpga-hash-table/rtl/hash_table_pkg.sv", "target_type": "case_statement", "cursor_line": 115, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "package_declaration", "package_or_generate_item_declaration", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "case_statement"], "target": "                      result.cmd.key, result.found_value, result.rescode, result.chain_state );\n"}
{"file": "riscv-dbg/src/dmi_test.sv", "target_type": "simple_identifier", "cursor_line": 88, "target_nlines": 1, "node_depth": 17, "node_path": ["source_file", "package_declaration", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "task_declaration", "task_body_declaration", "statement_or_null", "statement", "statement_item", "loop_statement", "expression", "expression", "primary", "select1", "member_identifier", "simple_identifier"], "target": "      while (bus.q_ready != 1) begin cycle_end(); cycle_start(); end\n"}
{"file": "AMBA_APB_SRAM/tb/test_lib/apb_mstr_test_lib/apb_reg_por_read_test.sv", "target_type": "operator_assignment", "cursor_line": 29, "target_nlines": 1, "node_depth": 11, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "task_declaration", "task_body_declaration", "statement_or_null", "statement", "statement_item", "blocking_assignment", "operator_assignment"], "target": "        super.run_phase(phase);        \r\n"}
{"file": "DDR5_PHY_WriteOperation/RTL/ddr5_phy_write_fsm.sv", "target_type": "case_statement", "cursor_line": 269, "target_nlines": 3, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "\t\t\t\t\t  next_state = wr_data ; \r\n\t\t\t\t\telse if (interamble_i)\r\n\t\t\t\t\t  next_state = interamble ;\r\n"}
{"file": "axi4_vip/axi_virtual_seqr.sv", "target_type": "simple_identifier", "cursor_line": 31, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "class_constructor_declaration", "tf_port_list", "tf_port_item1", "port_identifier", "simple_identifier"], "target": "\tfunction new(string name = \"axi_env\", uvm_component parent);\r\n"}
{"file": "davos/hdl/ultraplus/rx_interface.v", "target_type": "case_statement", "cursor_line": 279, "target_nlines": 4, "node_depth": 22, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "                             wr_en            <= 1'b0; \n                             cmd_in[1]      <= 1'b1;\n\n                                    state_wr <= BEGIN_WRITE;\n"}
{"file": "eurorack-pmod/gateware/cores/util/filter/karlsen_lpf_pipelined.sv", "target_type": "module_declaration", "cursor_line": 25, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "    input signed [17:0] scale,\n    output signed [35:0] o\n);\nassign o = 36'(a) + (36'(18'(-a + b) * 18'(scale)) >>> 16);\nendmodule\n"}
{"file": "riscv-tests-intro/practice/02_aapg/golden/tb/miriscv_mem_intf.sv", "target_type": "simple_identifier", "cursor_line": 2, "target_nlines": 1, "node_depth": 6, "node_path": ["source_file", "ERROR", "interface_ansi_header", "list_of_port_declarations", "ansi_port_declaration", "port_identifier", "simple_identifier"], "target": "    input logic clk,\n"}
{"file": "tiny-tpu/src/gradient_descent.sv", "target_type": "case_statement", "cursor_line": 58, "target_nlines": 1, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "            1'b1: begin\n"}
{"file": "ahb2apb-bridge/AHB2APB_Bridge/dv/env/ahb2apb_scb.svh", "target_type": "simple_identifier", "cursor_line": 102, "target_nlines": 1, "node_depth": 15, "node_path": ["source_file", "ERROR", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "checker_instantiation", "checker_identifier", "simple_identifier"], "target": "\t\t\t`uvm_error(get_type_name(), \"AHB-packet and APB-packet read/write mismatch! ahb-read, apb-write\")\n"}
{"file": "riscv-vip/src/riscv_vip_csr_if.sv", "target_type": "simple_identifier", "cursor_line": 30, "target_nlines": 1, "node_depth": 4, "node_path": ["source_file", "interface_declaration", "interface_ansi_header", "interface_identifier", "simple_identifier"], "target": "interface riscv_vip_csr_if (input clk, input rstn);\n"}
{"file": "DUA/Hardware/Common/SiliconNet/SiliconNet.sv", "target_type": "simple_identifier", "cursor_line": 377, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "module_instantiation", "hierarchical_instance", "list_of_port_connections", "named_port_connection", "expression", "primary", "simple_identifier"], "target": "        .high_cfg_read_valid_in      (high_cfg_read_valid_out),\n"}
{"file": "Design-Pattern-in-SV/BehavioralDesignPatterns/ChainOfResponsibility/top.sv", "target_type": "primary", "cursor_line": 32, "target_nlines": 1, "node_depth": 4, "node_path": ["source_file", "ERROR", "ERROR", "expression", "primary"], "target": "    repeat(10) begin\n"}
{"file": "FazyRV/soc/tb/fsoc_sim.sv", "target_type": "case_statement", "cursor_line": 181, "target_nlines": 4, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "    `INSTR_BGE:     dbg_ascii_instr = \"bge\";\n    `INSTR_BLTU:    dbg_ascii_instr = \"bltu\";\n    `INSTR_BGEU:    dbg_ascii_instr = \"bgeu\";\n    `INSTR_BEQ:     dbg_ascii_instr = \"beq\";\n"}
{"file": "axi-uvm/tb/axi_sequential_reads_test.svh", "target_type": "data_type", "cursor_line": 41, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "class_constructor_declaration", "tf_port_list", "tf_port_item1", "data_type_or_implicit1", "data_type"], "target": "  function new (string name=\"axi_sequential_reads_test\", uvm_component parent=null);\n"}
{"file": "openfpga-pokemonmini/src/fpga/core/rtl/key_input.sv", "target_type": "module_declaration", "cursor_line": 18, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "    begin\n        for(int i = 0; i < 9; ++i)\n        begin\n            key_irqs[i]    <= 0;\n            key_latches[i] <= keys_active[i];\n"}
{"file": "tang-nano-9k--riscv--cache-psram/notes/miscellaneous/study-fluke-with-version-of-uarttx/uarttx.sv", "target_type": "module_declaration", "cursor_line": 132, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "            state <= DataBits;\n          end\n        end\n\n"}
{"file": "pulp_cluster/tb/mock_uart.sv", "target_type": "case_statement", "cursor_line": 90, "target_nlines": 4, "node_depth": 30, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "                    LCR: lcr <= byte'(pwdata_i[7:0]);\n                    MCR: mcr <= byte'(pwdata_i[7:0] & 'h1F);\n                    LSR: lsr <= byte'(pwdata_i[7:0]);\n                    MSR: msr <= byte'(pwdata_i[7:0]);\n"}
{"file": "svaunit/sv/svaunit_sequence_test.svh", "target_type": "simple_identifier", "cursor_line": 27, "target_nlines": 1, "node_depth": 5, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_type", "class_identifier", "simple_identifier"], "target": "class svaunit_sequence_test#(type SEQ_TYPE=svaunit_base_sequence) extends svaunit_test;\n"}
{"file": "zerosoc/hw/prim/prim_pad_wrapper.sv", "target_type": "module_declaration", "cursor_line": 31, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "  inout wire         inout_io, // bidirectional pad\n  output logic       in_o,     // input data\n  output logic       in_raw_o, // uninverted output data\n  input              ie_i,     // input enable\n  input              out_i,    // output data\n"}
{"file": "rtl-fuzz-lab/test/resources/fuzzing/aes_opentitan/aes_core.sv", "target_type": "case_statement", "cursor_line": 199, "target_nlines": 5, "node_depth": 9, "node_path": ["ERROR", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "    unique case (key_init_sel)\n      KEY_INIT_INPUT: key_init_d = key_init;\n      KEY_INIT_CLEAR: key_init_d = '{default: prd_clearing_256};\n      default:        key_init_d = '{default: prd_clearing_256};\n    endcase\n"}
{"file": "CDIM/mycpu/mycpu_top.sv", "target_type": "primary", "cursor_line": 310, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "module_instantiation", "hierarchical_instance", "list_of_port_connections", "named_port_connection", "expression", "primary"], "target": "        .d_rdata           (d_rdata ),\n"}
{"file": "RTLStructLib/Systolic_Array/src/systolic_array_top.sv", "target_type": "module_declaration", "cursor_line": 23, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "    parameter INNER_DIMENSION = 50,\n    parameter RIGHT_MATRIX_COL = 50,\n"}
{"file": "fpu/hdl/fpu_fmac/booth_selector.sv", "target_type": "module_declaration", "cursor_line": 37, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "   input  logic                    Sel_1x_SI,\n   input logic                     Sel_2x_SI,\n   input logic                     Sel_sign_SI,\n   //Outputs\n   output logic                    Booth_pp_DO\n"}
{"file": "pulpissimo/hw/vendored_ips/gpio/src/gpio.sv", "target_type": "module_declaration", "cursor_line": 48, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "  /// Asynchronous active-low reset\n  input logic                rst_ni,\n  /// GPIO input signals from IO Pads (Pad -> SoC) signal.\n"}
{"file": "riscv-simple-sv/core/common/control_transfer.sv", "target_type": "module_declaration", "cursor_line": 9, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "module control_transfer (\n    input        result_equal_zero,\n"}
{"file": "DV-Interview-Prep-Guide/01_Projects/Multi-Master_Multi-Slave/scoreboard.sv", "target_type": "primary", "cursor_line": 34, "target_nlines": 1, "node_depth": 21, "node_path": ["source_file", "ERROR", "class_item", "class_method", "task_declaration", "task_body_declaration", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "checker_instantiation", "event_expression", "event_expression", "expression", "primary"], "target": "                `uvm_error(\"SCO\", $sformatf(\"FAIL: Transactions Mismatch\\nMaster:\\n%s\\nSlave:\\n%s\", m_tr.sprint(), s_tr.sprint()));\n"}
{"file": "fpga-virtual-console/src/parser/TabControl.sv", "target_type": "module_declaration", "cursor_line": 57, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\tend else begin\n"}
{"file": "pequeno_riscv/src/common/uart_ip/uart_tx.sv", "target_type": "module_declaration", "cursor_line": 231, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n                            // Last Stop bit\n                            if (stop_count_rg == i_frame_mode) begin\n                               stop_count_rg <= 0    ;\n"}
{"file": "cvfpu/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_prepare.v", "target_type": "case_statement", "cursor_line": 228, "target_nlines": 5, "node_depth": 14, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "  3'b010  : ex1_of_result_lfn = !ex1_result_sign;\n  3'b011  : ex1_of_result_lfn = ex1_result_sign;\n  3'b100  : ex1_of_result_lfn = 1'b0;\n  default: ex1_of_result_lfn = 1'b0;\nendcase\n"}
{"file": "dokifive_p50/src/modules/memory/data_bram.v", "target_type": "module_declaration", "cursor_line": 67, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\t\t\t\t.address_a (address),\n\t\t\t\t.byteena_a (byteena),\n\t\t\t\t.clock0 (clock),\n\t\t\t\t.data_a (data),\n\t\t\t\t.wren_a (wren),\n"}
{"file": "hw_interview_questions/rtl/multi_counter_variants/multi_counter_variants.sv", "target_type": "case_statement", "cursor_line": 321, "target_nlines": 4, "node_depth": 13, "node_path": ["source_file", "ERROR", "statement_or_null", "statement", "statement_item", "loop_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "        OP_INIT: p3_ucode_w.dat = p2_dat;\n        OP_INCR: p3_ucode_w.dat = p2_dat + 'b1;\n        OP_DECR: p3_ucode_w.dat = p2_dat - 'b1;\n        default: p3_ucode_w.dat = p2_dat;\n"}
{"file": "openfpga-NES/rtl/upstream/mappers/MMC3.sv", "target_type": "case_statement", "cursor_line": 199, "target_nlines": 1, "node_depth": 39, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement", "case_item", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "\t\t\t\t\t9: chr_bank_9 <= prg_din;       // If K=1, Select 1 KB CHR bank at PPU $0C00 (or $1C00)\n"}
{"file": "zynq-parrot/cosim/v/bsg_zynq_pl_shell.sv", "target_type": "primary_literal", "cursor_line": 218, "target_nlines": 1, "node_depth": 19, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "cond_predicate", "expression", "expression", "primary", "primary_literal"], "target": "        if ( S_AXI_ARESETN == 1'b0 )\n"}
{"file": "ITA/src/ita_inp2_mux.sv", "target_type": "module_declaration", "cursor_line": 8, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "(\n  input  logic         clk_i         ,\n  input  logic         rst_ni        ,\n  input  logic         calc_en_i     ,\n  input  weight_t      weight_i  ,\n"}
{"file": "opl3_fpga/fpga/modules/operator/src/tremolo.sv", "target_type": "module_declaration", "cursor_line": 46, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "(\n    input wire clk,\n    input wire sample_clk_en,\n    input wire [BANK_NUM_WIDTH-1:0] bank_num,\n"}
{"file": "tvip-axi/src/tvip_axi_if.sv", "target_type": "simple_identifier", "cursor_line": 166, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "interface_declaration", "interface_or_generate_item", "package_or_generate_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "simple_identifier"], "target": "  event at_slave_cb_edge;\n"}
{"file": "fpga_snark_prover/ip_cores/multiplier/src/rtl/multiplier.sv", "target_type": "simple_identifier", "cursor_line": 219, "target_nlines": 1, "node_depth": 7, "node_path": ["ERROR", "ERROR", "class_type", "parameter_value_assignment", "list_of_parameter_assignments", "named_parameter_assignment", "parameter_identifier", "simple_identifier"], "target": "  .CTL_BITS  ( CTL_BITS   )\n"}
{"file": "fpga-npu/rtl/npu_tb.sv", "target_type": "blocking_assignment", "cursor_line": 261, "target_nlines": 1, "node_depth": 11, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "initial_construct", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "blocking_assignment"], "target": "\tstart = 0;\n"}
{"file": "uvm_tb_cross_bar/rtl/bus2bus_mux.sv", "target_type": "case_statement", "cursor_line": 79, "target_nlines": 5, "node_depth": 19, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement", "case_item", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "\t\t\t\t0: begin\n\t\t\t\t\tbus_out[1].req   = bus_in[0].req & bus_enable[0];\n\t\t\t\t\tbus_out[1].addr  = bus_in[0].addr;\n\t\t\t\t\tbus_out[1].cmd   = bus_in[0].cmd;\n\t\t\t\t\tbus_out[1].wdata = bus_in[0].wdata;\n"}
{"file": "ddr5_phy/testbench/components/dram_agent/dram_driver.sv", "target_type": "primary_literal", "cursor_line": 205, "target_nlines": 1, "node_depth": 15, "node_path": ["ERROR", "statement_or_null", "statement", "statement_item", "conditional_statement", "cond_predicate", "expression", "primary", "function_subroutine_call", "subroutine_call", "method_call", "method_call_body", "list_of_arguments_parent", "expression", "primary", "primary_literal"], "target": "\t\t\t`uvm_info(\"dram driver\",$sformatf(\"driver says: command %s, cycle 2, bc: CA is   %b, CS is %b at %t\",jedec_seq_item_1.CMD,jedec_driver_vif.cb_J.CA_DA_o,jedec_driver_vif.cb_J.CS_DA_o,$time),UVM_HIGH);\n"}
{"file": "open-nic-shell/src/packet_adapter/packet_adapter.sv", "target_type": "module_declaration", "cursor_line": 34, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "  input   [31:0] s_axil_araddr,\n  output         s_axil_arready,\n"}
{"file": "NoCRouter/src/rtl/noc/node_link.sv", "target_type": "module_declaration", "cursor_line": 3, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "module node_link (\n"}
{"file": "nes_ecp5/mappers/MMC2.sv", "target_type": "case_statement", "cursor_line": 291, "target_nlines": 4, "node_depth": 14, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "\tcasez(prg_ain[14])\n\t\t1'b0:    prgsel = prg_bank;\n\t\tdefault: prgsel = 4'b1111;\n\tendcase\n"}
{"file": "yuu_ahb/include/yuu_ahb_macros.svh", "target_type": "simple_identifier", "cursor_line": 5, "target_nlines": 1, "node_depth": 3, "node_path": ["source_file", "id_directive", "text_macro_identifier", "simple_identifier"], "target": "`ifndef GUARD_YUU_AHB_MACROS_SVH\r\n"}
{"file": "MinecraftHDL/verilog/windows/autoyosys/share/xilinx/drams_map.v", "target_type": "module_declaration", "cursor_line": 53, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\t) _TECHMAP_REPLACE_ (\n\t\t.DPRA(A1ADDR),\n\t\t.DPO(A1DATA),\n"}
{"file": "SystemVerilogReference/projects/updown_counter/env/counter_rd_mon.sv", "target_type": "operator_assignment", "cursor_line": 12, "target_nlines": 1, "node_depth": 11, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "class_constructor_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "blocking_assignment", "operator_assignment"], "target": "\t\tthis.rdmon_if = rdmon_if;\n"}
{"file": "croyde-riscv/rtl/core/core_pipe_exec_cfu.sv", "target_type": "module_declaration", "cursor_line": 31, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "input  wire                 cfu_bltu    , //\ninput  wire                 cfu_bne     , //\ninput  wire                 cfu_ebrk    , //\ninput  wire                 cfu_ecall   , //\n"}
{"file": "apb-uart-uvm-env/uvm_tb/clk_sequencer.sv", "target_type": "simple_identifier", "cursor_line": 26, "target_nlines": 1, "node_depth": 2, "node_path": ["ERROR", "ERROR", "simple_identifier"], "target": "      `uvm_fatal(\"NOVIF\", {\"Virtual interface must be set for: \", get_full_name(), \".vifclk\"})\r\n"}
{"file": "bigpulp/fpga/rtl/xilinx_mailbox_read_adaptor.sv", "target_type": "module_declaration", "cursor_line": 147, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "  endgenerate\n\n  /*\n   *  Transaction acceptance\n"}
{"file": "Cores-VeeR-EH1/design/ifu/ifu.sv", "target_type": "variable_decl_assignment", "cursor_line": 281, "target_nlines": 1, "node_depth": 6, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "package_or_generate_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment"], "target": "   logic ifc_fetch_req_f1_raw, ifc_fetch_req_f1, ifc_fetch_req_f2;\n"}
{"file": "pulp/rtl/includes/debug_bus_defines.sv", "target_type": "simple_identifier", "cursor_line": 41, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "interface_declaration", "modport_declaration", "modport_item", "modport_ports_declaration", "modport_simple_ports_declaration", "modport_simple_port", "port_identifier", "simple_identifier"], "target": "    output      req,  addr,   we, wdata,\n"}
{"file": "systemverilog-design-patterns/decoratorpattern/example/SR_MENTOR_TYPED_NAME/starbuzz.sv", "target_type": "include_compiler_directive", "cursor_line": 8, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "include_compiler_directive"], "target": "`include \"CondimentDecorator.sv\"\n"}
{"file": "XS-Verilog-Library/int64_div_cla3/tb/tb_stim_signed.svh", "target_type": "variable_decl_assignment", "cursor_line": 117, "target_nlines": 1, "node_depth": 4, "node_path": ["source_file", "package_or_generate_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment"], "target": "\tstd::randomize(dividend_64);\n"}
{"file": "HaDes-V/lib/wishbone/wishbone_vga.sv", "target_type": "case_statement", "cursor_line": 232, "target_nlines": 4, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "                        wishbone_we = wishbone.sel;\n                    end\n                    else\n                        next_state = WAIT;\n"}
{"file": "amiq_apb/sv/amiq_apb_slave_seq_lib.sv", "target_type": "simple_identifier", "cursor_line": 53, "target_nlines": 1, "node_depth": 11, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "task_declaration", "task_body_declaration", "block_item_declaration", "data_declaration", "data_type_or_implicit1", "data_type", "simple_identifier"], "target": "\t\t\tamiq_apb_slave_drv_item slave_seq_item = amiq_apb_slave_drv_item::type_id::create(\"slave_seq_item\");\n"}
{"file": "scr1/src/core/pipeline/scr1_pipe_tdu.sv", "target_type": "case_statement", "cursor_line": 256, "target_nlines": 2, "node_depth": 17, "node_path": ["ERROR", "case_item", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "        end\n        SCR1_CSR_CMD_CLEAR: begin\n"}
{"file": "Deep-Neural-Network-Hardware-Accelerator/Source/Project/HDL/UART2AXI/source/fifo.sv", "target_type": "module_declaration", "cursor_line": 63, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\t\twrite_ptr <= 0;\n        read_over <= 1;\n        write_over <= 0;\n        read_enable_sync <= 0;\n        last_activity <= 0;\n"}
{"file": "h265_decoder/src/filter_32.sv", "target_type": "case_statement", "cursor_line": 1405, "target_nlines": 3, "node_depth": 38, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "    if (store_stage == 2) begin\r\n        deblock_buf_bk[0]         <= {8'd0,deblock_buf_bk[0][1]};\r\n        deblock_buf_bk[1]         <= {8'd0,deblock_buf_bk[1][1]};\r\n"}
{"file": "Cores-VeeR-EH2/design/dec/eh2_dec_csr.sv", "target_type": "expression", "cursor_line": 280, "target_nlines": 1, "node_depth": 11, "node_path": ["source_file", "package_or_generate_item_declaration", "net_declaration", "list_of_net_decl_assignments", "net_decl_assignment", "expression", "primary", "mintypmax_expression", "expression", "expression", "expression", "expression"], "target": "    &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]\n"}
{"file": "DDR4_controller/ips/ems_lib/priority_arbiter_8/priority_arbiter_8.sv", "target_type": "module_declaration", "cursor_line": 54, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\t   )mux\n\t   (\n\t\t.in(data_i),\n\t\t.sel(select_lcl),\n\t\t.out(data_o)\n"}
{"file": "Pre_Silicon-AHB-to_APB-Verification/Checkpoint 3_ SystemVerilog OOP Testbench/VIP_Different_Approach/top.sv", "target_type": "module_declaration", "cursor_line": 57, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "  logic clk, reset;\r\n\r\n  // Generates clk with a time period of 5 ns\r\n  always\r\n  begin\r\n"}
{"file": "SVA-AXI4-FVIP/AXI4/examples/axi_crossbar/axi_crossbar_rd.v", "target_type": "primary", "cursor_line": 311, "target_nlines": 1, "node_depth": 19, "node_path": ["source_file", "module_declaration", "generate_region", "loop_generate_construct", "generate_block", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "cond_predicate", "expression", "primary"], "target": "            if (rst) begin\n"}
{"file": "Saturn_MiSTer/rtl/pll.v", "target_type": "module_declaration", "cursor_line": 18, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\tpll_0002 pll_inst (\n\t\t.refclk            (refclk),            //            refclk.clk\n"}
{"file": "XT_RISC-V_Soc/RTL/RISC-V/Bus/WISHBONE_SYSCON.sv", "target_type": "module_declaration", "cursor_line": 2, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "    input clk,\n"}
{"file": "swerv_eh1/design/ifu/ifu.sv", "target_type": "primary_literal", "cursor_line": 401, "target_nlines": 1, "node_depth": 15, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "package_or_generate_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "expression", "expression", "expression", "primary", "select1", "bit_select1", "expression", "primary", "primary_literal"], "target": "      encode8_3[1] = in[7] | in[6] | in[3] | in[2];\n"}
{"file": "tiny-synth/examples/midi/tone_generator_fixed_param.vh", "target_type": "module_declaration", "cursor_line": 53, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n  wire [OUTPUT_BITS-1:0] wave_out;\n"}
{"file": "zynq-sandbox/hdl/reg_ifc.sv", "target_type": "port_identifier", "cursor_line": 38, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "interface_declaration", "modport_declaration", "modport_item", "modport_ports_declaration", "modport_simple_ports_declaration", "modport_simple_port", "port_identifier"], "target": "\toutput raddr, waddr, rd, wr, wdata,\n"}
{"file": "gateware/hdl/nexys4.sv", "target_type": "module_declaration", "cursor_line": 58, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\nreg [15:0]mem[0:4095];\n\nalways @(posedge clk) begin\n"}
{"file": "iDMA/test/idma_intf.sv", "target_type": "simple_identifier", "cursor_line": 71, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "interface_declaration", "interface_ansi_header", "parameter_port_list", "parameter_port_declaration", "parameter_declaration", "list_of_param_assignments", "param_assignment", "parameter_identifier", "simple_identifier"], "target": "    parameter int unsigned DataWidth   = 0,\n"}
{"file": "uvm_debug/src/cl_util.svh", "target_type": "simple_identifier", "cursor_line": 123, "target_nlines": 1, "node_depth": 16, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "conditional_statement", "cond_predicate", "expression", "expression", "primary", "simple_identifier"], "target": "      if ( end_pos >= len ) end_pos = len - 1;\n"}
{"file": "RISC-V-Vector/sva/vector_top_sva.sv", "target_type": "primary_literal", "cursor_line": 64, "target_nlines": 1, "node_depth": 12, "node_path": ["source_file", "package_or_generate_item_declaration", "net_declaration", "list_of_net_decl_assignments", "net_decl_assignment", "expression", "inside_expression", "open_range_list", "open_value_range", "value_range", "expression", "primary", "primary_literal"], "target": "                     7'b1111010\n"}
{"file": "RV12/rtl/verilog/core/cache/riscv_cache_setup.sv", "target_type": "module_declaration", "cursor_line": 57, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "  input  logic [XLEN     -1:0] d_i,\n"}
{"file": "kronos/rtl/peripherals/wb_spi_master.sv", "target_type": "module_declaration", "cursor_line": 80, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "    .full    (txq_full    ),\n    .empty   (txq_empty   ),\n"}
{"file": "FPGA_pract/Labs/04. LUTRAM BRAM/examples/03_bram_dp_simple/bram_dp_simple_2clk_tb.sv", "target_type": "module_declaration", "cursor_line": 21, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "    .RAM_ADDR_BITS ( RAM_ADDR_BITS )\n"}
{"file": "NanoMac/src/macplus/videoTimer.v", "target_type": "module_declaration", "cursor_line": 29, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\treg [9:0] xpos; // 0 ... 703\n\treg [8:0] ypos; // 0 ... 369\n"}
{"file": "APS/Labs/15. Programming device/bluster_pkg.sv", "target_type": "case_statement", "cursor_line": 47, "target_nlines": 5, "node_depth": 8, "node_path": ["source_file", "package_declaration", "package_or_generate_item_declaration", "task_declaration", "task_body_declaration", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "        else $error(\"Init message format is incorrect. Should be \\\"ready for flash starting from 0xADDR\\\"\");\n      end\n      FLASH_MSG_SIZE: begin\n        $display(\"%s\", str[0:FLASH_MSG_SIZE-2]);\n        assert((str[0:16] == \"finished write 0x\") && (str[25+:23] == \" bytes starting from 0x\"))begin end\n"}
{"file": "LainCore/rtl/utils/cam_cmp_lutram.sv", "target_type": "module_declaration", "cursor_line": 15, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "  logic [PACKS_OF_5_BITS-1:0][4:0] w_addr_q;\n  // 注意：若 w_addr_q 被清零，则出现错误，每次 UPDATE 时一定要清零上次的结果\n  assign key_o = w_addr_q;\n  logic refill_v_q, refill_q;\n"}
{"file": "tarsier/src/CornersAndDescriptorsTestbench.sv", "target_type": "module_declaration", "cursor_line": 88, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\t\trate_ctr <= rate_ctr + 1;\n"}
{"file": "FlooNoC/hw/test/floo_dma_test_node.sv", "target_type": "simple_identifier", "cursor_line": 92, "target_nlines": 1, "node_depth": 6, "node_path": ["source_file", "module_declaration", "text_macro_usage", "list_of_actual_arguments", "expression", "primary", "simple_identifier"], "target": "  `IDMA_TYPEDEF_FULL_REQ_T(idma_req_t, id_out_t, addr_t, tf_len_t)\n"}
{"file": "cv-hpdcache/rtl/src/utils/hpdcache_mem_to_axi_read.sv", "target_type": "case_statement", "cursor_line": 67, "target_nlines": 5, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "        case (axi_r_i.resp)\n            axi_pkg::RESP_SLVERR,\n            axi_pkg::RESP_DECERR: resp = HPDCACHE_MEM_RESP_NOK;\n            default:              resp = HPDCACHE_MEM_RESP_OK;\n        endcase\n"}
{"file": "TrivialMIPS/src/peripheral/graphics_controller.sv", "target_type": "module_declaration", "cursor_line": 98, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "                    if (dbus_last_stall) begin\r\n                        data_bus.data_rd <= gmem_data_out_a;\r\n                    end else begin\r\n                        if (data_bus.address == `GRAPHICS_CONFIG_ADDRESS) begin\r\n                            data_bus.data_rd <= pixel_offset_reg_o[1];\r\n"}
{"file": "lowrisc-chip/src/main/verilog/sd_data_serial_host.sv", "target_type": "primary", "cursor_line": 302, "target_nlines": 1, "node_depth": 12, "node_path": ["ERROR", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "primary"], "target": "                   transf_cnt_o <= transf_cnt_o + 16'h1;\n"}
{"file": "Superscalar-HIT-Core-NSCSCC2020/src/rtl/ifu/branch_predict.sv", "target_type": "module_declaration", "cursor_line": 158, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "    assign use_global_o = 1;\n    // Output logic\n    PredInfo pred_info_o;\n    assign pred_info_o.bht_index = pred_info_local_o.bht_index;\n    assign pred_info_o.pht_index = pred_info_local_o.pht_index;\n"}
{"file": "System-Verilog-Packet-Library/hdr_db/include/gcm-aes/sv-file/gcm_test.sv", "target_type": "variable_decl_assignment", "cursor_line": 35, "target_nlines": 1, "node_depth": 4, "node_path": ["source_file", "package_or_generate_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment"], "target": "  int         auth_only;\n"}
{"file": "NES_MiSTer/rtl/EEPROM_24C0x.sv", "target_type": "module_declaration", "cursor_line": 34, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "typedef enum bit [2:0] {\n\tSTATE_STANDBY,\n\tSTATE_TEST,\n\tSTATE_ADDRESS,\n"}
{"file": "BrianHG-DDR3-Controller/BrianHG_DDR3_CV_GFX_TEST_v16_1_LAYER_350MHz/I2C_Controller.v", "target_type": "case_statement", "cursor_line": 120, "target_nlines": 3, "node_depth": 18, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "\t6'd17  : SDO=SD[10];\r\n\t6'd18  : SDO=SD[9];\r\n\t6'd19  : SDO=SD[8];\r\n"}
{"file": "100DaysofRTL/day13/pedge_tb.sv", "target_type": "module_declaration", "cursor_line": 32, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\t#15 i_sig = 1'b0;\n"}
{"file": "ViT-FPGA-TPU/code/code_fpga/fpga/pci_mig_accelerator_1.0_32/src/accelerator_types.sv", "target_type": "simple_identifier", "cursor_line": 67, "target_nlines": 1, "node_depth": 5, "node_path": ["source_file", "package_or_generate_item_declaration", "net_declaration", "list_of_net_decl_assignments", "net_decl_assignment", "simple_identifier"], "target": "\t\toutput\tawvalid,\n"}
{"file": "sauria/RTL/src/sauria_core/systolic_array/multiplier/bam_cell.sv", "target_type": "module_declaration", "cursor_line": 43, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "logic [1:0] \tsum_result;\n\n// ---------------------\n// Combinational part\n"}
{"file": "riscv-iommu/vendor/axi_atop_filter.sv", "target_type": "module_declaration", "cursor_line": 399, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "  typedef logic [AXI_ID_WIDTH-1:0]     id_t;\n  typedef logic [AXI_ADDR_WIDTH-1:0]   addr_t;\n  typedef logic [AXI_DATA_WIDTH-1:0]   data_t;\n  typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;\n"}
{"file": "mega-ed-pub/fpga/mapper/lib_base/pi_map.sv", "target_type": "module_declaration", "cursor_line": 37, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\tassign map.ce_cfg\t \t= map.ce_sys & {pi_addr[15:3], 3'd0} == 16'h00f8;//8B \tsys config\n\tassign map.ce_sst\t \t= map.ce_sys & {pi_addr[15:8], 8'd0} == 16'h0100;//256B \tsave state data. 128B sniffer, 128B map regs\n\tassign map.ce_mst\t \t= map.ce_sys & {pi_addr[15:1], 1'd0} == 16'h0200;//2B \tmapper status\n\t\n\tassign map.ce_mcfg\t= map.ce_map & {pi_addr[15:8], 8'd0}  == 16'hff00;//256B\tmapper config.  \n"}
{"file": "tnCart/rtl/src/peripheral/signal/limiter.sv", "target_type": "module_declaration", "cursor_line": 69, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "    always_ff @(posedge CLK or negedge RESET_n) begin\n        if(!RESET_n)    OUT <= 0;\n        else            OUT <= (IN[IN_WIDTH-1:OUT_WIDTH-1] == sign_bits) ? IN[OUT_WIDTH-1:0] :\n                               (IN[IN_WIDTH-1:OUT_WIDTH-1] == zero_bits) ? IN[OUT_WIDTH-1:0] :\n                               (IN[IN_WIDTH-1])                          ? min : max;\n"}
{"file": "cv32e40x/sva/cv32e40x_debug_triggers_sva.sv", "target_type": "module_declaration", "cursor_line": 49, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "   input logic [31:0] trigger_match_if_wb,\n   input logic [31:0] trigger_match_ex_wb,\n   input logic        wb_valid_i,\n"}
{"file": "edn8-pro-pub/mappers/001/map_097.sv", "target_type": "module_declaration", "cursor_line": 17, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\tMemCtrl prg;\n"}
{"file": "zerowing/sys/shadowmask.sv", "target_type": "module_declaration", "cursor_line": 75, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n\tlut <= mask_lut[mask_idx];\n"}
{"file": "fpga-gameandwatch/platform/mimic/helpers/sys_umuldiv.sv", "target_type": "module_declaration", "cursor_line": 36, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "         output                       busy,\n\n         input          [NB_MUL1-1:0] mul1,\n         input          [NB_MUL2-1:0] mul2,\n         input           [NB_DIV-1:0] div,\n"}
{"file": "uvm-tutorial-for-candy-lovers/src/tutorial_28/design.sv", "target_type": "module_declaration", "cursor_line": 15, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "      jb_if.taste <= #2ns YUCKY;\r\n    else\r\n      jb_if.taste <= #2ns YUMMY;\r\n"}
{"file": "SoomRV/src/StoreQueue.sv", "target_type": "simple_identifier", "cursor_line": 147, "target_nlines": 1, "node_depth": 21, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "loop_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "loop_statement", "for_initialization", "for_variable_declaration", "simple_identifier"], "target": "    for (integer i = 0; i < NUM_OUT; i=i+1) begin\n"}
{"file": "The-FPGA-Programming-Handbook-Second-Edition/CH2/SystemVerilog/tb/tb.sv", "target_type": "module_declaration", "cursor_line": 29, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "  // Checking\n  always @(LED) begin\n"}
{"file": "The-FPGA-Programming-Handbook-Second-Edition/CH9/SystemVerilog/hdl/example_top.v", "target_type": "primary", "cursor_line": 1150, "target_nlines": 1, "node_depth": 10, "node_path": ["source_file", "module_declaration", "generate_region", "module_or_generate_item", "if_generate_construct", "generate_block", "continuous_assign", "list_of_net_assignments", "net_assignment", "expression", "primary"], "target": "        assign dbg_prbs_rdlvl_fine_dly_error            = dbg_prbs_rdlvl [254];\n"}
{"file": "cv32e40s/sva/cv32e40s_mpu_sva.sv", "target_type": "expression", "cursor_line": 196, "target_nlines": 1, "node_depth": 11, "node_path": ["source_file", "module_declaration", "generate_region", "interface_or_generate_item", "if_generate_construct", "generate_block", "concurrent_assertion_item", "assert_property_statement", "property_spec", "clocking_event", "event_expression", "expression"], "target": "        assert property (@(posedge clk) disable iff (!rst_n)\n"}
{"file": "axi/src/axi_chan_compare.sv", "target_type": "module_declaration", "cursor_line": 202, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "            automatic ar_chan_t ar_exp, ar_recv;\n            if (AllowReordering) begin\n                if (ar_queue[axi_b_req.ar.id].size() == 0) $error(\"AR queue is empty!\");\n                ar_exp = ar_queue[axi_b_req.ar.id].pop_front(); // verilog_lint: waive always-ff-non-blocking\n            end else begin\n"}
{"file": "axi/src/axi_id_prepend.sv", "target_type": "module_declaration", "cursor_line": 89, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "        mst_aw_chans_o[i].id = {pre_id_i, slv_aw_chans_i[i].id[AxiIdWidthSlvPort-1:0]};\n        mst_ar_chans_o[i].id = {pre_id_i, slv_ar_chans_i[i].id[AxiIdWidthSlvPort-1:0]};\n      end\n    end\n    // The ID is in the highest bits of the struct, so an assignment from a channel with a wide ID\n"}
{"file": "DisplayPort/gateware/src/pm/prt_dp_pm_top.sv", "target_type": "simple_identifier", "cursor_line": 592, "target_nlines": 1, "node_depth": 20, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "continuous_assign", "list_of_variable_assignments", "variable_assignment", "expression", "conditional_expression", "cond_predicate", "expression", "primary", "mintypmax_expression", "expression", "expression", "expression", "primary", "mintypmax_expression", "expression", "expression", "primary", "simple_identifier"], "target": "    assign msg_lb.rd    = ((hart_ram_if.rd_adr[15:14] == 'b11) && (hart_ram_if.rd_adr[8+:P_MAX_DEV_ADR] == P_MSG_BASE) && hart_ram_if.rd) ? 1 : 0;\n"}
{"file": "DisplayPort/gateware/src/scaler/prt_scaler_agnt_lut.sv", "target_type": "case_statement", "cursor_line": 229, "target_nlines": 4, "node_depth": 20, "node_path": ["source_file", "module_declaration", "generate_region", "module_or_generate_item", "if_generate_construct", "generate_block", "if_generate_construct", "generate_block", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "                {2'd3, 3'd4, 3'd1} : clk_dat <= {(P_MUX'(11)), (P_MUX'(10)), (P_MUX'(3)), (P_MUX'(2)), (P_COEF'(68)), (P_COEF'(67)), (P_COEF'(66)), (P_COEF'(65))};\n                {2'd3, 3'd4, 3'd2} : clk_dat <= {(P_MUX'(11)), (P_MUX'(10)), (P_MUX'(3)), (P_MUX'(2)), (P_COEF'(68)), (P_COEF'(67)), (P_COEF'(66)), (P_COEF'(65))};\n\n                default : clk_dat <= 'd0;\n"}
{"file": "eth_vlg/src/udp/udp_ifc.sv", "target_type": "simple_identifier", "cursor_line": 6, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "interface_declaration", "interface_or_generate_item", "package_or_generate_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "simple_identifier"], "target": "  logic      rdy;  // Data ready to IPv4\n"}
{"file": "eth_vlg/src/util/fifo_sc_ifc.sv", "target_type": "simple_identifier", "cursor_line": 1, "target_nlines": 1, "node_depth": 4, "node_path": ["source_file", "interface_declaration", "interface_nonansi_header", "interface_identifier", "simple_identifier"], "target": "interface fifo_sc_ifc\r\n"}
{"file": "enso/hardware/src/common/dc_fifo_reg_core.v", "target_type": "module_declaration", "cursor_line": 193, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "  test_fifo_0_altera_avalon_fifo_181_hicnqoy_dcfifo_with_controls the_dcfifo_with_controls\n    (\n      .data      (data),\n"}
{"file": "enso/hardware/src/hyper_pipe.sv", "target_type": "module_declaration", "cursor_line": 4, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "    parameter NUM_PIPES = 1)\n(\n    input clk,\n    input [WIDTH-1:0] din,\n    output [WIDTH-1:0] dout);\n"}
{"file": "CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2/rtl/phase_1/router_psum.sv", "target_type": "case_statement", "cursor_line": 98, "target_nlines": 5, "node_depth": 22, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "\t\t\t\t\t\t\tpsum_count <= 0;\n\t\t\t\t\t\t\tw_addr_glb_psum <= w_addr_glb_psum + 1;\n\t\t\t\t\t\t\titer <= iter + 1;\n\t\t\t\t\t\t\tstate <= IDLE;\n\t\t\t\t\t\tend else begin\n"}
{"file": "CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2/testbench/router_pe_4_clusters_tb.sv", "target_type": "simple_identifier", "cursor_line": 109, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "module_instantiation", "hierarchical_instance", "list_of_port_connections", "named_port_connection", "expression", "primary", "simple_identifier"], "target": "\t\t\t.west_enable_o_west_0(west_enable_o_west_0_whgt),\n"}
{"file": "Cores-VeeR-EL2/design/lsu/el2_lsu_stbuf.sv", "target_type": "primary_literal", "cursor_line": 302, "target_nlines": 1, "node_depth": 22, "node_path": ["ERROR", "expression", "conditional_expression", "cond_predicate", "expression", "conditional_expression", "cond_predicate", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "ERROR", "variable_lvalue", "select1", "constant_range", "constant_expression", "constant_primary", "primary_literal"], "target": "   assign ldst_byteen_ext_r[7:0] = ldst_byteen_r[7:0] << lsu_addr_r[1:0];\n"}
{"file": "Cores-VeeR-EL2/testbench/ahb_sif.sv", "target_type": "module_declaration", "cursor_line": 141, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "`endif\n\n"}
{"file": "cva5/core/execution_units/fp_unit/fp_div_sqrt_wrapper.sv", "target_type": "module_declaration", "cursor_line": 97, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "            wb.clz = div_wb.clz;\n"}
{"file": "cva5/core/fetch_stage/icache_tag_banks.sv", "target_type": "simple_identifier", "cursor_line": 36, "target_nlines": 1, "node_depth": 6, "node_path": ["source_file", "ERROR", "module_ansi_header", "list_of_port_declarations", "ansi_port_declaration", "port_identifier", "simple_identifier"], "target": "        input logic ifence,\n"}
{"file": "tnoc/env/bfm/tnoc_bfm_packet_vc_driver.svh", "target_type": "simple_identifier", "cursor_line": 85, "target_nlines": 1, "node_depth": 11, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "task_declaration", "task_body_declaration", "ERROR", "clockvar_expression", "select1", "member_identifier", "simple_identifier"], "target": "    seq_item_port.item_done();\n"}
{"file": "tnoc/rtl/axi_adapter/tnoc_axi_id_locker.sv", "target_type": "expression", "cursor_line": 35, "target_nlines": 1, "node_depth": 16, "node_path": ["source_file", "interface_declaration", "interface_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "cond_predicate", "expression"], "target": "    if (!i_rst_n) begin\n"}
{"file": "VeriGPU/prot/tasks_functs/prot_task_module_test.sv", "target_type": "module_declaration", "cursor_line": 29, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "        a = 3;\n        b = 2;\n        #1;\n        `assert(out == 1);\n"}
{"file": "VeriGPU/src/float/float_add_pipeline.sv", "target_type": "module_declaration", "cursor_line": 89, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "        n_new_mant = new_mant;\n        n_new_sign = new_sign;\n\n        n_out = '0;\n        n_ack = 0;\n"}
{"file": "intel-training-modules/RTL/examples/mmio_mc_read/hw/delay.sv", "target_type": "module_declaration", "cursor_line": 52, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n   generate\n      if (CYCLES == 0) begin\n\t assign data_out = data_in;\n"}
{"file": "intel-training-modules/RTL/exercises/mmio_fib/solution/hw/ccip_std_afu.sv", "target_type": "module_declaration", "cursor_line": 83, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "      .pck_af2cp_sTx_T1         (pck_af2cp_sTx)\n      );\n\n\n   // =============================================================\n"}
{"file": "common_cells/src/stream_fifo_optimal_wrap.sv", "target_type": "expression", "cursor_line": 87, "target_nlines": 1, "node_depth": 8, "node_path": ["ERROR", "module_or_generate_item", "concurrent_assertion_item", "checker_instantiation", "property_expr", "sequence_expr", "expression_or_dist", "expression", "expression"], "target": "    if (Depth > 32'd2) begin : gen_fifo\n"}
{"file": "common_cells/test/stream_test.sv", "target_type": "simple_identifier", "cursor_line": 60, "target_nlines": 1, "node_depth": 13, "node_path": ["source_file", "package_declaration", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "task_declaration", "task_body_declaration", "statement_or_null", "statement", "statement_item", "checker_instantiation", "checker_identifier", "simple_identifier"], "target": "      cycle_end();\n"}
{"file": "fwrisc/synth/microsemi/synplify/fwrisc/fwrisc_alu_op.svh", "target_type": "simple_identifier", "cursor_line": 16, "target_nlines": 1, "node_depth": 6, "node_path": ["source_file", "package_or_generate_item_declaration", "parameter_declaration", "list_of_param_assignments", "param_assignment", "parameter_identifier", "simple_identifier"], "target": "OP_GE  = (OP_LT+4'd1),\t// 8\n"}
{"file": "fwrisc/ve/fwrisc_fetch_formal/tests/fwrisc_fetch_formal_seqmix_test.sv", "target_type": "module_declaration", "cursor_line": 59, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\tend\n\t\n\treg[3:0] fetch_count;\n\treg iready_r;\n"}
{"file": "MiSTeryNano/src/tang/nano20k/gowin_clkdiv/gowin_clkdiv.v", "target_type": "module_declaration", "cursor_line": 24, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": ");\n\ndefparam clkdiv_inst.DIV_MODE = \"5\";\n"}
{"file": "MiSTeryNano/src/tang/nano20k/top_lcd.sv", "target_type": "module_declaration", "cursor_line": 99, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "  .pll_lock_main( pll_lock_32m ),\n  .por   ( por ),  \n\n  .leds_n ( leds_n ),\n"}
{"file": "fpga-tamagotchi/platform/mimic/pll/c5/pll_audio.v", "target_type": "module_declaration", "cursor_line": 12, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\t);\n\n\tpll_audio_0002 pll_audio_inst (\n"}
{"file": "fpga-tamagotchi/rtl/test/unit/instructions/cp_tb.sv", "target_type": "module_declaration", "cursor_line": 8, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n  function [1:0] cp_flags(reg [3:0] a, reg [3:0] b);\n    if (a > b) begin\n"}
{"file": "sargantana/rtl/datapath/rtl/exe_stage/rtl/fpu/fpnew_rounding.sv", "target_type": "module_declaration", "cursor_line": 21, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "  input logic                  sign_i,\n  // Rounding information\n"}
{"file": "sargantana/rtl/datapath/rtl/exe_stage/rtl/mul_unit.sv", "target_type": "case_statement", "cursor_line": 246, "target_nlines": 4, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "        default: begin\n            result_64 = 64'b0;\n        end\n    endcase\n"}
{"file": "zcash-fpga/ip_cores/util/src/rtl/barret_mod.sv", "target_type": "case_statement", "cursor_line": 129, "target_nlines": 5, "node_depth": 39, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement", "case_item", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "          case(prev_state)\n            S0: c2 <= mult_out_if.dat;\n            S2: c4 <= c4 - mult_out_if.dat;\n            default: begin end     \n          endcase\n"}
{"file": "zcash-fpga/zcash_fpga/src/rtl/bls12_381/bls12_381_top.sv", "target_type": "case_statement", "cursor_line": 612, "target_nlines": 3, "node_depth": 9, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "package_or_generate_item_declaration", "task_declaration", "task_body_declaration", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "         data_ram_sys_if.a <= curr_inst.a;\r\n         data_ram_read[0] <= 1;\r\n         cnt <= 5;\r\n"}
{"file": "bsg_manycore/v/bsg_manycore_tile_vcache.sv", "target_type": "variable_decl_assignment", "cursor_line": 165, "target_nlines": 1, "node_depth": 4, "node_path": ["source_file", "package_or_generate_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment"], "target": "  logic v_we_lo;\n"}
{"file": "bsg_manycore/v/chip/bsg_manycore_hor_io_router_column.sv", "target_type": "data_type", "cursor_line": 84, "target_nlines": 1, "node_depth": 2, "node_path": ["ERROR", "data_type_or_implicit1", "data_type"], "target": "    assign hor_link_sif_o[i][W] = link_sif_lo[i][W];\n"}
{"file": "pzbcm/pzbcm_arbiter/pzbcm_matrix_arbiter.sv", "target_type": "module_declaration", "cursor_line": 188, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "    .i_busy             (busy             ),\n    .i_request          (i_request        ),\n    .i_grant            (grant[1]         ),\n    .i_priority_matrix  (priority_matrix  )\n  );\n"}
{"file": "pzbcm/pzcorebus_m_to_1_switch/pzcorebus_request_m_to_1_switch.sv", "target_type": "module_declaration", "cursor_line": 127, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "      done[1] = switch_if[SLAVES].command_with_data_ack() && data_done;\n      done[2] = switch_if[SLAVES].write_data_last_ack() && command_done;\n    end\n"}
{"file": "nontrivial-mips/src/cpu/mmu/tlb.sv", "target_type": "module_declaration", "cursor_line": 27, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "generate\n\tfor(i = 0; i < `TLB_ENTRIES_NUM; ++i)\n\tbegin: gen_for_tlb\n\t\talways_ff @(posedge clk) begin\n\t\t\tif(rst) begin\n"}
{"file": "nontrivial-mips/vivado/ip_repo/usb_host_controller/usbh_crc5.v", "target_type": "module_declaration", "cursor_line": 55, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\nassign crc_o[3] =    data_i[10] ^ data_i[9] ^ data_i[8] ^ data_i[7] ^ data_i[4] ^ data_i[3] ^ data_i[1] ^ \n                       crc_i[1] ^ crc_i[2] ^ crc_i[3] ^ crc_i[4];\n"}
{"file": "sv-tutorial/testbenches/uvm/agents/axi4_stream_if.sv", "target_type": "expression", "cursor_line": 33, "target_nlines": 1, "node_depth": 17, "node_path": ["source_file", "interface_declaration", "interface_or_generate_item", "initial_construct", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "system_tf_call", "list_of_arguments_parent", "expression"], "target": "        if (DATA_WIDTH % 8 != 0) $fatal(1, $sformatf(\"AXI DATA_WIDTH=%0d is not byte aligned\", DATA_WIDTH));        \n"}
{"file": "sv-tutorial/testbenches/uvm/multiple_tests/accum_env.svh", "target_type": "expression", "cursor_line": 45, "target_nlines": 1, "node_depth": 7, "node_path": ["ERROR", "function_statement_or_null", "function_statement", "statement", "statement_item", "blocking_assignment", "operator_assignment", "expression"], "target": "        agent_in = axi4_stream_agent#(accum_tb_pkg::INPUT_WIDTH)::type_id::create(\"agent_in\", this);        \n"}
{"file": "logic/rtl/logic/axi4/lite/bus/logic_axi4_lite_bus_main.sv", "target_type": "simple_identifier", "cursor_line": 60, "target_nlines": 1, "node_depth": 5, "node_path": ["source_file", "package_or_generate_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "simple_identifier"], "target": "    multi_slave (\n"}
{"file": "logic/tests/logic/basic/gray2binary/logic_basic_gray2binary_unit_test.sv", "target_type": "module_declaration", "cursor_line": 25, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "    string name = \"logic_basic_gray2binary_unit_test\";\n    svunit_testcase svunit_ut;\n\n    parameter WIDTH = 16;\n"}
{"file": "openhmc/rtl/hmc_controller/rx/rx_descrambler.v", "target_type": "primary", "cursor_line": 119, "target_nlines": 1, "node_depth": 20, "node_path": ["ERROR", "interface_or_generate_item", "continuous_assign", "list_of_net_assignments", "net_assignment", "expression", "primary", "concatenation", "expression", "primary", "mintypmax_expression", "expression", "primary", "function_subroutine_call", "subroutine_call", "tf_call", "list_of_arguments_parent", "ERROR", "expression", "expression", "primary"], "target": "            lfsr     <= 15'h0;\n"}
{"file": "openhmc/sim/UVC/hmc/sv/hmc_requester_driver.sv", "target_type": "case_statement", "cursor_line": 80, "target_nlines": 5, "node_depth": 24, "node_path": ["ERROR", "class_item", "class_method", "task_declaration", "task_body_declaration", "statement_or_null", "statement", "statement_item", "loop_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "par_block", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "\t\t\t\t\t\tNULL_FLITS_2: null_flits_2();\n\t\t\t\t\t\tINITIAL_TRETS: initial_trets();\n\t\t\t\t\t\tLINK_UP: link_up();\n\t\t\t\t\t\tSTART_RETRY_INIT: start_retry_init();\n\t\t\t\t\t\tCLEAR_RETRY: clear_retry();\n"}
{"file": "esnet-smartnic-hw/src/p4_proc/tests/p4_proc_datapath/p4_proc_datapath_unit_test.sv", "target_type": "module_declaration", "cursor_line": 316, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "module p4_proc_datapath_hdrlen_0_unit_test;\n`P4_PROC_DATAPATH_UNIT_TEST(0)\nendmodule\n"}
{"file": "esnet-smartnic-hw/src/vitisnetp4/verif/include/vitisnetp4_agent__legacy.svh", "target_type": "case_statement", "cursor_line": 147, "target_nlines": 2, "node_depth": 13, "node_path": ["ERROR", "function_statement_or_null", "function_statement", "statement", "statement_item", "loop_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "                   parse_match_fields(table_format_str, cli_cmd.match_fields, key, mask);\n                   if (VERBOSE) begin\n"}
{"file": "intel-fpga-bbb/BBB_cci_mpf/hw/rtl/cci-mpf-if/ofs_plat_ccip_if_to_mpf.sv", "target_type": "module_declaration", "cursor_line": 63, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "            (* preserve *) t_if_ccip_Tx reg_af2cp_sTx[N_REG_STAGES];\n\n            // Tx to register stages\n"}
{"file": "intel-fpga-bbb/BBB_cci_mpf/hw/rtl/cci-mpf-shims/cci_mpf_shim_pwrite/cci_mpf_shim_pwrite.vh", "target_type": "port_identifier", "cursor_line": 126, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "interface_declaration", "modport_declaration", "modport_item", "modport_ports_declaration", "modport_simple_ports_declaration", "modport_simple_port", "port_identifier"], "target": "        output lock_idx,\n"}
{"file": "NTUEE_DIGITAL_CIRCUIT_LAB_24FALL/Lab2/src/Rsa256Core.sv", "target_type": "case_statement", "cursor_line": 339, "target_nlines": 4, "node_depth": 14, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "\t\tcase(state_r)\n\t\t\tS_CALC:  counter_w = counter_r + 1;\n\t\t\tdefault: counter_w = 0;\n\t\tendcase\n"}
{"file": "NTUEE_DIGITAL_CIRCUIT_LAB_24FALL/Resources/audio/audio.sv", "target_type": "case_statement", "cursor_line": 113, "target_nlines": 5, "node_depth": 14, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "\t\tcase(state_r)\n\t\t\tS_I2C: begin\n\t\t\t\tif(i2c_done) state_w = S_PLAY;\n\t\t\t\telse         state_w = S_I2C;\n\t\t\tend\n"}
{"file": "UVM-Examples/projects/ahb2_uvm_tb/ahb_slave_agent/ahb_smonitor.svh", "target_type": "simple_identifier", "cursor_line": 41, "target_nlines": 1, "node_depth": 4, "node_path": ["source_file", "ERROR", "ERROR", "class_identifier", "simple_identifier"], "target": "        function void ahb_smonitor::build_phase(uvm_phase phase);\n"}
{"file": "UVM-Examples/projects/spi_uvm_tb/spi_env/spi_subscriber.svh", "target_type": "simple_identifier", "cursor_line": 9, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "function_declaration", "function_body_declaration", "function_identifier", "function_identifier", "simple_identifier"], "target": "\tfunction void write(spi_transaction t);\n"}
{"file": "S32X_MiSTer/rtl/32X/VDPFIFO.v", "target_type": "module_declaration", "cursor_line": 59, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\twire  empty = sub_wire0;\n\twire  full = sub_wire1;\n"}
{"file": "S32X_MiSTer/rtl/GEN/jt12/jt12_dout.v", "target_type": "case_statement", "cursor_line": 38, "target_nlines": 5, "node_depth": 14, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "    casez( addr )\n        2'b00: dout <= {busy, 5'd0, flag_B, flag_A }; // YM2203\n        2'b01: dout <= (use_ssg  ==1) ? psg_dout : {busy, 5'd0, flag_B, flag_A };\n        2'b1?: dout <= (use_adpcm==1) ?\n            { adpcmb_flag, 1'b0, adpcma_flags } :\n"}
{"file": "ece_4305/M6 to M7 - Vanilla System/HDL/mmio_sys_vanilla.sv", "target_type": "module_declaration", "cursor_line": 50, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "    .slot_wr_data_array(wr_data_array)\r\n    );\r\n"}
{"file": "ece_4305/M8 to M 13 - Sampler System/HDL/uart/baud_gen.sv", "target_type": "module_declaration", "cursor_line": 26, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "   assign tick = (r_reg==1);\r\nendmodule"}
{"file": "100-Days-of-RTL-code/Assertions_Example_1 [DAY-84] /ass.sv", "target_type": "module_declaration", "cursor_line": 5, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "  bit clk, a;  \n  always #5 clk = ~clk; //clock generation \n  \n  initial begin \n         a = 1; \n"}
{"file": "100-Days-of-RTL-code/jk_flipflop [DAY 2]/jk_ff_tb.v", "target_type": "module_declaration", "cursor_line": 13, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "initial \nbegin\n  clk=0;\n     forever #10 clk = ~clk;  \nend \n"}
{"file": "cv32e40p/rtl/vendor/pulp_platform_fpnew/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_top.v", "target_type": "simple_identifier", "cursor_line": 117, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "package_or_generate_item_declaration", "net_declaration", "list_of_net_decl_assignments", "net_decl_assignment", "simple_identifier"], "target": "wire            ctrl_xx_ex1_warm_up;                 \n"}
{"file": "cv32e40p/scripts/lint/cv32e40p_wrapper.sv", "target_type": "module_declaration", "cursor_line": 119, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "      .fetch_enable_i(fetch_enable_i),\n      .core_sleep_o  (core_sleep_o)\n  );\n\n"}
{"file": "croc/rtl/common_cells/addr_decode_napot.sv", "target_type": "module_declaration", "cursor_line": 76, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "    .NoIndices ( NoIndices    ) ,\n    .NoRules   ( NoRules      ),\n    .addr_t    ( addr_t       ),\n    .rule_t    ( rule_range_t ),\n"}
{"file": "croc/rtl/common_cells/cf_math_pkg.sv", "target_type": "simple_identifier", "cursor_line": 23, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "package_declaration", "package_or_generate_item_declaration", "function_declaration", "function_body_declaration", "tf_port_list", "tf_port_item1", "port_identifier", "simple_identifier"], "target": "    function automatic integer ceil_div (input longint dividend, input longint divisor);\n"}
{"file": "uvmprimer/11_UVM_Test/tb_classes/coverage.svh", "target_type": "primary", "cursor_line": 76, "target_nlines": 1, "node_depth": 12, "node_path": ["source_file", "ERROR", "expression", "primary", "concatenation", "ERROR", "expression", "expression", "primary", "mintypmax_expression", "expression", "expression", "primary"], "target": "                       (binsof (a_leg.zeros) || binsof (b_leg.zeros));\n"}
{"file": "uvmprimer/17_Interthread_Communication/02_Blocking/consumer.svh", "target_type": "simple_identifier", "cursor_line": 36, "target_nlines": 1, "node_depth": 2, "node_path": ["ERROR", "ERROR", "simple_identifier"], "target": "   endtask : run_phase\n"}
{"file": "UVMCourse/reporting/uvm_actions/example1/actions_example1.sv", "target_type": "module_declaration", "cursor_line": 45, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n  //Do nohing when error message occured\n  rpt1.set_report_severity_action(UVM_ERROR,UVM_NO_ACTION);\n"}
{"file": "UVMCourse/stimuls_generation/sequence_arbitration/UVM_SEQ_ARB_STRICT_RANDOM/without_priority/env.sv", "target_type": "port_identifier", "cursor_line": 4, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "class_constructor_declaration", "tf_port_list", "tf_port_item1", "port_identifier"], "target": "  function new(input string inst = \"ENV\", uvm_component c);\n"}
{"file": "SuperScalar-RISCV-CPU/ssrv-on-scr1/fpga/rtl/instrman.v", "target_type": "expression", "cursor_line": 62, "target_nlines": 1, "node_depth": 5, "node_path": ["source_file", "package_or_generate_item_declaration", "net_declaration", "list_of_net_decl_assignments", "net_decl_assignment", "expression"], "target": "\tassign            imem_addr = fetch_addr & `PC_ALIGN;\t\t\n"}
{"file": "SuperScalar-RISCV-CPU/ssrv-on-scr1/fpga/scr1/pipeline/scr1_pipe_idu.sv", "target_type": "simple_identifier", "cursor_line": 576, "target_nlines": 1, "node_depth": 5, "node_path": ["source_file", "package_or_generate_item_declaration", "net_declaration", "list_of_net_decl_assignments", "net_decl_assignment", "simple_identifier"], "target": "                                idu2exu_cmd.imm         = {27'd0, instr[6:2]};\n"}
{"file": "aws-fpga/hdk/cl/examples/cl_sde/design/sde_ps_acc.sv", "target_type": "module_declaration", "cursor_line": 76, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n   always_comb begin\n     pcis_wr_num_dw_d = '0;\n     for (int dw_idx = 0; dw_idx < (PCIS_DATA_WIDTH>>5); dw_idx++)\n"}
{"file": "aws-fpga/hdk/common/shell_stable/design/sh_ddr/synth/ccf_ctl.v", "target_type": "primary", "cursor_line": 39, "target_nlines": 1, "node_depth": 78, "node_path": ["source_file", "package_or_generate_item_declaration", "net_declaration", "list_of_net_decl_assignments", "net_decl_assignment", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "expression", "primary"], "target": "aLSmfQSdIa4UaWLr4ca1tfQgyZHhY/95O8y9ZHPEIeoSYBnynHxc9TcItYNWbg/yUtwqhocgPjMI\n"}
{"file": "black-parrot/bp_me/src/v/cce/bp_cce_spec_bits.sv", "target_type": "primary", "cursor_line": 33, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "package_or_generate_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "ERROR", "expression", "primary"], "target": "    , localparam hash_idx_width_lp = $clog2((2**lg_cce_way_groups_lp+num_cce_p-1)/num_cce_p)\n"}
{"file": "black-parrot/bp_top/src/v/bp_core_tile.sv", "target_type": "simple_identifier", "cursor_line": 330, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "module_instantiation", "hierarchical_instance", "list_of_port_connections", "named_port_connection", "port_identifier", "simple_identifier"], "target": "    ,.pr_ready_and_i(lce_req_ready_and_lo)\n"}
{"file": "FPGA-OS/app/memcached/hls/rtl/memcachedBuddy_top.v", "target_type": "primary", "cursor_line": 283, "target_nlines": 1, "node_depth": 8, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "module_instantiation", "hierarchical_instance", "list_of_port_connections", "named_port_connection", "expression", "primary"], "target": " .S00_AXI_0_arready  (axi2dram_ht_arready),\n"}
{"file": "FPGA-OS/system/vcu118/tb/top_axi_mac_tb.v", "target_type": "case_statement", "cursor_line": 1598, "target_nlines": 1, "node_depth": 13, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "package_or_generate_item_declaration", "task_declaration", "task_body_declaration", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "            3'b011  : disparity_pos_out = pdes6;\n"}
{"file": "FDU1.1-NSCSCC/superscalar_inorder_bpb/bpb/bpb_line0.sv", "target_type": "case_statement", "cursor_line": 45, "target_nlines": 4, "node_depth": 26, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "procedural_timing_control_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "                            2'b00: state = (destpc_commit.taken) ? (2'b01) : (2'b00);\n                            2'b01: state = (destpc_commit.taken) ? (2'b11) : (2'b00);\n                            2'b10: state = (destpc_commit.taken) ? (2'b11) : (2'b00);\n                            2'b11: state = (destpc_commit.taken) ? (2'b11) : (2'b10);                        \n"}
{"file": "FDU1.1-NSCSCC/superscalar_inorder_bpb/top/readdata_format.sv", "target_type": "case_statement", "cursor_line": 34, "target_nlines": 5, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "                        rd = _rd;\n                    end\n                endcase\n            end\n            LHU: begin\n"}
{"file": "svunit/test/frmwrk_4/another_test/test0.sv", "target_type": "simple_identifier", "cursor_line": 1, "target_nlines": 1, "node_depth": 4, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_identifier", "simple_identifier"], "target": "class test0;\n"}
{"file": "svunit/test/sim_11/dut.sv", "target_type": "simple_identifier", "cursor_line": 1, "target_nlines": 1, "node_depth": 4, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_identifier", "simple_identifier"], "target": "class dut;\n"}
{"file": "prjuray/minitests/opentitan/src.vivado/lowrisc_ip_usbdev_0.1/rtl/usbdev_flop_2syncpulse.sv", "target_type": "module_declaration", "cursor_line": 22, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "    .q (d_sync)\n  );\n\n  // delay d_sync by 1 cycle\n  logic [Width-1:0] d_sync_q;\n"}
{"file": "prjuray/minitests/opentitan/src.vivado/lowrisc_prim_xilinx_clock_mux2_0/rtl/prim_xilinx_clock_mux2.sv", "target_type": "module_declaration", "cursor_line": 11, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "  output logic clk_o\n);\n\n  // for more info, refer to the Xilinx technology primitives userguide, e.g.:\n  // ug953-vivado-7series-libraries.pdf\n"}
{"file": "antikernel-ipcores/serdes/linecode/Gearbox32PlusHeaderTo32.sv", "target_type": "module_declaration", "cursor_line": 57, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n\t\ttx_33b_data_valid\t<= 0;\n\n\t\tif(tx_header_valid && tx_data_valid) begin\n\t\t\ttx_33b_data_valid\t<= 1;\n"}
{"file": "antikernel-ipcores/serdes/linecode/Gearbox32ToN.sv", "target_type": "module_declaration", "cursor_line": 56, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\t\t\tdata_in_flip[i] \t<= data_in[(IN_WIDTH-1) - i];\n\t\tdata_in_flip_valid\t\t<= valid_in;\n"}
{"file": "cvw/src/generic/mux.sv", "target_type": "module_declaration", "cursor_line": 54, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "module mux5 #(parameter WIDTH = 8) (\n  input  logic [WIDTH-1:0] d0, d1, d2, d3, d4,\n  input  logic [2:0]       s,\n"}
{"file": "cvw/src/ieu/aes/rconlut32.sv", "target_type": "case_statement", "cursor_line": 48, "target_nlines": 1, "node_depth": 6, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "case_statement"], "target": "      default : rcon8 = 8'h00;\n"}
{"file": "wav-lpddr-hw/rtl/wddr/ddr_dfi_csr.sv", "target_type": "case_statement", "cursor_line": 106, "target_nlines": 3, "node_depth": 10, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "always_construct", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "         `DDR_DFI_STATUS_IF_EVENT_1_CFG_ADR : decode = DECODE_DDR_DFI_STATUS_IF_EVENT_1_CFG;\n         `DDR_DFI_CTRLUPD_IF_CFG_ADR : decode = DECODE_DDR_DFI_CTRLUPD_IF_CFG;\n         `DDR_DFI_CTRLUPD_IF_STA_ADR : decode = DECODE_DDR_DFI_CTRLUPD_IF_STA;\n"}
{"file": "wav-lpddr-hw/verif/sv/agents/APB/APB_agent/wav_APB_agent.sv", "target_type": "expression", "cursor_line": 42, "target_nlines": 1, "node_depth": 21, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_method", "function_declaration", "function_body_declaration", "function_statement_or_null", "function_statement", "statement", "statement_item", "conditional_statement", "statement_or_null", "statement", "statement_item", "seq_block", "statement_or_null", "statement", "statement_item", "blocking_assignment", "operator_assignment", "expression"], "target": "      sequencer = wav_APB_sequencer::type_id::create(\"sequencer\", this);\n"}
{"file": "cgra4ml/deepsocflow/rtl/sys/axi_int_reg_cgra4ml.sv", "target_type": "expression", "cursor_line": 427, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "module_declaration", "module_or_generate_item", "module_instantiation", "hierarchical_instance", "list_of_port_connections", "named_port_connection", "expression"], "target": "    .s_axis_read_desc_tag({TAG_WIDTH{1'b0}}),\n"}
{"file": "cgra4ml/ibex-soc/vendor/lowrisc_ip/ip/prim/rtl/prim_intr_hw.sv", "target_type": "module_declaration", "cursor_line": 72, "target_nlines": 3, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "    logic [Width-1:0] test_q; // Storing test. Cleared by SW\n\n    always_ff @(posedge clk_i or negedge rst_ni) begin\n"}
{"file": "FEC/rtl/gsfc_ldpc/dec/gsfc_ldpc_dec_mem.sv", "target_type": "simple_identifier", "cursor_line": 136, "target_nlines": 1, "node_depth": 5, "node_path": ["ERROR", "port_declaration", "input_declaration", "list_of_port_identifiers", "port_identifier", "simple_identifier"], "target": "  input  mem_sela_t                  irsela       [pC][pW][pLLR_BY_CYCLE][pNODE_BY_CYCLE] ;\n"}
{"file": "FEC/rtl/gsfc_ldpc/gsfc_ldpc_parameters.svh", "target_type": "primary", "cursor_line": 66, "target_nlines": 1, "node_depth": 18, "node_path": ["source_file", "package_or_generate_item_declaration", "net_declaration", "list_of_net_decl_assignments", "net_decl_assignment", "expression", "primary", "assignment_pattern_expression", "assignment_pattern", "expression", "primary", "assignment_pattern_expression", "assignment_pattern", "expression", "primary", "assignment_pattern_expression", "assignment_pattern", "expression", "primary"], "target": "      '{192, 414}\n"}
{"file": "hero/hardware/deps/pulp_cluster/rtl/cluster_clock_gate.sv", "target_type": "module_declaration", "cursor_line": 32, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "  output logic                cluster_clk_o\n\n);\n\n  logic s_somebusy;\n"}
{"file": "hero/hardware/deps/scm/latch_scm/register_file_1w_multi_port_read.sv", "target_type": "module_declaration", "cursor_line": 19, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "(\n    input  logic                                   clk,\n    input  logic                                   rst_n,\n    input  logic                                   test_en_i,\n\n"}
{"file": "SSRL_work/lpddr4_memory_controller/wav-lpddr-hw/rtl/ibex/prim_assert.sv", "target_type": "simple_identifier", "cursor_line": 45, "target_nlines": 1, "node_depth": 4, "node_path": ["source_file", "text_macro_definition", "text_macro_name", "text_macro_identifier", "simple_identifier"], "target": "`define ASSERT_DEFAULT_CLK clk_i\n"}
{"file": "SSRL_work/lpddr4_memory_controller/wav-lpddr-hw/rtl/wddr/ddr_dfi_ahb_csr.sv", "target_type": "module_declaration", "cursor_line": 101, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "   );\n\n   ddr_dfi_csr #(\n      .AWIDTH(AWIDTH),\n"}
{"file": "core-v-mcu/rtl/logint_dc_fifo_xbar/dc_data_buffer.sv", "target_type": "module_declaration", "cursor_line": 39, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "            if (write_enable)\n                data[write_pointer_bin] <= write_data;\n    end\n\n"}
{"file": "core-v-mcu/rtl/vendor/pulp_platform_common_cells/formal/fifo_v3_properties.sv", "target_type": "module_declaration", "cursor_line": 61, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "    assume property (@(posedge clk_i) (!init) |-> !rst_ni);\n\n    // we don't have tests for FALL_THROUGH mode\n    always_comb assert (FALL_THROUGH == 1'b0);\n\n"}
{"file": "uvm_tb_gen/part1/uvm_callback/dadd_environment.sv", "target_type": "variable_decl_assignment", "cursor_line": 21, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "class_property", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment"], "target": "    dadd_oagent oagt;\n"}
{"file": "uvm_tb_gen/part3/dv/vip/apb_vip/apb_master/apb_master_config.sv", "target_type": "primary", "cursor_line": 21, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "package_or_generate_item_declaration", "class_declaration", "class_item", "text_macro_usage", "list_of_actual_arguments", "expression", "primary"], "target": "         `uvm_field_enum(bool,use_reg_model,UVM_ALL_ON)\n"}
{"file": "basejump_stl/hard/generic/bsg_mem/bsg_mem_1r1w_sync_mask_write_bit_macros.svh", "target_type": "simple_identifier", "cursor_line": 3, "target_nlines": 1, "node_depth": 4, "node_path": ["source_file", "text_macro_definition", "text_macro_name", "text_macro_identifier", "simple_identifier"], "target": "`define BSG_MEM_1R1W_SYNC_MASK_WRITE_BIT_MACROS_VH\n"}
{"file": "basejump_stl/testing/bsg_dataflow/bsg_fifo_1r1w_small_hardened/bsg_fifo_1r1w_small_hardened_tester.sv", "target_type": "module_declaration", "cursor_line": 188, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "    master_en = 0;\n"}
{"file": "UVM/distrib/examples/simple/registers/primer/test.sv", "target_type": "simple_identifier", "cursor_line": 55, "target_nlines": 1, "node_depth": 7, "node_path": ["source_file", "package_or_generate_item_declaration", "data_declaration", "data_type_or_implicit1", "data_type", "class_type", "class_identifier", "simple_identifier"], "target": "   uvm_config_db#(apb_vif)::set(env, \"apb\", \"vif\", $root.tb_top.apb0);\n"}
{"file": "UVM/tests/03data/05staticarray/04arrayobject_cfg/test.sv", "target_type": "module_declaration", "cursor_line": 71, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "  container cfg_container = new;\n"}
{"file": "uvm/distrib/examples/simple/tlm2/blocking_simple/target.sv", "target_type": "case_statement", "cursor_line": 42, "target_nlines": 1, "node_depth": 9, "node_path": ["source_file", "ERROR", "class_item", "class_method", "task_declaration", "task_body_declaration", "statement_or_null", "statement", "statement_item", "case_statement"], "target": "          else m_data = rw.data;\n"}
{"file": "uvm/tests/XXfail/10comfail/test.sv", "target_type": "simple_identifier", "cursor_line": 27, "target_nlines": 1, "node_depth": 12, "node_path": ["source_file", "program_declaration", "non_port_program_item", "initial_construct", "statement_or_null", "statement", "statement_item", "seq_block", "block_item_declaration", "data_declaration", "list_of_variable_decl_assignments", "variable_decl_assignment", "simple_identifier"], "target": "   uvm_component comp;\n"}
{"file": "basics-graphics-music/boards/terasic_sockit/board_specific_top.sv", "target_type": "module_declaration", "cursor_line": 15, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "              screen_width  = 640,\n"}
{"file": "basics-graphics-music/boards/zzz_postponed_and_retired/tang_nano_1k/board_specific_top.sv", "target_type": "module_declaration", "cursor_line": 109, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n    tm1638_board_controller\n    # (\n        .clk_mhz ( clk_mhz    ),\n"}
{"file": "verilog-mode/tests/ExampOutput.v", "target_type": "module_declaration", "cursor_line": 1, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "        module InstModule (output o);\n        endmodule\n"}
{"file": "verilog-mode/tests/autoreg_smith_multiassign.v", "target_type": "module_declaration", "cursor_line": 15, "target_nlines": 2, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\n   output [1:0] one;\n"}
{"file": "openeye-CamSI/0.doc/Puzhitech/Examples/3_13_PZ_SD/PZ_SD.ip_user_files/ip/clk_ref/clk_ref_clk_wiz.v", "target_type": "module_declaration", "cursor_line": 160, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "    .CLKIN2              (1'b0),\n"}
{"file": "openeye-CamSI/0.doc/Trenz/CPLD/CPLD-sources---SC-PRJ-TEB0707-02_CCB0707-01_20200702/altera_int_osc.v", "target_type": "module_declaration", "cursor_line": 52, "target_nlines": 4, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "\tassign clkout = wire_clkout;\n\t\t\n\t// -------------------------------------------------------------------\n\t// Instantiate wysiwyg for chipidblock according to device family\n"}
{"file": "caliptra-rtl/src/caliptra_prim/rtl/caliptra_prim_pkg.sv", "target_type": "primary_literal", "cursor_line": 12, "target_nlines": 1, "node_depth": 11, "node_path": ["source_file", "package_declaration", "package_or_generate_item_declaration", "data_declaration", "type_declaration", "data_type", "enum_base_type", "packed_dimension", "constant_range", "constant_expression", "constant_primary", "primary_literal"], "target": "  typedef enum logic [31:0] {\n"}
{"file": "caliptra-rtl/src/caliptra_tlul/rtl/caliptra_tlul_cmd_intg_chk.sv", "target_type": "module_declaration", "cursor_line": 42, "target_nlines": 5, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "  //VCS coverage off\n  // pragma coverage off\n  assign err_o = tl_i.a_valid & (|err | (|data_err));\n  //VCS coverage on\n  // pragma coverage on\n"}
{"file": "verilator/test_regress/t/t_event.v", "target_type": "simple_identifier", "cursor_line": 47, "target_nlines": 1, "node_depth": 11, "node_path": ["ERROR", "module_or_generate_item", "case_generate_construct", "case_generate_item", "generate_block", "interface_or_generate_item", "if_generate_construct", "constant_expression", "constant_expression", "constant_primary", "parameter_identifier", "simple_identifier"], "target": "            if (last_event != 0) $stop;\n"}
{"file": "verilator/test_regress/t/t_hier_block_chained.v", "target_type": "module_declaration", "cursor_line": 213, "target_nlines": 1, "node_depth": 1, "node_path": ["source_file", "module_declaration"], "target": "   always @ (posedge clk) v1_7 <= v0_56 + v0_57 + v0_58 + v0_59 + v0_60 + v0_61 + v0_62 + v0_63;\n"}