Datasets:
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d6720f3 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 | {"file": "CGRAs/src/main/scala/Alu.scala", "target_type": "function_definition", "cursor_line": 43, "target_nlines": 1, "node_depth": 2, "node_path": ["compilation_unit", "block", "function_definition"], "target": " def AND = 6.U // And \n"}
{"file": "CGRAs/src/main/scala/CellProcessing.scala", "target_type": "class_definition", "cursor_line": 149, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " joinDin2Valid := eb2.io.doutValid\n"}
{"file": "CGRAs/src/main/scala/ConfMux.scala", "target_type": "object_definition", "cursor_line": 69, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object ConfMuxMain extends App {\n println(\"Generating the hardware\")\n (new chisel3.stage.ChiselStage).emitVerilog(new ConfMux(2, 1), Array(\"--target-dir\", \"generated\"))\n}\n"}
{"file": "CGRAs/src/main/scala/DEb.scala", "target_type": "class_definition", "cursor_line": 79, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " io.dout := regDin1\n"}
{"file": "CGRAs/src/main/scala/DFifo.scala", "target_type": "class_definition", "cursor_line": 37, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class DFifo\n"}
{"file": "CGRAs/src/main/scala/DFifoImp.scala", "target_type": "class_definition", "cursor_line": 43, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " extends BlackBox(Map(\"dataWidth\" -> dataWidth, \"fifoDepth\" -> fifoDepth)) with HasBlackBoxResource{ \n val io = IO(new Bundle {\n"}
{"file": "CGRAs/src/main/scala/DReg.scala", "target_type": "block", "cursor_line": 56, "target_nlines": 4, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when (io.doutReady === true.B) {\n data := io.din\n valid := io.dinValid\n } \n"}
{"file": "CGRAs/src/main/scala/Fr.scala", "target_type": "class_definition", "cursor_line": 36, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class Fr \n"}
{"file": "CGRAs/src/main/scala/Fs.scala", "target_type": "object_definition", "cursor_line": 70, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object FsMain extends App {\n println(\"Generating the hardware\")\n (new chisel3.stage.ChiselStage).emitVerilog(new Fs(5), Array(\"--target-dir\", \"generated\"))\n} \n"}
{"file": "CGRAs/src/main/scala/Fu.scala", "target_type": "function_definition", "cursor_line": 44, "target_nlines": 1, "node_depth": 2, "node_path": ["compilation_unit", "block", "function_definition"], "target": " def STATE_0 = 0.U(2.W) // 00\n"}
{"file": "CGRAs/src/main/scala/Join.scala", "target_type": "object_definition", "cursor_line": 71, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object JoinMain extends App {\n println(\"Generating the hardware\")\n (new chisel3.stage.ChiselStage).emitVerilog(new Join(32), Array(\"--target-dir\", \"generated\"))\n}\n"}
{"file": "CGRAs/src/main/scala/OverlayRocc.scala", "target_type": "block", "cursor_line": 97, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when (io.cellConfig(191) === 1.U){\n catchConfig(unsignedCellConfig) := 1.B \n }\n"}
{"file": "CGRAs/src/main/scala/ProcessingElement.scala", "target_type": "class_definition", "cursor_line": 36, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class ProcessingElement \n"}
{"file": "CGRAs/src/test/scala/AluTest.scala", "target_type": "block", "cursor_line": 144, "target_nlines": 5, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block", "lambda_expression", "indented_block", "for_expression", "block"], "target": " for (i <- 1 until numOfTests) {\n dut.io.din1.poke((-(i*2)).S)\n dut.io.din2.poke(i.S)\n dut.clock.step(1)\n }\n"}
{"file": "CGRAs/src/test/scala/CellProcessingTest.scala", "target_type": "class_definition", "cursor_line": 70, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " dut.io.eastDinValid.poke(eastDinValid)\n\n dut.io.southDin.poke(southDin)\n dut.io.southDinValid.poke(southDinValid)\n"}
{"file": "CGRAs/src/test/scala/ConfMuxTest.scala", "target_type": "block", "cursor_line": 51, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " dut.clock.step(1)\n selector = 2\n muxInput = 53\n"}
{"file": "CGRAs/src/test/scala/DEbTest.scala", "target_type": "block", "cursor_line": 123, "target_nlines": 5, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block"], "target": " println(\"An: \" + dut.io.doutReady.peek().toString)\n dut.clock.step(1)\n dut.clock.step(1)\n dut.io.dinValid.poke(false.B)\n dut.clock.step(1)\n"}
{"file": "CGRAs/src/test/scala/DFifoTest.scala", "target_type": "block", "cursor_line": 49, "target_nlines": 2, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block", "lambda_expression", "indented_block", "for_expression", "block"], "target": " dut.io.din.poke(i.S) \n dut.io.dinValid.poke(true.B)\n"}
{"file": "CGRAs/src/test/scala/DRegTest.scala", "target_type": "block", "cursor_line": 41, "target_nlines": 2, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " var doutReady = false.B\n var dinValid = false.B \n"}
{"file": "CGRAs/src/test/scala/FrTest.scala", "target_type": "block", "cursor_line": 40, "target_nlines": 5, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block"], "target": " \n var validIn = \"b11011\".U \n var readyOut = \"b11011\".U \n var validMuxSel = \"b10\".U \n var forkMask = \"b11011\".U \n"}
{"file": "CGRAs/src/test/scala/FsTest.scala", "target_type": "block", "cursor_line": 40, "target_nlines": 3, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block"], "target": " \n dut.io.readyOut.poke(\"b00000\".U)\n dut.io.forkMask.poke(\"b00000\".U)\n"}
{"file": "CGRAs/src/test/scala/FuTest.scala", "target_type": "identifier", "cursor_line": 268, "target_nlines": 1, "node_depth": 13, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block", "lambda_expression", "indented_block", "call_expression", "field_expression", "field_expression", "field_expression", "identifier"], "target": " dut.io.dinValid.poke(dinValid)\n"}
{"file": "CGRAs/src/test/scala/JoinTest.scala", "target_type": "block", "cursor_line": 79, "target_nlines": 5, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block"], "target": " println(\"*************************************\")\n println(\"Test 1: Vin1: true, Vin2: false, Aout: false\")\n println(\"*************************************\")\n din1Valid = true.B\n din2Valid = false.B \n"}
{"file": "CGRAs/src/test/scala/OverlayRoccTestACC.scala", "target_type": "class_definition", "cursor_line": 49, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " dut.io.dataOutReady.poke(dataOutReady)\n dut.clock.step(1)\n\n var cellConfig: UInt = 0.U \n \n"}
{"file": "CGRAs/src/test/scala/OverlayRoccTestCAP.scala", "target_type": "block", "cursor_line": 116, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " dut.io.dataInValid.poke(\"b100001\".U)\n"}
{"file": "CGRAs/src/test/scala/OverlayRoccTestMAC.scala", "target_type": "class_definition", "cursor_line": 90, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " for (i <- 1 to 101) {\n // ------------------------------------------------------------------------------------------------\n"}
{"file": "CGRAs/src/test/scala/OverlayRoccTestMAC2.scala", "target_type": "block", "cursor_line": 91, "target_nlines": 5, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block", "lambda_expression", "indented_block", "for_expression", "block"], "target": " for (i <- 1 to 16) {\n // ------------------------------------------------------------------------------------------------\n // | | C5 | C4 | C3 | C2 | C1 | C0 |\n // ------------------------------------------------------------------------------------------------\n // ------------------------------------------------------------------------------------------------\n"}
{"file": "CGRAs/src/test/scala/OverlayRoccTestSUM.scala", "target_type": "block", "cursor_line": 124, "target_nlines": 3, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block", "lambda_expression", "indented_block", "for_expression", "block"], "target": " for( i <- 0 to 10){\n dut.clock.step(1)\n } \n"}
{"file": "CGRAs/src/test/scala/ProcessingElementTest.scala", "target_type": "function_definition", "cursor_line": 40, "target_nlines": 1, "node_depth": 2, "node_path": ["compilation_unit", "block", "function_definition"], "target": " def FIFO_DEPTH = 32 \n"}
{"file": "tywaves-chisel/example/detect2ones.test.scala", "target_type": "block", "cursor_line": 37, "target_nlines": 1, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "call_expression", "field_expression", "call_expression", "block"], "target": " when(isOne) { state := State.sTwo1s }.otherwise { state := State.sNone } \n"}
{"file": "tywaves-chisel/example/gcd.test.scala", "target_type": "block", "cursor_line": 43, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when(io.loadValues) { x := io.a; y := io.b }\n"}
{"file": "tywaves-chisel/example/myfsm.test.scala", "target_type": "block", "cursor_line": 90, "target_nlines": 3, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "call_expression", "block"], "target": " fsm.clock.step(10)\n fsm.io.inputState.poke(MyFSMStates.StateA)\n fsm.clock.step(10)\n"}
{"file": "tywaves-chisel/example/tydi-example-meaningfulnames.test.scala", "target_type": "class_definition", "cursor_line": 82, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class Generated_0_7_d3p7qsW3_29 extends BitsEl(64.W)\n"}
{"file": "tywaves-chisel/example/tydi-example.test.scala", "target_type": "function_definition", "cursor_line": 25, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition"], "target": " def generated_0_7_Tc5SbYQz_27 = UInt(64.W)\n"}
{"file": "tywaves-chisel/src/main/scala/tywaves/circuitmapper/TypedConverter.scala", "target_type": "function_definition", "cursor_line": 83, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition"], "target": " def getTopModuleName: Option[String] = topModuleName.name\n"}
{"file": "tywaves-chisel/src/main/scala/tywaves/simulator/ParametricSimulator.scala", "target_type": "function_definition", "cursor_line": 63, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " def getFirtoolArgs: Seq[String] = _firtoolArgs\n"}
{"file": "tywaves-chisel/src/main/scala/tywaves/simulator/ParametricSimulatorInterface.scala", "target_type": "function_definition", "cursor_line": 14, "target_nlines": 5, "node_depth": 3, "node_path": ["compilation_unit", "trait_definition", "template_body", "function_definition"], "target": " settings: Seq[SimulatorSettings] = Seq(),\n simName: String = \"defaultSimulation\",\n )(body: T => Unit): Unit = {\n if (_resetSimulationBeforeRun)\n reset()\n"}
{"file": "tywaves-chisel/src/main/scala/tywaves/simulator/SimulatorSettings.scala", "target_type": "class_definition", "cursor_line": 38, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "private[simulator] case class FirtoolArgs(args: Seq[String]) extends SimulatorSettings\n"}
{"file": "tywaves-chisel/src/main/scala/tywaves/simulator/TywavesInterface.scala", "target_type": "block", "cursor_line": 21, "target_nlines": 3, "node_depth": 5, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition", "block", "block"], "target": " if (exitCode != 0)\n throw new Exception(s\"$program not found on the PATH! Please install it running: make all\\n\")\n }\n"}
{"file": "tywaves-chisel/src/main/scala/tywaves/simulator/TywavesSimulator.scala", "target_type": "class_definition", "cursor_line": 10, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "class_definition"], "target": " private[simulator] case class Tywaves(runWaves: Boolean, waitFor: Boolean) extends SimulatorSettings\n"}
{"file": "tywaves-chisel/src/main/scala/tywaves/utils/UniqueHashMap.scala", "target_type": "block", "cursor_line": 40, "target_nlines": 5, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block"], "target": " this.foreach { case (key, value) =>\n bw.write(s\"$key: $value\\n\")\n }\n bw.close()\n }\n"}
{"file": "tywaves-chisel/src/test/scala/GetNameTest.scala", "target_type": "class_definition", "cursor_line": 5, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class MyBundle extends Bundle\n"}
{"file": "tywaves-chisel/src/test/scala/bar/Bar.scala", "target_type": "class_definition", "cursor_line": 29, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "\n val cable =\n Wire(Bool()) // do not use reserved verilog words as val names (val wire) -> tywaves-demo does not work for them yet\n cable := io.a & io.b\n\n"}
{"file": "tywaves-chisel/src/test/scala/bar/BarTest.scala", "target_type": "block", "cursor_line": 48, "target_nlines": 2, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block"], "target": " c.io.out.expect(true.B)\n\n"}
{"file": "tywaves-chisel/src/test/scala/foo/Foo.scala", "target_type": "class_definition", "cursor_line": 6, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class Simple extends Bundle\n"}
{"file": "tywaves-chisel/src/test/scala/foo/FooTest.scala", "target_type": "block", "cursor_line": 34, "target_nlines": 4, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " simulate(new Foo, Seq(VcdTraceWithUnderscore), simName = \"trace_with_underscore\") {\n println(\"Running test: \" + it)\n RunFoo(_)\n }\n"}
{"file": "tywaves-chisel/src/test/scala/gcd/GCD.scala", "target_type": "block", "cursor_line": 20, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when(io.loadValues) { x := io.a; y := io.b }\n"}
{"file": "tywaves-chisel/src/test/scala/gcd/GCDTest.scala", "target_type": "block", "cursor_line": 15, "target_nlines": 2, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "call_expression", "block"], "target": " gcd.io.a.poke(24.U)\n gcd.io.b.poke(36.U)\n"}
{"file": "tywaves-chisel/src/test/scala/hierarchicalmodules/Blink.scala", "target_type": "class_definition", "cursor_line": 16, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " when(io.enable) {\n when(cnt.inc() && cnt.value === (period - 1).U) {\n ledReg := ~ledReg\n }\n }\n"}
{"file": "tywaves-chisel/src/test/scala/hierarchicalmodules/BlinkTest.scala", "target_type": "block", "cursor_line": 56, "target_nlines": 4, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " simName = \"blink_with_tywaves_sim_should_work\",\n ) { dut =>\n blinkTb(dut)\n }\n"}
{"file": "tywaves-chisel/src/test/scala/hierarchicalmodules/MultiBlink.scala", "target_type": "object_definition", "cursor_line": 52, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": " ChiselStage.emitSystemVerilog(\n new AMultiBlink,\n firtoolOpts = Array(\n \"-O=debug\",\n \"-g\",\n"}
{"file": "tywaves-chisel/src/test/scala/hierarchicalmodules/MultiBlinkTest.scala", "target_type": "class_definition", "cursor_line": 21, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " dut.clock.step() // 5\n dut.clock.step() // 6\n dut.clock.step()\n"}
{"file": "tywaves-chisel/src/test/scala/hierarchicalmodules/UseCounter.scala", "target_type": "function_definition", "cursor_line": 14, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "class_definition", "template_body", "class_definition", "template_body", "function_definition"], "target": " def apply: UInt = value\n"}
{"file": "tywaves-chisel/src/test/scala/memories/BlockMem.scala", "target_type": "class_definition", "cursor_line": 12, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val wrAddr = Input(UInt(log2Ceil(depth).W))\n}\n"}
{"file": "tywaves-chisel/src/test/scala/memories/BlockMemTest.scala", "target_type": "object_definition", "cursor_line": 76, "target_nlines": 1, "node_depth": 7, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "object_definition"], "target": " object SelType extends ChiselEnum { val A, B, C = Value }\n"}
{"file": "tywaves-chisel/src/test/scala/tywaves/simulator/ImportSimulatorReverseOrder.scala", "target_type": "class_definition", "cursor_line": 8, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " describe(\"Issue 27\") {\n it(\"Should import chisel before tywaves\") {\n import chisel3._\n import tywaves.simulator.TywavesSimulator._\n"}
{"file": "tywaves-chisel/src/test/scala/tywaves/simulator/ParametricSimulatorSpec.scala", "target_type": "block", "cursor_line": 73, "target_nlines": 4, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block"], "target": " it(\"save the workdir with a name\") {\n simulate(new GCD(), Seq(VcdTrace, SaveWorkdirFile(\"myWorkdir\")))(gcd => gcdTb(gcd))\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/ParametricSimulator/defaultSimulation/myWorkdir\")))\n }\n"}
{"file": "tywaves-chisel/src/test/scala/tywaves/simulator/TywavesSimulatorSpec.scala", "target_type": "block", "cursor_line": 107, "target_nlines": 4, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block"], "target": " simulate(new GCD(), Seq(VcdTrace, NameTrace(\"gcdTb1\")), simName = \"use_a_name_for_the_simulation\")(gcd =>\n gcdTb(gcd)\n )\n assert(Files.exists(Paths.get(\"test_run_dir/GCD/TywavesSimulator/use_a_name_for_the_simulation/gcdTb1.vcd\")))\n"}
{"file": "an-ethernet-controller/src/main/scala/ethcontroller/design/EthRxController.scala", "target_type": "block", "cursor_line": 128, "target_nlines": 2, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "for_expression", "block"], "target": " ramMasterRegs(ramId).Cmd := RegNext(Mux(ramId.U === wrRamIdReg && ocpSelRam, OcpCmd.WR, Mux(ocpRamRdEn, OcpCmd.RD, OcpCmd.IDLE)))\n ramMasterRegs(ramId).Data := RegNext(ethByteReg)\n"}
{"file": "an-ethernet-controller/src/main/scala/ethcontroller/design/EthTxController.scala", "target_type": "block", "cursor_line": 201, "target_nlines": 3, "node_depth": 25, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "field_expression", "call_expression", "call_expression", "field_expression", "call_expression", "block", "call_expression", "call_expression", "field_expression", "call_expression", "call_expression", "field_expression", "call_expression", "call_expression", "field_expression", "call_expression", "call_expression", "field_expression", "call_expression", "block"], "target": " }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"fifoEmpty\")(\"Addr\")) {\n ocpDataReg := ethTxCtrlRegMap(\"fifoEmpty\")(\"Reg\")\n }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap(\"fifoFull\")(\"Addr\")) {\n"}
{"file": "an-ethernet-controller/src/main/scala/ethcontroller/design/MIIRx.scala", "target_type": "class_definition", "cursor_line": 79, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " eofReg := true.B\n"}
{"file": "an-ethernet-controller/src/main/scala/ethcontroller/design/MIITx.scala", "target_type": "block", "cursor_line": 48, "target_nlines": 3, "node_depth": 7, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "call_expression", "field_expression", "call_expression", "block"], "target": " when(~transmittingReg && serializeByteToNibble.io.dv) {\n transmittingReg := true.B\n }.elsewhen(~serializeByteToNibble.io.dv && serializeByteToNibble.io.done) {\n"}
{"file": "an-ethernet-controller/src/main/scala/ethcontroller/interfaces/MIIChannel.scala", "target_type": "class_definition", "cursor_line": 9, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val clk = Bool(INPUT)\n /** Received data valid */\n"}
{"file": "an-ethernet-controller/src/main/scala/ethcontroller/interfaces/PHYChannel.scala", "target_type": "class_definition", "cursor_line": 12, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " /** Management input data */\n val mdi = Bool(INPUT)\n"}
{"file": "an-ethernet-controller/src/main/scala/ethcontroller/protocols/EthernetConstants.scala", "target_type": "object_definition", "cursor_line": 13, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": " val constVLANt1 = Bits(\"h8100\", width = 16)\n"}
{"file": "an-ethernet-controller/src/main/scala/ethcontroller/protocols/EthernetFrame.scala", "target_type": "function_definition", "cursor_line": 38, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " def ethTypeNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(ethType, msbFirst = false)\n"}
{"file": "an-ethernet-controller/src/main/scala/ethcontroller/protocols/EthernetUtils.scala", "target_type": "function_definition", "cursor_line": 49, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition"], "target": " def toBytes(xs: Int*) = xs.map(_.toByte).toArray\n"}
{"file": "an-ethernet-controller/src/main/scala/ethcontroller/utils/Deserializer.scala", "target_type": "block", "cursor_line": 32, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " } else {\n shiftReg(outputWidth - inputWidth - 1, 0) := shiftReg(outputWidth - 1, inputWidth)\n shiftReg(outputWidth - 1, outputWidth - inputWidth) := io.shiftIn\n"}
{"file": "an-ethernet-controller/src/main/scala/ethcontroller/utils/ExtClockSampler.scala", "target_type": "class_definition", "cursor_line": 24, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "\n if (sampleRisingEdge) {\n extClkEdge := extClkSyncedReg & ~extClkSyncedOldReg //check for a rising edge\n } else {\n extClkEdge := ~extClkSyncedReg & extClkSyncedOldReg //or check for a falling edge\n"}
{"file": "an-ethernet-controller/src/main/scala/ethcontroller/utils/Serializer.scala", "target_type": "block", "cursor_line": 42, "target_nlines": 5, "node_depth": 7, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "call_expression", "field_expression", "call_expression", "block"], "target": " }.otherwise {\n countReg := countReg - 1.U\n doneReg := false.B\n }\n }.elsewhen(doneReg) {\n"}
{"file": "an-ethernet-controller/src/main/scala/ocp/Arbiter.scala", "target_type": "block", "cursor_line": 47, "target_nlines": 2, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "field_expression", "call_expression", "block"], "target": " stateReg := sWrite\n burstCntReg := UInt(0)\n"}
{"file": "an-ethernet-controller/src/main/scala/ocp/NodeTdmArbiter.scala", "target_type": "function_definition", "cursor_line": 60, "target_nlines": 3, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " def slotTable(i: Int): UInt = {\n (cntReg === UInt(i * slotLen)).toUInt\n }\n"}
{"file": "an-ethernet-controller/src/main/scala/ocp/Ocp.scala", "target_type": "object_definition", "cursor_line": 14, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object OcpCmd {\n"}
{"file": "an-ethernet-controller/src/main/scala/ocp/OcpBurst.scala", "target_type": "block", "cursor_line": 255, "target_nlines": 5, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " for (i <- 0 until master.burstLength - 1) {\n MBuffer(i) := MBuffer(i + 1)\n }\n MBuffer(master.burstLength - 1) := master.M\n }\n"}
{"file": "an-ethernet-controller/src/main/scala/ocp/OcpCache.scala", "target_type": "class_definition", "cursor_line": 38, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class OcpCacheSlavePort(addrWidth: Int, dataWidth: Int) extends Bundle() {\n // Clk is implicit in Chisel\n val M = new OcpCacheMasterSignals(addrWidth, dataWidth).asInput\n val S = new OcpSlaveSignals(dataWidth).asOutput\n}\n"}
{"file": "an-ethernet-controller/src/main/scala/ocp/OcpCore.scala", "target_type": "class_definition", "cursor_line": 28, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "\n // This does not really clone, but Data.clone doesn't either\n override def clone() = {\n val res = new OcpCoreMasterPort(addrWidth, dataWidth)\n res.asInstanceOf[this.type]\n"}
{"file": "an-ethernet-controller/src/main/scala/ocp/OcpIO.scala", "target_type": "block", "cursor_line": 54, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when(masterReg.Cmd === OcpCmd.IDLE || slave.S.CmdAccept === Bits(1)) {\n masterReg := master.M\n }\n"}
{"file": "an-ethernet-controller/src/main/scala/ocp/OcpNI.scala", "target_type": "class_definition", "cursor_line": 17, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "\n // This does not really clone, but Data.clone doesn't either\n override def clone() = {\n val res = new OcpNISlaveSignals(dataWidth)\n"}
{"file": "an-ethernet-controller/src/main/scala/ocp/OcpTest.scala", "target_type": "block", "cursor_line": 44, "target_nlines": 4, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when(cnt =/= UInt(0)) {\n cnt := cnt - UInt(1)\n io.S.Resp := OcpResp.DVA\n }\n"}
{"file": "an-ethernet-controller/src/main/scala/ocp/TdmArbiter.scala", "target_type": "block", "cursor_line": 101, "target_nlines": 3, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "for_expression", "block", "call_expression", "block", "call_expression", "block"], "target": " when(io.slave.S.Resp === OcpResp.DVA) {\n stateReg(i) := sIdle\n }\n"}
{"file": "an-ethernet-controller/src/main/scala/ocp/TdmArbiterWrapper.scala", "target_type": "block", "cursor_line": 22, "target_nlines": 3, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "arguments", "instance_expression", "template_body", "val_definition", "call_expression", "block"], "target": " val master = Vec.fill(cnt) {\n new OcpBurstSlavePort(addrWidth, dataWidth, burstLen)\n }\n"}
{"file": "an-ethernet-controller/src/test/scala/ethcontroller/design/EthRxControllerTester.scala", "target_type": "block", "cursor_line": 59, "target_nlines": 4, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "for_expression", "block"], "target": " for (nibble <- frame.dstMacNibbles ++ frame.srcMacNibbles ++ frame.ethTypeNibbles) {\n txPHY2MIIData(nibble, 6)\n peekEthRxStatus()\n }\n"}
{"file": "an-ethernet-controller/src/test/scala/ethcontroller/design/EthTxControllerTester.scala", "target_type": "block", "cursor_line": 65, "target_nlines": 4, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "for_expression", "block", "if_expression", "block"], "target": " if (byteCnt == 8) {\n byteCnt = 1\n ocpAddr += 0x1\n } else {\n"}
{"file": "an-ethernet-controller/src/test/scala/ethcontroller/design/MIIRxTester.scala", "target_type": "class_definition", "cursor_line": 39, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " poke(dut.io.miiChannel.dv, 0)\n step(3)\n"}
{"file": "an-ethernet-controller/src/test/scala/ethcontroller/design/MIITxTester.scala", "target_type": "block", "cursor_line": 62, "target_nlines": 4, "node_depth": 4, "node_path": ["compilation_unit", "object_definition", "template_body", "try_expression", "block"], "target": " () => Module(new MIITx())) {\n dut => new MIITxTester(dut, EthernetTesting.mockupPTPEthFrameOverIpUDP)\n }\n } finally {\n"}
{"file": "an-ethernet-controller/src/test/scala/ethcontroller/protocols/EthernetTesting.scala", "target_type": "object_definition", "cursor_line": 82, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": " override val ptpSuffix: Array[Byte] = Array.emptyByteArray\n override val fcs: Array[Byte] = Array.emptyByteArray\n override val igp: Array[Byte] = Array.emptyByteArray\n"}
{"file": "an-ethernet-controller/src/test/scala/ethcontroller/utils/DeserializerTester.scala", "target_type": "block", "cursor_line": 16, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "for_expression", "block"], "target": " peek(dut.io.shiftOut)\n peek(dut.io.done)\n step(1)\n"}
{"file": "an-ethernet-controller/src/test/scala/ethcontroller/utils/SerializerTester.scala", "target_type": "block", "cursor_line": 41, "target_nlines": 3, "node_depth": 6, "node_path": ["compilation_unit", "object_definition", "template_body", "try_expression", "block", "call_expression", "block"], "target": " () => Module(new Serializer(false, 8, 4))) {\n dut => new SerializerTester(dut, EthernetTesting.mockupPTPEthFrameOverIpUDP)\n }\n"}
{"file": "chiselv/chiselv/src/ALU.scala", "target_type": "if_expression", "cursor_line": 18, "target_nlines": 1, "node_depth": 7, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "infix_expression", "parenthesized_expression", "if_expression", "if_expression"], "target": " val shamt = (if (bitWidth == 32) 5 else if (bitWidth == 64) 6 else 0) - 1\n"}
{"file": "chiselv/chiselv/src/Blink.scala", "target_type": "block", "cursor_line": 26, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when(counterWrap) {\n led := ~led\n }\n"}
{"file": "chiselv/chiselv/src/CPUSingleCycle.scala", "target_type": "block", "cursor_line": 190, "target_nlines": 4, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block"], "target": " when(decoder.io.inst === LW) {\n dataSize := 3.U\n dataOut := memoryIOManager.io.MemoryIOPort.readData\n }\n"}
{"file": "chiselv/chiselv/src/Constants.scala", "target_type": "object_definition", "cursor_line": 23, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object InstructionType extends ChiselEnum {\n val IN_ERR, INST_R, INST_I, INST_S, INST_B, INST_U, INST_J, INST_Z = Value\n}\n"}
{"file": "chiselv/chiselv/src/DataMemory.scala", "target_type": "if_expression", "cursor_line": 40, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "class_definition", "template_body", "if_expression", "block", "if_expression"], "target": " if (debugMsg) println(s\" Load memory file: \" + memoryFile)\n"}
{"file": "chiselv/chiselv/src/Decoder.scala", "target_type": "function_definition", "cursor_line": 147, "target_nlines": 4, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " case INST_R => 0.S\n case INST_I => Cat(Fill(20, inst(31)), inst(31, 20)).asSInt\n case INST_S => Cat(Fill(20, inst(31)), inst(31, 25), inst(11, 7)).asSInt\n case INST_B => Cat(Fill(19, inst(31)), inst(31), inst(7), inst(30, 25), inst(11, 8), 0.U(1.W)).asSInt\n"}
{"file": "chiselv/chiselv/src/GPIO.scala", "target_type": "block", "cursor_line": 68, "target_nlines": 1, "node_depth": 9, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "arguments", "field_expression", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " | output [${numGPIO - 1}:0] dataOut,\n"}
{"file": "chiselv/chiselv/src/InstructionMemory.scala", "target_type": "if_expression", "cursor_line": 24, "target_nlines": 3, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "if_expression"], "target": " if (memoryFile.trim().nonEmpty) {\n loadMemoryFromFileInline(mem, memoryFile)\n }\n"}
{"file": "chiselv/chiselv/src/MemoryIOManager.scala", "target_type": "block", "cursor_line": 213, "target_nlines": 5, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "call_expression", "block"], "target": " }\n is(2.U) { // Write halfword\n switch(io.DataMemPort.writeAddress(1).asUInt) {\n is(1.U) { // Write half word 1\n dataToWrite := Cat(io.MemoryIOPort.writeData(15, 0).asUInt, Fill(16, 0.U))\n"}
{"file": "chiselv/chiselv/src/PLLBlackBox.scala", "target_type": "class_definition", "cursor_line": 12, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val lock = Output(Clock())\n })\n\n val filename = \"pll_\" + board + \".v\"\n val verilog = Source.fromResource(filename).getLines().mkString(\"\\n\")\n"}
{"file": "chiselv/chiselv/src/ProgramCounter.scala", "target_type": "class_definition", "cursor_line": 7, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val PC = Output(UInt(bitWidth.W))\n val PC4 = Output(UInt(bitWidth.W))\n"}
{"file": "chiselv/chiselv/src/RVFI_Wrapper.scala", "target_type": "class_definition", "cursor_line": 72, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " rvfi.insn := decoder.io.op\n\n"}
{"file": "chiselv/chiselv/src/RegisterBank.scala", "target_type": "class_definition", "cursor_line": 11, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val regwr_addr = Input(UInt(log2Ceil(bitWidth).W))\n val regwr_data = Input(UInt(bitWidth.W))\n"}
{"file": "chiselv/chiselv/src/SOC.scala", "target_type": "block", "cursor_line": 58, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "if_expression", "block"], "target": " if (numGPIO > 0) {\n core.io.GPIO0External <> io.GPIO0External\n }\n"}
{"file": "chiselv/chiselv/src/Syscon.scala", "target_type": "class_definition", "cursor_line": 6, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class SysconPort(val bitWidth: Int) extends Bundle {\n val Address = Input(UInt(12.W))\n val DataOut = Output(UInt(bitWidth.W))\n}\n"}
{"file": "chiselv/chiselv/src/Timer.scala", "target_type": "block", "cursor_line": 23, "target_nlines": 3, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block"], "target": " when(counterWrap) {\n counter := counter + 1.U\n }\n"}
{"file": "chiselv/chiselv/src/Toplevel.scala", "target_type": "if_expression", "cursor_line": 24, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "if_expression"], "target": " val customReset = if (invReset) ~reset.asBool else reset\n"}
{"file": "chiselv/chiselv/src/Uart.scala", "target_type": "block", "cursor_line": 181, "target_nlines": 5, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "call_expression", "block", "call_expression", "block"], "target": " when(rx === 1.U) {\n /* We might overflow the queue if we can't keep up */\n rxQueue.io.enq.bits := rxByte.reverse.reduce(_ ## _)\n rxQueue.io.enq.valid := true.B\n rxState := sRxIdle\n"}
{"file": "chiselv/chiselv/test/src/ALUSpec.scala", "target_type": "if_expression", "cursor_line": 110, "target_nlines": 1, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "indented_block", "match_expression", "case_block", "case_clause", "if_expression"], "target": " case GTE => if (a.toInt >= b.toInt) 1 else 0\n"}
{"file": "chiselv/chiselv/test/src/CPUDemoAppsSpec.scala", "target_type": "block", "cursor_line": 76, "target_nlines": 4, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block"], "target": " defaultDut(filename) { c =>\n c.clock.setTimeout(3000)\n c.clock.step(2000)\n }\n"}
{"file": "chiselv/chiselv/test/src/CPUSingleCycleAppsSpec.scala", "target_type": "block", "cursor_line": 84, "target_nlines": 2, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " c.clock.step(1 + writeLatency) // sw\n // Check Memory read at address 0x80000000\n"}
{"file": "chiselv/chiselv/test/src/CPUSingleCycleIOSpec.scala", "target_type": "block", "cursor_line": 134, "target_nlines": 5, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " c.registers(3).peekInt() should be(0)\n c.clock.step(1) // bne\n c.clock.step(2 * ms) // wait 2ms\n c.timerCounter.peekInt() should be(2)\n c.registers(3).peekInt() should be(2)\n"}
{"file": "chiselv/chiselv/test/src/CPUSingleCycleInstructionSpec.scala", "target_type": "block", "cursor_line": 120, "target_nlines": 5, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " jal x1, +8\n nop\n jalr x2, x1, +2044\n \"\"\"\n defaultDut(prog) { c =>\n"}
{"file": "chiselv/chiselv/test/src/DecoderSpec.scala", "target_type": "block", "cursor_line": 251, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " test(new Decoder) { c =>\n c.io.op.poke(makeBin(\"lbu x1, 16(x2)\"))\n c.clock.step()\n"}
{"file": "chiselv/chiselv/test/src/GPIOSpec.scala", "target_type": "function_definition", "cursor_line": 22, "target_nlines": 3, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " )\n\n it should \"read GPIO output and direction as 0 when initialized\" in {\n"}
{"file": "chiselv/chiselv/test/src/MemorySpec.scala", "target_type": "block", "cursor_line": 42, "target_nlines": 5, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block", "lambda_expression", "indented_block", "call_expression", "block"], "target": " addresses.foreach { address =>\n values.foreach { value =>\n c.io.writeEnable.poke(true)\n c.io.writeAddress.poke(addressOffset + address)\n c.io.readAddress.poke(addressOffset + address)\n"}
{"file": "chiselv/chiselv/test/src/ProgramCounterSpec.scala", "target_type": "block", "cursor_line": 28, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " c.clock.step()\n"}
{"file": "chiselv/chiselv/test/src/RegisterBankSpec.scala", "target_type": "block", "cursor_line": 14, "target_nlines": 4, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block"], "target": " test(new RegisterBank) { c =>\n c.io.rs1_addr.poke(0.U)\n c.io.rs1.expect(0.U)\n }\n"}
{"file": "chiselv/chiselv/test/src/SysconSpec.scala", "target_type": "block", "cursor_line": 35, "target_nlines": 4, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " c.clock.step()\n c.io.DataOut.peekInt() should be(1)\n }\n }\n"}
{"file": "chiselv/chiselv/test/src/TimerSpec.scala", "target_type": "block", "cursor_line": 28, "target_nlines": 4, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " c.io.dataOut.peekInt() should be(0)\n c.obs_counter.peekInt() should be(0)\n c.clock.step(ms)\n c.io.dataOut.peekInt() should be(1)\n"}
{"file": "chiselv/chiselv/test/src/UartSpec.scala", "target_type": "function_definition", "cursor_line": 21, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " def clockSerial(clk: Clock) = clk.step(fpgaClock / baudRate)\n"}
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