Datasets:
File size: 101,517 Bytes
d6720f3 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 | {"file": "chiffre/le-chiffre/src/main/scala/rocketchip/Configs.scala", "target_type": "class_definition", "cursor_line": 32, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class LeChiffreConfig extends Config(new WithLeChiffre ++ new DefaultConfig)\n"}
{"file": "chiffre/src/main/scala/chiffre/InjectorInfo.scala", "target_type": "block", "cursor_line": 31, "target_nlines": 1, "node_depth": 18, "node_path": ["compilation_unit", "trait_definition", "template_body", "function_definition", "block", "field_expression", "interpolated_string_expression", "interpolated_string", "interpolation", "block", "call_expression", "field_expression", "call_expression", "arguments", "lambda_expression", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " |${fields.map(a => s\"${a.serialize(tab + \" \")}\").mkString(\"\\n\")}\"\"\"\n"}
{"file": "chiffre/src/main/scala/chiffre/ScanField.scala", "target_type": "class_definition", "cursor_line": 18, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "case class ScanFieldBindingException(msg: String) extends Exception(msg)\n"}
{"file": "chiffre/src/main/scala/chiffre/inject/CycleInjector.scala", "target_type": "class_definition", "cursor_line": 21, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "case class Cycle(width: Int) extends ScanField\n"}
{"file": "chiffre/src/main/scala/chiffre/inject/LfsrInjector.scala", "target_type": "class_definition", "cursor_line": 22, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "case class Difficulty(width: Int) extends ScanField with ProbabilityBind\n"}
{"file": "chiffre/src/main/scala/chiffre/inject/StuckAt.scala", "target_type": "class_definition", "cursor_line": 58, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class StuckAtInjectorWithId(bitWidth: Int, val scanId: String) extends StuckAtInjector(bitWidth) with ChiffreInjector\n"}
{"file": "chiffre/src/main/scala/chiffre/passes/FaultInstrumentation.scala", "target_type": "block", "cursor_line": 64, "target_nlines": 1, "node_depth": 9, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "indented_block", "field_expression", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " |${indent}renames:\n"}
{"file": "chiffre/src/main/scala/chiffre/passes/ScanChainTransform.scala", "target_type": "block", "cursor_line": 43, "target_nlines": 1, "node_depth": 9, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "indented_block", "field_expression", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " |${injectors.map{ case (k, v) => s\"${tab} ${v.name}, ${k.module.name}, ${slaveIn(k).module.name}.${slaveIn(k).name}, ${slaveOut(k).module.name}.${slaveOut(k).name}\"}.mkString(\"\\n\")}\n"}
{"file": "chiffre/src/test/scala/chiffreTests/InstrumentationSpec.scala", "target_type": "class_definition", "cursor_line": 46, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "\n behavior of \"Chiffree Injectee annotation\"\n\n it should \"emit an annotation\" in {\n val circuit = ChiselStage.elaborate(new DummyInjectee)\n"}
{"file": "chiffre/src/test/scala/chiffreTests/inject/StuckAtInjectorSpec.scala", "target_type": "block", "cursor_line": 64, "target_nlines": 1, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block"], "target": " Driver(() => new StuckAtInjector(8)) { dut => new StuckAtTester(dut) }\n"}
{"file": "diagrammer/src/main/scala/dotvisualizer/RenderSvg.scala", "target_type": "if_expression", "cursor_line": 32, "target_nlines": 2, "node_depth": 7, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "if_expression", "block", "if_expression"], "target": " |<!DOCTYPE svg PUBLIC \"-//W3C//DTD SVG 1.1//EN\"\n | \"http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd\">\n"}
{"file": "diagrammer/src/main/scala/dotvisualizer/ToLoFirrtl.scala", "target_type": "function_definition", "cursor_line": 65, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " private def onMod(mod: DefModule): DefModule = mod.map(onStmt)\n"}
{"file": "diagrammer/src/main/scala/dotvisualizer/dotnodes/LiteralNode.scala", "target_type": "function_definition", "cursor_line": 6, "target_nlines": 4, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " def render: String = {\n s\"\"\"$absoluteName [shape=\"circle\" style=\"filled\" BGCOLOR=\"#C0C0C0\" label=\"$value\"]\n \"\"\".stripMargin\n }\n"}
{"file": "diagrammer/src/main/scala/dotvisualizer/dotnodes/PrimOpNode.scala", "target_type": "block", "cursor_line": 25, "target_nlines": 1, "node_depth": 7, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " override val absoluteName: String = s\"op_${name}_${PrimOpNode.hash}\"\n"}
{"file": "diagrammer/src/main/scala/dotvisualizer/stage/DiagrammerPhase.scala", "target_type": "object_definition", "cursor_line": 22, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": " val targets: Seq[PhaseManager.PhaseDependency] = Seq(\n Dependency[CheckPhase],\n Dependency[GetFirrtlCircuitPhase],\n"}
{"file": "diagrammer/src/main/scala/dotvisualizer/stage/phase/GenerateDotFilePhase.scala", "target_type": "function_definition", "cursor_line": 22, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " override def prerequisites = Seq(Dependency[OptionallyBuildTargetDirPhase])\n"}
{"file": "diagrammer/src/main/scala/dotvisualizer/stage/phase/OptionallyBuildTargetDirPhase.scala", "target_type": "block", "cursor_line": 40, "target_nlines": 1, "node_depth": 18, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "call_expression", "case_block", "case_clause", "if_expression", "block", "if_expression", "block", "throw_expression", "instance_expression", "arguments", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " throw new DiagrammerException(s\"Error: Target dir ${targetDir} exists and is not a directory\")\n"}
{"file": "diagrammer/src/main/scala/dotvisualizer/transforms/MakeDiagramGroup.scala", "target_type": "class_definition", "cursor_line": 14, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "\n override def optionalPrerequisites = Seq.empty\n\n"}
{"file": "diagrammer/src/main/scala/dotvisualizer/transforms/RemoveTempWires.scala", "target_type": "block", "cursor_line": 120, "target_nlines": 3, "node_depth": 18, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "function_definition", "block", "function_definition", "block", "match_expression", "case_block", "case_clause", "val_definition", "call_expression", "arguments", "call_expression", "arguments", "call_expression", "block"], "target": " val result = Some(Block(block.stmts.flatMap { substatement =>\n removeGenStatement(substatement)\n }))\n"}
{"file": "diagrammer/src/test/scala/dotvisualizer/PrintfSpec.scala", "target_type": "block", "cursor_line": 34, "target_nlines": 1, "node_depth": 11, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "function_definition", "block", "val_definition", "infix_expression", "parenthesized_expression", "if_expression", "block"], "target": " ) ++ (if (showPrintfs) { Seq(ShowPrintfsAnnotation) }\n"}
{"file": "dana/src/main/scala/dana/ActivationFunction.scala", "target_type": "block", "cursor_line": 222, "target_nlines": 1, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "call_expression", "block"], "target": " } .otherwise { out := one }\n"}
{"file": "dana/src/main/scala/dana/ProcessingElement.scala", "target_type": "class_definition", "cursor_line": 190, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " }\n is (PE_states('e_PE_ACTIVATION_FUNCTION)) {\n reqAf()\n"}
{"file": "dana/src/main/scala/dana/RegisterFile.scala", "target_type": "class_definition", "cursor_line": 158, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " // the number of expected writes.\n assert(!Vec((0 until transactionTableNumEntries * 2).map(\n i => (state(i).valid &&\n"}
{"file": "dana/src/main/scala/dana/util/Util.scala", "target_type": "block", "cursor_line": 13, "target_nlines": 5, "node_depth": 4, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition", "block"], "target": " def apply(epb: Int, pes: Int, cache: Int): Int = {\n var x = epb << (6 + 4);\n x = x | pes << 4;\n x = x | cache;\n x}\n"}
{"file": "dana/src/main/scala/standalone/XFilesTests.scala", "target_type": "class_definition", "cursor_line": 10, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "abstract class XFilesTests(implicit p: Parameters) extends XFilesTester {\n // New Transaction\n\n\n"}
{"file": "dana/src/main/scala/util/QueueAf.scala", "target_type": "function_definition", "cursor_line": 10, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " override def cloneType = new QueueIOAf(gen, entries).asInstanceOf[this.type]\n"}
{"file": "dana/src/main/scala/util/SRAM.scala", "target_type": "block", "cursor_line": 61, "target_nlines": 1, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "for_expression", "block", "call_expression", "block"], "target": " when (io.we(i)) { mem(io.addr(i)) := io.din(i) }\n"}
{"file": "dana/src/main/scala/util/SRAMBlockIncrement.scala", "target_type": "function_definition", "cursor_line": 68, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " def index(j: Int): (Int, Int) = (elementWidth*(j+1) - 1, elementWidth * j)\n"}
{"file": "dana/src/main/scala/util/SRAMElementCounter.scala", "target_type": "function_definition", "cursor_line": 20, "target_nlines": 2, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " override def cloneType = new SRAMElementCounterResp (\n sramDepth = sramDepth).asInstanceOf[this.type]\n"}
{"file": "dana/src/main/scala/util/SRAMElementIncrement.scala", "target_type": "function_definition", "cursor_line": 71, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " def index(j: Int): (Int, Int) = (elementWidth*(j+1) - 1, elementWidth * j)\n"}
{"file": "riscv-mini-five-stage/src/main/scala/riscv_mini_five_stage/IF_ID_Register.scala", "target_type": "class_definition", "cursor_line": 21, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val id_pc = Output(UInt(WLEN.W))\n val id_pc_4 = Output(UInt(WLEN.W))\n"}
{"file": "riscv-mini-five-stage/src/main/scala/riscv_mini_five_stage/InstCache.scala", "target_type": "object_definition", "cursor_line": 38, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object InstCache extends App {\n chisel3.Driver.execute(args, () => new InstCache)\n}\n"}
{"file": "riscv-mini-five-stage/src/main/scala/riscv_mini_five_stage/PC.scala", "target_type": "object_definition", "cursor_line": 30, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object PC extends App {\n chisel3.Driver.execute(args, () => new PC)\n}\n"}
{"file": "riscv-mini-five-stage/src/test/scala/riscv_mini_five_stage_test/ALU_Test.scala", "target_type": "block", "cursor_line": 30, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " iotesters.Driver.execute((Array(\"--is-verbose\")), () => new ALU) {\n c => new ALU_Test(c)\n }\n"}
{"file": "riscv-mini-five-stage/src/test/scala/riscv_mini_five_stage_test/Addr_Buffer_Test.scala", "target_type": "class_definition", "cursor_line": 20, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " poke(c.io.addr_input, addr)\n poke(c.io.record, record)\n peek(c.io.front)\n"}
{"file": "riscv-mini-five-stage/src/test/scala/riscv_mini_five_stage_test/Datapath_Test.scala", "target_type": "block", "cursor_line": 23, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " iotesters.Driver.execute(Array(\"--backend-name\", \"verilator\"), () => new Datapath) {\n c => new Datapath_Test(c)\n }\n"}
{"file": "riscv-mini-five-stage/src/test/scala/riscv_mini_five_stage_test/ID_EX_Register_Test.scala", "target_type": "block", "cursor_line": 15, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " iotesters.Driver.execute(Array(\"--backend-name\", \"-verilator\"), () => new ID_EX_Register) {\n c => new ID_EX_Register_Test(c)\n }\n"}
{"file": "riscv-mini-five-stage/src/test/scala/riscv_mini_five_stage_test/ImmGen_Test.scala", "target_type": "block", "cursor_line": 23, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " iotesters.Driver.execute(Array(\"--is-verbose\"), () => new ImmGen) {\n c => new ImmGen_Test(c)\n }\n"}
{"file": "riscv-mini-five-stage/src/test/scala/riscv_mini_five_stage_test/RegFile_Test.scala", "target_type": "class_definition", "cursor_line": 13, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " for(i <- 1 to 10) {\n"}
{"file": "riscv-mini-five-stage/src/test/scala/riscv_mini_five_stage_test/Tile_Test.scala", "target_type": "block", "cursor_line": 43, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " iotesters.Driver.execute(Array(\"--is-verbose\"), () => new Tile){\n c => new Tile_Test(c)\n }\n"}
{"file": "aes_chisel/src/main/scala/aes/InvMixColumns.scala", "target_type": "function_definition", "cursor_line": 153, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition"], "target": " def apply(Pipelined: Boolean = false): InvMixColumns = Module(new InvMixColumns(Pipelined))\n"}
{"file": "aes_chisel/src/main/scala/aes/MixColumns.scala", "target_type": "function_definition", "cursor_line": 152, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition"], "target": " def apply(Pipelined: Boolean = false): MixColumns = Module(new MixColumns(Pipelined))\n"}
{"file": "aes_chisel/src/main/scala/aes/Tables.scala", "target_type": "object_definition", "cursor_line": 25, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": " 0xe1.U, 0xf8.U, 0x98.U, 0x11.U, 0x69.U, 0xd9.U, 0x8e.U, 0x94.U, 0x9b.U, 0x1e.U, 0x87.U, 0xe9.U, 0xce.U, 0x55.U, 0x28.U, 0xdf.U,\n 0x8c.U, 0xa1.U, 0x89.U, 0x0d.U, 0xbf.U, 0xe6.U, 0x42.U, 0x68.U, 0x41.U, 0x99.U, 0x2d.U, 0x0f.U, 0xb0.U, 0x54.U, 0xbb.U, 0x16.U))\n\n"}
{"file": "aes_chisel/src/main/scala/gcd/GCD.scala", "target_type": "block", "cursor_line": 25, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " .otherwise { y := y - x }\n"}
{"file": "aes_chisel/src/main/scala/lfsr/LFSR.scala", "target_type": "function_definition", "cursor_line": 33, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition"], "target": " def apply(): LFSR = Module(new LFSR())\n"}
{"file": "aes_chisel/src/test/scala/aes/AddRoundKeyUnitTest.scala", "target_type": "block", "cursor_line": 67, "target_nlines": 2, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "if_expression", "block"], "target": " if (backendNames.contains(\"verilator\")) {\n iotesters.Driver.execute(\n"}
{"file": "aes_chisel/src/test/scala/aes/ShiftRowsUnitTest.scala", "target_type": "block", "cursor_line": 91, "target_nlines": 3, "node_depth": 9, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "if_expression", "block", "infix_expression", "call_expression", "block"], "target": " \"--backend-name\", \"firrtl\", \"--generate-vcd-output\", \"on\"), () => new ShiftRows) {\n c => new ShiftRowsUnitTester(c)\n } should be(true)\n"}
{"file": "aes_chisel/src/test/scala/aes/UnrolledAESUnitTest.scala", "target_type": "block", "cursor_line": 62, "target_nlines": 2, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "if_expression", "block"], "target": " Array(0x3d, 0xe2, 0x3a, 0x75, 0x52, 0x47, 0x75, 0xe7, 0x27, 0xbf, 0x9e, 0xb4, 0x54, 0x07, 0xcf, 0x39),\n Array(0x0b, 0xdc, 0x90, 0x5f, 0xc2, 0x7b, 0x09, 0x48, 0xad, 0x52, 0x45, 0xa4, 0xc1, 0x87, 0x1c, 0x2f),\n"}
{"file": "aes_chisel/src/test/scala/gcd/GCDMain.scala", "target_type": "object_definition", "cursor_line": 47, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object GCDRepl extends App {\n iotesters.Driver.executeFirrtlRepl(args, () => new GCD)\n}"}
{"file": "aes_chisel/src/test/scala/lfsr/LFSRUnitTest.scala", "target_type": "block", "cursor_line": 57, "target_nlines": 3, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "if_expression", "block"], "target": " iotesters.Driver.execute(\n Array(\"--target-dir\", \"test_run_dir/\" + dir + \"_firrtl_test\", \"--top-name\", dir,\n \"--backend-name\", \"firrtl\", \"--generate-vcd-output\", \"on\"), () => new LFSR) {\n"}
{"file": "Quasar/design/src/main/scala/dec/dec_decode_ctl.scala", "target_type": "block", "cursor_line": 543, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "block"], "target": " val csr_set_x = withClock(io.active_clk){RegNext(csr_set_d, init=0.B)}\n"}
{"file": "Quasar/design/src/main/scala/dec/dec_ib_ctl.scala", "target_type": "class_definition", "cursor_line": 9, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class dec_ib_ctl_IO extends Bundle with param{\n val ifu_ib = Flipped(new aln_ib)\n val ib_exu = Flipped(new ib_exu)\n val dbg_ib = new dbg_ib\n"}
{"file": "Quasar/design/src/main/scala/dec/dec_tlu_ctl.scala", "target_type": "if_expression", "cursor_line": 3068, "target_nlines": 1, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "call_expression", "field_expression", "call_expression", "arguments", "lambda_expression", "if_expression", "if_expression"], "target": "\tdef pattern(y : List[Int]) = (0 until y.size).map(i=> if(y(i)>=0 & y(i)!='z') io.dec_csr_rdaddr_d(y(i)) else if(y(i)<0) !io.dec_csr_rdaddr_d(y(i).abs) else !io.dec_csr_rdaddr_d(0)).reduce(_&_)\n"}
{"file": "Quasar/design/src/main/scala/dma_ctrl.scala", "target_type": "block", "cursor_line": 119, "target_nlines": 1, "node_depth": 11, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "call_expression", "field_expression", "field_expression", "call_expression", "arguments", "lambda_expression", "call_expression", "block"], "target": " fifo_error_bus := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_error_bus_en(i), 1.U, fifo_error_bus(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))\n"}
{"file": "Quasar/design/src/main/scala/dmi/dmi_wrapper.scala", "target_type": "class_definition", "cursor_line": 39, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val reg_wr_addr = Output(UInt(7.W))\n val reg_en = Output(UInt(1.W))\n val reg_wr_en = Output(UInt(1.W))\n"}
{"file": "Quasar/design/src/main/scala/exu/exu.scala", "target_type": "class_definition", "cursor_line": 21, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val\t\texu_div_wren\t\t\t = Output(UInt(1.W)) // Divide write enable to GPR\n //debug\n"}
{"file": "Quasar/design/src/main/scala/exu/exu_div_ctl.scala", "target_type": "if_expression", "cursor_line": 138, "target_nlines": 1, "node_depth": 11, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "val_definition", "call_expression", "field_expression", "call_expression", "arguments", "lambda_expression", "if_expression"], "target": " val pat_b = (0 until y.size).map(i=> if(y(i)>=0) m_ff(y(i)) else !m_ff(y(i).abs)).reduce(_&_)\n"}
{"file": "Quasar/design/src/main/scala/exu/exu_mul_ctl.scala", "target_type": "if_expression", "cursor_line": 224, "target_nlines": 1, "node_depth": 12, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "arguments", "call_expression", "field_expression", "field_expression", "call_expression", "arguments", "lambda_expression", "if_expression"], "target": " val shfl2_d = Mux(io.rs2_in(1), Range(0, 15,2).map(i=> if(i<4)Cat(shfl4_d(i+1+4,i+4),shfl4_d(i+1,i))else if(i<8)Cat(shfl4_d(i+9,i+8),shfl4_d(i+5,i+4))else if(i<12)Cat(shfl4_d(i+13,i+12),shfl4_d(i+9,i+8))else Cat(shfl4_d(i+17,i+16),shfl4_d(i+13,i+12))).reverse.reduce(Cat(_,_)), shfl4_d)\n"}
{"file": "Quasar/design/src/main/scala/lib/axi4_to_ahb.scala", "target_type": "block", "cursor_line": 26, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "call_expression", "block"], "target": " dec_tlu_force_halt_bus_q := withClock(io.free_clk) {RegNext(dec_tlu_force_halt_bus_ns, 0.U)}\n"}
{"file": "Quasar/design/src/main/scala/lsu/lsu_stbuf.scala", "target_type": "block", "cursor_line": 195, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " withClock(io.lsu_stbuf_c1_clk){ RdPtr := RegEnable(NxtRdPtr, 0.U, RdPtrEn)}\n"}
{"file": "NagiCore/src/main/scala/nagicore/Main.scala", "target_type": "block", "cursor_line": 48, "target_nlines": 3, "node_depth": 6, "node_path": ["compilation_unit", "object_definition", "template_body", "match_expression", "case_block", "case_clause", "block"], "target": " case _ => {\n exportVerilog(() => new nagicore.loongarch.nscscc2024.Core)\n }\n"}
{"file": "NagiCore/src/main/scala/nagicore/loongarch/nscscc2024/Config.scala", "target_type": "function_definition", "cursor_line": 14, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "trait_definition", "template_body", "function_definition"], "target": " def ICACHE_LINES = 128\n"}
{"file": "NagiCore/src/main/scala/nagicore/loongarch/nscscc2024/stages/IF.scala", "target_type": "if_expression", "cursor_line": 58, "target_nlines": 5, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "if_expression"], "target": " if(GlobalConfg.SIM){\n import nagicore.unit.DPIC_PERF_PIPE\n val perf_pipe_if = Module(new DPIC_PERF_PIPE())\n perf_pipe_if.io.clk := clock\n perf_pipe_if.io.rst := reset\n"}
{"file": "NagiCore/src/main/scala/nagicore/loongarch/nscscc2024/stages/MEM.scala", "target_type": "if_expression", "cursor_line": 87, "target_nlines": 2, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "if_expression"], "target": " val wordData = if(XLEN == 64) Mux(addr(2), rdata_raw(63, 32), rdata_raw(31, 0))\n else rdata_raw(31, 0)\n"}
{"file": "NagiCore/src/main/scala/nagicore/loongarch/nscscc2024Dual/Config.scala", "target_type": "function_definition", "cursor_line": 14, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "trait_definition", "template_body", "function_definition"], "target": " def ICACHE_LINES = 128\n"}
{"file": "NagiCore/src/main/scala/nagicore/loongarch/nscscc2024Dual/stages/IS.scala", "target_type": "class_definition", "cursor_line": 70, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val is2 = issue_buffer.io.rdatas(1)\n val data_hazard = (is1.rc === is2.ra || is1.rc === is2.rb) && is1.rc =/= 0.U\n // 只双发is2是ALU类，且无数据冒险的指令\n val issue_double =\n Flags.is(is2.instr_type, CtrlFlags.InstrType.alu) &&\n"}
{"file": "NagiCore/src/main/scala/nagicore/unit/DIVU.scala", "target_type": "match_expression", "cursor_line": 24, "target_nlines": 3, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "match_expression"], "target": " case DIVU_IMP.radix2 => {\n /* ref: https://github.com/MaZirui2001/LAdataBitsR-pipeline-scala */\n\n"}
{"file": "NagiCore/src/main/scala/nagicore/unit/GPR.scala", "target_type": "class_definition", "cursor_line": 9, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val wen = Input(Vec(wchannel, Bool()))\n val waddr = Input(Vec(wchannel, UInt(addrBits.W)))\n"}
{"file": "NagiCore/src/main/scala/nagicore/unit/cache/CachePiped.scala", "target_type": "block", "cursor_line": 165, "target_nlines": 5, "node_depth": 7, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "arguments", "call_expression", "block"], "target": " val rdatas = RegEnable(VecInit.tabulate(ways){ i =>\n VecInit.tabulate(num_word){ j =>\n data_bank_io(i)(j).dout\n }\n }, pipego_reg)\n"}
{"file": "NagiCore/src/main/scala/nagicore/unit/cache/CacheWT.scala", "target_type": "if_expression", "cursor_line": 199, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "if_expression"], "target": " val addr_word_reg = if(len_word!=0) addr_reg(len_word+len_byte-1, len_byte) else 0.U\n"}
{"file": "constellation/src/main/scala/channel/Nodes.scala", "target_type": "class_definition", "cursor_line": 8, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "case class EmptyParams()\n"}
{"file": "constellation/src/main/scala/channel/WidthWidget.scala", "target_type": "block", "cursor_line": 96, "target_nlines": 1, "node_depth": 7, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "instance_expression", "arguments", "assignment_expression", "block"], "target": " slaveFn = { s => s.copy(payloadBits=srcBits) }\n"}
{"file": "constellation/src/main/scala/noc/NoC.scala", "target_type": "block", "cursor_line": 180, "target_nlines": 1, "node_depth": 21, "node_path": ["compilation_unit", "class_definition", "template_body", "class_definition", "template_body", "val_definition", "call_expression", "field_expression", "call_expression", "block", "lambda_expression", "indented_block", "call_expression", "field_expression", "parenthesized_expression", "infix_expression", "call_expression", "arguments", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " (Seq(s\"${r.nodeId} $outs $egresses\") ++ ingresses).mkString(\"\\n\")\n"}
{"file": "constellation/src/main/scala/protocol/AXI4.scala", "target_type": "block", "cursor_line": 74, "target_nlines": 1, "node_depth": 9, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "arguments", "call_expression", "arguments", "call_expression", "block"], "target": " val arFIFOMap = WireInit(VecInit(Seq.fill(endId) { true.B }))\n"}
{"file": "constellation/src/main/scala/protocol/Protocol.scala", "target_type": "function_definition", "cursor_line": 43, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " def getNodesOut(ls: Seq[String]): Seq[Option[Int]] = getNodes(ls, outNodeMapping)\n"}
{"file": "constellation/src/main/scala/router/OutputUnit.scala", "target_type": "block", "cursor_line": 66, "target_nlines": 1, "node_depth": 9, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "arguments", "call_expression", "arguments", "call_expression", "block"], "target": " val states = Reg(MixedVec(cParam.virtualChannelParams.map { u => new OutputState(u.bufferSize) }))\n"}
{"file": "constellation/src/main/scala/router/vcalloc/SingleVCAllocator.scala", "target_type": "block", "cursor_line": 37, "target_nlines": 1, "node_depth": 9, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "arguments", "call_expression", "arguments", "call_expression", "block"], "target": " val in_alloc = Wire(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }))\n"}
{"file": "constellation/src/main/scala/routing/RoutingRelations.scala", "target_type": "function_definition", "cursor_line": 791, "target_nlines": 1, "node_depth": 7, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition", "lambda_expression", "instance_expression", "template_body", "function_definition"], "target": " override def getNPrios(src: ChannelRoutingInfo): Int = maxVCs\n"}
{"file": "constellation/src/main/scala/soc/Buses.scala", "target_type": "block", "cursor_line": 146, "target_nlines": 1, "node_depth": 15, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "field_expression", "call_expression", "block", "lambda_expression", "indented_block", "parenthesized_expression", "infix_expression", "infix_expression", "parenthesized_expression", "call_expression", "block"], "target": " } .getOrElse { TLAtomicAutomata(arithmetic = pa.arithmetic) })\n"}
{"file": "constellation/src/main/scala/util/Utils.scala", "target_type": "if_expression", "cursor_line": 14, "target_nlines": 3, "node_depth": 5, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition", "block", "if_expression"], "target": " val wrap = (value === (n-1).U)\n Mux(wrap, 0.U, value + 1.U)\n }\n"}
{"file": "essent/src/main/scala/Driver.scala", "target_type": "match_expression", "cursor_line": 11, "target_nlines": 4, "node_depth": 5, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition", "block", "match_expression"], "target": " (new ArgsParser).getConfig(args.toSeq) match {\n case Some(config) => generate(config)\n case None =>\n }\n"}
{"file": "essent/src/main/scala/Emitter.scala", "target_type": "block", "cursor_line": 157, "target_nlines": 1, "node_depth": 11, "node_path": ["compilation_unit", "function_definition", "match_expression", "case_block", "case_clause", "match_expression", "case_block", "case_clause", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " case Addw => s\"${emitExprWrap(p.args(0))}.addw(${emitExprWrap(p.args(1))})\"\n"}
{"file": "essent/src/main/scala/IR.scala", "target_type": "block", "cursor_line": 28, "target_nlines": 1, "node_depth": 7, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " def serialize: String = s\"if (${wrEn.serialize} && ${wrMask.serialize}) $memName[${wrAddr.serialize}] = ${wrData.serialize}\"\n"}
{"file": "essent/src/main/scala/MFFC.scala", "target_type": "function_definition", "cursor_line": 55, "target_nlines": 4, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition"], "target": " def apply(g: Graph, excludeSet: Set[NodeID] = Set()): ArrayBuffer[NodeID] = {\n val worker = new MFFC(g)\n excludeSet foreach { id => worker.mffc(id) = Excluded }\n val mffc = worker.findMFFCs()\n"}
{"file": "essent/src/main/scala/StatementGraph.scala", "target_type": "function_definition", "cursor_line": 85, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " def stmtsOrdered(): Seq[Statement] = collectValidStmts(TopologicalSort(this).toSeq)\n"}
{"file": "essent/src/main/scala/disabled/disabledInferAddw.scala", "target_type": "block", "cursor_line": 55, "target_nlines": 5, "node_depth": 11, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition", "block", "match_expression", "case_block", "case_clause", "match_expression", "case_block", "case_clause", "block"], "target": " val eName = primE.args.head match { case w: WRef => w.name }\n if ((addSigs.contains(eName)) && (primE.consts.head == 1) && (bitWidth(primE.tpe) == 64))\n Seq((tName, eName))\n else Seq()\n }\n"}
{"file": "essent/src/main/scala/disabled/disabledRandInitInvalids.scala", "target_type": "block", "cursor_line": 38, "target_nlines": 1, "node_depth": 9, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition", "block", "val_definition", "field_expression", "parenthesized_expression", "infix_expression", "block"], "target": " val portNames = (m.ports map { _.name }).toSet\n"}
{"file": "essent/src/main/scala/disabled/disabledZeroFromBits.scala", "target_type": "function_definition", "cursor_line": 36, "target_nlines": 5, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition"], "target": " def run(c: Circuit): Circuit = {\n val modulesx = c.modules.map {\n case m: ExtModule => m\n case m: Module => simpBitsModule(m)\n }\n"}
{"file": "essent/src/main/scala/passes/RegFromMem1.scala", "target_type": "block", "cursor_line": 69, "target_nlines": 1, "node_depth": 7, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition", "block", "val_definition", "infix_expression", "block"], "target": " val memsWithWrites = memsToReplace filter { _.writers.nonEmpty }\n"}
{"file": "essent/src/test/scala/ReplaceRsvdKeyTest.scala", "target_type": "class_definition", "cursor_line": 17, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val resultState = firrtlCompiler.execute(CircuitState(circuit, Seq()))\n val CorrectReader = Source.fromURL(getClass.getResource(\"/ReplacedRsvdKey_correct.fir\"))\n val correctString = CorrectReader.getLines().mkString(\"\\n\")\n assert(correctString == resultState.circuit.serialize)\n"}
{"file": "essent/src/test/scala/StatementGraphTest.scala", "target_type": "block", "cursor_line": 28, "target_nlines": 1, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block"], "target": " assertResult(2) { sg.numNodeRefs() }\n"}
{"file": "tree-core-cpu/rtl/TreeCoreL2/tc_l2/src/main/scala/common/InstConfig.scala", "target_type": "identifier", "cursor_line": 47, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "trait_definition", "template_body", "val_definition", "identifier"], "target": " val uInstType = 5.U(InstTypeLen.W)\n"}
{"file": "tree-core-cpu/rtl/TreeCoreL2/tc_l2/src/main/scala/core/ex/ALU.scala", "target_type": "class_definition", "cursor_line": 34, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " instSLTU -> Mux(io.src1.asUInt < io.src2.asUInt, 1.U(XLen.W), 0.U(XLen.W)),\n instSLTIU -> Mux(io.src1.asUInt < io.imm.asUInt, 1.U(XLen.W), 0.U(XLen.W)),\n instSLL -> (io.src1 << io.src2(5, 0))(63, 0),\n instSRL -> (io.src1 >> io.src2(5, 0)),\n"}
{"file": "tree-core-cpu/rtl/TreeCoreL2/tc_l2/src/main/scala/core/ex/EXU.scala", "target_type": "class_definition", "cursor_line": 26, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " protected val imm = exReg.imm\n protected val wen = exReg.wen\n protected val rs1 = exReg.inst(19, 15)\n"}
{"file": "tree-core-cpu/rtl/TreeCoreL2/tc_l2/src/main/scala/core/ex/Multiplier.scala", "target_type": "block", "cursor_line": 23, "target_nlines": 5, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "if_expression", "block"], "target": " } else {\n val done = RegNext(Mux(io.flush, false.B, en), false.B)\n val bits = RegEnable(data, en)\n generatePipe(done, bits, latency - 1)\n }\n"}
{"file": "tree-core-cpu/rtl/TreeCoreL2/tc_l2/src/main/scala/core/if/Cache.scala", "target_type": "class_definition", "cursor_line": 6, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class CacheReqIO extends Bundle with InstConfig {\n val addr = UInt(XLen.W)\n val data = UInt(XLen.W) // for write\n val mask = UInt((XLen / 8).W) // for write\n}\n"}
{"file": "tree-core-cpu/rtl/TreeCoreL2/tc_l2/src/main/scala/port/AXI4IO.scala", "target_type": "class_definition", "cursor_line": 29, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class AXI4WIO extends SOCAXI4WIO {}\n"}
{"file": "tree-core-cpu/rtl/TreeCoreL2/tc_l2/src/main/scala/port/BRANCHIO.scala", "target_type": "class_definition", "cursor_line": 9, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val taken = Output(Bool()) // is prev branch taken\n val idx = Output(UInt(GHRLen.W)) // prev idx of PHT(GHRLen)\n"}
{"file": "tree-core-cpu/rtl/TreeCoreL2/tc_l2/src/main/scala/port/COREIO.scala", "target_type": "class_definition", "cursor_line": 7, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val globalEn = Output(Bool())\n val fetch = Flipped(new IFIO)\n val ld = Flipped(new LDIO)\n val sd = Flipped(new SDIO)\n}\n"}
{"file": "tree-core-cpu/rtl/TreeCoreL2/tc_l2/src/main/scala/port/IFIO.scala", "target_type": "class_definition", "cursor_line": 6, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class IFIO extends Bundle with IOConfig {\n val en = Output(Bool())\n val addr = Output(UInt(XLen.W))\n val data = Input(UInt(InstLen.W))\n}\n"}
{"file": "tree-core-cpu/rtl/TreeCoreL2/tc_l2/src/main/scala/port/LSIO.scala", "target_type": "class_definition", "cursor_line": 15, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val addr = Output(UInt(XLen.W))\n val data = Output(UInt(XLen.W))\n"}
{"file": "tree-core-cpu/rtl/TreeCoreL2/tc_l2/src/main/scala/port/WBDATAIO.scala", "target_type": "class_definition", "cursor_line": 6, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class WBDATAIO extends Bundle with IOConfig {\n val wen = Output(Bool())\n val wdest = Output(UInt(RegfileLen.W))\n val data = Output(UInt(XLen.W))\n}\n"}
{"file": "rocket_chip_vpu/vpu/src/main/scala/VCompare.scala", "target_type": "function_definition", "cursor_line": 40, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " def less(src1: UInt, src2: UInt, sign: Bool): Bool = Mux(sign, src1.asSInt < src2.asSInt, src1 < src2)\r\n"}
{"file": "rocket_chip_vpu/vpu/src/main/scala/VDmemResp.scala", "target_type": "block", "cursor_line": 208, "target_nlines": 1, "node_depth": 7, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "block"], "target": " { state := s_write } \n"}
{"file": "rocket_chip_vpu/vpu/src/main/scala/VDmemSplit.scala", "target_type": "class_definition", "cursor_line": 37, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "//split vs2Data into SEW width vectors\n for(i <- 0 until E8Depth) io.vs2e.e8(i) := io.vs2Data(8*(i+1)-1, 8*i)\n for(i <- 0 until E16Depth) io.vs2e.e16(i) := io.vs2Data(16*(i+1)-1, 16*i)\n for(i <- 0 until E32Depth) io.vs2e.e32(i) := io.vs2Data(32*(i+1)-1, 32*i)\n"}
{"file": "rocket_chip_vpu/vpu/src/main/scala/VFDivSqrt.scala", "target_type": "block", "cursor_line": 34, "target_nlines": 1, "node_depth": 12, "node_path": ["compilation_unit", "class_definition", "template_body", "ERROR", "class_definition", "template_body", "function_definition", "call_expression", "field_expression", "call_expression", "arguments", "lambda_expression", "block"], "target": " def op_is(ops: UInt*) = ops.toList.map(x => {op === x}).reduceLeft(_ || _)\n"}
{"file": "rocket_chip_vpu/vpu/src/main/scala/VFSignInject.scala", "target_type": "block", "cursor_line": 31, "target_nlines": 5, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "for_expression", "block"], "target": " for(i <- 0 until f16Depth) {\n io.vFSgnJOut.f16(i) := MuxCase(Cat(io.vsrc1f.f16(i)(16), io.vsrc2f.f16(i)(15,0)),\n Array((io.fsgnjFun === FSgnJFun_Not) -> Cat(~io.vsrc1f.f16(i)(16), io.vsrc2f.f16(i)(15,0)),\n (io.fsgnjFun === FSgnJFun_Xor) -> Cat(io.vsrc1f.f16(i)(16) ^ io.vsrc2f.f16(i)(16), io.vsrc2f.f16(i)(15,0))))\n }\n"}
{"file": "rocket_chip_vpu/vpu/src/main/scala/VFWidthConvert.scala", "target_type": "function_definition", "cursor_line": 96, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " def F64ToS1: UInt = FType.S.recode(Mux(io.fromXData1(63,32).andR, io.fromXData1(31,0), qNaN32))\n"}
{"file": "rocket_chip_vpu/vpu/src/main/scala/VPUIO.scala", "target_type": "function_definition", "cursor_line": 131, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " override def cloneType = new VPUFPUResponse(FLEN).asInstanceOf[this.type]\n"}
{"file": "rocket_chip_vpu/vpu/src/main/scala/VPU_64V64E1L.scala", "target_type": "function_definition", "cursor_line": 156, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " def inMCPart3w = 23.U(6.W)\n"}
{"file": "rocket_chip_vpu/vpu/src/main/scala/VSplit.scala", "target_type": "block", "cursor_line": 293, "target_nlines": 5, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "for_expression", "block"], "target": " for(i <- 0 until e32Depth) io.vs2d.e32(i).d4(j) := io.vs2e.e32(i)((32/4)*(j+1)-1,(32/4)*j) \n for(i <- 0 until e64Depth) io.vs2d.e64(i).d4(j) := io.vs2e.e64(i)((64/4)*(j+1)-1,(64/4)*j) \n for(i <- 0 until e128Depth) io.vs2d.e128(i).d4(j) := io.vs2e.e128(i)((128/4)*(j+1)-1,(128/4)*j) \n for(i <- 0 until e256Depth) io.vs2d.e256(i).d4(j) := io.vs2e.e256(i)((256/4)*(j+1)-1,(256/4)*j) \n for(i <- 0 until e512Depth) io.vs2d.e512(i).d4(j) := io.vs2e.e512(i)((512/4)*(j+1)-1,(512/4)*j) \n"}
{"file": "rocket_chip_vpu/vpu/src/test/scala/VPU/VPUMain.scala", "target_type": "object_definition", "cursor_line": 58, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object VPUVerilog extends App with CustomConfig {\n chisel3.Driver.execute(args, () => new VPU_64V64E1L(customConfig, tagBits, addrBits))\n}\n"}
{"file": "rocket_chip_vpu/vpu/src/test/scala/VPU/VPUTest.scala", "target_type": "function_definition", "cursor_line": 331, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " def VLXH_V (vde: String, rs1: String = rs1, vs2e: String = vs2e, vm: String = \"1\") = (\"000\"+\"111\"+vm+vs2e +rs1+\"101\"+vde+\"0000111\", \"VLXH_V \")\n"}
{"file": "100DaysOfCHISEL/src/main/scala/day24/Mux_Case.scala", "target_type": "class_definition", "cursor_line": 4, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class LM_IO_Interface extends Bundle {\n"}
{"file": "100DaysOfCHISEL/src/main/scala/day26/branch_control.scala", "target_type": "block", "cursor_line": 19, "target_nlines": 3, "node_depth": 19, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "field_expression", "call_expression", "block", "call_expression", "field_expression", "call_expression", "call_expression", "field_expression", "call_expression", "call_expression", "field_expression", "call_expression", "call_expression", "field_expression", "call_expression", "block"], "target": " when ( io.fnct3 === 0.U ) {\n io.br_taken := io.arg_x === io.arg_y // Branch taken if arg_x is equal to arg_y\n }.elsewhen ( io.fnct3 === 1.U ) {\n"}
{"file": "100DaysOfCHISEL/src/main/scala/day27/ImmExtension.scala", "target_type": "class_definition", "cursor_line": 7, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class LM_IO_Interface_ImmdValGen extends Bundle {\n val instr = Input(UInt(32.W)) // 32-bit instruction input\n val pc_in = Input(SInt(32.W)) // 32-bit signed program counter input\n val immd_se = Output(UInt(32.W)) // 32-bit signed immediate output\n}\n"}
{"file": "100DaysOfCHISEL/src/main/scala/day29/ArbiterQueue.scala", "target_type": "class_definition", "cursor_line": 10, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "})\nval queue1 = Queue (io.in1 , 5)\n"}
{"file": "100DaysOfCHISEL/src/main/scala/day3/Bitwidth.scala", "target_type": "class_definition", "cursor_line": 9, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val output = Output(SInt(4.W))\r\n })\r\n"}
{"file": "100DaysOfCHISEL/src/test/scala/day1/Gates.scala", "target_type": "block", "cursor_line": 10, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " c.io.b.poke(2.U)\r\n"}
{"file": "100DaysOfCHISEL/src/test/scala/day14/Adder_Param_Test.scala", "target_type": "block", "cursor_line": 8, "target_nlines": 4, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block"], "target": " test(new Adder(32)){c=>\n c.io.in_0.poke(12.U)\n c.io.in_1.poke(4.U)\n c.clock.step(100)}\n"}
{"file": "100DaysOfCHISEL/src/test/scala/day18/TwoStageQueueTest.scala", "target_type": "block", "cursor_line": 16, "target_nlines": 3, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block"], "target": " c.clock.step(5)\n\n // Expect that the output bits should be 4.\n"}
{"file": "100DaysOfCHISEL/src/test/scala/day19/OneShotTimerTest.scala", "target_type": "block", "cursor_line": 9, "target_nlines": 3, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block"], "target": " test(new OneShotTimerModule()){c =>\n c.clock.step(10) \n }\n"}
{"file": "100DaysOfCHISEL/src/test/scala/day23/Mux_2to1test.scala", "target_type": "block", "cursor_line": 15, "target_nlines": 3, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block"], "target": " a.clock.step(4)\n\n }\n"}
{"file": "100DaysOfCHISEL/src/test/scala/day26/branch_controlTest.scala", "target_type": "block", "cursor_line": 10, "target_nlines": 5, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block"], "target": " test(new BranchControl()){c =>\n c.io.fnct3.poke(1.U) // Set input signals for the BranchControl module\n c.io.branch.poke(1.B)\n c.io.arg_x.poke(1.U)\n c.io.arg_y.poke(0.U)\n"}
{"file": "chiselverify/src/main/scala/chiselverify/assembly/BinaryLoader.scala", "target_type": "if_expression", "cursor_line": 22, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition", "block", "if_expression"], "target": " if (bytes(bytes.length - 1).length < 4) bytes(bytes.length - 1) = Array(0, 0, 0, 0)\n"}
{"file": "chiselverify/src/main/scala/chiselverify/assembly/Label.scala", "target_type": "function_definition", "cursor_line": 33, "target_nlines": 1, "node_depth": 7, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition", "block", "instance_expression", "template_body", "function_definition"], "target": " override def toAsm: String = s\"$id:\"\n"}
{"file": "chiselverify/src/main/scala/chiselverify/assembly/ProgramGenerator.scala", "target_type": "block", "cursor_line": 140, "target_nlines": 1, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " s\"$this\\n\\nInstruction histogram:\\n${this.histogram.map(_.toString()).mkString(\", \")}\\nCategory histogram:\\n${this.categoryHistogram.map(_.toString()).mkString(\", \")}\\n\"\n"}
{"file": "chiselverify/src/main/scala/chiselverify/crv/RandObj.scala", "target_type": "block", "cursor_line": 16, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "trait_definition", "template_body", "function_definition", "block"], "target": " def preRandomize(): Unit = {}\n"}
{"file": "chiselverify/src/main/scala/chiselverify/crv/backends/jacop/DistConstraint.scala", "target_type": "block", "cursor_line": 39, "target_nlines": 1, "node_depth": 14, "node_path": ["compilation_unit", "trait_definition", "template_body", "function_definition", "block", "match_expression", "case_block", "case_clause", "throw_expression", "call_expression", "arguments", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " case None => throw CRVException(s\"Something went wrong in the distribution selection of ${_var.toString}\")\n"}
{"file": "chiselverify/src/main/scala/chiselverify/crv/backends/jacop/IfCon.scala", "target_type": "function_definition", "cursor_line": 26, "target_nlines": 3, "node_depth": 5, "node_path": ["compilation_unit", "class_definition", "template_body", "class_definition", "template_body", "function_definition"], "target": " override def disable(): Unit = {\n crvc.disable()\n }\n"}
{"file": "chiselverify/src/main/scala/chiselverify/crv/backends/jacop/package.scala", "target_type": "function_definition", "cursor_line": 445, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "package_object", "template_body", "class_definition", "template_body", "function_definition"], "target": " def #^(that: U): U = this.^(that)\n"}
{"file": "chiselverify/src/main/scala/examples/heappriorityqueue/Interfaces.scala", "target_type": "function_definition", "cursor_line": 17, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "object_definition", "template_body", "class_definition", "template_body", "function_definition"], "target": " def >(that: Event): Bool = superCycle > that.superCycle || (superCycle === that.superCycle) && cycle > that.cycle\n"}
{"file": "chiselverify/src/main/scala/examples/heappriorityqueue/PriorityQueue.scala", "target_type": "class_definition", "cursor_line": 9, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "case class PriorityQueueParameters(size: Int, order: Int, superCycleWidth: Int, cycleWidth: Int, referenceIdWidth: Int)\n"}
{"file": "chiselverify/src/test/scala/examples/heappriorityqueue/MinFinderTest.scala", "target_type": "if_expression", "cursor_line": 21, "target_nlines": 1, "node_depth": 11, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "if_expression", "block", "val_definition", "call_expression", "arguments", "lambda_expression", "if_expression"], "target": " val candidates = Seq.tabulate(values.length)(i => if (cyclicMins.contains(i)) normals(i) else Int.MaxValue)\n"}
{"file": "chiselverify/src/test/scala/examples/leros/AluVerification.scala", "target_type": "if_expression", "cursor_line": 161, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "if_expression"], "target": " val tnumber = if(IsUnitTest) { 10 } else { 5000 }\n"}
{"file": "ofdm/rocket/src/test/scala/ofdm/AXI4StreamTimeAdapterSpec.scala", "target_type": "block", "cursor_line": 57, "target_nlines": 1, "node_depth": 7, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "infix_expression", "call_expression", "block"], "target": " chisel3.iotesters.Driver(() => new AXI4StreamTimeAdapaterTestModule) { new AXI4StreamTimeAdapterTester(_) } should be (true)\n"}
{"file": "ofdm/rocket/src/test/scala/ofdm/SyncBlockSpec.scala", "target_type": "block", "cursor_line": 106, "target_nlines": 3, "node_depth": 7, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "function_definition", "if_expression", "block"], "target": " def unsignedBigInt(i: BigInt): BigInt = if (i < 0) {\n (BigInt(2) << proto.getWidth) + i\n } else {\n"}
{"file": "ofdm/src/main/scala/ldpc/Encoder.scala", "target_type": "if_expression", "cursor_line": 11, "target_nlines": 1, "node_depth": 10, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition", "block", "val_definition", "call_expression", "arguments", "case_block", "case_clause", "if_expression"], "target": " if (w) g else Seq.fill(g.length)(false) })\n"}
{"file": "ofdm/src/main/scala/ofdm/AdjustableShiftRegister.scala", "target_type": "block", "cursor_line": 16, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition", "block"], "target": " adjustableShiftRegister.io.deq.ready := adjustableShiftRegister.io.count >= depth && en\n\n Mux(adjustableShiftRegister.io.deq.fire(), adjustableShiftRegister.io.deq.bits, resetData)\n"}
{"file": "ofdm/src/main/scala/ofdm/CPRemover.scala", "target_type": "block", "cursor_line": 23, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " cnt := cnt +% 1.U\n }\n }\n"}
{"file": "ofdm/src/main/scala/ofdm/Demod.scala", "target_type": "class_definition", "cursor_line": 12, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " out(0) := in.imag\n"}
{"file": "ofdm/src/main/scala/ofdm/FFT.scala", "target_type": "block", "cursor_line": 123, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "block"], "target": " val delays = (1 to nStages).map { n >> _ }\n"}
{"file": "ofdm/src/main/scala/ofdm/Packetizer.scala", "target_type": "block", "cursor_line": 24, "target_nlines": 3, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block"], "target": " when (count + 1.U === size.U) {\n nextCount := 0.U\n }\n"}
{"file": "ofdm/src/main/scala/ofdm/TreeReduce.scala", "target_type": "function_definition", "cursor_line": 4, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition"], "target": " def apply[V](in: Seq[V], func: (V, V) => V): V = {\n"}
{"file": "ofdm/src/test/scala/ldpc/LdpcSpec.scala", "target_type": "block", "cursor_line": 70, "target_nlines": 3, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "for_expression", "block", "infix_expression", "block"], "target": " it should s\"work for n = $i\" in {\n ShifterTester(i) should be (true)\n }\n"}
{"file": "ofdm/src/test/scala/ofdm/fft/TesterUtil.scala", "target_type": "if_expression", "cursor_line": 23, "target_nlines": 1, "node_depth": 7, "node_path": ["compilation_unit", "trait_definition", "template_body", "function_definition", "block", "while_expression", "block", "if_expression"], "target": " if (cyclesWaiting >= maxCyclesWait) { expect(false, \"waited for input too long\") }\n"}
{"file": "OpenNCB/src/main/scala/openncb/WithNCBParameters.scala", "target_type": "identifier", "cursor_line": 10, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "trait_definition", "template_body", "val_definition", "call_expression", "identifier"], "target": " val paramNCB = p(NCBParametersKey)\n"}
{"file": "OpenNCB/src/main/scala/openncb/axi/channel/AXI4ChannelAW.scala", "target_type": "function_definition", "cursor_line": 18, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition"], "target": " def apply()(implicit p: Parameters) = new AXI4ChannelAW(new AXI4BundleAW)\n"}
{"file": "OpenNCB/src/main/scala/openncb/chi/channel/package.scala", "target_type": "block", "cursor_line": 41, "target_nlines": 1, "node_depth": 13, "node_path": ["compilation_unit", "package_object", "template_body", "class_definition", "template_body", "function_definition", "block", "call_expression", "arguments", "infix_expression", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " s\"${dst.channelType.canonicalName} :>= ${src.channelType.canonicalName}\")\n"}
{"file": "OpenNCB/src/main/scala/openncb/logical/NCBOrderAddressCAM.scala", "target_type": "block", "cursor_line": 223, "target_nlines": 1, "node_depth": 12, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "arguments", "lambda_expression", "block", "call_expression", "arguments", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " s\"double allocation at [${i}]\")\n"}
{"file": "OpenNCB/src/main/scala/openncb/logical/NCBTransactionQueue.scala", "target_type": "block", "cursor_line": 1032, "target_nlines": 1, "node_depth": 12, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "arguments", "lambda_expression", "block", "call_expression", "arguments", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " s\"double allocation at [${i}]\")\n"}
{"file": "OpenNCB/src/main/scala/openncb/logical/NCBUpstreamRXDAT.scala", "target_type": "block", "cursor_line": 66, "target_nlines": 1, "node_depth": 11, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "indented_block", "throw_expression", "instance_expression", "arguments", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " throw new IllegalArgumentException(s\"unsupported CHI data width: ${width}\")\n"}
{"file": "OpenNCB/src/main/scala/openncb/logical/chi/AbstractCHILinkActiveManager.scala", "target_type": "class_definition", "cursor_line": 7, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "abstract class AbstractCHILinkActiveManager extends Module\n"}
{"file": "OpenNCB/src/main/scala/openncb/logical/chi/CHILinkCreditManagerTX.scala", "target_type": "block", "cursor_line": 32, "target_nlines": 1, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "arguments", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " s\"max maximum link credit count is ${CHI_MAX_REASONABLE_LINK_CREDIT_COUNT}, but ${paramMaxCount} configured\")\n"}
{"file": "OpenNCB/src/main/scala/openncb/util/AddressableReadWritePort.scala", "target_type": "class_definition", "cursor_line": 9, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class AddressableReadWritePort(val addressWidth: Int, val dataWidth: Int) extends Bundle {\n\n // Write Port\n val w = new AddressableWritePort(addressWidth, dataWidth)\n"}
{"file": "OpenNCB/src/main/scala/openncb/util/AddressableWritePort.scala", "target_type": "class_definition", "cursor_line": 11, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " // Write Port\n val en = Input(Bool())\n val addr = Input(UInt(addressWidth.W))\n val data = Input(UInt(dataWidth.W))\n"}
{"file": "OpenNCB/src/main/scala/openncb/util/package.scala", "target_type": "function_definition", "cursor_line": 20, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "package_object", "template_body", "class_definition", "template_body", "function_definition"], "target": " def BVec(n: Int): Vec[Bool] = Vec(n, boolean.B)\n"}
{"file": "sv2chisel/helpers/src/main/scala/tools/ModulePreset.scala", "target_type": "block", "cursor_line": 82, "target_nlines": 1, "node_depth": 17, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "function_definition", "block", "function_definition", "block", "match_expression", "case_block", "case_clause", "call_expression", "arguments", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " s\"[debug] Registering instance ${i.name} of ${i.module} for AsyncReset Propagation\"\n"}
{"file": "sv2chisel/helpers/src/test/scala/bundleconvertSpec.scala", "target_type": "block", "cursor_line": 29, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " val out = IO(Output(new MyBundle))\n"}
{"file": "sv2chisel/src/main/scala/sv2chisel/ir/ExpressionToLiteral.scala", "target_type": "class_definition", "cursor_line": 54, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " case _ => \n trace(e, s\"Cannot convert expression ${e.serialize} to Literal\")\n None\n }\n"}
{"file": "sv2chisel/src/main/scala/sv2chisel/transforms/FlowReferences.scala", "target_type": "match_expression", "cursor_line": 355, "target_nlines": 3, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "function_definition", "block", "match_expression", "case_block", "case_clause", "match_expression"], "target": " case (UnknownFlow, SinkFlow) => \n wasInferredSink += (r.serialize)\n debug(e, s\" > Recording that ${r.serialize} was used as sink\")\n"}
{"file": "sv2chisel/src/test/scala/BlackBoxSpec.scala", "target_type": "block", "cursor_line": 214, "target_nlines": 1, "node_depth": 11, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "infix_expression", "call_expression", "arguments", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " s\"${q}TESTS$q -> TESTS,\",\n"}
{"file": "sv2chisel/src/test/scala/DefLogicSpec.scala", "target_type": "block", "cursor_line": 58, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " | input rst,\n"}
{"file": "sv2chisel/src/test/scala/InstancesFlowSpec.scala", "target_type": "block", "cursor_line": 41, "target_nlines": 5, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " |wire post_out_b;\n |\n |assign post_out_u1 = inst_out_u1;\n |assign post_out_u2 = inst_out_u2;\n |assign post_out_u3 = inst_out_u3;\n"}
{"file": "sv2chisel/src/test/scala/LegalizeExpressionSpec.scala", "target_type": "block", "cursor_line": 72, "target_nlines": 5, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " \"\"\".stripMargin\n )\n debug(result)\n result should containStr (\"class Test() extends RawModule {\")\n result should containStr (\"val lhsc = Wire(Vec(32, Bool()))\")\n"}
{"file": "sv2chisel/src/test/scala/MacroSpecs.scala", "target_type": "block", "cursor_line": 30, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " \n result should containStr (\"val TRUC = 32\")\n result should containStr (\"val CALC = TRUC\")\n"}
{"file": "sv2chisel/src/test/scala/RemoveConcatSpec.scala", "target_type": "block", "cursor_line": 15, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " it should \"properly remove concats or use Cat\" in {\n val result = emitInModule(s\"\"\"\n |// might containStr more than the RAM due to moves\n"}
{"file": "sv2chisel/src/test/scala/UnpackedEmissionStyleSpec.scala", "target_type": "block", "cursor_line": 46, "target_nlines": 4, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " \"val w = Wire(Vec(4, UInt(2.W)))\",\n \"w(3) := 0.U\",\n \"w(2) := 3.U\",\n \"w(1) := 3.U\",\n"}
{"file": "riscv-boom/src/main/scala/v3/exu/execution-units/fpu.scala", "target_type": "class_definition", "cursor_line": 158, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class FpuReq()(implicit p: Parameters) extends BoomBundle\n"}
{"file": "riscv-boom/src/main/scala/v3/exu/execution-units/functional-unit.scala", "target_type": "class_definition", "cursor_line": 118, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class BrResolutionInfo(implicit p: Parameters) extends BoomBundle\n"}
{"file": "riscv-boom/src/main/scala/v3/exu/fp-pipeline.scala", "target_type": "class_definition", "cursor_line": 28, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class FpPipeline(implicit p: Parameters) extends BoomModule with tile.HasFPUParameters\n"}
{"file": "riscv-boom/src/main/scala/v3/exu/rename/rename-maptable.scala", "target_type": "if_expression", "cursor_line": 122, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "class_definition", "template_body", "for_expression", "block", "if_expression"], "target": " if (!float) io.map_resps(i).prs3 := DontCare\n"}
{"file": "riscv-boom/src/main/scala/v3/ifu/bpd/bim.scala", "target_type": "class_definition", "cursor_line": 16, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class BIMMeta(implicit p: Parameters) extends BoomBundle()(p)\n"}
{"file": "riscv-boom/src/main/scala/v3/ifu/bpd/loop.scala", "target_type": "block", "cursor_line": 62, "target_nlines": 1, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "class_definition", "template_body", "call_expression", "block"], "target": " when (reset_idx === (nSets-1).U) { doing_reset := false.B }\n"}
{"file": "riscv-boom/src/main/scala/v3/ifu/bpd/sw_predictor.scala", "target_type": "class_definition", "cursor_line": 80, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " addResource(\"/vsrc/predictor_harness.v\")\n addResource(\"/csrc/predictor_sw.cc\")\n}\n"}
{"file": "riscv-boom/src/main/scala/v3/util/util.scala", "target_type": "object_definition", "cursor_line": 624, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object FPRegToChars\n"}
{"file": "riscv-boom/src/main/scala/v4/exu/issue-units/issue-unit.scala", "target_type": "object_definition", "cursor_line": 80, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object IssueUnit\n"}
{"file": "riscv-boom/src/main/scala/v4/exu/rename/rename-maptable.scala", "target_type": "block", "cursor_line": 72, "target_nlines": 1, "node_depth": 9, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "arguments", "call_expression", "arguments", "infix_expression", "block"], "target": " val com_map_table = RegInit(VecInit((0 until numLregs) map { i => i.U(pregSz.W) }))\n"}
{"file": "riscv-boom/src/main/scala/v4/util/ParallelFindOne.scala", "target_type": "block", "cursor_line": 17, "target_nlines": 1, "node_depth": 7, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " override val desiredName = s\"Parallel_${decodeWidth}_f${favor}_FindOne\"\n"}
{"file": "homemade-riscv-en/chap04/01_LogicGatesVec/src/main/scala/LogicGatesVev.scala", "target_type": "class_definition", "cursor_line": 17, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " io.leds(1) := io.switches(0) & io.switches(1) // AND\n io.leds(2) := io.switches(0) | io.switches(1) // OR\n io.leds(3) := ~(io.switches(0) & io.switches(1)) // NAND\n"}
{"file": "homemade-riscv-en/chap04/02_IntCompare/src/main/scala/IntCompare.scala", "target_type": "class_definition", "cursor_line": 32, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " // Inequality operator is \"=/=\".\n io.not_5 := io.a =/= 5.U\n"}
{"file": "homemade-riscv-en/chap04/13_Shifter/src/main/scala/LeftShift.scala", "target_type": "object_definition", "cursor_line": 54, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object LeftShifter extends App {\n chisel3.Driver.execute(args, () => new LeftShifter)\n}\n"}
{"file": "homemade-riscv-en/chap04/13_Shifter/src/main/scala/Mux2.scala", "target_type": "function_definition", "cursor_line": 31, "target_nlines": 4, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition"], "target": " mux2.io.selector := selector\n mux2.io.in_0 := in_0\n mux2.io.in_1 := in_1\n mux2.io.out\n"}
{"file": "homemade-riscv-en/chap04/14_Multiplier/src/main/scala/Addr4Bit.scala", "target_type": "block", "cursor_line": 95, "target_nlines": 1, "node_depth": 7, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "arguments", "call_expression", "block"], "target": " val fullAdders = VecInit(Seq.fill(n){ Module(new FullAdder).io })\n"}
{"file": "homemade-riscv-en/chap05/00_SRLatch/src/main/scala/SRLatch.scala", "target_type": "object_definition", "cursor_line": 19, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object SRLatch extends App {\n chisel3.Driver.execute(args, () => new SRLatch)\n}\n"}
{"file": "homemade-riscv-en/chap05/01_DLatch/src/main/scala/SRLatch.scala", "target_type": "class_definition", "cursor_line": 9, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val set = Input(Bool())\n val reset = Input(Bool())\n"}
{"file": "homemade-riscv-en/chap05/04_EnRstFF/src/main/scala/SRLatch.scala", "target_type": "object_definition", "cursor_line": 19, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object SRLatch extends App {\n chisel3.Driver.execute(args, () => new SRLatch)\n}\n"}
{"file": "homemade-riscv-en/chap05/12_UART/src/main/scala/Seg7LED.scala", "target_type": "class_definition", "cursor_line": 10, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val cathodes = Output(UInt(7.W))\n /** For decimal point. It lights when it is 0, and goes out when it is 1. */\n"}
{"file": "homemade-riscv-en/chap05/14_VgaUartDisp/src/main/scala/CharVramWriter.scala", "target_type": "block", "cursor_line": 40, "target_nlines": 4, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "call_expression", "block"], "target": " when (io.charData.valid) {\n state := sRomRead\n yInChar := 0.U\n }\n"}
{"file": "homemade-riscv-en/chap07/01_PencilRocketII/src/main/scala/Uart.scala", "target_type": "block", "cursor_line": 74, "target_nlines": 3, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "call_expression", "block", "call_expression", "block"], "target": " } .otherwise {\n sendCount := sendCount + 1.U\n }\n"}
{"file": "homemade-riscv/chap04/01_LogicGatesVec/src/main/scala/LogicGatesVev.scala", "target_type": "class_definition", "cursor_line": 22, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " io.leds(6) := ~(io.switches(0) ^ io.switches(1)) // NXOR\n"}
{"file": "homemade-riscv/chap04/04_Mux4/src/main/scala/Mux4.scala", "target_type": "object_definition", "cursor_line": 26, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object Mux4 extends App {\n chisel3.Driver.execute(args, () => new Mux4())\n}\n"}
{"file": "homemade-riscv/chap04/09_FullAdder/src/main/scala/FullAdder.scala", "target_type": "object_definition", "cursor_line": 36, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object FullAdder extends App {\n chisel3.Driver.execute(args, () => new FullAdder)\n}\n"}
{"file": "homemade-riscv/chap04/12_LessThan/src/main/scala/Addr4Bit.scala", "target_type": "block", "cursor_line": 60, "target_nlines": 1, "node_depth": 7, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "arguments", "call_expression", "block"], "target": " val fullAdders = VecInit(Seq.fill(4){ Module(new FullAdder).io }) // [注意]ioを渡している\n"}
{"file": "homemade-riscv/chap04/13_Shifter/src/main/scala/LeftShift.scala", "target_type": "class_definition", "cursor_line": 25, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " mux1.io.in_0 := io.in(1)\n mux1.io.in_1 := io.in(0)\n"}
{"file": "homemade-riscv/chap04/14_Multiplier/src/main/scala/Multiplier.scala", "target_type": "block", "cursor_line": 101, "target_nlines": 1, "node_depth": 7, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "arguments", "for_expression", "block"], "target": " val adderLsbs = Cat(for (i <- (n - 2) to 0 by -1) yield { adders(i).sum(0) })\n"}
{"file": "homemade-riscv/chap05/02_DFlipFlop/src/main/scala/SRLatch.scala", "target_type": "object_definition", "cursor_line": 19, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object SRLatch extends App {\n chisel3.Driver.execute(args, () => new SRLatch)\n}\n"}
{"file": "homemade-riscv/chap05/03_SyncResetFF/src/main/scala/DLatch.scala", "target_type": "object_definition", "cursor_line": 21, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object DLatch extends App {\n chisel3.Driver.execute(args, () => new DLatch)\n}\n"}
{"file": "homemade-riscv/chap05/09_Stopwatch/src/main/scala/Stopwatch.scala", "target_type": "object_definition", "cursor_line": 32, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object Stopwatch extends App {\n chisel3.Driver.execute(args, () => new Stopwatch)\n}\n"}
{"file": "homemade-riscv/chap05/15_SvgaUartDisp/src/main/scala/Uart.scala", "target_type": "class_definition", "cursor_line": 10, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val rxData = Input(Bool())\n val txData = Output(Bool())\n val rts = Output(Bool())\n val cts = Input(Bool())\n"}
{"file": "homemade-riscv/chap07/00_PencilRocketI/src/main/scala/NegEdge.scala", "target_type": "class_definition", "cursor_line": 10, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val d = Input(Bool())\n val pulse = Output(Bool())\n"}
{"file": "CHISEL-Projects/src/main/scala/lab7/lab7ex1.scala", "target_type": "class_definition", "cursor_line": 6, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val in1 = Flipped(Decoupled(UInt(8.W))) //ready-> output , valid->input\n"}
{"file": "CHISEL-Projects/src/main/scala/lab8/lab8ex1.scala", "target_type": "block", "cursor_line": 22, "target_nlines": 3, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "field_expression", "call_expression", "block"], "target": " when(io.mask(3)){\n data(3):=io.dataIn(3)\n }.otherwise{\n"}
{"file": "CHISEL-Projects/src/main/scala/labs/lab1task1.scala", "target_type": "block", "cursor_line": 12, "target_nlines": 3, "node_depth": 21, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "field_expression", "call_expression", "call_expression", "field_expression", "call_expression", "call_expression", "field_expression", "call_expression", "call_expression", "field_expression", "call_expression", "call_expression", "field_expression", "call_expression", "call_expression", "field_expression", "call_expression", "block"], "target": " when(io.sel===0.U){\n io.x:=io.a + io.b\n }.elsewhen(io.sel===1.U){\n"}
{"file": "CHISEL-Projects/src/main/scala/labs/lab3ex1.scala", "target_type": "block", "cursor_line": 16, "target_nlines": 1, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block"], "target": " is(\"b1000\".U){io.out:=\"b11\".U}\n"}
{"file": "CHISEL-Projects/src/test/scala/lab1/lab1ex2test.scala", "target_type": "block", "cursor_line": 8, "target_nlines": 5, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block"], "target": " test(new resetcounter(5)){c=>\n c.clock.step(20)\n c.io.result.expect(0.B)\n\n }\n"}
{"file": "CHISEL-Projects/src/test/scala/lab2/lab2ex1test.scala", "target_type": "class_definition", "cursor_line": 6, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class mux2test extends FreeSpec with ChiselScalatestTester {\n"}
{"file": "CHISEL-Projects/src/test/scala/labs/lab3ex2test.scala", "target_type": "class_definition", "cursor_line": 6, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " \"ALU Test\" in {\n test(new ALU()){c=>\n c.io.in_A.poke(4.U)\n c.io.in_B.poke(5.U)\n c.io.alu_Op.poke(4.U)\n"}
{"file": "CHISEL-Projects/src/test/scala/labs/lab5task1test.scala", "target_type": "block", "cursor_line": 7, "target_nlines": 3, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block"], "target": " test(new Adder5(32)){c=>\n c.io.in0.poke(2.U)\n c.io.in1.poke(2.U)\n"}
{"file": "CHISEL-Projects/src/test/scala/practice/NANDtest.scala", "target_type": "block", "cursor_line": 7, "target_nlines": 4, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " \"NAND Gate Test\" in {\n test(new NAND()){c=>\n c.io.a.poke(8.S)\n c.io.b.poke(15.S)\n"}
{"file": "CHISEL-Projects/src/test/scala/practice/fulladdertest.scala", "target_type": "block", "cursor_line": 10, "target_nlines": 5, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block"], "target": " c.io.b.poke(-15.S)\n c.io.c.poke(2.S)\n c.clock.step(1)\n c.io.sum.expect(-5.S)\n c.io.cout.expect(0.S)\n"}
{"file": "CHISEL-Projects/src/test/scala/practice/halfaddertest.scala", "target_type": "block", "cursor_line": 8, "target_nlines": 2, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " test(new halfadder()){c=>\n c.io.a.poke(8.S)\n"}
{"file": "chipyard/generators/chipyard/src/main/scala/clocking/CanHaveClockTap.scala", "target_type": "object_definition", "cursor_line": 13, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "case object ClockTapKey extends Field[Boolean](true)\n"}
{"file": "chipyard/generators/chipyard/src/main/scala/config/BoomConfigs.scala", "target_type": "class_definition", "cursor_line": 92, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class MegaBoomV4Config extends Config(\n new boom.v4.common.WithNMegaBooms(1) ++ // mega boom config\n new chipyard.config.WithSystemBusWidth(128) ++\n new chipyard.config.AbstractConfig)\n"}
{"file": "chipyard/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala", "target_type": "object_definition", "cursor_line": 15, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "case object MultiRoCCKey extends Field[Map[Int, Seq[Parameters => LazyRoCC]]](Map.empty[Int, Seq[Parameters => LazyRoCC]])\n"}
{"file": "chipyard/generators/chipyard/src/main/scala/example/EmptyChipTop.scala", "target_type": "class_definition", "cursor_line": 14, "target_nlines": 3, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "class_definition"], "target": " class Impl extends LazyRawModuleImp(this) with DontTouch {\n // Your custom non-rocketchip-soc stuff here\n }\n"}
{"file": "chipyard/generators/chipyard/src/main/scala/example/TutorialTile.scala", "target_type": "function_definition", "cursor_line": 130, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "block", "val_definition", "instance_expression", "template_body", "function_definition"], "target": " override def parent = Some(ResourceAnchors.cpus)\n"}
{"file": "chipyard/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala", "target_type": "block", "cursor_line": 145, "target_nlines": 4, "node_depth": 7, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "instance_expression", "template_body", "function_definition", "block"], "target": " override def describe(resources: ResourceBindings): Description = {\n val Description(name, mapping) = super.describe(resources)\n Description(name, mapping)\n }\n"}
{"file": "chipyard/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala", "target_type": "object_definition", "cursor_line": 25, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "case object HarnessBinderClockFrequencyKey extends Field[Double](100.0) // MHz\n"}
{"file": "chipyard/generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala", "target_type": "class_definition", "cursor_line": 6, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class UnitTestSuite(implicit p: Parameters) extends freechips.rocketchip.unittest.UnitTestSuite {\n ElaborationArtefacts.add(\"plusArgs\", PlusArgArtefacts.serialize_cHeader)\n}\n"}
{"file": "chipyard/generators/chipyard/src/test/scala/clocking/SimplePllConfigurationSpec.scala", "target_type": "block", "cursor_line": 17, "target_nlines": 1, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "infix_expression", "infix_expression", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " it should s\"select a reference of ${expected} MHz for ${freqStr} MHz\" in {\n"}
{"file": "chipyard/generators/firechip/bridgeinterfaces/src/main/scala/UART.scala", "target_type": "class_definition", "cursor_line": 34, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "case class UARTKey(div: Int)\n"}
{"file": "chipyard/generators/firechip/bridgestubs/src/main/scala/uart/UARTBridge.scala", "target_type": "function_definition", "cursor_line": 50, "target_nlines": 2, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition"], "target": " ep\n }\n"}
{"file": "rocket-chip/src/main/scala/amba/axi4/Xbar.scala", "target_type": "block", "cursor_line": 286, "target_nlines": 1, "node_depth": 7, "node_path": ["compilation_unit", "block", "function_definition", "block", "call_expression", "arguments", "infix_expression", "block"], "target": " assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n"}
{"file": "rocket-chip/src/main/scala/devices/tilelink/MasterMux.scala", "target_type": "function_definition", "cursor_line": 93, "target_nlines": 1, "node_depth": 7, "node_path": ["compilation_unit", "class_definition", "template_body", "class_definition", "template_body", "if_expression", "block", "function_definition"], "target": " def castC(x: TLBundleC) = { val ret = Wire(out.c.bits); ret <> x; ret }\n"}
{"file": "rocket-chip/src/main/scala/interrupts/BlockDuringReset.scala", "target_type": "class_definition", "cursor_line": 11, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class IntBlockDuringReset(stretchResetCycles: Int = 0)(implicit p: Parameters) extends LazyModule\n"}
{"file": "rocket-chip/src/main/scala/interrupts/Xbar.scala", "target_type": "block", "cursor_line": 23, "target_nlines": 1, "node_depth": 9, "node_path": ["compilation_unit", "class_definition", "template_body", "class_definition", "template_body", "function_definition", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " override def desiredName = s\"IntXbar_i${intnode.in.size}_o${intnode.out.size}\"\n"}
{"file": "rocket-chip/src/main/scala/prci/ResetWrangler.scala", "target_type": "block", "cursor_line": 33, "target_nlines": 3, "node_depth": 7, "node_path": ["compilation_unit", "class_definition", "template_body", "class_definition", "template_body", "val_definition", "call_expression", "block"], "target": " val debounced = withClockAndReset(slowIn.clock, causes) {\n AsyncResetReg(incremented, 0, increment, Some(\"debounce\"))\n }\n"}
{"file": "rocket-chip/src/main/scala/subsystem/MemoryBus.scala", "target_type": "function_definition", "cursor_line": 53, "target_nlines": 1, "node_depth": 2, "node_path": ["compilation_unit", "block", "function_definition"], "target": " def busView: TLEdge = xbar.node.edges.in.head\n"}
{"file": "rocket-chip/src/main/scala/system/SimAXIMem.scala", "target_type": "block", "cursor_line": 30, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "block"], "target": " val io_axi4 = InModuleBody { node.makeIOs() }\n"}
{"file": "rocket-chip/src/main/scala/tilelink/Nodes.scala", "target_type": "block", "cursor_line": 153, "target_nlines": 1, "node_depth": 9, "node_path": ["compilation_unit", "class_definition", "template_body", "generic_function", "infix_expression", "infix_expression", "call_expression", "arguments", "assignment_expression", "block"], "target": " dFn = { p => p.base.v1copy(minLatency = 1) },\n"}
{"file": "rocket-chip/src/main/scala/util/ClockGate.scala", "target_type": "class_definition", "cursor_line": 54, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class EICG_wrapper extends ClockGate\n"}
{"file": "rocket-chip/src/main/scala/util/CoreMonitor.scala", "target_type": "class_definition", "cursor_line": 10, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class CoreMonitorBundle(val xLen: Int, val fLen: Int) extends Bundle with Clocked {\n val excpt = Bool()\n val priv_mode = UInt(width = 3.W)\n val hartid = UInt(width = xLen.W)\n val timer = UInt(width = 32.W)\n"}
{"file": "rocket-chip/src/main/scala/util/DescribedSRAM.scala", "target_type": "block", "cursor_line": 19, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition", "block"], "target": " mem.suggestName(name)\n\n val granWidth = data match {\n"}
{"file": "chiseltest/src/main/scala/chiseltest/coverage/FsmCoveragePass.scala", "target_type": "function_definition", "cursor_line": 113, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition", "block", "function_definition"], "target": " def inPrevState(s: BigInt): ir.Expression = Utils.eq(prevState, ir.UIntLiteral(s, ir.IntWidth(regWidth)))\n"}
{"file": "chiseltest/src/main/scala/chiseltest/simulator/BlackBox.scala", "target_type": "block", "cursor_line": 18, "target_nlines": 1, "node_depth": 13, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition", "block", "if_expression", "block", "if_expression", "block", "val_definition", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " val windowsfFile = s\"${fFile.toString()}.win\"\n"}
{"file": "chiseltest/src/main/scala/chiseltest/simulator/VerilatorSimulator.scala", "target_type": "block", "cursor_line": 52, "target_nlines": 1, "node_depth": 16, "node_path": ["compilation_unit", "object_definition", "template_body", "val_definition", "block", "val_definition", "call_expression", "field_expression", "call_expression", "field_expression", "field_expression", "call_expression", "field_expression", "call_expression", "arguments", "if_expression", "block"], "target": " if (JNAUtils.isWindows) { \"verilator_bin\" }\n"}
{"file": "chiseltest/src/main/scala/chiseltest/simulator/jna/JNASimulatorContext.scala", "target_type": "block", "cursor_line": 82, "target_nlines": 1, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "if_expression", "block"], "target": " if (isStale) { update() }\n"}
{"file": "chiseltest/src/main/scala/treadle2/executable/ClockInfo.scala", "target_type": "function_definition", "cursor_line": 33, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "function_definition"], "target": " def detail = s\"(up: $upPeriod, down: $downPeriod)\"\n"}
{"file": "chiseltest/src/test/scala/chiseltest/backends/icarus/IcarusBlackBoxTest.scala", "target_type": "class_definition", "cursor_line": 60, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class PlusArgReaderWrapper(expected: Int) extends Module {\n val reader = Module(new PlusArgReader)\n val msg = s\"Expected $expected, got %x.\\n\" // this works around the fact that s\"..\" is forbidden in the assert\n assert(reader.io.out === expected.U, msg, reader.io.out)\n}\n"}
{"file": "chiseltest/src/test/scala/chiseltest/formal/MagicPacketTrackerTests.scala", "target_type": "block", "cursor_line": 246, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "call_expression", "block"], "target": " io.enq.ready := emptyBits.reduce { _ || _ } // any empties?\n"}
{"file": "chiseltest/src/test/scala/chiseltest/formal/examples/SvaDemos.scala", "target_type": "if_expression", "cursor_line": 132, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "if_expression"], "target": " if (cStr.nonEmpty) c := seq(cStr)\n"}
{"file": "chiseltest/src/test/scala/chiseltest/iotesters/examples/GCDCalculator.scala", "target_type": "block", "cursor_line": 12, "target_nlines": 3, "node_depth": 6, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition", "block", "if_expression", "block"], "target": " } else {\n computeGcdResultsAndCycles(b, a % b, depth + 1)\n }\n"}
{"file": "chiseltest/src/test/scala/chiseltest/iotesters/examples/SecondClockDrivesRegisterSpec.scala", "target_type": "block", "cursor_line": 52, "target_nlines": 3, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "infix_expression", "block"], "target": " \"should work with Treadle\" in {\n test(new SecondClock).runPeekPoke(new SecondClockTester(_))\n }\n"}
{"file": "chiseltest/src/test/scala/chiseltest/simulator/WaveformCompliance.scala", "target_type": "function_definition", "cursor_line": 120, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " private def testDirFiles(): Seq[os.Path] = os.list(targetDir).filter(os.isFile)\n"}
{"file": "XiangShan/src/main/scala/top/Generator.scala", "target_type": "block", "cursor_line": 25, "target_nlines": 5, "node_depth": 4, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition", "block"], "target": " def execute(args: Array[String], mod: => chisel3.RawModule, firtoolOpts: Array[String]) = {\n val annotations = firtoolOpts.map(FirtoolOption.apply).toSeq\n\n (new XiangShanStage).execute(args, ChiselGeneratorAnnotation(() => mod) +: annotations)\n }\n"}
{"file": "XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala", "target_type": "block", "cursor_line": 18, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition", "block"], "target": " def apply(reg: UInt, emul: UInt): Bool = {\n emul === \"b101\".U && reg(0) =/= 0.U || emul === \"b110\".U && reg(1, 0) =/= 0.U || emul === \"b111\".U && reg(2, 0) =/= 0.U\n }\n"}
{"file": "XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala", "target_type": "block", "cursor_line": 386, "target_nlines": 1, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "arguments", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " XSDebug(func === ALUOpType.lui32addw, p\"[alu] func lui32w: add_src1=${Hexadecimal(addModule.io.srcw)} add_src2=${Hexadecimal(addModule.io.src(1)(31,0))} addres=${Hexadecimal(addw)}\\n\")\n"}
{"file": "XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala", "target_type": "object_definition", "cursor_line": 118, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "object_definition"], "target": " object CSRField55Bits extends CSREnum with CSRMacroApply\n"}
{"file": "XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala", "target_type": "function_definition", "cursor_line": 343, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "trait_definition", "template_body", "function_definition"], "target": " def GOING = BASE + 0x104\n"}
{"file": "XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala", "target_type": "function_definition", "cursor_line": 69, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "trait_definition", "template_body", "function_definition"], "target": " def IRQ_DEBUG = 17\n"}
{"file": "XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/JumpUnit.scala", "target_type": "class_definition", "cursor_line": 37, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val redirectValid = io.out.bits.res.redirect.get.valid\n redirectValid := io.in.valid && !jumpDataModule.io.isAuipc\n redirect := 0.U.asTypeOf(redirect)\n redirect.level := RedirectLevel.flushAfter\n"}
{"file": "XiangShan/src/main/scala/xiangshan/backend/regcache/RegCacheTagTable.scala", "target_type": "block", "cursor_line": 35, "target_nlines": 1, "node_depth": 9, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "arguments", "infix_expression", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " s\"writePorts: ${backendParams.getIntExuRCWriteSize} + ${backendParams.getMemExuRCWriteSize}\")\n"}
{"file": "XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/AtomicsReplayUnit.scala", "target_type": "block", "cursor_line": 126, "target_nlines": 3, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block"], "target": " when (io.lsu.resp.fire) {\n state := s_invalid\n }\n"}
{"file": "XiangShan/src/main/scala/xiangshan/mem/lsqueue/FreeList.scala", "target_type": "block", "cursor_line": 65, "target_nlines": 1, "node_depth": 11, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "field_expression", "call_expression", "arguments", "call_expression", "arguments", "lambda_expression", "block"], "target": " VecInit((0 until size / freeWidth).map(i => { input(freeWidth * i + rem) })).asUInt\n"}
{"file": "XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StridePrefetcher.scala", "target_type": "block", "cursor_line": 186, "target_nlines": 1, "node_depth": 9, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "arguments", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " val l1_stride_ratio_const = Constantin.createRecord(s\"l1_stride_ratio${p(XSCoreParamsKey).HartId}\", initValue = 2)\n"}
|