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{"file": "ChiselAIA/src/main/scala/Example-axi.scala", "target_type": "block", "cursor_line": 57, "target_nlines": 1, "node_depth": 24, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "arguments", "lambda_expression", "block", "val_definition", "field_expression", "call_expression", "arguments", "call_expression", "instance_expression", "arguments", "lambda_expression", "match_expression", "case_block", "case_clause", "call_expression", "arguments", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " case _ => assert(false, f\"unknown address ${addrSet.base}\"); 0\n"}
{"file": "ChiselAIA/src/main/scala/Example.scala", "target_type": "block", "cursor_line": 43, "target_nlines": 1, "node_depth": 13, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "arguments", "lambda_expression", "block", "call_expression", "arguments", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " require(memberID < aplic_params.membersNum, f\"memberID ${memberID} should less than membersNum ${aplic_params.membersNum}\")\n"}
{"file": "ChiselAIA/src/main/scala/IMSIC.scala", "target_type": "if_expression", "cursor_line": 610, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "indented_block", "if_expression"], "target": " if (params.HasTEEIMSIC) Some(LazyModule(new TLRegIMSIC(params, beatBytes)(Parameters.empty))) else None\n"}
{"file": "ChiselAIA/src/main/scala/IMSICParameters.scala", "target_type": "object_definition", "cursor_line": 9, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "case object IMSICParameKey extends Field[IMSICParameters]\n"}
{"file": "ChiselAIA/src/main/scala/common.scala", "target_type": "block", "cursor_line": 466, "target_nlines": 1, "node_depth": 11, "node_path": ["compilation_unit", "block", "class_definition", "template_body", "infix_expression", "case_block", "case_clause", "infix_expression", "case_block", "case_clause", "call_expression", "block"], "target": " when (in.b.fire && s) { r := r + 1.U }\n"}
{"file": "asyncfifo/src/main/scala/AsyncQueue.scala", "target_type": "block", "cursor_line": 159, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " io.async.index.foreach { _ := index }\n"}
{"file": "asyncfifo/src/main/scala/AsyncResetReg.scala", "target_type": "function_definition", "cursor_line": 98, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition"], "target": " def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B)\n"}
{"file": "asyncfifo/src/main/scala/CompileOptions.scala", "target_type": "object_definition", "cursor_line": 7, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object CompileOptions {\n /** Compatibility mode semantics except Module implicit reset should be inferred instead of Bool */\n implicit val NotStrictInferReset = NotStrict.copy(inferModuleReset = true)\n}"}
{"file": "asyncfifo/src/main/scala/Crossing.scala", "target_type": "class_definition", "cursor_line": 19, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "abstract class Crossing[T <: Data] extends RawModule {\n val io: CrossingIO[T]\n}"}
{"file": "asyncfifo/src/main/scala/ShiftReg.scala", "target_type": "block", "cursor_line": 58, "target_nlines": 1, "node_depth": 13, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "block", "lambda_expression", "indented_block", "call_expression", "arguments", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " Module (new AsyncResetRegVec(w, init)).suggestName(s\"${name}_${i}\")\n"}
{"file": "asyncfifo/src/main/scala/SynchronizerReg.scala", "target_type": "if_expression", "cursor_line": 51, "target_nlines": 1, "node_depth": 9, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "block", "lambda_expression", "indented_block", "val_definition", "if_expression"], "target": " val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)\n"}
{"file": "asyncfifo/src/main/scala/package.scala", "target_type": "function_definition", "cursor_line": 31, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "package_object", "template_body", "class_definition", "template_body", "function_definition"], "target": " def option[T](z: => T): Option[T] = if (x) Some(z) else None\n"}
{"file": "simpleinst/src/main/scala/BpfCircuitConstructor.scala", "target_type": "function_definition", "cursor_line": 51, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "trait_definition", "template_body", "class_definition", "template_body", "function_definition"], "target": " def set(ind: Int, data: LazyData): Context = copy(regMapping = regMapping.updated(ind, data))\n"}
{"file": "simpleinst/src/main/scala/BpfLoader.scala", "target_type": "match_expression", "cursor_line": 102, "target_nlines": 2, "node_depth": 6, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition", "block", "val_definition", "match_expression"], "target": " case SHT_SYMTAB => SymtabSection\n case SHT_REL => RelSection\n"}
{"file": "simpleinst/src/main/scala/ElfConstants.scala", "target_type": "function_definition", "cursor_line": 64, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "object_definition", "template_body", "object_definition", "template_body", "function_definition"], "target": " def r_type(x: Long): Int = x.toInt\n"}
{"file": "simpleinst/src/main/scala/Serializer.scala", "target_type": "block", "cursor_line": 35, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block"], "target": " retired := false.B\n }\n previousReqs += thisReq\n"}
{"file": "simpleinst/src/main/scala/SimpleInstRoCC.scala", "target_type": "class_definition", "cursor_line": 15, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "class_definition"], "target": " final case class BpfDescriptions(instructions: Map[Int, Seq[BpfInsn]], instrumentations: Seq[OpcodeHandler])\n"}
{"file": "simpleinst/src/test/scala/CircuitConstructorSpec.scala", "target_type": "block", "cursor_line": 120, "target_nlines": 1, "node_depth": 15, "node_path": ["compilation_unit", "object_definition", "template_body", "class_definition", "template_body", "call_expression", "case_block", "case_clause", "if_expression", "block", "call_expression", "arguments", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " expect(peek(dut.io.ready(i)) == 0, s\"Circuit should not finish its calculations before ${steps}th step\")\n"}
{"file": "simpleinst/src/test/scala/SerializerSpec.scala", "target_type": "block", "cursor_line": 53, "target_nlines": 4, "node_depth": 8, "node_path": ["compilation_unit", "object_definition", "template_body", "class_definition", "template_body", "for_expression", "block", "function_definition", "block"], "target": " def test(x: Bool, t1: Int, t2: Int, label: String): Unit = {\n val expected = (t + 1) >= t1 && (t + 1) <= t2\n expect((peek(x) != 0) == expected, s\"$label should be $expected\")\n }\n"}
{"file": "riscv32-cpu-chisel/src/main/scala/Consts.scala", "target_type": "object_definition", "cursor_line": 44, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": " val OP1_RS1 = 0.U(OP1_LEN.W)\n val OP1_PC = 1.U(OP1_LEN.W)\n val OP1_NONE = 2.U(OP1_LEN.W)\n"}
{"file": "riscv32-cpu-chisel/src/main/scala/Instructions.scala", "target_type": "object_definition", "cursor_line": 34, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": " // Compare\n val SLT = BitPat(\"b0000000??????????010?????0110011\")\n val SLTU = BitPat(\"b0000000??????????011?????0110011\")\n val SLTI = BitPat(\"b?????????????????010?????0010011\")\n val SLTIU = BitPat(\"b?????????????????011?????0010011\")\n"}
{"file": "riscv32-cpu-chisel/src/main/scala/Main.scala", "target_type": "block", "cursor_line": 16, "target_nlines": 4, "node_depth": 4, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition", "block"], "target": " return (a, args.take(i-1) ++ args.drop(i + 1))\n }\n }\n }\n"}
{"file": "riscv32-cpu-chisel/src/main/scala/Memory.scala", "target_type": "class_definition", "cursor_line": 45, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " io.dmem.rdata := Cat(\n mem(io.dmem.addr + 3.U(WORD_LEN.W)),\n"}
{"file": "riscv32-cpu-chisel/src/main/scala/Top.scala", "target_type": "class_definition", "cursor_line": 24, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " io.pc := core.io.pc\n"}
{"file": "riscv32-cpu-chisel/src/test/scala/CTests.scala", "target_type": "block", "cursor_line": 17, "target_nlines": 3, "node_depth": 12, "node_path": ["compilation_unit", "class_definition", "template_body", "for_expression", "block", "infix_expression", "block", "call_expression", "block", "lambda_expression", "indented_block", "while_expression", "block"], "target": " while (!c.io.exit.peek().litToBoolean) {\n c.clock.step(1)\n }\n"}
{"file": "riscv32-cpu-chisel/src/test/scala/RiscvTests.scala", "target_type": "block", "cursor_line": 11, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "for_expression", "block"], "target": " for (f <- new File(\"./riscv-tests-results\").listFiles.filter(f => f.isFile && f.getName.endsWith(\".hex\"))) {\n"}
{"file": "riscv32-cpu-chisel/src/test/scala/RustTests.scala", "target_type": "class_definition", "cursor_line": 18, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " c.clock.step(1)\n }\n }\n }\n }\n"}
{"file": "perfect-chisel/src/main/scala/perfect/random/Lfsr.scala", "target_type": "class_definition", "cursor_line": 88, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class Lfsr16 extends Lfsr(16)\n"}
{"file": "perfect-chisel/src/main/scala/perfect/random/Prng.scala", "target_type": "class_definition", "cursor_line": 19, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class PrngIo(n: Int) extends Bundle {\n val seed = Input(Valid(UInt(n.W)))\n val y = Output(UInt(n.W))\n}\n"}
{"file": "perfect-chisel/src/main/scala/perfect/util/Counter.scala", "target_type": "block", "cursor_line": 36, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when (io.extReset || io.wrap) { value := 0.U }\n"}
{"file": "perfect-chisel/src/main/scala/perfect/util/Fletcher.scala", "target_type": "class_definition", "cursor_line": 38, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val b = RegInit(UInt((n/2).W), 0.U)\n\n val do_reset = io.data.fire() && io.data.bits.cmd === k_reset.U\n val do_compute = io.data.fire() && io.data.bits.cmd === k_compute.U\n"}
{"file": "perfect-chisel/src/main/scala/perfect/util/NoDedup.scala", "target_type": "identifier", "cursor_line": 23, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "trait_definition", "template_body", "call_expression", "arguments", "identifier"], "target": " doNotDedup(self)\n"}
{"file": "perfect-chisel/src/main/scala/perfect/util/PWM.scala", "target_type": "block", "cursor_line": 31, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when (io.enable) { count := count + 1.U }\n"}
{"file": "perfect-chisel/src/main/scala/perfect/util/Piso.scala", "target_type": "class_definition", "cursor_line": 19, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class PisoCmd(n: Int) extends Bundle {\n val data = UInt(n.W)\n val count = UInt(log2Ceil(n).W)\n}\n"}
{"file": "perfect-chisel/src/main/scala/perfect/util/Printf.scala", "target_type": "function_definition", "cursor_line": 25, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "trait_definition", "template_body", "function_definition"], "target": " def printfWarn (m: String, a: Bits*) { pp(\"[WARN] \", printfSigil++m, a:_*) }\n"}
{"file": "perfect-chisel/src/test/scala/random/Lfsr.scala", "target_type": "class_definition", "cursor_line": 54, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class Lfsr16Test extends LfsrTester(16)\n"}
{"file": "MultiScalarMultiplication/src/main/scala/MSM/Bucket.scala", "target_type": "block", "cursor_line": 28, "target_nlines": 5, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when (io.load) {\n x := io.px\n y := io.py\n s := io.s\n }\n"}
{"file": "MultiScalarMultiplication/src/main/scala/MSM/Interfaces.scala", "target_type": "function_definition", "cursor_line": 27, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " override def cloneType = (new PointProjectiveBundle(w)).asInstanceOf[this.type]\n"}
{"file": "MultiScalarMultiplication/src/main/scala/MSM/PAddReduction.scala", "target_type": "block", "cursor_line": 50, "target_nlines": 4, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "for_expression", "block"], "target": " for (i <- 0 until numPoints) {\n xvec(i) := io.xs(i)\n yvec(i) := io.ys(i)\n }\n"}
{"file": "MultiScalarMultiplication/src/main/scala/MSM/PMNaive.scala", "target_type": "block", "cursor_line": 129, "target_nlines": 3, "node_depth": 11, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "call_expression", "call_expression", "field_expression", "call_expression", "block"], "target": " when (s === 2.S) {\n state := idle\n io.valid := true.B\n"}
{"file": "MultiScalarMultiplication/src/main/scala/MSM/PointAddition.scala", "target_type": "class_definition", "cursor_line": 49, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val inverses = p1x === p2x && p1y === -p2y\n"}
{"file": "MultiScalarMultiplication/src/main/scala/MSM/TopLevelMSM.scala", "target_type": "block", "cursor_line": 43, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "infix_expression", "block"], "target": " val xregseq = io.pointsx map { x => RegEnable(x, 0.S, io.load) }\n"}
{"file": "MultiScalarMultiplication/src/test/scala/MSM/EllipticCurve.scala", "target_type": "class_definition", "cursor_line": 13, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class EllipticCurve(A: BigInt, B: BigInt, P: BigInt) {\n val a: BigInt = A\n val b: BigInt = B\n val p: BigInt = P\n //val g: Point = G\n"}
{"file": "MultiScalarMultiplication/src/test/scala/MSM/MSMtest.scala", "target_type": "block", "cursor_line": 133, "target_nlines": 1, "node_depth": 7, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "assignment_expression", "infix_expression", "block"], "target": " allinputs = (0 until 1000) flatMap { i => allinputs }\n"}
{"file": "MultiScalarMultiplication/src/test/scala/MSM/Point.scala", "target_type": "function_definition", "cursor_line": 54, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " def unary_- = new Point(this.x, this.y * -1, this.curve)\n"}
{"file": "MultiScalarMultiplication/src/test/scala/MSM/Util.scala", "target_type": "block", "cursor_line": 51, "target_nlines": 1, "node_depth": 6, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition", "block", "infix_expression", "block"], "target": " g zip e map { case (gi, ei) => gi * ei } reduce {_ + _}\n"}
{"file": "KyogenRV/src/main/scala/bus/simpleio.scala", "target_type": "class_definition", "cursor_line": 105, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val r_dmem_dat: DataChannel = new DataChannel // read operation\n"}
{"file": "KyogenRV/src/main/scala/core/ALU.scala", "target_type": "function_definition", "cursor_line": 15, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition"], "target": " def ALU_AND: UInt = 7.U(4.W)\n"}
{"file": "KyogenRV/src/main/scala/core/Instructions.scala", "target_type": "function_definition", "cursor_line": 84, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition"], "target": " def MRET: BitPat = BitPat(\"b00110000001000000000000001110011\")\n"}
{"file": "KyogenRV/src/main/scala/core/constant.scala", "target_type": "function_definition", "cursor_line": 40, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition"], "target": " def OP2_X: UInt = 0.U(2.W)\n"}
{"file": "KyogenRV/src/main/scala/core/control.scala", "target_type": "function_definition", "cursor_line": 16, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition"], "target": " implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)\n"}
{"file": "KyogenRV/src/main/scala/core/core.scala", "target_type": "function_definition", "cursor_line": 22, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " def risingEdge(x: Bool): Bool = x && !RegNext(x)\n"}
{"file": "KyogenRV/src/main/scala/core/csr.scala", "target_type": "block", "cursor_line": 283, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when(time.andR) { timeh := timeh + 1.U }\n"}
{"file": "KyogenRV/src/main/scala/mem/DMem.scala", "target_type": "block", "cursor_line": 65, "target_nlines": 1, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "field_expression", "call_expression", "block", "call_expression", "block"], "target": " when(byteenable(3)){ mem_3.write(addr_align, wdat_3) }\n"}
{"file": "KyogenRV/src/main/scala/mem/IMem.scala", "target_type": "block", "cursor_line": 66, "target_nlines": 1, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "field_expression", "call_expression", "block", "call_expression", "block"], "target": " when(byteenable(2)){ mem_2.write(addr_align, wdat_2) }\n"}
{"file": "KyogenRV/src/test/scala/core/CpuBusTester.scala", "target_type": "block", "cursor_line": 76, "target_nlines": 5, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "for_expression", "block"], "target": "/*\n if( (lp >= 20 && lp<=25) || lp == 65 || lp == 90){\n poke(signal = c.io.sw.w_waitrequest_sig, value = 1)\n }\n else{\n"}
{"file": "KyogenRV/src/test/scala/core/TestCoreAll.scala", "target_type": "block", "cursor_line": 183, "target_nlines": 3, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "infix_expression", "call_expression", "arguments", "assignment_expression", "lambda_expression", "block"], "target": "\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-sw.hex\", \"src/sw/rv32ui-p-sw_tester.log\")\n\t\t}) should be (true)\n"}
{"file": "Frenda/src/main/scala/frenda/FirrtlCompiler.scala", "target_type": "object_definition", "cursor_line": 9, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object FirrtlCompiler extends StageMain(new FrendaStage)\n"}
{"file": "Frenda/src/main/scala/frenda/FrendaException.scala", "target_type": "class_definition", "cursor_line": 8, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class FrendaException(msg: String) extends Exception(msg)\n"}
{"file": "Frenda/src/main/scala/frenda/stage/FrendaAnnotations.scala", "target_type": "if_expression", "cursor_line": 107, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "if_expression"], "target": " @inline def log(message: String): Unit = if (!silentMode) stream.println(message)\n"}
{"file": "Frenda/src/main/scala/frenda/stage/FrendaCli.scala", "target_type": "identifier", "cursor_line": 9, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "trait_definition", "template_body", "self_type", "identifier"], "target": " this: Shell =>\n"}
{"file": "Frenda/src/main/scala/frenda/stage/FrendaPhase.scala", "target_type": "class_definition", "cursor_line": 9, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class FrendaPhase extends PhaseManager(FrendaPhase.targets)\n"}
{"file": "Frenda/src/main/scala/frenda/stage/FrendaStage.scala", "target_type": "block", "cursor_line": 15, "target_nlines": 5, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block"], "target": " def run(annotations: AnnotationSeq): AnnotationSeq = {\n val result = new FrendaPhase().transform(annotations)\n FrendaOptions.fromAnnotations(result).executionContext.shutdown()\n result\n }\n"}
{"file": "Frenda/src/main/scala/frenda/stage/phases/AddCircuit.scala", "target_type": "function_definition", "cursor_line": 14, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " override def optionalPrerequisiteOf = Seq()\n"}
{"file": "Frenda/src/main/scala/frenda/stage/phases/CheckOptions.scala", "target_type": "function_definition", "cursor_line": 19, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " override def invalidates(a: Phase) = false\n"}
{"file": "Frenda/src/main/scala/frenda/stage/phases/IncrementalCompile.scala", "target_type": "function_definition", "cursor_line": 19, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " override def optionalPrerequisites = Seq()\n"}
{"file": "Frenda/src/main/scala/frenda/stage/phases/PreTransform.scala", "target_type": "function_definition", "cursor_line": 16, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " override def optionalPrerequisites = Seq()\n"}
{"file": "Frenda/src/main/scala/frenda/stage/phases/SplitCircuit.scala", "target_type": "function_definition", "cursor_line": 21, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " override def optionalPrerequisiteOf = Seq()\n"}
{"file": "Frenda/src/main/scala/frenda/stage/phases/WriteDotFFile.scala", "target_type": "function_definition", "cursor_line": 15, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " override def optionalPrerequisites = Seq()\n"}
{"file": "chisel-circt/project/Dependencies.scala", "target_type": "object_definition", "cursor_line": 3, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object Dependencies {\n lazy val scalaTest = \"org.scalatest\" %% \"scalatest\" % \"3.2.14\"\n private val chiselVersion = \"3.5.5\"\n lazy val chisel3 = \"edu.berkeley.cs\" %% \"chisel3\" % chiselVersion\n lazy val chiselCompilerPlugin = \"edu.berkeley.cs\" %% \"chisel3-plugin\" % chiselVersion\n"}
{"file": "chisel-circt/src/main/scala/circt/Implicits.scala", "target_type": "object_definition", "cursor_line": 14, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": " Some(b)\n else\n None\n }\n\n"}
{"file": "chisel-circt/src/main/scala/circt/stage/Annotations.scala", "target_type": "class_definition", "cursor_line": 37, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "trait_definition", "template_body", "class_definition"], "target": "case class PreserveAggregate(mode: PreserveAggregate.Type) extends NoTargetAnnotation with CIRCTOption\n"}
{"file": "chisel-circt/src/main/scala/circt/stage/CIRCTOptions.scala", "target_type": "class_definition", "cursor_line": 19, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val firtoolOptions: Seq[String] = Seq.empty) {\n\n"}
{"file": "chisel-circt/src/main/scala/circt/stage/CIRCTStage.scala", "target_type": "function_definition", "cursor_line": 43, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " override def run(annotations: AnnotationSeq): AnnotationSeq = phaseManager.transform(annotations)\n"}
{"file": "chisel-circt/src/main/scala/circt/stage/ChiselStage.scala", "target_type": "function_definition", "cursor_line": 24, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " override def invalidates(a: Phase) = false\n"}
{"file": "chisel-circt/src/main/scala/circt/stage/package.scala", "target_type": "object_definition", "cursor_line": 19, "target_nlines": 4, "node_depth": 3, "node_path": ["compilation_unit", "package_object", "template_body", "object_definition"], "target": " case a: CIRCTOption => a\n case a: FirrtlOption => a\n case a: FirrtlFileAnnotation => a\n }\n"}
{"file": "chisel-circt/src/main/scala/circt/stage/phases/AddFIRRTLInputFile.scala", "target_type": "function_definition", "cursor_line": 16, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " override def invalidates(a: Phase) = false\n"}
{"file": "chisel-circt/src/main/scala/circt/stage/phases/CIRCT.scala", "target_type": "block", "cursor_line": 184, "target_nlines": 1, "node_depth": 17, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "val_definition", "indented_block", "parenthesized_expression", "match_expression", "case_block", "case_clause", "throw_expression", "instance_expression", "arguments", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " s\"Invalid combination of circtOptions.target ${circtOptions.target} and split ${split}\"\n"}
{"file": "chisel-circt/src/main/scala/circt/stage/phases/Checks.scala", "target_type": "function_definition", "cursor_line": 17, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " override def invalidates(a: Phase) = false\n"}
{"file": "chisel-circt/src/test/scala/circtTests/stage/CIRCTStageSpec.scala", "target_type": "class_definition", "cursor_line": 46, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " outputFile.delete()\n\n val stage = new CIRCTStage\n\n stage.execute(\n"}
{"file": "chisel-circt/src/test/scala/circtTests/stage/ChiselStageSpec.scala", "target_type": "block", "cursor_line": 563, "target_nlines": 5, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block"], "target": " it(\"should emit FIRRTL dialect\") {\n\n ChiselStage.emitFIRRTLDialect(new ChiselStageSpec.Foo) should include(\" firrtl.module\")\n\n }\n"}
{"file": "Pythia-HDL/src/main/scala/pythia/IndexGen.scala", "target_type": "block", "cursor_line": 19, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "if_expression", "block"], "target": " val raw_val = if(iType == 1) {Cat(io.pc, io.offset)} else {io.delta_path}\n"}
{"file": "Pythia-HDL/src/main/scala/pythia/MasterModule.scala", "target_type": "block", "cursor_line": 96, "target_nlines": 1, "node_depth": 13, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "field_expression", "call_expression", "block", "call_expression", "field_expression", "call_expression", "call_expression", "field_expression", "call_expression", "block"], "target": " .elsewhen(state === s_query_read14) { vault0.io.rdcol0 := 12.U }\n"}
{"file": "Pythia-HDL/src/main/scala/pythia/MaxN.scala", "target_type": "block", "cursor_line": 31, "target_nlines": 4, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " io.maxId := io.ids(1)\n io.maxNum := io.nums(1)\n }.otherwise{\n io.maxId := io.ids(2)\n"}
{"file": "Pythia-HDL/src/main/scala/pythia/Plane.scala", "target_type": "class_definition", "cursor_line": 35, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " wrindex := (io.wrrow << 4) + io.wrcol\n\n when(io.we) {\n mem(wrindex) := io.wrdata\n // printf(\"[PLANE WRITE] row %d col %d index %d val %d\\n\", io.wrrow, io.wrcol, wrindex, io.wrdata)\n"}
{"file": "Pythia-HDL/src/main/scala/pythia/QVCompare.scala", "target_type": "class_definition", "cursor_line": 23, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "\n val qv0 = io.qv0_p0 + io.qv0_p1 + io.qv0_p2\n"}
{"file": "Pythia-HDL/src/main/scala/pythia/Valut.scala", "target_type": "class_definition", "cursor_line": 17, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val rdrow1 = Input(Vec(3, UInt(7.W)))\n val rdcol1 = Input(UInt(4.W))\n"}
{"file": "Pythia-HDL/src/test/scala/pythia/Launcher.scala", "target_type": "function_definition", "cursor_line": 42, "target_nlines": 3, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition"], "target": " def main(args: Array[String]): Unit = {\n PythiaRunner(\"pythia\", tests, args)\n }\n"}
{"file": "Pythia-HDL/src/test/scala/pythia/MasterModuleTests.scala", "target_type": "block", "cursor_line": 14, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block"], "target": " step(3)\n poke(c.io.sigUpdate, 0)\n // step(1)\n"}
{"file": "Pythia-HDL/src/test/scala/pythia/MaxNTests.scala", "target_type": "block", "cursor_line": 19, "target_nlines": 5, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " backends foreach {backend =>\n it should s\"correctly add randomly generated numbers and show carry in $backend\" in {\n Driver(() => new MaxN, backend)((c) => new MaxNTests(c)) should be (true)\n }\n }\n"}
{"file": "Pythia-HDL/src/test/scala/pythia/PlaneTests.scala", "target_type": "block", "cursor_line": 31, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "for_expression", "block"], "target": " PlaneWrite(row0, col0, data0)\n"}
{"file": "Pythia-HDL/src/test/scala/pythia/QVComapreTests.scala", "target_type": "if_expression", "cursor_line": 16, "target_nlines": 1, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "val_definition", "if_expression"], "target": " val max = if (qv0 >= qv1) {qv0} else {qv1}\n"}
{"file": "Pythia-HDL/src/test/scala/pythia/VaultTests.scala", "target_type": "block", "cursor_line": 19, "target_nlines": 2, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block"], "target": " expect(c.io.rddata0(1), data0)\n expect(c.io.rddata0(2), data0)\n"}
{"file": "Pythia-HDL/src/test/scala/utils/PythiaRunner.scala", "target_type": "block", "cursor_line": 68, "target_nlines": 1, "node_depth": 18, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition", "block", "for_expression", "block", "match_expression", "case_block", "case_clause", "try_expression", "catch_clause", "case_block", "case_clause", "infix_expression", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " errors += s\"Pythia module $testName: throwable ${t.getMessage}\"\n"}
{"file": "dma/chisel/src/main/scala/aha/dma/controller/Controller.scala", "target_type": "block", "cursor_line": 179, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "block"], "target": " val read_cmd_posted = withClockAndReset(ACLK, reset) { RegInit(false.B) }\n"}
{"file": "dma/chisel/src/main/scala/aha/dma/controller/DataMover.scala", "target_type": "class_definition", "cursor_line": 96, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " //\n peekQueue.ACLK := ACLK\n"}
{"file": "dma/chisel/src/main/scala/aha/dma/controller/Splitter.scala", "target_type": "block", "cursor_line": 72, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "block"], "target": " val state = withClockAndReset(ACLK, reset) { RegInit(sIDLE) }\n"}
{"file": "dma/chisel/src/main/scala/aha/dma/package.scala", "target_type": "class_definition", "cursor_line": 50, "target_nlines": 4, "node_depth": 3, "node_path": ["compilation_unit", "package_object", "template_body", "class_definition"], "target": " class TransBundle(AddrWidth: Int) extends Bundle {\n val NumBytes = UInt(32.W)\n val Address = UInt(AddrWidth.W)\n }\n"}
{"file": "dma/chisel/src/main/scala/aha/dma/reader/Reader.scala", "target_type": "block", "cursor_line": 64, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "block"], "target": " val state = withClockAndReset(ACLK, reset) { RegInit(sIDLE) }\n"}
{"file": "dma/chisel/src/main/scala/aha/dma/regfile/APBRegFile.scala", "target_type": "block", "cursor_line": 138, "target_nlines": 1, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "call_expression", "block"], "target": " is (4.U) { reg_data_out := reg_dst_addr }\n"}
{"file": "dma/chisel/src/main/scala/aha/dma/regfile/AXILiteRegFile.scala", "target_type": "block", "cursor_line": 161, "target_nlines": 5, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "for_expression", "block"], "target": " for (n <- 0 to 3) {\n when (RegIntf.WSTRB(n) === 1.U) {\n reg_src_addr_v(n) := RegIntf.WDATA(n*8+7, n*8)\n }\n }\n"}
{"file": "dma/chisel/src/main/scala/aha/dma/regfile/RegFile.scala", "target_type": "class_definition", "cursor_line": 15, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "case class RegFileConfig(AddrWidth: Int, DataWidth: Int, MagicID: Int)\n"}
{"file": "dma/chisel/src/main/scala/aha/dma/top/DMA.scala", "target_type": "class_definition", "cursor_line": 86, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " // Connections\n //\n\n controller.ACLK := ACLK\n controller.ARESETn := ARESETn\n"}
{"file": "dma/chisel/src/main/scala/aha/dma/top/Top.scala", "target_type": "class_definition", "cursor_line": 20, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " // Width of AXI Address Bus\n AddrWidth: Int = 32,\n // Width of AXI Data Bus\n"}
{"file": "dma/chisel/src/main/scala/aha/dma/util/APB.scala", "target_type": "class_definition", "cursor_line": 18, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val PSEL = Output(Bool())\n val PENABLE = Output(Bool())\n val PWRITE = Output(Bool())\n val PWDATA = Output(UInt(DataWidth.W))\n val PREADY = Input(Bool())\n"}
{"file": "dma/chisel/src/main/scala/aha/dma/util/AXI4.scala", "target_type": "class_definition", "cursor_line": 286, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val RESP = UInt(2.W)\n val LAST = Bool()\n"}
{"file": "dma/chisel/src/main/scala/aha/dma/util/PeekQueue.scala", "target_type": "block", "cursor_line": 53, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "block"], "target": " val rdptr = withClockAndReset(ACLK, reset) { RegInit(0.U(ADDR_WIDTH.W)) }\n"}
{"file": "dma/chisel/src/main/scala/aha/dma/writer/Writer.scala", "target_type": "block", "cursor_line": 75, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "block"], "target": " val aw_valid = withClockAndReset(ACLK, reset) { RegInit(false.B) }\n"}
{"file": "icenet/src/main/scala/Aligner.scala", "target_type": "block", "cursor_line": 104, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when (inDone) { sending := false.B }\n"}
{"file": "icenet/src/main/scala/Buffer.scala", "target_type": "block", "cursor_line": 213, "target_nlines": 1, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block"], "target": " when (inIdx === 0.U) { startHead := bufHead }\n"}
{"file": "icenet/src/main/scala/Checksum.scala", "target_type": "if_expression", "cursor_line": 163, "target_nlines": 1, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "arguments", "if_expression"], "target": " val keep = take.map(if (_) 0x3 else 0x0)\n"}
{"file": "icenet/src/main/scala/Configs.scala", "target_type": "class_definition", "cursor_line": 26, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class IceNetUnitTestConfig extends Config(\n new WithIceNetUnitTests ++ new BaseSubsystemConfig)\n"}
{"file": "icenet/src/main/scala/Consts.scala", "target_type": "function_definition", "cursor_line": 37, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition"], "target": " def NET_FULL_KEEP = ~0.U(NET_IF_BYTES.W)\n"}
{"file": "icenet/src/main/scala/DMA.scala", "target_type": "block", "cursor_line": 298, "target_nlines": 1, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "class_definition", "template_body", "call_expression", "block"], "target": " when (io.resp.fire) { state := s_idle }\n"}
{"file": "icenet/src/main/scala/Headers.scala", "target_type": "function_definition", "cursor_line": 12, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition"], "target": " def htonl(a: UInt) = reverse_bytes(a, 4)\n"}
{"file": "icenet/src/main/scala/Limiter.scala", "target_type": "block", "cursor_line": 73, "target_nlines": 1, "node_depth": 6, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition", "block", "if_expression", "block"], "target": " } else { in }\n"}
{"file": "icenet/src/main/scala/NIC.scala", "target_type": "if_expression", "cursor_line": 343, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "if_expression"], "target": " val pauseDropCheck = if (usePauser) Some(PauseDropCheck(_, _, _)) else None\n"}
{"file": "icenet/src/main/scala/NICTests.scala", "target_type": "block", "cursor_line": 287, "target_nlines": 1, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "class_definition", "template_body", "call_expression", "block"], "target": " when (sendCompDone) { completing := false.B }\n"}
{"file": "icenet/src/main/scala/Pauser.scala", "target_type": "block", "cursor_line": 149, "target_nlines": 1, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block"], "target": " when (arb.io.in(1).bits.last) { outInProgress := false.B }\n"}
{"file": "icenet/src/main/scala/Stream.scala", "target_type": "function_definition", "cursor_line": 18, "target_nlines": 4, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " def flipConnect(other: StreamIO) {\n in <> other.out\n other.in <> out\n }\n"}
{"file": "icenet/src/main/scala/TCAM.scala", "target_type": "block", "cursor_line": 58, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " maskArr(wordaddr) := acq.bits.data(outer.dataBits - 1, 0)\n } .otherwise {\n dataArr(wordaddr) := acq.bits.data(outer.dataBits - 1, 0)\n"}
{"file": "icenet/src/main/scala/Tap.scala", "target_type": "block", "cursor_line": 129, "target_nlines": 1, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "block", "lambda_expression", "parenthesized_expression", "infix_expression", "call_expression", "block"], "target": " pl => (Seq.fill(pl.size-1) { false } ++ Seq(true))\n"}
{"file": "icenet/src/main/scala/TestUtils.scala", "target_type": "block", "cursor_line": 76, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when (checkDone) { finished := true.B }\n"}
{"file": "icenet/src/main/scala/TraceROM.scala", "target_type": "class_definition", "cursor_line": 8, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val io = IO(new Bundle {\n val clock = Input(Clock())\n val reset = Input(Bool())\n val stream = Decoupled(new StreamChannel(NET_IF_WIDTH))\n val macAddr = Output(UInt(48.W))\n"}
{"file": "rjrouter/src/main/scala/gcd/DecoupledGCD.scala", "target_type": "block", "cursor_line": 55, "target_nlines": 5, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "field_expression", "call_expression", "block", "call_expression", "block"], "target": " output.bits.value2 := yInitial\n resultValid := true.B\n\n when(output.ready && resultValid) {\n busy := false.B\n"}
{"file": "rjrouter/src/main/scala/gcd/GCD.scala", "target_type": "block", "cursor_line": 24, "target_nlines": 1, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "field_expression", "call_expression", "block"], "target": " when(x > y) { x := x - y }\n"}
{"file": "rjrouter/src/main/scala/router/Bundles.scala", "target_type": "block", "cursor_line": 27, "target_nlines": 1, "node_depth": 13, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "call_expression", "field_expression", "call_expression", "arguments", "lambda_expression", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " .map(b => p\"${Hexadecimal(b)}\")\n"}
{"file": "rjrouter/src/main/scala/router/pipeline/ArpPipeline.scala", "target_type": "block", "cursor_line": 24, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " io.arpModify.get.ipv4 := arpIn.srcIpv4\n io.arpModify.get.mac := arpIn.srcMac\n\n"}
{"file": "rjrouter/src/main/scala/router/pipeline/Ipv4Check.scala", "target_type": "block", "cursor_line": 16, "target_nlines": 3, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "call_expression", "block"], "target": " when(!ipv4In.isValid) {\n dropRest()\n }\n"}
{"file": "rjrouter/src/main/scala/router/pipeline/Ipv4Forward.scala", "target_type": "block", "cursor_line": 26, "target_nlines": 2, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block"], "target": " val outIface = WireInit(3.U)\n val nextHop = WireInit(Ipv4Addr(\"10.0.3.2\"))\n"}
{"file": "rjrouter/src/main/scala/router/pipeline/Ipv4SetMac.scala", "target_type": "block", "cursor_line": 26, "target_nlines": 5, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " val iface = io.config.iface(nextHop.iface)\n when(dstMac.valid) {\n // update ethernet header\n val ethOut = WireInit(ethIn)\n ethOut.ethSrc := iface.mac\n"}
{"file": "rjrouter/src/main/scala/router/pipeline/L2Filter.scala", "target_type": "block", "cursor_line": 11, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " val dstIsMe = ethIn.ethDst === io.config.iface(io.in.bits.id).mac\n"}
{"file": "rjrouter/src/main/scala/router/pipeline/Loopback.scala", "target_type": "class_definition", "cursor_line": 11, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val ethIn = io.in.bits.data.asTypeOf(new EtherHeader())\n // swap src and dst MAC\n val ethOut = WireDefault(ethIn)\n ethOut.ethSrc := ethIn.ethDst\n ethOut.ethDst := ethIn.ethSrc\n"}
{"file": "rjrouter/src/main/scala/router/pipeline/Pipeline.scala", "target_type": "block", "cursor_line": 29, "target_nlines": 1, "node_depth": 11, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "assignment_expression", "if_expression", "if_expression", "block", "infix_expression", "call_expression", "block"], "target": " Seq.fill(wb - bytes.length) { 0.toByte } ++ bytes\n"}
{"file": "rjrouter/src/main/scala/router/pipeline/Router.scala", "target_type": "function_definition", "cursor_line": 21, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " in <> m.io.in\n"}
{"file": "rjrouter/src/main/scala/router/table/ArpCache.scala", "target_type": "block", "cursor_line": 79, "target_nlines": 5, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when(io.modify.op === ArpOp.Remove) {\n when(table(idx).bits.ipv4 === io.modify.ipv4) {\n table(idx).valid := false.B\n }\n }\n"}
{"file": "rjrouter/src/test/scala/gcd/GCDMain.scala", "target_type": "block", "cursor_line": 27, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "object_definition", "template_body", "call_expression", "block"], "target": " iotesters.Driver.execute(args, () => new GCD) {\n c => new GCDUnitTester(c)\n }\n"}
{"file": "rjrouter/src/test/scala/gcd/GCDUnitTest.scala", "target_type": "block", "cursor_line": 65, "target_nlines": 3, "node_depth": 5, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "if_expression", "block"], "target": " private val backendNames = if(firrtl.FileUtils.isCommandAvailable(Seq(\"verilator\", \"--version\"))) {\n Array(\"firrtl\", \"verilator\")\n }\n"}
{"file": "rjrouter/src/test/scala/gcd/GcdTesters2.scala", "target_type": "block", "cursor_line": 27, "target_nlines": 2, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " dut.input.setSourceClock(dut.clock)\n dut.output.initSink()\n"}
{"file": "rjrouter/src/test/scala/router/pipeline/Pipeline.scala", "target_type": "block", "cursor_line": 148, "target_nlines": 1, "node_depth": 9, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "try_expression", "catch_clause", "case_block", "case_clause", "block"], "target": " case e: EOFException => {}\n"}
{"file": "rjrouter/src/test/scala/router/table/ArpCache.scala", "target_type": "block", "cursor_line": 52, "target_nlines": 2, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block"], "target": " check(Ipv4Addr(\"192.168.0.0\"), Some(MacAddr(\"00:00:00:00:00:00\")))\n check(Ipv4Addr(\"192.168.1.1\"), None)\n"}
{"file": "FPGA-Application-Development-and-Simulation/chisel/src/main/scala/gen_verilog.scala", "target_type": "if_expression", "cursor_line": 110, "target_nlines": 1, "node_depth": 6, "node_path": ["compilation_unit", "object_definition", "template_body", "val_definition", "call_expression", "arguments", "if_expression"], "target": " if (genSplitFiles) \"--split-verilog\" else \"\"\n"}
{"file": "FPGA-Application-Development-and-Simulation/chisel/src/main/scala/loywong/accumulator.scala", "target_type": "block", "cursor_line": 52, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when(io.en) {\n accu := nextWrap\n }\n"}
{"file": "FPGA-Application-Development-and-Simulation/chisel/src/main/scala/loywong/axi4lite_to_localmm.scala", "target_type": "block", "cursor_line": 141, "target_nlines": 1, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " s\"_${1 << regAddrWidth}x${regDataBytes * 8}\"\n"}
{"file": "FPGA-Application-Development-and-Simulation/chisel/src/main/scala/loywong/cordic.scala", "target_type": "block", "cursor_line": 334, "target_nlines": 1, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "match_expression", "case_block", "case_clause", "block"], "target": " case _ => { }\n"}
{"file": "FPGA-Application-Development-and-Simulation/chisel/src/main/scala/loywong/counter.scala", "target_type": "object_definition", "cursor_line": 75, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": " when(en) {\n when(wrap) {\n cnt := 0.U(width.W)\n"}
{"file": "FPGA-Application-Development-and-Simulation/chisel/src/main/scala/loywong/cross_clock_domain.scala", "target_type": "block", "cursor_line": 520, "target_nlines": 1, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "infix_expression", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " override def desiredName: String = super.desiredName + s\"_${(1<<addrWidth)}_x_${gen.typeName}\"\n"}
{"file": "FPGA-Application-Development-and-Simulation/chisel/src/main/scala/loywong/decoder.scala", "target_type": "function_definition", "cursor_line": 30, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition"], "target": " def apply(in:UInt) : UInt = { 1.U << in }\n"}
{"file": "FPGA-Application-Development-and-Simulation/chisel/src/main/scala/loywong/delay_chain.scala", "target_type": "class_definition", "cursor_line": 34, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "package_clause", "template_body", "class_definition"], "target": " val io = IO(new Bundle {\n"}
{"file": "FPGA-Application-Development-and-Simulation/chisel/src/main/scala/loywong/encoder.scala", "target_type": "class_definition", "cursor_line": 39, "target_nlines": 4, "node_depth": 3, "node_path": ["compilation_unit", "package_clause", "template_body", "class_definition"], "target": " })\n // use chisel3.PriorityEncoder !\n io.out := PriorityEncoder(io.in)\n }\n"}
{"file": "FPGA-Application-Development-and-Simulation/chisel/src/main/scala/loywong/memory.scala", "target_type": "function_definition", "cursor_line": 1139, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " override def desiredName = s\"${super.desiredName}_${nWords}_x_${gen.typeName}\"\n"}
{"file": "FPGA-Application-Development-and-Simulation/chisel/src/main/scala/loywong/scfifo.scala", "target_type": "block", "cursor_line": 146, "target_nlines": 1, "node_depth": 7, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " override def desiredName = s\"${super.desiredName}_${gen.typeName}\"\n"}
{"file": "FPGA-Application-Development-and-Simulation/chisel/src/main/scala/loywong/shift_reg.scala", "target_type": "function_definition", "cursor_line": 61, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " def qout: UInt = regs\n"}
{"file": "FPGA-Application-Development-and-Simulation/chisel/src/main/scala/loywong/str_common.scala", "target_type": "block", "cursor_line": 1022, "target_nlines": 1, "node_depth": 12, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "for_expression", "block", "call_expression", "block", "match_expression", "case_block", "case_clause", "block"], "target": " case _ => {}\n"}
{"file": "FPGA-Application-Development-and-Simulation/chisel/src/main/scala/loywong/str_pipe_control.scala", "target_type": "block", "cursor_line": 110, "target_nlines": 1, "node_depth": 7, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " override def desiredName = s\"${super.desiredName}_${genUS.typeName}_to_${genDS.typeName}\"\n"}
{"file": "FPGA-Application-Development-and-Simulation/chisel/src/main/scala/loywong/util.scala", "target_type": "function_definition", "cursor_line": 1389, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "object_definition", "template_body", "class_definition", "template_body", "function_definition"], "target": " final def <<<(n: UInt): FixPoint = shiftLeft(n)\n"}
{"file": "FPGA-Application-Development-and-Simulation/chisel/src/main/scala/temp.scala", "target_type": "block", "cursor_line": 22, "target_nlines": 1, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "ERROR", "val_definition", "call_expression", "block"], "target": " val b = IO( Input(Bool())).suggestName{\"bbb\"}\n"}
{"file": "FPGA-Application-Development-and-Simulation/chisel/src/test/scala/loywongtest/axi4lite_test_common.scala", "target_type": "function_definition", "cursor_line": 62, "target_nlines": 3, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " axi4l.b.ready.poke(true)\n val awt = fork {\n while (!axi4l.aw.ready.peekBoolean()) {\n"}
{"file": "FPGA-Application-Development-and-Simulation/chisel/src/test/scala/loywongtest/str_test_common.scala", "target_type": "function_definition", "cursor_line": 203, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " def totalClocks: Long = clksArray.last + 1\n"}
{"file": "FPGA-Application-Development-and-Simulation/chisel/src/test/scala/test_accumulator.scala", "target_type": "if_expression", "cursor_line": 56, "target_nlines": 5, "node_depth": 11, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block", "lambda_expression", "block", "for_expression", "block", "if_expression"], "target": " if(y + step >= modu)\n dut.io.wrapUp.expect(true)\n else\n dut.io.wrapUp.expect(false)\n dut.io.wrapDown.expect(false)\n"}
{"file": "FPGA-Application-Development-and-Simulation/chisel/src/test/scala/test_str_cordic_1.scala", "target_type": "block", "cursor_line": 332, "target_nlines": 1, "node_depth": 18, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block", "lambda_expression", "block", "if_expression", "block", "for_expression", "block", "call_expression", "arguments", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " print(f\"beat_${i}%04d: \")\n"}
{"file": "FPGA-Application-Development-and-Simulation/chisel/src/test/scala/test_str_cordic_2.scala", "target_type": "block", "cursor_line": 195, "target_nlines": 1, "node_depth": 18, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block", "lambda_expression", "block", "if_expression", "block", "for_expression", "block", "call_expression", "arguments", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " print(f\"beat_${i}%04d: \")\n"}
{"file": "riscv-self/src/main/scala/ALU.scala", "target_type": "class_definition", "cursor_line": 9, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val A = Input(UInt(32.W))\n"}
{"file": "riscv-self/src/main/scala/BranchCond.scala", "target_type": "class_definition", "cursor_line": 14, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class BrJumpIO extends Bundle {\n val disp = Input(UInt(13.W))\n val PC = Input(UInt(32.W))\n}\n"}
{"file": "riscv-self/src/main/scala/Compile.scala", "target_type": "block", "cursor_line": 23, "target_nlines": 1, "node_depth": 13, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition", "block", "val_definition", "instance_expression", "arguments", "instance_expression", "arguments", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " val verilog = new FileWriter(new File(dir, s\"${chirrtl.main}.v\"))\n"}
{"file": "riscv-self/src/main/scala/Constants.scala", "target_type": "object_definition", "cursor_line": 15, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": " val ALU_SRA = 13.U(4.W)\n val ALU_OR = 6.U(4.W)\n"}
{"file": "riscv-self/src/main/scala/Control.scala", "target_type": "class_definition", "cursor_line": 37, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val inst = Input(UInt(32.W))\n val mode = Output(UInt(4.W))\n val sel = Output(UInt(3.W))\n val imm = Output(UInt(3.W))\n"}
{"file": "riscv-self/src/main/scala/Datapath.scala", "target_type": "block", "cursor_line": 121, "target_nlines": 1, "node_depth": 5, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "infix_expression", "block"], "target": " val rdReg = mods.indices map { i => RegInit(false.B) }\n"}
{"file": "riscv-self/src/main/scala/Execute.scala", "target_type": "class_definition", "cursor_line": 20, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val reg = Flipped(new RegFileReaderIO)\n"}
{"file": "riscv-self/src/main/scala/ImmGen.scala", "target_type": "class_definition", "cursor_line": 15, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val io = IO(new ImmGenIO)\n"}
{"file": "riscv-self/src/main/scala/Interface.scala", "target_type": "class_definition", "cursor_line": 7, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val addr = Input(UInt(32.W))\n"}
{"file": "riscv-self/src/main/scala/Jump.scala", "target_type": "function_definition", "cursor_line": 15, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " def s(i: Int): UInt = Utility.extendSign(io.imm(i, 0), 32)\n"}
{"file": "riscv-self/src/main/scala/LoadStore.scala", "target_type": "function_definition", "cursor_line": 35, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " def UNS(i: Int):UInt = Mux(~io.mode(2), Utility.extendSign(io.mem.data(i-1, 0), 32), io.mem.data(i-1, 0))\n"}
{"file": "riscv-self/src/main/scala/RegFile.scala", "target_type": "block", "cursor_line": 28, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when(io.writer.wen & io.writer.waddr.orR) {\n regs(io.writer.waddr) := io.writer.wdata\n }\n"}
{"file": "riscv-self/src/main/scala/SystemOperation.scala", "target_type": "class_definition", "cursor_line": 15, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val inst = Input(UInt(32.W))\n })\n // Execute no Operation\n}\n"}
{"file": "riscv-self/src/main/scala/Utils.scala", "target_type": "class_definition", "cursor_line": 16, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val in = Input(Bool())\n val re = Input(Bool())\n val out = Output(Bool())\n })\n"}
{"file": "riscv-self/src/test/scala/ALUTests.scala", "target_type": "block", "cursor_line": 33, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when(done) { stop(); stop() }\n"}
{"file": "riscv-self/src/test/scala/BranchTests.scala", "target_type": "block", "cursor_line": 62, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when(done) { stop(); stop() }\n"}
{"file": "riscv-self/src/test/scala/Constants.scala", "target_type": "object_definition", "cursor_line": 7, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object Constants {\n val ALU = Map(\n \"ADD\" -> 0L,\n \"SUB\" -> 8L,\n \"SLL\" -> 1L,\n"}
{"file": "riscv-self/src/test/scala/ControlTests.scala", "target_type": "block", "cursor_line": 23, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when(done) { stop(); stop() }\n"}
{"file": "riscv-self/src/test/scala/DatapathTests.scala", "target_type": "block", "cursor_line": 203, "target_nlines": 1, "node_depth": 12, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "lambda_expression", "indented_block", "infix_expression", "infix_expression", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " \"DataPath\" should s\"pass ${test.name}\" in {\n"}
{"file": "riscv-self/src/test/scala/ExecuteTests.scala", "target_type": "block", "cursor_line": 51, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when(done) { stop(); stop() }\n"}
{"file": "riscv-self/src/test/scala/ImmGenTests.scala", "target_type": "block", "cursor_line": 34, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when(done) { stop(); stop() }\n"}
{"file": "riscv-self/src/test/scala/JumpTests.scala", "target_type": "block", "cursor_line": 97, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when(done) { stop(); stop() }\n"}
{"file": "riscv-self/src/test/scala/LoadStoreTests.scala", "target_type": "block", "cursor_line": 34, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when(done) { printf(\"\\n\"); stop(); stop() }\n"}
{"file": "riscv-self/src/test/scala/TestUtils.scala", "target_type": "if_expression", "cursor_line": 134, "target_nlines": 1, "node_depth": 8, "node_path": ["compilation_unit", "trait_definition", "template_body", "function_definition", "block", "function_definition", "block", "val_definition", "if_expression"], "target": " val low = if (lo == -1) {hi} else {lo}\n"}
{"file": "Bossa/generators/chipyard/src/main/scala/ChipTop.scala", "target_type": "object_definition", "cursor_line": 16, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) => new DigitalTop()(p))\n"}
{"file": "Bossa/generators/chipyard/src/main/scala/Clocks.scala", "target_type": "if_expression", "cursor_line": 59, "target_nlines": 1, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "extends_clause", "arguments", "lambda_expression", "case_block", "case_clause", "call_expression", "arguments", "lambda_expression", "if_expression"], "target": " Seq((cName: String) => if (cName.contains(name)) Some(fMHz) else None)\n"}
{"file": "Bossa/generators/chipyard/src/main/scala/ConfigFragments.scala", "target_type": "block", "cursor_line": 35, "target_nlines": 1, "node_depth": 15, "node_path": ["compilation_unit", "class_definition", "extends_clause", "arguments", "lambda_expression", "case_block", "case_clause", "call_expression", "arguments", "call_expression", "arguments", "assignment_expression", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " case BootROMLocated(x) => up(BootROMLocated(x), site).map(_.copy(contentFileName = s\"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img\"))\n"}
{"file": "Bossa/generators/chipyard/src/main/scala/CustomBusTopologies.scala", "target_type": "if_expression", "cursor_line": 28, "target_nlines": 4, "node_depth": 5, "node_path": ["compilation_unit", "class_definition", "extends_clause", "arguments", "assignment_expression", "if_expression"], "target": " (SBUS, L2, TLBusWrapperConnection(xType = NoCrossing, driveClockFromMaster = Some(true), nodeBinding = BIND_STAR)()),\n (L2, MBUS, TLBusWrapperConnection.crossTo(\n xType = sbusToMbusXType,\n driveClockFromMaster = None,\n"}
{"file": "Bossa/generators/chipyard/src/main/scala/DigitalTop.scala", "target_type": "class_definition", "cursor_line": 39, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " with sifive.blocks.devices.spi.HasPeripherySPIModuleImp\n with freechips.rocketchip.util.DontTouch\n"}
{"file": "Bossa/generators/chipyard/src/main/scala/Generator.scala", "target_type": "object_definition", "cursor_line": 6, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object Generator extends StageMain(new ChipyardStage)\n"}
{"file": "Bossa/generators/chipyard/src/main/scala/HarnessBinders.scala", "target_type": "block", "cursor_line": 215, "target_nlines": 1, "node_depth": 9, "node_path": ["compilation_unit", "class_definition", "extends_clause", "arguments", "block", "lambda_expression", "block", "call_expression", "arguments", "block"], "target": " ports.foreach({ p => p := DontCare; p.bits.tieoff() })\n"}
{"file": "Bossa/generators/chipyard/src/main/scala/IOBinders.scala", "target_type": "block", "cursor_line": 282, "target_nlines": 1, "node_depth": 20, "node_path": ["compilation_unit", "class_definition", "extends_clause", "arguments", "block", "lambda_expression", "block", "call_expression", "block", "val_definition", "call_expression", "arguments", "case_block", "case_clause", "val_definition", "call_expression", "arguments", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " val p = IO(new ClockedAndResetIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s\"axi4_mem_${i}\")\n"}
{"file": "Bossa/generators/chipyard/src/main/scala/Subsystem.scala", "target_type": "block", "cursor_line": 74, "target_nlines": 1, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "lambda_expression", "indented_block", "call_expression", "block"], "target": " tlBusWrapperLocationMap.lift(loc).foreach { _.clockGroupNode := asyncClockGroupsNode }\n"}
{"file": "Bossa/generators/chipyard/src/main/scala/System.scala", "target_type": "block", "cursor_line": 33, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "block", "val_definition", "call_expression", "block"], "target": " val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) }\n"}
{"file": "Bossa/generators/chipyard/src/main/scala/TestHarness.scala", "target_type": "object_definition", "cursor_line": 19, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "case object BuildTop extends Field[Parameters => LazyModule]((p: Parameters) => new ChipTop()(p))\n"}
{"file": "Bossa/generators/chipyard/src/main/scala/TestSuites.scala", "target_type": "block", "cursor_line": 60, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "block", "function_definition", "block"], "target": " def addSuite(s: RocketTestSuite) { suites += (s.makeTargetName -> s) }\n"}
{"file": "Bossa/generators/chipyard/src/main/scala/clocking/ClockDividerN.scala", "target_type": "block", "cursor_line": 18, "target_nlines": 5, "node_depth": 4, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition", "block"], "target": " def apply(clockIn: Clock, div: Int): Clock = {\n val clockDivider = Module(new ClockDividerN(div))\n clockDivider.io.clk_in := clockIn\n clockDivider.io.clk_out\n }\n"}
{"file": "Bossa/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala", "target_type": "block", "cursor_line": 36, "target_nlines": 1, "node_depth": 29, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition", "indented_block", "field_expression", "call_expression", "arguments", "instance_expression", "arguments", "assignment_expression", "block", "lambda_expression", "call_expression", "arguments", "assignment_expression", "call_expression", "case_block", "case_clause", "call_expression", "arguments", "match_expression", "case_block", "case_clause", "call_expression", "arguments", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " case None => Some(s\"${s.name}_${idx}\")\n"}
{"file": "Bossa/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala", "target_type": "block", "cursor_line": 84, "target_nlines": 1, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "case_block", "case_clause", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " s\" Output clock ${sink.name.get}, requested: ${requested} MHz, actual: ${actual} MHz (division of ${division})\"\n"}
{"file": "Bossa/generators/chipyard/src/main/scala/config/AbstractConfig.scala", "target_type": "class_definition", "cursor_line": 16, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " new chipyard.harness.WithBlackBoxSimMem ++ // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled\n new chipyard.harness.WithSimSerial ++ // add external serial-adapter and RAM\n new chipyard.harness.WithSimDebug ++ // add SimJTAG or SimDTM adapters if debug module is enabled\n new chipyard.harness.WithGPIOTiedOff ++ // tie-off chiptop GPIOs, if GPIOs are present\n"}
{"file": "Bossa/generators/chipyard/src/main/scala/config/BoomConfigs.scala", "target_type": "class_definition", "cursor_line": 9, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class SmallBoomConfig extends Config(\n new boom.common.WithNSmallBooms(1) ++ // small boom config\n new chipyard.config.AbstractConfig)\n"}
{"file": "Bossa/generators/chipyard/src/main/scala/config/RocketConfigs.scala", "target_type": "class_definition", "cursor_line": 19, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$\n new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory\n new freechips.rocketchip.subsystem.With1TinyCore ++ // single tiny rocket-core\n new chipyard.config.AbstractConfig)\n"}
{"file": "Bossa/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala", "target_type": "block", "cursor_line": 19, "target_nlines": 1, "node_depth": 22, "node_path": ["compilation_unit", "object_definition", "template_body", "val_definition", "call_expression", "arguments", "instance_expression", "arguments", "assignment_expression", "lambda_expression", "block", "call_expression", "arguments", "instance_expression", "arguments", "infix_expression", "block", "lambda_expression", "if_expression", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " Seq(new ConfigsAnnotation(configs map { config => if (config contains \".\") s\"${config}\" else s\"${packageName}.${config}\" } ))\n"}
{"file": "Bossa/generators/chipyard/src/main/scala/stage/ChipyardCli.scala", "target_type": "identifier", "cursor_line": 8, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "trait_definition", "template_body", "self_type", "identifier"], "target": "trait ChipyardCli { this: Shell =>\n"}
{"file": "Bossa/generators/chipyard/src/main/scala/stage/ChipyardStage.scala", "target_type": "class_definition", "cursor_line": 33, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " Dependency[chipyard.stage.phases.GenerateTestSuiteMakefrags],\n Dependency[freechips.rocketchip.stage.phases.GenerateArtefacts],\n"}
{"file": "Bossa/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala", "target_type": "if_expression", "cursor_line": 39, "target_nlines": 5, "node_depth": 5, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "if_expression"], "target": " if (p.lift(XLen).nonEmpty)\n // If a custom test suite is set up, use the custom test suite\n annotations += CustomMakefragSnippet(p(TestSuitesKey).apply(tileParams, suiteHelper, p))\n\n RocketTestSuiteAnnotation(suiteHelper.suites.values.toSeq) +: annotations\n"}
{"file": "Bossa/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala", "target_type": "class_definition", "cursor_line": 21, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "case class CustomMakefragSnippet(val toMakefrag: String) extends NoTargetAnnotation with MakefragSnippet with Unserializable\n"}
{"file": "Bossa/generators/chipyard/src/main/scala/unittest/TestHarness.scala", "target_type": "class_definition", "cursor_line": 6, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class TestHarness(implicit val p: Parameters) extends Module {\n val io = IO(new Bundle { val success = Output(Bool()) })\n io.success := Module(new UnitTestSuite).io.finished\n}\n"}
{"file": "Bossa/generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala", "target_type": "class_definition", "cursor_line": 6, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class UnitTestSuite(implicit p: Parameters) extends freechips.rocketchip.unittest.UnitTestSuite {\n ElaborationArtefacts.add(\"plusArgs\", PlusArgArtefacts.serialize_cHeader)\n}\n"}
{"file": "Bossa/generators/chipyard/src/test/scala/clocking/SimplePllConfigurationSpec.scala", "target_type": "block", "cursor_line": 17, "target_nlines": 1, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "infix_expression", "infix_expression", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " it should s\"select a reference of ${expected} MHz for ${freqStr} MHz\" in { \n"}
{"file": "riscv-mini/src/main/scala/junctions/nasti.scala", "target_type": "function_definition", "cursor_line": 32, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition"], "target": " def RespOkay = 0.U(RespBits.W)\n"}
{"file": "riscv-mini/src/main/scala/mini/Alu.scala", "target_type": "class_definition", "cursor_line": 40, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val io = IO(new AluIO(width))\n\n"}
{"file": "riscv-mini/src/main/scala/mini/BrCond.scala", "target_type": "class_definition", "cursor_line": 43, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val lt = Mux(isSameSign, diff(xlen - 1), io.rs1(xlen - 1))\n val ltu = Mux(isSameSign, diff(xlen - 1), io.rs2(xlen - 1))\n val ge = !lt\n"}
{"file": "riscv-mini/src/main/scala/mini/CSR.scala", "target_type": "block", "cursor_line": 319, "target_nlines": 1, "node_depth": 14, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "call_expression", "call_expression", "field_expression", "call_expression", "call_expression", "field_expression", "call_expression", "block"], "target": " .elsewhen(csr_addr === CSR.cyclehw) { cycleh := wdata }\n"}
{"file": "riscv-mini/src/main/scala/mini/Cache.scala", "target_type": "class_definition", "cursor_line": 30, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "case class CacheConfig(nWays: Int, nSets: Int, blockBytes: Int)\n"}
{"file": "riscv-mini/src/main/scala/mini/Config.scala", "target_type": "class_definition", "cursor_line": 7, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "case class Config(core: CoreConfig, cache: CacheConfig, nasti: NastiBundleParameters)\n"}
{"file": "riscv-mini/src/main/scala/mini/Control.scala", "target_type": "class_definition", "cursor_line": 135, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val alu_op = Output(UInt(4.W))\n"}
{"file": "riscv-mini/src/main/scala/mini/Core.scala", "target_type": "class_definition", "cursor_line": 33, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " dpath.io.ctrl <> ctrl.io\n}\n"}
{"file": "riscv-mini/src/main/scala/mini/Datapath.scala", "target_type": "class_definition", "cursor_line": 130, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " alu.io.B := Mux(io.ctrl.B_sel === B_RS2, rs2, immGen.io.out)\n"}
{"file": "riscv-mini/src/main/scala/mini/ImmGen.scala", "target_type": "class_definition", "cursor_line": 25, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val Uimm = Cat(io.inst(31, 12), 0.U(12.W)).asSInt\n val Jimm = Cat(io.inst(31), io.inst(19, 12), io.inst(20), io.inst(30, 25), io.inst(24, 21), 0.U(1.W)).asSInt\n val Zimm = io.inst(19, 15).zext\n\n"}
{"file": "riscv-mini/src/main/scala/mini/Instructions.scala", "target_type": "function_definition", "cursor_line": 51, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition"], "target": " def JAL = BitPat(\"b?????????????????????????1101111\")\n"}
{"file": "riscv-mini/src/main/scala/mini/Main.scala", "target_type": "object_definition", "cursor_line": 10, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": " coreParams = config.core,\n"}
{"file": "riscv-mini/src/main/scala/mini/RegFile.scala", "target_type": "class_definition", "cursor_line": 10, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val rdata1 = Output(UInt(xlen.W))\n val rdata2 = Output(UInt(xlen.W))\n val wen = Input(Bool())\n val waddr = Input(UInt(5.W))\n val wdata = Input(UInt(xlen.W))\n"}
{"file": "riscv-mini/src/main/scala/mini/Tile.scala", "target_type": "function_definition", "cursor_line": 102, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition"], "target": " def apply(config: Config): Tile = new Tile(config.core, config.nasti, config.cache)\n"}
{"file": "riscv-mini/src/test/scala/mini/ALUTests.scala", "target_type": "block", "cursor_line": 77, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when(done) { stop() }\n"}
{"file": "riscv-mini/src/test/scala/mini/BrCondTests.scala", "target_type": "block", "cursor_line": 62, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when(done) { stop() }\n"}
{"file": "riscv-mini/src/test/scala/mini/CSRTests.scala", "target_type": "block", "cursor_line": 256, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when(done) { stop() }\n"}
{"file": "riscv-mini/src/test/scala/mini/CacheTests.scala", "target_type": "function_definition", "cursor_line": 315, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " def rand_idx = rnd.nextInt(1 << slen).U(slen.W)\n"}
{"file": "riscv-mini/src/test/scala/mini/CoreTests.scala", "target_type": "if_expression", "cursor_line": 50, "target_nlines": 1, "node_depth": 7, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "if_expression"], "target": " if (trace) printf(\"MEM[%x] => %x\\n\", daddr * (xlen / 8).U, dmem(daddr))\n"}
{"file": "riscv-mini/src/test/scala/mini/DatapathTests.scala", "target_type": "block", "cursor_line": 49, "target_nlines": 1, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "call_expression", "block"], "target": " when(done) { state := sRun }\n"}
{"file": "riscv-mini/src/test/scala/mini/ImmGenTests.scala", "target_type": "block", "cursor_line": 47, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when(done) { stop() }\n"}
{"file": "riscv-mini/src/test/scala/mini/IntegrationTest.scala", "target_type": "object_definition", "cursor_line": 6, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object IntegrationTest extends Tag(\"IntegrationTest\")\n"}
{"file": "riscv-mini/src/test/scala/mini/Opcode.scala", "target_type": "object_definition", "cursor_line": 63, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": " val CSRRWI = BigInt(\"101\", 2).U(3.W)\n val CSRRSI = BigInt(\"110\", 2).U(3.W)\n"}
{"file": "riscv-mini/src/test/scala/mini/TestConfig.scala", "target_type": "block", "cursor_line": 48, "target_nlines": 1, "node_depth": 11, "node_path": ["compilation_unit", "object_definition", "template_body", "val_definition", "postfix_expression", "call_expression", "arguments", "lambda_expression", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " ).map(t => s\"rv32ui-p-${t}\") ++\n"}
{"file": "riscv-mini/src/test/scala/mini/TestUtils.scala", "target_type": "block", "cursor_line": 89, "target_nlines": 1, "node_depth": 9, "node_path": ["compilation_unit", "trait_definition", "template_body", "function_definition", "call_expression", "arguments", "call_expression", "arguments", "call_expression", "block"], "target": " def iimm(inst: UInt) = Cat(Cat(Seq.fill(21) { inst_31(inst) }), inst_30_25(inst), inst_24_21(inst), inst_20(inst))\n"}
{"file": "riscv-mini/src/test/scala/mini/TileTester.scala", "target_type": "if_expression", "cursor_line": 107, "target_nlines": 1, "node_depth": 9, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "call_expression", "block", "if_expression"], "target": " if (trace) printf(\"MEM[%x] <= %x\\n\", (addr + off) * (nasti.dataBits / 8).U, write)\n"}
{"file": "fpga_final_project/src/main/scala/bram/bram.scala", "target_type": "class_definition", "cursor_line": 63, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class big_bank1(w: Int, addr_w: Int) extends BlackBox{\n val io = IO(new TrueDualPort(w, addr_w))\n}\n"}
{"file": "fpga_final_project/src/main/scala/calc8x8/accumu.scala", "target_type": "block", "cursor_line": 62, "target_nlines": 4, "node_depth": 17, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "field_expression", "call_expression", "block", "call_expression", "field_expression", "call_expression", "block", "call_expression", "field_expression", "call_expression", "call_expression", "field_expression", "call_expression", "block"], "target": " when(counter.ccnt===counter.cend){\n valid_out_reg := 0.U\n counter.ccnt := counter.ccnt-1.U\n }.elsewhen(counter.ccnt===0.U){\n"}
{"file": "fpga_final_project/src/main/scala/calc8x8/calc6x6.scala", "target_type": "if_expression", "cursor_line": 328, "target_nlines": 1, "node_depth": 13, "node_path": ["compilation_unit", "class_definition", "template_body", "for_expression", "block", "for_expression", "block", "for_expression", "block", "if_expression", "if_expression", "block", "val_definition", "if_expression"], "target": " val real_i = if(i>=5) 9 else i+6\n"}
{"file": "fpga_final_project/src/main/scala/calc8x8/calc8x8.scala", "target_type": "if_expression", "cursor_line": 201, "target_nlines": 1, "node_depth": 9, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "infix_expression", "parenthesized_expression", "if_expression"], "target": " io.valid_out := (if(para_num==1) A(0).valid_out else Cat(0.U((para_num-1).W), A(0).valid_out))\n"}
{"file": "fpga_final_project/src/main/scala/calc8x8/core.scala", "target_type": "class_definition", "cursor_line": 11, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val result = Output(SInt(40.W))\n })\n \n val dsp48 = Module(new DSP48())\n"}
{"file": "fpga_final_project/src/main/scala/calc8x8/quant.scala", "target_type": "function_definition", "cursor_line": 25, "target_nlines": 3, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " def clamp_rs(x: SInt, a: UInt): Data = {\n val ret2 = ((1<<(w-1))-1).S(32.W)\n val ret3 = (-(1<<(w-1))).S(32.W)\n"}
{"file": "fpga_final_project/src/main/scala/control/switch.scala", "target_type": "block", "cursor_line": 40, "target_nlines": 1, "node_depth": 9, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "arguments", "call_expression", "arguments", "call_expression", "block"], "target": " val cache = RegInit(VecInit(Seq.fill(64){0.S(w.W)}))\n"}
{"file": "fpga_final_project/src/main/scala/some/maxpool.scala", "target_type": "block", "cursor_line": 43, "target_nlines": 3, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "for_expression", "block", "for_expression", "block"], "target": " b2 := Mux(w4(2)<w4(3), w4(3), w4(2))\n cache((ii+t*4)*4+jj) := Mux(a2<b2, b2, a2)\n }\n"}
{"file": "fpga_final_project/src/main/scala/some/sigmoid.scala", "target_type": "class_definition", "cursor_line": 89, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " 1058213120,\n 1069382976,\n"}
{"file": "fpga_final_project/src/main/scala/top/emit.scala", "target_type": "class_definition", "cursor_line": 72, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "\n val r64 = RegInit(0.U.asTypeOf(Vec(para_num, new AccumuRawData(w))))\n for(t <- 0 to para_num-1)\n"}
{"file": "fpga_final_project/src/main/scala/top/final_top.scala", "target_type": "if_expression", "cursor_line": 37, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "if_expression"], "target": " val rom_weight = if(StdPara.para_num==4) Module(new ROMWeight(StdPara.para_num)).io else Module(new ROMHalfWeight(StdPara.para_num)).io\n"}
{"file": "fpga_final_project/src/main/scala/top/show_on_board.scala", "target_type": "block", "cursor_line": 17, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when(fuck.complete_output){\n io.ok := fuck.checksum===26782.U\n }\n"}
{"file": "fpga_final_project/src/main/scala/top/top.scala", "target_type": "if_expression", "cursor_line": 36, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "if_expression"], "target": " val rom_bias = if(StdPara.para_num==4) Module(new ROMBias(StdPara.para_num)).io else Module(new ROMHalfBias(StdPara.para_num)).io\n"}
{"file": "fpga_final_project/src/main/scala/top/wrapper.scala", "target_type": "block", "cursor_line": 139, "target_nlines": 3, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "call_expression", "block"], "target": " when(out_64_counter.inc()){\n out_state := 5.U\n }\n"}
{"file": "fpga_final_project/src/main/scala/utils/para.scala", "target_type": "if_expression", "cursor_line": 296, "target_nlines": 1, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "val_definition", "lambda_expression", "parenthesized_expression", "if_expression"], "target": " val _min = (x: Int, y: Int) => (if(x>=y) y else x)\n"}
{"file": "fpga_final_project/src/main/scala/utils/utils.scala", "target_type": "function_definition", "cursor_line": 36, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition"], "target": " def apply(w: Int) = new ACounter(w.W)\n"}
{"file": "fpga_final_project/src/main/scala/wr/gen_addr.scala", "target_type": "function_definition", "cursor_line": 12, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition"], "target": " def apply(addr_w: Int, id_w: Int) = new Address(addr_w, id_w)\n"}
{"file": "fpga_final_project/src/main/scala/wr/read.scala", "target_type": "block", "cursor_line": 43, "target_nlines": 3, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "call_expression", "block"], "target": " is(ReadType.toMaxp){\n gen(state).go_maxp()\n }\n"}
{"file": "fpga_final_project/src/main/scala/wr/read_pack.scala", "target_type": "if_expression", "cursor_line": 69, "target_nlines": 1, "node_depth": 12, "node_path": ["compilation_unit", "class_definition", "template_body", "for_expression", "block", "if_expression", "block", "call_expression", "field_expression", "call_expression", "call_expression", "arguments", "if_expression"], "target": " when(if(x==6) cnt_ic.cend(x-1) else ~cnt_ic.cend(x)&&cnt_ic.cend(x-1)){\n"}
{"file": "fpga_final_project/src/main/scala/wr/read_weight.scala", "target_type": "class_definition", "cursor_line": 6, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class WeightReaderBundle(val w: Int, val addr_w: Int) extends TransBundle{\n val addr_end = Input(UInt(addr_w.W))\n val begin_addr = Input(UInt(addr_w.W))\n val addr = Output(UInt(addr_w.W))\n}\n"}
{"file": "fpga_final_project/src/main/scala/wr/write.scala", "target_type": "class_definition", "cursor_line": 76, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " for(j <- 0 to 5)\n"}
{"file": "fpga_final_project/src/main/scala/wr/wrjob.scala", "target_type": "if_expression", "cursor_line": 85, "target_nlines": 1, "node_depth": 9, "node_path": ["compilation_unit", "object_definition", "template_body", "function_definition", "block", "for_expression", "block", "infix_expression", "parenthesized_expression", "if_expression"], "target": " ret.small(i).cnt_invalid_end := (if(i==0) (loop_num*in_chan*h*loop_h).U else 0.U)\n"}
{"file": "fpga_final_project/src/test/scala/gcd/test_calc8x8.scala", "target_type": "class_definition", "cursor_line": 67, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " for(j <- 0 to 7){\n"}
{"file": "fpga_final_project/src/test/scala/gcd/test_conv.scala", "target_type": "if_expression", "cursor_line": 229, "target_nlines": 1, "node_depth": 9, "node_path": ["compilation_unit", "class_definition", "template_body", "for_expression", "for_expression", "block", "var_definition", "call_expression", "arguments", "if_expression"], "target": " var t2 = bank_id_small(j%2)(if(i%2==1) 0 else 2)\n"}
{"file": "fpga_final_project/src/test/scala/gcd/test_leakyrelu.scala", "target_type": "if_expression", "cursor_line": 24, "target_nlines": 1, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "block", "lambda_expression", "block", "if_expression"], "target": " if(A(i)(j)<0) A(i)(j)*6554 else A(i)(j)*32768\n"}
{"file": "fpga_final_project/src/test/scala/gcd/test_maxpool.scala", "target_type": "if_expression", "cursor_line": 267, "target_nlines": 1, "node_depth": 11, "node_path": ["compilation_unit", "class_definition", "template_body", "while_expression", "block", "if_expression", "block", "function_definition", "block", "assignment_expression", "parenthesized_expression", "if_expression"], "target": " vis(i)(j) = (if(i==1) (peek(dut.io.rd_addr1.addrs(j).addr)).toInt else (peek(dut.io.rd_addr2.addrs(j).addr)).toInt)\n"}
{"file": "fpga_final_project/src/test/scala/gcd/test_read_conv.scala", "target_type": "if_expression", "cursor_line": 111, "target_nlines": 1, "node_depth": 15, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "for_expression", "for_expression", "for_expression", "for_expression", "for_expression", "block", "assignment_expression", "tuple_expression", "call_expression", "arguments", "if_expression"], "target": " bank_id_small(if(i%2==0) 1 else 3),\n"}
{"file": "fpga_final_project/src/test/scala/gcd/test_write_conv.scala", "target_type": "if_expression", "cursor_line": 101, "target_nlines": 1, "node_depth": 13, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "for_expression", "for_expression", "for_expression", "block", "assignment_expression", "tuple_expression", "call_expression", "arguments", "if_expression"], "target": " bank_id_small(if(i%2==0) 0 else 2),\n"}
{"file": "magma-si/src/main/scala/components/AdderSwitch.scala", "target_type": "block", "cursor_line": 54, "target_nlines": 4, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "call_expression", "block"], "target": " is (\"b101\".U) {\n r_vn := Cat(reductionMux.io.o_data)\n r_vn_valid := 3.U\n }\n"}
{"file": "magma-si/src/main/scala/components/Benes.scala", "target_type": "if_expression", "cursor_line": 101, "target_nlines": 1, "node_depth": 13, "node_path": ["compilation_unit", "class_definition", "template_body", "for_expression", "block", "infix_expression", "call_expression", "arguments", "infix_expression", "infix_expression", "infix_expression", "infix_expression", "parenthesized_expression", "if_expression"], "target": " out_switch.io.in1 := w_internal(2 * (if(i % 2 == 0) i + 1 else i - 1) * (LEVELS - 1) + (2 * (LEVELS - 2)) + 1)\n"}
{"file": "magma-si/src/main/scala/components/Bitmap.scala", "target_type": "block", "cursor_line": 28, "target_nlines": 3, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "field_expression", "call_expression", "block"], "target": " when (io.mat2(i)(j) =/= 0.U){\n matReg2(i)(j) := 1.U\n }.otherwise{\n"}
{"file": "magma-si/src/main/scala/components/EdgeAdderSwitch.scala", "target_type": "block", "cursor_line": 33, "target_nlines": 5, "node_depth": 7, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "call_expression", "field_expression", "call_expression", "block"], "target": " when (rst) {\n r_adder := 0.U\n r_vn := 0.U\n r_vn_valid := 0.U\n } .elsewhen (r_valid) {\n"}
{"file": "magma-si/src/main/scala/components/FanCtrl.scala", "target_type": "block", "cursor_line": 726, "target_nlines": 4, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "for_expression", "block", "call_expression", "block", "call_expression", "block"], "target": " }.otherwise {\n r_reduction_add(30.U + x.U) := 0.U\n r_reduction_cmd( 30.U + x.U) := \"b000\".U\n }\n"}
{"file": "magma-si/src/main/scala/components/FanNetwork.scala", "target_type": "block", "cursor_line": 622, "target_nlines": 4, "node_depth": 5, "node_path": ["compilation_unit", "class_definition", "template_body", "ERROR", "call_expression", "block"], "target": " }.otherwise {\n r_lvl_output_ff(67) := r_lvl_output_ff(35)\n r_lvl_output_ff_valid(67) := r_lvl_output_ff_valid(35)\n }\n"}
{"file": "magma-si/src/main/scala/components/FlexDPE.scala", "target_type": "class_definition", "cursor_line": 12, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val i_data_bus = Input(Vec(NUM_PES, UInt(DATA_TYPE.W)))\n val i_data_bus2 = Input(Vec(NUM_PES, UInt(DATA_TYPE.W)))\n\n val o_valid = Output(Vec(NUM_PES, UInt(1.W)))\n"}
{"file": "magma-si/src/main/scala/components/MagmasiConfig.scala", "target_type": "class_definition", "cursor_line": 7, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val NUM_IN : Int = 4,\n val SEL_IN: Int = 2,\n"}
{"file": "magma-si/src/main/scala/components/MultSwitch.scala", "target_type": "block", "cursor_line": 37, "target_nlines": 3, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "field_expression", "call_expression", "block"], "target": " when (r_buffer_valid && io.i_valid) {\n o_validReg := true.B\n }.otherwise {\n"}
{"file": "magma-si/src/main/scala/components/ReductionMux.scala", "target_type": "block", "cursor_line": 31, "target_nlines": 4, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "field_expression", "call_expression", "block"], "target": " when ((w_sel_in_left).asUInt < 2.U) {\n \n io.o_data(0) := w_data_left(w_sel_in_left)\n }.otherwise {\n"}
{"file": "magma-si/src/main/scala/components/Regor.scala", "target_type": "block", "cursor_line": 37, "target_nlines": 3, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block"], "target": " }.otherwise{\n matReg1(i)(j) := bitmap.io.bitmap1(i)(j)\n }\n"}
{"file": "magma-si/src/main/scala/components/SimpleAdder.scala", "target_type": "class_definition", "cursor_line": 14, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " io.O := io.A + io.B\n"}
{"file": "magma-si/src/main/scala/components/SimpleMultiplier.scala", "target_type": "class_definition", "cursor_line": 14, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " io.O := io.A * io.B\n"}
{"file": "magma-si/src/main/scala/components/Switches.scala", "target_type": "class_definition", "cursor_line": 39, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val in1 = Input(UInt(width.W))\n val sel0 = Input(Bool())\n"}
{"file": "magma-si/src/main/scala/components/benseBuffers.scala", "target_type": "class_definition", "cursor_line": 8, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " val io = IO(new Bundle{\n val i_data_bus2 = Input(Vec(config.NUM_PES, UInt(config.DATA_TYPE.W)))\n val i_data_bus1 = Input(Vec(config.NUM_PES, UInt(config.DATA_TYPE.W)))\n val i_mux_bus = Input(Vec(config.NUM_PES, UInt((config.LEVELS-1).W)))\n"}
{"file": "magma-si/src/main/scala/components/buffer_multiplication.scala", "target_type": "function_definition", "cursor_line": 16, "target_nlines": 5, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " } else {\n val elementMul = vec1(index) * vec2(index)\n val result = multiply(vec1, vec2, index + 1)\n result(index) := elementMul\n result\n"}
{"file": "magma-si/src/test/scala/components/AdderSwitchTester.scala.scala", "target_type": "block", "cursor_line": 17, "target_nlines": 4, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block"], "target": " // dut.io.i_data_bus(7).poke(6.U)\n dut.io.i_valid.poke(1.B)\n dut.io.i_add_en.poke(1.U)\n dut.io.i_cmd.poke(5.U)\n"}
{"file": "magma-si/src/test/scala/components/BitmapTester.scala", "target_type": "block", "cursor_line": 22, "target_nlines": 4, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block", "lambda_expression", "indented_block", "for_expression", "block"], "target": " for (j <- 0 until 4) {\n dut.io.mat1(i)(j).poke(inputData(i)(j).U)\n dut.io.mat2(i)(j).poke(inputData(i)(j).U)\n }\n"}
{"file": "magma-si/src/test/scala/components/EdgeAdderSwitchTester.scala.scala", "target_type": "class_definition", "cursor_line": 8, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": "class EdgeAdderSwitchTester extends AnyFreeSpec with ChiselScalatestTester {\n \"Edge Adder Switch Test\" in {\n implicit val config = MagmasiConfig()\n"}
{"file": "magma-si/src/test/scala/components/FanCtrlTester.scala", "target_type": "block", "cursor_line": 21, "target_nlines": 5, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " c.io.i_vn(10).poke(\"b11111\".U)\n c.io.i_vn(11).poke(\"b11111\".U)\n\n c.io.i_vn(12).poke(\"b11111\".U)\n c.io.i_vn(13).poke(\"b11111\".U)\n"}
{"file": "magma-si/src/test/scala/components/FanNetworkTester.scala", "target_type": "class_definition", "cursor_line": 48, "target_nlines": 1, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " for (i <- 0 until 31) {\n"}
{"file": "magma-si/src/test/scala/components/FlexDPE_Tester.scala", "target_type": "block", "cursor_line": 38, "target_nlines": 2, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block"], "target": " c.io.i_vn(24).poke(\"b11111\".U)\n\n"}
{"file": "magma-si/src/test/scala/components/MultSwitchTester.scala", "target_type": "block", "cursor_line": 13, "target_nlines": 3, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block"], "target": " dut.io.i_data.poke(2.U)\n dut.io.i_stationary.poke(1.U)\n dut.io.o_valid.expect(0.B)\n"}
{"file": "magma-si/src/test/scala/components/MybenesTester.scala", "target_type": "block", "cursor_line": 22, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block"], "target": " val LEVELS : Int = (2 * (math.log(4) / math.log(2))).toInt + 1\n"}
{"file": "magma-si/src/test/scala/components/ReductionMuxTester.scala", "target_type": "block", "cursor_line": 13, "target_nlines": 5, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block"], "target": " dut.io.i_data(1).poke(4.U)\n dut.io.i_data(2).poke(5.U)\n dut.io.i_data(3).poke(6.U)\n dut.io.i_sel.poke(3.U)\n dut.clock.step(1)\n"}
{"file": "magma-si/src/test/scala/components/RegorTester.scala", "target_type": "class_definition", "cursor_line": 17, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " ) \n val inputData1 = Seq(\n Seq(1, 2, 0, 0),\n"}
{"file": "magma-si/src/test/scala/components/benesBuffersTester.scala", "target_type": "block", "cursor_line": 18, "target_nlines": 3, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block", "for_expression", "block"], "target": " for (i <- 0 until 4) {\n dut.io.i_data_bus1(i).poke(inputData(i).U)\n }\n"}
{"file": "magma-si/src/test/scala/components/bufferMultTester.scala", "target_type": "block", "cursor_line": 14, "target_nlines": 4, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block"], "target": " val inputData = Seq(1, 2, 3, 4, 5, 6, 7, 8)\n for (i <- 0 until NUM_IN) {\n dut.io.buffer1(i).poke(inputData(i).U)\n dut.io.buffer2(i).poke(inputData(i).U)\n"}
{"file": "tiny-gpu-chisel/playground/src/Alu.scala", "target_type": "class_definition", "cursor_line": 31, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " when(io.decoded_alu_op.output_mux) {\n // Set values to compare with NZP register in alu_out[2:0]\n val gt = io.reg_in.rs > io.reg_in.rt\n val eq = io.reg_in.rs === io.reg_in.rt\n val lt = io.reg_in.rs < io.reg_in.rt\n"}
{"file": "tiny-gpu-chisel/playground/src/Controller.scala", "target_type": "block", "cursor_line": 125, "target_nlines": 4, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "for_expression", "block", "call_expression", "block", "call_expression", "block"], "target": " current_consumer(i) := first_write_idx\n\n mem_write_valid(i) := true.B\n mem_write_address(i) := write_address\n"}
{"file": "tiny-gpu-chisel/playground/src/Core.scala", "target_type": "block", "cursor_line": 104, "target_nlines": 4, "node_depth": 7, "node_path": ["compilation_unit", "class_definition", "template_body", "val_definition", "call_expression", "arguments", "lambda_expression", "block"], "target": " lsu.io.enable := enable\n lsu.io.core_state := scheduler.io.core_state\n lsu.io.mem_rw_enable := decoder.io.mem_rw_enable\n lsu.io.mem_read_data := io.data_mem_read_data(i)\n"}
{"file": "tiny-gpu-chisel/playground/src/Decoder.scala", "target_type": "block", "cursor_line": 108, "target_nlines": 4, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block"], "target": " decoded_reg_write_enable := true.B\n decoded_reg_input_mux := RegInputOp.ARITHMETIC\n decoded_alu_arithmetic_mux := AluOpCode.DIV\n }\n"}
{"file": "tiny-gpu-chisel/playground/src/DecoupledGCD.scala", "target_type": "block", "cursor_line": 38, "target_nlines": 3, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "field_expression", "call_expression", "block"], "target": " x := x - y\n }.otherwise {\n y := y - x\n"}
{"file": "tiny-gpu-chisel/playground/src/DeviceControlRegister.scala", "target_type": "block", "cursor_line": 18, "target_nlines": 3, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when(!reset.asBool && io.device_control_write_enable) {\n device_control_register := io.device_control_data\n }\n"}
{"file": "tiny-gpu-chisel/playground/src/Dispatch.scala", "target_type": "block", "cursor_line": 41, "target_nlines": 1, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "arguments", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " cf\"Dispatch outputs: core_start=${core_start}, core_reset=${core_reset}, core_block_id=${core_block_id}, core_thread_count=${core_thread_count}, done=${done}\\n\"\n"}
{"file": "tiny-gpu-chisel/playground/src/Elaborate.scala", "target_type": "object_definition", "cursor_line": 21, "target_nlines": 3, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": " circt.stage.ChiselStage.emitSystemVerilogFile(new dcr.DeviceControlRegister(), args, firtoolOptions)\n circt.stage.ChiselStage.emitSystemVerilogFile(new controller.Controller(), args, firtoolOptions)\n circt.stage.ChiselStage.emitSystemVerilogFile(new gpu.Gpu(), args, firtoolOptions)\n"}
{"file": "tiny-gpu-chisel/playground/src/Fetcher.scala", "target_type": "block", "cursor_line": 45, "target_nlines": 3, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "call_expression", "block", "call_expression", "block"], "target": " when(io.core_state === CoreState.DECODE) {\n fetcher_state := FetcherState.IDLE\n }\n"}
{"file": "tiny-gpu-chisel/playground/src/GCD.scala", "target_type": "block", "cursor_line": 20, "target_nlines": 1, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " when(x > y) { x := x - y }.otherwise { y := y - x }\n"}
{"file": "tiny-gpu-chisel/playground/src/MemLoadStoreUnit.scala", "target_type": "block", "cursor_line": 97, "target_nlines": 3, "node_depth": 12, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "call_expression", "block", "call_expression", "block", "call_expression", "block"], "target": " when(io.core_state === CoreState.UPDATE) {\n lsu_state := LSUState.IDLE\n }\n"}
{"file": "tiny-gpu-chisel/playground/src/ProgramCounter.scala", "target_type": "block", "cursor_line": 50, "target_nlines": 5, "node_depth": 6, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block"], "target": " when(io.core_state === CoreState.UPDATE) {\n when(io.decoded_nzp_write_enable) {\n nzp := io.alu_out(2, 0)\n }\n }\n"}
{"file": "tiny-gpu-chisel/playground/src/RegisterFiles.scala", "target_type": "block", "cursor_line": 69, "target_nlines": 5, "node_depth": 4, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block"], "target": " }\n is(RegInputOp.MEMORY) {\n registers(io.decoded_reg_address.rd) := io.lsu_out\n }\n is(RegInputOp.CONSTANT) {\n"}
{"file": "tiny-gpu-chisel/playground/src/Scheduler.scala", "target_type": "block", "cursor_line": 60, "target_nlines": 3, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "template_body", "call_expression", "block", "call_expression", "block", "call_expression", "block", "call_expression", "block"], "target": " when(io.fetcher_state === FetcherState.FETCHED) {\n core_state := CoreState.DECODE\n }\n"}
{"file": "tiny-gpu-chisel/playground/src/StateCode.scala", "target_type": "object_definition", "cursor_line": 20, "target_nlines": 5, "node_depth": 1, "node_path": ["compilation_unit", "object_definition"], "target": "object RegInputOp extends ChiselEnum {\n val ARITHMETIC = Value(\"b00\".U)\n val MEMORY = Value(\"b01\".U)\n val CONSTANT = Value(\"b10\".U)\n}\n"}
{"file": "tiny-gpu-chisel/playground/test/src/AluSpec.scala", "target_type": "if_expression", "cursor_line": 27, "target_nlines": 1, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "if_expression", "block", "if_expression", "block", "val_definition", "if_expression"], "target": " val gt = if (rs > rt) 1 else 0\n"}
{"file": "tiny-gpu-chisel/playground/test/src/ControllerSpec.scala", "target_type": "match_expression", "cursor_line": 71, "target_nlines": 1, "node_depth": 7, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "for_expression", "block", "match_expression"], "target": " if (mem_write_ready(i)) {\n"}
{"file": "tiny-gpu-chisel/playground/test/src/CoreSpec.scala", "target_type": "class_definition", "cursor_line": 68, "target_nlines": 2, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " // PC output\n var next_pc = Array.fill(ThreadsPerBlock)(0)\n"}
{"file": "tiny-gpu-chisel/playground/test/src/DecoderSpec.scala", "target_type": "block", "cursor_line": 109, "target_nlines": 1, "node_depth": 10, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "if_expression", "block", "match_expression", "case_block", "case_clause", "block"], "target": " case _ => {}\n"}
{"file": "tiny-gpu-chisel/playground/test/src/DispatchSpec.scala", "target_type": "block", "cursor_line": 60, "target_nlines": 1, "node_depth": 13, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "for_expression", "block", "if_expression", "block", "if_expression", "block", "assignment_expression", "if_expression", "block"], "target": " } else { ThreadsPerCore }\n"}
{"file": "tiny-gpu-chisel/playground/test/src/FetcherSpec.scala", "target_type": "if_expression", "cursor_line": 28, "target_nlines": 5, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "match_expression", "case_block", "case_clause", "if_expression"], "target": " if (core_state == CoreState.FETCH) {\n fetcher_state = FetcherState.FETCHING\n read_valid = true\n read_address = current_pc\n }\n"}
{"file": "tiny-gpu-chisel/playground/test/src/GCDSpec.scala", "target_type": "block", "cursor_line": 56, "target_nlines": 4, "node_depth": 14, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "call_expression", "block", "lambda_expression", "indented_block", "while_expression", "block", "if_expression", "block", "if_expression", "block"], "target": " if (dut.output.valid.peekValue().asBigInt == 1) {\n dut.output.bits.gcd.expect(BigInt(testValues(received)._1).gcd(testValues(received)._2))\n received += 1\n }\n"}
{"file": "tiny-gpu-chisel/playground/test/src/GpuSpec.scala", "target_type": "block", "cursor_line": 329, "target_nlines": 1, "node_depth": 13, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "call_expression", "case_block", "case_clause", "call_expression", "arguments", "interpolated_string_expression", "interpolated_string", "interpolation", "block"], "target": " s\"Read: valid=${sender.valid.peek().litToBoolean}, addr=${sender.bits.peekValue().asBigInt.toInt}\"\n"}
{"file": "tiny-gpu-chisel/playground/test/src/GpuVM.scala", "target_type": "object_definition", "cursor_line": 25, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "object_definition", "template_body", "object_definition"], "target": " case object Ret extends Token\n"}
{"file": "tiny-gpu-chisel/playground/test/src/LsuSpec.scala", "target_type": "if_expression", "cursor_line": 108, "target_nlines": 1, "node_depth": 14, "node_path": ["compilation_unit", "class_definition", "template_body", "infix_expression", "block", "infix_expression", "block", "call_expression", "block", "lambda_expression", "indented_block", "while_expression", "block", "val_definition", "if_expression"], "target": " val write_enable = if (read_enable) false else rng.nextBoolean() // Ensure not both enabled\n"}
{"file": "tiny-gpu-chisel/playground/test/src/PCSpec.scala", "target_type": "function_definition", "cursor_line": 60, "target_nlines": 1, "node_depth": 3, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition"], "target": " def getNzp: Int = nzp\n"}
{"file": "tiny-gpu-chisel/playground/test/src/RegFileSpec.scala", "target_type": "class_definition", "cursor_line": 28, "target_nlines": 4, "node_depth": 1, "node_path": ["compilation_unit", "class_definition"], "target": " def update(\n enable: Boolean,\n block_id: Int,\n core_state: CoreState.Type,\n"}
{"file": "tiny-gpu-chisel/playground/test/src/SchdulerSpec.scala", "target_type": "if_expression", "cursor_line": 59, "target_nlines": 4, "node_depth": 8, "node_path": ["compilation_unit", "class_definition", "template_body", "function_definition", "block", "match_expression", "case_block", "case_clause", "if_expression"], "target": " core_state = CoreState.DONE\n } else {\n // Use the last thread's next_pc (same as in module)\n current_pc = next_pc(ThreadsPerBlock - 1)\n"}
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