prompt listlengths 2 2 | answer stringlengths 9 300 |
|---|---|
[
{
"role": "system",
"content": "You are an expert RTL hardware engineer. Given code context from multiple files and a specific cropped code block from a file, predict the next line of Verilog code that should logically come next. Respond with ONLY the next line of Verilog code."
},
{
"role": "user",... | infor = { (~cw[8]), cw[6:4], cw[2] }; end |
[
{
"role": "system",
"content": "You are an expert RTL hardware engineer. Given code context from multiple files and a specific cropped code block from a file, predict the next line of Verilog code that should logically come next. Respond with ONLY the next line of Verilog code."
},
{
"role": "user",... | input wire [11:0] A; |
[
{
"role": "system",
"content": "You are an expert RTL hardware engineer. Given code context from multiple files and a specific cropped code block from a file, predict the next line of Verilog code that should logically come next. Respond with ONLY the next line of Verilog code."
},
{
"role": "user",... | output reg [31:0] Do; |
[
{
"role": "system",
"content": "You are an expert RTL hardware engineer. Given code context from multiple files and a specific cropped code block from a file, predict the next line of Verilog code that should logically come next. Respond with ONLY the next line of Verilog code."
},
{
"role": "user",... | end else if(awaddr == 12'h10) begin |
[
{
"role": "system",
"content": "You are an expert RTL hardware engineer. Given code context from multiple files and a specific cropped code block from a file, predict the next line of Verilog code that should logically come next. Respond with ONLY the next line of Verilog code."
},
{
"role": "user",... | .rst_n (rst_n ), |
[
{
"role": "system",
"content": "You are an expert RTL hardware engineer. Given code context from multiple files and a specific cropped code block from a file, predict the next line of Verilog code that should logically come next. Respond with ONLY the next line of Verilog code."
},
{
"role": "user",... | reg bps_start_en = 1'b0 ; |
[
{
"role": "system",
"content": "You are an expert RTL hardware engineer. Given code context from multiple files and a specific cropped code block from a file, predict the next line of Verilog code that should logically come next. Respond with ONLY the next line of Verilog code."
},
{
"role": "user",... | always @ (posedge clk or negedge rstn) |
[
{
"role": "system",
"content": "You are an expert RTL hardware engineer. Given code context from multiple files and a specific cropped code block from a file, predict the next line of Verilog code that should logically come next. Respond with ONLY the next line of Verilog code."
},
{
"role": "user",... | D_ff_async uut (.d(d), .rstn(rstn), .clk(clk), .q(q)); |
[{"role":"system","content":"You are an expert RTL hardware engineer. Given code context from multip(...TRUNCATED) | instr_32 = {7'b0000000, instr_16[6:2], 5'd0, 3'b000, instr_16[11:7], 7'b0110011}; |
[{"role":"system","content":"You are an expert RTL hardware engineer. Given code context from multip(...TRUNCATED) | (mstatus_sel && csrrs_op)? (mstatus_reg | csr_write_data): |
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