content stringlengths 1 1.04M ⌀ |
|---|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 16/07/2014
--! Module Name: MUX2_Nbit
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use ... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 16/07/2014
--! Module Name: MUX2_Nbit
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use ... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 16/07/2014
--! Module Name: MUX2_Nbit
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
architecture RTL of ENTITY_NAME is
type T_FLAG_TYPE is protected -- protected type declaration
procedure init (foo : real);
impure function myfunct return boolean;
end protected T_FLAG_TYPE;
begin
end architecture RTL;
|
architecture RTL of FIFO is
TYPE state_machine is (idle, write, read, done);
-- Violations below
TYPE state_machine is (idle, write, read, done);
begin
end architecture RTL;
|
-- $Id: comlib.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2,... |
-- $Id: comlib.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2,... |
-- megafunction wizard: %ALTFP_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altfp_compare
-- ============================================================
-- File Name: fp_cmp.vhd
-- Megafunction Name(s):
-- altfp_compare
--
-- Simulation Library Files(s):
--
-- ================================... |
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity user_io_board_controller_opbw is
generic (
C_BASEADDR: std_logic_vector(0 to 31) := ... |
entity conv1 is
end entity;
architecture test of conv1 is
type my_bit_vector is array (natural range <>) of bit;
signal x : bit_vector(7 downto 0);
signal y : my_bit_vector(3 downto 0);
begin
process is
begin
x <= X"ab";
wait for 1 ns;
y <= my_bit_vector(x(3 downto 0));
... |
entity conv1 is
end entity;
architecture test of conv1 is
type my_bit_vector is array (natural range <>) of bit;
signal x : bit_vector(7 downto 0);
signal y : my_bit_vector(3 downto 0);
begin
process is
begin
x <= X"ab";
wait for 1 ns;
y <= my_bit_vector(x(3 downto 0));
... |
entity conv1 is
end entity;
architecture test of conv1 is
type my_bit_vector is array (natural range <>) of bit;
signal x : bit_vector(7 downto 0);
signal y : my_bit_vector(3 downto 0);
begin
process is
begin
x <= X"ab";
wait for 1 ns;
y <= my_bit_vector(x(3 downto 0));
... |
entity conv1 is
end entity;
architecture test of conv1 is
type my_bit_vector is array (natural range <>) of bit;
signal x : bit_vector(7 downto 0);
signal y : my_bit_vector(3 downto 0);
begin
process is
begin
x <= X"ab";
wait for 1 ns;
y <= my_bit_vector(x(3 downto 0));
... |
entity conv1 is
end entity;
architecture test of conv1 is
type my_bit_vector is array (natural range <>) of bit;
signal x : bit_vector(7 downto 0);
signal y : my_bit_vector(3 downto 0);
begin
process is
begin
x <= X"ab";
wait for 1 ns;
y <= my_bit_vector(x(3 downto 0));
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--
-- SDRAM controller. This uses the Altera sdr_sdram component to interface with
-- the SDRAM, and couple it to the 68k bus.
--
entity BusSDRAM is
PORT(
-- system signa... |
-- Fairly simple VGA (640x480 @ 60hz) output for the machine.
-- Connected to some memory so that it can get bytes in and then outputs the right RGB based
-- on the corresponding bit value in each byte. Fakes the cellophane overlays from the original
-- if colourOutput is high.
library IEEE;
use IEEE.STD_LOGIC_1164... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.command_if_pkg.all;
entity command_protocol is
port (
clock : in std_logic;
reset : in std_logic;
-- io int... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.command_if_pkg.all;
entity command_protocol is
port (
clock : in std_logic;
reset : in std_logic;
-- io int... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.command_if_pkg.all;
entity command_protocol is
port (
clock : in std_logic;
reset : in std_logic;
-- io int... |
architecture struct of trfsm is
constant MaxRowWidth : integer := 9; -- sync with entity generics "NumRowsX"
type NumRows_t is array (0 to MaxRowWidth) of integer;
constant NumRows : NumRows_t := (NumRows0,NumRows1,NumRows2,NumRows3,NumRows4,NumRows5,NumRows6,NumRows7,NumRows8,NumRows9);
constant RowOffset ... |
architecture struct of trfsm is
constant MaxRowWidth : integer := 9; -- sync with entity generics "NumRowsX"
type NumRows_t is array (0 to MaxRowWidth) of integer;
constant NumRows : NumRows_t := (NumRows0,NumRows1,NumRows2,NumRows3,NumRows4,NumRows5,NumRows6,NumRows7,NumRows8,NumRows9);
constant RowOffset ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_vga_framebuffer_v1_0_S_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AX... |
-------------------------------------------------------------------------------
-- Title : Goertzel Algorithm pipelined with BRAM
-- Project :
-------------------------------------------------------------------------------
-- File : goertzel_pipelined_v2.vhd
-- Author : strongly-typed
-- Created :... |
-------------------------------------------------------------------------------
-- Title : Goertzel Algorithm pipelined with BRAM
-- Project :
-------------------------------------------------------------------------------
-- File : goertzel_pipelined_v2.vhd
-- Author : strongly-typed
-- Created :... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
package p is
procedure foo(x : in integer; y : out integer);
procedure yah is -- Error
begin
null;
end procedure;
end package;
package body p is
procedure foo(x : in integer; y : out integer) is
variable i : integer;
begin
y := x + 1;
end proce... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Company: UOM
-- Engineer: Gihan Karunarathne
--
-- Create Date: 11:40:23 08/21/2013
-- Design Name:
-- Module Name: Full_Subtractor - Behavioral
-- Project Name: Tutorial I
-----------------------------------------... |
-- $Id: genlib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: genlib
-- Description: some general purpose com... |
library IEEE;
use IEEE.std_logic_1164.all;
entity valid is
generic
(
clock_speed0: std_logic; -- $SOL:0:0$
clock_speed1: std_logic := '0'; -- $SOL:1:0$
clock_g_speed2: natural; -- $SOL:2:0$
clock_g_speed3: natural := 3; -- $SOL:3:0$
i_g_g_param : std_logic -- $SOL:4:0$
);
end;
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity spi_sreg is
generic (
size_g : integer := 8
);
port (
clk : in std_logic;
rst : in std_logic;
--co... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity spi_sreg is
generic (
size_g : integer := 8
);
port (
clk : in std_logic;
rst : in std_logic;
--co... |
entity clock_Generator is
port (
Clock : out bit
);
end entity;
entity clock_Monitor is
port (
Clock : in bit
);
end entity;
package clock is
end package;
library Clock;
use Clock.clock.all;
entity test is
end entity;
architecture tb of test is
signal Clock : bit;
begin
gen: entity Clock.clo... |
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1... |
---------------------------------------------------------
-- JAM CPU core
-- Simple 32bit RISC CPU
--
-- Copyright © 2002:
-- Anders Lindström, Johan E. Thelin, Michael Nordseth
---------------------------------------------------------
-- This is free software; you can redistribute it and/or
-- modify it under the ter... |
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under ... |
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional... |
---------------------------------------------------------------------------
-- This file is part of lt24ctrl, a video controler IP core for Terrasic
-- LT24 LCD display
-- Copyright (C) 2017 Ludovic Noury <ludovic.noury@esiee.fr>
--
-- This program is free software: you can redistribute it and/or
-- modify it under th... |
architecture RTL of FIFO is begin end architecture RTL;
-- This should not fail
architecture RTL of FIFO is begin end architecture RTL;
-- This should fail
library ieee;
architecture RTL of FIFO is begin end architecture RTL;
-- This should not fail
library ieee;
architecture RTL of FIFO is begin end architecture ... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This fil... |
-- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: lpm_dff_uart0.vhd
-- Megafunction Name(s):
-- lpm_ff
--
-- Simulation Library Files(s):
-- lpm
-- ===============================... |
entity test is
subtype t is foo(bar (open)(open)(baz (quz'xxx)));
end;
|
-------------------------------------------------------------------------------------
-- FILE NAME : tb_toggle.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity -
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : May 21, 2010
-------------------------------------------------... |
-----LIBRARIES-----
library ieee;
use ieee.std_logic_1164.all;
-----ENTITY-----
entity SevenSegCase is
port (
-- Inputs, outputs, inouts go here...
bin : in std_logic_vector(3 downto 0);
seg : out std_logic_vector(6 downto 0)
);
end entity;
-----Architecture-----
architecture Decode of SevenSegCase is
--... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_243 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_243;
architecture augh of sub_243 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_243 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_243;
architecture augh of sub_243 is
signal carry_inA : std_l... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
use work.pkg.all;
use work.all;
entity repro is
end repro;
architecture behav of repro is
component comp is
end component;
begin
c : comp;
end behav;
|
use work.pkg.all;
use work.all;
entity repro is
end repro;
architecture behav of repro is
component comp is
end component;
begin
c : comp;
end behav;
|
entity sub is
end entity;
architecture test of sub is
type rec is record
x : integer;
end record;
constant c : rec := (x => 2);
signal ss : rec := c;
function add1(x : integer) return integer is
begin
return x + 1;
end function;
begin
process is
variable r ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_spi_master_v1_0_S00_AXI is
generic (
-- Users to add parameters here
SPI_DATA_WIDTH : integer := 8;
SPI_CLK_DIV : integer := 100;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width o... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_spi_master_v1_0_S00_AXI is
generic (
-- Users to add parameters here
SPI_DATA_WIDTH : integer := 8;
SPI_CLK_DIV : integer := 100;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width o... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_spi_master_v1_0_S00_AXI is
generic (
-- Users to add parameters here
SPI_DATA_WIDTH : integer := 8;
SPI_CLK_DIV : integer := 100;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width o... |
entity ODD_PARITY_TB is
end;
library ieee;
use ieee.std_logic_1164.all;
architecture
OP_TB_ARCH of ODD_PARITY_TB is
component Parity_Generator1
port(
input_stream : in input;
clk : in std_logic;
parity : out bit);
end component;
signal input_stream : input;
signal clk :std_logic;
signal parity... |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.math_real.all ;
use ieee.math_complex.all ;
architecture hosted_bladerf of bladerf is
component nios_system is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in ... |
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram_dq_PHASE_m.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- =======================... |
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram_dq_PHASE_m.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- =======================... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk512_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(2 downto 0)
);
end dk512_rnd;
architecture behaviour of dk512_rnd is
constant state_1: std_logic_vector(3 downto ... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:12:10 03/30/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/ProjLab1/DCCTL_tb.vhd
-- Project Name: ProjLab1
-- Target Device:
-- Tool versio... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:12:10 03/30/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/ProjLab1/DCCTL_tb.vhd
-- Project Name: ProjLab1
-- Target Device:
-- Tool versio... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:12:10 03/30/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/ProjLab1/DCCTL_tb.vhd
-- Project Name: ProjLab1
-- Target Device:
-- Tool versio... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:12:10 03/30/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/ProjLab1/DCCTL_tb.vhd
-- Project Name: ProjLab1
-- Target Device:
-- Tool versio... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:12:10 03/30/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/ProjLab1/DCCTL_tb.vhd
-- Project Name: ProjLab1
-- Target Device:
-- Tool versio... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:12:10 03/30/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/ProjLab1/DCCTL_tb.vhd
-- Project Name: ProjLab1
-- Target Device:
-- Tool versio... |
entity sub1 is
port (i : bit_vector);
end;
entity notype1 is
end;
architecture behav of notype1 is
type counter_t is array (2 downto 0) of (31 downto 0);
signal cnts : counter_t;
begin
i : entity work.sub1
port map (i => cnts (0));
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fullAdder is (
Port(
A: in STD_LOGIC;
B: in STD_LOGIC;
Cin: in STD_LOGIC;
Cout: out STD_LOGIC;
Sum: out STD_LOGIC;
);
);
architecture FullAdderBehavioral is
begin
Sum <= A xor B xor Cin;
... |
-------------------------------------------------------------------------------
--! @file atomicmodifyRtl.vhd
--
--! @brief Atomic modify
--
--! @details This component is used to modify memory atomically.
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automa... |
-- NEED RESULT: ARCH00075.P1: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075.P2: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00075.P3: Multi transport transactions occurred on signal asg with simpl... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
entity concat is
end entity;
architecture arch of concat is
type int_array is array (integer range <>) of integer;
begin
process
variable w : int_array(1 to 4);
variable x, y : int_array(1 to 3);
variable z : int_array(1 to 6);
variable s : string(1 to 5);
variable t : ... |
-- megafunction wizard: %ALTPLL_RECONFIG%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll_reconfig
-- ============================================================
-- File Name: PLL_RECONFIG.vhd
-- Megafunction Name(s):
-- altpll_reconfig
--
-- Simulation Library Files(s):
-- altera_mf;cycloneive;lpm... |
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Company: Nameless2
-- Engineer: Ana María Martínez Gómez, Aitor Alonso Lorenzo, Víctor Adolfo Gallego Alcalá
--
-- Create Date: 12:15:23 11/18/2013
-- Design Name:
-- Module Name: conversor - Behavioral
-- Project Nam... |
----------------------------------------------------------------------------------
-- Company: Nameless2
-- Engineer: Ana María Martínez Gómez, Aitor Alonso Lorenzo, Víctor Adolfo Gallego Alcalá
--
-- Create Date: 12:15:23 11/18/2013
-- Design Name:
-- Module Name: conversor - Behavioral
-- Project Nam... |
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