prompt stringlengths 162 4.26M | response stringlengths 109 5.16M |
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Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
class IDPool(numIds: Int, lateValid: Boolean = false, revocableSelect: Boolean = false) extends Module {
require (numIds > 0)
val idWidth... | module IDPool(
input clock,
input reset,
input io_free_valid,
input [2:0] io_free_bits,
input io_alloc_ready,
output io_alloc_valid,
output [2:0] io_alloc_bits
);
reg [7:0] bitmap;
reg [2:0] select;
reg valid;
wire [7:0] taken = io_alloc_ready ? 8'h1 <<... |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If no... | module data_40x37(
input [5:0] R0_addr,
input R0_en,
input R0_clk,
output [36:0] R0_data,
input [5:0] W0_addr,
input W0_en,
input W0_clk,
input [36:0] W0_data
);
reg [36:0] Memory[0:39];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] ... |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or c... | module ClockCrossingReg_w32(
input clock,
input [31:0] io_d,
output [31:0] io_q,
input io_en
);
reg [31:0] cdc_reg;
always @(posedge clock) begin
if (io_en)
cdc_reg <= io_d;
end
assign io_q = cdc_reg;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.jtag for license details.
package freechips.rocketchip.jtag
import chisel3._
import chisel3.reflect.DataMirror
import chisel3.internal.firrtl.KnownWidth
import chisel3.util.{Cat, Valid}
import org.chipsalliance.cde.config.Parameters
import fr... | module CaptureChain_JTAGIdcodeBundle(
input clock,
input reset,
input io_chainIn_shift,
input io_chainIn_data,
input io_chainIn_capture,
input io_chainIn_update,
output io_chainOut_data
);
reg regs_0;
reg regs_1;
reg regs_2;
reg regs_3;
reg regs_4;
reg regs_5;
reg regs_6;
reg regs_7... |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPref... | module LoopBranchPredictorColumn(
input clock,
input reset,
input [36:0] io_f2_req_idx,
input io_f3_req_fire,
input io_f3_pred_in,
output io_f3_pred,
output [9:0] io_f3_meta_s_cnt,
input io_update_mispredict,
input io_update_repair,
input [36... |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and And... | module RoundRawFNToRecFN_e8_s24(
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [9:0] io_in_sExp,
input [26:0] io_in_sig,
input [2:0] io_roundingMode,
output [32:0] io_out,
output [4:0] io_exception... |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPref... | module ebtb(
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [39:0] R0_data,
input [6:0] W0_addr,
input W0_en,
input W0_clk,
input [39:0] W0_data
);
ebtb_ext ebtb_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_da... |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//----------------... | module regfile_48x65(
input [5:0] R0_addr,
input R0_en,
input R0_clk,
output [64:0] R0_data,
input [5:0] R1_addr,
input R1_en,
input R1_clk,
output [64:0] R1_data,
input [5:0] R2_addr,
input R2_en,
input R2_clk,
output [64:0] R2_data,
input... |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and And... | module RecFNToIN_e11_s53_i64(
input [64:0] io_in,
input [2:0] io_roundingMode,
input io_signedOut,
output [63:0] io_out,
output [2:0] io_intExceptionFlags
);
wire rawIn_isNaN = (&(io_in[63:62])) & io_in[61];
wire magJustBelowOne = ~(io_in[63]) & (&(io_in[62:52]));
wire ... |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//----------------... | module FMADecoder(
input [6:0] io_uopc,
output [1:0] io_cmd
);
wire [5:0] decoder_decoded_invInputs = ~(io_uopc[5:0]);
assign io_cmd = {|{&{io_uopc[0], io_uopc[1], io_uopc[2], io_uopc[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], decod... |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and And... | module RecFNToIN_e11_s53_i32(
input [64:0] io_in,
input [2:0] io_roundingMode,
input io_signedOut,
output [2:0] io_intExceptionFlags
);
wire magJustBelowOne = ~(io_in[63]) & (&(io_in[62:52]));
wire [83:0] shiftedSig = {31'h0, io_in[63], io_in[51:0]} << (io_in[63] ? io_in[56:52] : 5'h0);
... |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPref... | module TageTable_1(
input clock,
input reset,
input io_f1_req_valid,
input [39:0] io_f1_req_pc,
input [63:0] io_f1_req_ghist,
output io_f3_resp_0_valid,
output [2:0] io_f3_resp_0_bits_ctr,
output [1:0] io_f3_resp_0_bits_u,
output io_f3_resp_1_valid,
output [... |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//----------------... | module ghist_1(
input [3:0] R0_addr,
input R0_clk,
output [71:0] R0_data,
input [3:0] W0_addr,
input W0_en,
input W0_clk,
input [71:0] W0_data
);
ghist_0_ext ghist_0_ext (
.R0_addr (R0_addr),
.R0_en (1'h1),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_ad... |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Cat, log2Up, log2Ceil, log2Floor, Log2, Decoupled, Enum, Fill, Valid, Pipe}
import freechips.roc... | module PipelinedMultiplier(
input clock,
input reset,
input io_req_valid,
input [4:0] io_req_bits_fn,
input io_req_bits_dw,
input [63:0] io_req_bits_in1,
input [63:0] io_req_bits_in2,
output [63:0] io_resp_bits_data
);
reg in_pipe_v;
reg [4:0] in_pipe... |
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