dataset_schema.md

Dataset Schema

Per-row reference for pphilip/analog-circuits-sky130. Companion document to the dataset card.

Three of the columns are JSON strings carrying nested structure (sim_params, metrics, netlist_json). This document freezes the key names and semantics within those strings so consumers can parse them with confidence.

Arrow schema

Every row, every split, every source:

Column	Type	Description
circuit_id	string	Unique row id. Sweep siblings share a base_circuit_id prefix + _sNNN suffix.
base_circuit_id	string	Structural identity — sweep siblings of one graph share this value. Used as the split-group key.
topology	string	Topology family label (one of 49 — see vocabulary below).
source_dataset	string	"ocb" / "analogtobi" / "analoggym".
pdk	string	"sky130" in current release
sim_params	string (JSON)	Simulation configuration + sweep point. See § sim_params.
converged	bool	true if ngspice reached a valid operating point and the requested analyses completed.
error	string	Empty "" on converged rows; one of 7 vocabulary strings otherwise. See § error vocabulary.
metrics	string (JSON)	Testbench-type-specific measurements. See § metrics.
netlist_json	string (JSON)	Lossless typed-pin graph primitive. See § netlist_json.
testbench_spice	string (SPICE)	Only present in the with_testbench config. The exact ngspice-ready testbench that produced metrics. Contains a {{SKY130_LIB}} placeholder that consumers substitute with their local PDK .lib path before running ngspice. See § testbench_spice.

Stability intent: column additions across releases will be append-only so existing consumers don't break silently. Any column rename or removal would be flagged prominently in the release notes.

Topology vocabulary (49 families)

Every row's topology value comes from a fixed set of 49 strings in this release. Full list + sample counts + upstream sources is in the dataset card's "Topology families" table.

sim_params (JSON string)

Captures everything needed to re-run the exact same simulation. Parsed as:

{
  "vdd": 1.8,
  "vth": 0.5,
  "vov": 0.2,
  "kp_n": 2e-4,
  "kp_p": 8e-5,
  "default_l": 0.5,
  "model_map": {
    "nmos4": "sky130_fd_pr__nfet_01v8",
    "pmos4": "sky130_fd_pr__pfet_01v8",
    "npn":   "sky130_fd_pr__npn_05v5_W1p00L1p00",
    "pnp":   "sky130_fd_pr__pnp_05v5_W3p40L3p40"
  },
  "testbench": "OpampTestbench",
  "convergence_opts": {},
  "sweep": {
    "design": {"w_scale": 1.34, "l_scale": 0.92},
    "test":   {"ib_scale": 0.67, "cl_F": 4.2e-12}
  }
}

Key	Type	Meaning
vdd	float	Supply voltage used for this sim (V).
vth	float	Nominal MOSFET threshold voltage (V). Used by the bias-inference heuristic.
vov	float	Nominal gate overdrive voltage (V).
kp_n, kp_p	float	Nominal NMOS / PMOS transconductance parameter (A/V²).
default_l	float	Default channel length applied when the DUT builder has no better info (µm).
model_map	dict[str,str]	Mapping from abstract device-type token → PDK-specific subcircuit name. Captures which SKY130 model bin each MOSFET/BJT uses.
testbench	str	One of: OpampTestbench, LdoTestbench, BandgapTestbench, ComparatorTestbench, VcoTestbench, MixerTestbench, PaTestbench. Determines which metric keys appear in metrics.
convergence_opts	dict	Per-PDK .option directives (gmin, gminsteps) appended to the testbench header. Empty for SKY130 in this release.
sweep	dict or null	Null for 1× default-sizing rows (OCB and AnalogToBi baseline); populated for LHS sweep points.
sweep.design.w_scale	float	Multiplicative factor applied to every MOSFET W. Log-uniform over [0.3, 3.0], post-clamped to W_MAX = 500 µm.
sweep.design.l_scale	float	Multiplicative factor applied to every MOSFET L. Log-uniform over [0.7, 1.5].
sweep.test.ib_scale	float	Scale applied to external I__* bias sources. Log-uniform over [0.3, 3.0].
sweep.test.cl_F	float	Absolute load capacitance (F). Log-uniform over [1e-14, 1e-10].

Design / test axis split (inspired by FALCON's contribution gap): sweep.design modifies the DUT itself (wing geometry); sweep.test modifies the testbench harness (airspeed). Consumers can project the 4-D LHS down to design-only or operating-condition-only as needed.

metrics (JSON string)

Keys depend on the testbench (sim_params.testbench) because different analyses emit different output signals. dc_gain_dB only appears on AC-based testbenches; time-domain ones emit vout_min_V / vout_max_V / t_*_s instead.

Key catalogue per testbench

Testbench	Always-present keys	Conditional keys	Sample rows
OpampTestbench	dc_gain_dB, vdd_current_A, power_W	vout_dc_V (98.6%), ugf_Hz (27.4%), phase_at_ugf_deg (27.4%)	107,672
LdoTestbench	vdd_current_A, power_W	dc_gain_dB (99.1%), vout_dc_V (98.1%), ugf_Hz (1.3%)	9,748
BandgapTestbench	vdd_current_A, power_W	vout_dc_V (96.7%)	7,101
VcoTestbench	vout_min_V, vout_max_V	vdd_current_A (93%), power_W (93%), vout_dc_V (53%), osc_freq_Hz (1.8%), t_rise1_s, t_rise2_s	2,166
MixerTestbench	dc_gain_dB	vdd_current_A (97%), power_W (97%), vout_dc_V (47%)	708
PaTestbench	dc_gain_dB, vdd_current_A, power_W	vout_dc_V (67%), ugf_Hz (4.2%)	504
ComparatorTestbench	vout_min_V, vout_max_V, vdd_current_A, power_W	vout_dc_V (85%), t_out_cross_s (6%)	327

Conditional-key percentages are measured against converged rows in this release.

Key semantics

Key	Unit	Meaning
dc_gain_dB	dB	Small-signal AC gain at 1 Hz. For LdoTestbench, this is vdb(vout) with VDD AC 1 — functionally the negated PSRR (conventionally reported as the absolute value).
ugf_Hz	Hz	Unity-gain frequency — lowest frequency at which vdb(vout) = 0. NaN-equivalent (key absent) if the AC sweep never crosses 0 dB.
phase_at_ugf_deg	degrees	Phase margin proxy — phase of the AC response at ugf_Hz.
vout_dc_V	V	Output node DC level from the .op solve.
vout_min_V, vout_max_V	V	Transient output extremes over the simulated window. Used by time-domain testbenches (VCO, comparator) to detect oscillation amplitude / switching range.
vdd_current_A	A	Current into VDD at the DC operating point. Sign convention: negative = sourcing (VDD → circuit → GND), which is the typical case.
power_W	W	abs(vdd_current_A) * vdd.
osc_freq_Hz	Hz	Detected oscillation frequency (VCO, oscillator). Present only when the transient produced a stable oscillation — rare at default sizing (1.8% of VCO rows).
t_rise1_s, t_rise2_s, t_out_cross_s	s	Transient timestamp markers for switching measurements (comparator, VCO first/second zero-crossing).

⚠️ Known caveats on metrics semantics

1. Testbench-topology mismatch for non-amplifier circuits. Most non-op-amp topologies are simulated with OpampTestbench (the only shipped AC testbench that fits a 2-input / 1-output pattern). Their dc_gain_dB is the literal small-signal AC response of the circuit, which is a real physical number, but often not the canonical metric a designer would cite for that topology. Concrete symptom: ~22% of converged rows have |dc_gain_dB| < 0.1, dominated by OCB opamps with degenerate behavioural→transistor remaps (19K rows) and AnalogToBi switched-capacitor samplers (5.6K rows). Treat dc_gain_dB as a signal-path DC indicator, not a performance metric.

2. Missing dc_gain_dB is not an error. Time-domain testbenches (VcoTestbench, ComparatorTestbench, BandgapTestbench) don't produce an AC gain; they emit temperature-sweep voltages, oscillation metrics, or transient edge timestamps instead. 7.6% of converged rows land in this regime.

3. Units are SI throughout (V, A, W, Hz, s). MOSFET dimensions in netlist_json.devices[].params are in µm (our ngspice runs with ngbehavior=hs + scale=1e-6).

4. dc_gain_dB can be negative. Many sweep points land in attenuation (gain < 1, so dB < 0) rather than amplification — that's the physical answer for a degenerate bias point or a non-amp topology driven through an OpampTestbench, not a data bug. If you train a regressor with a log1p(y) or other unsigned transform on this target, it will silently clamp all attenuation samples to 0 and bias the model. Use a sign-preserving transform (e.g. sign(y) * log1p(|y|)), or filter to positive-gain rows with ds.filter(lambda r: json.loads(r["metrics"]).get("dc_gain_dB", 0) > 0) before training.

netlist_json (JSON string)

Lossless typed-pin primitive — the canonical graph representation. See scripts/pyg/schema.py for the builder; full primitive schema:

{
  "nets": [
    {"name": "VDD",  "role": "supply_pos", "external": true},
    {"name": "NET1", "role": "internal",   "external": false}
  ],
  "devices": [
    {"name": "M1", "type": "nmos", "model": "nmos4",
     "pins": [{"role": "D", "net": "NET1"}, {"role": "G", "net": "VIN"},
              {"role": "S", "net": "VSS"}, {"role": "B", "net": "VSS"}],
     "params": {"W": 10.0, "L": 0.5}}
  ]
}

Vocabularies (frozen, tested in tests/test_vocabularies.py):

• Device types: nmos, pmos, npn, pnp, res, cap, ind, isrc, vsrc, other (overflow).
• Pin roles: D / G / S / B (MOSFET drain/gate/source/bulk), C / B / E / SUB (BJT collector/base/emitter/substrate), P / N (2-terminal positive/negative), X (overflow).
• Net roles: supply_pos, supply_neg, input_v, input_i, output_v, output_i, bias_voltage, bias_current, clock, logic, lo_drive, rf_input, internal, unknown.

Three projections live in scripts/pyg/:

Function	Shape	Typical use
to_bipartite(p)	Two node classes (devices + nets), incidence edges.	OCB-style heterogeneous GNNs.
to_bus(p)	Nets as nodes, devices as multi-edges.	FALCON's graph.json shape.
to_node_centric(p)	Devices as nodes, shared nets as edges.	Compact device-level GNNs.

Every projection carries pin-role and net-role attributes so the primitive is fully recoverable.

testbench_spice (SPICE text, with_testbench config only)

The exact ngspice-ready SPICE that produced this row's metrics. Running ngspice -b on this text (after substituting the PDK path placeholder) bit-reproduces every numeric value in metrics.

Structure (roughly, varies per testbench type):

* testbench for <circuit_id> (sky130 typical)
.lib "{{SKY130_LIB}}" tt            ← placeholder; consumers substitute their local lib path

* --- Supply ---
VDD VDD 0 DC 1.8
VSS VSS 0 DC 0

* --- Bias (BFS + Vth/Vov) ---
V__VB1 VB1 0 DC 0.900              ← inferred bias voltages (port-role heuristic)
I__IB1 IB1 VSS DC 0.000050         ← inferred bias currents

* --- Input ---
VIN1 VIN1 0 DC 0.9 AC 1            ← topology-specific stimulus

* --- DUT: <circuit_id> ---
X<name> <d> <g> <s> <b> <sky130 model> W=... L=...
...

* --- Load ---
CL VOUT 0 10p

* --- Analysis ---
.control
op
ac dec 20 1 1G
meas ac dc_gain_dB find vdb(vout) at=1
...
quit
.endc
.end

The only environment-specific token is the {{SKY130_LIB}} placeholder — everything else is deterministic given the same circuit + ngspice version.

Consumer workflow:

import os
sky130_lib = os.environ["SKY130_LIB"]
spice = row["testbench_spice"].replace("{{SKY130_LIB}}", sky130_lib)
# → hand to ngspice as a batch-mode input

example_simulate.py in the repo automates this. The with_testbench config adds ~40 MB to the default download; skip it if you only need to train on metrics and don't need to re-run ngspice.

Notes

• ngspice lowercases output. ngbehavior=hs (which the testbench sets via .spiceinit) lowercases tokens during parsing. .meas ac dc_gain_dB prints as dc_gain_db = …. Parse case-insensitively.
• Sweep-aware deck. Rows with sim_params.sweep ≠ null carry their sweep's W/L/Ibias/CL values baked into the deck. You don't need to re-apply the sweep yourself — what's in testbench_spice IS the sweep sample.
• Failed rows (converged=false). The failed split also carries testbench_spice for rows where the builder succeeded but ngspice didn't converge. Re-running these with different .option directives or tighter initial conditions may rescue some.

error vocabulary

Converged rows carry error = "". Failed rows use exactly one of:

Value	Cause
no_convergence	ngspice DC operating point iteration hit the step limit without converging.
singular_matrix	Jacobian was singular — typically compact-model internal parasitic nodes without a DC path to ground.
timeout	Runner killed ngspice after sim_params.convergence_opts-defined timeout (60 s for sky130).
sim_error	ngspice exited non-zero with an unclassified failure. Often a parser or model-lookup error.
no_output_port	Testbench generator couldn't identify an output node in the netlist — structural issue, not a simulator one.
netlist_not_found	The source .spice file wasn't on disk at simulation time. Shouldn't appear in the shipped release.
model_not_found	PDK subcircuit for a device's model token couldn't be resolved — e.g. W/L outside BSIM4 bin coverage.

Supported tasks

Three task variants are explicitly supported by the schema. Code snippets use the unified config (load_dataset("pphilip/analog-circuits-sky130", split="train")).

1. netlist → metrics (regression)

Predict performance metrics from the circuit graph + sweep parameters.

The snippet below includes a self-contained to_bus converter — nets-as-nodes, devices-as-edges. The full converter (with pin-role features and all three projections: bipartite, bus, node-centric) lives in the project repo at scripts/pyg/ — copy it from there if you want the complete feature set.

import json, torch
from itertools import combinations
from datasets import load_dataset
from torch_geometric.data import Data

DEVICE_TYPES = ["nmos", "pmos", "npn", "pnp", "res", "cap", "ind",
                "isrc", "vsrc", "other"]
DTYPE_IDX = {t: i for i, t in enumerate(DEVICE_TYPES)}


def to_bus(primitive_json: str) -> dict:
    """Minimal bus projection: nets→nodes, device pin-pairs→edges.

    One edge per unordered pair of pins on the same device. A 4-pin MOSFET
    yields 6 edges; a 2-pin R/C yields 1. Edges are duplicated in both
    directions so message passing sees a symmetric graph.
    """
    p = json.loads(primitive_json)
    net_idx = {n["name"]: i for i, n in enumerate(p["nets"])}
    src, dst, edge_type, edge_dev_id = [], [], [], []
    for dev_id, d in enumerate(p["devices"]):
        t = DTYPE_IDX.get(d["type"], DTYPE_IDX["other"])
        pins = d["pins"]
        for a, b in combinations(range(len(pins)), 2):
            ia, ib = net_idx.get(pins[a]["net"]), net_idx.get(pins[b]["net"])
            if ia is None or ib is None:
                continue
            for u, v in ((ia, ib), (ib, ia)):
                src.append(u); dst.append(v)
                edge_type.append(t); edge_dev_id.append(dev_id)
    return {
        "num_nodes": len(p["nets"]),
        "edge_index": [src, dst],
        "edge_type": edge_type,
        "edge_device_id": edge_dev_id,
    }


ds = load_dataset("pphilip/analog-circuits-sky130", split="train")

def row_to_pyg(r):
    g = to_bus(r["netlist_json"])
    y = json.loads(r["metrics"]).get("dc_gain_dB", float("nan"))
    return Data(
        edge_index=torch.tensor(g["edge_index"], dtype=torch.long),
        edge_attr=torch.tensor(g["edge_type"], dtype=torch.long).unsqueeze(-1),
        num_nodes=g["num_nodes"],
        y=torch.tensor([y], dtype=torch.float),
    )

Filter to op-amp testbench rows first if you want a uniform target:

op_ds = ds.filter(lambda r: json.loads(r["sim_params"])["testbench"] == "OpampTestbench")

2. metrics → topology (classification)

49-class classification from the metric vector.

import json
from datasets import load_dataset

TOPO_VOCAB = sorted({r["topology"] for r in load_dataset(
    "pphilip/analog-circuits-sky130", split="train"
)})
TOPO_TO_IDX = {t: i for i, t in enumerate(TOPO_VOCAB)}

def row_to_cls(r):
    m = json.loads(r["metrics"])
    features = [m.get(k, float("nan")) for k in (
        "dc_gain_dB", "ugf_Hz", "phase_at_ugf_deg",
        "vout_dc_V", "vdd_current_A", "power_W"
    )]
    return features, TOPO_TO_IDX[r["topology"]]

Class imbalance is extreme (55% opamp). Apply torch.utils.data.WeightedRandomSampler or class-weighted loss.

3. metrics → sizing (inverse-design regression)

Predict W, L, I_bias scale factors (and/or per-device sizing from netlist_json.devices[].params) from target metrics. Requires conditioning on topology.

import json
from datasets import load_dataset

ds = load_dataset("pphilip/analog-circuits-sky130", split="train")
# Sweep rows only — the default-sizing 1× baseline carries no sizing signal
sweep = ds.filter(lambda r: json.loads(r["sim_params"]).get("sweep") is not None)

def row_to_inverse(r):
    sp = json.loads(r["sim_params"])
    m = json.loads(r["metrics"])
    target_metrics = [m.get(k, float("nan")) for k in ("dc_gain_dB", "ugf_Hz", "power_W")]
    sizing = [
        sp["sweep"]["design"]["w_scale"],
        sp["sweep"]["design"]["l_scale"],
        sp["sweep"]["test"]["ib_scale"],
    ]
    return target_metrics, sizing, r["topology"]

Reproducibility

• Split determinism: base_circuit_id → split is stored in splits.json. Rebuild with scripts/build_hf_release.py --seed 42 (default).
• Simulation determinism: ngspice DC / AC analyses are deterministic given the same netlist + .option directives. Transient solvers can diverge across versions — sim_params captures every parameter needed to re-run.
• Schema stability: the vocabularies (DEVICE_TYPES, PIN_ROLES, NET_ROLES, error strings, topology families) in this release are fixed; any change in a future release would be announced in the release notes.