LLM4Cov
Collection
7 items • Updated • 1
id string | difficulty string | is_agentic string | instruction string | targets list | dut_module_name string | dut_instance_name string | rtl_files list | spec_files list |
|---|---|---|---|---|---|---|---|---|
cvdp_agentic_byte_enable_ram_0004 | medium | Agentic | I have a specification of a custom_byte_enable_ram module in the docs directory. Write a SystemVerilog testbench `tb_custom_byte_enable_ram.sv` in the verif directory to apply stimulus and achieve maximum coverage for the `custom_byte_enable_ram` module.
Include the following in the generated testbench:
**Module Inst... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 95
}
] | custom_byte_enable_ram | uut | [
{
"name": "custom_byte_enable_ram.sv",
"content": "module custom_byte_enable_ram \n #(\n parameter XLEN = 32,\n parameter LINES = 8192\n )\n (\n input logic clk,\n input logic[$clog2(LINES)-1:0] addr_a,\n input logic en_a,\n input logic[XLEN... | [
{
"name": "specs.md",
"content": "# Custom Byte-Enable RAM Module\n\nThis module implements a dual-port RAM with byte-enable support and pipelining, designed for efficient memory operations in systems such as processors or embedded controllers. It features separate interfaces for two independent ports (Port... |
cvdp_copilot_hamming_code_tx_and_rx_0031 | easy | Non-Agentic | Create a testbench to only supply stimulus to a `hamming_code_receiver` module. This module decodes an 8-bit input signal and detects single-bit errors using Hamming code principles. The receiver performs "even parity checks" to identify single-bit errors in `data_in` and provides corrected 4-bit data through the outpu... | [
{
"inst_name": "uut_receiver",
"metric": "Overall Average",
"target_percentage": 100
}
] | hamming_code_receiver | uut_receiver | [
{
"name": "hamming_code_receiver.sv",
"content": "module hamming_code_receiver (\n input[7:0] data_in,\n output [3:0] data_out\n);\n \n wire c1,c2,c3,error;\n reg[7:0] correct_data;\n \n \n assign c3 = data_in[1] ^ data_in[3] ^ data_in[5] ^ data_in[7];\n assign c2 = data_in[2] ^ data_in[3] ^ data_in... | [] |
cvdp_copilot_simple_spi_0003 | medium | Non-Agentic | Create a test bench in SystemVerilog for a Verilog module named `spi_fsm`. The module handles data transmission in a serial format from a 16-bit input vector (`i_data_in`) using an SPI protocol. The design includes proper state transitions, signal handling, and timing synchronization to ensure accurate data transmissio... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 94
}
] | spi_fsm | dut | [
{
"name": "spi_fsm.v",
"content": "module spi_fsm (\n input wire i_clk, // System clock\n input wire i_rst_b, // Active-low async reset\n input wire [15:0] i_data_in, // Parallel 16-bit data to transmit\n input wire i_enable, // Enable block\n input... | [] |
cvdp_copilot_word_reducer_0012 | easy | Non-Agentic | Create a testbench named `tb_Bit_Difference_Counter` using SystemVerilog to generate stimulus for the `Bit_Difference_Counter` module, which calculates the hamming distance (bitwise difference) between two inputs of equal bit width. The testbench should apply edge-case scenarios and random input patterns to thoroughly ... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 100
}
] | Bit_Difference_Counter | dut | [
{
"name": "Data_Reduction.sv",
"content": "`timescale 1ns / 1ps\n\nmodule Bit_Difference_Counter\n#(\n parameter BIT_WIDTH = 3, // Defines the width of the input vectors.\n localparam COUNT_WIDTH = $clog2(BIT_WIDTH + 1) // Calculates the width required to represent th... | [] |
cvdp_agentic_ttc_lite_0007 | hard | Agentic | I have a specification of a `ttc_counter_lite` module in the `docs` directory. Write a SystemVerilog TB `ttc_counter_lite_tb.sv` in the `verif` directory to only generate stimuli and achieve maximum functional coverage for the `ttc_counter_lite` module.
Include the following in the generated testbench:
- **Module Ins... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 99
}
] | ttc_counter_lite | dut | [
{
"name": "ttc_counter_lite.sv",
"content": "`timescale 1ns / 1ps\nmodule ttc_counter_lite (\n input wire clk, // Clock signal\n input wire reset, // Reset signal\n input wire [3:0] axi_addr, // AXI address for read/write\n input wire [3... | [
{
"name": "specification.md",
"content": "# ttc_counter_lite Specification Document\n\n## Introduction\n\nThe **ttc_counter_lite** module implements a lightweight, programmable timer with support for **interval and single-shot counting modes**. It includes a 16-bit up-counter, configurable match and reload ... |
cvdp_copilot_bcd_adder_0007 | easy | Non-Agentic | Create a testbench to generate stimulus for the `bcd_adder` module, which performs Binary Coded Decimal (BCD) addition on two 4-bit inputs, a and b.
## Testbench Description
### Inputs
- Registers: a and b are 4-bit registers that provide the two BCD numbers to be added.
### Outputs
- The outputs from the BCD adder... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 95
}
] | bcd_adder | uut | [
{
"name": "bcd_adder.sv",
"content": "module bcd_adder( \n input [3:0] a, // 4-bit BCD input\n input [3:0] b, // 4-bit BCD input\n output [3:0] sum, // The corrected 4-bit BCD result of the addition\n ... | [] |
cvdp_copilot_apb_history_shift_register_0003 | medium | Non-Agentic | Create a test bench in SystemVerilog for a Verilog module named `APBGlobalHistoryRegister`. The register updates synchronously on every gated rising edge of the `history_shift_valid` clock, shifting in predicted outcomes or restoring history on mispredictions. The test bench should systematically generate input vectors... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 98
}
] | APBGlobalHistoryRegister | dut | [
{
"name": "APBGlobalHistoryRegister.v",
"content": "module APBGlobalHistoryRegister (\n // APB clock & reset\n input wire pclk,\n input wire presetn, // Active-low reset\n\n // APB signals\n input wire [9:0] paddr,\n input wire pselx,\n input wire ... | [] |
cvdp_copilot_ring_token_0004 | easy | Non-Agentic | Create a SystemVerilog testbench module named **`tb_token_ring_fsm`** that instantiates the `token_ring_fsm` module as the Unit Under Test (UUT). The testbench must include a **stimulus generator** that systematically drives various input conditions to achieve **100% code and functional coverage** for the `token_ring_f... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 100
}
] | token_ring_fsm | uut | [
{
"name": "token_ring_fsm.sv",
"content": "module token_ring_fsm (\n input logic clk, // Clock input\n input logic rst, // Reset input\n input logic [3:0] data_in, // Data input from node\n output reg [3:0] data_out, // Data output to node\n input logic has_dat... | [] |
cvdp_copilot_morse_code_0027 | easy | Non-Agentic | Complete the given partial SystemVerilog testbench `morse_encoder_tb`. The testbench must instantiate the `morse_encoder` **RTL** module and provide input stimulus for it, focusing exclusively on generating test vectors rather than building a full testbench.
The `morse_encoder` module converts an **8-bit ASCII input... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 95
}
] | morse_encoder | dut | [
{
"name": "morse_encoder.sv",
"content": "module morse_encoder (\n input wire [7:0] ascii_in, // ASCII input character\n output reg [5:0] morse_out, // Morse code output \n output reg [3:0] morse_length // Length of the Morse code sequence\n);\n\n always @(*) begin\n case (a... | [] |
cvdp_copilot_restoring_division_0006 | easy | Non-Agentic | Write a testbench to generate stimulus only for the `restoring_division` module, which performs restoring division on two unsigned positive integer inputs. The module generates the output `quotient`, `remainder`, and `valid` once the computation is completed for the given `dividend` and `divisor` when the `start` signa... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 95
}
] | restoring_division | uut | [
{
"name": "restore_division.sv",
"content": "`timescale 1ns / 1ps\n\nmodule restoring_division #(parameter WIDTH = 6) (\n input clk, // Clock signal\n input rst, // Reset signal (active low)\n input start, // Start signal to b... | [] |
cvdp_copilot_restoring_division_0034 | easy | Non-Agentic | Write a testbench to generate stimulus only for the `restoring_division` module, which performs restoring division on two unsigned positive integer inputs. The module produces the `quotient`, `remainder`, and asserts the `valid` signal upon computation completion. Additionally, it sets the `divisor_valid_result` flag t... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 95
}
] | restoring_division | uut | [
{
"name": "restore_division.sv",
"content": "`timescale 1ns / 1ps\nmodule restoring_division #(parameter WIDTH = 6) (\n input clk, // Clock signal\n input rst, // Reset signal (active low)\n input start, // Start s... | [] |
cvdp_copilot_microcode_sequencer_0028 | medium | Non-Agentic | Complete the given partial System Verilog Testbench `tb_microcode_sequencer`.The testbench must instantiate the `microcode_sequencer` RTL module and provide input stimulus for it, apply various input combinations representing different instructions and conditions such as resetting, fetching instructions, loading data, ... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 90
}
] | microcode_sequencer | uut | [
{
"name": "microcode_sequencer.sv",
"content": "module microcode_sequencer (\n // Inputs\n input logic clk, // Input Clock\n input logic c_n_in, // Input Carry for Carry Lookahead Adder\n input logic c_inc_in, // Input Carry for Carry Lookahead Program Counter Incrementer\n input logic r_en, // A... | [] |
cvdp_agentic_async_fifo_compute_ram_application_0004 | medium | Agentic | Create a test bench in SystemVerilog for a Verilog module named `async_fifo`. The **async_fifo** design is a parameterizable asynchronous FIFO module. It uses separate clock domains for writing and reading, providing safe data transfer between two clock domains. The design employs dual-port memory and Gray-coded pointe... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 90
},
{
"inst_name": "dut",
"metric": "Assertion",
"target_percentage": 100
},
{
"inst_name": "dut",
"metric": "Toggle",
"target_percentage": 90
},
{
"inst_name": "dut",
"metric": "Block",... | async_fifo | dut | [
{
"name": "async_fifo.sv",
"content": "module async_fifo\n #(\n parameter p_data_width = 32, // Parameter to define the width of the data\n parameter p_addr_width = 16 // Parameter to define the width of the address\n )(\n input wire i_wr_clk, // Write ... | [
{
"name": "fifo.md",
"content": "# Asynchronous FIFO Specification\n\n## 1. Overview\n\nThe **async_fifo** design is a parameterizable asynchronous FIFO module. It uses separate clock domains for writing and reading, providing safe data transfer between two clock domains. The design employs dual-port memory... |
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