Revisiting VerilogEval: Newer LLMs, In-Context Learning, and Specification-to-RTL Tasks
Paper • 2408.11053 • Published
problem_id stringlengths 11 29 | prompt stringlengths 211 2.97k | ref stringlengths 70 1.67k | test stringlengths 2.33k 9.09k |
|---|---|---|---|
Prob001_zero |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- output zero
The module should always outputs a LOW.
|
module RefModule (
output zero
);
assign zero = 1'b0;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
en... |
Prob002_m2014_q4i |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- output out
The module should always drive 0 (or logic low).
|
module RefModule (
output out
);
assign out = 1'b0;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int cl... |
Prob003_step_one |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- output one
The module should always drive 1 (or logic high).
|
module RefModule (
output one
);
assign one = 1'b1;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
en... |
Prob004_vector2 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (32 bits)
- output out (32 bits)
The module should reverse the byte order of a 32-bit vector.
|
module RefModule (
input [31:0] in,
output [31:0] out
);
assign out = {in[7:0], in[15:8], in[23:16], in[31:24]};
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [31:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(in... |
Prob005_notgate |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in
- output out
The module should implement a NOT gate.
|
module RefModule (
input in,
output out
);
assign out = ~in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0]... |
Prob006_vectorr |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (8 bits)
- output out (8 bits)
The module should reverse the bit ordering of the input port and write
the result to the output port.
|
module RefModule (
input [7:0] in,
output [7:0] out
);
assign {out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]} = in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [7:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(inpu... |
Prob007_wire |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in
- output out
The module should behave like a wire.
|
module RefModule (
input in,
output out
);
assign out = in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0]... |
Prob008_m2014_q4h |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in
- output out
The module should assign the output port to the same value as the input
port combinationally.
|
module RefModule (
input in,
output out
);
assign out = in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg in = 0
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
in <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_... |
Prob009_popcount3 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (3 bits)
- output out (2 bits)
The module should implement a "population count" circuit that counts the
number of '1's in the input vector.
|
module RefModule (
input [2:0] in,
output [1:0] out
);
assign out = in[0]+in[1]+in[2];
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [2:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(inpu... |
Prob010_mt2015_q4a |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input x
- input y
- output z
The module should implement the boolean function z = (x^y) & x.
|
module RefModule (
input x,
input y,
output z
);
assign z = (x^y) & x;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic x,
output logic y
);
always @(posedge clk, negedge clk)
{x, y} <= $random % 4;
initial begin
repeat(101) @(negedge clk);
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors... |
Prob011_norgate |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- output out
The module should implement a NOR gate.
|
module RefModule (
input a,
input b,
output out
);
assign out = ~(a | b);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg a, b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:... |
Prob012_xnorgate |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- output out
The module should implement an XNOR gate.
|
module RefModule (
input a,
input b,
output out
);
assign out = ~(a^b);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg a, b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:... |
Prob013_m2014_q4e |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in1
- input in2
- output out
The module should implement a 2-input NOR gate.
|
module RefModule (
input in1,
input in2,
output logic out
);
assign out = ~(in1 | in2);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic in1, in2
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
{in1, in2} <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
... |
Prob014_andgate |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- output out
The module should implement a 2-input AND gate.
|
module RefModule (
input a,
input b,
output out
);
assign out = a & b;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg a, b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:... |
Prob015_vector1 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (16 bits)
- output out_hi ( 8 bits)
- output out_lo ( 8 bits)
The module should implement a combinational circuit that splits an input
half-word (... |
module RefModule (
input [15:0] in,
output [7:0] out_hi,
output [7:0] out_lo
);
assign {out_hi, out_lo} = in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [15:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(in... |
Prob016_m2014_q4j |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input x (4 bits)
- input y (4 bits)
- output sum (5 bits)
Implement a 4-bit adder with full adders. The output sum should include
the overflow bit.
|
module RefModule (
input [3:0] x,
input [3:0] y,
output [4:0] sum
);
assign sum = x+y;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [3:0] x,y
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
{x,y} <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int... |
Prob017_mux2to1v |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a (100 bits)
- input b (100 bits)
- input sel
- output out (100 bits)
The module should implement a 2-1 multiplexer. When sel=0, choose a. When
se... |
module RefModule (
input [99:0] a,
input [99:0] b,
input sel,
output [99:0] out
);
assign out = sel ? b : a;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [99:0] a,b,
output logic sel,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
ta... |
Prob018_mux256to1 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (256 bits)
- input sel ( 8 bits)
- output out
The module should implement a 1-bit wide, 256-to-1 multiplexer. The 256
inputs are all packed into a ... |
module RefModule (
input [255:0] in,
input [7:0] sel,
output out
);
assign out = in[sel];
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [255:0] in,
output logic [7:0] sel
);
always @(posedge clk, negedge clk) begin
for (int i=0;i<8; i++)
in[i*32+:32] <= $random;
sel <= $random;
end
initial begin
repeat(1000) @(negedge clk);
$finis... |
Prob019_m2014_q4f |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in1
- input in2
- output out
The module should implement the following circuit in Verilog. Two inputs
(in1 and in2) go to an AND gate, but the in2 input... |
module RefModule (
input in1,
input in2,
output logic out
);
assign out = in1 & ~in2;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic in1, in2
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
{in1, in2} <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
... |
Prob020_mt2015_eq2 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input A (2 bits)
- input B (2 bits)
- output z
The module should implement a circuit that has two 2-bit inputs A[1:0]
and B[1:0], and produces an output z. Th... |
module RefModule (
input [1:0] A,
input [1:0] B,
output z
);
assign z = A[1:0]==B[1:0];
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
/*
Midterm 2015 Question 1k. 2-bit equality comparator.
*/
module stimulus_gen (
input clk,
output logic [1:0] A,
output logic [1:0] B
);
always @(posedge clk, negedge clk)
{A, B} <= $random % 16;
initial begin
repeat(1000) @(negedge clk);
#1 $fin... |
Prob021_mux256to1v |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (1024 bits)
- input sel ( 8 bits)
- output out ( 4 bits)
The module should implement a 4-bit wide, 256-to-1 multiplexer. The 256
4-bit inputs ar... |
module RefModule (
input [1023:0] in,
input [7:0] sel,
output [3:0] out
);
assign out = {in[sel*4+3], in[sel*4+2], in[sel*4+1], in[sel*4+0]};
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [1023:0] in,
output logic [7:0] sel
);
always @(posedge clk, negedge clk) begin
for (int i=0;i<32; i++)
in[i*32+:32] <= $random;
sel <= $random;
end
initial begin
repeat(1000) @(negedge clk);
$fin... |
Prob022_mux2to1 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- input sel
- output out
The module should implement a one-bit wide, 2-to-1 multiplexer. When
sel=0, choose a. When sel=1, choose b.
|
module RefModule (
input a,
input b,
input sel,
output out
);
assign out = sel ? b : a;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic a,b,sel,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(inpu... |
Prob023_vector100r |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (100 bits)
- output out (100 bits)
The module should reverse the bit ordering of the input and write to the
output.
|
module RefModule (
input [99:0] in,
output reg [99:0] out
);
always_comb
for (int i=0;i<$bits(out);i++)
out[i] = in[$bits(out)-i-1];
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [99:0] in
);
always @(posedge clk, negedge clk)
in <= {$random, $random, $random, $random};
initial begin
repeat(100) @(negedge clk);
$finish;
end
endmodule
module tb();
typedef struct packed {
i... |
Prob024_hadd |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- output sum
- output cout
The module should implement a half adder. A half adder adds two bits
(with no carry-in) and produces a sum and c... |
module RefModule (
input a,
input b,
output sum,
output cout
);
assign {cout, sum} = a+b;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic a,b
);
always @(posedge clk, negedge clk)
{a,b} <= $random;
initial begin
repeat(100) @(negedge clk);
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int... |
Prob025_reduction |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (8 bits)
- output parity
Parity checking is often used as a simple method of detecting errors when
transmitting data through an imperfect channel. ... |
module RefModule (
input [7:0] in,
output parity
);
assign parity = ^in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [7:0] in
);
initial begin
repeat(100) @(posedge clk, negedge clk)
in <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_parity;
int ... |
Prob026_alwaysblock1 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- output out_assign
- output out_alwaysblock
The module should implement an AND gate using both an assign statement
and a combinational alw... |
module RefModule (
input a,
input b,
output out_assign,
output reg out_alwaysblock
);
assign out_assign = a & b;
always @(*) out_alwaysblock = a & b;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg a, b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:... |
Prob027_fadd |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- input cin
- output cout
- output sum
The module should impement a full adder. A full adder adds three bits
(including carry-in) and pro... |
module RefModule (
input a,
input b,
input cin,
output cout,
output sum
);
assign {cout, sum} = a+b+cin;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic a,b,cin,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(inpu... |
Prob028_m2014_q4a |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input d
- input ena
- output q
The module should impement a D latch using an always block.
|
module RefModule (
input d,
input ena,
output logic q
);
always@(*) begin
if (ena)
q = d;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic d, ena
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
{d,ena} <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int ... |
Prob029_m2014_q4g |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in1
- input in2
- input in3
- output out
The module should impement the following circuit: A two-input XNOR
(connected to 'in1' and 'in2) has an outpu... |
module RefModule (
input in1,
input in2,
input in3,
output logic out
);
assign out = (~(in1 ^ in2)) ^ in3;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic in1, in2, in3
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
{in1, in2, in3} <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int er... |
Prob030_popcount255 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (255 bits)
- output out ( 8 bits)
A "population count" circuit counts the number of '1's in an input
vector. The module should implement a population... |
module RefModule (
input [254:0] in,
output reg [7:0] out
);
always_comb begin
out = 0;
for (int i=0;i<255;i++)
out = out + in[i];
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [254:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(i... |
Prob031_dff |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input d
- input q
The module should implement a single D flip-flop. Assume all sequential
logic is triggered on the positive edge of the clock.
|
module RefModule (
input clk,
input d,
output reg q
);
initial
q = 1'hx;
always @(posedge clk)
q <= d;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg d,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0... |
Prob032_vector0 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input vec (3 bits)
- output outv (3 bits)
- output o2
- output o1
- output o0
The module has one 3-bit input, then outputs the same vector, and also
splits ... |
module RefModule (
input [2:0] vec,
output [2:0] outv,
output o2,
output o1,
output o0
);
assign outv = vec;
assign {o2, o1, o0} = vec;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg [2:0] vec,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input... |
Prob033_ece241_2014_q1c |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a (8 bits)
- input b (8 bits)
- output s (8 bits)
- output overflow
Assume that you have two 8-bit 2's complement numbers, a[7:0] and b[7:0].
The modul... |
module RefModule (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
);
wire [8:0] sum = a+b;
assign s = sum[7:0];
assign overflow = !(a[7]^b[7]) && (a[7] != s[7]);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [7:0] a, b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(i... |
Prob034_dff8 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input d (8 bits)
- output q (8 bits)
The module should include 8 D flip-flops. All DFFs should be triggered by
the positive edge of clock.
|
module RefModule (
input clk,
input [7:0] d,
output reg [7:0] q
);
initial
q = 8'h0;
always @(posedge clk)
q <= d;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg [7:0] d,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input... |
Prob035_count1to10 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- output q (4 bits)
The module should implement a decade counter that counts 1 through 10,
inclusive. Assume all sequential logic is t... |
module RefModule (
input clk,
input reset,
output reg [3:0] q
);
always @(posedge clk)
if (reset || q == 10)
q <= 1;
else
q <= q+1;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg reset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3... |
Prob036_ringer |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input ring
- input vibrate_mode
- output ringer
- output motor
The module should implement a circuit to control a cellphone's ringer and
vibration motor. Whe... |
module RefModule (
input ring,
input vibrate_mode,
output ringer,
output motor
);
assign ringer = ring & ~vibrate_mode;
assign motor = ring & vibrate_mode;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg ring, vibrate_mode,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_st... |
Prob037_review2015_count1k |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- output q (10 bits)
The module should implement a counter that counts from 0 to 999,
inclusive, with a period of 1000 cycles. Assume ... |
module RefModule (
input clk,
input reset,
output reg [9:0] q
);
always @(posedge clk)
if (reset || q == 999)
q <= 0;
else
q <= q+1;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg reset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) ... |
Prob038_count15 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- output q (4 bits)
The module should implement a 4-bit binary counter that counts from 0
through 15, inclusive, with a period of 16. ... |
module RefModule (
input clk,
input reset,
output reg [3:0] q
);
always @(posedge clk)
if (reset)
q <= 0;
else
q <= q+1;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg reset,
input tb_match,
output reg wavedrom_enable,
output reg[511:0] wavedrom_title
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedr... |
Prob039_always_if |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- input sel_b1
- input sel_b2
- output out_assign
- output out_always
The module should implement a 2-to-1 mux that chooses between a a... |
module RefModule (
input a,
input b,
input sel_b1,
input sel_b2,
output out_assign,
output reg out_always
);
assign out_assign = (sel_b1 & sel_b2) ? b : a;
always @(*) out_always = (sel_b1 & sel_b2) ? b : a;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic a,b,sel_b1, sel_b2,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom... |
Prob040_count10 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- output q (4 bits)
The module should implement a decade counter that counts from 0 through
9, inclusive, with a period of 10. Assume ... |
module RefModule (
input clk,
input reset,
output reg [3:0] q
);
always @(posedge clk)
if (reset || q == 9)
q <= 0;
else
q <= q+1;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg reset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3... |
Prob041_dff8r |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- input d (8 bits)
- output q (8 bits)
The module should include 8 D flip-flops with active high synchronous
reset setting the outpu... |
module RefModule (
input clk,
input [7:0] d,
input reset,
output reg [7:0] q
);
always @(posedge clk)
if (reset)
q <= 0;
else
q <= d;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg [7:0] d, output reg reset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom... |
Prob042_vector4 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (8 bits)
- output out (32 bits)
One common place to see a replication operator is when sign-extending a
smaller number to a larger one, while preserv... |
module RefModule (
input [7:0] in,
output [31:0] out
);
assign out = { {24{in[7]}}, in };
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [7:0] in
);
initial begin
repeat(100) @(posedge clk, negedge clk)
in <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int err... |
Prob043_vector5 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- input c
- input d
- input e
- output out (25 bits)
Implement a module that given five 1-bit signals (a, b, c, d, and e),
compute all... |
module RefModule (
input a,
input b,
input c,
input d,
input e,
output [24:0] out
);
assign out = ~{ {5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}} } ^ {5{a,b,c,d,e}};
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic a, b, c, d, e
);
initial begin
repeat(100) @(posedge clk, negedge clk)
{a,b,c,d,e} <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_... |
Prob044_vectorgates |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a (3 bits)
- input b (3 bits)
- output out_or_bitwise (3 bits)
- output out_or_logical
- output out_not (6 bits)
Impl... |
module RefModule (
input [2:0] a,
input [2:0] b,
output [2:0] out_or_bitwise,
output out_or_logical,
output [5:0] out_not
);
assign out_or_bitwise = a | b;
assign out_or_logical = a || b;
assign out_not = {~b,~a};
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg [2:0] a, b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(inpu... |
Prob045_edgedetect2 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input in (8 bits)
- input anyedge (8 bits)
Implement a module that for each bit in an 8-bit input vector, detect
when the input signal changes ... |
module RefModule (
input clk,
input [7:0] in,
output reg [7:0] anyedge
);
reg [7:0] d_last;
always @(posedge clk) begin
d_last <= in;
anyedge <= in ^ d_last;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
input tb_match,
output reg [7:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wa... |
Prob046_dff8p |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- input d (8 bits)
- output q (8 bits)
Implement a module that includes 8 D flip-flops with active high
synchronous reset. The flip-... |
module RefModule (
input clk,
input [7:0] d,
input reset,
output reg [7:0] q
);
always @(negedge clk)
if (reset)
q <= 8'h34;
else
q <= d;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg [7:0] d, output reg reset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom... |
Prob047_dff8ar |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input areset
- input d (8 bits)
- output q (8 bits)
The module should include 8 D flip-flops with active high asynchronous
reset. The ... |
module RefModule (
input clk,
input [7:0] d,
input areset,
output reg [7:0] q
);
always @(posedge clk, posedge areset)
if (areset)
q <= 0;
else
q <= d;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg [7:0] d, output areset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
reg reset;
assign areset = reset;
// Add two ports to module stimulus_gen:
// output [511:0] wavedr... |
Prob048_m2014_q4c |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input d
- input r
- output q
The module should implement a simple D flip flop with active high
synchronous reset (reset output to 0).
|
module RefModule (
input clk,
input d,
input r,
output logic q
);
always@(posedge clk) begin
if (r)
q <= 0;
else
q <= d;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic d, r
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
{d,r} <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int erro... |
Prob049_m2014_q4b |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input ar
- input d
- output q
The module should implement a D flip flop, positive edge triggered, with
an asynchronous reset "ar".
|
module RefModule (
input clk,
input d,
input ar,
output logic q
);
always@(posedge clk or posedge ar) begin
if (ar)
q <= 0;
else
q <= d;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic d, ar
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
{d,ar} <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int er... |
Prob050_kmap1 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- input c
- output out
The module should implement the circuit described by the Karnaugh map
below.
a
bc 0 1
00 | 0 |... |
module RefModule (
input a,
input b,
input c,
output out
);
assign out = (a | b | c);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg a, b, c,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[5... |
End of preview. Expand in Data Studio
VerilogEvalv2 spec-to-rtl dataset from the VerilogEval paper. Paper: Revisiting VerilogEval: Newer LLMs, In-Context Learning, and Specification-to-RTL Tasks Repo: https://github.com/NVlabs/verilog-eval).
Disclaimer: I am not the original author and uploaded this here only for convenience! Please refer to the original repo for any information.
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