| # A lot of slew in asap7/sram-64x16 |
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| Tool: Clock Tree Synthesis |
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| Subcategory: Timing analysis issue |
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| ## Conversation |
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| ### oharboe |
| Is this amount of slew expected on the clock pin to the SRAM?
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| `SRAM2RW16x32_2/CE2` is one of two clocks to the SRAM, the SRAM has one read and one write port.
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| ```
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| make DESIGN_CONFIG=designs/asap7/sram-64x16/config.mk
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| ```
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| ```
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| >>> report_checks -path_delay max -fields {slew net cap} -to _351_/D
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| Startpoint: SRAM2RW16x32_2 (rising edge-triggered flip-flop clocked by io_clk)
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| Endpoint: _351_ (falling edge-triggered flip-flop clocked by io_clk')
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| Path Group: io_clk
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| Path Type: max
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| Fanout Cap Slew Delay Time Description
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| -----------------------------------------------------------------------------
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| 0.00 0.00 clock io_clk (rise edge)
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| 241.44 241.44 clock network delay (propagated)
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| 150.83 0.00 241.44 ^ SRAM2RW16x32_2/CE2 (SRAM2RW16x32)
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| 40.24 202.07 443.51 v SRAM2RW16x32_2/O2[4] (SRAM2RW16x32)
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| 1 9.73 _SRAM2RW16x32_2_O2[4] (net)
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| 53.97 5.14 448.65 v _351_/D (DFFLQNx1_ASAP7_75t_R)
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| 448.65 data arrival time
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| 500.00 500.00 clock io_clk' (fall edge)
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| 186.47 686.47 clock network delay (propagated)
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| 0.52 686.99 clock reconvergence pessimism
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| 686.99 v _351_/CLK (DFFLQNx1_ASAP7_75t_R)
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| -22.88 664.11 library setup time
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| 664.11 data required time
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| -----------------------------------------------------------------------------
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| 664.11 data required time
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| -448.65 data arrival time
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| -----------------------------------------------------------------------------
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| 215.46 slack (MET)
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| ```
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| ### maliberty |
| Probably not but without a test case not much more can be said. |
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| ### oharboe |
| `make DESIGN_CONFIG=designs/asap7/sram-64x16/config.mk issue_cts` standalone testcase:
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| 1. Unzip (note! bzip2 compression so that it would fit into github limit) [slew.zip](https://github.com/The-OpenROAD-Project/OpenROAD/files/12294012/slew.zip)
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| 2. run `./run*.sh`
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| 3. Enter `report_checks -path_delay max -fields {slew net cap} -to _351_/D` in the GUI
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| You should get:
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| ```
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| >>> report_checks -path_delay max -fields {slew net cap} -to _351_/D
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| Startpoint: SRAM2RW16x32_2 (rising edge-triggered flip-flop clocked by io_clk)
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| Endpoint: _351_ (falling edge-triggered flip-flop clocked by io_clk')
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| Path Group: io_clk
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| Path Type: max
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| Fanout Cap Slew Delay Time Description
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| -----------------------------------------------------------------------------
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| 0.00 0.00 clock io_clk (rise edge)
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| 274.66 274.66 clock network delay (propagated)
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| 186.64 0.00 274.66 ^ SRAM2RW16x32_2/CE2 (SRAM2RW16x32)
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| 35.53 205.56 480.22 v SRAM2RW16x32_2/O2[4] (SRAM2RW16x32)
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| 1 7.54 _SRAM2RW16x32_2_O2[4] (net)
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| 47.76 5.26 485.49 v _351_/D (DFFLQNx1_ASAP7_75t_R)
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| 485.49 data arrival time
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| 500.00 500.00 clock io_clk' (fall edge)
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| 212.33 712.33 clock network delay (propagated)
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| 0.00 712.33 clock reconvergence pessimism
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| 712.33 v _351_/CLK (DFFLQNx1_ASAP7_75t_R)
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| -21.20 691.13 library setup time
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| 691.13 data required time
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| -----------------------------------------------------------------------------
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| 691.13 data required time
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| -485.49 data arrival time
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| -----------------------------------------------------------------------------
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| 205.64 slack (MET)
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| ```
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| ### maliberty |
| Converted to an issue https://github.com/The-OpenROAD-Project/OpenROAD/issues/3817 |
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