| # How do I find and view the nets that are causing hold and setup violations? |
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| Tool: OpenSTA |
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| Subcategory: Timing analysis |
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| ## Conversation |
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| ### oharboe |
| It want to find and view nets that cause hold violations.
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| Today I have to wait and hope for a global routing failure to be able to view the nets that cause hold violations in DRC viewer there.
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| ```
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| Repair setup and hold violations...
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| TNS end percent 5
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| [INFO RSZ-0041] Resized 2 instances.
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| [WARNING RSZ-0062] Unable to repair all setup violations.
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| [INFO RSZ-0046] Found 2957 endpoints with hold violations.
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| [INFO RSZ-0032] Inserted 40106 hold buffers.
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| Placement Analysis
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| ```
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| ### vvbandeira |
| ```tcl
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| find_timing_paths -path_delay min -slack_max 0
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| ```
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| @oharboe, Would this work for you?
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| Note that RSZ just said it had found `2957` hold violations; after inserting the `40106` buffers, there's no warning.
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| So it is likely that all have been fixed -- see the warning in the line above for a contrast about setup violations.
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| For setup you would do:
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| ```tcl
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| find_timing_paths -path_delay max -slack_max 0
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| ``` |
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| ### oharboe |
| Found an approach... Here is what I did:
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| 1. create some hold failures by reducing the clock period from 2000 to 1000ps in mock-array, using diff below.
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| 2. There are no timing violations in placement, the timing violations happen after CTS.
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| 3. Modify cts.tcl to write out an ODB file *before* hold cells are inserted and the design is repair. Post repair in CTS there are no violations.
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| Now I can run commands to examine minimum hold time violations, which will lead to hold cells being inserted.
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| ```
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| report_checks -path_delay min
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| Startpoint: io_insRight_0[61] (input port clocked by clock)
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| Endpoint: ces_0_0 (rising edge-triggered flip-flop clocked by clock)
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| Path Group: clock
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| Path Type: min
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| Delay Time Description
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| ---------------------------------------------------------
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| 0.00 0.00 clock clock (rise edge)
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| 0.00 0.00 clock network delay (propagated)
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| 200.00 200.00 ^ input external delay
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| 0.00 200.00 ^ io_insRight_0[61] (in)
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| 10.45 210.45 ^ input1082/Y (BUFx2_ASAP7_75t_R)
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| 0.04 210.48 ^ ces_0_0/io_ins_right[61] (Element)
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| 210.48 data arrival time
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| 0.00 0.00 clock clock (rise edge)
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| 337.72 337.72 clock network delay (propagated)
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| 0.00 337.72 clock reconvergence pessimism
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| 337.72 ^ ces_0_0/clock (Element)
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| 102.40 440.11 library hold time
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| 440.11 data required time
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| ---------------------------------------------------------
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| 440.11 data required time
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| -210.48 data arrival time
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| ---------------------------------------------------------
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| -229.63 slack (VIOLATED)
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| ```
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| ```
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| foreach path [find_timing_paths -slack_max 0 -group_count 10 -path_delay min] {puts "[get_property $path slack] [get_property [get_property $path endpoint] full_name]"}
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| -229.630280 ces_0_0/io_ins_right[61]
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| -229.599152 ces_0_0/io_ins_right[3]
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| -229.596451 ces_0_0/io_ins_right[56]
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| -229.570663 ces_0_0/io_ins_right[51]
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| -229.570786 ces_0_0/io_ins_right[53]
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| -229.568649 ces_0_0/io_ins_right[1]
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| -229.561371 ces_0_0/io_ins_right[14]
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| -229.517380 ces_0_0/io_ins_right[30]
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| -229.512604 ces_0_0/io_ins_right[5]
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| -229.509186 ces_7_0/io_ins_right[61]
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| ```
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| ```
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| diff --git a/flow/designs/asap7/mock-array/Element/constraints.sdc b/flow/designs/asap7/mock-array/Element/constraints.sdc
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| index be545b8f..0a66e62e 100644
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| --- a/flow/designs/asap7/mock-array/Element/constraints.sdc
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| +++ b/flow/designs/asap7/mock-array/Element/constraints.sdc
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| @@ -4,7 +4,7 @@ set cols [expr {[info exists ::env(MOCK_ARRAY_COLS)] ? $::env(MOCK_ARRAY_COLS) :
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| set clk_name clock
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| set clk_port_name clock
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| -set clk_period 2000
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| +set clk_period 1000
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| set clk_port [get_ports $clk_port_name]
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| create_clock -period $clk_period -waveform [list 0 [expr $clk_period / 2]] -name $clk_name $clk_port
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| diff --git a/flow/designs/asap7/mock-array/constraints.sdc b/flow/designs/asap7/mock-array/constraints.sdc
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| index 5d33c792..46b20e5b 100644
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| --- a/flow/designs/asap7/mock-array/constraints.sdc
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| +++ b/flow/designs/asap7/mock-array/constraints.sdc
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| @@ -1,6 +1,6 @@
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| set sdc_version 2.0
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| -set clk_period 2000
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| +set clk_period 1000
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| create_clock [get_ports clock] -period $clk_period -waveform [list 0 [expr $clk_period/2]]
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| set clk_name clock
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| diff --git a/flow/scripts/cts.tcl b/flow/scripts/cts.tcl
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| index 0b7c56b8..2c0c6fef 100644
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| --- a/flow/scripts/cts.tcl
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| +++ b/flow/scripts/cts.tcl
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| @@ -45,6 +45,8 @@ estimate_parasitics -placement
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| report_metrics "cts pre-repair"
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| utl::pop_metrics_stage
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| +write_db $::env(RESULTS_DIR)/4_1_cts_pre_repair.odb
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| +
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| repair_clock_nets
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| utl::push_metrics_stage "cts__{}__post_repair"
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| ```
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| ### oharboe |
| `make gui_cts` ctrl-f and searching for instance `*hold*` is helpful. :-)
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| From there I can go to the buffer tree, then find the endpoints.
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| ### maliberty |
| Various useful patterns at https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/2734e98ee7c0f6888a686c2ef2445c0bb837ed0f/flow/scripts/save_images.tcl#L59 |
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