| # How can I go from timing reports to Verilog? |
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| Tool: OpenSTA |
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| Subcategory: Tracing timing paths |
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| ## Conversation |
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| ### oharboe |
| I have a timing path in the OpenROAD GUI that I want to understand.
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| How can I go from the timing report in the GUI to the Verilog? |
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| ### maliberty |
| https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/pull/1129 should help with naming once merged.
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| There is no direct link today so you'll have to work back from the names. @QuantamHD has some work to store line numbers that is hopefully going to land but has been tied up in OSS licensing issues. |
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| ### oharboe |
| @maliberty Here is an example of how it is hard to get from the static timing report to the Verilog:
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| Build the design with ` make DESIGN_CONFIG=designs/asap7/mock-array-big/config.mk`, then look at the Element `make DESIGN_CONFIG=designs/asap7/mock-array-big/Element/config.mk gui_final`.
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| How, in general, do I find my way to the Verilog code?
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| ### maliberty |
| If you use the rename PR I mentioned then the register should have a name matching the Element.v to some degree. Does that work here? |
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| ### oharboe |
| What I've heard is that tracking from timing reports back to RTL is an "unsolved problem in EDA tools", so https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/pull/1129 is probably as good as it gets for now.
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| To go beyond this, I suppose Yosys has to grow some sophistication w.r.t. tracking back to the original Verilog.
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| One of the goals of https://circt.llvm.org/ is to provide an improved infrastructure for RTL as it goes through a number of tools in a flow. Perhaps, one day, yosys will support https://circt.llvm.org/. Ideally this would give Yosys more input languages and better "debug information" through synthesis and technology mapping... |
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