| # How can I find the net for a wire? |
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| Tool: Graphical User Interface |
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| Subcategory: Usage question |
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| ## Conversation |
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| ### oharboe |
| I am currently dealing with an issue related to unexpected congestion in a design that has me stumped. It appears that there might be incorrect constraints on some I/O pins of a macro.
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| When I try to probe deeper into the congested area by clicking on the wires, the details provided are fairly vague – something along the lines of "wire4940/A". I'm led to believe that this wire is simply a segment of a larger net.
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| Ideally, I would be able to trace this wire segment back to its origin and endpoint within the RTL design, which would help me identify the exact register/pin it connects from and to. However, I'm unsure of how to proceed with this.
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| ### rovinski |
| `wire4940/A` is an iTerm (instance terminal) meaning that `wire4940` is the name of a cell, not a wire segment. I believe `wire####` is the generated name for buffers which are inserted due to max wirelength targets.
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| The net that you have selected is connecting two iTerms, most likely buffers.
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| There should be a GUI display item called "Buffer Tree" which should show you what you want. See #2781 and #2824 for discussion. |
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| ### maliberty |
| wireXXX will be part of multiple nets and they will be show next to the iterm name.
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| Buffer tree only shows up if one is detected. To detect buffers we need the liberty to be loaded. If you used GUI_NO_TIMING=1 then it will not appear. |
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| ### oharboe |
| Works very well!
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| When I click on the buffer tree, I get the terminals (endpoints), which I can relate to my Verilog easily.
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