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Datasets:
OvertureMMXXI
/
HDL-RepoBench-Sample
like
0
Tasks:
Text Generation
Languages:
code
Size:
1K<n<10K
Tags:
hardware
verilog
systemverilog
vhdl
chisel
hls
+ 1
License:
other
Dataset card
Data Studio
Files
Files and versions
xet
Community
main
HDL-RepoBench-Sample
/
systemverilog
/
test_content_classfied.jsonl
Commit History
Upload HDL-RepoBench sample
d6720f3
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OvertureMMXXI
commited on
2 days ago
OvertureMMXXI commited on 