abstract stringlengths 1 4.43k | claims stringlengths 14 189k | description stringlengths 5 1.46M |
|---|---|---|
A memory module system with a global shared context. A memory module system can include a plurality of memory modules and at least one processor, which can implement the global shared context. The memory modules of the system can provide the global shared context at least in part by providing an address space shared be... |
1.A system including:A plurality of memory modules connected to provide physical memory, and the memory modules of the plurality of memory modules include:A plurality of partitions of the physical memory, wherein a partition of the plurality of partitions is associated with at least one physical memory address; andThe... |
Memory module system using global shared contextTechnical fieldAt least some embodiments disclosed herein relate to a memory module system that utilizes a global shared context.Background techniqueSome conventional examples of memory modules may include single in-line memory modules (SIMM) and dual in-line memory modu... |
A finite state machine (115) is provided that both serializes virtual GPIO signals (135) and messaging signals (136) and that deserializes virtual GPIO signals and the messaging signals. The finite state machine frames the serialized virtual GPIO signals and messaging signals into frames each demarcated by a start bit ... |
1.An integrated circuit comprising:First processor;a plurality of messaging signal registers, wherein the first processor is configured to write a transmit set of messaging signals into the messaging signal register;Multiple GPIO pins;a GPIO interface configured to receive a first set of signals from the first process... |
Hybrid virtual GPIORelated applicationThis application claims the benefit of U.S. Provisional Patent Application Serial No. 61/982, file, filed on Apr The entire contents of the application are hereby incorporated by reference in its entirety.Technical fieldThis application relates to general purpose input/output (GPI... |
"Aspects described herein include devices, wireless communication apparatuses, methods, and associat(...TRUNCATED) | "\nCLAIMSWhat is claimed is:1. A wireless communication apparatus, comprising: a millimeter wave (mm(...TRUNCATED) | "\nHEATSINK FOR MILLIMETER WAVE (MMW) AND NON-MMW ANTENNA INTEGRATIONFIELD[0001] The present disclos(...TRUNCATED) |
"Various embodiments include methods and devices for managing optional commands. Some embodiments ma(...TRUNCATED) | "\nCLAIMSWhat is claimed is:1. A method performed in a processor of a computing device, comprising: (...TRUNCATED) | "\nRead Optional And Write Optional CommandsRELATED APPLICATIONS[0001] This application claims the b(...TRUNCATED) |
"Integrated circuits and methods of manufacturing such circuits are disclosed herein that feature me(...TRUNCATED) | "\nCLAIMS1. A method of manufacturing an integrated circuit, the method comprising:performing routin(...TRUNCATED) | "\nMITIGATING ELEC TROMIGRATION, IN-RUSH CURRENT EFFECTS, IR-VOLTAGE DROP, AND JITTER THROUGH METALL(...TRUNCATED) |
"Reducing memory fragmentation. Memory is allocated during a preboot phase of a computer system, whe(...TRUNCATED) | "\n1.A method for reducing memory segmentation includes:The firmware module is allocated memory duri(...TRUNCATED) | "\nMethod, equipment and system for reducing memory segmentationTechnical fieldEmbodiments of the pr(...TRUNCATED) |
"A method, apparatus, and system are described for rasterizing a triangle. Pixel parameter values ar(...TRUNCATED) | "\nWhat is claimed is: 1. A method of rasterization using a tile-based digital differential analyzer(...TRUNCATED) | "\nThe present application is a continuation-in-part (CIP) based on and claims priority from U.S. pa(...TRUNCATED) |
"III-N semiconductor-on-silicon integrated circuit structures and techniques are disclosed. In some (...TRUNCATED) | "\n CLAIMS What is claimed is: 1. An integrated circuit comprising: a crystalline silicon substrat(...TRUNCATED) | "\n III-N SEMICONDUCTOR-ON-SILICON STRUCTURES AND TECHNIQUES BACKGROUND Integrated circuit (IC) desi(...TRUNCATED) |
"Embodiments of a silicon-on-insulator (SOI) wafer having an etch stop layer (130) overlying the bur(...TRUNCATED) | "\nCLAIMS What is claimed is: 1. A method comprising forming an etch stop layer in a silicon-on-insu(...TRUNCATED) | "\nMETHOD FOR MANUFACTURING A SILICON-ON-INSULATOR (SOI) WAFERWITH AN ETCH STOP LAYERFIELD OF THE IN(...TRUNCATED) |
"An apparatus is described. The apparatus includes a memory controller to interface with a multi-lev(...TRUNCATED) | "\nClaims1. An apparatus, comprising:a memory controller to interface with a multi-level system memo(...TRUNCATED) | "\nMEMORY CONTROLLER FOR MULTI-LEVEL SYSTEM MEMORY HAVINGSECTORED CACHEField of InventionThe field o(...TRUNCATED) |
End of preview. Expand in Data Studio
No dataset card yet
- Downloads last month
- 17