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## Summary
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RuC is a grammar-driven, rule-selectable benchmark generator that automatically produces RTL code-completion tasks from a set of input hardware description sources. It uses the target HDL grammar to mask syntactically defined code regions and prompts a model to regenerate them using the surrounding unmasked code as context.
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RuC-datasets is a collection of design datasets processed with the RuC framework and used for the experimentations in the paper.
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Although RuC-cve2_b72358c7-32k and RuC-tt07-32k share the same schema and preprocessing steps, they originate from different base datasets and should be treated as separate datasets.
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## Datasets structure
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Each project inside both datasets contains:
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- <top_module>.sv for cve2 or <top_module>.v for tt07
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Verilog or SystemVerilog hardware design named after the top-level module.
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- mask_idx.json
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Indices of selected rule occurrences used for RuC.
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- all_mask_idx.json
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Full set of candidate rule occurrences eligible for masking.
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## Datasets creation
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Both datasets computed mask_idx.json and all_mask_idx.json using RuC as explained in the paper.
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### RuC-tt07-32k
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NotSoTiny shuttle tt07 (https://huggingface.co/datasets/HPAI-BSC/NotSoTiny-25-12) filtered to keep designs that contain less than 32000 tokens.
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### RuC-cve2_b72358c7-32k
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CVE2 is an industry-grade RISC-V core maintained by OpenHWGroup. CVE2 codebase preprocessed using vppreproc and filtered to keep designs that contain less than 32000 tokens.
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## Datasets usage
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This datasets are intended to use together with the RuC framework (https://github.com/HPAI-BSC/RuC) to directly perform inference and evaluation on different LLMs.
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---
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license: apache-2.0
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