LLMs for Chip Design
Collection
Benchmarks, datasets and other resources related with LLM models tuned for chip design. • 6 items • Updated • 2
Search is not available for this dataset
module_program_interface_instantiation list | continuous_assign list | blocking_assignment list | nonblocking_assignment list | case_statement list | conditional_statement list | always_construct list | parameter_declaration list | ansi_port_declaration list |
|---|---|---|---|---|---|---|---|---|
[
[
725,
813
]
] | [
[
817,
845
],
[
848,
902
],
[
905,
933
],
[
936,
964
],
[
967,
995
],
[
998,
1026
],
[
1029,
1058
],
[
1061,
1090
],
[
1093,
1122
],
[
1125,
1154
],
[
1158,
1179
],
[
1932,
198... | [] | [
[
1743,
1760
],
[
1767,
1790
],
[
1816,
1857
],
[
1864,
1920
]
] | [] | [
[
1719,
1928
]
] | [
[
1676,
1928
]
] | [
[
1411,
1441
]
] | [
[
152,
199
],
[
204,
252
],
[
257,
303
],
[
308,
355
],
[
360,
440
],
[
445,
533
],
[
538,
574
],
[
579,
632
],
[
1444,
1477
],
[
1460,
1477
],
[
1480,
1535
],
[
1508,
1535
]... |
[
[
725,
813
]
] | [
[
2468,
2511
],
[
905,
933
],
[
848,
902
]
] | null | [
[
1816,
1857
],
[
1767,
1790
],
[
1743,
1760
]
] | null | [
[
1719,
1928
]
] | [
[
1676,
1928
]
] | [
[
1411,
1441
]
] | [
[
1480,
1535
],
[
1606,
1626
],
[
152,
199
]
] |
YAML Metadata Warning:empty or missing yaml metadata in repo card
Check out the documentation for more information.
Summary
RuC is a grammar-driven, rule-selectable benchmark generator that automatically produces RTL code-completion tasks from a set of input hardware description sources. It uses the target HDL grammar to mask syntactically defined code regions and prompts a model to regenerate them using the surrounding unmasked code as context.
Paper: https://arxiv.org/abs/2604.27780
RuC-datasets is a collection of design datasets processed with the RuC framework and used for the experimentations in the paper. Although RuC-cve2_b72358c7-32k and RuC-tt07-32k share the same schema and preprocessing steps, they originate from different base datasets and should be treated as separate datasets.
Datasets structure
Each project inside both datasets contains:
- .sv for cve2 or .v for tt07 Verilog or SystemVerilog hardware designs named after the top-level module.
- mask_idx.json Indices of selected rule occurrences used for RuC.
- all_mask_idx.json Full set of candidate rule occurrences eligible for masking.
Dataset creation
Both datasets computed mask_idx.json and all_mask_idx.json using RuC as explained in the paper.
RuC-tt07-32k
NotSoTiny shuttle tt07 (https://huggingface.co/datasets/HPAI-BSC/NotSoTiny-25-12) filtered to keep designs that contain less than 32000 tokens.
RuC-cve2_b72358c7-32k
CVE2 is an industry-grade RISC-V core maintained by OpenHWGroup. The CVE2 codebase preprocessed using vppreproc and filtered to keep designs that contain less than 32000 tokens.
Datasets usage
These datasets are intended to be used together with the RuC framework (https://github.com/HPAI-BSC/RuC) to directly perform inference and evaluation with different LLMs.
license: apache-2.0
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