ID string | Name string | Abstraction string | Structure string | Status string | Description string | ExtendedDescription string | ApplicablePlatforms list | AlternateTerms list | ModesOfIntroduction list | CommonConsequences list | PotentialMitigations list | ObservedExamples list | AffectedResources sequence | TaxonomyMappings list | RelatedAttackPatterns sequence | References list | Notes list | ContentHistory list | MappingNotes_Usage string | MappingNotes_Rationale string | MappingNotes_Comments string | MappingNotes_Reasons sequence | MappingNotes_Suggestions list | RelatedWeaknesses list | WeaknessOrdinalities list | DetectionMethods list | DemonstrativeExamples list | FunctionalAreas sequence | Diagram string | LikelihoodOfExploit string | BackgroundDetails sequence | NumPaths int64 | Paths sequence | Children sequence |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
284 | Improper Access Control | Pillar | Simple | Incomplete | The product does not restrict or incorrectly restricts access to a resource from an unauthorized actor. |
Access control involves the use of several protection mechanisms such as:
- Authentication (proving the identity of an actor)
- Authorization (ensuring that a given actor can access a resource), and
- Accountability (tracking of activities that were performed)
When any mechanism is not applied or otherwise... | [
{
"Class": "Not Technology-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Technology"
},
{
"Class": "ICS/OT",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Technology"
}
] | [
{
"Description": "The terms \"access control\" and \"authorization\" are often used interchangeably, although many people have distinct definitions. The CWE usage of \"access control\" is intended as a general term for the various mechanisms that restrict which users can access which resources, and \"authorizat... | [
{
"Note": null,
"Phase": "Architecture and Design"
},
{
"Note": "REALIZATION: This weakness is caused during implementation of an architectural security tactic.",
"Phase": "Implementation"
},
{
"Note": null,
"Phase": "Operation"
}
] | [
{
"Impact": [
"Varies by Context"
],
"Likelihood": null,
"Note": null,
"Scope": [
"Other"
]
}
] | [
{
"Description": "Very carefully manage the setting, management, and handling of privileges. Explicitly manage trust zones in the software.",
"Effectiveness": null,
"EffectivenessNotes": null,
"MitigationID": "MIT-1",
"Phase": [
"Architecture and Design",
"Operation"
],
"Stra... | [
{
"Description": "A form hosting website only checks the session authentication status for a single form, making it possible to bypass authentication when there are multiple forms",
"Link": "https://www.cve.org/CVERecord?id=CVE-2022-24985",
"Reference": "CVE-2022-24985"
},
{
"Description": "Acce... | [
"File or Directory"
] | [
{
"EntryID": null,
"EntryName": "Access Control List (ACL) errors",
"MappingFit": null,
"TaxonomyName": "PLOVER"
},
{
"EntryID": "2",
"EntryName": "Insufficient Authorization",
"MappingFit": null,
"TaxonomyName": "WASC"
},
{
"EntryID": null,
"EntryName": "Missing Acce... | [
"19",
"441",
"478",
"479",
"502",
"503",
"536",
"546",
"550",
"551",
"552",
"556",
"558",
"562",
"563",
"564",
"578"
] | [
{
"Authors": [
"Michael Howard",
"David LeBlanc"
],
"Edition": "2nd Edition",
"ExternalReferenceID": "REF-7",
"Publication": null,
"PublicationDay": "04",
"PublicationMonth": "12",
"PublicationYear": "2002",
"Publisher": "Microsoft Press",
"Section": "Chapter 6, \... | [
{
"Note": "\n\nThis entry needs more work. Possible sub-categories include:\n\n\n - Trusted group includes undesired entities (partially covered by CWE-286)\n\n - Group can perform undesired actions\n\n - ACL parse error does not fail closed\n\n",
"Type": "Maintenance"
}
] | [
{
"ContributionComment": null,
"ContributionDate": null,
"ContributionName": null,
"ContributionOrganization": null,
"ContributionReleaseDate": null,
"ContributionType": null,
"ContributionVersion": null,
"Date": null,
"ModificationComment": null,
"ModificationDate": null,
... | Discouraged | CWE-284 is extremely high-level, a Pillar. Its name, "Improper Access Control," is often misused in low-information vulnerability reports [REF-1287] or by active use of the OWASP Top Ten, such as "A01:2021-Broken Access Control". It is not useful for trend analysis. | Consider using descendants of CWE-284 that are more specific to the kind of access control involved, such as those involving authorization (Missing Authorization (CWE-862), Incorrect Authorization (CWE-863), Incorrect Permission Assignment for Critical Resource (CWE-732), etc.); authentication (Missing Authentication (... | [
"Frequent Misuse",
"Abstraction"
] | [
{
"Comment": "Missing Authorization",
"CweID": "862"
},
{
"Comment": "Incorrect Authorization",
"CweID": "863"
},
{
"Comment": "Incorrect Permission Assignment for Critical Resource",
"CweID": "732"
},
{
"Comment": "Missing Authentication",
"CweID": "306"
},
{
"Co... | [] | null | null | null | null | null | null | null | 1 | [
[
"284"
]
] | [
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"1270",
"1274",
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"1280",
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"1290",
"1292",
"1294",
"1296",
"1304",
"1311",
"1312",
"1313",
"1315",
"1316",
"1317",
"1320",
"1323"... |
1191 | On-Chip Debug and Test Interface With Improper Access Control | Base | Simple | Stable | The chip does not implement or does not correctly perform access control to check whether users are authorized to access internal registers and test modes through the physical debug/test interface. |
A device's internal information may be accessed through a scan chain of interconnected internal registers, usually through a JTAG interface. The JTAG interface provides access to these registers in a serial fashion in the form of a scan chain for the purposes of debugging programs running on a device. Since almost al... | [
{
"Class": "Not Language-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Language"
},
{
"Class": "Not OS-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Operating_System"
},
{
"Class": "Not Architecture-Specific",
"Name": null,
"Pre... | null | [
{
"Note": null,
"Phase": "Architecture and Design"
},
{
"Note": null,
"Phase": "Implementation"
}
] | [
{
"Impact": [
"Read Application Data"
],
"Likelihood": [
"High"
],
"Note": null,
"Scope": [
"Confidentiality"
]
},
{
"Impact": [
"Read Memory"
],
"Likelihood": [
"High"
],
"Note": null,
"Scope": [
"Confidentiality"
]
}... | [
{
"Description": "If feasible, the manufacturer should disable the JTAG interface or implement authentication and authorization for the JTAG interface. If authentication logic is added, it should be resistant to timing attacks. Security-sensitive data stored in registers, such as keys, etc. should be cleared wh... | [
{
"Description": "chain: JTAG interface is not disabled (CWE-1191) during ROM code execution, introducing a race condition (CWE-362) to extract encryption keys",
"Link": "https://www.cve.org/CVERecord?id=CVE-2019-18827",
"Reference": "CVE-2019-18827"
}
] | null | null | [
"1",
"180"
] | [
{
"Authors": [
"Kurt Rosenfeld",
"Ramesh Karri"
],
"Edition": null,
"ExternalReferenceID": "REF-1037",
"Publication": null,
"PublicationDay": null,
"PublicationMonth": "02",
"PublicationYear": "2010",
"Publisher": null,
"Section": null,
"Title": "Attacks and D... | [
{
"Note": "CWE-1191 and CWE-1244 both involve physical debug access, but the weaknesses are different. CWE-1191 is effectively about missing authorization for a debug interface, i.e. JTAG. CWE-1244 is about providing internal assets with the wrong debug access level, exposing the asset to untrusted debug agents... | [
{
"ContributionComment": null,
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... | Allowed | This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities. | Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction. | [
"Acceptable-Use"
] | null | [
{
"CweID": "284",
"Nature": "ChildOf",
"Ordinal": "Primary",
"ViewID": "1000"
}
] | [
{
"Description": null,
"Ordinality": "Primary"
}
] | [
{
"Description": "\n\nAuthentication and authorization of debug and test interfaces should be part of the architecture and design review process. Withholding of private register documentation from the debug and test interface public specification (\"Security by obscurity\") should not be considered as sufficien... | [
{
"Entries": [
{
"BodyText": null,
"ExampleCode": null,
"IntroText": "A home, WiFi-router device implements a login prompt which prevents an unauthorized user from issuing any commands on the device until appropriate credentials are provided. The credentials are protected on the de... | null | null | null | null | 1 | [
[
"284",
"1191"
]
] | [] |
1220 | Insufficient Granularity of Access Control | Base | Simple | Incomplete | The product implements access controls via a policy or other feature with the intention to disable or restrict accesses (reads and/or writes) to assets in a system from untrusted agents. However, implemented access controls lack required granularity, which renders the control policy too broad because it allows accesses... |
Integrated circuits and hardware engines can expose accesses to assets (device configuration, keys, etc.) to trusted firmware or a software module (commonly set by BIOS/bootloader). This access is typically access-controlled. Upon a power reset, the hardware or system usually starts with default values in registers, ... | [
{
"Class": "Not Language-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Language"
},
{
"Class": "Not OS-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Operating_System"
},
{
"Class": "Not Architecture-Specific",
"Name": null,
"Pre... | null | [
{
"Note": "Such issues could be introduced during hardware architecture and design and identified later during Testing or System Configuration phases.",
"Phase": "Architecture and Design"
},
{
"Note": "Such issues could be introduced during hardware implementation and identified later during Testing... | [
{
"Impact": [
"Modify Memory",
"Read Memory",
"Execute Unauthorized Code or Commands",
"Gain Privileges or Assume Identity",
"Bypass Protection Mechanism",
"Other"
],
"Likelihood": [
"High"
],
"Note": null,
"Scope": [
"Confidentiality",
"... | [
{
"Description": "\n\n - Access-control-policy protections must be reviewed for design inconsistency and common weaknesses.\n\n - Access-control-policy definition and programming flow must be tested in pre-silicon, post-silicon testing.\n\n",
"Effectiveness": "High",
"EffectivenessNotes": null,
"M... | [
{
"Description": "A form hosting website only checks the session authentication status for a single form, making it possible to bypass authentication when there are multiple forms",
"Link": "https://www.cve.org/CVERecord?id=CVE-2022-24985",
"Reference": "CVE-2022-24985"
},
{
"Description": "An o... | null | null | [
"1",
"180"
] | [
{
"Authors": null,
"Edition": null,
"ExternalReferenceID": "REF-1346",
"Publication": null,
"PublicationDay": null,
"PublicationMonth": null,
"PublicationYear": "2019",
"Publisher": null,
"Section": null,
"Title": "axi_node_intf_wrap.sv",
"URL": "https://github.com/HACK-E... | null | [
{
"ContributionComment": null,
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... | Allowed | This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities. | Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction. | [
"Acceptable-Use"
] | null | [
{
"CweID": "284",
"Nature": "ChildOf",
"Ordinal": "Primary",
"ViewID": "1000"
}
] | null | null | [
{
"Entries": [
{
"BodyText": null,
"ExampleCode": null,
"IntroText": "Consider a system with a register for storing AES key for encryption or decryption. The key is 128 bits, implemented as a set of four 32-bit registers. The key registers are assets and registers, AES_KEY_READ_POL... | null | null | null | null | 1 | [
[
"284",
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]
] | [
"1222"
] |
1222 | Insufficient Granularity of Address Regions Protected by Register Locks | Variant | Simple | Incomplete | The product defines a large address region protected from modification by the same register lock control bit. This results in a conflict between the functional requirement that some addresses need to be writable by software during operation and the security requirement that the system configuration lock bit must be set... |
Integrated circuits and hardware IPs can expose the device configuration controls that need to be programmed after device power reset by a trusted firmware or software module (commonly set by BIOS/bootloader) and then locked from any further modification. In hardware design, this is commonly implemented using a progr... | [
{
"Class": "Not Language-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Language"
},
{
"Class": "Not OS-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Operating_System"
},
{
"Class": "Not Architecture-Specific",
"Name": null,
"Pre... | null | [
{
"Note": "Such issues are introduced during hardware architecture and design since software controls and configuration are defined during these phases and identified later during Testing or System Configuration phases.",
"Phase": "Architecture and Design"
}
] | [
{
"Impact": [
"Other"
],
"Likelihood": null,
"Note": "System security configuration cannot be defined in a way that does not conflict with functional requirements of device.",
"Scope": [
"Access Control"
]
}
] | [
{
"Description": "\n\nThe defining of protected locked registers should be reviewed or tested early in the design phase with software teams to ensure software flows are not blocked by the security locks.\n\n\nAs an alternative to using register lock control bits and fixed access control regions, the hardware de... | null | null | null | [
"679"
] | null | null | [
{
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... | Allowed | This CWE entry is at the Variant level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities. | Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction. | [
"Acceptable-Use"
] | null | [
{
"CweID": "1220",
"Nature": "ChildOf",
"Ordinal": "Primary",
"ViewID": "1000"
}
] | null | null | [
{
"Entries": [
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"BodyText": null,
"ExampleCode": null,
"IntroText": "For example, consider a hardware unit with a 32 kilobyte configuration address space where the first 8 kilobyte address contains security sensitive controls that must only be writable by device bootloader. One wa... | null | null | null | null | 1 | [
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] | [] |
1224 | Improper Restriction of Write-Once Bit Fields | Base | Simple | Incomplete | The hardware design control register "sticky bits" or write-once bit fields are improperly implemented, such that they can be reprogrammed by software. |
Integrated circuits and hardware IP software programmable controls and settings are commonly stored in register circuits. These register contents have to be initialized at hardware reset to define default values that are hard coded in the hardware description language (HDL) code of the hardware unit. A common securit... | [
{
"Class": null,
"Name": "Verilog",
"Prevalence": "Undetermined",
"Type": "Language"
},
{
"Class": null,
"Name": "VHDL",
"Prevalence": "Undetermined",
"Type": "Language"
},
{
"Class": "System on Chip",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Techn... | null | [
{
"Note": null,
"Phase": "Architecture and Design"
},
{
"Note": "Such issues could be introduced during implementation of hardware design, since IP parameters and defaults are defined in HDL code and identified later during Testing or System Configuration phases.",
"Phase": "Implementation"
}
... | [
{
"Impact": [
"Varies by Context"
],
"Likelihood": null,
"Note": "System configuration cannot be programmed in a secure way.",
"Scope": [
"Confidentiality",
"Integrity",
"Availability",
"Access Control"
]
}
] | [
{
"Description": "During hardware design all register write-once or sticky fields must be evaluated for proper configuration.",
"Effectiveness": null,
"EffectivenessNotes": null,
"MitigationID": null,
"Phase": [
"Architecture and Design"
],
"Strategy": null
},
{
"Descriptio... | null | null | null | [
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... | Allowed | This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities. | Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction. | [
"Acceptable-Use"
] | null | [
{
"CweID": "284",
"Nature": "ChildOf",
"Ordinal": "Primary",
"ViewID": "1000"
}
] | null | null | [
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"IntroText": "Consider the example design module system verilog code shown below. register_write_once_example module is an example of register that has a write-once field defined. Bit 0 field captures the write_once_status val... | null | null | null | null | 1 | [
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1231 | Improper Prevention of Lock Bit Modification | Base | Simple | Stable | The product uses a trusted lock bit for restricting access to registers, address regions, or other resources, but the product does not prevent the value of the lock bit from being modified after it has been set. |
In integrated circuits and hardware intellectual property (IP) cores, device configuration controls are commonly programmed after a device power reset by a trusted firmware or software module (e.g., BIOS/bootloader) and then locked from any further modification.
This behavior is commonly implemented using a trusted... | [
{
"Class": "Not Language-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Language"
},
{
"Class": "Not OS-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Operating_System"
},
{
"Class": "Not Architecture-Specific",
"Name": null,
"Pre... | null | [
{
"Note": "Such issues could be introduced during hardware architecture and design and identified later during Testing or System Configuration phases.",
"Phase": "Architecture and Design"
},
{
"Note": "Such issues could be introduced during implementation and identified later during Testing or Syste... | [
{
"Impact": [
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"Likelihood": [
"High"
],
"Note": "Registers protected by lock bit can be modified even when lock is set.",
"Scope": [
"Access Control"
]
}
] | [
{
"Description": "\n\n - Security lock bit protections must be reviewed for design inconsistency and common weaknesses.\n\n - Security lock programming flow and lock properties must be tested in pre-silicon and post-silicon testing.\n\n",
"Effectiveness": "High",
"EffectivenessNotes": null,
"Mitig... | [
{
"Description": "chip reset clears critical read/write lock permissions for RSA function",
"Link": "https://www.cve.org/CVERecord?id=CVE-2017-6283",
"Reference": "CVE-2017-6283"
}
] | null | null | [
"680"
] | [
{
"Authors": null,
"Edition": null,
"ExternalReferenceID": "REF-1350",
"Publication": null,
"PublicationDay": null,
"PublicationMonth": null,
"PublicationYear": "2021",
"Publisher": null,
"Section": null,
"Title": "reglk_wrapper.sv",
"URL": "https://github.com/HACK-EVENT/... | null | [
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... | Allowed | This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities. | Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction. | [
"Acceptable-Use"
] | null | [
{
"CweID": "284",
"Nature": "ChildOf",
"Ordinal": "Primary",
"ViewID": "1000"
}
] | [
{
"Description": null,
"Ordinality": "Primary"
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] | [
{
"Description": "Set the lock bit. Power cycle the device. Attempt to clear the lock bit. If the information is changed, implement a design fix. Retest. Also, attempt to indirectly clear the lock bit or bypass it.",
"DetectionMethodID": null,
"Effectiveness": "High",
"EffectivenessNotes": null,
... | [
{
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"IntroText": "Consider the example design below for a digital thermal sensor that detects overheating of the silicon and triggers system shutdown. The system critical temperature limit (CRITICAL_TEMP_LIMIT) and thermal sensor ... | null | null | null | null | 1 | [
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1233 | Security-Sensitive Hardware Controls with Missing Lock Bit Protection | Base | Simple | Stable | The product uses a register lock bit protection mechanism, but it does not ensure that the lock bit prevents modification of system registers or controls that perform changes to important hardware system configuration. |
Integrated circuits and hardware intellectual properties (IPs) might provide device configuration controls that need to be programmed after device power reset by a trusted firmware or software module, commonly set by BIOS/bootloader. After reset, there can be an expectation that the controls cannot be used to perform... | [
{
"Class": "Not Language-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Language"
},
{
"Class": "Not OS-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Operating_System"
},
{
"Class": "Not Architecture-Specific",
"Name": null,
"Pre... | null | [
{
"Note": "Such issues could be introduced during hardware architecture and design and identified later during Testing or System Configuration phases.",
"Phase": "Architecture and Design"
},
{
"Note": "Such issues could be introduced during implementation and identified later during Testing or Syste... | [
{
"Impact": [
"Modify Memory"
],
"Likelihood": null,
"Note": "System Configuration protected by the lock bit can be modified even when the lock is set.",
"Scope": [
"Access Control"
]
}
] | [
{
"Description": "\n\n - Security lock bit protections must be reviewed for design inconsistency and common weaknesses.\n\n - Security lock programming flow and lock properties must be tested in pre-silicon and post-silicon testing.\n\n",
"Effectiveness": null,
"EffectivenessNotes": null,
"Mitigat... | [
{
"Description": "Certain servers leave a write protection lock bit unset after boot, potentially allowing modification of parts of flash memory.",
"Link": "https://www.cve.org/CVERecord?id=CVE-2018-9085",
"Reference": "CVE-2018-9085"
},
{
"Description": "Chain: chipset has a race condition (CWE... | null | null | [
"176",
"680"
] | [
{
"Authors": [
"CERT Coordination Center"
],
"Edition": null,
"ExternalReferenceID": "REF-1237",
"Publication": null,
"PublicationDay": "05",
"PublicationMonth": "01",
"PublicationYear": "2015",
"Publisher": null,
"Section": null,
"Title": "Intel BIOS locking mechan... | null | [
{
"ContributionComment": null,
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"ContributionName": null,
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"ContributionReleaseDate": null,
"ContributionType": null,
"ContributionVersion": null,
"Date": null,
"ModificationComment": null,
"ModificationDate": null,
... | Allowed | This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities. | Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction. | [
"Acceptable-Use"
] | null | [
{
"CweID": "284",
"Nature": "ChildOf",
"Ordinal": "Primary",
"ViewID": "1000"
},
{
"CweID": "667",
"Nature": "ChildOf",
"Ordinal": null,
"ViewID": "1000"
}
] | [
{
"Description": null,
"Ordinality": "Primary"
}
] | [
{
"Description": "Set the lock bit. Attempt to modify the information protected by the lock bit. If the information is changed, implement a design fix. Retest. Also, attempt to indirectly clear the lock bit or bypass it.",
"DetectionMethodID": null,
"Effectiveness": "High",
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"IntroText": "Consider the example design below for a digital thermal sensor that detects overheating of the silicon and triggers system shutdown. The system critical temperature limit (CRITICAL_TEMP_LIMIT) and thermal sensor ... | null | null | null | null | 3 | [
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1242 | Inclusion of Undocumented Features or Chicken Bits | Base | Simple | Incomplete | The device includes chicken bits or undocumented features that can create entry points for unauthorized actors. |
A common design practice is to use undocumented bits on a device that can be used to disable certain functional security features. These bits are commonly referred to as "chicken bits". They can facilitate quick identification and isolation of faulty components, features that negatively affect performance, or feature... | [
{
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{
"Class": "Not Architecture-Specific",
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"Bypass Protection Mechanism"
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"Likelihood": null,
"Note": null,
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"Description": "\n\nThe implementation of chicken bits in a released product is highly discouraged. If implemented at all, ensure that they are disabled in production devices. All interfaces to a device should be documented.\n",
"Effectiveness": "High",
"EffectivenessNotes": null,
"MitigationID": ... | null | null | [
{
"EntryID": "Part 4-1",
"EntryName": "Req SD-4",
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"TaxonomyName": "ISA/IEC 62443"
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{
"EntryID": "Part 4-1",
"EntryName": "Req SVV-3",
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"TaxonomyName": "ISA/IEC 62443"
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{
"EntryID": "Part 4-2",
"EntryName": "Req CR 2.12",
... | [
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{
"Authors": [
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"Thorsten Holz"
],
"Edition": null,
"ExternalReferenceID": "REF-1071",
"Publication": null,
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... | Allowed | This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities. | Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction. | [
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1252 | CPU Hardware Not Configured to Support Exclusivity of Write and Execute Operations | Base | Simple | Incomplete | The CPU is not configured to provide hardware support for exclusivity of write and execute operations on memory. This allows an attacker to execute data from all of memory. |
CPUs provide a special bit that supports exclusivity of write and execute operations. This bit is used to segregate areas of memory to either mark them as code (instructions, which can be executed) or data (which should not be executed). In this way, if a user can write to a region of memory, the user cannot execute ... | [
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"Name": null,
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"Likelihood": null,
"Note": null,
"Scope": [
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{
"Description": "\n\nImplement a dedicated bit that can be leveraged by the Operating System to mark data areas as non-executable. If such a bit is not available in the CPU, implement MMU/MPU (memory management unit / memory protection unit).\n",
"Effectiveness": null,
"EffectivenessNotes": null,
"... | null | null | null | [
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"Title": "Cortex-R4 Manual",
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... | Allowed | This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities. | Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction. | [
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{
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"IntroText": "MCS51 Microcontroller (based on 8051) does not have a special bit to support write exclusivity. It also does not have an MMU/MPU support. The Cortex-M CPU has an optional MPU that supports up to 8 regions.",
... | null | null | null | null | 1 | [
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1257 | Improper Access Control Applied to Mirrored or Aliased Memory Regions | Base | Simple | Incomplete | Aliased or mirrored memory regions in hardware designs may have inconsistent read/write permissions enforced by the hardware. A possible result is that an untrusted agent is blocked from accessing a memory region but is not blocked from accessing the corresponding aliased memory region.
|
Hardware product designs often need to implement memory protection features that enable privileged software to define isolated memory regions and access control (read/write) policies. Isolated memory regions can be defined on different memory spaces in a design (e.g. system physical address, virtual address, memory m... | [
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{
"Description": "The checks should be applied for consistency access rights between primary memory regions and any mirrored or aliased memory regions. If different memory protection units (MPU) are protecting the aliased regions, their protected range definitions and policies should be synchronized.",
"Eff... | null | null | null | [
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... | Allowed | This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities. | Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction. | [
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"IntroText": "In a System-on-a-Chip (SoC) design the system fabric uses 16 bit addresses. An IP unit (Unit_A) has 4 kilobyte of internal memory which is mapped into a 16 kilobyte address range in the system fabric address map.... | null | null | null | null | 1 | [
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1259 | Improper Restriction of Security Token Assignment | Base | Simple | Incomplete | The System-On-A-Chip (SoC) implements a Security Token mechanism to differentiate what actions are allowed or disallowed when a transaction originates from an entity. However, the Security Tokens are improperly protected. | Systems-On-A-Chip (Integrated circuits and hardware engines) implement Security Tokens to differentiate and identify which actions originated from which agent. These actions may be one of the directives: 'read', 'write', 'program', 'reset', 'fetch', 'compute', etc. Security Tokens are assigned to every agent in the Sys... | [
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"Class": "Not Architecture-Specific",
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"Note": null,
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"Impact": [
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"Bypass Protection Mechanism",
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"Modify Memory",
"Modify Memory",
"DoS: Crash, Exit, or Restart"
],
"Likelihood": [
"High"
],
... | [
{
"Description": "\n\n - Security Token assignment review checks for design inconsistency and common weaknesses.\n\n - Security-Token definition and programming flow is tested in both pre-silicon and post-silicon testing.\n\n",
"Effectiveness": null,
"EffectivenessNotes": null,
"MitigationID": nul... | null | null | null | [
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{
"Note": "This entry is still under development and will continue to see updates and content improvements. Currently it is expressed as a general absence of a protection mechanism as opposed to a specific mistake, and the entry's name and description could be interpreted as applying to software.",
"Type": ... | [
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... | Allowed | This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities. | Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction. | [
"Acceptable-Use"
] | null | [
{
"CweID": "284",
"Nature": "ChildOf",
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"ViewID": "1000"
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"IntroText": "For example, consider a system with a register for storing an AES key for encryption and decryption. The key is of 128 bits implemented as a set of four 32-bit registers. The key register assets have an associate... | null | null | null | null | 1 | [
[
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