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LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY floating_point_v7_1_2; USE floating_point_v7_1_2.floating_point_v7_1_2; ENTITY fmul IS PORT ( aclk : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tda... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 11; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use work.CONSTANTS.all; use work.CONFIG_MANDELBROT.all; entity cpt_iter is Port ( clock : in STD_LOGIC; reset : in STD_LOGIC; inib : in std_logic; endcalcul : in STD_LOGIC; maxiter : in STD_LOGIC; iter : out STD_LOGIC_VECTOR(ITER_RANGE-1 downto 0)); ... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; entity CU_instruction_dispatcher is --{{{ port( clk, nrst : in std_logic; cram_rqst : out std_logic := '0'; cram_rdAddr : out unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); cram_rdAddr_con... |
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; USE IEEE.NUMERIC_STD.all; LIBRARY UniSim; USE UniSim.vComponents.ALL; entity xil_SystemMonitor_Virtex6 is port ( Reset : in STD_LOGIC; -- Reset signal for the System Monitor control logic Alarm_UserTemp : out STD_LOGIC; -- Temperature-sensor alarm output Alarm_OverTemp : out ... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.ALL; package mips_defs is subtype mips_opcode_type is std_logic_vector(5 downto 0); subtype mips_func_type is std_logic_vector(5 downto 0); constant OP_SPECIAL : std_logic_vector(5 downto 0) := "000000"; constant OP_J : std... |
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.nf_pkg.all; entity nf_transmitter is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : ... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY echo_tb IS END echo_tb; ARCHITECTURE behavior OF echo_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT echo PORT( rx : IN std_logic; tx : OUT std_logic; clk : IN std_logic ); END COMPONENT; component uart is generic ( CLK_FREQ : integer := 32; -- M... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 0; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity uart is generic ( CLK_FREQ : integer := 32; -- Main frequency (MHz) SER_FREQ : integer := 9600; -- Baud rate (bps) PARITY_BIT : boolean := true -- Parity bit enable/disable ); port ( -- Control clk : in std_... |
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY Decoder_Decoder_sch_tb IS END Decoder_Decoder_sch_tb; ARCHITECTURE behavioral OF Decoder_Decoder_sch_tb IS COMPONENT Decoder PORT ( RF : OUT STD_LOGIC; RR : OUT STD_LOGIC; LF : OUT STD_LOGIC; LR : OUT STD_LOGIC; SCLK : IN STD_LOGIC; I : IN STD_... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; package FGPU_definitions is constant N_CU_W : natural := 0; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W ... |
library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.ALL; entity register_file is port (clk : in std_logic; rst : in std_logic; a1 : in std_logic_vector(4 downto 0); a2 : in std_logic_vector(4 downto 0); a3 : in std_logic_vector(4 downto 0); wd3 : in std_logic_vector(31 downt... |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; library PoC; use PoC.my_config.all; use PoC.utils.all; entity io_TimingCounter is generic ( TIMING_TABLE : T_NATVEC -- timing table ); port ( Clock : in STD_LOGIC; -- clock Enable : in STD_LOGIC; -- enable counter Load : in STD_LOGIC; -- load Timing ... |
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