Henry Shulayev Barnes commited on
Commit ·
982f68d
1
Parent(s): 488732d
Fix Loihi parity claims
Browse files
README.md
CHANGED
|
@@ -22,7 +22,7 @@ For full-scale hardware-accurate simulations, use the [Catalyst Cloud API](https
|
|
| 22 |
|
| 23 |
## Features
|
| 24 |
|
| 25 |
-
- **Processor comparison** — N1
|
| 26 |
- **Hardware constraint validation** — check if your network fits on the target processor
|
| 27 |
- **Live LIF simulation** — configure neurons, connections, and topology
|
| 28 |
- **Spike raster visualisation** — see firing patterns across populations
|
|
|
|
| 22 |
|
| 23 |
## Features
|
| 24 |
|
| 25 |
+
- **Processor comparison** — N1 and N2 side-by-side
|
| 26 |
- **Hardware constraint validation** — check if your network fits on the target processor
|
| 27 |
- **Live LIF simulation** — configure neurons, connections, and topology
|
| 28 |
- **Spike raster visualisation** — see firing patterns across populations
|
app.py
CHANGED
|
@@ -20,7 +20,6 @@ PROCESSORS = {
|
|
| 20 |
"graded_spike_bits": 8,
|
| 21 |
"learning_opcodes": 14,
|
| 22 |
"max_axon_delay": 63,
|
| 23 |
-
"parity": "Intel Loihi 1",
|
| 24 |
"neuron_models": ["LIF"],
|
| 25 |
"features": [
|
| 26 |
"Dendritic compartments (4 per neuron)",
|
|
@@ -39,7 +38,6 @@ PROCESSORS = {
|
|
| 39 |
"graded_spike_bits": 8,
|
| 40 |
"learning_opcodes": 14,
|
| 41 |
"max_axon_delay": 63,
|
| 42 |
-
"parity": "Intel Loihi 2",
|
| 43 |
"neuron_models": ["LIF", "CUBA", "ALIF", "Izhikevich", "Custom"],
|
| 44 |
"features": [
|
| 45 |
"Programmable neuron models (microcode engine)",
|
|
@@ -326,7 +324,6 @@ def get_processor_info(processor):
|
|
| 326 |
"""Return markdown specs for selected processor."""
|
| 327 |
spec = PROCESSORS[processor]
|
| 328 |
md = f"## Catalyst {processor}\n\n"
|
| 329 |
-
md += f"**Parity**: {spec['parity']}\n\n"
|
| 330 |
md += f"| Spec | Value |\n|------|-------|\n"
|
| 331 |
md += f"| Cores | {spec['cores']} |\n"
|
| 332 |
md += f"| Neurons/core | {spec['neurons_per_core']:,} |\n"
|
|
@@ -370,7 +367,6 @@ Configure networks, validate hardware constraints, and run simulations — all i
|
|
| 370 |
|
| 371 |
| | **N1** | **N2** |
|
| 372 |
|---|---|---|
|
| 373 |
-
| **Parity** | Intel Loihi 1 | Intel Loihi 2 |
|
| 374 |
| **Cores** | 128 | 128 |
|
| 375 |
| **Neurons/core** | 1,024 | 1,024 |
|
| 376 |
| **Total neurons** | 131,072 | 131,072 |
|
|
@@ -381,7 +377,7 @@ Configure networks, validate hardware constraints, and run simulations — all i
|
|
| 381 |
| **Max axon delay** | 63 timesteps | 63 timesteps |
|
| 382 |
| **Key advance** | Foundation | Programmable neuron microcode engine |
|
| 383 |
|
| 384 |
-
The **N1** is a complete neuromorphic processor with
|
| 385 |
|
| 386 |
The **N2** adds a **programmable microcode engine** for custom neuron models. Instead of hardwired LIF, you can program arbitrary neuron dynamics — CUBA, ALIF, Izhikevich, or anything you design.
|
| 387 |
|
|
|
|
| 20 |
"graded_spike_bits": 8,
|
| 21 |
"learning_opcodes": 14,
|
| 22 |
"max_axon_delay": 63,
|
|
|
|
| 23 |
"neuron_models": ["LIF"],
|
| 24 |
"features": [
|
| 25 |
"Dendritic compartments (4 per neuron)",
|
|
|
|
| 38 |
"graded_spike_bits": 8,
|
| 39 |
"learning_opcodes": 14,
|
| 40 |
"max_axon_delay": 63,
|
|
|
|
| 41 |
"neuron_models": ["LIF", "CUBA", "ALIF", "Izhikevich", "Custom"],
|
| 42 |
"features": [
|
| 43 |
"Programmable neuron models (microcode engine)",
|
|
|
|
| 324 |
"""Return markdown specs for selected processor."""
|
| 325 |
spec = PROCESSORS[processor]
|
| 326 |
md = f"## Catalyst {processor}\n\n"
|
|
|
|
| 327 |
md += f"| Spec | Value |\n|------|-------|\n"
|
| 328 |
md += f"| Cores | {spec['cores']} |\n"
|
| 329 |
md += f"| Neurons/core | {spec['neurons_per_core']:,} |\n"
|
|
|
|
| 367 |
|
| 368 |
| | **N1** | **N2** |
|
| 369 |
|---|---|---|
|
|
|
|
| 370 |
| **Cores** | 128 | 128 |
|
| 371 |
| **Neurons/core** | 1,024 | 1,024 |
|
| 372 |
| **Total neurons** | 131,072 | 131,072 |
|
|
|
|
| 377 |
| **Max axon delay** | 63 timesteps | 63 timesteps |
|
| 378 |
| **Key advance** | Foundation | Programmable neuron microcode engine |
|
| 379 |
|
| 380 |
+
The **N1** is a complete 128-core neuromorphic processor with on-chip STDP learning, dendritic compartments, graded spikes, and programmable axonal delays — a Loihi-class feature set.
|
| 381 |
|
| 382 |
The **N2** adds a **programmable microcode engine** for custom neuron models. Instead of hardwired LIF, you can program arbitrary neuron dynamics — CUBA, ALIF, Izhikevich, or anything you design.
|
| 383 |
|