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@@ -95,14 +95,11 @@ All core libraries extracted from this project are published as standalone open-
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  ## 📸 Visual Proof: Silicon Pulse & FPGA Deployment
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- ![First SNN Pulse](https://huggingface.co/rmems/Spikenaut-SNN-v2/resolve/main/assets/snn_pulse_v2.png)
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- *The very first experience seeing neural spikes - Birth of Spikenaut v1.*
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- ![Silicon Heartbeat](https://huggingface.co/rmems/Spikenaut-SNN-v2/resolve/main/assets/snn_heartbeat_sharp.png)
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- *Close-up timing analysis of the asynchronous spike-train encoding (v2).*
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- ![Waveform Analysis](https://huggingface.co/rmems/Spikenaut-SNN-v2/resolve/main/assets/snn_waveform_close.png)
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- *Detailed waveform visualization showing neural membrane potential dynamics.*
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  ![FPGA Hardware Deployment](https://huggingface.co/rmems/Spikenaut-SNN-v2/resolve/main/assets/fpga_hardware_cat.jpg)
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  *Real-world deployment on the Xilinx Artix-7 (Basys3) FPGA. Verified neural cortex protocol running on bare metal (Lion approved).*
 
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  ## 📸 Visual Proof: Silicon Pulse & FPGA Deployment
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+ ![First SNN Pulse](https://huggingface.co/rmems/Spikenaut-SNN-v2/resolve/main/assets/first_spike_pulse.png)
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+ *The very first experience seeing neural spikes - Spikenaut v1 birth moment.*
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+ ![First Spike Detail](https://huggingface.co/rmems/Spikenaut-SNN-v2/resolve/main/assets/first_spike_detail.png)
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+ *Close-up timing analysis of the asynchronous spike-train encoding (v1).*
 
 
 
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  ![FPGA Hardware Deployment](https://huggingface.co/rmems/Spikenaut-SNN-v2/resolve/main/assets/fpga_hardware_cat.jpg)
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  *Real-world deployment on the Xilinx Artix-7 (Basys3) FPGA. Verified neural cortex protocol running on bare metal (Lion approved).*