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alwas-ml-models
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{
  "hours_features": [
    "tech_node_encoded",
    "block_type_encoded",
    "priority_encoded",
    "transistor_count",
    "transistor_count_log",
    "has_dependencies",
    "num_dependencies",
    "constraint_complexity",
    "drc_iterations",
    "engineer_skill_factor",
    "type_node_interaction",
    "complexity_score",
    "size_priority_interaction"
  ],
  "complexity_features": [
    "tech_node_encoded",
    "block_type_encoded",
    "priority_encoded",
    "transistor_count",
    "transistor_count_log",
    "has_dependencies",
    "num_dependencies",
    "constraint_complexity",
    "drc_iterations",
    "type_node_interaction",
    "complexity_score",
    "size_priority_interaction"
  ],
  "bottleneck_features": [
    "tech_node_encoded",
    "block_type_encoded",
    "priority_encoded",
    "transistor_count_log",
    "has_dependencies",
    "num_dependencies",
    "constraint_complexity",
    "estimated_hours",
    "hours_logged",
    "drc_iterations",
    "drc_violations_total",
    "lvs_mismatches_total",
    "current_stage_idx",
    "engineer_skill_factor",
    "complexity_score",
    "hours_budget_pct",
    "stage_velocity"
  ],
  "completion_features": [
    "tech_node_encoded",
    "block_type_encoded",
    "priority_numeric",
    "transistor_count_log",
    "has_dependencies",
    "num_dependencies",
    "constraint_complexity",
    "estimated_hours",
    "engineer_skill_factor",
    "drc_iterations",
    "current_stage_idx",
    "cumulative_hours",
    "cumulative_days",
    "cumulative_drc_violations",
    "cumulative_lvs_mismatches",
    "hours_vs_estimate_ratio",
    "stages_completed",
    "avg_hours_per_stage_so_far",
    "avg_days_per_stage_so_far"
  ],
  "tech_nodes": [
    "12nm",
    "14nm",
    "22nm",
    "28nm",
    "45nm",
    "5nm",
    "65nm",
    "7nm"
  ],
  "block_types": [
    "ADC",
    "BGR",
    "BandgapRef",
    "Comparator",
    "CurrentMirror",
    "DAC",
    "DiffAmp",
    "LDO",
    "LNA",
    "LVDS_Driver",
    "Mixer",
    "OTA",
    "Oscillator",
    "PA",
    "PLL",
    "PowerDetector",
    "SampleHold",
    "SerDes",
    "TIA",
    "VCO"
  ],
  "priorities": [
    "P4-Low",
    "P3-Medium",
    "P2-High",
    "P1-Critical"
  ],
  "complexity_classes": [
    "High",
    "Low",
    "Medium"
  ],
  "bottleneck_classes": [
    "High",
    "Low",
    "Medium"
  ]
}