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-# Audio files - compressed
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DATASET_STRUCTURE.md

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+# Dataset Structure
+
+## Atomic unit
+
+The atomic unit is one problem bundle.
+
+Each bundle should contain:
+
+- `problem.md`
+- `config.yaml`
+- `testbench.v`
+
+The default public release excludes `reference.v`.
+
+## Example layout
+
+```text
+bundles/
+├── L1_basic/
+│   ├── problem_0001/
+│   └── ...
+├── L2_sequential/
+├── L3_module/
+├── L4_system/
+└── L5_ultimate/
+```
+
+## Release notes
+
+Before publishing, update this file with:
+
+- final problem count
+- exact level names
+- whether a separate validation package includes `reference.v`
+- any held-out or omitted assets

LICENSE.md

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+# VeriScope Dataset License
+
+The released VeriScope benchmark bundles in this dataset repository are
+distributed under the terms of the Creative Commons Attribution 4.0
+International License:
+
+- https://creativecommons.org/licenses/by/4.0/
+
+## Scope of this license
+
+This license applies to the benchmark bundles released in this repository,
+including:
+
+- rewritten `problem.md` task briefs
+- benchmark-side `config.yaml` metadata
+- public `testbench.v` files
+- accompanying dataset metadata and documentation
+
+## Third-party source material
+
+VeriScope was constructed using public and open-source Verilog material,
+including a source crawl of public HDL educational problems. Those raw
+third-party source materials are not redistributed verbatim in this default
+public dataset release and remain under their original terms.
+
+## Reference RTL
+
+The default public dataset release excludes `reference.v`. Reference RTL is
+treated as a benchmark-side validation anchor rather than as part of the default
+public evaluation package.

RAI.md

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+# Responsible AI and Release Notes
+
+This file is a draft for the RAI fields expected in the NeurIPS 2026 E&D submission package.
+
+## Resource type
+
+- benchmark dataset
+- evaluation suite companion data release
+
+## Intended use
+
+- evaluation of first-pass Verilog code generation
+- comparison of hardware coding models under a common benchmark
+- study of execution-only vs. quality-aware evaluation
+
+## Foreseeable misuse
+
+- generation of unsafe or malicious RTL
+- unauthorized recreation of proprietary-style hardware patterns
+- overclaiming model readiness for production chip design
+
+## Limitations
+
+- public third-party models are not fully decontaminated
+- top-end expert-scale coverage is still limited
+- benchmark scores do not replace synthesis, timing, formal verification, or human sign-off
+- the default public dataset excludes `reference.v`, so benchmark-side gold verification is not fully reproduced from the dataset release alone
+
+## Human oversight
+
+The benchmark should be used as an evaluation aid, not as a final arbiter of production hardware quality.
+
+## Release safeguards
+
+- clear licensing and attribution
+- explicit statement of intended use
+- explicit statement of out-of-scope uses
+- public documentation of benchmark limitations
+- default exclusion of benchmark-side reference RTL from the public dataset

README.md

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+---
+pretty_name: VeriScope
+license: cc-by-4.0
+task_categories:
+  - text-generation
+task_ids:
+  - text-to-code
+language:
+  - en
+size_categories:
+  - n<1K
+annotations_creators:
+  - expert-generated
+source_datasets:
+  - extended
+multilinguality:
+  - monolingual
+configs:
+  - config_name: default
+    data_files:
+      - split: train
+        path: "bundles/**"
+---
+
+# VeriScope
+
+VeriScope is an open benchmark dataset for first-pass Verilog coding.
+
+This Hugging Face repository is intended to host the released benchmark bundles and dataset metadata that accompany the public code release.
+
+## Dataset summary
+
+- domain: Verilog / RTL generation
+- unit of release: task bundle
+- target setting: first-pass code generation from natural-language task briefs
+- public paper size: 568 problems
+
+## Dataset structure
+
+Each public example is a task bundle containing:
+
+- `problem.md`
+- `config.yaml`
+- `testbench.v`
+
+The default public release excludes `reference.v`. The reference RTL is treated as a benchmark-side validation anchor rather than as part of the default evaluation package.
+
+Suggested tree:
+
+```text
+bundles/
+├── L1_basic/
+├── L2_sequential/
+├── L3_module/
+├── L4_system/
+└── L5_ultimate/
+```
+
+## Supported uses
+
+- evaluation of Verilog code generation models
+- evaluation of first-pass hardware coding agents
+- analysis of functional correctness vs. structural quality
+
+## Out-of-scope uses
+
+- production sign-off
+- security certification
+- claims of complete training-data decontamination
+
+## Dataset creation
+
+The benchmark is built from a curated Verilog seed corpus and standardized into reusable problem bundles with benchmark-side validation harnesses. Public task briefs are rewritten and packaged rather than copied verbatim from source material.
+
+## Evaluation
+
+The companion GitHub repository contains the public evaluation harness, scoring logic, and reproduction instructions.
+
+## Licensing
+
+The released benchmark bundles are distributed under `CC BY 4.0`. This license applies to the released task packages in this repository. Third-party source material used during benchmark construction is not redistributed verbatim here and remains under its original terms.
+
+## Citation
+
+```bibtex
+@inproceedings{veriscope2026,
+  title={VeriScope: An Open Benchmark and Evaluation Suite for First-Pass Verilog Coding},
+  author={Wei Zhang and collaborators},
+  booktitle={NeurIPS},
+  year={2026}
+}
+```
+
+## Additional metadata
+
+- Croissant metadata: `croissant.json`
+- responsible release notes: `RAI.md`
+- dataset layout notes: `DATASET_STRUCTURE.md`
+- dataset license note: `LICENSE.md`

bundles/L1_basic/001_and_gate/config.yaml

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+problem_id: "001"
+title: "AND Gate"
+level: 1
+category: "basic_gates"
+description: "Implement a 2-input AND gate"
+
+module_name: "and_gate"
+ports:
+  a:
+    direction: "input"
+    width: "1"
+  b:
+    direction: "input"
+    width: "1"
+  y:
+    direction: "output"
+    width: "1"
+
+testbench_file: "testbench.v"
+timeout_compile: 10
+timeout_simulate: 10
+
+require_synthesis: false
+check_waveform: false
+
+weight_functional: 1.0
+weight_synthesis: 0.0
+weight_resource: 0.0

bundles/L1_basic/001_and_gate/problem.md

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+# Problem 001: AND Gate
+
+## Description
+
+Implement a 2-input AND gate.
+
+## Module Interface
+
+```verilog
+module and_gate(
+    input a,
+    input b,
+    output y
+);
+    // Your code here
+endmodule
+```
+
+## Specification
+
+- Inputs: `a`, `b` (1-bit each)
+- Output: `y` (1-bit)
+- Function: `y = a & b`
+
+## Truth Table
+
+| a | b | y |
+|---|---|---|
+| 0 | 0 | 0 |
+| 0 | 1 | 0 |
+| 1 | 0 | 0 |
+| 1 | 1 | 1 |
+
+## Example
+
+```verilog
+module and_gate(
+    input a,
+    input b,
+    output y
+);
+    assign y = a & b;
+endmodule
+```
+
+## Scoring
+
+- Functional correctness: 100%

bundles/L1_basic/001_and_gate/testbench.v

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+`timescale 1ns/1ps
+
+module tb_and_gate;
+    reg a, b;
+    wire y;
+
+    // Instantiate the module under test
+    and_gate uut (
+        .a(a),
+        .b(b),
+        .y(y)
+    );
+
+    integer pass_count = 0;
+    integer fail_count = 0;
+
+    initial begin
+        $display("Testing AND gate...");
+
+        // Test case 1: 0 & 0 = 0
+        a = 0; b = 0; #10;
+        if (y === 1'b0) begin
+            pass_count = pass_count + 1;
+            $display("[PASS] Test 1: %b & %b = %b", a, b, y);
+        end else begin
+            fail_count = fail_count + 1;
+            $display("[FAIL] Test 1: %b & %b = %b (expected 0)", a, b, y);
+        end
+
+        // Test case 2: 0 & 1 = 0
+        a = 0; b = 1; #10;
+        if (y === 1'b0) begin
+            pass_count = pass_count + 1;
+            $display("[PASS] Test 2: %b & %b = %b", a, b, y);
+        end else begin
+            fail_count = fail_count + 1;
+            $display("[FAIL] Test 2: %b & %b = %b (expected 0)", a, b, y);
+        end
+
+        // Test case 3: 1 & 0 = 0
+        a = 1; b = 0; #10;
+        if (y === 1'b0) begin
+            pass_count = pass_count + 1;
+            $display("[PASS] Test 3: %b & %b = %b", a, b, y);
+        end else begin
+            fail_count = fail_count + 1;
+            $display("[FAIL] Test 3: %b & %b = %b (expected 0)", a, b, y);
+        end
+
+        // Test case 4: 1 & 1 = 1
+        a = 1; b = 1; #10;
+        if (y === 1'b1) begin
+            pass_count = pass_count + 1;
+            $display("[PASS] Test 4: %b & %b = %b", a, b, y);
+        end else begin
+            fail_count = fail_count + 1;
+            $display("[FAIL] Test 4: %b & %b = %b (expected 1)", a, b, y);
+        end
+
+        // Summary
+        $display("");
+        $display("=================================");
+        $display("PASS: %0d", pass_count);
+        $display("FAIL: %0d", fail_count);
+
+        if (fail_count == 0) begin
+            $display("TEST PASSED");
+        end else begin
+            $display("TEST FAILED");
+        end
+        $display("=================================");
+
+        $finish;
+    end
+endmodule

bundles/L1_basic/002_or_gate/config.yaml

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+problem_id: "002"
+title: "OR Gate"
+level: 1
+category: "basic_gates"
+description: "Implement a 2-input OR gate"
+module_name: "or_gate"
+ports:
+  a: { direction: "input", width: "1" }
+  b: { direction: "input", width: "1" }
+  y: { direction: "output", width: "1" }
+testbench_file: "testbench.v"
+timeout_compile: 10
+timeout_simulate: 10
+require_synthesis: false
+check_waveform: false
+weight_functional: 1.0
+weight_synthesis: 0.0
+weight_resource: 0.0

bundles/L1_basic/002_or_gate/problem.md

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+# Problem 002: OR Gate
+
+## Description
+
+Implement a 2-input OR gate.
+
+## Module Interface
+
+```verilog
+module or_gate(
+    input a,
+    input b,
+    output y
+);
+    // Your code here
+endmodule
+```
+
+## Specification
+
+- Inputs: `a`, `b` (1-bit each)
+- Output: `y` (1-bit)
+- Function: `y = a | b`
+
+## Scoring
+
+- Functional correctness: 100%

bundles/L1_basic/002_or_gate/testbench.v

@@ -0,0 +1,24 @@
+`timescale 1ns/1ps
+module tb_or_gate;
+    reg a, b;
+    wire y;
+    or_gate uut(.a(a), .b(b), .y(y));
+    integer pass_count = 0;
+    integer fail_count = 0;
+    task check(input expected);
+        begin
+            #10;
+            if (y === expected) pass_count = pass_count + 1;
+            else fail_count = fail_count + 1;
+        end
+    endtask
+    initial begin
+        a=0; b=0; check(1'b0);
+        a=0; b=1; check(1'b1);
+        a=1; b=0; check(1'b1);
+        a=1; b=1; check(1'b1);
+        if (fail_count == 0) $display("TEST PASSED");
+        else $display("TEST FAILED");
+        $finish;
+    end
+endmodule

bundles/L1_basic/003_not_gate/config.yaml

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+problem_id: "003"
+title: "NOT Gate"
+level: 1
+category: "basic_gates"
+description: "Implement a NOT gate"
+module_name: "not_gate"
+ports:
+  a: { direction: "input", width: "1" }
+  y: { direction: "output", width: "1" }
+testbench_file: "testbench.v"
+timeout_compile: 10
+timeout_simulate: 10
+require_synthesis: false
+check_waveform: false
+weight_functional: 1.0
+weight_synthesis: 0.0
+weight_resource: 0.0

bundles/L1_basic/003_not_gate/problem.md

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+# Problem 003: NOT Gate
+
+## Description
+
+Implement a NOT gate (inverter).
+
+## Module Interface
+
+```verilog
+module not_gate(
+    input a,
+    output y
+);
+    // Your code here
+endmodule
+```
+
+## Specification
+
+- Input: `a` (1-bit)
+- Output: `y` (1-bit)
+- Function: `y = ~a`
+
+## Scoring
+
+- Functional correctness: 100%

bundles/L1_basic/003_not_gate/testbench.v

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+`timescale 1ns/1ps
+module tb_not_gate;
+    reg a;
+    wire y;
+    not_gate uut(.a(a), .y(y));
+    integer pass_count = 0;
+    integer fail_count = 0;
+    initial begin
+        a = 0; #10;
+        if (y === 1'b1) pass_count = pass_count + 1; else fail_count = fail_count + 1;
+        a = 1; #10;
+        if (y === 1'b0) pass_count = pass_count + 1; else fail_count = fail_count + 1;
+        if (fail_count == 0) $display("TEST PASSED");
+        else $display("TEST FAILED");
+        $finish;
+    end
+endmodule

bundles/L1_basic/004_xor_gate/config.yaml

@@ -0,0 +1,18 @@
+problem_id: "004"
+title: "XOR Gate"
+level: 1
+category: "basic_gates"
+description: "Implement a 2-input XOR gate"
+module_name: "xor_gate"
+ports:
+  a: { direction: "input", width: "1" }
+  b: { direction: "input", width: "1" }
+  y: { direction: "output", width: "1" }
+testbench_file: "testbench.v"
+timeout_compile: 10
+timeout_simulate: 10
+require_synthesis: false
+check_waveform: false
+weight_functional: 1.0
+weight_synthesis: 0.0
+weight_resource: 0.0

bundles/L1_basic/004_xor_gate/problem.md

@@ -0,0 +1,27 @@
+# Problem 004: XOR Gate
+
+## Description
+
+Implement a 2-input XOR gate.
+
+## Module Interface
+
+```verilog
+module xor_gate(
+    input a,
+    input b,
+    output y
+);
+    // Your code here
+endmodule
+```
+
+## Specification
+
+- Inputs: `a`, `b` (1-bit each)
+- Output: `y` (1-bit)
+- Function: `y = a ^ b`
+
+## Scoring
+
+- Functional correctness: 100%

bundles/L1_basic/004_xor_gate/testbench.v

@@ -0,0 +1,16 @@
+`timescale 1ns/1ps
+module tb_xor_gate;
+    reg a, b;
+    wire y;
+    xor_gate uut(.a(a), .b(b), .y(y));
+    integer pass_count = 0;
+    integer fail_count = 0;
+    initial begin
+        a=0; b=0; #10; if (y===1'b0) pass_count=pass_count+1; else fail_count=fail_count+1;
+        a=0; b=1; #10; if (y===1'b1) pass_count=pass_count+1; else fail_count=fail_count+1;
+        a=1; b=0; #10; if (y===1'b1) pass_count=pass_count+1; else fail_count=fail_count+1;
+        a=1; b=1; #10; if (y===1'b0) pass_count=pass_count+1; else fail_count=fail_count+1;
+        if (fail_count==0) $display("TEST PASSED"); else $display("TEST FAILED");
+        $finish;
+    end
+endmodule

bundles/L1_basic/005_mux2to1/config.yaml

@@ -0,0 +1,31 @@
+problem_id: "005"
+title: "2-to-1 Multiplexer"
+level: 1
+category: "mux"
+description: "Implement a 2-to-1 mux for 8-bit data"
+
+module_name: "mux2to1"
+ports:
+  a:
+    direction: "input"
+    width: "8"
+  b:
+    direction: "input"
+    width: "8"
+  sel:
+    direction: "input"
+    width: "1"
+  y:
+    direction: "output"
+    width: "8"
+
+testbench_file: "testbench.v"
+timeout_compile: 10
+timeout_simulate: 10
+
+require_synthesis: false
+check_waveform: false
+
+weight_functional: 1.0
+weight_synthesis: 0.0
+weight_resource: 0.0

bundles/L1_basic/005_mux2to1/problem.md

@@ -0,0 +1,27 @@
+# Problem 005: 2-to-1 Multiplexer
+
+## Description
+
+Implement a 2-to-1 multiplexer that selects between two 8-bit inputs.
+
+## Module Interface
+
+```verilog
+module mux2to1(
+    input [7:0] a,
+    input [7:0] b,
+    input sel,
+    output [7:0] y
+);
+    // Your code here
+endmodule
+```
+
+## Specification
+
+- When `sel = 0`: output `y = a`
+- When `sel = 1`: output `y = b`
+
+## Scoring
+
+- Functional correctness: 100%

bundles/L1_basic/005_mux2to1/testbench.v

@@ -0,0 +1,62 @@
+`timescale 1ns/1ps
+
+module tb_mux2to1;
+    reg [7:0] a, b;
+    reg sel;
+    wire [7:0] y;
+
+    mux2to1 uut (
+        .a(a),
+        .b(b),
+        .sel(sel),
+        .y(y)
+    );
+
+    integer pass_count = 0;
+    integer fail_count = 0;
+    integer i;
+
+    initial begin
+        $display("Testing 2-to-1 Multiplexer...");
+
+        // Test with various values
+        for (i = 0; i < 10; i = i + 1) begin
+            a = $random;
+            b = $random;
+
+            // Test sel = 0 (should select a)
+            sel = 0; #10;
+            if (y === a) begin
+                pass_count = pass_count + 1;
+                $display("[PASS] sel=0: y=%h (a=%h, b=%h)", y, a, b);
+            end else begin
+                fail_count = fail_count + 1;
+                $display("[FAIL] sel=0: y=%h, expected a=%h", y, a);
+            end
+
+            // Test sel = 1 (should select b)
+            sel = 1; #10;
+            if (y === b) begin
+                pass_count = pass_count + 1;
+                $display("[PASS] sel=1: y=%h (a=%h, b=%h)", y, a, b);
+            end else begin
+                fail_count = fail_count + 1;
+                $display("[FAIL] sel=1: y=%h, expected b=%h", y, b);
+            end
+        end
+
+        // Summary
+        $display("");
+        $display("=================================");
+        $display("PASS: %0d", pass_count);
+        $display("FAIL: %0d", fail_count);
+
+        if (fail_count == 0)
+            $display("TEST PASSED");
+        else
+            $display("TEST FAILED");
+        $display("=================================");
+
+        $finish;
+    end
+endmodule

bundles/L1_basic/006_mux4to1/config.yaml

@@ -0,0 +1,21 @@
+problem_id: "006"
+title: "4-to-1 Multiplexer"
+level: 1
+category: "basic_mux"
+description: "Implement a 4-to-1 multiplexer"
+module_name: "mux4to1"
+ports:
+  a: { direction: "input", width: "8" }
+  b: { direction: "input", width: "8" }
+  c: { direction: "input", width: "8" }
+  d: { direction: "input", width: "8" }
+  sel: { direction: "input", width: "2" }
+  y: { direction: "output", width: "8" }
+testbench_file: "testbench.v"
+timeout_compile: 10
+timeout_simulate: 10
+require_synthesis: false
+check_waveform: false
+weight_functional: 1.0
+weight_synthesis: 0.0
+weight_resource: 0.0

bundles/L1_basic/006_mux4to1/problem.md

@@ -0,0 +1,31 @@
+# Problem 006: 4-to-1 Multiplexer
+
+## Description
+
+Implement a 4-to-1 multiplexer with 8-bit data inputs.
+
+## Module Interface
+
+```verilog
+module mux4to1(
+    input [7:0] a,
+    input [7:0] b,
+    input [7:0] c,
+    input [7:0] d,
+    input [1:0] sel,
+    output [7:0] y
+);
+    // Your code here
+endmodule
+```
+
+## Specification
+
+- When `sel = 00`: `y = a`
+- When `sel = 01`: `y = b`
+- When `sel = 10`: `y = c`
+- When `sel = 11`: `y = d`
+
+## Scoring
+
+- Functional correctness: 100%

bundles/L1_basic/006_mux4to1/testbench.v

@@ -0,0 +1,25 @@
+`timescale 1ns/1ps
+module tb_mux4to1;
+    reg [7:0] a, b, c, d;
+    reg [1:0] sel;
+    wire [7:0] y;
+    mux4to1 uut(.a(a), .b(b), .c(c), .d(d), .sel(sel), .y(y));
+    integer pass_count = 0;
+    integer fail_count = 0;
+    integer i;
+    initial begin
+        a = 8'hAA; b = 8'hBB; c = 8'hCC; d = 8'hDD;
+        sel = 2'b00; #10; if (y===8'hAA) pass_count=pass_count+1; else fail_count=fail_count+1;
+        sel = 2'b01; #10; if (y===8'hBB) pass_count=pass_count+1; else fail_count=fail_count+1;
+        sel = 2'b10; #10; if (y===8'hCC) pass_count=pass_count+1; else fail_count=fail_count+1;
+        sel = 2'b11; #10; if (y===8'hDD) pass_count=pass_count+1; else fail_count=fail_count+1;
+        // More tests with different values
+        a = 8'h12; b = 8'h34; c = 8'h56; d = 8'h78;
+        sel = 2'b00; #10; if (y===8'h12) pass_count=pass_count+1; else fail_count=fail_count+1;
+        sel = 2'b01; #10; if (y===8'h34) pass_count=pass_count+1; else fail_count=fail_count+1;
+        sel = 2'b10; #10; if (y===8'h56) pass_count=pass_count+1; else fail_count=fail_count+1;
+        sel = 2'b11; #10; if (y===8'h78) pass_count=pass_count+1; else fail_count=fail_count+1;
+        if (fail_count==0) $display("TEST PASSED"); else $display("TEST FAILED");
+        $finish;
+    end
+endmodule

bundles/L1_basic/007_half_adder/config.yaml

@@ -0,0 +1,19 @@
+problem_id: "007"
+title: "Half Adder"
+level: 1
+category: "basic_arithmetic"
+description: "Implement a half adder"
+module_name: "half_adder"
+ports:
+  a: { direction: "input", width: "1" }
+  b: { direction: "input", width: "1" }
+  sum: { direction: "output", width: "1" }
+  carry: { direction: "output", width: "1" }
+testbench_file: "testbench.v"
+timeout_compile: 10
+timeout_simulate: 10
+require_synthesis: false
+check_waveform: false
+weight_functional: 1.0
+weight_synthesis: 0.0
+weight_resource: 0.0

bundles/L1_basic/007_half_adder/problem.md

@@ -0,0 +1,27 @@
+# Problem 007: Half Adder
+
+## Description
+
+Implement a half adder.
+
+## Module Interface
+
+```verilog
+module half_adder(
+    input a,
+    input b,
+    output sum,
+    output carry
+);
+    // Your code here
+endmodule
+```
+
+## Specification
+
+- `sum = a ^ b`
+- `carry = a & b`
+
+## Scoring
+
+- Functional correctness: 100%

bundles/L1_basic/007_half_adder/testbench.v

@@ -0,0 +1,16 @@
+`timescale 1ns/1ps
+module tb_half_adder;
+    reg a, b;
+    wire sum, carry;
+    half_adder uut(.a(a), .b(b), .sum(sum), .carry(carry));
+    integer pass_count = 0;
+    integer fail_count = 0;
+    initial begin
+        a=0; b=0; #10; if (sum===1'b0 && carry===1'b0) pass_count=pass_count+1; else fail_count=fail_count+1;
+        a=0; b=1; #10; if (sum===1'b1 && carry===1'b0) pass_count=pass_count+1; else fail_count=fail_count+1;
+        a=1; b=0; #10; if (sum===1'b1 && carry===1'b0) pass_count=pass_count+1; else fail_count=fail_count+1;
+        a=1; b=1; #10; if (sum===1'b0 && carry===1'b1) pass_count=pass_count+1; else fail_count=fail_count+1;
+        if (fail_count==0) $display("TEST PASSED"); else $display("TEST FAILED");
+        $finish;
+    end
+endmodule

bundles/L1_basic/008_full_adder/config.yaml

@@ -0,0 +1,34 @@
+problem_id: "008"
+title: "8-bit Adder"
+level: 1
+category: "arithmetic"
+description: "Implement an 8-bit adder with carry"
+
+module_name: "adder8"
+ports:
+  a:
+    direction: "input"
+    width: "8"
+  b:
+    direction: "input"
+    width: "8"
+  cin:
+    direction: "input"
+    width: "1"
+  sum:
+    direction: "output"
+    width: "8"
+  cout:
+    direction: "output"
+    width: "1"
+
+testbench_file: "testbench.v"
+timeout_compile: 10
+timeout_simulate: 10
+
+require_synthesis: false
+check_waveform: false
+
+weight_functional: 1.0
+weight_synthesis: 0.0
+weight_resource: 0.0

bundles/L1_basic/008_full_adder/problem.md

@@ -0,0 +1,31 @@
+# Problem 008: 8-bit Adder
+
+## Description
+
+Implement an 8-bit adder with carry output.
+
+## Module Interface
+
+```verilog
+module adder8(
+    input [7:0] a,
+    input [7:0] b,
+    input cin,
+    output [7:0] sum,
+    output cout
+);
+    // Your code here
+endmodule
+```
+
+## Specification
+
+- Compute `{cout, sum} = a + b + cin`
+- `a`, `b`: 8-bit inputs
+- `cin`: carry input
+- `sum`: 8-bit sum output
+- `cout`: carry output
+
+## Scoring
+
+- Functional correctness: 100%

bundles/L1_basic/008_full_adder/testbench.v

@@ -0,0 +1,83 @@
+`timescale 1ns/1ps
+
+module tb_adder8;
+    reg [7:0] a, b;
+    reg cin;
+    wire [7:0] sum;
+    wire cout;
+
+    adder8 uut (
+        .a(a),
+        .b(b),
+        .cin(cin),
+        .sum(sum),
+        .cout(cout)
+    );
+
+    integer pass_count = 0;
+    integer fail_count = 0;
+    integer i;
+    reg [8:0] expected;
+
+    initial begin
+        $display("Testing 8-bit Adder...");
+
+        // Test cases
+        for (i = 0; i < 50; i = i + 1) begin
+            a = $random;
+            b = $random;
+            cin = $random & 1'b1;
+
+            #10;
+
+            expected = a + b + cin;
+
+            if ({cout, sum} === expected) begin
+                pass_count = pass_count + 1;
+                $display("[PASS] %d + %d + %d = {%b,%h} (expected %h)",
+                         a, b, cin, cout, sum, expected);
+            end else begin
+                fail_count = fail_count + 1;
+                $display("[FAIL] %d + %d + %d = {%b,%h}, expected %h",
+                         a, b, cin, cout, sum, expected);
+            end
+        end
+
+        // Edge cases
+        // Max + Max
+        a = 8'hFF; b = 8'hFF; cin = 1; #10;
+        expected = 9'h1FF;
+        if ({cout, sum} === expected) begin
+            pass_count = pass_count + 1;
+            $display("[PASS] Edge: FF + FF + 1 = {%b,%h}", cout, sum);
+        end else begin
+            fail_count = fail_count + 1;
+            $display("[FAIL] Edge: FF + FF + 1 = {%b,%h}, expected %h", cout, sum, expected);
+        end
+
+        // Zero + Zero
+        a = 8'h00; b = 8'h00; cin = 0; #10;
+        expected = 9'h000;
+        if ({cout, sum} === expected) begin
+            pass_count = pass_count + 1;
+            $display("[PASS] Edge: 00 + 00 + 0 = {%b,%h}", cout, sum);
+        end else begin
+            fail_count = fail_count + 1;
+            $display("[FAIL] Edge: 00 + 00 + 0 = {%b,%h}, expected %h", cout, sum, expected);
+        end
+
+        // Summary
+        $display("");
+        $display("=================================");
+        $display("PASS: %0d", pass_count);
+        $display("FAIL: %0d", fail_count);
+
+        if (fail_count == 0)
+            $display("TEST PASSED");
+        else
+            $display("TEST FAILED");
+        $display("=================================");
+
+        $finish;
+    end
+endmodule

bundles/L1_basic/009_decoder2to4/config.yaml

@@ -0,0 +1,18 @@
+problem_id: "009"
+title: "2-to-4 Decoder"
+level: 1
+category: "basic_decoder"
+description: "Implement a 2-to-4 decoder with enable"
+module_name: "decoder2to4"
+ports:
+  in: { direction: "input", width: "2" }
+  en: { direction: "input", width: "1" }
+  out: { direction: "output", width: "4" }
+testbench_file: "testbench.v"
+timeout_compile: 10
+timeout_simulate: 10
+require_synthesis: false
+check_waveform: false
+weight_functional: 1.0
+weight_synthesis: 0.0
+weight_resource: 0.0

bundles/L1_basic/009_decoder2to4/problem.md

@@ -0,0 +1,30 @@
+# Problem 009: 2-to-4 Decoder
+
+## Description
+
+Implement a 2-to-4 decoder with enable.
+
+## Module Interface
+
+```verilog
+module decoder2to4(
+    input [1:0] in,
+    input en,
+    output [3:0] out
+);
+    // Your code here
+endmodule
+```
+
+## Specification
+
+- When `en = 1`: exactly one bit of `out` is high based on `in`
+  - `in=00`: `out=0001`
+  - `in=01`: `out=0010`
+  - `in=10`: `out=0100`
+  - `in=11`: `out=1000`
+- When `en = 0`: `out = 0000`
+
+## Scoring
+
+- Functional correctness: 100%

bundles/L1_basic/009_decoder2to4/testbench.v

@@ -0,0 +1,23 @@
+`timescale 1ns/1ps
+module tb_decoder2to4;
+    reg [1:0] in;
+    reg en;
+    wire [3:0] out;
+    decoder2to4 uut(.in(in), .en(en), .out(out));
+    integer pass_count = 0;
+    integer fail_count = 0;
+    initial begin
+        // Enable tests
+        en=1; in=2'b00; #10; if (out===4'b0001) pass_count=pass_count+1; else fail_count=fail_count+1;
+        en=1; in=2'b01; #10; if (out===4'b0010) pass_count=pass_count+1; else fail_count=fail_count+1;
+        en=1; in=2'b10; #10; if (out===4'b0100) pass_count=pass_count+1; else fail_count=fail_count+1;
+        en=1; in=2'b11; #10; if (out===4'b1000) pass_count=pass_count+1; else fail_count=fail_count+1;
+        // Disable tests
+        en=0; in=2'b00; #10; if (out===4'b0000) pass_count=pass_count+1; else fail_count=fail_count+1;
+        en=0; in=2'b01; #10; if (out===4'b0000) pass_count=pass_count+1; else fail_count=fail_count+1;
+        en=0; in=2'b10; #10; if (out===4'b0000) pass_count=pass_count+1; else fail_count=fail_count+1;
+        en=0; in=2'b11; #10; if (out===4'b0000) pass_count=pass_count+1; else fail_count=fail_count+1;
+        if (fail_count==0) $display("TEST PASSED"); else $display("TEST FAILED");
+        $finish;
+    end
+endmodule

bundles/L1_basic/010_priority_encoder/config.yaml

@@ -0,0 +1,18 @@
+problem_id: "010"
+title: "Priority Encoder"
+level: 1
+category: "basic_encoder"
+description: "Implement a 4-bit priority encoder"
+module_name: "priority_encoder"
+ports:
+  in: { direction: "input", width: "4" }
+  out: { direction: "output", width: "2" }
+  valid: { direction: "output", width: "1" }
+testbench_file: "testbench.v"
+timeout_compile: 10
+timeout_simulate: 10
+require_synthesis: false
+check_waveform: false
+weight_functional: 1.0
+weight_synthesis: 0.0
+weight_resource: 0.0

bundles/L1_basic/010_priority_encoder/problem.md

@@ -0,0 +1,28 @@
+# Problem 010: Priority Encoder
+
+## Description
+
+Implement a 4-bit priority encoder.
+
+## Module Interface
+
+```verilog
+module priority_encoder(
+    input [3:0] in,
+    output reg [1:0] out,
+    output valid
+);
+    // Your code here
+endmodule
+```
+
+## Specification
+
+- Output encodes the highest-priority (most significant) active input
+- `in[3]` has highest priority, `in[0]` has lowest
+- `valid` is high when any input is active
+- When no input is active: `out = 00`, `valid = 0`
+
+## Scoring
+
+- Functional correctness: 100%

bundles/L1_basic/010_priority_encoder/testbench.v

@@ -0,0 +1,23 @@
+`timescale 1ns/1ps
+module tb_priority_encoder;
+    reg [3:0] in;
+    wire [1:0] out;
+    wire valid;
+    priority_encoder uut(.in(in), .out(out), .valid(valid));
+    integer pass_count = 0;
+    integer fail_count = 0;
+    initial begin
+        in=4'b0000; #10; if (valid===1'b0 && out===2'b00) pass_count=pass_count+1; else fail_count=fail_count+1;
+        in=4'b0001; #10; if (valid===1'b1 && out===2'b00) pass_count=pass_count+1; else fail_count=fail_count+1;
+        in=4'b0010; #10; if (valid===1'b1 && out===2'b01) pass_count=pass_count+1; else fail_count=fail_count+1;
+        in=4'b0100; #10; if (valid===1'b1 && out===2'b10) pass_count=pass_count+1; else fail_count=fail_count+1;
+        in=4'b1000; #10; if (valid===1'b1 && out===2'b11) pass_count=pass_count+1; else fail_count=fail_count+1;
+        in=4'b0011; #10; if (valid===1'b1 && out===2'b01) pass_count=pass_count+1; else fail_count=fail_count+1;
+        in=4'b0110; #10; if (valid===1'b1 && out===2'b10) pass_count=pass_count+1; else fail_count=fail_count+1;
+        in=4'b1111; #10; if (valid===1'b1 && out===2'b11) pass_count=pass_count+1; else fail_count=fail_count+1;
+        in=4'b1010; #10; if (valid===1'b1 && out===2'b11) pass_count=pass_count+1; else fail_count=fail_count+1;
+        in=4'b0101; #10; if (valid===1'b1 && out===2'b10) pass_count=pass_count+1; else fail_count=fail_count+1;
+        if (fail_count==0) $display("TEST PASSED"); else $display("TEST FAILED");
+        $finish;
+    end
+endmodule

bundles/L1_basic/011_not_gate/config.yaml

@@ -0,0 +1,21 @@
+problem_id: '011'
+title: NOT Gate
+level: 1
+category: basic_gates
+description: Implement a NOT gate
+module_name: not_gate
+ports:
+  a:
+    direction: input
+    width: 1
+  y:
+    direction: output
+    width: 1
+testbench_file: testbench.v
+timeout_compile: 10
+timeout_simulate: 30
+require_synthesis: false
+check_waveform: false
+weight_functional: 1.0
+weight_synthesis: 0.0
+weight_resource: 0.0

bundles/L1_basic/011_not_gate/problem.md

@@ -0,0 +1,35 @@
+# NOT Gate
+
+**Level**: 1 (Basic Combinational Logic)
+**Category**: basic_gates
+
+## Problem Description
+
+Implement a NOT gate
+
+## Module Interface
+
+```verilog
+module not_gate(
+    input a,
+    output y
+);
+```
+
+## Specifications
+
+**Inputs:**
+- `a` (1-bit): Input signal
+
+**Outputs:**
+- `y` (1-bit): Output signal
+
+## Examples
+
+See testbench for comprehensive test cases.
+
+## Notes
+
+- This is a purely combinational circuit
+- No clock or reset signals needed
+- Output should be valid after propagation delay

bundles/L1_basic/011_not_gate/testbench.v

@@ -0,0 +1,52 @@
+`timescale 1ns/1ps
+
+module tb_not_gate;
+    reg a;
+    wire y;
+
+    // Instantiate the module under test
+    not_gate uut (
+
+        .a(a),
+        .y(y)
+    );
+
+    integer pass_count = 0;
+    integer fail_count = 0;
+
+    initial begin
+        $display("Testing not_gate...");
+
+        // Test 1
+        a = 1'b0; #10;
+        if ((y === 1'b1)) begin
+            pass_count = pass_count + 1;
+        end else begin
+            fail_count = fail_count + 1;
+            $display("[FAIL] Test 1");
+        end
+        // Test 2
+        a = 1'b1; #10;
+        if ((y === 1'b0)) begin
+            pass_count = pass_count + 1;
+        end else begin
+            fail_count = fail_count + 1;
+            $display("[FAIL] Test 2");
+        end
+
+        // Summary
+        $display("");
+        $display("=================================");
+        $display("PASS: %0d", pass_count);
+        $display("FAIL: %0d", fail_count);
+
+        if (fail_count == 0) begin
+            $display("TEST PASSED");
+        end else begin
+            $display("TEST FAILED");
+        end
+        $display("=================================");
+
+        $finish;
+    end
+endmodule

bundles/L1_basic/012_and_gate/config.yaml

@@ -0,0 +1,24 @@
+problem_id: '012'
+title: AND Gate
+level: 1
+category: basic_gates
+description: Implement a 2-input AND gate
+module_name: and_gate
+ports:
+  a:
+    direction: input
+    width: 1
+  b:
+    direction: input
+    width: 1
+  y:
+    direction: output
+    width: 1
+testbench_file: testbench.v
+timeout_compile: 10
+timeout_simulate: 30
+require_synthesis: false
+check_waveform: false
+weight_functional: 1.0
+weight_synthesis: 0.0
+weight_resource: 0.0

bundles/L1_basic/012_and_gate/problem.md

@@ -0,0 +1,36 @@
+# AND Gate
+
+**Level**: 1 (Basic Combinational Logic)
+**Category**: basic_gates
+
+## Problem Description
+
+Implement a 2-input AND gate
+
+## Module Interface
+
+```verilog
+module and_gate(
+    input a, input b,
+    output y
+);
+```
+
+## Specifications
+
+**Inputs:**
+- `a` (1-bit): Input signal
+- `b` (1-bit): Input signal
+
+**Outputs:**
+- `y` (1-bit): Output signal
+
+## Examples
+
+See testbench for comprehensive test cases.
+
+## Notes
+
+- This is a purely combinational circuit
+- No clock or reset signals needed
+- Output should be valid after propagation delay

bundles/L1_basic/012_and_gate/testbench.v

@@ -0,0 +1,70 @@
+`timescale 1ns/1ps
+
+module tb_and_gate;
+    reg a;
+    reg b;
+    wire y;
+
+    // Instantiate the module under test
+    and_gate uut (
+
+        .a(a),
+        .b(b),
+        .y(y)
+    );
+
+    integer pass_count = 0;
+    integer fail_count = 0;
+
+    initial begin
+        $display("Testing and_gate...");
+
+        // Test 1
+        a = 1'b0; b = 1'b0; #10;
+        if ((y === 1'b0)) begin
+            pass_count = pass_count + 1;
+        end else begin
+            fail_count = fail_count + 1;
+            $display("[FAIL] Test 1");
+        end
+        // Test 2
+        a = 1'b1; b = 1'b0; #10;
+        if ((y === 1'b0)) begin
+            pass_count = pass_count + 1;
+        end else begin
+            fail_count = fail_count + 1;
+            $display("[FAIL] Test 2");
+        end
+        // Test 3
+        a = 1'b0; b = 1'b1; #10;
+        if ((y === 1'b0)) begin
+            pass_count = pass_count + 1;
+        end else begin
+            fail_count = fail_count + 1;
+            $display("[FAIL] Test 3");
+        end
+        // Test 4
+        a = 1'b1; b = 1'b1; #10;
+        if ((y === 1'b1)) begin
+            pass_count = pass_count + 1;
+        end else begin
+            fail_count = fail_count + 1;
+            $display("[FAIL] Test 4");
+        end
+
+        // Summary
+        $display("");
+        $display("=================================");
+        $display("PASS: %0d", pass_count);
+        $display("FAIL: %0d", fail_count);
+
+        if (fail_count == 0) begin
+            $display("TEST PASSED");
+        end else begin
+            $display("TEST FAILED");
+        end
+        $display("=================================");
+
+        $finish;
+    end
+endmodule

bundles/L1_basic/013_or_gate/config.yaml

@@ -0,0 +1,24 @@
+problem_id: '013'
+title: OR Gate
+level: 1
+category: basic_gates
+description: Implement a 2-input OR gate
+module_name: or_gate
+ports:
+  a:
+    direction: input
+    width: 1
+  b:
+    direction: input
+    width: 1
+  y:
+    direction: output
+    width: 1
+testbench_file: testbench.v
+timeout_compile: 10
+timeout_simulate: 30
+require_synthesis: false
+check_waveform: false
+weight_functional: 1.0
+weight_synthesis: 0.0
+weight_resource: 0.0

bundles/L1_basic/013_or_gate/problem.md

@@ -0,0 +1,36 @@
+# OR Gate
+
+**Level**: 1 (Basic Combinational Logic)
+**Category**: basic_gates
+
+## Problem Description
+
+Implement a 2-input OR gate
+
+## Module Interface
+
+```verilog
+module or_gate(
+    input a, input b,
+    output y
+);
+```
+
+## Specifications
+
+**Inputs:**
+- `a` (1-bit): Input signal
+- `b` (1-bit): Input signal
+
+**Outputs:**
+- `y` (1-bit): Output signal
+
+## Examples
+
+See testbench for comprehensive test cases.
+
+## Notes
+
+- This is a purely combinational circuit
+- No clock or reset signals needed
+- Output should be valid after propagation delay

bundles/L1_basic/013_or_gate/testbench.v

@@ -0,0 +1,70 @@
+`timescale 1ns/1ps
+
+module tb_or_gate;
+    reg a;
+    reg b;
+    wire y;
+
+    // Instantiate the module under test
+    or_gate uut (
+
+        .a(a),
+        .b(b),
+        .y(y)
+    );
+
+    integer pass_count = 0;
+    integer fail_count = 0;
+
+    initial begin
+        $display("Testing or_gate...");
+
+        // Test 1
+        a = 1'b0; b = 1'b0; #10;
+        if ((y === 1'b0)) begin
+            pass_count = pass_count + 1;
+        end else begin
+            fail_count = fail_count + 1;
+            $display("[FAIL] Test 1");
+        end
+        // Test 2
+        a = 1'b1; b = 1'b0; #10;
+        if ((y === 1'b1)) begin
+            pass_count = pass_count + 1;
+        end else begin
+            fail_count = fail_count + 1;
+            $display("[FAIL] Test 2");
+        end
+        // Test 3
+        a = 1'b0; b = 1'b1; #10;
+        if ((y === 1'b1)) begin
+            pass_count = pass_count + 1;
+        end else begin
+            fail_count = fail_count + 1;
+            $display("[FAIL] Test 3");
+        end
+        // Test 4
+        a = 1'b1; b = 1'b1; #10;
+        if ((y === 1'b1)) begin
+            pass_count = pass_count + 1;
+        end else begin
+            fail_count = fail_count + 1;
+            $display("[FAIL] Test 4");
+        end
+
+        // Summary
+        $display("");
+        $display("=================================");
+        $display("PASS: %0d", pass_count);
+        $display("FAIL: %0d", fail_count);
+
+        if (fail_count == 0) begin
+            $display("TEST PASSED");
+        end else begin
+            $display("TEST FAILED");
+        end
+        $display("=================================");
+
+        $finish;
+    end
+endmodule

bundles/L1_basic/014_xor_gate/config.yaml

@@ -0,0 +1,24 @@
+problem_id: '014'
+title: XOR Gate
+level: 1
+category: basic_gates
+description: Implement a 2-input XOR gate
+module_name: xor_gate
+ports:
+  a:
+    direction: input
+    width: 1
+  b:
+    direction: input
+    width: 1
+  y:
+    direction: output
+    width: 1
+testbench_file: testbench.v
+timeout_compile: 10
+timeout_simulate: 30
+require_synthesis: false
+check_waveform: false
+weight_functional: 1.0
+weight_synthesis: 0.0
+weight_resource: 0.0

bundles/L1_basic/014_xor_gate/problem.md

@@ -0,0 +1,36 @@
+# XOR Gate
+
+**Level**: 1 (Basic Combinational Logic)
+**Category**: basic_gates
+
+## Problem Description
+
+Implement a 2-input XOR gate
+
+## Module Interface
+
+```verilog
+module xor_gate(
+    input a, input b,
+    output y
+);
+```
+
+## Specifications
+
+**Inputs:**
+- `a` (1-bit): Input signal
+- `b` (1-bit): Input signal
+
+**Outputs:**
+- `y` (1-bit): Output signal
+
+## Examples
+
+See testbench for comprehensive test cases.
+
+## Notes
+
+- This is a purely combinational circuit
+- No clock or reset signals needed
+- Output should be valid after propagation delay

bundles/L1_basic/014_xor_gate/testbench.v

@@ -0,0 +1,70 @@
+`timescale 1ns/1ps
+
+module tb_xor_gate;
+    reg a;
+    reg b;
+    wire y;
+
+    // Instantiate the module under test
+    xor_gate uut (
+
+        .a(a),
+        .b(b),
+        .y(y)
+    );
+
+    integer pass_count = 0;
+    integer fail_count = 0;
+
+    initial begin
+        $display("Testing xor_gate...");
+
+        // Test 1
+        a = 1'b0; b = 1'b0; #10;
+        if ((y === 1'b0)) begin
+            pass_count = pass_count + 1;
+        end else begin
+            fail_count = fail_count + 1;
+            $display("[FAIL] Test 1");
+        end
+        // Test 2
+        a = 1'b1; b = 1'b0; #10;
+        if ((y === 1'b1)) begin
+            pass_count = pass_count + 1;
+        end else begin
+            fail_count = fail_count + 1;
+            $display("[FAIL] Test 2");
+        end
+        // Test 3
+        a = 1'b0; b = 1'b1; #10;
+        if ((y === 1'b1)) begin
+            pass_count = pass_count + 1;
+        end else begin
+            fail_count = fail_count + 1;
+            $display("[FAIL] Test 3");
+        end
+        // Test 4
+        a = 1'b1; b = 1'b1; #10;
+        if ((y === 1'b0)) begin
+            pass_count = pass_count + 1;
+        end else begin
+            fail_count = fail_count + 1;
+            $display("[FAIL] Test 4");
+        end
+
+        // Summary
+        $display("");
+        $display("=================================");
+        $display("PASS: %0d", pass_count);
+        $display("FAIL: %0d", fail_count);
+
+        if (fail_count == 0) begin
+            $display("TEST PASSED");
+        end else begin
+            $display("TEST FAILED");
+        end
+        $display("=================================");
+
+        $finish;
+    end
+endmodule

bundles/L1_basic/015_nand_gate/config.yaml

@@ -0,0 +1,24 @@
+problem_id: '015'
+title: NAND Gate
+level: 1
+category: basic_gates
+description: Implement a 2-input NAND gate
+module_name: nand_gate
+ports:
+  a:
+    direction: input
+    width: 1
+  b:
+    direction: input
+    width: 1
+  y:
+    direction: output
+    width: 1
+testbench_file: testbench.v
+timeout_compile: 10
+timeout_simulate: 30
+require_synthesis: false
+check_waveform: false
+weight_functional: 1.0
+weight_synthesis: 0.0
+weight_resource: 0.0

bundles/L1_basic/015_nand_gate/problem.md

@@ -0,0 +1,36 @@
+# NAND Gate
+
+**Level**: 1 (Basic Combinational Logic)
+**Category**: basic_gates
+
+## Problem Description
+
+Implement a 2-input NAND gate
+
+## Module Interface
+
+```verilog
+module nand_gate(
+    input a, input b,
+    output y
+);
+```
+
+## Specifications
+
+**Inputs:**
+- `a` (1-bit): Input signal
+- `b` (1-bit): Input signal
+
+**Outputs:**
+- `y` (1-bit): Output signal
+
+## Examples
+
+See testbench for comprehensive test cases.
+
+## Notes
+
+- This is a purely combinational circuit
+- No clock or reset signals needed
+- Output should be valid after propagation delay

bundles/L1_basic/015_nand_gate/testbench.v

@@ -0,0 +1,70 @@
+`timescale 1ns/1ps
+
+module tb_nand_gate;
+    reg a;
+    reg b;
+    wire y;
+
+    // Instantiate the module under test
+    nand_gate uut (
+
+        .a(a),
+        .b(b),
+        .y(y)
+    );
+
+    integer pass_count = 0;
+    integer fail_count = 0;
+
+    initial begin
+        $display("Testing nand_gate...");
+
+        // Test 1
+        a = 1'b0; b = 1'b0; #10;
+        if ((y === 1'b1)) begin
+            pass_count = pass_count + 1;
+        end else begin
+            fail_count = fail_count + 1;
+            $display("[FAIL] Test 1");
+        end
+        // Test 2
+        a = 1'b1; b = 1'b0; #10;
+        if ((y === 1'b1)) begin
+            pass_count = pass_count + 1;
+        end else begin
+            fail_count = fail_count + 1;
+            $display("[FAIL] Test 2");
+        end
+        // Test 3
+        a = 1'b0; b = 1'b1; #10;
+        if ((y === 1'b1)) begin
+            pass_count = pass_count + 1;
+        end else begin
+            fail_count = fail_count + 1;
+            $display("[FAIL] Test 3");
+        end
+        // Test 4
+        a = 1'b1; b = 1'b1; #10;
+        if ((y === 1'b0)) begin
+            pass_count = pass_count + 1;
+        end else begin
+            fail_count = fail_count + 1;
+            $display("[FAIL] Test 4");
+        end
+
+        // Summary
+        $display("");
+        $display("=================================");
+        $display("PASS: %0d", pass_count);
+        $display("FAIL: %0d", fail_count);
+
+        if (fail_count == 0) begin
+            $display("TEST PASSED");
+        end else begin
+            $display("TEST FAILED");
+        end
+        $display("=================================");
+
+        $finish;
+    end
+endmodule