--- license: apache-2.0 language: - en task_categories: - graph-ml - tabular-regression - tabular-classification size_categories: - 100K")`. | Family | Samples | Graphs | Sources | |---|---:|---:|---| | operational_amplifier | 70,595 | 60,496 | analoggym, analogtobi, ocb | | switched_capacitor_sampler | 18,236 | 871 | analogtobi | | ldo | 9,517 | 454 | analoggym, analogtobi | | bandgap_reference | 7,101 | 343 | analoggym, analogtobi | | power_converter | 5,498 | 269 | analogtobi | | vco | 1,515 | 78 | analogtobi | | current_mirror_bias | 1,428 | 68 | analogtobi | | feedback | 966 | 46 | analogtobi | | lna | 821 | 40 | analogtobi | | frequency_response | 777 | 37 | analogtobi | | high_perf_opamp | 767 | 37 | analogtobi | | noise | 735 | 35 | analogtobi | | mixer | 708 | 34 | analogtobi | | switched_capacitor | 693 | 33 | analogtobi | | oscillator | 651 | 39 | analogtobi | | single_stage_amplifier | 546 | 26 | analogtobi | | stability_compensation | 525 | 25 | analogtobi | | cmos_amplifier | 525 | 25 | analogtobi | | power_amplifier | 504 | 24 | analogtobi | | frequency_synthesizer | 462 | 22 | analogtobi | | differential_amplifier | 462 | 22 | analogtobi | | continuous_time_filter | 437 | 21 | analogtobi | | analog_subcircuit | 420 | 20 | analogtobi | | current_mirror_amplifier | 378 | 18 | analogtobi | | sample_hold | 357 | 17 | analogtobi | | output_stage | 336 | 16 | analogtobi | | transceiver | 315 | 15 | analogtobi | | cmos_opamp | 315 | 15 | analogtobi | | rf_basic | 252 | 12 | analogtobi | | single_transistor_amplifier | 252 | 12 | analogtobi | | nanometer_design | 252 | 12 | analogtobi | | fully_differential_opamp | 252 | 12 | analogtobi | | comparator | 236 | 24 | analogtobi | | misc | 231 | 11 | analogtobi | | voltage_regulator | 231 | 11 | analogtobi | | unknown | 189 | 9 | analogtobi | | nonlinearity_mismatch | 147 | 7 | analogtobi | | nonlinear | 126 | 6 | analogtobi | | adc | 71 | 4 | analogtobi | | transconductance_amplifier | 63 | 3 | analogtobi | | layout_packaging | 63 | 3 | analogtobi | | dac | 63 | 3 | analogtobi | | power | 42 | 2 | analogtobi | | current_source | 42 | 2 | analogtobi | | converter | 41 | 2 | analogtobi | | cmos_processing | 21 | 1 | analogtobi | | filter | 21 | 1 | analogtobi | | fractional_n_synthesizer | 21 | 1 | analogtobi | | charge_pump | 20 | 1 | analoggym | **Observations:** - **Opamps dominate by sample count** (70.5K / 128.6K = 55%) due to OCB's 60K-graph contribution, but only 3 of the 49 families appear in more than one upstream source (`operational_amplifier`, `ldo`, `bandgap_reference`). The 46 other families are single-source (45 AnalogToBi-only, 1 AnalogGym-only). - **Only `operational_amplifier` spans all three upstream sources.** `ldo` and `bandgap_reference` each span two (analoggym + analogtobi) — useful for cross-source generalisation tests on those families. - **Long tail** — 20 families have <500 samples. Useful for few-shot / meta-learning evaluation but small for end-to-end training in isolation. - **`charge_pump`** is exclusive to `analoggym` and has only 20 samples (1 graph × 20 sweeps) — the most specialised class in the corpus. ### Data Instances One row: ```json { "circuit_id": "analogtobi_0705_s003", "base_circuit_id": "analogtobi_0705", "topology": "operational_amplifier", "source_dataset": "analogtobi", "pdk": "sky130", "sim_params": "{\"vdd\": 1.8, \"vth\": 0.5, \"vov\": 0.2, \"testbench\": \"OpampTestbench\", \"sweep\": {\"design\": {\"w_scale\": 1.34, \"l_scale\": 0.92}, \"test\": {\"ib_scale\": 0.67, \"cl_F\": 4.2e-12}}, ...}", "converged": true, "error": "", "metrics": "{\"dc_gain_dB\": 38.2, \"ugf_Hz\": 1.25e6, \"phase_at_ugf_deg\": 52.3, \"power_W\": 0.00083, \"vout_dc_V\": 0.87, \"vdd_current_A\": 4.6e-4}", "netlist_json": "{\"nets\":[{\"name\":\"VDD\",\"role\":\"supply_pos\",\"external\":true},...],\"devices\":[{\"name\":\"M1\",\"type\":\"nmos\",\"model\":\"nmos4\",\"pins\":[{\"role\":\"D\",\"net\":\"vout\"},{\"role\":\"G\",\"net\":\"vinn\"},{\"role\":\"S\",\"net\":\"tail\"},{\"role\":\"B\",\"net\":\"VSS\"}],\"params\":{}},...]}" } ``` ### Data Fields | Column | Type | Description | |---|---|---| | `circuit_id` | string | Unique row id. Sweep siblings share a `base_circuit_id` prefix + `_sNNN` suffix. | | `base_circuit_id` | string | Structural identity, shared across sweep siblings of one graph. | | `topology` | string | Coarse topology family (one of 49). | | `source_dataset` | string | `ocb`, `analogtobi`, or `analoggym`. | | `pdk` | string | Always `sky130` in this release. | | `sim_params` | string (JSON) | Full simulation parameters for reproducibility: PDK config (VDD, Vth, Vov, model_map), testbench class, convergence options, and sweep point `{design: {...}, test: {...}}`. | | `converged` | bool | Whether the ngspice DC operating point + requested analyses completed. | | `error` | string | Failure mode if `converged=false`: `no_convergence`, `singular_matrix`, `timeout`, `sim_error`, `no_output_port`. | | `metrics` | string (JSON) | All output metrics for this row. Schema varies by testbench (op-amp vs LDO vs bandgap, etc.). | | `netlist_json` | string (JSON) | Lossless typed-pin graph primitive — see "Graph Representation" below. | ### Graph Representation Each row's `netlist_json` carries a canonical primitive that can be projected into any of the three common PyG shapes (bipartite / bus / node-centric) at load time — without re-parsing the SPICE text. Consumers parse the JSON string and build the representation they need; an example bus-style projection is shown in the "How to Use" section below. Primitive schema (compact JSON stored per row): ```json { "nets": [ {"name": "VDD", "role": "supply_pos", "external": true}, {"name": "NET1", "role": "internal", "external": false} ], "devices": [ {"name": "M1", "type": "nmos", "model": "nmos4", "pins": [{"role": "D", "net": "NET1"}, {"role": "G", "net": "VIN"}, {"role": "S", "net": "VSS"}, {"role": "B", "net": "VSS"}], "params": {"W": 10.0, "L": 0.5}} ] } ``` Pin roles: MOSFET `D G S B`; BJT `C B E SUB`; 2-terminal `P N`. Device types: `nmos pmos npn pnp res cap ind isrc vsrc other`. ## Dataset Creation ### Curation Rationale Open-source analog circuit design tooling has lacked a labelled benchmark corpus at the scale GNNs expect. Existing datasets are either topology-only (AnalogToBi: 3,350 textbook graphs, no sizing), Cadence-locked (AnalogGym PLL, AICircuit), or behavioural-only (OCB: 60K opamp graphs without transistor-level metrics). This dataset unifies three permissively-licensed upstream sources under a single open PDK (SKY130) and simulator (ngspice), so the entire pipeline — netlist → simulator → labels → graph representation — is reproducible from open source. ### Source Data **OCB** (Open Circuit Benchmark, 60,000 graphs). Zehao Dong et al., "CktGNN: Circuit Graph Neural Network for Electronic Design Automation", ICLR 2023. Behavioural `(gm, R, C)` opamp subgraphs remapped to SKY130 transistor-level netlists using a library of equivalent sub-circuits. MIT License. The 60K graphs come from **two upstream sub-benchmarks** which this release keeps pooled under the `ocb` `source_dataset` value but remains distinguishable via the `circuit_id` prefix: - **Ckt-Bench-101** (10,000 graphs, `circuit_id` like `ocb_sky130_101_*`) — the paper's diversity-focused sample; per the CktGNN authors' data-generation procedure, topologies here are drawn broadly across the opamp graph space without a performance prior. - **Ckt-Bench-301** (50,000 graphs, `circuit_id` like `ocb_sky130_301_*`) — generated by a Bayesian-optimisation search in the CktGNN graph latent space. This is **not an i.i.d. sample**: graphs were selected because the BO thought they'd score high on the FoM metric, so the 301 subset is distribution-shifted toward high-performance opamps. Downstream models trained on it inherit that prior — useful if you want performance-focused training, a caveat if you want an unbiased opamp-graph distribution. Filter with `circuit_id` prefix if you want just one: ```python ds_101 = ds.filter(lambda r: r["circuit_id"].startswith("ocb_sky130_101_")) # 10K diverse ds_301 = ds.filter(lambda r: r["circuit_id"].startswith("ocb_sky130_301_")) # 50K BO-curated ``` **AnalogToBi** (3,350 topologies upstream, 3,329 ingested across 48 families). Seungmin Lee et al. Textbook + paper analog circuits (Razavi, Camenzind, Carusone/Johns/Martin, Gray/Hurst/Lewis/Meyer, Allen/Holberg, RF Microelectronics, plus assorted papers). Topology-only — our pipeline supplies default sizing and a 20-LHS sweep per topology. MIT License. **AnalogGym** (25 ngspice-ready topologies: 16 amplifiers + 4 LDO variants + 4 voltage references + 1 charge pump, across 4 families). CODA-Team, ICCAD 2024. Native SKY130 netlists with upstream sizing. Charge-pump is a structural homage — the upstream targets SMIC 130 nm devices at 3.3V, remapped here to SKY130 1.8V core devices; AnalogGym's published current-mismatch targets are not reproducible at this voltage. BSD 3-Clause. **PDK.** SkyWater SKY130 (Apache 2.0), accessed via [volare](https://github.com/efabless/volare). Only `.lib` and `.model` references appear in the shipped netlists; no PDK model files are redistributed as part of this dataset. ### Simulation Pipeline Every row was generated by the same deterministic pipeline: 1. **Parse** upstream netlists via per-source readers — one reader per source handles Spectre→ngspice dialect conversion, model-name remapping (proprietary PDK tokens → SKY130 equivalents), and the ingest of AnalogGym's Markdown-inlined voltage-reference netlists. 2. **Emit testbench** per topology type: op-amp AC, LDO AC-on-VDD, bandgap DC+temp-sweep, comparator transient, VCO transient, mixer AC+LO, PA AC+50Ω. 3. **Bias inference** via graph-distance BFS + Vth/Vov formulas, plus self-biasing current mirrors for gate-only bias ports (follows AnalogToBi Appendix G). 4. **Apply 20-point LHS sweep** over `(W_scale ∈ [0.3,3.0], L_scale ∈ [0.7,1.5], I_bias_scale ∈ [0.3,3.0], C_load ∈ [10fF,100pF])` with a post-sweep `W_MAX = 500µm` clamp to stay inside BSIM4 bin coverage. 5. **Run ngspice 46** with per-PDK convergence options (`gmin=1e-10`, `gminsteps=10` for SKY130) and a 60-second per-sim timeout. 6. **Extract metrics** from `.measure` statements + control-block prints. 7. **Merge** per-batch outputs globally with group-aware splits (`base_circuit_id`, seed 42) applied once across all sources. The `sim_params` column on every row captures the full reproducibility-relevant configuration (PDK tokens, testbench class, convergence options, sweep point); `netlist_json` captures the exact transistor-level graph that went into ngspice. Together with the upstream raw data, these are sufficient to reproduce any row with the open-source toolchain listed above. ### Personal and Sensitive Information None. The dataset contains circuit netlists and their simulated electrical metrics; no personal data, no text generated by humans beyond device/net naming conventions. ## Considerations for Using the Data ### Social Impact Open analog design tooling is a long-standing gap in EDA. A labelled benchmark at this scale enables researchers without Cadence licences to develop and evaluate analog-domain GNNs, lowering the barrier to entry for analog circuit ML. We expect primary uptake in academic circuit-design labs and hobbyist/open-source hardware communities. ### Discussion of Biases - **Opamp over-representation.** After rebalancing with 20× sweeps, op-amps still account for ~55% of rows due to OCB's 60K-graph contribution. Training a `(graph, metrics)` model without stratified sampling will bias the encoder toward opamp features. The long tail of 48 non-opamp families averages ~1,200 rows each — enough for within-family `metrics → sizing` work but small for transfer-learning claims. - **OCB-301 is BO-curated, not random.** 50K of the 60K OCB rows come from Ckt-Bench-301, which the original CktGNN authors generated via Bayesian optimisation in the graph latent space. That sub-corpus is distribution-shifted toward high-FoM opamps; 301 is not an unbiased sample of the opamp graph space. Ckt-Bench-101 (10K rows, `ocb_sky130_101_*`) is the upstream's diversity-focused sample and is closer to uniform. Train on `ocb` indiscriminately and the opamp encoder inherits the 301 prior. Filter by the `circuit_id` prefix if you want to remove that bias. - **Default-sizing artefacts.** AnalogToBi ships topology-only; our pipeline supplies uniform default W = 10 µm, L = 0.5 µm on the 1× baseline rows. Circuits where performance depends on heterogeneous sizing (cascode headroom, compensation-cap tuning) are under-represented at their intended operating points. Use the 20× LHS sweep rows (the majority of AnalogToBi rows) for downstream work that needs realistic sizings. - **Testbench-topology mismatch for non-amplifier circuits.** Many non-opamp topologies (switched-capacitor samplers, filters, mixers, LNAs, sample-hold, etc.) are simulated with the op-amp AC testbench — the only testbench type applied to most AnalogToBi families in this release. Their `metrics` reflect the AC response of the circuit, which is a real physical quantity but often not the metric a circuit engineer would quote for that topology (e.g., SC samplers don't have a meaningful small-signal gain). The concrete symptom: **~22% of converged rows have `|dc_gain_dB| < 0.1`**, dominated by OCB opamps (19K rows with degenerate structure after behavioural→transistor remap) and AnalogToBi SC samplers (5.6K rows). Treat these as testbench-AC measurements, not as the topology's canonical performance metric. - **Family-specific `metrics` keys.** Not every row carries `dc_gain_dB`. 7.6% of converged rows instead emit testbench-appropriate metrics: bandgaps give `vout_27 / vout_m40 / vout_125` (temperature sweep), VCOs give `osc_freq_Hz`, comparators and the charge-pump give `prop_delay_s`. See `dataset_schema.md` for the full per-testbench metric catalogue. - **Single-PDK.** Everything is SKY130 1.8V. Models trained here should not be assumed to transfer to other process nodes without explicit retraining. - **Convergence bias.** The 2,183 failed rows are preserved in the `failed` split, not silently dropped. Rows there carry the same `netlist_json` as converged rows but empty `metrics`, letting consumers study the boundary between convergent and divergent circuits. ### Other Known Limitations - `sim_params.sweep.design.w_scale` and `l_scale` are applied uniformly across every MOSFET. Real circuit design varies W and L per-transistor; our sweep is a global perturbation, not a fine-grained sizing exploration. - AnalogGym's 4 voltage-reference circuits come with redacted-PDK netlists; our pipeline strips layout-dependent parameters (`sd`, `ad`, `ps`, etc.) and remaps SMIC/proprietary model-name tokens to SKY130. The graph structure is intact; absolute metric values reflect SKY130, not the upstream process. ## Additional Information ### Dataset Curators Philip Pilgerstorfer (`pphilip` on hf). ### Licensing Information This dataset is released under the **Apache License 2.0** (`LICENSE`). Upstream source-dataset licences are included in `LICENSES/` and must be carried forward by any downstream redistribution: - `LICENSES/LICENSE-OCB`: MIT (CktGNN authors, Washington University in St. Louis) - `LICENSES/LICENSE-AnalogToBi`: MIT (Seungmin Lee et al.) - `LICENSES/LICENSE-AnalogGym`: BSD 3-Clause (CODA-Team) ### Citation Information If you use this dataset, please cite it and all upstream sources: ```bibtex @dataset{pilgerstorfer_analog_circuits_sky130, title = {{Analog SPICE Circuits on SKY130}}, author = {Pilgerstorfer, Philip}, year = 2026, publisher = {Hugging Face}, url = {https://huggingface.co/datasets/pphilip/analog-circuits-sky130} } @inproceedings{dong2023cktgnn, title = {{CktGNN}: Circuit Graph Neural Network for Electronic Design Automation}, author = {Dong, Zehao and Cao, Weidong and Zhang, Muhan and Tao, Dacheng and Chen, Yixin and Zhang, Xuan}, booktitle = {International Conference on Learning Representations (ICLR)}, year = 2023 } @misc{lee_analogtobi, title = {{AnalogToBi}: A Dataset of Analog Circuit Schematics}, author = {Lee, Seungmin and others}, howpublished = {\url{https://github.com/Seungmin0825/AnalogToBi}}, note = {MIT License} } @inproceedings{coda2024analoggym, title = {{AnalogGym}: An Open and Practical Testing Suite for Analog Circuit Synthesis}, author = {{CODA-Team}}, booktitle = {International Conference on Computer-Aided Design (ICCAD)}, year = 2024, doi = {10.1145/3676536.3697117} } ``` ### Contributions Thanks to the CktGNN, AnalogToBi, and AnalogGym teams for making their upstream corpora available under permissive licenses. Thanks to the SkyWater + Google + efabless teams for the SKY130 open PDK and the ngspice team for the open-source simulator. ## Reproducibility The **`with_testbench`** config ships the exact ngspice-ready SPICE that produced every row's `metrics`. Reproducing any shipped number is three steps: 1. Load the row — `row["testbench_spice"]` is a self-contained SPICE deck. 2. Substitute `{{SKY130_LIB}}` with your local SKY130 combined/continuous `.lib` path (portability placeholder — the only environment-specific token in the deck). 3. Run `ngspice -b ` and parse `.meas` output. The `example_simulate.py` file in this repo does exactly those three steps: ```bash # One-time setup pip install datasets volare volare fetch --pdk sky130 export SKY130_LIB="$(volare show sky130)/sky130A/libs.tech/combined/continuous/sky130.lib.spice" # Install ngspice 46+ via your package manager or from source # Reproduce the first converged row of the train split python example_simulate.py # Reproduce a specific circuit python example_simulate.py --circuit-id analoggym_amp_yan_az_pin_3_s015 # Inspect the reconstructed SPICE without running (no PDK needed) python example_simulate.py --print-spice ``` Expected output (bit-exact match to four decimal places, on ngspice 46): ``` circuit_id: analoggym_amp_yan_az_pin_3_s015 topology: operational_amplifier (source: analoggym) shipped metric: dc_gain_dB = 104.818 dB Running ngspice… reproduced: dc_gain_dB = 104.818 dB delta: 0.000000 dB ✓ bit-exact ``` ### Extending the corpus Every row is a starting point for new samples. You can: - **Perturb a sweep point.** Edit `sim_params.sweep.design.w_scale` / `l_scale` / `sweep.test.ib_scale` / `cl_F`, rescale the corresponding values in `testbench_spice` (a simple regex on `W=` / `L=` / DC-source values), and run ngspice. - **Rewire the DUT.** `netlist_json` is the lossless graph representation: add a device, change a pin's net, and regenerate the SPICE lines. The `with_testbench` column shows you the full deck format your emission needs to match. - **Swap the testbench.** Replace the analysis block in `testbench_spice` (the lines after `* --- DUT ---`) with `.tran`, `.noise`, or whatever ngspice analysis you need — the DUT section is already correct. None of these extensions require a commercial simulator or PDK. ## How to Use ### Load the dataset ```python from datasets import load_dataset ds = load_dataset("pphilip/analog-circuits-sky130", split="train") # also available: "validation", "test", "failed" ``` ### Iterate rows and pull metrics ```python import json row = ds[0] metrics = json.loads(row["metrics"]) print(f"{row['circuit_id']}: gain = {metrics['dc_gain_dB']:.1f} dB, UGF = {metrics['ugf_Hz']:.2e} Hz") ``` ### Filter to a specific upstream, family, or sweep axis ```python # AnalogToBi circuits only atb = ds.filter(lambda r: r["source_dataset"] == "analogtobi") # Only AnalogGym charge pumps cp = ds.filter(lambda r: r["topology"] == "charge_pump") # Only LHS sweep samples (exclude AnalogToBi default-sizing 1× baseline) sweep = ds.filter(lambda r: json.loads(r["sim_params"]).get("sweep") is not None) ``` ### Build a PyG graph from `netlist_json` `netlist_json` is a self-contained JSON string — no pipeline library required. The example below builds a bus-style graph (nets as nodes, devices as edges — FALCON's `graph.json` shape). See `dataset_schema.md` for the full primitive schema and the bipartite / node-centric alternatives. ```python import json import torch from torch_geometric.data import Data def to_bus(netlist_json: str) -> Data: """Project the row's netlist_json primitive into a bus graph (nets as nodes, devices as edges). Every device becomes K*(K-1)/2 parallel edges (all pin-pairs), so a 4-terminal MOSFET adds 6 edges with a shared `device_id` group tag. """ from itertools import combinations p = json.loads(netlist_json) net_idx = {n["name"]: i for i, n in enumerate(p["nets"])} src, dst, dev_id, dev_type = [], [], [], [] type_vocab = {t: i for i, t in enumerate( ["nmos","pmos","npn","pnp","res","cap","ind","isrc","vsrc","other"] )} for i, d in enumerate(p["devices"]): pins = d["pins"] for a, b in combinations(range(len(pins)), 2): na, nb = net_idx[pins[a]["net"]], net_idx[pins[b]["net"]] for (s, t) in ((na, nb), (nb, na)): # both directions src.append(s); dst.append(t) dev_id.append(i) dev_type.append(type_vocab.get(d["type"], type_vocab["other"])) return Data( edge_index=torch.tensor([src, dst], dtype=torch.long), edge_attr=torch.tensor(dev_type, dtype=torch.long).unsqueeze(1), num_nodes=len(p["nets"]), ) graph = to_bus(ds[0]["netlist_json"]) ``` ### Group-aware split reproducibility Split assignment is keyed by `base_circuit_id` with `seed=42`. The dataset's `splits.json` maps every group to its split, so you can reconstruct the exact train/val/test partition locally without re-running a splitter: ```python import json, urllib.request with urllib.request.urlopen( "https://huggingface.co/datasets/pphilip/analog-circuits-sky130/resolve/main/splits.json" ) as f: splits = json.load(f) # splits[""] == "train" / "validation" / "test" ``` ## Release notes — 2026-04-21 - **130,409 rows** across **49 topology families**, SKY130 only. Available in a lean `default` config and a reproducibility-focused `with_testbench` config, each with `train` / `validation` / `test` / `failed` splits. - Group-aware split by `base_circuit_id` (seed=42) — every structural graph and all its sweep siblings land in exactly one split, no leakage. - Primitive `netlist_json` column on every row — a lossless typed-pin JSON description of the circuit graph that can be projected into bipartite / bus / node-centric PyG shapes at load time (example in § How to Use).