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cb65407 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | # Copyright cocotb contributors
# Licensed under the Revised BSD License, see LICENSE for details.
# SPDX-License-Identifier: BSD-3-Clause USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
TOPLEVEL_LANG ?= verilog
TOPLEVEL := fatal
MODULE := test_fatal
PWD=$(shell pwd)
ifeq ($(TOPLEVEL_LANG),verilog)
VERILOG_SOURCES := $(PWD)/fatal.sv
else ifeq ($(TOPLEVEL_LANG),vhdl)
VHDL_SOURCES := $(PWD)/fatal.vhd
ifneq ($(filter $(SIM),ius xcelium),)
COMPILE_ARGS += -v93
endif
endif
ifeq ($(shell echo $(SIM) | tr A-Z a-z),verilator)
COMPILE_ARGS += --timing
# error if results file exists, because currently verilator cannot find root handle with an empty module containing $fatal (gh-2346)
.PHONY: verilator_override_for_this_test
verilator_override_for_this_test:
-$(MAKE) all
@test ! -f $(COCOTB_RESULTS_FILE) || (echo "ERROR: $(COCOTB_RESULTS_FILE) was written by Verilator but not expected to" >&2 && exit 1)
else
# squash error code from simulator and ensure the cocotb test passed
.PHONY: override_for_this_test
override_for_this_test:
-$(MAKE) all
$(call check_for_results_file)
../../../bin/combine_results.py &> /dev/null
endif
include $(shell cocotb-config --makefiles)/Makefile.sim
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