File size: 1,803 Bytes
cb65407 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 | import os
import sys
import cocotb
import pytest
from cocotb.clock import Clock
from cocotb.runner import get_runner
from cocotb.triggers import ClockCycles
from test_cocotb import (
compile_args,
gpi_interfaces,
hdl_toplevel,
hdl_toplevel_lang,
sim_args,
sim_build,
tests_dir,
verilog_sources,
vhdl_sources,
)
sys.path.insert(0, os.path.join(tests_dir, "pytest"))
test_module = os.path.basename(os.path.splitext(__file__)[0])
sim = os.getenv("SIM", "icarus")
@cocotb.test()
async def clock_design(dut):
clock = Clock(dut.clk, 10, units="us")
cocotb.start_soon(clock.start())
await ClockCycles(dut.clk, 10)
def run_simulation(sim):
runner = get_runner(sim)
runner.build(
always=True,
clean=True,
verilog_sources=verilog_sources,
vhdl_sources=vhdl_sources,
hdl_toplevel=hdl_toplevel,
build_dir=sim_build,
build_args=compile_args,
defines={"NODUMPFILE": 1},
waves=True,
)
runner.test(
hdl_toplevel_lang=hdl_toplevel_lang,
hdl_toplevel=hdl_toplevel,
gpi_interfaces=gpi_interfaces,
test_module=test_module,
test_args=sim_args,
build_dir=sim_build,
waves=True,
)
@pytest.mark.simulator_required
@pytest.mark.skipif(
sim not in ["icarus", "xcelium"],
reason="Skipping test because it is only for Icarus or Xcelium simulators",
)
def test_wave_dump():
run_simulation(sim=sim)
if sim == "icarus":
dumpfile_path = os.path.join(sim_build, f"{hdl_toplevel}.fst")
elif sim == "xcelium":
dumpfile_path = os.path.join(sim_build, "cocotb_waves.shm", "cocotb_waves.trn")
else:
raise RuntimeError("Not a supported simulator")
assert os.path.exists(dumpfile_path)
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