File size: 1,676 Bytes
cb65407 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 | # Copyright cocotb contributors
# Licensed under the Revised BSD License, see LICENSE for details.
# SPDX-License-Identifier: BSD-3-Clause
import os
import sys
from pathlib import Path
import pytest
from cocotb.runner import get_runner
pytestmark = pytest.mark.simulator_required
src_path = Path(__file__).resolve().parent.parent / "designs" / "plusargs_module"
test_module_path = (
Path(__file__).resolve().parent.parent / "test_cases" / "test_plusargs"
)
sys.path.insert(0, str(test_module_path))
def test_toplevel_library():
hdl_toplevel_lang = os.getenv("HDL_TOPLEVEL_LANG", "verilog")
vhdl_gpi_interfaces = os.getenv("VHDL_GPI_INTERFACE", None)
sim = os.getenv("SIM", "icarus")
runner = get_runner(sim)
build_test_args = []
if hdl_toplevel_lang == "vhdl" and sim == "xcelium":
build_test_args = ["-v93"]
if sim == "verilator":
build_test_args = ["--timing"]
verilog_sources = []
vhdl_sources = []
if hdl_toplevel_lang == "verilog":
verilog_sources = [src_path / "tb_top.v"]
gpi_interfaces = ["vpi"]
else:
vhdl_sources = [src_path / "tb_top.vhd"]
gpi_interfaces = [vhdl_gpi_interfaces]
runner.build(
vhdl_sources=vhdl_sources,
verilog_sources=verilog_sources,
hdl_toplevel="tb_top",
build_dir=str(test_module_path / "sim_build" / "pytest"),
build_args=build_test_args,
)
runner.test(
hdl_toplevel="tb_top",
test_module="plusargs",
test_args=build_test_args,
gpi_interfaces=gpi_interfaces,
plusargs=["+foo=bar", "+test1", "+test2", "+options=fubar", "+lol=wow=4"],
)
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