File size: 2,331 Bytes
cb65407 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 | # This file is public domain, it can be freely copied without restrictions.
# SPDX-License-Identifier: CC0-1.0
# Simple tests for an adder module
import os
import random
import sys
from pathlib import Path
import cocotb
from cocotb.runner import get_runner
from cocotb.triggers import Timer
if cocotb.simulator.is_running():
from adder_model import adder_model
@cocotb.test()
async def adder_basic_test(dut):
"""Test for 5 + 10"""
A = 5
B = 10
dut.A.value = A
dut.B.value = B
await Timer(2, units="ns")
assert dut.X.value == adder_model(
A, B
), f"Adder result is incorrect: {dut.X.value} != 15"
@cocotb.test()
async def adder_randomised_test(dut):
"""Test for adding 2 random numbers multiple times"""
for i in range(10):
A = random.randint(0, 15)
B = random.randint(0, 15)
dut.A.value = A
dut.B.value = B
await Timer(2, units="ns")
assert dut.X.value == adder_model(
A, B
), f"Randomised test failed with: {dut.A.value} + {dut.B.value} = {dut.X.value}"
def test_adder_runner():
"""Simulate the adder example using the Python runner.
This file can be run directly or via pytest discovery.
"""
hdl_toplevel_lang = os.getenv("HDL_TOPLEVEL_LANG", "verilog")
sim = os.getenv("SIM", "icarus")
proj_path = Path(__file__).resolve().parent.parent
# equivalent to setting the PYTHONPATH environment variable
sys.path.append(str(proj_path / "model"))
verilog_sources = []
vhdl_sources = []
if hdl_toplevel_lang == "verilog":
verilog_sources = [proj_path / "hdl" / "adder.sv"]
else:
vhdl_sources = [proj_path / "hdl" / "adder.vhdl"]
build_test_args = []
if hdl_toplevel_lang == "vhdl" and sim == "xcelium":
build_test_args = ["-v93"]
# equivalent to setting the PYTHONPATH environment variable
sys.path.append(str(proj_path / "tests"))
runner = get_runner(sim)
runner.build(
verilog_sources=verilog_sources,
vhdl_sources=vhdl_sources,
hdl_toplevel="adder",
always=True,
build_args=build_test_args,
)
runner.test(
hdl_toplevel="adder", test_module="test_adder", test_args=build_test_args
)
if __name__ == "__main__":
test_adder_runner()
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