target:
    output wire [3:0] dma_address
);

    // Combinational logic for outputs


target:
            counter <= 3'b0;
            a_in1 <= 8'b0;
            a_in2 <= 8'b0;
            state <= IDLE;


target:
    .load_weight(load_weight),
    .valid(valid),
    .a_in(a_in1),


target:
  output reg [7:0] a_out,    // Output A to right neighbor
  output reg [7:0] acc_out   // Accumulated value to the PE below
);


target: input  wire       reset     // rst_n - low to reset --> // TODO: rename back to rst_n!


target:
  input wire store, // flag for storing data from accumulators to unified buffer
  input wire ext, // flag for output to host computer

  input wire [7:0] acc1_mem_0,


target:
      weight4 <= 8'b0;

    end else if (fetch_w) begin // READ data into weight memory
      memory[dma_address] <= ui_in;


target:
module dump();
    initial begin
        $dumpfile ("acc.vcd");
        $dumpvars (0, accumulator);


target:
        $dumpvars(0, dma.test_storage[2]);
        $dumpvars(0, dma.test_storage[3]);

        $dumpvars(0, dma.test_storage[4]);


target:
module dump();
    initial begin
        $dumpfile ("mmu.vcd");


target:
        $dumpvars (0, tpu);
        #1;
    end
endmodule


target:
    initial begin
        $dumpfile ("tt_um_tpu.vcd");
        $dumpvars (0, tt_um_tpu);
        #1;
    end


target:
always_ff @(posedge clk or posedge rst)
begin


target:
    .bus_reset  (sie_bus.reset)         //  o: Bus reset active
);


target:
            STRIP_EOP_S : begin
                data_valid  = 'b0;


target:
// USB FS 12.000 Mb/s +-0.25% (+-208ps)
localparam USB_PERIOD = 83333;   // ps
localparam USB_JIT    = 100;     // ps
`define USB_PERIOD_DEL  ((USB_PERIOD + ($urandom_range(0, USB_JIT*2) - USB_JIT))/1000.0)


target:
        sie_bus.tx_data  = data[i];
        sie_bus.tx_valid = 1'b1;


target:
        disable iff (intf.reset) $rose(intf.rcc_clk) |=> !$isunknown(intf.din);
    endproperty


target_type: primary

node_path: ERROR ERROR mintypmax_expression expression primary

target: if(!uvm_config_db#(virtual rcc_if)::get(this, "", "vif", vif))


target: rcc_cov  = rcc_in_coverage::type_id::create(.name("rcc_cov"), .parent(this));


node_path: ERROR ERROR primary

target: `uvm_fatal("No Vif", {"virtual interface must be set for: ", get_full_name(), ".vif"});


target:
    // coverage instance for coverage result display
    rcc_in_coverage cov_in;


target:
                        end
                        else
                            state <= `IDLE ;
                    end


target:
                INITIAL: begin
                    inter.ready <= 1;
                    state <= WAIT;


target: drv = driver::type_id::create("drv", this);


target: function new(string name = "agent_out", uvm_component parent = null);


target: uvm_report_fatal("No expect transaction to compare with", "");


target: assert(uvm_config_db#(input_vif)::get(this, "", "vif", vif));


target: assert(uvm_config_db#(output_vif)::get(this, "", "vif", vif));


target: modport port(input clk, rst, A, B, valid, output ready);


target: function new(string name, uvm_component parent);


target: tr_out = packet_out::type_id::create("tr_out", this);


target: class sequencer extends uvm_sequencer #(packet_in);


target:
    output signed [31:0] out
);
    assign out = clog2_math(in_);
endmodule


target:
    `EQ_INTO_REAL(a_int, b_int, eq_o);
    `NE_INTO_REAL(a_int, b_int, ne_o);
endmodule


target:
);
    `COMPRESS_UINT(in_, (`WIDTH), val);
    assign out = `TO_REAL(val);
endmodule


target:
);
    // produce a_o output
    `MAKE_CONST_REAL(a_const, a_const_int);
    assign a_o = `TO_REAL(a_const_int);


target:
module test_dff #(
    parameter real init=0.0
) (


target:
    // create c_int interface
    svreal #(`REAL_INTF_PARAMS(value, 18, -10)) c_int ();


target:
module level1 (svreal.in a, svreal.in b, svreal.out c);
    level2 inner(.a(a), .b(b), .c(c));
endmodule


target:
    assign a.value = a_value;
    assign b.value = b_value;
    assign c_value = c.value;


target:
    input real b_i,
    // if-then-else
    input cond_i,


target:
    input [7:0] in_,
    output [7:0] out
);
    `MEAS_UINT_WIDTH_INTO(in_, 8, out, 8);


target:
module test_sync_rom (
    input [1:0] addr,
    output real out,
    input clk,


target:
    input wire logic signed [`A_WIDTH-1:0] a_ext,
    input wire logic signed [`B_WIDTH-1:0] b_ext,
    // unary op I/O
    output wire logic signed [`A_WIDTH-1:0] neg_ext,
    output wire logic signed [`A_WIDTH-1:0] abs_ext,


target:
            vd_data = vlsu_wdata;
        VREG_WB_SRC_ARITH:
            vd_data = arith_output;
        VREG_WB_SRC_SCALAR:
            vd_data = replicated_scalar;


target:
        PE_OPERAND_IMMEDIATE:
        begin
            if (unsigned_immediate)
            begin


target:
    (input logic signed [W_IN-1:0] a_in,
     output logic signed [W_OUT-1:0] a_out);


target:
            2'd0: // 8b -> 16b
                sat_result = {'0, sat16_result};
            2'd1: // 16b -> 32b
                sat_result = sat32_result;
        endcase


target:
            ar = 0;
        else if (a > N)
            ar = N[6:0];
        else
            ar = a[6:0];


target:
    logic signed [W_OUT-1:0] min_out = {1'b1,{(W_OUT-1){1'b0}}};

    assign a_out = a_in < min_in ? min_out : (a_in > max_in) ? max_out : a_in[W_OUT-1:0];

    //initial $display("%d, %d, %d, %d", max_in, min_in, max_out, min_out);


target:
            else
                replicated_out = {
                    {16{scalar_in[15]}},
                    scalar_in[15:0],
                    {16{scalar_in[15]}},


target: #1ns $display("%d, %d", in, out);


target: #10ns $display("%d, %d", in, out);


target: sat_unit #(.W_IN(13), .W_OUT(8)) satu(in, out);


target:
                    packed_set[1] = 1'b1;
                    memory_read_packed[1] = memory_read_bytes[2];
                end
                4'bzz11 : begin
                    packed_set[2] = 1'b1;


target:
        vl_next = max_vl;
    else
        vl_next = avl_in[4:0];

end


target:
                case(vs3_addr_o[0])
                    1'd0 : data_wdata_o = {vs_rdata_i[47:32], vs_rdata_i[15:0]};
                    1'd1 : data_wdata_o = {vs_rdata_i[111:96], vs_rdata_i[79:64]};
                endcase
            end


target:
                    end
                    // 2'd1: // Not needed, just wr_en0 = '1
                    2'd2:
                    begin