{"task_id": "ChiselAIA", "path": "ChiselAIA/src/main/scala/APLIC.scala", "left_context": "//MC{hide}\n/***************************************************************************************\n* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)\n*\n* ChiselAIA is licensed under Mulan PSL v2.\n* You can use this software according to the terms and conditions of the Mulan PSL v2.\n* You may obtain a copy of Mulan PSL v2 at:\n* http://license.coscl.org.cn/MulanPSL2\n*\n* THIS SOFTWARE IS PROVIDED ON AN \"AS IS\" BASIS, WITHOUT WARRANTIES OF ANY KIND,\n* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,\n* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.\n*\n* See the Mulan PSL v2 for more details.\n***************************************************************************************/\n\npackage aia\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.diplomacy._\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.tilelink._\nimport freechips.rocketchip.devices.tilelink._\nimport freechips.rocketchip.amba.axi4._\nimport freechips.rocketchip.regmapper._\nimport utility._\n\ncase class APLICParams(\n //MC APLIC接收的中断源数量的对数。\n //MC 默认值7表示APLIC支持最多128（2^7）个中断源。\n //MC **注意**：`aplicIntSrcWidth`必须小于`imsicIntSrcWidth`，\n //MC 因为APLIC的中断源将被转换为MSI，\n //MC 而APLIC转换成的MSI是IMSIC中断源的子集。\n //MC （Logarithm of number of interrupt sources to APLIC:\n //MC The default 7 means APLIC support at most 128 (2^7) interrupt sources.\n //MC **Note**: `aplicIntSrcWidth` must be **less than** `imsicIntSrcWidth`,\n //MC as APLIC interrupt sources are converted to MSIs,\n //MC which are a subset of IMSIC's interrupt sources）：\n //MC{visible}\n aplicIntSrcWidth: Int = 7,\n imsicIntSrcWidth: Int = 9,\n //MC 👉 APLIC域的基地址（Base address of APLIC domains）:\n baseAddr: Long = 0x19960000L,\n //MC **注意**：下述中括号内的变量与AIA规范中的一致（第3.6节：用于多个中断文件的内存区域排列）。\n //MC\n //MC **Note**: The following variables in bracket align with the AIA specification (Section 3.6: Memory Region Arrangement for Multiple Interrupt Files).\n //MC\n //MC 👉 每个组的成员数量（Number of members per group）[\\\\(h_{max}\\\\)]：\n membersNum : Int = 2 ,\n //MC 👉 所有IMSIC的机器态中断文件的基地址（Base address of machine-level interrupt files for all IMSICs）[\\\\(A\\\\)]：\n mBaseAddr : Long = 0x61000000L ,\n //MC 👉 所有IMSIC的监管态和客户态中断文件的基地址（Base addr for supervisor-level and guest-level interrupt files for all IMSICs）[\\\\(B\\\\)]:\n sgBaseAddr : Long = 0x82900000L ,\n //MC 👉 组的数量（Number of groups ）[\\\\(g_{max}\\\\)]:\n groupsNum : Int = 1 ,\n //MC 👉 客户中断文件的数量（Number of guest interrupt files）:\n geilen : Int = 7 ,\n //MC{hide}\n //MC{hide}\n) {\n require(aplicIntSrcWidth <= 10, f\"aplicIntSrcWidth=${aplicIntSrcWidth}, must not greater than log2(1024)=10, as there are at most 1023 sourcecfgs\")\n lazy val intSrcNum: Int = pow2(aplicIntSrcWidth).toInt\n lazy val ixNum: Int = pow2(aplicIntSrcWidth).toInt / 32\n lazy val domainMemWidth : Int = 14 // interrupt file memory region width: 14-bit width => 16KB size\n\n lazy val intFileMemWidth : Int = 12 // interrupt file memory region width: 12-bit width => 4KB size\n // require(mStrideWidth >= intFileMemWidth)\n lazy val mStrideWidth : Int = intFileMemWidth // C: stride between each machine-level interrupt files\n // require(sgStrideWidth >= log2Ceil(geilen+1) + intFileMemWidth)\n lazy val sgStrideWidth : Int = log2Ceil(geilen+1) + intFileMemWidth // D: stride between each supervisor- and guest-level interrupt files\n // require(groupStrideWidth >= k + math.max(mStrideWidth, sgStrideWidth))\n lazy val membersWidth : Int = log2Ceil(membersNum) // k\n require((mBaseAddr & (pow2(membersWidth + mStrideWidth) -1)) == 0, \"mBaseAddr should be aligned to a 2^(k+C)\")\n lazy val groupStrideWidth: Int = membersWidth + math.max(mStrideWidth, sgStrideWidth) // E: stride between each interrupt file groups\n lazy val groupsWidth : Int = log2Ceil(groupsNum) // j\n require((sgBaseAddr & (pow2(membersWidth + sgStrideWidth) - 1)) == 0, \"sgBaseAddr should be aligned to a 2^(k+D)\")\n require(( ((pow2(groupsWidth)-1) * pow2(groupStrideWidth)) & mBaseAddr ) == 0)\n require(( ((pow2(groupsWidth)-1) * pow2(groupStrideWidth)) & sgBaseAddr) == 0)\n\n def hartIndex_to_gh(hartIndex: Int): (Int, Int) = {\n val g = (hartIndex>>membersWidth) & (pow2(groupsWidth)-1)\n val h = hartIndex & (pow2(membersWidth)-1)\n (g.toInt, h.toInt)\n }\n def gh_to_hartIndex(g: Int, h: Int): Int = {\n (g< ~reg.D && reg.SM=/=inactive))\n }\n abstract class IXs extends Bundle {\n protected val bits = RegInit(VecInit.fill(params.intSrcNum){false.B})\n val bits0 = VecInit(false.B +: bits.drop(1)) // bits0(0) is read-only 0\n def r32I(i:Int): UInt = Cat((0 until 32).map(j => rBitUI((i< wBitUI((i< {\n rect32 := Cat(intSrcsRectified.slice(i*32, i*32+32).reverse)\n }}\n def RWF_setixs(i:Int, ixs:IXs) = RegWriteFn((valid, data) => {\n when(valid) {ixs.w32I(i, ixs.r32I(i) | data)}; true.B })\n def RWF_setipnum = RegWriteFn((valid, data) => {\n when (valid && data=/=0.U) { ips.wBitUI(data(params.aplicIntSrcWidth-1,0), true.B) }; true.B })\n def RWF_setclrixnum(setclr:Bool, ixs:IXs) = RegWriteFn((valid, data) => {\n when (valid && data=/=0.U) { ixs.wBitUI(data(params.aplicIntSrcWidth-1,0), setclr) }; true.B })\n def RWF_clrixs(i:Int, ixs:IXs) = RegWriteFn((valid, data) => {\n when (valid) { ixs.w32I(i, ixs.r32I(i) & ~data) }; true.B })\n io.regmapOut <> RegMapper(beatBytes, 1, true, io.regmapIn,\n /*domaincfg*/ 0x0000 -> Seq(RegField(32, domaincfg.r, RegWriteFn((v, d)=>{ when(v){domaincfg.w(d)}; true.B }))),\n /*sourcecfgs*/ 0x0004 -> (1 until params.intSrcNum).map(i => RegField(32, sourcecfgs.rI(i),\n RegWriteFn((v, d)=>{ when(v){sourcecfgs.wI(i, d)}; true.B }))),\n /*mmsiaddrcfgh*/0x1BC4 -> Seq(RegField(32, 0x80000000L.U, RegWriteFn(():Unit))), // hardwired *msiaddrcfg* regs\n /*setips*/ 0x1C00 -> (0 until params.ixNum).map(i => RegField(32, ips.r32I(i), RWF_setixs(i, ips))),\n /*setipnum*/ 0x1CDC -> Seq(RegField(32, 0.U, RWF_setipnum)),\n /*in_clrips*/ 0x1D00 -> (0 until params.ixNum).map(i => RegField(32, intSrcsRectified32(i), RWF_clrixs(i, ips))),\n /*clripnum*/ 0x1DDC -> Seq(RegField(32, 0.U, RWF_setclrixnum(false.B, ips))),\n /*seties*/ 0x1E00 -> (0 until params.ixNum).map(i => RegField(32, ies.r32I(i), RWF_setixs(i, ies))),\n /*setienum*/ 0x1EDC -> Seq(RegField(32, 0.U, RWF_setclrixnum(true.B, ies))),\n /*clries*/ 0x1F00 -> (0 until params.ixNum).map(i => RegField(32, 0.U, RWF_clrixs(i, ies))),\n /*clrienum*/ 0x1FDC -> Seq(RegField(32, 0.U, RWF_setclrixnum(false.B, ies))),\n /*setipnum_le*/ 0x2000 -> Seq(RegField(32, 0.U, RWF_setipnum)),\n /*setipnum_be*/ 0x2004 -> Seq(RegField(32, 0.U, RegWriteFn(():Unit))), // setipnum_be not implemented\n /*genmsi*/ 0x3000 -> Seq(RegField(32, genmsi.r, RegWriteFn((v,d)=>{ when(v){genmsi.w(d)}; true.B }))),\n /*targets*/ 0x3004 -> (1 until params.intSrcNum).map(i => RegField(32, targets.rI(i),\n RegWriteFn((v, d)=>{ when(v){targets.wI(i, d)}; true.B }))),\n )\n }\n\n private val intSrcsSynced = RegNextN(intSrcs, 3)\n intSrcsRectified(0) := false.B\n (1 until params.intSrcNum).map(i => {\n val (rect, sync, sm) = (intSrcsRectified(i), intSrcsSynced(i), sourcecfgs.regs(i).SM)\n when (sm===sourcecfgs.edge1 || sm===sourcecfgs.level1) {\n rect := sync\n }.elsewhen(sm===sourcecfgs.edge0 || sm===sourcecfgs.level0) {\n rect := !sync\n }.otherwise {\n rect := false.B\n }\n })\n private val intSrcsTriggered = Wire(Vec(params.intSrcNum, Bool())); /*for debug*/dontTouch(intSrcsTriggered)\n (intSrcsTriggered zip intSrcsRectified).map { case (trigger, rect) => {\n trigger := rect && !RegNext(rect)\n }}\n intSrcsTriggered.zipWithIndex.map { case (trigger:Bool, i:Int) =>\n when(trigger) {ips.wBitUI(i.U, true.B)}\n }\n\n // The \":+ true.B\" trick explain:\n // Append true.B to handle the cornor case, where all bits in ip and ie are disabled.\n // If do not append true.B, then we need to check whether the ip & ie are empty,\n // otherwise, the returned topei will become the max index, that is 2^aplicIntSrcWidth-1\n // [0, 2^aplicIntSrcWidth-1] :+ 2^aplicIntSrcWidth\n private val topi = Wire(UInt(params.aplicIntSrcWidth.W)); /*for debug*/dontTouch(topi)\n topi := ParallelPriorityMux((\n (ips.bits0:+true.B) zip (ies.bits0:+true.B)\n ).zipWithIndex.map {\n case ((p: Bool, e: Bool), i: Int) => (p & e, i.U)\n })\n // send MSI\n locally {\n val idle :: waiting_ack :: Nil = Enum(2)\n val state = RegInit(idle)\n\n def getMSIAddr(HartIndex:UInt, guestID:UInt): UInt = {\n val groupID = if (params.groupsWidth == 0) 0.U\n else HartIndex(params.groupsWidth+params.membersWidth-1, params.membersWidth)\n val memberID = if (params.membersWidth == 0) 0.U\n else HartIndex(params.membersWidth-1, 0)\n // It is recommended to hardwire *msiaddrcfg* by the manual:\n // \"For any given system, these addresses are fixed and should be hardwired into the APLIC if possible.\"\n imsicBaseAddr.U |\n (groupID< r.D&i}\n }\n\n // domain(0) is m domain, domain(1) is sg domain\n private val domains = Seq(Module(new Domain(\n params.baseAddr,\n params.mBaseAddr,\n params.mStrideWidth,\n 0,\n )), Module(new Domain(\n params.baseAddr + pow2(params.domainMemWidth),\n params.sgBaseAddr,\n params.sgStrideWidth,\n params.geilen,\n )))\n val ios = domains.map(d => { val io = IO(d.io.cloneType); io <> d.io; io })\n\n val intSrcs = IO(Input(Vec(params.intSrcNum, Bool())))\n domains(0).intSrcs := intSrcs\n domains(1).intSrcs := domains(0).intSrcsDelegated\n}\n\nclass TLAPLIC(\n params: APLICParams,\n beatBytes: Int = 4,\n)(implicit p: Parameters) extends LazyModule {\n val fromCPU = LazyModule(new TLXbar).node\n val toIMSIC = LazyModule(new TLXbar).node\n private val domainFromCPUs = Seq(\n params.baseAddr, params.baseAddr + pow2(params.domainMemWidth) \n ).map ( baseAddr => {\n val domainFromCPU = TLRegMapperNode(\n address = Seq(AddressSet(baseAddr, pow2(params.domainMemWidth)-1)),\n beatBytes = beatBytes)\n domainFromCPU := fromCPU; domainFromCPU\n })\n private val domainToIMSICs = (0 until 2).map (_ => {\n val domainToIMSIC = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(\"toimsic\", IdRange(0,16))))))\n toIMSIC := domainToIMSIC; domainToIMSIC\n })\n\n lazy val module = new Imp\n class Imp extends LazyModuleImp(this) {\n val intSrcs = IO(Input(Vec(params.intSrcNum, Bool())))\n private val aplic = Module(new APLIC(params, beatBytes))\n aplic.intSrcs := intSrcs\n\n (domainToIMSICs zip aplic.ios).map { case (domainToIMSIC, aplicIO) => {\n val (tl, edge) = domainToIMSIC.out.head\n val msi = aplicIO.msi\n val (_, bits) = edge.Put(0.U, msi.bits.addr, 2.U, msi.bits.data)\n tl.a.bits := bits\n tl.a.valid := msi.valid\n msi.ready := tl.a.ready\n tl.d.ready := true.B\n aplicIO.ack := tl.d.valid\n }}\n\n (domainFromCPUs zip aplic.ios).map { case (domainFromCPU, aplicIO) => {\n domainFromCPU.regmap(aplicIO.regmapIn, aplicIO.regmapOut)\n }}\n }\n}\n\nclass AXI4APLIC(\n params: APLICParams,\n beatBytes: Int = 4,\n)(implicit p: Parameters) extends LazyModule {\n val fromCPU = LazyModule(new AXI4Xbar).node\n val toIMSIC = LazyModule(new AXI4Xbar).node\n private val domainFromCPUs = Seq(\n params.baseAddr, params.baseAddr + pow2(params.domainMemWidth) \n ).map ( baseAddr => {\n val domainFromCPU = AXI4RegMapperNode(\n address = AddressSet(baseAddr, pow2(params.domainMemWidth)-1),\n beatBytes = beatBytes)\n domainFromCPU := fromCPU; domainFromCPU\n })\n private val domainToIMSICs = (0 until 2).map (_ => {\n val domainToIMSIC = AXI4MasterNode(Seq(AXI4MasterPortParameters(Seq(AXI4MasterParameters(\"toimsic\", IdRange(0,16))))))\n toIMSIC := domainToIMSIC; domainToIMSIC\n })\n\n lazy val module = new Imp\n class Imp extends LazyModuleImp(this) {\n val intSrcs = IO(Input(Vec(params.intSrcNum, Bool())))\n private val aplic = Module(new APLIC(params, beatBytes))\n aplic.intSrcs := intSrcs\n\n (domainToIMSICs zip aplic.ios).map { case (domainToIMSIC, aplicIO) => {\n val (axi, edge_params) = domainToIMSIC.out.head\n val msi = aplicIO.msi\n axi.aw.bits.addr := msi.bits.addr\n axi.aw.bits.size := 2.U\n axi.aw.valid := msi.valid\n axi.w.bits.data := msi.bits.data\n axi.w.bits.strb := MaskGen(msi.bits.addr, 2.U, beatBytes)\n axi.w.bits.last := true.B\n axi.w.valid := msi.valid\n msi.ready := axi.aw.ready & axi.w.ready\n axi.b.ready := true.B\n aplicIO.ack := axi.b.valid\n }}\n\n (domainFromCPUs zip aplic.ios).map { case (domainFromCPU, aplicIO) => {\n domainFromCPU.regmap(aplicIO.regmapIn, aplicIO.regmapOut)\n }}\n }\n}\n", "groundtruth": " when (intSrcsRectified(ui)) { bits(ui):=bit }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "ChiselAIA", "path": "ChiselAIA/src/main/scala/Example-axi.scala", "left_context": "/***************************************************************************************\n* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)\n*\n* ChiselAIA is licensed under Mulan PSL v2.\n* You can use this software according to the terms and conditions of the Mulan PSL v2.\n* You may obtain a copy of Mulan PSL v2 at:\n* http://license.coscl.org.cn/MulanPSL2\n*\n* THIS SOFTWARE IS PROVIDED ON AN \"AS IS\" BASIS, WITHOUT WARRANTIES OF ANY KIND,\n* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,\n* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.\n*\n* See the Mulan PSL v2 for more details.\n***************************************************************************************/\n\npackage aia\n\nimport chisel3.{IO, _}\nimport chisel3.util._\nimport freechips.rocketchip.diplomacy._\nimport org.chipsalliance.cde.config.{Parameters, Config}\nimport freechips.rocketchip.amba.axi4._\n// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._\nimport _root_.circt.stage.ChiselStage\n\n\nclass AXI4AIA()(implicit p: Parameters) extends LazyModule {\n val toAIA = AXI4MasterNode(\n Seq(AXI4MasterPortParameters(\n Seq(AXI4MasterParameters(\"aia_axi4\", IdRange(0, 16)))\n )))\n val toAIA_xbar = LazyModule(new AXI4Xbar).node\n toAIA_xbar := toAIA\n\n // Here we create 2 imsic groups, each group contains two 2 CPUs\n val imsic_params = IMSICParams(EnableImsicAsyncBridge = true)\n val aplic_params = APLICParams(groupsNum = 2, membersNum = 2)\n val imsics_fromMem_xbar = LazyModule(new AXI4Xbar).node\n imsics_fromMem_xbar := toAIA_xbar\n\n val imsics = (0 until 4).map(i => {\n val (groupID, memberID) = aplic_params.hartIndex_to_gh(i)\n require(groupID < aplic_params.groupsNum, f\"groupID ${groupID} should less than groupsNum ${aplic_params.groupsNum}\")\n require(memberID < aplic_params.membersNum, f\"memberID ${memberID} should less than membersNum ${aplic_params.membersNum}\")\n println(f\"Generating IMSIC groupID=0x${groupID}%x memberID=0x${memberID}%x\")\n val map = LazyModule(new AXI4Map(addrSet => addrSet.base.toLong match {\n case imsic_params.mAddr => groupID * pow2(aplic_params.groupStrideWidth) + aplic_params.mBaseAddr + memberID * pow2(aplic_params.mStrideWidth)\n case imsic_params.sgAddr => groupID * pow2(aplic_params.groupStrideWidth) + aplic_params.sgBaseAddr + memberID * pow2(aplic_params.sgStrideWidth)\n case imsic_params.tee_mAddr => groupID * pow2(aplic_params.groupStrideWidth) + 0x40010000L + memberID * pow2(aplic_params.mStrideWidth)\n case imsic_params.tee_sgAddr => groupID * pow2(aplic_params.groupStrideWidth) + 0x80010000L + memberID * pow2(aplic_params.sgStrideWidth)\n", "right_context": " })(Parameters.empty)).node\n\n val teemap = LazyModule(new AXI4Map(addrSet => addrSet.base.toLong match {\n case imsic_params.mAddr => groupID * pow2(aplic_params.groupStrideWidth) + 0x40010000L + memberID * pow2(aplic_params.mStrideWidth)\n case imsic_params.sgAddr => groupID * pow2(aplic_params.groupStrideWidth) + 0x80010000L + memberID * pow2(aplic_params.sgStrideWidth)\n\n })(Parameters.empty)).node\n\n val imsic = LazyModule(new AXI4IMSIC(imsic_params)(new Config((site, here, up) => {\n case IMSICParameKey => IMSICParameters(HasTEEIMSIC = false)\n })))\n\n// imsic.axireg.axireg.axi4tolite.head.node := map := imsics_fromMem_xbar\n imsic.axireg.imsic_xbar1to2 := map := imsics_fromMem_xbar\n// imsic.axireg.tee_axireg.foreach { tee_axireg => tee_axireg.axi4tolite.head.node := teemap := imsics_fromMem_xbar }\n imsic\n })\n\n val aplic = LazyModule(new AXI4APLIC(aplic_params)(Parameters.empty))\n aplic.fromCPU := toAIA_xbar\n imsics_fromMem_xbar := aplic.toIMSIC\n\n lazy val module = new LazyModuleImp(this) with HasIMSICParameters{\n toAIA.makeIOs()(ValName(\"toaia\"))\n (0 until 4).map(i => {\n val toCSR = IO(Output(chiselTypeOf(imsics(i).module.toCSR))).suggestName(f\"toCSR${i}\")\n val fromCSR = IO(Input(chiselTypeOf(imsics(i).module.fromCSR))).suggestName(f\"fromCSR${i}\")\n toCSR <> imsics(i).module.toCSR\n fromCSR <> imsics(i).module.fromCSR\n })\n val intSrcs = IO(Input(chiselTypeOf(aplic.module.intSrcs)))\n intSrcs <> aplic.module.intSrcs\n val sec_cmode = if (GHasTEEIMSIC) Some(IO(Input(Bool()))) else None\n val sec_notice_pending = if (GHasTEEIMSIC) Some(IO(Output(Vec(4,Bool())))) else None\n for (i <- 0 until 4) {\n imsics(i).module.soc_clock := clock\n imsics(i).module.soc_reset := reset\n sec_cmode.foreach { sec_cmode =>\n imsics(i).module.io_sec.foreach {\n instance_iosec =>\n instance_iosec.cmode := sec_cmode\n }\n }\n\n sec_notice_pending.foreach { sec_notice_pending =>\n imsics(i).module.io_sec.foreach {\n instance_iosec =>\n sec_notice_pending(i) := instance_iosec.notice_pending\n }\n }\n }\n }\n}\n\n/**\n * Generate Verilog sources\n */\nobject AXI4AIA extends App {\n\n val axi4top = LazyModule(new AXI4AIA()(\n Parameters.empty.alterPartial({\n case IMSICParameKey => IMSICParameters(HasTEEIMSIC=false)\n })\n ))\n\n\n ChiselStage.emitSystemVerilog(\n axi4top.module,\n args = Array(\"--dump-fir\"),\n // more opts see: $CHISEL_FIRTOOL_PATH/firtool -h\n firtoolOpts = Array(\n \"-disable-all-randomization\",\n \"-strip-debug-info\",\n // without this, firtool will exit with error: Unhandled annotation\n \"--disable-annotation-unknown\",\n \"--lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing,locationInfoStyle=none\",\n \"--split-verilog\", \"-o=gen_axi\",\n )\n )\n}", "groundtruth": " case _ => assert(false, f\"unknown address ${addrSet.base}\"); 0\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.7, "category_reason": "Scala case/match expression"} {"task_id": "ChiselAIA", "path": "ChiselAIA/src/main/scala/Example.scala", "left_context": "/***************************************************************************************\n* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)\n*\n* ChiselAIA is licensed under Mulan PSL v2.\n* You can use this software according to the terms and conditions of the Mulan PSL v2.\n* You may obtain a copy of Mulan PSL v2 at:\n* http://license.coscl.org.cn/MulanPSL2\n*\n* THIS SOFTWARE IS PROVIDED ON AN \"AS IS\" BASIS, WITHOUT WARRANTIES OF ANY KIND,\n* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,\n* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.\n*\n* See the Mulan PSL v2 for more details.\n***************************************************************************************/\n\npackage aia\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.diplomacy._\nimport org.chipsalliance.cde.config.{Parameters, Config}\nimport freechips.rocketchip.tilelink._\n// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._\nimport _root_.circt.stage.ChiselStage\n\nclass TLAIA()(implicit p: Parameters) extends LazyModule {\n val toAIA = TLClientNode(\n Seq(TLMasterPortParameters.v1(\n Seq(TLMasterParameters.v1(\"aia_tl\", IdRange(0, 16)))\n )))\n val toAIA_xbar = LazyModule(new TLXbar).node\n toAIA_xbar := toAIA\n\n // Here we create 2 imsic groups, each group contains two 2 CPUs\n val imsic_params = IMSICParams(EnableImsicAsyncBridge = false)\n val aplic_params = APLICParams(groupsNum=2, membersNum=2)\n val imsics_fromMem_xbar = LazyModule(new TLXbar).node\n imsics_fromMem_xbar := toAIA_xbar\n\n val imsics = (0 until 4).map( i => {\n val (groupID,memberID) = aplic_params.hartIndex_to_gh(i)\n require(groupID < aplic_params.groupsNum, f\"groupID ${groupID} should less than groupsNum ${aplic_params.groupsNum}\")\n", "right_context": " println(f\"Generating IMSIC groupID=0x${groupID }%x memberID=0x${memberID}%x\")\n val map = LazyModule(new TLMap( addrSet => addrSet.base.toLong match {\n case imsic_params.mAddr => groupID * pow2(aplic_params.groupStrideWidth) + aplic_params.mBaseAddr + memberID * pow2(aplic_params.mStrideWidth)\n case imsic_params.sgAddr=> groupID * pow2(aplic_params.groupStrideWidth) + aplic_params.sgBaseAddr+ memberID * pow2(aplic_params.sgStrideWidth)\n case imsic_params.tee_mAddr => groupID * pow2(aplic_params.groupStrideWidth) + 0x40010000L + memberID * pow2(aplic_params.mStrideWidth)\n case imsic_params.tee_sgAddr => groupID * pow2(aplic_params.groupStrideWidth) + 0x80010000L + memberID * pow2(aplic_params.sgStrideWidth)\n case _ => assert(false, f\"unknown address ${addrSet.base}\"); 0\n })(Parameters.empty)).node\n\n val teemap = LazyModule(new TLMap(addrSet => addrSet.base.toLong match {\n case imsic_params.mAddr => groupID * pow2(aplic_params.groupStrideWidth) + 0x40010000L + memberID * pow2(aplic_params.mStrideWidth)\n case imsic_params.sgAddr => groupID * pow2(aplic_params.groupStrideWidth) + 0x80010000L + memberID * pow2(aplic_params.sgStrideWidth)\n case _ => assert(false, f\"unknown address ${addrSet.base}\"); 0\n })(Parameters.empty)).node\n val imsic = LazyModule(new TLIMSIC(imsic_params)(new Config((site, here, up) => {\n case IMSICParameKey => IMSICParameters(HasTEEIMSIC = false)\n })))\n\n// imsic.axireg.axireg.fromMem.head := map := imsics_fromMem_xbar\n// imsic.axireg.tee_axireg.foreach { tee_axireg => tee_axireg.fromMem.head := teemap := imsics_fromMem_xbar }\n imsic.axireg.imsic_xbar1to2 := map := imsics_fromMem_xbar\n imsic\n })\n\n val aplic = LazyModule(new TLAPLIC(aplic_params)(Parameters.empty))\n aplic.fromCPU := toAIA_xbar\n imsics_fromMem_xbar := aplic.toIMSIC\n\n lazy val module = new LazyModuleImp(this) with HasIMSICParameters{\n toAIA.makeIOs()(ValName(\"toaia\"))\n (0 until 4).map (i => {\n val toCSR = IO(Output(chiselTypeOf(imsics(i).module.toCSR))).suggestName(f\"toCSR${i}\")\n val fromCSR = IO(Input(chiselTypeOf(imsics(i).module.fromCSR))).suggestName(f\"fromCSR${i}\")\n toCSR <> imsics(i).module.toCSR\n fromCSR <> imsics(i).module.fromCSR\n })\n val intSrcs = IO(Input(chiselTypeOf(aplic.module.intSrcs)))\n intSrcs <> aplic.module.intSrcs\n val sec_cmode = if (GHasTEEIMSIC) Some(IO(Input(Bool()))) else None\n val sec_notice_pending = if (GHasTEEIMSIC) Some(IO(Output(Vec(4,Bool())))) else None\n for (i <- 0 until 4) {\n imsics(i).module.soc_clock := clock\n imsics(i).module.soc_reset := reset\n sec_cmode.foreach { sec_cmode =>\n imsics(i).module.io_sec.foreach {\n instance_iosec =>\n instance_iosec.cmode := sec_cmode\n }\n }\n sec_notice_pending.foreach { sec_notice_pending =>\n imsics(i).module.io_sec.foreach {\n instance_iosec =>\n sec_notice_pending(i) := instance_iosec.notice_pending\n }\n }\n }\n }\n}\n\n/**\n * Generate Verilog sources\n */\nobject TLAIA extends App {\n val top = LazyModule(new TLAIA()(\n Parameters.empty.alterPartial({\n case IMSICParameKey => IMSICParameters(HasTEEIMSIC=false)\n })\n ))\n\n ChiselStage.emitSystemVerilog(\n top.module,\n args = Array(\"--dump-fir\"),\n // more opts see: $CHISEL_FIRTOOL_PATH/firtool -h\n firtoolOpts = Array(\n \"-disable-all-randomization\",\n \"-strip-debug-info\",\n // without this, firtool will exit with error: Unhandled annotation\n \"--disable-annotation-unknown\",\n \"--lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing,locationInfoStyle=none\",\n \"--split-verilog\", \"-o=gen\",\n )\n )\n}\n", "groundtruth": " require(memberID < aplic_params.membersNum, f\"memberID ${memberID} should less than membersNum ${aplic_params.membersNum}\")\n", "crossfile_context": "", "category": "Property and Assertion Specification", "subcategory": "Assertion Definition", "confidence": 0.65, "category_reason": "Require/assert check"} {"task_id": "ChiselAIA", "path": "ChiselAIA/src/main/scala/IMSIC.scala", "left_context": "package aia\n\nimport chisel3._\nimport chisel3.IO\nimport chisel3.util._\nimport freechips.rocketchip.amba.axi4._\nimport freechips.rocketchip.amba.axi4.AXI4Xbar\nimport freechips.rocketchip.devices.tilelink._\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.prci.ClockSinkDomain\nimport freechips.rocketchip.regmapper._\nimport freechips.rocketchip.tilelink._\nimport freechips.rocketchip.util._\nimport org.chipsalliance.cde.config.Parameters\nimport utility._\n\nobject RegMapDV {\n def Unwritable = null\n def apply(addr: Int, reg: UInt, wfn: UInt => UInt = (x => x)) = (addr, (reg, wfn))\n def generate(\n default: UInt,\n mapping: Map[Int, (UInt, UInt => UInt)],\n raddr: UInt,\n rvld: Bool,\n rdata: UInt,\n rvalid: Bool,\n waddr: UInt,\n wen: Bool,\n wdata: UInt,\n wmask: UInt,\n illegal_priv: Bool,\n illegal_op: Bool\n ): Unit = {\n val chiselMapping = mapping.map { case (a, (r, w)) => (a.U, r, w) }\n when(rvld) {\n rdata := LookupTreeDefault(\n raddr,\n Cat(default),\n chiselMapping.map { case (a, r, _) => (a, r) }\n )\n rvalid := true.B\n }.otherwise {\n rdata := 0.U((rdata.getWidth).W)\n rvalid := illegal_priv | illegal_op\n }\n\n chiselMapping.foreach { case (a, r, w) =>\n if (w != null) {\n when(wen && waddr === a && !illegal_priv && !illegal_op) {\n r := w(MaskData(r, wdata, wmask))\n }\n }\n }\n }\n def generate(\n default: UInt,\n mapping: Map[Int, (UInt, UInt => UInt)],\n addr: UInt,\n rvld: Bool,\n rdata: UInt,\n rvalid: Bool,\n wen: Bool,\n wdata: UInt,\n wmask: UInt,\n illegal_priv: Bool,\n illegal_wdata_op: Bool\n ): Unit = generate(default, mapping, addr, rvld, rdata, rvalid, addr, wen, wdata, wmask, illegal_priv, illegal_wdata_op)\n}\n\n// Based on Xiangshan NewCSR\nobject OpType extends ChiselEnum {\n val ILLEGAL = Value(0.U)\n val CSRRW = Value(1.U)\n val CSRRS = Value(2.U)\n val CSRRC = Value(3.U)\n}\nobject PrivType extends ChiselEnum {\n val U = Value(0.U)\n val S = Value(1.U)\n val H = Value(2.U)\n val M = Value(3.U)\n}\nclass MSITransBundle(params: IMSICParams) extends Bundle {\n val vld_req = Input(Bool()) // request from axireg\n val data = Input(UInt(params.MSI_INFO_WIDTH.W))\n val vld_ack = Output(Bool()) // ack for axireg from imsic. which indicates imsic can work actively.\n}\nclass ForCVMBundle extends Bundle {\n val cmode = Input(Bool()) // add port: cpu mode is tee or ree\n val notice_pending =\n Output(Bool()) // add port: interrupt pending of ree when cmode is tee,else interrupt pending of tee.\n}\nclass AddrBundle(params: IMSICParams) extends Bundle {\n val valid = Bool() // 表示 addr 是否有效\n val bits = new Bundle {\n val addr = UInt(params.iselectWidth.W) // 存储实际地址值\n val virt = Bool()\n val priv = PrivType()\n }\n}\nclass CSRToIMSICBundle(params: IMSICParams) extends Bundle {\n val addr = new AddrBundle(params)\n val vgein = UInt(params.vgeinWidth.W)\n val wdata = ValidIO(new Bundle {\n val op = OpType()\n val data = UInt(params.xlen.W)\n })\n val claims = Vec(params.privNum, Bool())\n}\nclass IMSICToCSRBundle(params: IMSICParams) extends Bundle {\n val rdata = ValidIO(UInt(params.xlen.W))\n val illegal = Bool()\n val pendings = UInt(params.intFilesNum.W)\n val topeis = Vec(params.privNum, UInt(32.W))\n}\ncase class IMSICParams(\n // MC IMSIC中断源数量的对数，默认值8表示IMSIC支持最多512（2^9）个中断源\n\n // MC （Logarithm of number of interrupt sources to IMSIC.\n // MC The default 9 means IMSIC support at most 256 (2^9) interrupt sources）:\n // MC{visible}\n imsicIntSrcWidth: Int = 9,\n // MC 👉 本IMSIC的机器态中断文件的地址（Address of machine-level interrupt files for this IMSIC）：\n mAddr: Long = 0x00000L,\n // MC 👉 本IMSIC的监管态和客户态中断文件的地址（Addr for supervisor-level and guest-level interrupt files for this IMSIC）:\n sgAddr: Long = 0x10000L,\n // MC 👉 客户中断文件的数量（Number of guest interrupt files）:\n geilen: Int = 7,\n // MC vgein信号的位宽（The width of the vgein signal）:\n vgeinWidth: Int = 6,\n // MC iselect信号的位宽(The width of iselect signal):\n iselectWidth: Int = 12,\n EnableImsicAsyncBridge: Boolean = true,\n HasTEEIMSIC: Boolean = false,\n HartIDBits: Int = 9\n // MC{hide}\n) {\n lazy val xlen: Int = 64 // currently only support xlen = 64\n lazy val xlenWidth = log2Ceil(xlen)\n require(\n imsicIntSrcWidth <= 11 && imsicIntSrcWidth >= 6,\n f\"imsicIntSrcWidth=${imsicIntSrcWidth}, must not greater than log2(2048)=11, as there are at most 2048 eip/eie bits\" +\n \"must not be less than log2(64)=6, as there must be at least 64 eip/eie bits\"\n )\n lazy val privNum: Int = 3 // number of privilege modes: machine, supervisor, virtualized supervisor\n lazy val intFilesNum: Int = 2 + geilen // number of interrupt files, m, s, vs0, vs1, ...\n\n lazy val eixNum: Int = pow2(imsicIntSrcWidth).toInt / xlen // number of eip/eie registers\n lazy val intFileMemWidth: Int = 12 // interrupt file memory region width: 12-bit width => 4KB size\n lazy val tee_mshift: Int = HartIDBits + intFileMemWidth // 9: max 512 hart, bit10 is 1, tee imsic accessed.\n lazy val tee_sshift: Int = HartIDBits + log2Ceil(1+ geilen) + intFileMemWidth // 9: max 512 hart, bit10 is 1, tee imsic accessed.\n lazy val tee_mAddr: Long = mAddr + (1L << tee_mshift)\n lazy val tee_sgAddr: Long = sgAddr + (1L << tee_sshift)\n require(vgeinWidth >= log2Ceil(geilen))\n require(\n iselectWidth >= 8,\n f\"iselectWidth=${iselectWidth} needs to be able to cover addr [0x70, 0xFF], that is from CSR eidelivery to CSR eie63\"\n )\n lazy val INTP_FILE_WIDTH = log2Ceil(intFilesNum)\n lazy val MSI_INFO_WIDTH = imsicIntSrcWidth + INTP_FILE_WIDTH\n}\n\nclass IMSIC(\n params: IMSICParams,\n beatBytes: Int = 4\n)(implicit p: Parameters) extends Module {\n println(f\"IMSICParams.geilen: ${params.geilen}%d\")\n\n class IMSICGateWay extends Module {\n // === io port define ===\n val msiio = IO(new MSITransBundle(params))\n val msi_data_o = IO(Output(UInt(params.imsicIntSrcWidth.W)))\n val msi_valid_o = IO(Output(UInt(params.intFilesNum.W)))\n\n // === main body ===\n val msi_in = Wire(UInt(params.MSI_INFO_WIDTH.W))\n msi_in := msiio.data\n val msi_vld_req_cpu = WireInit(false.B)\n when(params.EnableImsicAsyncBridge.B) {\n msi_vld_req_cpu := AsyncResetSynchronizerShiftReg(msiio.vld_req, 3, 0)\n }.otherwise {\n msi_vld_req_cpu := msiio.vld_req\n }\n val msi_vld_ack_cpu = RegInit(false.B)\n when(msi_vld_req_cpu)(\n msi_vld_ack_cpu := true.B\n ).otherwise(\n msi_vld_ack_cpu := false.B\n )\n // generate the msi_vld_ack,to handle with the input msi request.\n msiio.vld_ack := msi_vld_ack_cpu\n val msi_vld_ris_cpu = msi_vld_req_cpu & (~msi_vld_ack_cpu) // rising of msi_vld_req\n val msi_data_catch = RegInit(0.U(params.imsicIntSrcWidth.W))\n val msi_intf_valids = RegInit(0.U(params.intFilesNum.W))\n msi_data_o := msi_data_catch(params.imsicIntSrcWidth - 1, 0)\n msi_valid_o := msi_intf_valids // multi-bis switch vector\n when(msi_vld_ris_cpu) {\n msi_data_catch := msi_in(params.imsicIntSrcWidth - 1, 0)\n msi_intf_valids := 1.U << msi_in(params.MSI_INFO_WIDTH - 1,params.imsicIntSrcWidth)\n }.otherwise {\n msi_intf_valids := 0.U\n }\n }\n class IntFile extends Module {\n override def desiredName = \"IntFile\"\n val fromCSR = IO(Input(new Bundle {\n val seteipnum = ValidIO(UInt(params.imsicIntSrcWidth.W))\n val addr = ValidIO(UInt(params.iselectWidth.W))\n val virt = Bool()\n val priv = PrivType()\n val vgein = UInt(params.vgeinWidth.W)\n val wdata = ValidIO(new Bundle {\n val op = OpType()\n val data = UInt(params.xlen.W)\n })\n val claim = Bool()\n }))\n val toCSR = IO(Output(new Bundle {\n val rdata = ValidIO(UInt(params.xlen.W))\n val illegal = Bool()\n val pending = Bool()\n val topei = UInt(params.imsicIntSrcWidth.W)\n }))\n val illegal_io = IO(new Bundle {\n val illegal_priv = Input(Bool())\n })\n val illegal_priv = illegal_io.illegal_priv\n \n /// indirect CSRs\n val eidelivery = RegInit(0.U(params.xlen.W))\n val eithreshold = RegInit(0.U(params.xlen.W))\n val eips = RegInit(VecInit.fill(params.eixNum)(0.U(params.xlen.W)))\n val eies = RegInit(VecInit.fill(params.eixNum)(0.U(params.xlen.W)))\n\n val illegal_wdata_op = WireDefault(false.B)\n locally { // scope for xiselect CSR reg map\n val wdata = WireDefault(0.U(params.xlen.W))\n val wmask = WireDefault(0.U(params.xlen.W))\n when(fromCSR.wdata.valid) {\n switch(fromCSR.wdata.bits.op) {\n // is(OpType.ILLEGAL) {\n // illegal_wdata_op := true.B\n // }\n is(OpType.CSRRW) {\n wdata := fromCSR.wdata.bits.data\n wmask := Fill(params.xlen, 1.U)\n }\n is(OpType.CSRRS) {\n wdata := Fill(params.xlen, 1.U)\n wmask := fromCSR.wdata.bits.data\n }\n is(OpType.CSRRC) {\n wdata := 0.U\n wmask := fromCSR.wdata.bits.data\n }\n }\n }\n def bit0ReadOnlyZero(x: UInt): UInt = x & ~1.U(x.getWidth.W)\n def fixEIDelivery(x: UInt): UInt = x & 1.U\n RegMapDV.generate(\n 0.U,\n Map(\n RegMapDV(0x70, eidelivery, fixEIDelivery),\n RegMapDV(0x72, eithreshold),\n RegMapDV(0x80, eips(0), bit0ReadOnlyZero),\n RegMapDV(0xc0, eies(0), bit0ReadOnlyZero)\n ) ++ eips.drop(1).zipWithIndex.map { case (eip: UInt, i: Int) =>\n RegMapDV(0x82 + i * 2, eip)\n } ++ eies.drop(1).zipWithIndex.map { case (eie: UInt, i: Int) =>\n RegMapDV(0xc2 + i * 2, eie)\n },\n /*raddr*/ fromCSR.addr.bits,\n /*rvld */ fromCSR.addr.valid,\n /*rdata*/ toCSR.rdata.bits,\n /*rvalid*/ toCSR.rdata.valid,\n /*waddr*/ fromCSR.addr.bits,\n /*wen */ fromCSR.wdata.valid,\n /*wdata*/ wdata,\n /*wmask*/ wmask,\n /*priv*/ illegal_priv,\n /*op*/ illegal_wdata_op\n )\n val illegal_csr = WireDefault(false.B)\n when(fromCSR.addr.bits >= 0x80.U && fromCSR.addr.bits <= 0xFF.U &&\n fromCSR.addr.bits(0) === 1.U) {\n illegal_csr := true.B\n }\n toCSR.illegal := illegal_csr\n }\n locally {\n val index = fromCSR.seteipnum.bits(params.imsicIntSrcWidth - 1, params.xlenWidth)\n val offset = fromCSR.seteipnum.bits(params.xlenWidth - 1, 0)\n when(fromCSR.seteipnum.valid) {\n // set eips bit\n eips(index) := eips(index) | UIntToOH(offset)\n }\n }\n\n locally { // scope for xtopei\n // The \":+ true.B\" trick explain:\n // Append true.B to handle the cornor case, where all bits in eip and eie are disabled.\n // If do not append true.B, then we need to check whether the eip & eie are empty,\n // otherwise, the returned topei will become the max index, that is 2^intSrcWidth-1\n // Noted: the support max interrupt sources number = 2^intSrcWidth\n // [0, 2^intSrcWidth-1] :+ 2^intSrcWidth\n val eipBools = Cat(eips.reverse).asBools :+ true.B\n val eieBools = Cat(eies.reverse).asBools :+ true.B\n \n def xtopei_filter(xeidelivery: UInt, xeithreshold: UInt, xtopei: UInt): UInt = {\n val tmp_xtopei = Mux(xeidelivery(params.xlen - 1, 1) === 0.U, Mux(xeidelivery(0), xtopei, 0.U) , 0.U)\n // {\n // all interrupts are enabled, when eithreshold == 1;\n // interrupts, when i < eithreshold, are enabled;\n // } <=> interrupts, when i <= (eithreshold -1), are enabled\n Mux(tmp_xtopei <= (xeithreshold - 1.U), tmp_xtopei, 0.U)\n }\n toCSR.topei := xtopei_filter(\n eidelivery,\n eithreshold,\n ParallelPriorityMux(\n (eipBools zip eieBools).zipWithIndex.map {\n case ((p: Bool, e: Bool), i: Int) => (p & e, i.U)\n }\n )\n )\n } // end of scope for xtopei\n toCSR.pending := toCSR.topei =/= 0.U\n\n when(fromCSR.claim) {\n val index = toCSR.topei(params.imsicIntSrcWidth - 1, params.xlenWidth)\n val offset = toCSR.topei(params.xlenWidth - 1, 0)\n // clear the pending bit indexed by xtopei in xeip\n eips(index) := eips(index) & ~UIntToOH(offset)\n }\n }\n val toCSR = IO(Output(new IMSICToCSRBundle(params)))\n val fromCSR = IO(Input(new CSRToIMSICBundle(params)))\n val msiio = IO(new MSITransBundle(params))\n val illegal_priv = WireInit(false.B)\n\n private val intFilesSelOH_r = WireDefault(0.U(params.intFilesNum.W))\n private val intFilesSelOH_w = WireDefault(0.U(params.intFilesNum.W))\n locally {\n when (fromCSR.addr.valid)\n {\n when(fromCSR.addr.bits.virt === false.B )\n {\n when(((fromCSR.addr.bits.priv.asUInt === 3.U) || (fromCSR.addr.bits.priv.asUInt === 1.U))/* && fromCSR.vgein === 0.U*/){\n illegal_priv := false.B\n }.otherwise{\n illegal_priv := true.B\n }\n }.otherwise{\n when(fromCSR.addr.bits.priv.asUInt === 1.U && (fromCSR.vgein >= 1.U) && (fromCSR.vgein < (params.geilen + 1).U((params.vgeinWidth+1).W)))\n {\n illegal_priv := false.B\n }.otherwise{\n illegal_priv := true.B\n }\n }\n }\n when (fromCSR.addr.valid && !illegal_priv) // read\n {\n val pv = Cat(fromCSR.addr.bits.priv.asUInt, fromCSR.addr.bits.virt)\n when(pv === Cat(PrivType.M.asUInt, false.B)){intFilesSelOH_r := UIntToOH(0.U)}\n .elsewhen(pv === Cat(PrivType.S.asUInt, false.B)){intFilesSelOH_r := UIntToOH(1.U)}\n .elsewhen(pv === Cat(PrivType.S.asUInt, true.B)){intFilesSelOH_r := UIntToOH(1.U((fromCSR.vgein.getWidth+1).W)\n + fromCSR.vgein.pad(params.vgeinWidth+1))\n }\n }\n when (fromCSR.addr.valid && fromCSR.wdata.valid && !(fromCSR.wdata.bits.op.asUInt === 0.U) && !illegal_priv) // write\n {\n val pv = Cat(fromCSR.addr.bits.priv.asUInt, fromCSR.addr.bits.virt)\n when(pv === Cat(PrivType.M.asUInt, false.B)){intFilesSelOH_w := UIntToOH(0.U)}\n .elsewhen(pv === Cat(PrivType.S.asUInt, false.B)){intFilesSelOH_w := UIntToOH(1.U)}\n .elsewhen(pv === Cat(PrivType.S.asUInt, true.B)){intFilesSelOH_w := UIntToOH(1.U((fromCSR.vgein.getWidth+1).W)\n + fromCSR.vgein.pad(params.vgeinWidth+1))\n }\n }\n }\n\n private val topeis_forEachIntFiles = Wire(Vec(params.intFilesNum, UInt(params.imsicIntSrcWidth.W)))\n private val illegals_forEachIntFiles = Wire(Vec(params.intFilesNum, Bool()))\n // instance and connect IMSICGateWay.\n val imsicGateWay = Module(new IMSICGateWay)\n imsicGateWay.msiio <> msiio\n val pendings = Wire(Vec(params.intFilesNum,Bool()))\n val vec_rdata = Wire(Vec(params.intFilesNum, ValidIO(UInt(params.xlen.W))))\n Seq(1, 1 + params.geilen).zipWithIndex.map {\n case (intFilesNum: Int, i: Int) => {\n // j: index for S intFile: S, G1, G2, ...\n val maps = (0 until intFilesNum).map { j =>\n val flati = i + j\n val pi = if (flati > 2) 2 else flati // index for privileges: M, S, VS.\n\n def sel_addr(old: AddrBundle): AddrBundle = {\n val new_ = Wire(new AddrBundle(params))\n new_.valid := old.valid & intFilesSelOH_r(flati)\n new_.bits.addr := old.bits.addr\n new_.bits.virt := old.bits.virt\n new_.bits.priv := old.bits.priv\n new_\n }\n def sel_wdata[T <: Data](old: Valid[T]): Valid[T] = {\n val new_ = Wire(Valid(chiselTypeOf(old.bits)))\n new_.bits := old.bits\n new_.valid := old.valid & intFilesSelOH_w(flati)\n new_\n }\n\n val intFile = Module(new IntFile)\n // Preventing overflow\n when (flati.U((params.vgeinWidth + 1).W) === fromCSR.vgein.pad(params.vgeinWidth + 1)+1.U) {\n intFile.fromCSR.vgein := fromCSR.vgein\n } .otherwise {\n intFile.fromCSR.vgein := 0.U\n }\n val intfile_rdata_d = RegNext(intFile.toCSR.rdata)\n val msi_valid_delayed = RegNext(imsicGateWay.msi_valid_o(flati), false.B)\n intFile.fromCSR.seteipnum.bits := imsicGateWay.msi_data_o\n intFile.fromCSR.seteipnum.valid := imsicGateWay.msi_valid_o(flati) | msi_valid_delayed\n intFile.fromCSR.addr.valid := sel_addr(fromCSR.addr).valid\n intFile.fromCSR.addr.bits := sel_addr(fromCSR.addr).bits.addr\n intFile.fromCSR.virt := sel_addr(fromCSR.addr).bits.virt\n intFile.fromCSR.priv := sel_addr(fromCSR.addr).bits.priv\n intFile.fromCSR.wdata := sel_wdata(fromCSR.wdata)\n intFile.fromCSR.claim := fromCSR.claims(pi)\n intFile.illegal_io.illegal_priv := illegal_priv\n vec_rdata(flati) := intfile_rdata_d\n pendings(flati) := intFile.toCSR.pending\n topeis_forEachIntFiles(flati) := intFile.toCSR.topei\n illegals_forEachIntFiles(flati) := intFile.toCSR.illegal\n }\n }\n }\n toCSR.rdata.valid := vec_rdata.map(_.valid).reduce(_|_)\n toCSR.rdata.bits := vec_rdata.map(_.bits).reduce(_|_)\n toCSR.pendings := (pendings.zipWithIndex.map{case (p,i) => p << i.U}).reduce(_ | _) //vector -> multi-bit\n locally {\n // Format of *topei:\n // * bits 26:16 Interrupt identity\n // * bits 10:0 Interrupt priority (same as identity)\n // * All other bit positions are zeros.\n // For detailed explainations of these memory region arguments,\n // please refer to the manual *The RISC-V Advanced Interrupt Architeture*: 3.9. Top external interrupt CSRs\n def wrap(topei: UInt): UInt = {\n val zeros = 0.U((16 - params.imsicIntSrcWidth).W)\n Cat(zeros, topei, zeros, topei)\n }\n val pv = Cat(fromCSR.addr.bits.priv.asUInt, fromCSR.addr.bits.virt)\n toCSR.topeis(0) := wrap(topeis_forEachIntFiles(0)) // m\n toCSR.topeis(1) := wrap(topeis_forEachIntFiles(1)) // s\n toCSR.topeis(2) := wrap(ParallelMux(\n UIntToOH(fromCSR.vgein - 1.U, params.geilen).asBools,\n topeis_forEachIntFiles.drop(2)\n )) // vs\n } \n val toCSR_illegal_d = RegNext((fromCSR.addr.valid | fromCSR.wdata.valid) & Seq(\n illegals_forEachIntFiles.reduce(_ | _),\n (fromCSR.wdata.valid && fromCSR.wdata.bits.op.asUInt === 0.U),\n illegal_priv\n ).reduce(_ | _))\n toCSR.illegal := toCSR_illegal_d\n}\n\n//define IMSIC_WRAP: instance one imsic when HasCVMExtention is supported, else instance two imsic modules.\nclass IMSIC_WRAP(\n params: IMSICParams,\n beatBytes: Int = 4\n)(implicit p: Parameters) extends Module {\n // define the ports\n val toCSR = IO(Output(new IMSICToCSRBundle(params)))\n val fromCSR = IO(Input(new CSRToIMSICBundle(params)))\n val msiio = IO(new MSITransBundle(params))\n // define additional ports when HasCVMExtention is supported.\n val sec = if (params.HasTEEIMSIC) Some(IO(new ForCVMBundle()))\n else None // include cmode input port,and o_notice_pending output port.\n val teemsiio = if (params.HasTEEIMSIC) Some(IO(new MSITransBundle(params))) else None\n // instance module,and body logic\n private val imsic = Module(new IMSIC(params, beatBytes))\n imsic.fromCSR := fromCSR\n toCSR := imsic.toCSR\n imsic.msiio <> msiio\n // define additional logic for sec extention\n // .foreach logic only happens when sec is not none.\n sec.foreach { secIO =>\n // get the sec.mode, connect sec.o_notice_pending to top.\n val cmode = Wire(Bool())\n val notice_pending = Wire(Bool())\n cmode := secIO.cmode\n secIO.notice_pending := notice_pending\n\n // instance tee imsic module.\n val teeimsic = Module(new IMSIC(params, beatBytes))\n teemsiio.foreach(teemsiio => teeimsic.msiio <> teemsiio)\n toCSR.rdata := Mux(cmode, teeimsic.toCSR.rdata, imsic.toCSR.rdata) // toCSR needs to the selected depending cmode.\n toCSR.illegal := Mux(cmode, teeimsic.toCSR.illegal, imsic.toCSR.illegal)\n val s_pendings = Mux(cmode, teeimsic.toCSR.pendings(params.intFilesNum-1,1), imsic.toCSR.pendings(params.intFilesNum-1,1))\n val m_pendings = imsic.toCSR.pendings(0) // machine mode only from imsic.\n toCSR.pendings := Cat(s_pendings,m_pendings)\n // toCSR.pendings := VecInit((0 until params.intFilesNum).map(i => pendings(i))) // uint->vector\n \n toCSR.topeis := Mux(cmode, teeimsic.toCSR.topeis, imsic.toCSR.topeis)\n toCSR.topeis(0) := imsic.toCSR.topeis(0) // machine mode only from imsic.\n // to get the o_notice_pending, excluding the machine interrupt\n// val s_orpend_ree = imsic.toCSR.pendings.slice(1, params.intFilesNum) // extract the | of vector(1,N-1)\n// val s_orpend_tee = teeimsic.toCSR.pendings.slice(1, params.intFilesNum)\n// notice_pending := Mux(cmode, s_orpend_ree.reduce(_ | _), s_orpend_tee.reduce(_ | _))\n val s_orpend_ree = imsic.toCSR.pendings(params.intFilesNum-1,1) // extract the | of vector(1,N-1)\n val s_orpend_tee = teeimsic.toCSR.pendings(params.intFilesNum-1,1) //bit(params.intFilesNum-1:1)\n notice_pending := Mux(cmode, s_orpend_ree.orR, s_orpend_tee.orR)\n teeimsic.fromCSR := fromCSR\n teeimsic.fromCSR.addr.valid := cmode & fromCSR.addr.valid // cmode=1,controls tee csr access to interrupt file indirectly\n teeimsic.fromCSR.wdata.valid := cmode & fromCSR.wdata.valid\n teeimsic.fromCSR.claims(0) := false.B // machine interrupts are inactive for tee imsic.\n for (i <- 1 until params.privNum) {\n teeimsic.fromCSR.claims(i) := cmode & fromCSR.claims(i)\n }\n\n imsic.fromCSR.addr.valid := (cmode === false.B) & fromCSR.addr.valid // cmode=1,controls tee csr access to interrupt file indirectly\n imsic.fromCSR.wdata.valid := (cmode === false.B) & fromCSR.wdata.valid\n imsic.fromCSR.claims(0) := fromCSR.claims(0) // machine interrupts are inactive for tee imsic.\n for (i <- 1 until params.privNum) {\n imsic.fromCSR.claims(i) := (cmode === false.B) & fromCSR.claims(i)\n }\n }\n}\n\n//generate TLIMSIC top module:including TLRegIMSIC_WRAP and IMSIC_WRAP\nclass TLIMSIC(\n params: IMSICParams,\n beatBytes: Int = 4\n// asyncQueueParams: AsyncQueueParams\n)(implicit p: Parameters) extends LazyModule with HasIMSICParameters {\n val axireg = LazyModule(new TLRegIMSIC_WRAP(IMSICParams(HasTEEIMSIC = GHasTEEIMSIC), beatBytes))\n lazy val module = new Imp\n\n class Imp extends LazyModuleImp(this) {\n val toCSR = IO(Output(new IMSICToCSRBundle(params)))\n val fromCSR = IO(Input(new CSRToIMSICBundle(params)))\n private val imsic = Module(new IMSIC_WRAP(IMSICParams(HasTEEIMSIC = GHasTEEIMSIC), beatBytes))\n toCSR := imsic.toCSR\n imsic.fromCSR := fromCSR\n axireg.module.msiio <> imsic.msiio // msi_req/msi_ack interconnect\n // define additional ports for cvm extention\n val io_sec = if (GHasTEEIMSIC) Some(IO(new ForCVMBundle()))\n else None // include cmode input port,and o_notice_pending output port.\n /* code on when imsic has two clock domains.*/\n // --- define soc_clock for imsic bus logic ***//\n val soc_clock = IO(Input(Clock()))\n val soc_reset = IO(Input(Reset()))\n axireg.module.clock := soc_clock\n axireg.module.reset := soc_reset\n imsic.clock := clock\n imsic.reset := reset\n axireg.module.msiio <> imsic.msiio // msi_req/msi_ack interconnect\n // code will be compiled only when io_sec is not None.\n io_sec.foreach(iosec => imsic.sec.foreach(imsicsec => imsicsec <> iosec))\n // code will be compiled only when tee_axireg is not None.\n axireg.module.teemsiio.foreach(tee_msi_trans => imsic.teemsiio.foreach(teemsiio => tee_msi_trans <> teemsiio))\n }\n}\n\nclass AXI4IMSIC(\n params: IMSICParams,\n beatBytes: Int = 4\n)(implicit p: Parameters) extends LazyModule with HasIMSICParameters {\n val axireg = LazyModule(new AXIRegIMSIC_WRAP(IMSICParams(HasTEEIMSIC = GHasTEEIMSIC), beatBytes))\n lazy val module = new Imp\n class Imp extends LazyModuleImp(this) {\n val toCSR = IO(Output(new IMSICToCSRBundle(params)))\n val fromCSR = IO(Input(new CSRToIMSICBundle(params)))\n private val imsic = Module(new IMSIC_WRAP(IMSICParams(HasTEEIMSIC = GHasTEEIMSIC), beatBytes))\n toCSR := imsic.toCSR\n imsic.fromCSR := fromCSR\n axireg.module.msiio <> imsic.msiio // msi_req/msi_ack interconnect\n // define additional ports for cvm extention\n val io_sec = if (GHasTEEIMSIC) Some(IO(new ForCVMBundle()))\n else None // include cmode input port,and o_notice_pending output port.\n /* code on when imsic has two clock domains.*/\n // --- define soc_clock for imsic bus logic ***//\n val soc_clock = IO(Input(Clock()))\n val soc_reset = IO(Input(Reset()))\n axireg.module.clock := soc_clock\n axireg.module.reset := soc_reset\n imsic.clock := clock\n imsic.reset := reset\n // code will be compiled only when io_sec is not None.\n io_sec.foreach(iosec => imsic.sec.foreach(imsicsec => imsicsec <> iosec))\n // code will be compiled only when tee_axireg is not None.\n axireg.module.teemsiio.foreach(tee_msi_trans => imsic.teemsiio.foreach(teemsiio => tee_msi_trans <> teemsiio))\n }\n}\n\n\n// code below is for SEC IMSIC spec\n//generate TLRegIMSIC_WRAP for IMSIC, when HasCVMExtention is supported, IMSIC is instantiated by two times,else only one\nclass TLRegIMSIC_WRAP(\n params: IMSICParams,\n beatBytes: Int = 4,\n seperateBus: Boolean = false\n)(implicit p: Parameters) extends LazyModule {\n // def IMSIC access TLXbar\n// require((params.HasTEEIMSIC && seperateBus) == false,\n// f\"both seperateTLBus and HasTEEIMSIC are true !!\")\n require(seperateBus == false,\n f\"seperateTLBus is true inside TLRegIMSIC_WRAP !!\")\n val axireg = LazyModule(new TLRegIMSIC(params, beatBytes)(Parameters.empty))\n val tee_axireg =\n", "right_context": " val imsic_xbar1to2 = TLXbar()\n private val ree_sNode = TLManagerNode(Seq(TLSlavePortParameters.v1(\n managers = Seq(TLSlaveParameters.v1(\n address = Seq(\n AddressSet(params.mAddr, pow2(params.intFileMemWidth) - 1),\n AddressSet(params.sgAddr, pow2(params.intFileMemWidth) * pow2(log2Ceil(1 + params.geilen)) - 1)),\n regionType = RegionType.UNCACHED,\n executable = false,\n supportsGet = TransferSizes(1, beatBytes),\n supportsPutPartial = TransferSizes(1, beatBytes),\n supportsPutFull = TransferSizes(1, beatBytes),\n // fifoId = Some(0)\n )),\n beatBytes = beatBytes\n )))\n\n private val tee_sNode = Option.when(params.HasTEEIMSIC)(TLManagerNode(Seq(TLSlavePortParameters.v1(\n managers = Seq(TLSlaveParameters.v1(\n address = Seq(\n AddressSet(params.tee_mAddr, pow2(params.intFileMemWidth) - 1),\n AddressSet(params.tee_sgAddr, pow2(params.intFileMemWidth) * pow2(log2Ceil(1 + params.geilen)) - 1)),\n regionType = RegionType.UNCACHED,\n executable = false,\n supportsGet = TransferSizes(1, beatBytes),\n supportsPutPartial = TransferSizes(1, beatBytes),\n supportsPutFull = TransferSizes(1, beatBytes),\n // fifoId = Some(0)\n )),\n beatBytes = beatBytes\n ))))\n ree_sNode := imsic_xbar1to2\n tee_sNode.foreach (_ := imsic_xbar1to2)\n val ree_mNode = TLClientNode(\n Seq(TLMasterPortParameters.v1(\n Seq(TLMasterParameters.v1(\"s_tl_\", IdRange(0, 65536)))\n )))\n val tee_mNode = Option.when(params.HasTEEIMSIC)(\n TLClientNode(\n Seq(TLMasterPortParameters.v1(\n Seq(TLMasterParameters.v1(\"s_tl_\", IdRange(0, 65536)))\n ))))\n axireg.fromMem.head := ree_mNode\n tee_mNode.foreach(tee_axireg.get.fromMem.head := _)\n lazy val module = new TLRegIMSICImp(this)\n class TLRegIMSICImp(outer: LazyModule) extends LazyModuleImp(outer) {\n val msiio = IO(Flipped(new MSITransBundle(params)))\n msiio <> axireg.module.msiio\n val teemsiio = if (params.HasTEEIMSIC) Some(IO(Flipped(new MSITransBundle(params))))\n else None // backpressure signal for axi4bus, from imsic working on cpu clock\n\n // code below will be compiled only when teeio is not none.\n teemsiio.foreach(teemsiio => tee_axireg.foreach(tee_axireg => teemsiio <> tee_axireg.module.msiio))\n ree_mNode.out.head._1 <> ree_sNode.in.head._1\n tee_mNode.foreach(_.out.head._1 <> tee_sNode.get.in.head._1)\n }\n}\n\n//generate AXIRegIMSIC_WRAP for IMSIC, when HasCVMExtention is supported, IMSIC is instantiated by two times,else only one\nclass AXIRegIMSIC_WRAP(\n params: IMSICParams,\n beatBytes: Int = 4,\n seperateBus: Boolean = false\n)(implicit p: Parameters) extends LazyModule {\n // def IMSIC access AXI4Xbar\n val imsic_xbar1to2 = AXI4Xbar()\n val ree_sNode = {\n AXI4SlaveNode(Seq(AXI4SlavePortParameters(\n slaves = Seq(AXI4SlaveParameters(\n address = Seq(\n AddressSet(params.mAddr, pow2(params.intFileMemWidth) - 1),\n AddressSet(params.sgAddr, pow2(params.intFileMemWidth) * pow2(log2Ceil(1 + params.geilen)) - 1)),\n supportsWrite = TransferSizes(1, beatBytes),\n supportsRead = TransferSizes(1, beatBytes)\n )),\n beatBytes = beatBytes\n )))\n }\n val tee_sNode = Option.when(params.HasTEEIMSIC) {\n AXI4SlaveNode(Seq(AXI4SlavePortParameters(\n slaves = Seq(AXI4SlaveParameters(\n address = Seq(\n AddressSet(params.tee_mAddr, pow2(params.intFileMemWidth) - 1),\n AddressSet(params.tee_sgAddr, pow2(params.intFileMemWidth) * pow2(log2Ceil(1 + params.geilen)) - 1)),\n supportsWrite = TransferSizes(1, beatBytes),\n supportsRead = TransferSizes(1, beatBytes)\n )),\n beatBytes = beatBytes\n )))\n }\n ree_sNode := imsic_xbar1to2\n tee_sNode.foreach(_ := imsic_xbar1to2)\n val axireg = LazyModule(new AXIRegIMSIC(params, beatBytes)(Parameters.empty))\n // val tee_axireg = if (params.HasTEEIMSIC) Some(LazyModule(new AXIRegIMSIC(IMSICParams(teemode = true), beatBytes)(Parameters.empty))) else None\n val tee_axireg =\n if (params.HasTEEIMSIC) Some(LazyModule(new AXIRegIMSIC(params, beatBytes)(Parameters.empty))) else None\n val ree_mNode = AXI4MasterNode(Seq(AXI4MasterPortParameters(\n Seq(AXI4MasterParameters(\n name = \"s_axi_\",\n id = IdRange(0, 65536)\n ))\n )))\n val tee_mNode = Option.when(params.HasTEEIMSIC) {\n AXI4MasterNode(Seq(AXI4MasterPortParameters(\n Seq(AXI4MasterParameters(\n name = \"s_axi_\",\n id = IdRange(0, 65536)\n ))\n )))\n }\n axireg.axi4tolite.head.node := ree_mNode\n tee_axireg.foreach(_.axi4tolite.head.node := tee_mNode.get)\n lazy val module = new AXIRegIMSICImp(this)\n\n class AXIRegIMSICImp(outer: LazyModule) extends LazyModuleImp(outer) {\n val msiio = IO(Flipped(new MSITransBundle(params))) // backpressure signal for axi4bus, from imsic working on cpu clock\n msiio <> axireg.module.msiio\n val teemsiio = if (params.HasTEEIMSIC) Some(IO(Flipped(new MSITransBundle(params))))\n else None // backpressure signal for axi4bus, from imsic working on cpu clock\n // code below will be compiled only when teeio is not none.\n teemsiio.foreach(teemsiio => tee_axireg.foreach(tee_axireg => teemsiio <> tee_axireg.module.msiio))\n ree_mNode.out.head._1 <> ree_sNode.in.head._1\n tee_mNode.foreach(_.out.head._1 <> tee_sNode.get.in.head._1)\n }\n}\n\nclass TLRegIMSIC(\n params: IMSICParams,\n beatBytes: Int = 4,\n seperateBus: Boolean = false\n)(implicit p: Parameters) extends LazyModule {\n val fromMem = Seq.fill(if (seperateBus) 2 else 1)(TLXbar())\n // val fromMem = LazyModule(new TLXbar).node\n private val intfileFromMems = Seq(\n AddressSet(params.mAddr, pow2(params.intFileMemWidth) - 1),\n AddressSet(params.sgAddr, pow2(params.intFileMemWidth) * pow2(log2Ceil(1 + params.geilen)) - 1)\n ).zipWithIndex.map { case (addrset, i) =>\n val intfileFromMem = TLRegMapperNode(\n address = Seq(addrset),\n beatBytes = beatBytes\n )\n intfileFromMem := (if (seperateBus) fromMem(i) else fromMem.head)\n intfileFromMem\n }\n\n lazy val module = new TLRegIMSICImp(this)\n class TLRegIMSICImp(outer: LazyModule) extends LazyModuleImp(outer) {\n val msiio = IO(Flipped(new MSITransBundle(params))) // backpressure signal for axi4bus, from imsic working on cpu clock\n private val reggen = Module(new RegGen(params, beatBytes))\n // ---- instance sync fifo ----//\n // --- fifo wdata: {vector_valid,setipnum}, fifo wren: |vector_valid---//\n val FifoDataWidth = params.MSI_INFO_WIDTH\n val fifo_wdata = Wire(Valid(UInt(FifoDataWidth.W)))\n\n // depth:8, data width: FifoDataWidth\n private val fifo_sync = Module(new Queue(UInt(FifoDataWidth.W), 8))\n // define about fifo write\n fifo_wdata.bits := reggen.io.seteipnum\n fifo_wdata.valid := reggen.io.valid\n fifo_sync.io.enq.valid := fifo_wdata.valid\n fifo_sync.io.enq.bits := fifo_wdata.bits\n // fifo rd,controlled by msi_vld_ack from imsic working on csr clock.\n // msi_vld_ack_soc: sync result with soc clock\n val msi_vld_ack_soc = WireInit(false.B)\n val msi_vld_ack_cpu = msiio.vld_ack\n val msi_vld_req = RegInit(false.B)\n when(params.EnableImsicAsyncBridge.B) {\n msi_vld_ack_soc := AsyncResetSynchronizerShiftReg(msi_vld_ack_cpu, 3, 0)\n }.otherwise {\n msi_vld_ack_soc := msi_vld_ack_cpu\n }\n fifo_sync.io.deq.ready := ~msi_vld_req\n // generate the msi_vld_req: high if ~empty,low when msi_vld_ack_soc\n msiio.vld_req := msi_vld_req\n val msi_vld_ack_soc_1f = RegNext(msi_vld_ack_soc)\n val msi_vld_ack_soc_ris = msi_vld_ack_soc & (~msi_vld_ack_soc_1f)\n // val fifo_empty = ~fifo_sync.io.deq.valid\n // msi_vld_req : high when fifo empty is false, low when ack is high. and io.deq.valid := ~empty\n when(msi_vld_ack_soc_ris) {\n msi_vld_req := false.B\n }.elsewhen(fifo_sync.io.deq.valid === true.B) {\n msi_vld_req := true.B\n }.otherwise {\n msi_vld_req := msi_vld_req\n }\n\n // get the msi interrupt ID info\n val msi_id_data = RegInit(0.U(params.MSI_INFO_WIDTH.W))\n val rdata_vld = fifo_sync.io.deq.fire // assign to fifo rdata\n when(rdata_vld) { // fire: io.deq.valid & io.deq.ready\n msi_id_data := fifo_sync.io.deq.bits(params.MSI_INFO_WIDTH - 1, 0)\n }.otherwise {\n msi_id_data := msi_id_data\n }\n // port connect: io.valid is interrupt file index info.\n msiio.data := msi_id_data\n val backpress = fifo_sync.io.enq.ready\n (intfileFromMems zip reggen.regmapIOs).map {\n case (intfileFromMem, regmapIO) => intfileFromMem.regmap(regmapIO._1, regmapIO._2, backpress)\n }\n }\n}\n\n\n//generate axi42reg for IMSIC\nclass AXIRegIMSIC(\n params: IMSICParams,\n beatBytes: Int = 4,\n seperateBus: Boolean = false\n)(implicit p: Parameters) extends LazyModule {\n val fromMem = Seq.fill(if (seperateBus) 2 else 1)(AXI4Xbar())\n val axi4tolite = Seq.fill(if (seperateBus) 2 else 1)(LazyModule(new AXI4ToLite()(Parameters.empty)))\n fromMem zip axi4tolite.map(_.node) foreach (x => x._1 := x._2)\n private val intfileFromMems = Seq(\n AddressSet(params.mAddr, pow2(params.intFileMemWidth) - 1),\n AddressSet(params.sgAddr, pow2(params.intFileMemWidth) * pow2(log2Ceil(1 + params.geilen)) - 1)\n ).zipWithIndex.map { case (addrset, i) =>\n val intfileFromMem = AXI4RegMapperNode(\n address = addrset,\n beatBytes = beatBytes\n )\n intfileFromMem := (if (seperateBus) fromMem(i) else fromMem.head)\n intfileFromMem\n }\n \n lazy val module = new AXIRegIMSICImp(this)\n class AXIRegIMSICImp(outer: LazyModule) extends LazyModuleImp(outer) {\n val msiio = IO(Flipped(new MSITransBundle(params))) // backpressure signal for axi4bus, from imsic working on cpu clock\n private val reggen = Module(new RegGen(params, beatBytes))\n // ---- instance sync fifo ----//\n // --- fifo wdata: {vector_valid,setipnum}, fifo wren: |vector_valid---//\n val FifoDataWidth = params.MSI_INFO_WIDTH\n val fifo_wdata = Wire(Valid(UInt(FifoDataWidth.W)))\n\n // depth:8, data width: FifoDataWidth\n private val fifo_sync = Module(new Queue(UInt(FifoDataWidth.W), 8))\n // define about fifo write\n fifo_wdata.bits := reggen.io.seteipnum\n fifo_wdata.valid := reggen.io.valid\n fifo_sync.io.enq.valid := fifo_wdata.valid\n fifo_sync.io.enq.bits := fifo_wdata.bits\n // fifo rd,controlled by msi_vld_ack from imsic working on csr clock.\n // msi_vld_ack_soc: sync result with soc clock\n val msi_vld_ack_soc = WireInit(false.B)\n val msi_vld_ack_cpu = msiio.vld_ack\n val msi_vld_req = RegInit(false.B)\n when(params.EnableImsicAsyncBridge.B) {\n msi_vld_ack_soc := AsyncResetSynchronizerShiftReg(msi_vld_ack_cpu, 3, 0)\n }.otherwise {\n msi_vld_ack_soc := msi_vld_ack_cpu\n }\n fifo_sync.io.deq.ready := ~msi_vld_req\n // generate the msi_vld_req: high if ~empty,low when msi_vld_ack_soc\n msiio.vld_req := msi_vld_req\n val msi_vld_ack_soc_1f = RegNext(msi_vld_ack_soc)\n val msi_vld_ack_soc_ris = msi_vld_ack_soc & (~msi_vld_ack_soc_1f)\n // val fifo_empty = ~fifo_sync.io.deq.valid\n // msi_vld_req : high when fifo empty is false, low when ack is high. and io.deq.valid := ~empty\n when(msi_vld_ack_soc_ris) {\n msi_vld_req := false.B\n }.elsewhen(fifo_sync.io.deq.valid === true.B) {\n msi_vld_req := true.B\n }.otherwise {\n msi_vld_req := msi_vld_req\n }\n\n // get the msi interrupt ID info\n val msi_id_data = RegInit(0.U(params.MSI_INFO_WIDTH.W))\n val rdata_vld = fifo_sync.io.deq.fire // assign to fifo rdata\n when(rdata_vld) { // fire: io.deq.valid & io.deq.ready\n msi_id_data := fifo_sync.io.deq.bits(params.MSI_INFO_WIDTH - 1, 0)\n }.otherwise {\n msi_id_data := msi_id_data\n }\n // port connect: io.valid is interrupt file index info.\n msiio.data := msi_id_data\n val backpress = fifo_sync.io.enq.ready\n (intfileFromMems zip reggen.regmapIOs).map {\n case (intfileFromMem, regmapIO) => intfileFromMem.regmap(regmapIO._1, regmapIO._2, backpress)\n }\n }\n}\n\n//integrated for async clock domain,kmh,zhaohong\nclass RegGen(\n params: IMSICParams,\n beatBytes: Int = 4\n) extends Module {\n val regmapIOs = Seq(\n params.intFileMemWidth,\n params.intFileMemWidth + log2Ceil(1 + params.geilen)\n ).map { width =>\n val regmapParams = RegMapperParams(width - log2Up(beatBytes), beatBytes)\n (IO(Flipped(Decoupled(new RegMapperInput(regmapParams)))), IO(Decoupled(new RegMapperOutput(regmapParams))))\n }\n // define the output reg: seteipnum is the MSI id,vld[],valid flag for interrupt file domains: m,s,vs1~vsgeilen\n val io = IO(Output(new Bundle {\n val seteipnum = UInt(params.MSI_INFO_WIDTH.W)\n val valid = Bool()\n }))\n val valids = WireInit(VecInit(Seq.fill(params.intFilesNum)(false.B)))\n val seteipnums = WireInit(VecInit(Seq.fill(params.intFilesNum)(0.U(params.imsicIntSrcWidth.W))))\n val outseteipnum = RegInit(0.U(params.MSI_INFO_WIDTH.W))\n val outvalids = RegInit(VecInit(Seq.fill(params.intFilesNum)(false.B)))\n\n (regmapIOs zip Seq(1, 1 + params.geilen)).zipWithIndex.map { // seq[0]: m interrupt file, seq[1]: s&vs interrupt file\n case ((regmapIO: (DecoupledIO[RegMapperInput], DecoupledIO[RegMapperOutput]), intFilesNum: Int), i: Int) =>\n {\n // j: index is 0 for m file for seq[0],index is 0~params.geilen for S intFile for seq[1]: S, G1, G2, ...\n val maps = (0 until intFilesNum).map { j =>\n val flati = i + j // seq[0]:0+0=0;seq[1]:(0~geilen)+1\n val seteipnum = WireInit(0.U.asTypeOf(Valid(UInt(params.imsicIntSrcWidth.W)))); /*for debug*/\n dontTouch(seteipnum)\n valids(flati) := seteipnum.valid\n seteipnums(flati) := seteipnum.bits\n j * pow2(params.intFileMemWidth).toInt -> Seq(RegField(\n 32,\n 0.U,\n RegWriteFn { (valid, data) =>\n when(valid) { seteipnum.bits := data(params.imsicIntSrcWidth - 1, 0); seteipnum.valid := true.B }; true.B\n }\n ))\n }\n regmapIO._2 <> RegMapper(beatBytes, 1, true, regmapIO._1, maps: _*)\n }\n for (i <- 0 until params.intFilesNum) {\n when(valids(i)) {\n outseteipnum := Cat(i.U, seteipnums(i))\n }\n }\n outvalids := valids\n io.seteipnum := outseteipnum\n io.valid := outvalids.reduce(_ | _)\n }\n}", "groundtruth": " if (params.HasTEEIMSIC) Some(LazyModule(new TLRegIMSIC(params, beatBytes)(Parameters.empty))) else None\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "ChiselAIA", "path": "ChiselAIA/src/main/scala/IMSICParameters.scala", "left_context": "package aia\n\n\nimport chisel3._\nimport org.chipsalliance.cde.config.{Field, Parameters}\n\n\n\n", "right_context": "\ncase class IMSICParameters\n(\n HasTEEIMSIC: Boolean = false\n)\n\n//trait HasIMSICParameters extends IMSICParameters\ntrait HasIMSICParameters {\n implicit val p: Parameters\n\n val IMSICParam = p(IMSICParameKey)\n val GHasTEEIMSIC = IMSICParam.HasTEEIMSIC\n}\n\n", "groundtruth": "case object IMSICParameKey extends Field[IMSICParameters]\n", "crossfile_context": "", "category": "Design Structure", "subcategory": "Parameterization and Configuration", "confidence": 0.7, "category_reason": "Config Field definition"} {"task_id": "ChiselAIA", "path": "ChiselAIA/src/main/scala/common.scala", "left_context": "/***************************************************************************************\n* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)\n*\n* ChiselAIA is licensed under Mulan PSL v2.\n* You can use this software according to the terms and conditions of the Mulan PSL v2.\n* You may obtain a copy of Mulan PSL v2 at:\n* http://license.coscl.org.cn/MulanPSL2\n*\n* THIS SOFTWARE IS PROVIDED ON AN \"AS IS\" BASIS, WITHOUT WARRANTIES OF ANY KIND,\n* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,\n* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.\n*\n* See the Mulan PSL v2 for more details.\n***************************************************************************************/\n\npackage aia\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.amba._\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\nimport freechips.rocketchip.amba.axi4._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.regmapper._\n\nobject pow2 { def apply(n: Int): Long = 1L << n }\n\nclass AXI4ToLite()(implicit p: Parameters) extends LazyModule { \n val node = AXI4AdapterNode( // identity\n masterFn = { mp => \n val masters = (0 until 3).map { i =>\n AXI4MasterParameters(\n name = s\"master_$i\",\n id =IdRange(i * 16, (i + 1) * 16 - 1)\n )\n }.toList\n mp.copy(masters = masters)\n },\n slaveFn = { sp =>\n sp.copy(slaves = sp.slaves.map(s =>\n s.copy(address = s.address.map(a =>\n AddressSet(a.base, a.mask)))))}\n )\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this) {\n (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>\n // out <> in\n dontTouch(in.aw.bits)\n dontTouch(in.ar.bits)\n dontTouch(in.w.bits)\n dontTouch(in.b.bits)\n dontTouch(in.r.bits)\n dontTouch(in.b.ready)\n dontTouch(in.ar.ready)\n // in.ar.bits.addr = in.ar.bits.addr.pad(32)\n // in.aw.bits.addr = in.aw.bits.addr.pad(32)\n val isAWValid = in.aw.valid\n val isARValid = in.ar.valid\n val sIDLE :: sWCH :: sBCH :: Nil =Enum(3)\n val state = RegInit(sIDLE)\n val next_state = WireInit(sIDLE)\n state := next_state\n //code about read state\n val rstate = RegInit(false.B)\n when(isARValid && (!rstate)) {\n rstate := true.B\n }.elsewhen(rstate & in.r.bits.last & in.r.ready) {\n rstate := false.B\n }.otherwise(rstate := rstate)\n\n val rstate_dly = RegInit(false.B)\n rstate_dly := RegNext(rstate)\n\n val awpulse_l = (state === sIDLE) && (next_state === sWCH)\n val arpulse_l = isARValid && (!rstate)\n val awchvld = isAWValid & in.w.valid\n val aw_l = RegEnable(in.aw.bits, awpulse_l)\n val w_l = RegEnable(in.w.bits, awpulse_l)\n // val b_l = RegEnable(in.b.bits, awpulse_l)\n val ar_l = RegEnable(in.ar.bits, arpulse_l)\n // al r_l = RegEnable(in.r.bits, awpulse_l)\n\n //======TODO======//\n val awcnt = RegInit(0.U(8.W)) // width of awcnt is same with awlen\n val arcnt = RegInit(0.U(8.W))\n val addrAW = aw_l.addr\n val addrAR = ar_l.addr\n // only support little-endian (0x0 is active) msi write address check for AW,refer to riscv aia spec.\n val isValidAddressAW = (addrAW(11, 0) === 0.U)\n val isValidAddressAR = (addrAR(11, 0) === 0.U) //\n\n val isValidAlignmentAW = (addrAW(1, 0) === 0.U) // Example alignment check for AW\n val isValidAlignmentAR = (addrAR(1, 0) === 0.U) // Example alignment check for AR\n // val isAccessingValidRegisterAW = (addrAW(11, 2) === 0.U) // Example valid register check for AW\n // val isAccessingValidRegisterAR = (addrAR(11, 2) === 0.U) // Example valid register check for AR\n\n val isWAligErr = !((aw_l.size === 2.U) & (w_l.strb === 15.U) & isValidAlignmentAW) // alignment with 4B.\n val isWCacheErr = false.B//(aw_l.cache(3,1)).orR //non device\n val isWLockErr = aw_l.lock // AMO access\n val isWburstErr = false.B //aw_l.burst(1) //0'b10 or 0'b11 : wrap or reserved\n val isWCErr = isWAligErr | isWCacheErr | isWburstErr\n\n val isRAligErr = !((ar_l.size === 2.U) & isValidAlignmentAR)\n val isRCacheErr = false.B//(ar_l.cache(3,1)).orR //non device\n val isRLockErr = ar_l.lock // AMO access\n val isRburstErr = false.B//ar_l.burst(1) //0'b10 or 0'b11 : wrap or reserved\n val isRCErr = isRAligErr | isRCacheErr | isRburstErr\n // val isReservedAreaAccessAW = !(isAccessingValidRegisterAW) // Reserved area for AW\n // val isReservedAreaAccessAR = !(isAccessingValidRegisterAR) // Reserved area for AR\n\n val isillegalAW = (!isValidAddressAW) | isWCErr | isWLockErr\n val isillegalAR = (!isValidAlignmentAR) | isRCErr | isRLockErr\n\n in.r.bits.last := (arcnt === ar_l.len) && in.r.valid\n val awready = RegInit(false.B) // temp signal ,out.awready for the first data, true.B for other data transaction.\n val wready = RegInit(false.B) // temp signal\n val aw_last = RegInit(false.B)\n val w_last = RegInit(false.B)\n // aw_last: the last addr for burst,\n when (state === sWCH){\n when((awcnt === aw_l.len) & awready){ //may be pulse signal\n aw_last := true.B\n }\n }.otherwise{\n aw_last := false.B\n }\n when (state === sWCH){\n when(in.w.bits.last & in.w.ready){\n w_last := true.B\n }\n }.otherwise{\n w_last := false.B\n }\n val isFinalBurst = aw_last & w_last // may be level signal ,the final data for a transaction\n val w2b_vld = (state === sWCH) & (isillegalAW | out.b.valid) & isFinalBurst\n // val rready = out.ar.ready //ready from downstream\n\n //code about write state\n next_state := state\n switch(state){\n is(sIDLE) {\n when(awchvld){\n next_state := sWCH\n }\n }\n is(sWCH) {\n when(w2b_vld.asBool){ // in.b.valid can be high,only when the last burst data done and the bvalid for data to downstream is high.\n next_state := sBCH\n }\n }\n is(sBCH) {\n when(in.b.ready){\n next_state := sIDLE\n }\n }\n\n }\n when(state === sWCH) {\n when((!isillegalAW) & (!awready) & out.aw.ready & in.aw.valid) { // only the first illegal data to downstream\n awready := true.B\n }.elsewhen(aw_last | (awready & (awcnt === aw_l.len))) {\n awready := false.B\n }.elsewhen(isillegalAW === true.B) {\n awready := true.B\n }\n }.otherwise {\n awready := false.B\n }\n\n when(state === sWCH) {\n when((!isillegalAW) & (!wready) & out.w.ready & in.w.valid) { //first data\n wready := true.B\n }.elsewhen(in.w.bits.last & in.w.ready | w_last) {\n wready := false.B // legal or non first data\n }.elsewhen(isillegalAW === true.B) {\n wready := true.B\n }\n }.otherwise {\n wready := false.B\n }\n when(state === sWCH) {\n when(awcnt >= aw_l.len) { // arrive the max length of burst\n awcnt := awcnt\n }.elsewhen(awready) {\n awcnt := awcnt + 1.U\n }\n }.otherwise {\n awcnt := 0.U\n }\n when(rstate) {\n when(in.r.valid & in.r.ready) {\n arcnt := arcnt + 1.U\n }\n }.otherwise {\n arcnt := 0.U\n }\n // response for in\n val awready_dly = RegInit(false.B)\n awready_dly := awready\n val awready_ris = awready & (!awready_dly)\n\n in.aw.ready := awready_ris\n in.w.ready := wready\n in.b.valid := state === sBCH\n in.b.bits.id := aw_l.id\n in.b.bits.resp := Cat(isWCErr, 0.U)\n val rvalid = RegInit(false.B)\n when(rstate) {\n when(in.r.bits.last & in.r.ready) {\n rvalid := false.B\n }.otherwise {\n rvalid := true.B\n }\n }.otherwise {\n rvalid := false.B\n }\n in.r.valid := rvalid\n in.r.bits.resp := Cat(isRCErr, 0.U)\n in.r.bits.id := ar_l.id\n in.r.bits.data := 0.U\n val arready = RegInit(false.B)\n arready := arpulse_l\n\n in.ar.ready := arready\n\n // When either AW or AR is valid, perform address checks\n val m_awvalid = RegInit(false.B)\n when(awpulse_l) {\n m_awvalid := true.B\n }.elsewhen(out.aw.ready) {\n m_awvalid := false.B\n }.elsewhen(state === sIDLE) {\n m_awvalid := false.B\n }\n out.aw.valid := m_awvalid & (!isillegalAW)\n out.aw.bits.addr := aw_l.addr\n out.aw.bits.id := 0.U\n out.ar.bits.id := 0.U\n out.aw.bits.echo := aw_l.echo\n out.ar.bits.echo := ar_l.echo\n out.aw.bits.size := 2.U\n val m_wvalid = RegInit(false.B)\n when(awpulse_l) {\n m_wvalid := true.B\n }.elsewhen(out.w.ready) {\n m_wvalid := false.B\n }.elsewhen(state === sIDLE) {\n m_wvalid := false.B\n }\n out.w.valid := m_wvalid & (!isillegalAW)\n out.w.bits.strb := 15.U\n out.w.bits.data := w_l.data\n out.w.bits.last := 1.U\n val m_bready = RegInit(false.B)\n when((state === sBCH) && (next_state === sIDLE)) {\n m_bready := true.B\n }.otherwise {\n m_bready := false.B\n }\n out.b.ready := m_bready & (!isillegalAW)\n\n //else out signal is from the signals latched,for timing.\n }\n }\n}\n\n\nclass AXI4Map(fn: AddressSet => BigInt)(implicit p: Parameters) extends LazyModule\n{\n val node = AXI4AdapterNode( // identity\n masterFn = { mp => \n val masters = (0 until 3).map { i =>\n AXI4MasterParameters(\n name = s\"master_$i\",\n id =IdRange(i * 16, (i + 1) * 16 - 1)\n )\n }.toList\n mp.copy(masters = masters)\n },\n slaveFn = { sp =>\n sp.copy(slaves = sp.slaves.map(s =>\n s.copy(address = s.address.map(a =>\n AddressSet(fn(a), a.mask)))))}\n )\n\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this) {\n (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>\n out <> in\n val convert = edgeIn.slave.slaves.flatMap(_.address) zip edgeOut.slave.slaves.flatMap(_.address)\n def forward(x: UInt) =\n convert.map { case (i, o) => Mux(i.contains(x), o.base.U | (x & o.mask.U), 0.U) }.reduce(_ | _)\n def backward(x: UInt) =\n convert.map { case (i, o) => Mux(o.contains(x), i.base.U | (x & i.mask.U), 0.U) }.reduce(_ | _)\n\n out.aw.bits.addr := forward(in.aw.bits.addr)\n out.ar.bits.addr := forward(in.ar.bits.addr)\n }\n }\n}\n\n\nobject AXI4Map\n{\n def apply(fn: AddressSet => BigInt)(implicit p: Parameters): AXI4Node =\n {\n val map = LazyModule(new AXI4Map(fn))\n map.node\n }\n \n}\n\n/**\n * Convert AXI4 master to TileLink **without TLError**.\n *\n * You can use this adapter to connect external AXI4 masters to TileLink bus topology.\n *\n * Setting wcorrupt=true is insufficient to enable w.user.corrupt.\n * One must additionally list it in the AXI4 master's requestFields.\n *\n * @param wcorrupt enable AMBACorrupt in w.user\n */\nclass AXI4ToTLNoTLError(wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule\n{\n val node = AXI4ToTLNode(wcorrupt)\n\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this) {\n (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>\n val numIds = edgeIn.master.endId\n val beatBytes = edgeOut.manager.beatBytes\n val beatCountBits = AXI4Parameters.lenBits + (1 << AXI4Parameters.sizeBits) - 1\n val maxFlight = edgeIn.master.masters.map(_.maxFlight.get).max\n val logFlight = log2Ceil(maxFlight)\n val txnCountBits = log2Ceil(maxFlight+1) // wrap-around must not block b_allow\n val addedBits = logFlight + 1 // +1 for read vs. write source ID\n\n require (edgeIn.master.masters(0).aligned)\n edgeOut.manager.requireFifo()\n\n // // Look for an Error device to redirect bad requests\n // val errorDevs = edgeOut.manager.managers.filter(_.nodePath.last.lazyModule.className == \"TLError\")\n // require (!errorDevs.isEmpty, \"There is no TLError reachable from AXI4ToTL. One must be instantiated.\")\n // val errorDev = errorDevs.maxBy(_.maxTransfer)\n // val error = errorDev.address.head.base\n // require (errorDev.supportsPutPartial.contains(edgeOut.manager.maxTransfer),\n // s\"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support ${edgeOut.manager.maxTransfer}\")\n // require (errorDev.supportsGet.contains(edgeOut.manager.maxTransfer),\n // s\"Error device supports ${errorDev.supportsGet} Get but must support ${edgeOut.manager.maxTransfer}\")\n\n val r_out = WireDefault(out.a)\n val r_size1 = in.ar.bits.bytes1()\n val r_size = OH1ToUInt(r_size1)\n val r_ok = edgeOut.manager.supportsGetSafe(in.ar.bits.addr, r_size)\n // val r_addr = Mux(r_ok, in.ar.bits.addr, error.U | in.ar.bits.addr(log2Up(beatBytes)-1, 0))\n val r_addr = in.ar.bits.addr\n val r_count = RegInit(VecInit.fill(numIds) { 0.U(txnCountBits.W) })\n val r_id = if (maxFlight == 1) {\n Cat(in.ar.bits.id, 0.U(1.W))\n } else {\n Cat(in.ar.bits.id, r_count(in.ar.bits.id)(logFlight-1,0), 0.U(1.W))\n }\n\n assert (!in.ar.valid || r_size1 === UIntToOH1(r_size, beatCountBits)) // because aligned\n in.ar.ready := r_out.ready\n r_out.valid := in.ar.valid\n r_out.bits :<= edgeOut.Get(r_id, r_addr, r_size)._2\n\n Connectable.waiveUnmatched(r_out.bits.user, in.ar.bits.user) match {\n case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll\n }\n\n r_out.bits.user.lift(AMBAProt).foreach { rprot =>\n rprot.privileged := in.ar.bits.prot(0)\n rprot.secure := !in.ar.bits.prot(1)\n rprot.fetch := in.ar.bits.prot(2)\n rprot.bufferable := in.ar.bits.cache(0)\n rprot.modifiable := in.ar.bits.cache(1)\n rprot.readalloc := in.ar.bits.cache(2)\n rprot.writealloc := in.ar.bits.cache(3)\n }\n\n val r_sel = UIntToOH(in.ar.bits.id, numIds)\n (r_sel.asBools zip r_count) foreach { case (s, r) =>\n when (in.ar.fire && s) { r := r + 1.U }\n }\n\n val w_out = WireDefault(out.a)\n val w_size1 = in.aw.bits.bytes1()\n val w_size = OH1ToUInt(w_size1)\n val w_ok = edgeOut.manager.supportsPutPartialSafe(in.aw.bits.addr, w_size)\n // val w_addr = Mux(w_ok, in.aw.bits.addr, error.U | in.aw.bits.addr(log2Up(beatBytes)-1, 0))\n val w_addr = in.aw.bits.addr\n val w_count = RegInit(VecInit.fill(numIds) { 0.U(txnCountBits.W) })\n val w_id = if (maxFlight == 1) {\n Cat(in.aw.bits.id, 1.U(1.W))\n } else {\n Cat(in.aw.bits.id, w_count(in.aw.bits.id)(logFlight-1,0), 1.U(1.W))\n }\n\n assert (!in.aw.valid || w_size1 === UIntToOH1(w_size, beatCountBits)) // because aligned\n assert (!in.aw.valid || in.aw.bits.len === 0.U || in.aw.bits.size === log2Ceil(beatBytes).U) // because aligned\n in.aw.ready := w_out.ready && in.w.valid && in.w.bits.last\n in.w.ready := w_out.ready && in.aw.valid\n w_out.valid := in.aw.valid && in.w.valid\n w_out.bits :<= edgeOut.Put(w_id, w_addr, w_size, in.w.bits.data, in.w.bits.strb)._2\n in.w.bits.user.lift(AMBACorrupt).foreach { w_out.bits.corrupt := _ }\n\n Connectable.waiveUnmatched(w_out.bits.user, in.aw.bits.user) match {\n case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll\n }\n\n w_out.bits.user.lift(AMBAProt).foreach { wprot =>\n wprot.privileged := in.aw.bits.prot(0)\n wprot.secure := !in.aw.bits.prot(1)\n wprot.fetch := in.aw.bits.prot(2)\n wprot.bufferable := in.aw.bits.cache(0)\n wprot.modifiable := in.aw.bits.cache(1)\n wprot.readalloc := in.aw.bits.cache(2)\n wprot.writealloc := in.aw.bits.cache(3)\n }\n\n val w_sel = UIntToOH(in.aw.bits.id, numIds)\n (w_sel.asBools zip w_count) foreach { case (s, r) =>\n when (in.aw.fire && s) { r := r + 1.U }\n }\n\n TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, r_out), (in.aw.bits.len, w_out))\n\n val ok_b = WireDefault(in.b)\n val ok_r = WireDefault(in.r)\n\n val d_resp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)\n val d_hasData = edgeOut.hasData(out.d.bits)\n val d_last = edgeOut.last(out.d)\n\n out.d.ready := Mux(d_hasData, ok_r.ready, ok_b.ready)\n ok_r.valid := out.d.valid && d_hasData\n ok_b.valid := out.d.valid && !d_hasData\n\n ok_r.bits.id := out.d.bits.source >> addedBits\n ok_r.bits.data := out.d.bits.data\n ok_r.bits.resp := d_resp\n ok_r.bits.last := d_last\n ok_r.bits.user :<= out.d.bits.user\n\n // AXI4 needs irrevocable behaviour\n in.r :<>= Queue.irrevocable(ok_r, 1, flow=true)\n\n ok_b.bits.id := out.d.bits.source >> addedBits\n ok_b.bits.resp := d_resp\n ok_b.bits.user :<= out.d.bits.user\n\n // AXI4 needs irrevocable behaviour\n val q_b = Queue.irrevocable(ok_b, 1, flow=true)\n\n // We need to prevent sending B valid before the last W beat is accepted\n // TileLink allows early acknowledgement of a write burst, but AXI does not.\n val b_count = RegInit(VecInit.fill(numIds) { 0.U(txnCountBits.W) })\n val b_allow = b_count(in.b.bits.id) =/= w_count(in.b.bits.id)\n val b_sel = UIntToOH(in.b.bits.id, numIds)\n\n (b_sel.asBools zip b_count) foreach { case (s, r) =>\n", "right_context": " }\n\n in.b.bits :<= q_b.bits\n in.b.valid := q_b.valid && b_allow\n q_b.ready := in.b.ready && b_allow\n\n // Unused channels\n out.b.ready := true.B\n out.c.valid := false.B\n out.e.valid := false.B\n }\n }\n}\n\n// object AXI4ToTL\nobject AXI4ToTLNoTLError\n{\n def apply(wcorrupt: Boolean = true)(implicit p: Parameters) =\n {\n val axi42tl = LazyModule(new AXI4ToTLNoTLError(wcorrupt))\n axi42tl.node\n }\n}\n\n// modifications based on `rocket-chip/src/main/scala/tilelink/RegisterRouter.scala`\ncase class TLRegMapperNode(\n address: Seq[AddressSet],\n beatBytes: Int,\n)(implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1(\n Seq(TLSlaveParameters.v1(\n address = address,\n executable = false,\n supportsGet = TransferSizes(1, beatBytes),\n supportsPutPartial = TransferSizes(1, beatBytes),\n supportsPutFull = TransferSizes(1, beatBytes),\n fifoId = Some(0), // requests are handled in order\n )),\n beatBytes = beatBytes,\n minLatency = 1,\n))) with TLFormatNode {\n val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min)\n require (size >= beatBytes)\n address.foreach { case a =>\n require (a.widen(size-1).base == address.head.widen(size-1).base,\n s\"TLRegMapperNode addresses (${address}) must be aligned to its size ${size}\")\n }\n\n def regmap(in: DecoupledIO[RegMapperInput], out: DecoupledIO[RegMapperOutput], backpress: Bool = true.B) = {\n val (bundleIn, edge) = this.in(0)\n val a = bundleIn.a\n val d = bundleIn.d\n\n in.bits.read := a.bits.opcode === TLMessages.Get\n in.bits.index := edge.addr_hi(a.bits)\n in.bits.data := a.bits.data\n in.bits.mask := a.bits.mask\n Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match {\n case (lhs, rhs) => lhs :<= rhs\n }\n\n // copy a.bits.{source, size} to d.bits.{source, size}\n val sourceReg = RegInit(0.U.asTypeOf(a.bits.source))\n val sizeReg = RegInit(0.U.asTypeOf(a.bits.size))\n when (a.valid) {\n sourceReg := a.bits.source\n sizeReg := a.bits.size\n }\n\n // No flow control needed\n in.valid := a.valid\n a.ready := Mux(in.bits.read, in.ready, (backpress & in.ready))\n d.valid := Mux(out.bits.read, out.valid, (backpress & out.valid))\n out.ready := d.ready\n\n // We must restore the size to enable width adapters to work\n d.bits := edge.AccessAck(toSource = sourceReg, lgSize = sizeReg)\n\n // avoid a Mux on the data bus by manually overriding two fields\n d.bits.data := out.bits.data\n Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match {\n case (lhs, rhs) => lhs :<= rhs\n }\n\n d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck)\n\n // Tie off unused channels\n bundleIn.b.valid := false.B\n bundleIn.c.ready := true.B\n bundleIn.e.ready := true.B\n }\n}\n\n// modification based on `rocket-chip/src/main/scala/amba/axi4/RegisterRouter.scala`\ncase class AXI4RegMapperNode(\n address: AddressSet,\n beatBytes: Int = 4,\n)(implicit valName: ValName) extends SinkNode(AXI4Imp)(Seq(AXI4SlavePortParameters(\n Seq(AXI4SlaveParameters(\n address = Seq(address),\n executable = false,\n supportsWrite = TransferSizes(1, beatBytes),\n supportsRead = TransferSizes(1, beatBytes),\n interleavedId = Some(0))),\n beatBytes = beatBytes,\n minLatency = 1,\n))) {\n require (address.contiguous)\n\n // Calling this method causes the matching AXI4 bundle to be\n // configured to route all requests to the listed RegFields.\n //backpress: add by zhaohong for bus backpressure\n def regmap(in: DecoupledIO[RegMapperInput],out: DecoupledIO[RegMapperOutput], backpress: Bool = true.B) = {\n val (io, _) = this.in(0)\n val ar = io.ar\n val aw = io.aw\n val w = io.w\n val r = io.r\n val b = io.b\n\n dontTouch(aw.bits)\n dontTouch(ar.bits)\n dontTouch(w.bits)\n dontTouch(b.bits)\n dontTouch(r.bits)\n \n // Prefer to execute reads first\n in.valid := ar.valid || (aw.valid && w.valid)\n ar.ready := in.ready\n aw.ready := backpress && in.ready && !ar.valid\n w .ready := backpress && in.ready && !ar.valid\n\n // copy {ar,aw}_bits.{echo,id} to {r,b}_bits.{echo,id}\n val arEchoReg = RegInit(0.U.asTypeOf(ar.bits.echo))\n val awEchoReg = RegInit(0.U.asTypeOf(aw.bits.echo))\n val arIdReg = RegInit(0.U.asTypeOf(ar.bits.id))\n val awIdReg = RegInit(0.U.asTypeOf(aw.bits.id))\n when (ar.valid) { arEchoReg := ar.bits.echo; arIdReg := ar.bits.id }\n when (aw.valid) { awEchoReg := aw.bits.echo; awIdReg := aw.bits.id }\n\n val addr = Mux(ar.valid, ar.bits.addr, aw.bits.addr)\n val mask = MaskGen(ar.bits.addr, ar.bits.size, beatBytes)\n\n in.bits.read := ar.valid\n in.bits.index := addr >> log2Ceil(beatBytes)\n in.bits.data := w.bits.data\n in.bits.mask := Mux(ar.valid, mask, w.bits.strb)\n\n // No flow control needed\n out.ready := Mux(out.bits.read, r.ready, b.ready)\n r.valid := out.valid && out.bits.read\n b.valid := backpress && out.valid && !out.bits.read // backpressure for write operation.\n\n r.bits.id := arIdReg\n r.bits.data := out.bits.data\n r.bits.last := true.B\n r.bits.resp := AXI4Parameters.RESP_OKAY\n r.bits.echo :<= arEchoReg\n\n b.bits.id := awIdReg\n b.bits.resp := AXI4Parameters.RESP_OKAY\n b.bits.echo :<= awEchoReg\n }\n}", "groundtruth": " when (in.b.fire && s) { r := r + 1.U }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "asyncfifo", "path": "asyncfifo/src/main/scala/AsyncQueue.scala", "left_context": "// See LICENSE.SiFive for license details.\n\n// Modified by Aleksi Korsman (aleksi.korsman@aalto.fi), 2024-04-02\n// - Added TestAsyncQueue object\n// Copyright 2024 Aalto University\n\npackage asyncqueue.modules\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.stage.{ChiselStage}\nimport chisel3.stage.ChiselGeneratorAnnotation\n\ncase class AsyncQueueParams(\n depth: Int = 8,\n sync: Int = 3,\n safe: Boolean = true,\n// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.\n// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.\n narrow: Boolean = false)\n// If narrow is true then the read mux is moved to the source side of the crossing.\n// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,\n// at the expense of a combinational path from the sink to the source and back to the sink.\n{\n require (depth > 0 && isPow2(depth))\n require (sync >= 2)\n\n val bits = log2Ceil(depth)\n val wires = if (narrow) 1 else depth\n}\n\nobject AsyncQueueParams {\n // When there is only one entry, we don't need narrow.\n def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)\n}\n\nclass AsyncBundleSafety extends Bundle {\n val ridx_valid = Input (Bool())\n val widx_valid = Output(Bool())\n val source_reset_n = Output(Bool())\n val sink_reset_n = Input (Bool())\n}\n\nclass AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {\n // Data-path synchronization\n val mem = Output(Vec(params.wires, gen))\n val ridx = Input (UInt((params.bits+1).W))\n val widx = Output(UInt((params.bits+1).W))\n val index = params.narrow.option(Input(UInt(params.bits.W)))\n\n // Signals used to self-stabilize a safe AsyncQueue\n val safe = params.safe.option(new AsyncBundleSafety)\n}\n\nobject GrayCounter {\n def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = \"binary\"): UInt = {\n val incremented = Wire(UInt(bits.W))\n val binary = RegNext(next=incremented, init=0.U).suggestName(name)\n incremented := Mux(clear, 0.U, binary + increment.asUInt)\n incremented ^ (incremented >> 1)\n }\n}\n\nclass AsyncValidSync(sync: Int, desc: String) extends RawModule {\n val io = IO(new Bundle {\n val in = Input(Bool())\n val out = Output(Bool())\n })\n val clock = IO(Input(Clock()))\n val reset = IO(Input(AsyncReset()))\n withClockAndReset(clock, reset){\n io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))\n }\n}\n\nclass AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {\n val io = IO(new Bundle {\n // These come from the source domain\n val enq = Flipped(Decoupled(gen))\n // These cross to the sink clock domain\n val async = new AsyncBundle(gen, params)\n })\n\n val bits = params.bits\n val sink_ready = WireInit(true.B)\n val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.\n val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, \"widx_bin\"))\n val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some(\"ridx_gray\"))\n val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)\n\n val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))\n when (io.enq.fire) { mem(index) := io.enq.bits }\n\n val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName(\"ready_reg\"))\n io.enq.ready := ready_reg && sink_ready\n\n val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName(\"widx_gray\"))\n io.async.widx := widx_reg\n\n io.async.index match {\n case Some(index) => io.async.mem(0) := mem(index)\n case None => io.async.mem := mem\n }\n\n io.async.safe.foreach { sio =>\n val source_valid_0 = Module(new AsyncValidSync(params.sync, \"source_valid_0\"))\n val source_valid_1 = Module(new AsyncValidSync(params.sync, \"source_valid_1\"))\n\n val sink_extend = Module(new AsyncValidSync(params.sync, \"sink_extend\"))\n val sink_valid = Module(new AsyncValidSync(params.sync, \"sink_valid\"))\n source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset\n source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset\n sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset\n sink_valid .reset := reset.asAsyncReset\n\n source_valid_0.clock := clock\n source_valid_1.clock := clock\n sink_extend .clock := clock\n sink_valid .clock := clock\n\n source_valid_0.io.in := true.B\n source_valid_1.io.in := source_valid_0.io.out\n sio.widx_valid := source_valid_1.io.out\n sink_extend.io.in := sio.ridx_valid\n sink_valid.io.in := sink_extend.io.out\n sink_ready := sink_valid.io.out\n sio.source_reset_n := !reset.asBool\n\n // Assert that if there is stuff in the queue, then reset cannot happen\n // Impossible to write because dequeue can occur on the receiving side,\n // then reset allowed to happen, but write side cannot know that dequeue\n // occurred.\n // TODO: write some sort of sanity check assertion for users\n // that denote don't reset when there is activity\n // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, \"Enqueue while sink is reset and AsyncQueueSource is unprotected\")\n // assert (!reset_rise || prev_idx_match.asBool, \"Sink reset while AsyncQueueSource not empty\")\n }\n}\n\nclass AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {\n val io = IO(new Bundle {\n // These come from the sink domain\n val deq = Decoupled(gen)\n // These cross to the source clock domain\n val async = Flipped(new AsyncBundle(gen, params))\n })\n\n val bits = params.bits\n val source_ready = WireInit(true.B)\n val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, \"ridx_bin\"))\n val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some(\"widx_gray\"))\n val valid = source_ready && ridx =/= widx\n\n // The mux is safe because timing analysis ensures ridx has reached the register\n // On an ASIC, changes to the unread location cannot affect the selected value\n // On an FPGA, only one input changes at a time => mem updates don't cause glitches\n // The register only latches when the selected valued is not being written\n val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))\n", "right_context": " // This register does not NEED to be reset, as its contents will not\n // be considered unless the asynchronously reset deq valid register is set.\n // It is possible that bits latches when the source domain is reset / has power cut\n // This is safe, because isolation gates brought mem low before the zeroed widx reached us\n val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)\n io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some(\"deq_bits_reg\"))\n\n val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName(\"valid_reg\"))\n io.deq.valid := valid_reg && source_ready\n\n val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName(\"ridx_gray\"))\n io.async.ridx := ridx_reg\n\n io.async.safe.foreach { sio =>\n val sink_valid_0 = Module(new AsyncValidSync(params.sync, \"sink_valid_0\"))\n val sink_valid_1 = Module(new AsyncValidSync(params.sync, \"sink_valid_1\"))\n\n val source_extend = Module(new AsyncValidSync(params.sync, \"source_extend\"))\n val source_valid = Module(new AsyncValidSync(params.sync, \"source_valid\"))\n sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset\n sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset\n source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset\n source_valid .reset := reset.asAsyncReset\n\n sink_valid_0 .clock := clock\n sink_valid_1 .clock := clock\n source_extend.clock := clock\n source_valid .clock := clock\n\n sink_valid_0.io.in := true.B\n sink_valid_1.io.in := sink_valid_0.io.out\n sio.ridx_valid := sink_valid_1.io.out\n source_extend.io.in := sio.widx_valid\n source_valid.io.in := source_extend.io.out\n source_ready := source_valid.io.out\n sio.sink_reset_n := !reset.asBool\n\n // TODO: write some sort of sanity check assertion for users\n // that denote don't reset when there is activity\n // \n // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool\n // val reset_and_extend_prev = RegNext(reset_and_extend, true.B)\n // val reset_rise = !reset_and_extend_prev && reset_and_extend\n // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)\n // assert (!reset_rise || prev_idx_match.asBool, \"Source reset while AsyncQueueSink not empty\")\n }\n}\n\nobject FromAsyncBundle\n{\n // Sometimes it makes sense for the sink to have different sync than the source\n def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)\n def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {\n val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))\n sink.io.async <> x\n sink.io.deq\n }\n}\n\nobject ToAsyncBundle\n{\n def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {\n val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))\n source.io.enq <> x\n source.io.async\n }\n}\n\nclass AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {\n val io = IO(new CrossingIO(gen))\n val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }\n val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }\n\n source.io.enq <> io.enq\n io.deq <> sink.io.deq\n sink.io.async <> source.io.async\n}\n\nobject TestAsyncQueue extends App {\n // Generate verilog\n (new ChiselStage).execute(\n args,\n Seq(\n ChiselGeneratorAnnotation(() => {\n new AsyncQueue(\n UInt(32.W),\n AsyncQueueParams(\n depth = 8,\n sync = 3,\n safe = false,\n narrow = false\n )\n )\n }),\n )\n )\n}", "groundtruth": " io.async.index.foreach { _ := index }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Loop-based Control", "confidence": 0.75, "category_reason": "Functional iteration"} {"task_id": "asyncfifo", "path": "asyncfifo/src/main/scala/AsyncResetReg.scala", "left_context": "// See LICENSE.SiFive for license details.\n\npackage asyncqueue.modules\n\n\n\nimport chisel3._\n\n/** This black-boxes an Async Reset\n * (or Set)\n * Register.\n * \n * Because Chisel doesn't support\n * parameterized black boxes, \n * we unfortunately have to \n * instantiate a number of these.\n * \n * We also have to hard-code the set/\n * reset behavior.\n * \n * Do not confuse an asynchronous\n * reset signal with an asynchronously\n * reset reg. You should still \n * properly synchronize your reset \n * deassertion.\n * \n * @param d Data input\n * @param q Data Output\n * @param clk Clock Input\n * @param rst Reset Input\n * @param en Write Enable Input\n * \n */\n\nclass AsyncResetReg(resetValue: Int = 0) extends RawModule {\n val io = IO(new Bundle {\n val d = Input(Bool())\n val q = Output(Bool())\n val en = Input(Bool())\n\n val clk = Input(Clock())\n val rst = Input(Reset())\n })\n\n val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W)))\n when (io.en) {\n reg := io.d\n }\n io.q := reg\n}\n\nclass SimpleRegIO(val w: Int) extends Bundle{\n val d = Input(UInt(w.W))\n val q = Output(UInt(w.W))\n val en = Input(Bool())\n}\n\nclass AsyncResetRegVec(val w: Int, val init: BigInt) extends Module {\n override def desiredName = s\"AsyncResetRegVec_w${w}_i${init}\"\n\n val io = IO(new SimpleRegIO(w))\n\n val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W)))\n when (io.en) {\n reg := io.d\n }\n io.q := reg\n}\n\nobject AsyncResetReg {\n // Create Single Registers\n def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = {\n val reg = Module(new AsyncResetReg(if (init) 1 else 0))\n reg.io.d := d\n reg.io.clk := clk\n reg.io.rst := rst\n reg.io.en := true.B\n name.foreach(reg.suggestName(_))\n reg.io.q\n }\n\n def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, init = false, None)\n def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, init = false, Some(name))\n\n // Create Vectors of Registers\n def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = {\n val w = updateData.getWidth max resetData.bitLength\n val reg = Module(new AsyncResetRegVec(w, resetData))\n name.foreach(reg.suggestName(_))\n reg.io.d := updateData\n reg.io.en := enable\n reg.io.q\n }\n def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData,\n resetData, enable, Some(name))\n\n\n", "right_context": " def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name))\n\n def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable)\n def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name))\n\n def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B)\n def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name))\n}\n", "groundtruth": " def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "asyncfifo", "path": "asyncfifo/src/main/scala/CompileOptions.scala", "left_context": "// See LICENSE.SiFive for license details.\n\npackage asyncqueue.modules\n\nimport chisel3.ExplicitCompileOptions.NotStrict\n\n", "right_context": "", "groundtruth": "object CompileOptions {\n /** Compatibility mode semantics except Module implicit reset should be inferred instead of Bool */\n implicit val NotStrictInferReset = NotStrict.copy(inferModuleReset = true)\n}", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.6, "category_reason": "val binding"} {"task_id": "asyncfifo", "path": "asyncfifo/src/main/scala/Crossing.scala", "left_context": "// See LICENSE.SiFive for license details.\n\npackage asyncqueue.modules\n\nimport chisel3._\nimport chisel3.util._\n\nclass CrossingIO[T <: Data](gen: T) extends Bundle {\n // Enqueue clock domain\n val enq_clock = Input(Clock())\n val enq_reset = Input(Bool()) // synchronously deasserted wrt. enq_clock\n val enq = Flipped(Decoupled(gen))\n // Dequeue clock domain\n val deq_clock = Input(Clock())\n val deq_reset = Input(Bool()) // synchronously deasserted wrt. deq_clock\n val deq = Decoupled(gen)\n}\n\n", "right_context": "", "groundtruth": "abstract class Crossing[T <: Data] extends RawModule {\n val io: CrossingIO[T]\n}", "crossfile_context": "", "category": "Design Structure", "subcategory": "Top-level Structure", "confidence": 0.85, "category_reason": "Module class definition"} {"task_id": "asyncfifo", "path": "asyncfifo/src/main/scala/ShiftReg.scala", "left_context": "// See LICENSE.SiFive for license details.\n\npackage asyncqueue.modules\n\nimport chisel3._\n\n// Similar to the Chisel ShiftRegister but allows the user to suggest a\n// name to the registers that get instantiated, and\n// to provide a reset value.\nobject ShiftRegInit {\n def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =\n\n (0 until n).foldRight(in) {\n case (i, next) => {\n val r = RegNext(next, init = init)\n name.foreach { na => r.suggestName(s\"${na}_${i}\") }\n r\n }\n }\n}\n\n/** These wrap behavioral\n * shift registers into specific modules to allow for\n * backend flows to replace or constrain\n * them properly when used for CDC synchronization,\n * rather than buffering.\n * \n * The different types vary in their reset behavior:\n * AsyncResetShiftReg -- Asynchronously reset register array\n * A W(width) x D(depth) sized array is constructed from D instantiations of a\n * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,\n * but only used for timing applications\n */\n\nabstract class AbstractPipelineReg(w: Int = 1) extends Module {\n val io = IO(new Bundle {\n val d = Input(UInt(w.W))\n val q = Output(UInt(w.W))\n }\n )\n}\n\nobject AbstractPipelineReg {\n def apply [T <: Chisel.Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {\n val chain = Module(gen)\n name.foreach{ chain.suggestName(_) }\n chain.io.d := in.asUInt\n chain.io.q.asTypeOf(in)\n }\n}\n\nclass AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = \"pipe\") extends AbstractPipelineReg(w) {\n require(depth > 0, \"Depth must be greater than 0.\")\n\n override def desiredName = s\"AsyncResetShiftReg_w${w}_d${depth}_i${init}\"\n\n val chain = List.tabulate(depth) { i =>\n", "right_context": " }\n\n chain.last.io.d := io.d\n chain.last.io.en := true.B\n\n (chain.init zip chain.tail).foreach { case (sink, source) =>\n sink.io.d := source.io.q\n sink.io.en := true.B\n }\n io.q := chain.head.io.q\n}\n\nobject AsyncResetShiftReg {\n def apply [T <: Chisel.Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =\n AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)\n\n def apply [T <: Chisel.Data](in: T, depth: Int, name: Option[String]): T =\n apply(in, depth, 0, name)\n\n def apply [T <: Chisel.Data](in: T, depth: Int, init: T, name: Option[String]): T =\n apply(in, depth, init.litValue.toInt, name)\n\n def apply [T <: Chisel.Data](in: T, depth: Int, init: T): T =\n apply (in, depth, init.litValue.toInt, None)\n}", "groundtruth": " Module (new AsyncResetRegVec(w, init)).suggestName(s\"${name}_${i}\")\n", "crossfile_context": "", "category": "Design Structure", "subcategory": "Hierarchical Composition", "confidence": 0.7, "category_reason": "Module instantiation"} {"task_id": "asyncfifo", "path": "asyncfifo/src/main/scala/SynchronizerReg.scala", "left_context": "// See LICENSE.SiFive for license details.\n\npackage asyncqueue.modules\n\nimport chisel3._\nimport chisel3.util.{RegEnable, Cat}\n\n/** These wrap behavioral\n * shift and next registers into specific modules to allow for\n * backend flows to replace or constrain\n * them properly when used for CDC synchronization,\n * rather than buffering.\n * \n * \n * These are built up of *ResetSynchronizerPrimitiveShiftReg,\n * intended to be replaced by the integrator's metastable flops chains or replaced\n * at this level if they have a multi-bit wide synchronizer primitive.\n * The different types vary in their reset behavior:\n * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin\n * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep\n * 1-bit-wide shift registers.\n * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg\n * \n * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.\n * \n * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross\n * Clock Domains.\n*/\n\nobject SynchronizerResetType extends Enumeration {\n val NonSync, Inferred, Sync, Async = Value\n}\n\n\n// Note: this should not be used directly.\n// Use the companion object to generate this with the correct reset type mixin.\nprivate class SynchronizerPrimitiveShiftReg(\n sync: Int,\n init: Boolean,\n resetType: SynchronizerResetType.Value)\n extends AbstractPipelineReg(1) {\n\n val initInt = if (init) 1 else 0\n val initPostfix = resetType match {\n case SynchronizerResetType.NonSync => \"\"\n case _ => s\"_i${initInt}\"\n }\n override def desiredName = s\"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}\"\n\n val chain = List.tabulate(sync) { i =>\n", "right_context": " reg.suggestName(s\"sync_$i\")\n }\n chain.last := io.d.asBool\n\n (chain.init zip chain.tail).foreach { case (sink, source) =>\n sink := source\n }\n io.q := chain.head.asUInt\n}\n\nprivate object SynchronizerPrimitiveShiftReg {\n def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {\n val gen: () => SynchronizerPrimitiveShiftReg = resetType match {\n case SynchronizerResetType.NonSync =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType)\n case SynchronizerResetType.Async =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset\n case SynchronizerResetType.Sync =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset\n case SynchronizerResetType.Inferred =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType)\n }\n AbstractPipelineReg(gen(), in)\n }\n}\n\n// Note: This module may end up with a non-AsyncReset type reset.\n// But the Primitives within will always have AsyncReset type.\nclass AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)\n extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n withReset(reset.asAsyncReset){\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)\n }\n }\n io.q := Cat(output.reverse)\n}\n\nobject AsyncResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\n// Note: This module may end up with a non-Bool type reset.\n// But the Primitives within will always have Bool reset type.\n@deprecated(\"SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.\", \"rocket-chip 1.2\")\nclass SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n withReset(reset.asBool){\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)\n }\n }\n io.q := Cat(output.reverse)\n}\n\nobject SyncResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\nclass ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)\n }\n io.q := Cat(output.reverse)\n}\n\nobject ResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\nclass SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"SynchronizerShiftReg_w${w}_d${sync}\"\n val output = Seq.tabulate(w) { i =>\n SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)\n }\n io.q := Cat(output.reverse)\n}\n\nobject SynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =\n if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, None)\n\n def apply [T <: Data](in: T): T =\n apply (in, 3, None)\n\n\n}\n\nclass ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {\n\n override def desiredName = s\"ClockCrossingReg_w${w}\"\n\n val io = IO(new Bundle{\n val d = Input(UInt(w.W))\n val q = Output(UInt(w.W))\n val en = Input(Bool())\n })\n\n val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)\n io.q := cdc_reg\n}\n\nobject ClockCrossingReg {\n def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {\n val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))\n name.foreach{ cdc_reg.suggestName(_) }\n cdc_reg.io.d := in.asUInt\n cdc_reg.io.en := en\n cdc_reg.io.q.asTypeOf(in)\n }\n}", "groundtruth": " val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)\n", "crossfile_context": "", "category": "Storage Block", "subcategory": "Register-based Storage", "confidence": 0.85, "category_reason": "RegInit register"} {"task_id": "asyncfifo", "path": "asyncfifo/src/main/scala/package.scala", "left_context": "// See LICENSE.SiFive for license details.\n// This file is a selection of implicits used in AsyncQueue.\n\npackage asyncqueue\n\nimport Chisel._\n\npackage object modules {\n implicit class SeqToAugmentedSeq[T <: Data](val x: Seq[T]) extends AnyVal {\n def asUInt(): UInt = Cat(x.map(_.asUInt).reverse)\n }\n\n implicit class UIntToAugmentedUInt(val x: UInt) extends AnyVal {\n def padTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(UInt(0, n - x.getWidth), x)\n }\n }\n\n implicit class IntToAugmentedInt(val x: Int) extends AnyVal {\n // exact log2\n def log2: Int = {\n require(isPow2(x))\n log2Ceil(x)\n }\n }\n\n implicit class BooleanToAugmentedBoolean(val x: Boolean) extends AnyVal {\n // this one's snagged from scalaz\n", "right_context": " }\n}", "groundtruth": " def option[T](z: => T): Option[T] = if (x) Some(z) else None\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "simpleinst", "path": "simpleinst/src/main/scala/BpfCircuitConstructor.scala", "left_context": "package freechips.rocketchip.instrumenter\n\nimport chisel3._\nimport chisel3.util.Cat\nimport freechips.rocketchip.instrumenter.BpfLoader.BpfInsn\nimport freechips.rocketchip.util._\n\ntrait BpfCircuitConstructor {\n val mask32 = \"hFFFFFFFF\".U(64.W)\n val mask64 = \"hFFFFFFFFFFFFFFFF\".U(64.W)\n\n def posedge(x: Bool): Bool = x && !RegNext(x)\n\n def forceWidth(data: UInt, width: Int = 64): UInt = {\n require(data.isWidthKnown)\n val w = data.getWidth\n if (w < width)\n Cat(0.U(width - w), data)\n else if (w > width)\n data(width - 1, 0)\n else\n data\n }\n\n type LazyData = (Resolved, Bool)\n private final case class Context\n (\n inputValid: Bool,\n globalReady: Bool,\n regMapping: Map[Int, LazyData],\n auxRegMapping: Map[UInt, Bool] = Map.empty\n ) {\n def getAuxValid(reg: UInt): Bool = auxRegMapping.getOrElse(reg, inputValid)\n def withAuxValid(reg: UInt, valid: Bool): Context = copy(\n auxRegMapping = auxRegMapping.updated(reg, getAuxValid(reg) && valid)\n )\n\n def get(ind: Int): LazyData = regMapping.getOrElse(ind, (Value(forceWidth(0.U)), inputValid))\n def queue(maybeReg: Resolved, done: Bool): Context = {\n val newGlobalReady = globalReady && done\n val t = maybeReg match {\n case Value(_) => this\n case RegisterReference(reg) => withAuxValid(reg, done)\n }\n t.copy(globalReady = newGlobalReady)\n }\n def result: (UInt, Bool) = {\n val (Value(result), resultValid) = get(0)\n result -> (resultValid && globalReady)\n }\n", "right_context": " def resolve(x: Either[Long, BpfLoader.Symbol]): (Resolved, Bool) = x match {\n case Left(value) => Value(value.U) -> inputValid\n case Right(sym) => resolveSymbol(sym) -> inputValid\n }\n }\n\n final case class Opnds(x: () => UInt, y: () => UInt, c: () => UInt) {\n def xy(op: (UInt, UInt) => UInt): UInt = op(x(), y())\n def xc(op: (UInt, UInt) => UInt): UInt = op(x(), c())\n }\n final case class OpndsValid(xv: Bool, yv: Bool, cv: Bool) {\n def xy: Bool = xv && yv\n def xc: Bool = xv && cv\n }\n type AluOpDesc = (Opnds => UInt, OpndsValid => Bool)\n private def constThenY(op: (UInt, UInt) => UInt) = Seq[AluOpDesc](\n (_.xc(op), _.xc),\n (_.xy(op), _.xy)\n )\n private def aluTable: Seq[AluOpDesc] = Seq(\n constThenY(_ +% _),\n constThenY(_ -% _),\n constThenY(_ * _),\n constThenY(_ / _),\n constThenY(_ | _),\n constThenY(_ & _),\n constThenY((a, b) => (a << b(5, 0)).asUInt()),\n constThenY((a, b) => (a >> b(5, 0)).asUInt()),\n Seq[AluOpDesc](\n (0.U -% _.x(), _.xv),\n (0.U -% _.x(), _.xv) // second time\n ),\n constThenY(_ % _), // TODO\n constThenY(_ ^ _),\n Seq[AluOpDesc](\n (_.c(), _.cv),\n (_.y(), _.yv),\n ),\n constThenY((a, b) => (a.asSInt() >> b(5, 0)).asUInt()),\n ).flatten\n\n private def createAlu(insn: BpfInsn, tail: List[BpfInsn], ctx: Context, mask: UInt): Context = {\n val num = insn.opcode >> 3\n val (op, opValid) = aluTable(num)\n\n val (dst, dstValid) = ctx.get(insn.dst)\n val (src, srcValid) = ctx.get(insn.src)\n val (imm, immValid) = ctx.resolve(insn.imm)\n\n val res = op(Opnds(\n () => dst.asPlainValue & mask,\n () => src.asPlainValue & mask,\n () => imm.asPlainValue & mask\n ))\n val valid = opValid(OpndsValid(dstValid, srcValid, immValid))\n createCircuit(tail, ctx.set(insn.dst, (Value(forceWidth(res)), valid)))\n }\n\n private val loadLgSizeByOpc = Map(0x61 -> u32, 0x69 -> u16, 0x71 -> u8, 0x79 -> u64)\n private val storeImmLgSizeByOpc = Map(0x62 -> u32, 0x6a -> u16, 0x72 -> u8, 0x7a -> u64)\n private val storeLgSizeByOpc = Map(0x63 -> u32, 0x69 -> u16, 0x73 -> u8, 0x7b -> u64)\n\n private def createLdst(insn: BpfInsn, tail: List[BpfInsn], ctx: Context): Context = {\n if (loadLgSizeByOpc.contains(insn.opcode)) {\n val (addr, addrValid) = ctx.get(insn.src)\n val newNode = addr.load(ctx, insn.offset, loadLgSizeByOpc(insn.opcode), addrValid)\n createCircuit(tail, ctx.queue(addr, newNode._2).set(insn.dst, newNode))\n } else if (storeImmLgSizeByOpc.contains(insn.opcode)) {\n val (addr, addrValid) = ctx.get(insn.dst)\n val (Value(imm), immValid) = ctx.resolve(insn.imm)\n val storeDone = addr.store(insn.offset, storeImmLgSizeByOpc(insn.opcode), imm, addrValid && immValid)\n createCircuit(tail, ctx.queue(addr, storeDone))\n } else { // store reg\n val (addr, addrValid) = ctx.get(insn.dst)\n val (Value(src), srcValid) = ctx.get(insn.src)\n val storeDone = addr.store(insn.offset, storeLgSizeByOpc(insn.opcode), src, addrValid && srcValid)\n createCircuit(tail, ctx.queue(addr, storeDone))\n }\n }\n\n def createByteswap(arg: LazyData, size: Int): LazyData = {\n val (Value(data), valid) = arg\n val resultingBytes = (0 until size / 8).map { byteInd =>\n (data >> (byteInd * 8)).asUInt()(7, 0)\n }\n Value(Cat(resultingBytes)) -> valid\n }\n\n // TODO add sequential dependencies?\n private def createCircuit(progTail: List[BpfInsn], ctx: Context): Context = {\n progTail match {\n case Nil => ctx\n case i :: Nil if i.opcode == 0x95 => ctx // exit\n case i :: is if i.opcode == 0xd4 => // htole on le host\n createCircuit(is, ctx)\n case i :: is if i.opcode == 0xdc => // htobe on le host\n createCircuit(is, ctx.set(i.dst, createByteswap(ctx.get(i.dst), i.imm.left.get.toInt)))\n case i :: is if (i.opcode & 0x07) == 0x07 => // 64 bit ALU\n createAlu(i, is, ctx, mask64)\n case i :: is if (i.opcode & 0x07) == 0x04 => // 32 bit ALU\n createAlu(i, is, ctx, mask32)\n case i :: is if i.opcode == 0x18 => // load imm\n createCircuit(is, ctx.set(i.dst, ctx.resolve(i.imm)))\n case i :: is if Seq(0x01, 0x02, 0x03).contains(i.opcode & 0x07) =>\n createLdst(i, is, ctx)\n case _ => ???\n }\n }\n\n sealed abstract class LdStType(val lgsize: Int) {\n val byteSize = 1 << lgsize\n val bitSize = byteSize * 8\n val mask: UInt = if (bitSize == 64) mask64 else ((1l << bitSize) - 1).U\n }\n case object u8 extends LdStType(0)\n case object u16 extends LdStType(1)\n case object u32 extends LdStType(2)\n case object u64 extends LdStType(3)\n\n def doMemLoad(addr: UInt, tpe: LdStType, valid: Bool): (UInt, Bool)\n def doMemStore(addr: UInt, tpe: LdStType, data: UInt, valid: Bool): Bool\n\n sealed trait Resolved {\n def asPlainValue: UInt\n def load(ctx: Context, offset: Int, tpe: LdStType, valid: Bool): LazyData\n def store(offset: Int, tpe: LdStType, data: UInt, valid: Bool): Bool\n }\n final case class Value(value: UInt) extends Resolved {\n override def asPlainValue: UInt = value\n override def load(ctx: Context, offset: Int, tpe: LdStType, valid: Bool): (Resolved, Bool) = {\n val (result, done) = doMemLoad(value + offset.U, tpe, valid)\n Value(result) -> done\n }\n override def store(offset: Int, tpe: LdStType, data: UInt, valid: Bool): Bool = {\n doMemStore(value + offset.U, tpe, data, valid)\n }\n }\n final case class RegisterReference(reg: UInt) extends Resolved {\n override def asPlainValue: UInt = ???\n override def load(ctx: Context, offset: Int, tpe: LdStType, valid: Bool): (Resolved, Bool) = {\n require(offset == 0)\n val allValid = valid && ctx.getAuxValid(reg)\n when (posedge(allValid)) {\n printf(\"Reg load: %d\\n\", reg & tpe.mask)\n }\n Value((reg & tpe.mask) holdUnless posedge(allValid)) -> allValid\n }\n\n override def store(offset: Int, tpe: LdStType, data: UInt, valid: Bool): Bool = {\n require(offset == 0)\n when (posedge(valid)) {\n printf(\"Reg store: %d\\n\", data & tpe.mask)\n reg := data & tpe.mask\n }\n valid && RegNext(valid)\n }\n }\n def resolveSymbol(sym: BpfLoader.Symbol): Resolved\n\n def processProgram(\n valid: Bool,\n program: Seq[BpfInsn],\n args: UInt*\n ): (UInt, Bool) = {\n val ctx = Context(\n valid,\n valid,\n args.zipWithIndex.map {\n case (arg, ind) => (ind + 1) -> (Value(forceWidth(arg & mask64)) -> valid)\n }.toMap,\n )\n createCircuit(program.toList, ctx).result\n }\n}\n", "groundtruth": " def set(ind: Int, data: LazyData): Context = copy(regMapping = regMapping.updated(ind, data))\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "simpleinst", "path": "simpleinst/src/main/scala/BpfLoader.scala", "left_context": "package freechips.rocketchip.instrumenter\n\nimport java.nio.file.{Files, Paths}\nimport java.nio.{ByteBuffer, ByteOrder}\n\n\nimport scala.collection.mutable.ArrayBuffer\n\nobject BpfLoader {\n import ElfConstants._\n\n sealed trait SectionKind\n case object RegularSection extends SectionKind\n case object SymtabSection extends SectionKind\n case object StrtabSection extends SectionKind\n case object RelSection extends SectionKind\n\n final case class Elf64Header(sectionHeaders: Seq[ByteBuffer], sectionStringTableIndex: Int)\n final case class Elf64Section(data: ByteBuffer, linkIndex: Int, infoIndex: Int, kind: SectionKind)\n final case class Symbol(name: String, value: Int, size: Int, shndx: Int, isInstrumenter: Boolean)\n final case class Relocation(relocatedSection: Int, offset: Int, symbol: Symbol)\n\n final case class BpfInsn(opcode: Int, dst: Int, src: Int, offset: Int, imm: Either[Long, Symbol])\n final case class BpfProg(name: String, insns: Seq[BpfInsn])\n\n def isDoubleWidthOpcode(opcode: Int): Boolean = opcode == 0x18\n\n def relocatedInsn(buffer: ByteBuffer, ind: Int, sym: Symbol): BpfInsn = notRelocatedInsn(buffer, ind).copy(imm = Right(sym))\n def notRelocatedInsn(buffer: ByteBuffer, ind: Int): BpfInsn = {\n val raw = buffer.getLong(ind)\n val opcode = (raw & 0xFF).toInt\n val hi_imm = if (isDoubleWidthOpcode(opcode)) buffer.getLong(ind + 8) & 0xFFFFFFFF00000000l else 0\n BpfInsn(\n opcode = opcode,\n dst = ((raw >> 8) & 0xF).toInt,\n src = ((raw >> 12) & 0xF).toInt,\n offset = ((raw >> 16) & 0xFFFF).toInt,\n imm = Left(((raw >> 32) & 0xFFFFFFFFl) | hi_imm)\n )\n }\n\n\n def getString(strtab: ByteBuffer, start: Int): String = {\n val array = strtab.array()\n val realStart = strtab.arrayOffset() + start\n var end = realStart\n while (array(end) != 0)\n end += 1\n new String(array, realStart, end - realStart)\n }\n\n def headerFrom(data: ByteBuffer): Elf64Header = {\n import Elf64_Ehdr._\n {\n import e_ident._\n assert(data.getInt(0) == ElfMagic)\n assert(data.get(EI_CLASS) == ELFCLASS64)\n assert(data.get(EI_DATA) == ELFDATA2LSB)\n assert(data.get(EI_VERSION) == EV_CURRENT)\n }\n assert(data.getShort(TypeOffset) == ET_REL)\n assert(data.getShort(MachineOffset) == EM_BPF)\n\n val sectionTableOffset = data.getLong(ShOffsetOffset).toInt\n assert(sectionTableOffset != 0)\n\n val sectionNumber = data.getShort(ShNumOffset)\n val sectionHeaderSize = data.getShort(ShentSizeOffset)\n val sectionStrtabInd = data.getShort(ShStrndxOffset)\n\n val sectionHeaders = (0 until sectionNumber).map { ind =>\n data.position(sectionTableOffset + ind * sectionHeaderSize)\n data.limit(sectionTableOffset + (ind + 1) * sectionHeaderSize)\n data.slice().order(ByteOrder.LITTLE_ENDIAN)\n }\n\n Elf64Header(sectionHeaders, sectionStrtabInd)\n }\n\n def createSection(data: ByteBuffer, shdrData: ByteBuffer, names: Option[ByteBuffer]): Elf64Section = {\n import Elf64_Shdr._\n\n val nameOffset = shdrData.getInt(NameOffset)\n val name = names.map(getString(_, nameOffset)).getOrElse(\"\")\n val tpe = shdrData.getInt(TypeOffset)\n val offset = shdrData.getLong(OffsetOffset).toInt\n val size = shdrData.getLong(SizeOffset).toInt\n val link = shdrData.getInt(LinkOffset)\n val info = shdrData.getInt(InfoOffset)\n\n val sectionData = tpe match {\n case SHT_NULL => null\n case SHT_NOBITS => ByteBuffer.allocate(size)\n case _ =>\n data.position(0)\n data.limit(offset + size)\n data.position(offset)\n data.slice().order(ByteOrder.LITTLE_ENDIAN)\n }\n val sectionKind = tpe match {\n case SHT_STRTAB => StrtabSection\n", "right_context": " case _ => RegularSection\n }\n Elf64Section(sectionData, link, info, sectionKind)\n }\n\n def parseSymbols(symtab: ByteBuffer, symstrtab: ByteBuffer): Seq[Symbol] = {\n import Elf64_Sym._\n (0 until (symtab.capacity() / TotalSize)).map { ind =>\n val nameOffset = symtab.getShort(ind * TotalSize + NameOffset)\n val tpe = symtab.get(ind * TotalSize + InfoOffset)\n val shndx = symtab.getShort(ind * TotalSize + ShndxOffset)\n val value = symtab.getLong(ind * TotalSize + ValueOffset).toInt\n val size = symtab.getLong(ind * TotalSize + SizeOffset).toInt\n\n val name = getString(symstrtab, nameOffset)\n Symbol(name, value, size, shndx, tpe == GlobalFunction)\n }\n }\n\n def collectRelocations(sections: Seq[Elf64Section], symstrtab: ByteBuffer, rel: Elf64Section): Seq[Relocation] = {\n import Elf64_Rel._\n val data = rel.data\n val syms = parseSymbols(sections(rel.linkIndex).data, symstrtab)\n (0 until (data.capacity() / TotalSize)).map { ind =>\n val offset = data.getLong(ind * TotalSize + OffsetOffset).toInt\n val info = data.getLong(ind * TotalSize + InfoOffset)\n val tpe = r_type(info)\n val sym = r_sym(info).toInt\n\n assert(tpe == R_BPF_64_64)\n\n Relocation(rel.infoIndex, offset, syms(sym))\n }\n }\n\n def parseInstrumenters(syms: Seq[Symbol], sectionData: ByteBuffer, relocs: Seq[Relocation]): Seq[BpfProg] = {\n // values are supposed to be of length 1\n val relocsByOffset = relocs.groupBy(_.offset)\n\n syms.filter(_.isInstrumenter).map { sym =>\n var cur = sym.value\n val end = sym.value + sym.size\n val insns = ArrayBuffer[BpfInsn]()\n while (cur < end) {\n val insn = relocsByOffset.get(cur) match {\n case None => notRelocatedInsn(sectionData, cur)\n case Some(Seq(rel)) => relocatedInsn(sectionData, cur, rel.symbol)\n }\n cur += (if (isDoubleWidthOpcode(insn.opcode)) 16 else 8)\n insns += insn\n }\n BpfProg(sym.name, insns)\n }\n }\n\n def fetchProgs(data: ByteBuffer): Seq[BpfProg] = {\n data.order(ByteOrder.LITTLE_ENDIAN)\n val header = headerFrom(data)\n val strtab = createSection(data, header.sectionHeaders(header.sectionStringTableIndex), None)\n val sections = header.sectionHeaders.map { sectionHeaderData =>\n createSection(data, sectionHeaderData, Some(strtab.data))\n }\n val symtab = sections.find(_.kind == SymtabSection).get\n val symstrtab = sections.find(_.kind == StrtabSection).get\n\n val relocs = sections\n .collect {\n case rel@Elf64Section(_, _, _, `RelSection`) =>\n collectRelocations(sections, symstrtab.data, rel)\n }\n .flatten\n val syms = parseSymbols(symtab.data, symstrtab.data)\n\n syms\n .groupBy(_.shndx)\n .flatMap {\n case (0xFFFFFFF1 | 0xFFFFFFF2, _) =>\n Seq()\n case (shndx, theseSymbols) =>\n parseInstrumenters(theseSymbols, sections(shndx).data, relocs.filter(_.relocatedSection == shndx))\n }\n .toSeq\n }\n def fetchProgs(file: String): Seq[BpfProg] = {\n val data = Files.readAllBytes(Paths.get(file))\n fetchProgs(ByteBuffer.wrap(data))\n }\n}\n", "groundtruth": " case SHT_SYMTAB => SymtabSection\n case SHT_REL => RelSection\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.7, "category_reason": "Scala case/match expression"} {"task_id": "simpleinst", "path": "simpleinst/src/main/scala/ElfConstants.scala", "left_context": "package freechips.rocketchip.instrumenter\n\nobject ElfConstants {\n object Elf64_Ehdr {\n object e_ident {\n val ElfMagic = 0x464c457f // [0x7F, 'E', 'L', 'F']\n\n val EI_CLASS = 4\n val EI_DATA = 5\n val EI_VERSION = 6\n\n val ELFCLASS32 = 1\n val ELFCLASS64 = 2\n\n val ELFDATA2LSB = 1\n val ELFDATA2MSB = 2\n\n val EV_CURRENT = 1\n }\n val TypeOffset = 16\n val MachineOffset = 18\n val ShOffsetOffset = 40\n val ShentSizeOffset = 58\n val ShNumOffset = 60\n val ShStrndxOffset = 62\n\n val ET_REL = 1\n val EM_BPF = 247\n }\n\n object Elf64_Shdr {\n val NameOffset = 0\n val TypeOffset = 4\n val OffsetOffset = 24\n val SizeOffset = 32\n val LinkOffset = 40\n val InfoOffset = 44\n\n val SHT_NULL = 0\n val SHT_NOBITS = 8\n val SHT_SYMTAB = 2\n val SHT_STRTAB = 3\n val SHT_REL = 9\n val SHT_RELA = 4\n\n val SHN_COMMON = 0xfff2.toShort\n }\n\n object Elf64_Sym {\n val NameOffset = 0\n val InfoOffset = 4\n val ShndxOffset = 6\n val ValueOffset = 8\n val SizeOffset = 16\n val TotalSize = 24\n\n val GlobalFunction = 0x12\n }\n\n object Elf64_Rel {\n val OffsetOffset = 0\n val InfoOffset = 8\n def r_sym(x: Long): Long = (x >> 32).toInt\n", "right_context": " val TotalSize = 16\n\n val R_BPF_64_64 = 1\n }\n}\n", "groundtruth": " def r_type(x: Long): Int = x.toInt\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "simpleinst", "path": "simpleinst/src/main/scala/Serializer.scala", "left_context": "package freechips.rocketchip.instrumenter\n\nimport chisel3._\n\nimport scala.collection.mutable.ArrayBuffer\n\nclass Serializer(isComputing: Bool, next: Bool) {\n def monotonic(x: Bool): Bool = {\n val res = WireInit(false.B)\n val prevRes = RegInit(false.B)\n prevRes := res && isComputing\n res := (x || prevRes) && isComputing\n res\n }\n private def noone(bs: Seq[Bool]): Bool = !bs.foldLeft(false.B)(_ || _)\n\n private val previousReqs = ArrayBuffer[Bool]()\n def nextReq(x: Bool): (Bool, Int) = {\n val enable = monotonic(x)\n val result = RegInit(false.B)\n val retired = RegInit(false.B)\n val doRetire = result && next\n val thisReq = enable && !retired && !doRetire\n val reqWon = thisReq && noone(previousReqs)\n when (isComputing) {\n when(reqWon) {\n result := true.B\n }\n when(doRetire) {\n result := false.B\n retired := true.B\n }\n } otherwise {\n result := false.B\n", "right_context": "}\n", "groundtruth": " retired := false.B\n }\n previousReqs += thisReq\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.6, "category_reason": ":= in when/switch context"} {"task_id": "simpleinst", "path": "simpleinst/src/main/scala/SimpleInstRoCC.scala", "left_context": "package freechips.rocketchip.instrumenter\n\nimport Chisel.BitPat\nimport chisel3._\nimport freechips.rocketchip.config.{Field, Parameters}\nimport freechips.rocketchip.instrumenter.BpfLoader.{BpfInsn, BpfProg}\nimport freechips.rocketchip.rocket._\nimport freechips.rocketchip.tile.{LazyRoCC, LazyRoCCModuleImp, OpcodeSet}\nimport freechips.rocketchip.util._\n\nimport scala.collection.mutable\nimport scala.collection.mutable.ArrayBuffer\n\nobject SimpleInstRoCC {\n", "right_context": " def fetchInstructions(bpfObject: String): BpfDescriptions = {\n val srcs = BpfLoader.fetchProgs(bpfObject)\n val instructions = ArrayBuffer[(Int, Seq[BpfInsn])]()\n val instrumentations = ArrayBuffer[OpcodeHandler]()\n srcs.foreach {\n case BpfProg(name, insns) if name.startsWith(\"funct\") =>\n instructions += name.substring(5).toInt -> insns\n case BpfProg(name, insns) if name.startsWith(\"inst\") =>\n val key = name.substring(4)\n val pat = Instructions.getClass.getMethod(key).invoke(Instructions).asInstanceOf[BitPat]\n val funct = instrumentations.length | (1 << 6)\n instructions += funct -> insns\n instrumentations += OpcodeHandler(pat, funct)\n }\n BpfDescriptions(instructions = instructions.toMap, instrumentations = instrumentations)\n }\n}\n\nclass SimpleInstRoCC(opcodes: OpcodeSet, val insns: Map[Int, Seq[BpfInsn]], val watchdogTicks: Int = 1000)(implicit p: Parameters) extends LazyRoCC(opcodes) {\n override lazy val module: LazyRoCCModuleImp = new SimpleInstRoCCImp(this)\n}\n\nclass SimpleInstRoCCImp(outer: SimpleInstRoCC)(implicit p: Parameters) extends LazyRoCCModuleImp(outer) {\n val cmd = io.cmd\n val funct = cmd.bits.inst.funct\n\n val isKnown = WireInit(false.B)\n val doneComputing = WireInit(true.B)\n val watchdogCountdown = RegInit(0.U(16.W))\n\n val isComputing = watchdogCountdown =/= 0.U\n watchdogCountdown := Mux(isComputing, watchdogCountdown - 1.U, 0.U)\n\n val isResponding = RegInit(false.B)\n\n cmd.ready := !isComputing && !isResponding\n io.resp.valid := isResponding\n io.busy := isComputing || isResponding\n\n when (cmd.fire()) {\n watchdogCountdown := outer.watchdogTicks.U\n isResponding := cmd.bits.inst.xd\n } otherwise {\n when (doneComputing) {\n watchdogCountdown := 0.U\n }\n }\n when(io.resp.fire()) {\n isResponding := false.B\n }\n\n io.interrupt := false.B\n io.resp.bits.rd := cmd.bits.inst.rd holdUnless cmd.fire()\n\n io.mem.req.valid := false.B\n io.mem.req.bits.phys := false.B\n\n val regs = mutable.Map[String, UInt]()\n\n class Constructor extends BpfCircuitConstructor {\n val serializer = new Serializer(isComputing, io.mem.req.fire())\n override def doMemLoad(addr: UInt, tpe: LdStType, valid: Bool): (UInt, Bool) = {\n val (doReq, thisTag) = serializer.nextReq(valid)\n when (doReq) {\n io.mem.req.bits.addr := addr\n require((1 << io.mem.req.bits.tag.getWidth) > thisTag)\n io.mem.req.bits.tag := thisTag.U\n io.mem.req.bits.cmd := M_XRD\n io.mem.req.bits.typ := (4 | tpe.lgsize).U\n io.mem.req.bits.data := 0.U\n io.mem.req.valid := true.B\n }\n\n val doResp = isComputing &&\n serializer.monotonic(doReq && io.mem.req.fire()) &&\n io.mem.resp.valid &&\n io.mem.resp.bits.tag === thisTag.U &&\n io.mem.resp.bits.cmd === M_XRD\n\n (io.mem.resp.bits.data holdUnless doResp, serializer.monotonic(doResp))\n }\n override def doMemStore(addr: UInt, tpe: LdStType, data: UInt, valid: Bool): Bool = {\n val (doReq, thisTag) = serializer.nextReq(valid)\n when (doReq) {\n io.mem.req.bits.addr := addr\n require((1 << io.mem.req.bits.tag.getWidth) > thisTag)\n io.mem.req.bits.tag := thisTag.U\n io.mem.req.bits.cmd := M_XWR\n io.mem.req.bits.typ := (4 | tpe.lgsize).U\n io.mem.req.bits.data := data\n io.mem.req.valid := true.B\n }\n serializer.monotonic(doReq && io.mem.req.fire())\n }\n override def resolveSymbol(sym: BpfLoader.Symbol): Resolved = sym match {\n case BpfLoader.Symbol(symName, _, size, ElfConstants.Elf64_Shdr.SHN_COMMON, false) if size <= 8 =>\n RegisterReference(regs.getOrElseUpdate(symName, RegInit(0.U(64.W))))\n }\n }\n\n outer.insns.foreach {\n case (opcode, insns) =>\n val constructor = new Constructor\n val active = (funct === opcode.U) holdUnless cmd.fire()\n val (result, ready) = constructor.processProgram(\n (isComputing || cmd.fire()) && active,\n insns,\n cmd.bits.rs1 holdUnless cmd.fire(),\n cmd.bits.rs2 holdUnless cmd.fire()\n )\n\n when (active) {\n // only when funct is known\n io.resp.bits.data := result\n doneComputing := ready\n isKnown := true.B\n }\n }\n}\n", "groundtruth": " final case class BpfDescriptions(instructions: Map[Int, Seq[BpfInsn]], instrumentations: Seq[OpcodeHandler])\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Type Definition", "confidence": 0.7, "category_reason": "Case class definition"} {"task_id": "simpleinst", "path": "simpleinst/src/test/scala/CircuitConstructorSpec.scala", "left_context": "package freechips.rocketchip.instrumenter\n\nimport java.nio.ByteBuffer\nimport java.nio.file.{Files, Paths}\n\nimport chisel3._\nimport chisel3.iotesters._\nimport chisel3.util.Cat\nimport freechips.rocketchip.instrumenter.BpfLoader.{BpfInsn, BpfProg}\nimport freechips.rocketchip.util._\nimport org.scalatest.{FlatSpec, Matchers}\n\nobject CircuitConstructorSpec {\n val MemLengthLg = 5\n val MemLength = 1 << MemLengthLg\n val MemInit = 0xaa\n class DUT(programs: Seq[Seq[BpfInsn]]) extends Module {\n override val io = IO(new Bundle {\n\n val arg1 = Input(UInt(64.W))\n val arg2 = Input(UInt(64.W))\n val arg3 = Input(UInt(64.W))\n\n val valid = Input(Vec(programs.length, Bool()))\n val ready = Output(Vec(programs.length, Bool()))\n val result = Output(Vec(programs.length, UInt(64.W)))\n\n val readAddr = Input(UInt(5.W))\n val readResult = Output(UInt(8.W))\n })\n\n val mem = SyncReadMem(MemLength, UInt(8.W))\n // Zero memory at the beginning of the simulation\n val memInitInd = RegInit(0.U((MemLengthLg + 1).W))\n memInitInd := Mux(memInitInd < MemLength.U, memInitInd + 1.U, memInitInd)\n when (memInitInd < MemLength.U) {\n mem.write(memInitInd, MemInit.U)\n }\n\n object Constructor extends BpfCircuitConstructor {\n override def doMemLoad(addr: UInt, tpe: LdStType, valid: Bool): (UInt, Bool) = {\n val shiftedBytes = (0 until (1 << tpe.lgsize)).map { i =>\n mem.read(addr + i.U, valid).asUInt()\n }\n when (RegNext(posedge(valid))) {\n printf(\"load %d: %x\\n\", addr, Cat(shiftedBytes.reverse))\n }\n (Cat(shiftedBytes.reverse) holdUnless RegNext(posedge(valid)), RegNext(RegNext(RegNext(valid))))\n }\n\n override def doMemStore(addr: UInt, tpe: LdStType, data: UInt, valid: Bool): Bool = {\n (0 until (1 << tpe.lgsize)).foreach { i =>\n when (posedge(valid)) {\n mem.write(addr + i.U, (data >> (i * 8))(7, 0))\n }\n }\n when (posedge(valid)) {\n printf(\"store %d <- %x\\n\", addr, data)\n }\n RegNext(RegNext(RegNext(valid)))\n }\n\n val regA = RegInit(0.U(64.W))\n val regB = RegInit(0.U(64.W))\n val regC = RegInit(0.U(64.W))\n val regD = RegInit(0.U(64.W))\n val regAddr = RegInit(0.U(64.W))\n override def resolveSymbol(sym: BpfLoader.Symbol): Resolved = sym match {\n case BpfLoader.Symbol(\"a\", _, _, _, _) =>\n RegisterReference(regA)\n case BpfLoader.Symbol(\"b\", _, _, _, _) =>\n RegisterReference(regB)\n case BpfLoader.Symbol(\"c\", _, _, _, _) =>\n RegisterReference(regC)\n case BpfLoader.Symbol(\"d\", _, _, _, _) =>\n RegisterReference(regC)\n case BpfLoader.Symbol(\"addr\", _, _, _, _) =>\n RegisterReference(regAddr)\n case BpfLoader.Symbol(_, value, _, shndx, _) if shndx != ElfConstants.Elf64_Shdr.SHN_COMMON =>\n Value(value.U)\n }\n }\n\n io.readResult := mem.read(io.readAddr)\n\n programs.zipWithIndex.foreach {\n case (prog, ind) =>\n val (result, resultValid) = Constructor.processProgram(\n io.valid(ind),\n prog,\n io.arg1, io.arg2, io.arg3\n )\n\n io.result(ind) := result\n io.ready(ind) := resultValid\n }\n\n }\n\n class CircuitTester(dut: DUT, resultsAndSteps: Seq[(BigInt, Int)], arg1: BigInt, arg2: BigInt, arg3: BigInt, memContents: Seq[Int]) extends PeekPokeTester(dut) {\n resultsAndSteps.indices.foreach { ind =>\n poke(dut.io.valid(ind), false)\n }\n step(100) // clear memory\n\n poke(dut.io.arg1, arg1)\n poke(dut.io.arg2, arg2)\n poke(dut.io.arg3, arg3)\n\n resultsAndSteps.zipWithIndex.foreach { case ((result, steps), i) =>\n\n step(100)\n\n expect(peek(dut.io.ready(i)) == 0, \"Circuit should not start on its own\")\n\n poke(dut.io.valid(i), true)\n\n if (steps > 0) {\n step(steps - 1)\n", "right_context": " } else {\n step(-steps)\n }\n\n step(1)\n\n if (steps >= 0) {\n expect(peek(dut.io.ready(i)) == 1, s\"Circuit should finish its calculations on ${steps}th step\")\n }\n\n val realResult = peek(dut.io.result(i))\n expect(realResult == result, s\"Result should be $result, got $realResult\")\n\n step(10)\n poke(dut.io.valid(i), false)\n }\n\n memContents.zipWithIndex.foreach {\n case (byte, ind) =>\n poke(dut.io.readAddr, ind)\n step(1)\n val realByte = peek(dut.io.readResult)\n expect((realByte & 0xFF) == (byte & 0xFF), s\"Byte #$ind should be $byte, got $realByte\")\n }\n }\n}\n\nclass CircuitConstructorSpec extends FlatSpec with Matchers {\n import CircuitConstructorSpec._\n\n behavior of \"CircuitConstructor\"\n\n def testWith(progs: BpfInsn*)(args: (BigInt, BigInt, BigInt), result: BigInt, steps: Int, sparseMemContents: (Int, Int)*): Unit = {\n val mem = sparseMemContents.toMap\n val memContents = (0 until MemLength).map(mem.getOrElse(_, MemInit))\n chisel3.iotesters.Driver(\n () => new DUT(Seq(progs, progs, progs)), backendType=\"firrtl\")(\n new CircuitTester(_, Seq.tabulate(3)(_ => result -> steps), args._1, args._2, args._3, memContents)\n ) shouldBe true\n }\n\n def compileAndTest(textsAndResults: Seq[(String, BigInt)], args: (BigInt, BigInt), sparseMemContents: (Int, Int)*): Unit = {\n val mem = sparseMemContents.toMap\n val memContents = (0 until MemLength).map(mem.getOrElse(_, MemInit))\n val tempFile = Files.createTempFile(\"bpf\", \".c\")\n val fullText =\n s\"\"\"#include \n |volatile uint64_t a, b;\n |uint64_t c, d;\n |uint64_t *addr;\n |\"\"\".stripMargin +\n textsAndResults.zipWithIndex.map { case ((text, _), ind) =>\n s\"\"\"\n |int f$ind(uint64_t x, uint64_t y) {\n | $text\n }\n \"\"\".stripMargin\n }.mkString\n val results = textsAndResults.map(_._2)\n Files.write(tempFile, fullText.getBytes)\n val fname = tempFile.toAbsolutePath.toString\n Runtime.getRuntime\n .exec(Array(\"/bin/sh\", \"-c\", s\"clang -O3 -emit-llvm -c $fname -o - | llc -march=bpf -filetype=obj -o $fname.o\"))\n .waitFor()\n val data = Files.readAllBytes(Paths.get(fname + \".o\"))\n val progs = BpfLoader.fetchProgs(ByteBuffer.wrap(data))\n chisel3.iotesters.Driver(\n () => new DUT(progs.map(_.insns)), backendType=\"firrtl\")(\n new CircuitTester(_, results.map(_ -> -100), args._1, args._2, 0, memContents)\n ) shouldBe true\n Files.delete(tempFile)\n Files.delete(Paths.get(tempFile.toString + \".o\"))\n }\n\n it should \"return immediate values\" in {\n testWith(\n BpfInsn(0x18, 0, 0, 0, Left(123))\n )((1, 2, 3), 123, 0)\n }\n\n it should \"handle arithmetic on small numbers\" in {\n testWith(\n BpfInsn(0x0f, 1, 2, 0, Left(0)), // r1 += r2\n BpfInsn(0x27, 1, 0, 0, Left(3)), // r1 *= 3\n BpfInsn(0x0f, 1, 3, 0, Left(0)), // r1 += r3\n BpfInsn(0x0f, 0, 1, 0, Left(0)), // r0 += r1\n )((1, 2, 3), 12, 0)\n }\n\n it should \"handle 64-bit ALU\" in {\n testWith(\n BpfInsn(0x0f, 1, 2, 0, Left(0)), // r1 += r2\n BpfInsn(0x27, 1, 0, 0, Left(3)), // r1 *= 3\n BpfInsn(0x2f, 1, 3, 0, Left(0)), // r1 *= r3\n BpfInsn(0x0f, 0, 1, 0, Left(0)), // r0 += r1\n )((1, 2, 0x80000000l), 0x480000000l, 0)\n }\n\n it should \"handle 32-bit ALU\" in {\n testWith(\n BpfInsn(0x0c, 1, 2, 0, Left(0)), // r1 += r2\n BpfInsn(0x24, 1, 0, 0, Left(3)), // r1 *= 3\n BpfInsn(0x2c, 1, 3, 0, Left(0)), // r1 *= r3\n BpfInsn(0x0c, 0, 1, 0, Left(0)), // r0 += r1\n )((1, 2, 0x80000000l), 0x80000000l, 0) // 72 == 0x48\n }\n\n it should \"handle exit at the end\" in {\n testWith(\n BpfInsn(0x0f, 1, 2, 0, Left(0)), // r1 += r2\n BpfInsn(0x0f, 0, 1, 0, Left(0)), // r0 += r1\n BpfInsn(0x95, 0, 0, 0, Left(0)), // exit\n )((1, 2, 3), 3, 0)\n }\n\n it should \"write to memory\" in {\n testWith(\n BpfInsn(0x72, 1, 0, 0, Left(0xabc)), // *(uint8_t *)(r1 + 0) = 0xbc\n BpfInsn(0xb4, 1, 0, 0, Left(10)), // r1 = 10\n BpfInsn(0x73, 1, 3, 12, Left(0xabc)), // *(uint8_t *)(r1 + 12) = r3\n )((1, 2, 3), 0, 3,\n 1 -> 0xbc,\n 22 -> 3\n )\n }\n\n it should \"load then store\" in {\n testWith(\n BpfInsn(0x71, 1, 1, 1, Left(0)), // r1 = *(uint8_t *)(r1 + 1)\n BpfInsn(0x07, 1, 0, 0, Left(3)), // r1 += 3\n BpfInsn(0x73, 2, 1, 10, Left(0)), // *(uint8_t *)(r2 + 10) = r1\n )((1, 2, 3), 0, 6,\n 12 -> 0xad\n )\n }\n\n it should \"handle byteswap2\" in {\n compileAndTest(Seq(\"return ((x & 0xFF) << 8) | ((x & 0xFF00) >> 8);\" -> 0xefcd),\n (0xabcdef, 0x00))\n }\n\n it should \"handle bytemerge2\" in {\n compileAndTest(Seq(\"return (x & 0xFF) | (y & 0xFF00);\" -> 0x34ef),\n (0xabcdef, 0x123456))\n }\n\n it should \"handle popcount\" in {\n compileAndTest(Seq(\n \"return __builtin_popcount(x);\" -> 6,\n \"return __builtin_popcountl(x);\" -> 8),\n (0x10000020AA000011l, 0))\n }\n\n it should \"handle explicit register allocation\" in {\n compileAndTest(Seq(\"a = x; b = a * 2; a = b + 2; return a + b;\" -> 6),\n (1, 0))\n }\n\n it should \"store registers between invocations\" in {\n compileAndTest(Seq.tabulate(3)(_ => \"*(uint8_t*)(a + 1) += ++b; a += x; return 0;\" -> 0),\n (3, 0), 1 -> 0xab, 4 -> 0xac, 7 -> 0xad\n )\n }\n\n it should \"store registers between invocations (not volatile)\" in {\n compileAndTest(Seq.tabulate(3)(_ => \"*(uint8_t*)(c + 1) += ++a; c += x; return 0;\" -> 0),\n (3, 0), 1 -> 0xab, 4 -> 0xac, 7 -> 0xad\n )\n }\n\n it should \"handle storing the pointer between funct-s\" in {\n compileAndTest(Seq(\n \"addr = (void *)x; return ((uint32_t)addr) << 1;\" -> 16,\n /* cannot perform not naturally fully ordered operations on a particular byte of memory, so \"addr + 1\" */\n \"*addr = (*addr) + 1; return (*(addr + 1)) & 0xFF;\" -> 0xaa,\n \"addr += 2; return addr;\" -> 24\n ), (8, 0), 8 -> 0xab)\n }\n}\n", "groundtruth": " expect(peek(dut.io.ready(i)) == 0, s\"Circuit should not finish its calculations before ${steps}th step\")\n", "crossfile_context": "", "category": "Monitoring and Checking Logic", "subcategory": "Error Reporting and Logging", "confidence": 0.85, "category_reason": "Chisel expect (golden check)"} {"task_id": "simpleinst", "path": "simpleinst/src/test/scala/SerializerSpec.scala", "left_context": "package freechips.rocketchip.instrumenter\n\nimport chisel3._\nimport chisel3.iotesters.PeekPokeTester\nimport org.scalatest.{FlatSpec, Matchers}\n\nobject SerializerSpec {\n class DUT extends Module {\n override val io = IO(new Bundle {\n val isComputing = Input(Bool())\n val next = Input(Bool())\n\n val req1 = Input(Bool())\n val req2 = Input(Bool())\n val req3 = Input(Bool())\n val req4 = Input(Bool())\n\n val resp1 = Output(Bool())\n val resp2 = Output(Bool())\n val resp3 = Output(Bool())\n val resp4 = Output(Bool())\n })\n val serializer = new Serializer(io.isComputing, io.next)\n io.resp1 := serializer.nextReq(io.req1)._1\n io.resp2 := serializer.nextReq(io.req2)._1\n io.resp3 := serializer.nextReq(io.req3)._1\n io.resp4 := serializer.nextReq(io.req4)._1\n }\n\n final case class Session(start: Int, reqs: T, resps: T, nexts: T, stop: Int)\n final case class T(a: Int, b: Int, c: Int, d: Int) {\n def contains(t: Int): Boolean = Seq(a, b, c, d).contains(t)\n }\n\n class Tester(dut: DUT, sessions: Seq[Session]) extends PeekPokeTester(dut) {\n var sessionInd = 0\n def curSession = sessions(sessionInd)\n for (t <- 0 until sessions.last.stop) {\n if (t >= curSession.stop) {\n sessionInd += 1\n }\n poke(dut.io.isComputing, t >= curSession.start)\n\n poke(dut.io.req1, t >= curSession.reqs.a)\n poke(dut.io.req2, t >= curSession.reqs.b)\n poke(dut.io.req3, t >= curSession.reqs.c)\n poke(dut.io.req4, t >= curSession.reqs.d)\n\n poke(dut.io.next, curSession.nexts.contains(t))\n\n step(1)\n\n", "right_context": " test(dut.io.resp4, curSession.resps.d, curSession.nexts.d, \"Response 4\")\n\n }\n }\n}\n\nclass SerializerSpec extends FlatSpec with Matchers {\n import SerializerSpec._\n\n behavior of \"Serializer\"\n\n def testWith(sessions: Session*): Unit = {\n chisel3.iotesters.Driver(() => new DUT, backendType=\"firrtl\")(new Tester(_, sessions)) shouldBe true\n }\n\n it should \"pass through sequential requests\" in {\n testWith(Session(0, T(1, 2, 3, 4), T(2, 3, 4, 5), T(2, 3, 4, 5), 10))\n }\n it should \"handle all-simultaneous request\" in {\n testWith(Session(0, T(1, 1, 1, 1), T(2, 3, 4, 5), T(2, 3, 4, 5), 10))\n }\n it should \"handle simultaneous request\" in {\n testWith(Session(0, T(1, 1, 7, 7), T(2, 3, 8, 9), T(2, 3, 8, 9), 10))\n }\n it should \"handle queued request\" in {\n testWith(Session(0, T(1, 1, 2, 3), T(2, 3, 4, 5), T(2, 3, 4, 5), 10))\n }\n it should \"handle not-immediate processing\" in {\n testWith(Session(0, T(1, 1, 1, 1), T(2, 4, 5, 8), T(3, 4, 7, 9), 10))\n }\n it should \"handle multiple sessions\" in {\n testWith(\n Session(0, T(1, 1, 1, 1), T(2, 4, 5, 118), T(3, 4, 117, 119), 5), // the last resp is not asserted this session\n Session(6, T(7, 7, 15, 15), T(8, 9, 16, 17), T(8, 9, 16, 17), 20)\n )\n }\n}\n", "groundtruth": " def test(x: Bool, t1: Int, t2: Int, label: String): Unit = {\n val expected = (t + 1) >= t1 && (t + 1) <= t2\n expect((peek(x) != 0) == expected, s\"$label should be $expected\")\n }\n", "crossfile_context": "", "category": "Monitoring and Checking Logic", "subcategory": "Error Reporting and Logging", "confidence": 0.85, "category_reason": "Chisel expect (golden check)"} {"task_id": "riscv32-cpu-chisel", "path": "riscv32-cpu-chisel/src/main/scala/Consts.scala", "left_context": "package cpu\n\nimport chisel3._\nimport chisel3.util._\n\nobject Consts {\n val WORD_LEN = 32\n val START_ADDR = 0.U(WORD_LEN.W)\n val BUBBLE = 0x00000013.U(WORD_LEN.W) // [ADDI x0,x0,0] = NOP = BUBBLE (2.4)\n val UNIMP = \"x_c0001073\".U(WORD_LEN.W) // [CSRRW x0, cycle, x0] p.159\n val ADDR_LEN = 5 // rs1,rs2,wb\n val CSR_ADDR_LEN = 12\n val VLEN = 128\n val LMUL_LEN = 2\n val SEW_LEN = 11\n val VL_ADDR = 0xC20\n val VTYPE_ADDR = 0xC21\n\n val EXE_FUN_LEN = 5\n val ALU_NONE = 0.U(EXE_FUN_LEN.W)\n val ALU_ADD = 1.U(EXE_FUN_LEN.W)\n val ALU_SUB = 2.U(EXE_FUN_LEN.W)\n val ALU_AND = 3.U(EXE_FUN_LEN.W)\n val ALU_OR = 4.U(EXE_FUN_LEN.W)\n val ALU_XOR = 5.U(EXE_FUN_LEN.W)\n val ALU_SLL = 6.U(EXE_FUN_LEN.W)\n val ALU_SRL = 7.U(EXE_FUN_LEN.W)\n val ALU_SRA = 8.U(EXE_FUN_LEN.W)\n val ALU_SLT = 9.U(EXE_FUN_LEN.W)\n val ALU_SLTU = 10.U(EXE_FUN_LEN.W)\n val BR_BEQ = 11.U(EXE_FUN_LEN.W)\n val BR_BNE = 12.U(EXE_FUN_LEN.W)\n val BR_BLT = 13.U(EXE_FUN_LEN.W)\n val BR_BGE = 14.U(EXE_FUN_LEN.W)\n val BR_BLTU = 15.U(EXE_FUN_LEN.W)\n val BR_BGEU = 16.U(EXE_FUN_LEN.W)\n val ALU_JALR = 17.U(EXE_FUN_LEN.W)\n val ALU_RS1 = 18.U(EXE_FUN_LEN.W) // Copy RS1\n val ALU_VADDVV = 19.U(EXE_FUN_LEN.W)\n val VSET = 20.U(EXE_FUN_LEN.W)\n val ALU_PCNT = 21.U(EXE_FUN_LEN.W)\n\n val OP1_LEN = 2\n", "right_context": " val OP2_LEN = 3\n val OP2_NONE = 0.U(OP2_LEN.W)\n val OP2_RS2 = 1.U(OP2_LEN.W)\n val OP2_IMI = 2.U(OP2_LEN.W)\n val OP2_IMS = 3.U(OP2_LEN.W)\n val OP2_IMJ = 4.U(OP2_LEN.W)\n val OP2_IMU = 5.U(OP2_LEN.W)\n\n val MEN_LEN = 2\n val MEN_NONE = 0.U(MEN_LEN.W)\n val MEN_SCALAR = 1.U(MEN_LEN.W) // Scalar\n val MEN_VECTOR = 2.U(MEN_LEN.W) // Vector\n\n val REN_LEN = 2\n val REN_NONE = 0.U(REN_LEN.W)\n val REN_SCALAR = 1.U(REN_LEN.W) // Scalar\n val REN_VECTOR = 2.U(REN_LEN.W) // Vector\n\n val WB_SEL_LEN = 3\n val WB_NONE = 0.U(WB_SEL_LEN.W)\n val WB_ALU = 0.U(WB_SEL_LEN.W)\n val WB_MEM = 1.U(WB_SEL_LEN.W)\n val WB_PC = 2.U(WB_SEL_LEN.W)\n val WB_CSR = 3.U(WB_SEL_LEN.W)\n val WB_MEM_V = 4.U(WB_SEL_LEN.W)\n val WB_ALU_V = 5.U(WB_SEL_LEN.W)\n val WB_VL = 6.U(WB_SEL_LEN.W)\n\n val MW_LEN = 3\n val MW_X = 0.U(MW_LEN.W)\n val MW_W = 1.U(MW_LEN.W)\n val MW_H = 2.U(MW_LEN.W)\n val MW_B = 3.U(MW_LEN.W)\n val MW_HU = 4.U(MW_LEN.W)\n val MW_BU = 5.U(MW_LEN.W)\n\n val CSR_LEN = 3\n val CSR_NONE = 0.U(CSR_LEN.W)\n val CSR_W = 1.U(CSR_LEN.W) // Write\n val CSR_S = 2.U(CSR_LEN.W) // Set bits\n val CSR_C = 3.U(CSR_LEN.W) // Clear bits\n val CSR_E = 4.U(CSR_LEN.W) // Exception (ECALL)\n val CSR_V = 5.U(CSR_LEN.W)\n}\n", "groundtruth": " val OP1_RS1 = 0.U(OP1_LEN.W)\n val OP1_PC = 1.U(OP1_LEN.W)\n val OP1_NONE = 2.U(OP1_LEN.W)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.7, "category_reason": "Literal value binding"} {"task_id": "riscv32-cpu-chisel", "path": "riscv32-cpu-chisel/src/main/scala/Instructions.scala", "left_context": "package cpu\n\nimport chisel3._\nimport chisel3.util._\n\nobject Instructions {\n // Load/Store\n val LW = BitPat(\"b?????????????????010?????0000011\")\n val SW = BitPat(\"b?????????????????010?????0100011\")\n\n // Add\n val ADD = BitPat(\"b0000000??????????000?????0110011\")\n val ADDI = BitPat(\"b?????????????????000?????0010011\")\n\n // Sub\n val SUB = BitPat(\"b0100000??????????000?????0110011\")\n\n // Logical operations\n val AND = BitPat(\"b0000000??????????111?????0110011\")\n val OR = BitPat(\"b0000000??????????110?????0110011\")\n val XOR = BitPat(\"b0000000??????????100?????0110011\")\n val ANDI = BitPat(\"b?????????????????111?????0010011\")\n val ORI = BitPat(\"b?????????????????110?????0010011\")\n val XORI = BitPat(\"b?????????????????100?????0010011\")\n\n // Shift\n val SLL = BitPat(\"b0000000??????????001?????0110011\")\n val SRL = BitPat(\"b0000000??????????101?????0110011\")\n val SRA = BitPat(\"b0100000??????????101?????0110011\")\n val SLLI = BitPat(\"b0000000??????????001?????0010011\")\n val SRLI = BitPat(\"b0000000??????????101?????0010011\")\n val SRAI = BitPat(\"b0100000??????????101?????0010011\")\n\n", "right_context": " val BLT = BitPat(\"b?????????????????100?????1100011\")\n val BGE = BitPat(\"b?????????????????101?????1100011\")\n val BLTU = BitPat(\"b?????????????????110?????1100011\")\n val BGEU = BitPat(\"b?????????????????111?????1100011\")\n\n // Jump\n val JAL = BitPat(\"b?????????????????????????1101111\")\n val JALR = BitPat(\"b?????????????????000?????1100111\")\n\n // Load immediate\n val LUI = BitPat(\"b?????????????????????????0110111\")\n val AUIPC = BitPat(\"b?????????????????????????0010111\")\n\n // CSR\n val CSRRW = BitPat(\"b?????????????????001?????1110011\")\n val CSRRWI = BitPat(\"b?????????????????101?????1110011\")\n val CSRRS = BitPat(\"b?????????????????010?????1110011\")\n val CSRRSI = BitPat(\"b?????????????????110?????1110011\")\n val CSRRC = BitPat(\"b?????????????????011?????1110011\")\n val CSRRCI = BitPat(\"b?????????????????111?????1110011\")\n\n // Exception\n val ECALL = BitPat(\"b00000000000000000000000001110011\")\n\n // Vector\n val VSETVLI = BitPat(\"b?????????????????111?????1010111\")\n val VLE = BitPat(\"b000000100000?????????????0000111\")\n val VSE = BitPat(\"b000000100000?????????????0100111\")\n val VADDVV = BitPat(\"b0000001??????????000?????1010111\")\n\n // Custom\n val PCNT = BitPat(\"b000000000000?????110?????0001011\")\n}\n", "groundtruth": " // Compare\n val SLT = BitPat(\"b0000000??????????010?????0110011\")\n val SLTU = BitPat(\"b0000000??????????011?????0110011\")\n val SLTI = BitPat(\"b?????????????????010?????0010011\")\n val SLTIU = BitPat(\"b?????????????????011?????0010011\")\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.6, "category_reason": "val binding"} {"task_id": "riscv32-cpu-chisel", "path": "riscv32-cpu-chisel/src/main/scala/Main.scala", "left_context": "package cpu\n\nimport java.io.File\nimport chisel3._\nimport chisel3.stage.ChiselStage\n\nobject MyCpuDriver extends App {\n def getMemoryHexFilePath(args: Array[String]): (String, Array[String]) = {\n for (i <- 1 until args.length) {\n if (args(i-1) == \"--memoryHexFile\") {\n val a = args(i)\n if (!a.isEmpty) {\n if (!new File(a).isFile) {\n throw new IllegalArgumentException(a ++ \" is not a file at --memoryHexFile argument\")\n }\n", "right_context": " (new ChiselStage).emitVerilog(new Top(p), a)\n}\n", "groundtruth": " return (a, args.take(i-1) ++ args.drop(i + 1))\n }\n }\n }\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "riscv32-cpu-chisel", "path": "riscv32-cpu-chisel/src/main/scala/Memory.scala", "left_context": "package cpu\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.util.experimental.loadMemoryFromFile\nimport Consts._\n\n// Group input/output between CPU core and memory (see p.77)\n// 'I' stands for 'Instruction'.\nclass ImemPortIo extends Bundle {\n // input port for memory address\n val addr = Input(UInt(WORD_LEN.W))\n // output port for fetching instruction\n val inst = Output(UInt(WORD_LEN.W))\n}\n\nclass DmemPortIo extends Bundle {\n val addr = Input(UInt(WORD_LEN.W))\n val rdata = Output(UInt(WORD_LEN.W)) // r stands for read\n val wen = Input(Bool()) // Indicate when data should be written\n val wdata = Input(UInt(WORD_LEN.W)) // w stands for write\n}\n\n// Group input/output between CPU core and memory (p.92)\n// 'D' stands for 'data'.\nclass Memory(hexMemoryPath: String) extends Module {\n val io = IO(new Bundle {\n val imem = new ImemPortIo()\n val dmem = new DmemPortIo()\n })\n\n // As underlying implementation, memory consists of 8bit * 0x4000 registers (16KB). The register\n // size is 8bits because PC is counted up by 4bytes.\n val mem = Mem(0x4000, UInt(8.W))\n\n loadMemoryFromFile(mem, hexMemoryPath)\n\n io.imem.inst := Cat(\n mem(io.imem.addr + 3.U(WORD_LEN.W)),\n mem(io.imem.addr + 2.U(WORD_LEN.W)),\n mem(io.imem.addr + 1.U(WORD_LEN.W)),\n mem(io.imem.addr)\n )\n\n", "right_context": " mem(io.dmem.addr + 1.U(WORD_LEN.W)),\n mem(io.dmem.addr)\n )\n\n when(io.dmem.wen) {\n mem(io.dmem.addr + 3.U(WORD_LEN.W)) := io.dmem.wdata(31, 24)\n mem(io.dmem.addr + 2.U(WORD_LEN.W)) := io.dmem.wdata(23, 16)\n mem(io.dmem.addr + 1.U(WORD_LEN.W)) := io.dmem.wdata(15, 8)\n mem(io.dmem.addr) := io.dmem.wdata(7, 0)\n }\n}\n", "groundtruth": " io.dmem.rdata := Cat(\n mem(io.dmem.addr + 3.U(WORD_LEN.W)),\n", "crossfile_context": "", "category": "Computation Block", "subcategory": "Type Casting and Conversion", "confidence": 0.75, "category_reason": "Cat/Fill operation"} {"task_id": "riscv32-cpu-chisel", "path": "riscv32-cpu-chisel/src/main/scala/Top.scala", "left_context": "package cpu\n\nimport chisel3._\nimport chisel3.util._\nimport Consts._\n\nclass Top(hexMemoryPath: String) extends Module {\n val io = IO(new Bundle {\n val exit = Output(Bool())\n val gp = Output(UInt(WORD_LEN.W))\n val pc = Output(UInt(WORD_LEN.W))\n })\n\n val core = Module(new Core())\n val memory = Module(new Memory(hexMemoryPath))\n\n // Connect ports between core and memory\n core.io.imem <> memory.io.imem\n core.io.dmem <> memory.io.dmem\n\n // Connect signals inside core\n io.exit := core.io.exit\n io.gp := core.io.gp\n", "right_context": "}\n", "groundtruth": " io.pc := core.io.pc\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.5, "category_reason": ":= to io port"} {"task_id": "riscv32-cpu-chisel", "path": "riscv32-cpu-chisel/src/test/scala/CTests.scala", "left_context": "package cpu\n\nimport java.io.File\nimport chisel3._\nimport org.scalatest._\nimport chiseltest._\nimport Consts._\n\nclass CTests extends FlatSpec with ChiselScalatestTester {\n behavior of \"mycpu\"\n\n for (f <- new File(\"./c\").listFiles.filter(f => f.isFile && f.getName.endsWith(\".hex\"))) {\n val p = f.getPath\n it should p in {\n test(new Top(p)) { c =>\n // c is an instance of Top\n", "right_context": " }\n}\n", "groundtruth": " while (!c.io.exit.peek().litToBoolean) {\n c.clock.step(1)\n }\n", "crossfile_context": "", "category": "Testbench Stimulus and Environment", "subcategory": "Stimulus Generation", "confidence": 0.85, "category_reason": "Chisel test harness (poke/peek/step)"} {"task_id": "riscv32-cpu-chisel", "path": "riscv32-cpu-chisel/src/test/scala/RiscvTests.scala", "left_context": "package cpu\n\nimport java.io.File\nimport chisel3._\nimport org.scalatest._\nimport chiseltest._\n\nclass RiscvTests extends FlatSpec with ChiselScalatestTester {\n behavior of \"mycpu\"\n\n", "right_context": " val p = f.getPath\n it should p in {\n test(new Top(p)) { c =>\n // riscv-tests test case finishes when program counter is at 0x44\n while (c.io.pc.peek().litValue != 0x44) {\n c.clock.step(1)\n }\n // riscv-tests sets 1 to gp when the test passed otherwise gp represents which test case failed\n c.io.gp.expect(1.U)\n }\n }\n }\n}\n", "groundtruth": " for (f <- new File(\"./riscv-tests-results\").listFiles.filter(f => f.isFile && f.getName.endsWith(\".hex\"))) {\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Loop-based Control", "confidence": 0.8, "category_reason": "for loop"} {"task_id": "riscv32-cpu-chisel", "path": "riscv32-cpu-chisel/src/test/scala/RustTests.scala", "left_context": "package cpu\n\nimport java.io.File\nimport chisel3._\nimport org.scalatest._\nimport chiseltest._\nimport Consts._\n\nclass RustTests extends FlatSpec with ChiselScalatestTester {\n behavior of \"mycpu\"\n\n for (f <- new File(\"./rust\").listFiles.filter(f => f.isFile && f.getName.endsWith(\".hex\"))) {\n val p = f.getPath\n it should p in {\n test(new Top(p)) { c =>\n // c is an instance of Top\n while (!c.io.exit.peek().litToBoolean) {\n", "right_context": "", "groundtruth": " c.clock.step(1)\n }\n }\n }\n }\n", "crossfile_context": "", "category": "Testbench Stimulus and Environment", "subcategory": "Stimulus Generation", "confidence": 0.85, "category_reason": "Chisel test harness (poke/peek/step)"} {"task_id": "perfect-chisel", "path": "perfect-chisel/src/main/scala/perfect/random/Lfsr.scala", "left_context": "// Copyright 2017 IBM\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\npackage perfect.random\n\nimport chisel3._\nimport chisel3.util._\n\nobject LfsrTaps {\n // This was sourced from:\n // \\@TechReport{,\n // author = {R. W. Ward and T.C.A. Molteno},\n // title = {Table of Linear Feedback Shift Registers},\n // institution = {University of Otago},\n // year = {2012},\n // number = {2012-1},\n // issn = {1172-496X}\n // }\n def apply(size: Int): Seq[Int] = { // scalastyle:off magic.number\n size match {\n case 2 => Seq(1)\n case 3 => Seq(2)\n case 4 => Seq(3)\n case 5 => Seq(3)\n case 6 => Seq(5)\n case 7 => Seq(6)\n case 8 => Seq(6, 5, 4)\n case 9 => Seq(5)\n case 10 => Seq(7)\n case 11 => Seq(9)\n case 12 => Seq(11, 8, 6)\n case 13 => Seq(12, 10, 9)\n case 14 => Seq(13, 11, 9)\n case 15 => Seq(14)\n case 16 => Seq(14, 13, 11)\n case 17 => Seq(14)\n case 18 => Seq(11)\n case 19 => Seq(18, 17, 14)\n case 20 => Seq(17)\n case 21 => Seq(19)\n case 22 => Seq(21)\n case 23 => Seq(18)\n case 24 => Seq(23, 21, 20)\n case 25 => Seq(25, 24, 20)\n case 27 => Seq(26, 25, 22)\n case 28 => Seq(25)\n case 29 => Seq(27)\n case 30 => Seq(29, 26, 24)\n case 31 => Seq(28)\n case 32 => Seq(30, 26, 25)\n case 64 => Seq(63, 61, 60)\n case 128 => Seq(127, 126, 121)\n case 256 => Seq(254, 251, 246)\n case 512 => Seq(510, 507, 504)\n case 1024 => Seq(1015, 1002, 1001)\n case 2048 => Seq(2035, 2034, 2029)\n case 4096 => Seq(4095, 4081, 4069) // scalastyle:on magic.number\n case _ => throw new Exception(\"No LFSR taps stored for requested size\")\n }\n }\n}\n\nclass Lfsr(n: Int, seed: Int = 1) extends Module {\n require(seed > 0, \"Seed cannot be zero\")\n\n val io = IO(new PrngIo(n))\n\n val shiftReg = RegInit(VecInit((seed.U(n.W)).asBools))\n shiftReg.zipWithIndex.map {case (x, i) => { x := shiftReg((i + 1) % n) } }\n LfsrTaps(n) map (x => { shiftReg(x - 1) := shiftReg(0) ^ shiftReg(x) })\n\n when (io.seed.fire()) {\n shiftReg zip io.seed.bits.asBools map { case(l, r) => l := r } }\n io.y := shiftReg.asUInt\n}\n\nclass Lfsr8 extends Lfsr(8)\n", "right_context": "class Lfsr64 extends Lfsr(64)\n", "groundtruth": "class Lfsr16 extends Lfsr(16)\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.55, "category_reason": "Code near when block"} {"task_id": "perfect-chisel", "path": "perfect-chisel/src/main/scala/perfect/random/Prng.scala", "left_context": "// Copyright 2017 IBM\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\npackage perfect.random\n\nimport chisel3._\nimport chisel3.util._\n\n", "right_context": "", "groundtruth": "class PrngIo(n: Int) extends Bundle {\n val seed = Input(Valid(UInt(n.W)))\n val y = Output(UInt(n.W))\n}\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.9, "category_reason": "Bundle class definition"} {"task_id": "perfect-chisel", "path": "perfect-chisel/src/main/scala/perfect/util/Counter.scala", "left_context": "// Copyright 2017 IBM\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\npackage perfect\n\nimport chisel3._\nimport chisel3.util._\n\nclass CounterWithReset(n: Int) extends Counter(n: Int) {\n override def reset(): Unit = { value := 0.U }\n}\n\nclass CounterModule(n: Int) extends Module {\n val io = IO(new Bundle {\n val inc = Input(Bool())\n val extReset = Input(Bool())\n val max = Input(UInt(log2Ceil(n + 1).W))\n val wrap = Output(Bool())\n val value = Output(UInt(log2Ceil(n).W))\n })\n\n val value = RegInit(0.U(n.W))\n io.value := value\n when (io.inc) { value := value + 1.U }\n io.wrap := value === (io.max - 1.U)\n", "right_context": "}\n\nobject CounterWithReset {\n def apply(n: Int): CounterWithReset = new CounterWithReset(n)\n\n def apply(cond: Bool, reset: Bool, n: Int): (UInt, Bool) = {\n val c = new CounterWithReset(n)\n var wrap: Bool = null\n when (cond) { wrap = c.inc() }\n when (reset) { c.reset() }\n (c.value, cond && wrap)\n }\n\n def apply(cond: Bool, reset: Bool, max: UInt): (UInt, Bool) = {\n val c = Module(new CounterModule(max.getWidth))\n c.io.inc := cond\n c.io.extReset := reset\n c.io.max := max\n val Seq(value, wrap) = Seq(UInt(), Bool())\n (c.io.value, cond && c.io.wrap)\n }\n}\n", "groundtruth": " when (io.extReset || io.wrap) { value := 0.U }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "perfect-chisel", "path": "perfect-chisel/src/main/scala/perfect/util/Fletcher.scala", "left_context": "// Copyright 2017 IBM\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\npackage perfect.util\n\nimport chisel3._\nimport chisel3.util._\n\ntrait FletcherH {\n val k_reset = 0\n val k_compute = 1\n}\n\nclass FletcherCmd(val n: Int) extends Bundle {\n val cmd = UInt(2.W)\n val word = UInt((n/2).W)\n}\n\nclass FletcherIO(val n: Int) extends Bundle {\n val data = Flipped(Valid(new FletcherCmd(n)))\n val checksum = Output(UInt((n).W))\n}\n\nclass Fletcher(n: Int) extends Module with FletcherH with UniformPrintfs {\n val io = IO(new FletcherIO(n))\n\n val a = RegInit(UInt((n/2).W), 0.U)\n", "right_context": " when (do_reset) {\n a := 0.U\n b := 0.U\n printfInfo(\"Fletcher: Reset\\n\")\n }\n\n when (do_compute) {\n val new_a = a + io.data.bits.word\n a := new_a\n b := b + new_a\n printfInfo(\"Fletcher: Compute a => 0x%x, b => 0x%x\\n\", new_a, b + new_a)\n }\n}\n", "groundtruth": " val b = RegInit(UInt((n/2).W), 0.U)\n\n val do_reset = io.data.fire() && io.data.bits.cmd === k_reset.U\n val do_compute = io.data.fire() && io.data.bits.cmd === k_compute.U\n", "crossfile_context": "", "category": "Storage Block", "subcategory": "Register-based Storage", "confidence": 0.85, "category_reason": "RegInit register"} {"task_id": "perfect-chisel", "path": "perfect-chisel/src/main/scala/perfect/util/NoDedup.scala", "left_context": "// Copyright 2017 IBM\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\npackage perfect\npackage util\n\nimport chisel3.RawModule\nimport chisel3.experimental.doNotDedup\n\ntrait NoDedup {\n self: RawModule =>\n\n", "right_context": "}\n", "groundtruth": " doNotDedup(self)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "perfect-chisel", "path": "perfect-chisel/src/main/scala/perfect/util/PWM.scala", "left_context": "// Copyright 2017 IBM\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\npackage perfect.util\n\nimport chisel3._\n\nclass PwmIo(n: Int) extends Bundle {\n val enable = Input(Bool())\n val pulseWidth = Input(UInt(n.W))\n val period = Input(UInt(n.W))\n val out = Output(Bool())\n}\n\nclass Pwm(n: Int) extends Module {\n val io = IO(new PwmIo(n))\n\n val count = Reg(UInt(n.W))\n\n io.out := io.enable && count <= io.pulseWidth\n", "right_context": " when (count >= io.period || ~io.enable) { count := 0.U }\n}\n", "groundtruth": " when (io.enable) { count := count + 1.U }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "perfect-chisel", "path": "perfect-chisel/src/main/scala/perfect/util/Piso.scala", "left_context": "// Copyright 2017 IBM\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\npackage perfect.util\n\nimport chisel3._\nimport chisel3.util._\n\n", "right_context": " val s = Valid(Bool())\n}\n\nclass Piso(n: Int) extends Module with UniformPrintfs {\n val io = IO(new PisoIO(n))\n\n val sr = Reg(UInt(n.W))\n val count = Reg(UInt(log2Ceil(n).W))\n\n val sentCount = Reg(UInt(log2Ceil(n).W))\n val hasData = RegInit(false.B)\n io.p.ready := !hasData\n when (io.p.fire()) {\n hasData := true.B\n sr := io.p.bits.data\n count := io.p.bits.count\n sentCount := 0.U\n }\n\n io.s.valid := hasData\n io.s.bits := sr(0)\n when (hasData) {\n sr := sr >> 1\n sentCount := sentCount + 1.U\n hasData := sentCount =/= count\n }\n\n when (io.p.fire()) {\n printfInfo(\"Piso: Parallel bits 0x%x, count 0x%x\\n\", io.p.bits.data,\n io.p.bits.count)\n }\n\n assert(!(io.p.valid && !io.p.ready),\n \"Piso: Received parallel data but not ready\\n\")\n}\n", "groundtruth": "class PisoCmd(n: Int) extends Bundle {\n val data = UInt(n.W)\n val count = UInt(log2Ceil(n).W)\n}\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.9, "category_reason": "Bundle class definition"} {"task_id": "perfect-chisel", "path": "perfect-chisel/src/main/scala/perfect/util/Printf.scala", "left_context": "// Copyright 2017 IBM\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\npackage perfect.util\n\nimport chisel3._\n\ntrait UniformPrintfs {\n val printfSigil = \"\"\n\n def pp(prefix: String, message: String, args: Bits*): Unit = {\n printf(prefix + message, args:_*) }\n\n def printfInfo (m: String, a: Bits*) { pp(\"[INFO] \", printfSigil++m, a:_*) }\n", "right_context": " def printfError(m: String, a: Bits*) { pp(\"[ERROR] \", printfSigil++m, a:_*) }\n def printfDebug(m: String, a: Bits*) { pp(\"[DEBUG] \", printfSigil++m, a:_*) }\n def printfTodo (m: String, a: Bits*) { pp(\"[TODO] \", printfSigil++m, a:_*) }\n}\n", "groundtruth": " def printfWarn (m: String, a: Bits*) { pp(\"[WARN] \", printfSigil++m, a:_*) }\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "perfect-chisel", "path": "perfect-chisel/src/test/scala/random/Lfsr.scala", "left_context": "// Copyright 2017 IBM\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\npackage perfect.random\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.testers.BasicTester\nimport math.pow\n\nclass LfsrTester(n: Int, seed: Int = 1) extends BasicTester {\n val dut = Module(new Lfsr(n))\n val count = RegInit(0.U((n + 1).W))\n\n val s_INIT :: s_RUN :: s_CYCLE :: s_DONE :: Nil = Enum(4)\n val state = RegInit(UInt(4.W), s_INIT)\n\n dut.io.seed.valid := state === s_INIT\n when (state === s_INIT) {\n dut.io.seed.bits := seed.U\n count := 0.U\n state := s_RUN\n }\n\n when (state === s_RUN) {\n count := count + 1.U\n when (dut.io.y === seed.U && count > 0.U) {\n state := s_CYCLE\n }\n }\n\n when (state === s_CYCLE) {\n printf(\"[INFO] Found period 0d%d\\n\", count)\n assert(count === math.pow(2, n).toInt.U,\n \"LfsrTester: Found unexpectedly short cycle\")\n state := s_DONE\n }\n\n when (state === s_DONE) { stop }\n\n}\n\nclass Lfsr8Test extends LfsrTester(8)\n", "right_context": "", "groundtruth": "class Lfsr16Test extends LfsrTester(16)\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.55, "category_reason": "Code near when block"} {"task_id": "MultiScalarMultiplication", "path": "MultiScalarMultiplication/src/main/scala/MSM/Bucket.scala", "left_context": "package MSM\n\nimport chisel3._\n\n/** TODO\n * - should this take as input one point at a time? a few points at a time?\n * */\n\nclass Bucket(pw: Int, sw: Int) extends Module {\n val io = IO(new Bundle {\n val px = Input(UInt(pw.W))\n val py = Input(UInt(pw.W))\n val s = Input(UInt(sw.W))\n val load = Input(Bool())\n val mult = Input(Bool())\n val outx = Output(UInt(pw.W))\n val outy = Output(UInt(pw.W))\n })\n\n val x = RegInit(UInt(pw.W))\n val y = RegInit(UInt(pw.W))\n val s = RegInit(UInt(pw.W))\n val numbuckets = math.pow(2, sw)\n val B = Reg(Vec(numbuckets.toInt, UInt(sw.W))) // buckets, one for each possible s\n val pa = Module(new PointAddition(pw))\n\n // latch point into regs\n", "right_context": "", "groundtruth": " when (io.load) {\n x := io.px\n y := io.py\n s := io.s\n }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "MultiScalarMultiplication", "path": "MultiScalarMultiplication/src/main/scala/MSM/Interfaces.scala", "left_context": "package MSM\n\nimport chisel3._\n\n/** TODO\n * - remove cloneType when upgrade to chisel3.5\n * */\n\n/* bundle that represents affine (x,y) coordinate */\nclass PointBundle(val w: Int) extends Bundle {\n val x = SInt(w.W)\n val y = SInt(w.W)\n\n def apply(X: Int, Y: Int): Unit = {\n x := X.S\n y := Y.S\n }\n override def cloneType = (new PointBundle(w)).asInstanceOf[this.type]\n}\n\n/* bundle that represents projective coordinates where\n * x = X/X and y = Y/Z */\nclass PointProjectiveBundle(val w: Int) extends Bundle {\n val x = SInt(w.W)\n val y = SInt(w.W)\n val z = SInt(w.W)\n", "right_context": "}\n", "groundtruth": " override def cloneType = (new PointProjectiveBundle(w)).asInstanceOf[this.type]\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "MultiScalarMultiplication", "path": "MultiScalarMultiplication/src/main/scala/MSM/PAddReduction.scala", "left_context": "package MSM\n\nimport chisel3._\nimport chisel3.util.log2Ceil\nimport chisel3.util.RegEnable\nimport chisel3.util._\n\n/**\n * Point Addition Reduction Module\n * This module takes in a number of points to sum up at a certain time and\n * performs an addition reduction. This is done by instantiating a Point Addition\n * module and using it repeatedly to end up with a final sum.\n *\n * @param numPoints: the number of ec points to sum up\n * @param pw: \"point width\" i.e. the bit width of the ec points\n * @param a: coefficient from definition of elliptic curve\n * @param p: prime modulus from definition of elliptic curve\n * */\n\nobject PAddReduction {\n val idle :: working :: Nil = Enum(2)\n}\n\nclass PAddReduction(numPoints: Int, pw: Int, a: Int, p: Int) extends Module {\n val io = IO(new Bundle {\n val load = Input(Bool())\n val xs = Input(Vec(numPoints, SInt(pw.W)))\n val ys = Input(Vec(numPoints, SInt(pw.W)))\n val outx = Output(SInt(pw.W))\n val outy = Output(SInt(pw.W))\n val valid = Output(Bool())\n })\n\n // import states\n import PAddReduction._\n\n\n // instantiations\n val count = RegInit(1.U(log2Ceil(numPoints).W))\n val xreg = RegInit(io.xs(0.U))\n val yreg = RegInit(io.ys(0.U))\n val validBit = RegEnable(false.B, false.B, io.load)\n validBit := validBit || io.load\n val state = RegInit(idle)\n\n // latch points into regs\n val xvec = Reg(Vec(numPoints, SInt(pw.W)))\n val yvec = Reg(Vec(numPoints, SInt(pw.W)))\n when (io.load) {\n", "right_context": " io.outx := 0.S\n io.outy := 0.S\n io.valid := false.B\n\n // regs to hold intermediate values\n val xinter = RegEnable(xvec(0), 0.S, RegNext(io.load))\n val yinter = RegEnable(yvec(0), 0.S, RegNext(io.load))\n\n // main switch statement\n switch (state) {\n is (idle) {\n io.valid := false.B\n\n // have defaults ready\n xinter := xvec(0)\n yinter := yvec(0)\n count := 1.U\n\n when (io.load) {\n state := working\n }\n }\n is (working) {\n io.valid := false.B\n\n // instantiate the Point Addition Module\n val pa = Module(new PointAddition(pw))\n pa.io.load := RegNext(RegNext(io.load)) || RegNext(pa.io.valid)\n pa.io.a := a.S\n pa.io.p := p.S\n\n // assign inputs to PAdd Module\n pa.io.p1x := xinter\n pa.io.p1y := yinter\n pa.io.p2x := xvec(count)\n pa.io.p2y := yvec(count)\n\n // check if we have an infinite input\n val p1inf = (pa.io.p1x === 0.S && pa.io.p1y === 0.S)\n val p2inf = (pa.io.p2x === 0.S && pa.io.p2y === 0.S)\n val infinput = (p1inf || p2inf) && validBit\n\n // go high with infinput, go low when valid goes back down\n val test = RegInit(false.B)\n when (infinput) {\n test := true.B\n } .elsewhen (!pa.io.valid && RegNext(pa.io.valid)) {\n test := false.B\n }\n\n // update inputs to PAdd Module\n when (infinput && pa.io.valid) {\n when (p1inf && !p2inf) { // may need this later for other case\n xinter := pa.io.p2x\n yinter := pa.io.p2y\n } .elsewhen (!p1inf && p2inf) {\n when (count === numPoints.U - 1.U) {\n state := idle\n io.valid := true.B\n io.outx := xinter\n io.outy := yinter\n }\n }\n count := count + 1.U\n }.elsewhen (pa.io.valid && !test) {\n count := count + 1.U\n xinter := pa.io.outx\n yinter := pa.io.outy\n }\n\n // assert valid signal, state transition\n when (pa.io.valid && count === numPoints.U - 1.U && !test) {//&& !RegNext(infinput) && !RegNext(RegNext(infinput))) {\n state := idle\n io.valid := true.B\n io.outx := pa.io.outx\n io.outy := pa.io.outy\n }\n }\n }\n\n // debugging\n /*when ((io.load) || RegNext(io.load)) {\n io.xs zip io.ys foreach { case (x, y) => printf(p\"(${x},${y}) \") }\n printf(p\" PADDREDUCTION count=${count}\\n\")\n xvec zip yvec foreach { case (x, y) => printf(p\"(${x},${y}) \") }\n printf(p\" PADDREDUCTION count=${count}\\n\")\n }*/\n}\n", "groundtruth": " for (i <- 0 until numPoints) {\n xvec(i) := io.xs(i)\n yvec(i) := io.ys(i)\n }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Loop-based Control", "confidence": 0.8, "category_reason": "for loop"} {"task_id": "MultiScalarMultiplication", "path": "MultiScalarMultiplication/src/main/scala/MSM/PMNaive.scala", "left_context": "package MSM\n\nimport chisel3._\nimport chisel3.internal.naming.chiselName\nimport chisel3.util.RegEnable\nimport chisel3.util._\n\n\n/**\n * Point Multiplication Module (Naive)\n * This module performs scalar point multiplication. However, it does this\n * rather inefficiently. If we wanted to compute P * 12, this module does\n * P + P + ... + P and so on. There's a faster way to do this, which would constrain\n * the latency to log2Ceil(scalar) cycles would be to use the double and add\n * method, and implementation for which can be found in PMBitSerial.\n *\n * @param pw: \"point width\" i.e. the bit width of the ec points\n * @param sw: \"scalar width\" i.e. the bit width of the scalar\n * */\n\nobject PMNaive {\n val idle :: working :: specialcases :: Nil = Enum(3)\n}\n\nclass PMNaive(pw: Int, sw: Int) extends Module {\n val io = IO(new Bundle {\n val a = Input(SInt(pw.W))\n val p = Input(SInt(pw.W))\n val px = Input(SInt(pw.W))\n val py = Input(SInt(pw.W))\n val s = Input(SInt(sw.W))\n val load = Input(Bool())\n val valid = Output(Bool())\n val outx = Output(SInt(pw.W))\n val outy = Output(SInt(pw.W))\n })\n\n // import states\n import PMNaive._\n val state = RegInit(idle)\n\n // valid bit that determines whether output is valid on start up\n val validBit = RegEnable(false.B, false.B, io.load)\n validBit := validBit || io.load\n\n // reg to deal w inf input\n val infinputreg = Reg(Bool())\n\n // regs to latch x, y, and s values, delay load by 1 cycle\n val x = RegEnable(io.px, 0.S, io.load)\n val y = RegEnable(io.py, 0.S, io.load)\n val s = RegEnable(io.s, 0.S, io.load)\n val delayedLoad = RegNext(io.load)\n\n // regs to hold intermediate results\n val xinter = RegEnable(io.px, 0.S, io.load)\n val yinter = RegEnable(io.py, 0.S, io.load)\n\n // instantiate PointAddition module and make connections\n val padd = Module(new PointAddition(pw))\n padd.io.a := io.a\n padd.io.p := io.p\n padd.io.p1x := x\n padd.io.p1y := y\n padd.io.p2x := xinter\n padd.io.p2y := yinter\n padd.io.load := RegNext(io.load)\n\n // check if we have an infinite input\n val p1inf = (padd.io.p1x === 0.S && padd.io.p1y === 0.S)\n val p2inf = (padd.io.p2x === 0.S && padd.io.p2y === 0.S)\n val infinput = (p1inf || p2inf) && validBit\n\n // go high with infinput, go low when valid goes back down\n val test = RegInit(false.B)\n when (infinput) {\n test := true.B\n } .elsewhen (!padd.io.valid && RegNext(padd.io.valid)) {\n test := false.B\n }\n\n // default values\n io.outx := 0.S\n io.outy := 0.S\n io.valid := false.B\n\n // main switch statement\n switch (state) {\n is (idle) {\n // defaults\n io.valid := false.B\n xinter := io.px\n yinter := io.py\n\n when (io.load) {\n when (io.s === 0.S || io.s === 1.S) {\n state := specialcases\n } .otherwise {\n state := working\n }\n }\n }\n is (specialcases) {\n io.valid := false.B\n when (io.s === 0.S) {\n io.valid := true.B\n state := idle\n io.outx := 0.S\n io.outy := 0.S\n }\n when (io.s === 1.S) {\n io.valid := true.B\n state := idle\n io.outx := x\n io.outy := y\n }\n }\n is (working) {\n padd.io.load := RegNext(io.load) || RegNext(padd.io.valid)\n\n when (infinput && padd.io.valid) {\n when (p1inf && !p2inf) {\n printf(\"should never happen\\n\")\n } .elsewhen (!p1inf && p2inf) {\n when (s === 3.S) {\n xinter := x\n yinter := y\n }\n", "right_context": " } .otherwise {\n s := s - 1.S\n xinter := x\n yinter := y\n }\n }\n //s := s - 1.S\n } .elsewhen (padd.io.valid & !test) {\n s := s - 1.S\n xinter := padd.io.outx\n yinter := padd.io.outy\n }\n\n // we are done, set output and state transistion\n when (s === 2.S && padd.io.valid && !infinput && !test) {\n io.valid := true.B\n state := idle\n io.outx := padd.io.outx\n io.outy := padd.io.outy\n }\n }\n }\n // debugging\n /*printf(p\"state(${state}) valid(${io.valid}) out(${io.outx},${io.outy}) count(${s}) inter(${xinter}${yinter}) pa.io.load=${padd.io.load}, pa.io.valid(${padd.io.valid}) inputs(${padd.io.p1x}${padd.io.p1y})(${padd.io.p2x}${padd.io.p2y}) test(${test}) s=${io.s}\")\n when (infinput) {\n printf(\"we got an infinput\")\n }\n printf(\"\\n\")*/\n\n}\n", "groundtruth": " when (s === 2.S) {\n state := idle\n io.valid := true.B\n", "crossfile_context": "", "category": "Interface", "subcategory": "Handshake and Flow Control", "confidence": 0.8, "category_reason": "Ready/valid handshake assignment"} {"task_id": "MultiScalarMultiplication", "path": "MultiScalarMultiplication/src/main/scala/MSM/PointAddition.scala", "left_context": "package MSM\n\nimport chisel3._\nimport chisel3.util.RegEnable\n\n/**\n * Point Addition Module\n * This module takes in two EC points and adds them together.\n *\n * @param w: the bit width of the EC point inputs\n *\n * TODO\n * - custom bundle interface for PointAddition (will make switching to Projective easier)\n * - utilize Option[T] to let this synthesize full adder or just doubler\n * - mod inverse with gcd method\n * */\n\n\n/* hardware module that performs ec point additon. */\nclass PointAddition(val w: Int) extends Module {\n val io = IO(new Bundle {\n val a = Input(SInt(w.W))\n val p = Input(SInt(w.W))\n val p1x = Input(SInt(w.W))\n val p1y = Input(SInt(w.W))\n val p2x = Input(SInt(w.W))\n val p2y = Input(SInt(w.W))\n val load = Input(Bool())\n val outx = Output(SInt(w.W))\n val outy = Output(SInt(w.W))\n val valid = Output(Bool())\n })\n\n // latch inputs into regs\n val p1x = RegEnable(io.p1x, 0.S, io.load)\n val p1y = RegEnable(io.p1y, 0.S, io.load)\n val p2x = RegEnable(io.p2x, 0.S, io.load)\n val p2y = RegEnable(io.p2y, 0.S, io.load)\n\n // instantiations\n val modinv = Module(new ModularInverse(w))\n val l = Wire(SInt())\n val new_x = Wire(SInt())\n val new_y = Wire(SInt())\n val validBit = RegEnable(false.B, false.B, io.load)\n validBit := validBit || RegNext(io.load)\n\n // control signals\n", "right_context": " val p1inf = p1x === 0.S && p1y === 0.S\n val p2inf = p2x === 0.S && p2y === 0.S\n\n // default values and assignments\n modinv.io.p := io.p\n modinv.io.load := RegNext(io.load) // takes a cycle to latch inputs\n io.outx := 0.S\n io.outy := 0.S\n new_x := 0.S\n new_y := 0.S\n\n // create new point coordinates, when not dealing w special case\n when (!p1inf && !p2inf && !inverses) {\n new_x := ((l * l) - p1x - p2x) % io.p\n io.outx := new_x\n when (new_x < 0.S) {\n io.outx := new_x + io.p\n }\n new_y := (l * (p1x - new_x) - p1y) % io.p\n io.outy := new_y\n when (new_y < 0.S) {\n io.outy := new_y + io.p\n }\n }\n \n // calculate lambda, handle case when P1 == P2\n modinv.io.a := p2x - p1x\n when (p1x === p2x && p1y === p2y) { // point double\n new_x := ((l * l) - p1x - p1x) % io.p\n modinv.io.a := 2.S * p1y\n l := (3.S * p1x * p1x + io.a) * modinv.io.out\n } .otherwise {\n l := (p2y - p1y) * modinv.io.out\n }\n\n // assert valid signal, handles special cases\n io.valid := modinv.io.valid && !io.load && !RegNext(io.load) && validBit\n\n when (RegNext(inverses)) { // output point at infinity\n io.valid := true.B && validBit // when P1 == -P2\n io.outx := 0.S\n io.outy := 0.S\n } .elsewhen (RegNext(p1inf)) { // p1 is point at inf\n io.valid := true.B && validBit\n io.outx := p2x\n io.outy := p2y\n } .elsewhen (RegNext(p2inf)) { // p2 is point at inf\n io.valid := true.B && validBit\n io.outx := p1x\n io.outy := p1y\n } .elsewhen (modinv.io.valid && modinv.io.out === -1.S) { // no mod inverse\n io.valid := true.B && validBit // when P1 == -P2\n io.outx := 0.S\n io.outy := 0.S\n }\n\n // debugging\n //when (RegNext(io.load)) {\n // printf(p\"padd -> (${p1x}${p1y})\\n(${p2x}${p2y})\\n\")\n //}\n //printf(p\"--- inside PAdd modinvout=${modinv.io.out}, load=${io.load}, valid=${io.valid}, validBit=${validBit}, p1inf=${p1inf}, p2inf=${p2inf}\\n\\n\")\n //printf(p\"--- inside PAdd (${p1x},${p1y}) + (${p2x},${p2y}) = (${io.outx},${io.outy}), load=${io.load}, padd.io.valid=${io.valid}\\n\\n\\n\")\n}\n\n/**\n * Multiplicative Modular Inverse Module\n * This module takes in two values, a and p, and finds the mod inverse of\n * a mod p.\n *\n * @param w: the bit width of inputs a and p\n * */\nclass ModularInverse(val w: Int) extends Module {\n val io = IO(new Bundle {\n val a = Input(SInt(w.W))\n val p = Input(SInt(w.W))\n val load = Input(Bool())\n val valid = Output(Bool())\n val out = Output(SInt(w.W))\n })\n\n val a = RegInit(0.S(w.W))\n val p = RegInit(0.S(w.W))\n val n = RegInit(0.S(w.W))\n val condition = (a * n) % p\n val neg = io.a < 0.S\n\n when (io.load) {\n a := Mux(neg, -io.a, io.a)\n p := io.p\n n := 0.S\n io.valid := false.B\n }\n\n io.out := Mux(neg, io.p - n, n)\n io.valid := false.B\n\n when (condition =/= 1.S && n < p) {\n n := n + 1.S\n } .elsewhen (condition === 1.S && n < p) {\n io.valid := true.B\n } .elsewhen (n === p) {\n io.out := -1.S\n io.valid := true.B\n }\n\n // debugging\n //printf(p\"a=${a}, p=${p}, n=${n}, valid=${io.valid}\\n\\n\")\n}\n", "groundtruth": " val inverses = p1x === p2x && p1y === -p2y\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.6, "category_reason": "val binding"} {"task_id": "MultiScalarMultiplication", "path": "MultiScalarMultiplication/src/main/scala/MSM/TopLevelMSM.scala", "left_context": "package MSM\n\nimport chisel3._\nimport chisel3.util.RegEnable\nimport chisel3.util.log2Ceil\nimport chisel3.util._\n\n/**\n * Top Level Multi-Scalar Multiplication Module\n * This module requests input from memory and uses that data for its msm computation.\n * It instantiates Point Mult modules and a Point Addition Reduction modules to sum\n * up the results from all the multiplications.\n *\n * @param requestsize: number of scalars/points to request at a time\n * @param numPMmodules: number of PMult modules to request at a time\n * @param a: coefficient from definition of elliptic curve\n * @param p: prime modulus from definition of elliptic curve\n * */\n\nobject TopLevelMSM {\n val idle :: multiplying :: reduction :: Nil = Enum(3)\n}\n\nclass TopLevelMSM(pw: Int, sw: Int, a: Int, p: Int,\n requestsize: Int, numPMmodules: Int) extends Module {\n val io = IO(new Bundle {\n val complete = Input(Bool())\n val load = Input(Bool())\n val pointsx = Input(Vec(requestsize, SInt(pw.W)))\n val pointsy = Input(Vec(requestsize, SInt(pw.W)))\n val scalars = Input(Vec(requestsize, SInt(sw.W)))\n val valid = Output(Bool())\n val outx = Output(SInt(pw.W))\n val outy = Output(SInt(pw.W))\n })\n\n // import states\n import TopLevelMSM._\n val state = RegInit(idle)\n\n\n // make Seq of Regs, holding Points and Scalars\n", "right_context": " val yregseq = io.pointsy map { y => RegEnable(y, 0.S, io.load) }\n val sregseq = io.scalars map { s => RegEnable(s, 0.S, io.load) }\n val completebits = Reg(Vec(requestsize, Bool()))\n when(io.load) {\n for (i <- 0 until requestsize) {\n completebits(i) := false.B\n }\n }\n\n\n // Seq of PointMult Modules\n // connect all point mult modules\n // set completebit and capture output when a mult is complete\n val PointMults = Seq.fill(requestsize)(Module(new PMNaive(pw, sw)))\n PointMults.zipWithIndex foreach { case (pm, i) =>\n pm.io.a := a.S\n pm.io.p := p.S\n pm.io.px := xregseq(i)\n pm.io.py := yregseq(i)\n pm.io.s := sregseq(i)\n pm.io.load := RegNext(RegNext(io.load))\n when ((pm.io.valid) && !completebits(i)) {\n completebits(i) := true.B\n xregseq(i) := pm.io.outx // capture outputs\n yregseq(i) := pm.io.outy\n }\n }\n\n\n // Point Addition Reduction Module and check completebits array\n val par = Module(new PAddReduction(numPMmodules, pw, a, p))\n PointMults.zipWithIndex foreach { case (pm, i) =>\n par.io.xs(i) := xregseq(i)\n par.io.ys(i) := yregseq(i)\n }\n val readyforreduction = completebits reduce {_ && _}\n when (RegNext(readyforreduction)) {\n for (i <- 0 until requestsize) {\n completebits(i) := false.B\n }\n }\n par.io.load := RegNext(!readyforreduction && RegNext(readyforreduction))\n\n // val outputregs\n val outregx = RegInit(0.S(pw.W))\n val outregy = RegInit(0.S(pw.W))\n io.outx := outregx\n io.outy := outregy\n io.valid := false.B\n\n // main switch statement\n switch (state) {\n is (idle) {\n io.valid := false.B\n when (io.load) {\n state := multiplying\n }\n }\n is (multiplying) {\n when (readyforreduction) {\n state := reduction\n }\n }\n is (reduction) {\n outregx := par.io.outx\n outregy := par.io.outy\n when (RegNext(par.io.valid)) {\n state := idle\n io.valid := true.B\n }\n }\n }\n\n // debugging\n /*when (RegNext(RegNext(io.load))) {\n printf(\"IO.LOAD: \")\n xregseq zip yregseq zip sregseq foreach { case((x,y), s) => printf(p\"(${x},${y})${s} \")}\n printf(\"\\n\")\n }*/\n\n /*when (readyforreduction) {\n printf(\"READYFORREDUCTION: \")\n xregseq zip yregseq foreach { case(x,y) => printf(p\"(${x},${y}) \")}\n printf(\"\\n\")\n }*/\n\n //printf(p\"${completebits} load=${io.load} valid${io.valid} paddreduc.load(${par.io.load}) result(${par.io.outx},${par.io.outy})\\n\")\n}", "groundtruth": " val xregseq = io.pointsx map { x => RegEnable(x, 0.S, io.load) }\n", "crossfile_context": "", "category": "Storage Block", "subcategory": "Register-based Storage", "confidence": 0.85, "category_reason": "RegEnable register"} {"task_id": "MultiScalarMultiplication", "path": "MultiScalarMultiplication/src/test/scala/MSM/EllipticCurve.scala", "left_context": "package MSM\n\n/**\n * This is an elliptic curve class that tracks a curves\n * a and b coefficients, as well as the order of the\n * finite field it is defined over. The elliptic curve\n * will have the form: y^2 = A*x^3 + B*x (mod P)\n * param A: a coefficient\n * param B: a coefficient\n * param P: order of the finite field, hopefully prime\n * param G: generator point for this curve\n */\n", "right_context": "", "groundtruth": "class EllipticCurve(A: BigInt, B: BigInt, P: BigInt) {\n val a: BigInt = A\n val b: BigInt = B\n val p: BigInt = P\n //val g: Point = G\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "MultiScalarMultiplication", "path": "MultiScalarMultiplication/src/test/scala/MSM/MSMtest.scala", "left_context": "package MSM\n\n//import MSM.{EllipticCurve, Point, zksnarkMSM_model}\nimport Util._\nimport chisel3._\nimport chisel3.tester._\nimport chisel3.tester.RawTester.test\nimport org.scalatest.{FlatSpec, FreeSpec}\nimport chisel3.experimental.BundleLiterals._\n\n/**\n * This class contains functions that interface with different modules. They allow\n * tests to be run with much cleaner syntax and allow for the poking and expecting\n * of inputs to be reused.\n * */\nclass testfunctions {\n def PointAdditionTest(dut: PointAddition, a: Int, p: Int,\n p1x: Int, p1y: Int, p2x: Int, p2y: Int,\n rx: Int, ry: Int): Unit = {\n //println(\"PA Tests starting: (\" + p1x, p1y +\") + (\" + p2x, p2y + \") = (\" + rx, ry +\")\")\n dut.io.a.poke(a.S)\n dut.io.p.poke(p.S)\n dut.io.p1x.poke(p1x.S)\n dut.io.p1y.poke(p1y.S)\n dut.io.p2x.poke(p2x.S)\n dut.io.p2y.poke(p2y.S)\n dut.io.load.poke(true.B)\n dut.clock.step(1)\n dut.io.load.poke(false.B)\n dut.clock.step(1)\n while ((dut.io.valid.peek().litValue() == 0)) dut.clock.step(1)\n dut.io.outx.expect(rx.S)\n dut.io.outy.expect(ry.S)\n dut.clock.step()\n }\n\n def PMNaiveTest(dut: PMNaive, a: Int, p: Int,\n px: Int, py: Int, s: Int,\n rx: Int, ry: Int): Unit = {\n println(\"PMNaive Tests starting: (\" + px, py +\") * (\" + s + \") = (\" + rx, ry +\")\")\n dut.io.a.poke(a.S)\n dut.io.p.poke(p.S)\n dut.io.px.poke(px.S)\n dut.io.py.poke(py.S)\n dut.io.s.poke(s.S)\n dut.io.load.poke(true.B)\n dut.clock.step()\n dut.io.load.poke(false.B)\n while ((dut.io.valid.peek().litValue() == 0)) dut.clock.step(1)\n //dut.clock.step(3)\n dut.io.outy.expect(ry.S)\n dut.io.outx.expect(rx.S)\n dut.clock.step()\n }\n\n def PMBSTest(dut: PMBitSerial, a: Int, p: Int,\n px: Int, py: Int, s: Int,\n rx: Int, ry: Int): Unit = {\n println(\"PMBS Tests starting: (\" + px, py +\") * (\" + s + \") = (\" + rx, ry +\")\")\n dut.io.a.poke(a.S)\n dut.io.p.poke(p.S)\n dut.io.px.poke(px.S)\n dut.io.py.poke(py.S)\n dut.io.s.poke(s.S)\n dut.io.load.poke(true.B)\n dut.clock.step()\n dut.io.load.poke(false.B)\n while ((dut.io.valid.peek().litValue() == 0)) dut.clock.step(1)\n dut.io.outy.expect(ry.S)\n dut.io.outx.expect(rx.S)\n }\n\n def PAReductionTest(dut: PAddReduction, x: Seq[SInt], y: Seq[SInt],\n rx: Int, ry: Int): Unit = {\n x.zipWithIndex foreach { case (s, i) => dut.io.xs(i).poke(s) }\n y.zipWithIndex foreach { case (s, i) => dut.io.ys(i).poke(s) }\n dut.io.load.poke(true.B)\n dut.clock.step()\n dut.io.load.poke(false.B)\n while ((dut.io.valid.peek().litValue() == 0)) dut.clock.step(1)\n dut.io.outx.expect(rx.S)\n dut.io.outy.expect(ry.S)\n dut.clock.step()\n }\n\n def betterReductionTest(dut: PAddReduction, points: Seq[(Int, Int)],\n a: BigInt, b: BigInt, p: BigInt): Unit = {\n\n // make curve and list of Point objects\n val curve = new EllipticCurve(a, b, p)\n val refpoints = points map { case(x,y) => new Point(x, y, curve) }\n val result = refpoints reduce {_ + _}\n\n points.zipWithIndex foreach { case ((x, y), i) =>\n dut.io.xs(i).poke(x.S)\n dut.io.ys(i).poke(y.S)\n }\n dut.io.load.poke(true.B)\n dut.clock.step()\n dut.io.load.poke(false.B)\n while ((dut.io.valid.peek().litValue() == 0)) dut.clock.step(1)\n dut.clock.step(5)\n //dut.io.outx.expect(result.x.S)\n //dut.io.outy.expect(result.y.S)\n //dut.clock.step()\n }\n\n\n def TopLevelTest(dut: TopLevelMSM, x: Seq[SInt], y: Seq[SInt], s: Seq[SInt],\n rx: Int, ry: Int): Unit = {\n println(s\"TopLevelTest nummults = ${x.length}\")\n x.zipWithIndex foreach { case (x, i) => dut.io.pointsx(i).poke(x) }\n y.zipWithIndex foreach { case (y, i) => dut.io.pointsy(i).poke(y) }\n s.zipWithIndex foreach { case (s, i) => dut.io.scalars(i).poke(s) }\n dut.io.load.poke(true.B)\n dut.io.complete.poke(true.B)\n dut.clock.step()\n dut.io.load.poke(false.B)\n while ((dut.io.valid.peek().litValue() == 0)) dut.clock.step(1)\n dut.io.outx.expect(rx.S)\n dut.io.outy.expect(ry.S)\n dut.clock.step(3)\n }\n\n def TopLevelTestVariableLength(dut: TopLevelMSM, points: Seq[(Int, Int)], scalars: Seq[Int],\n rs: Int, wkld: Int, a: Int, b: Int, p: Int): Unit = {\n assert (points.size == scalars.size)\n //assert (points.size % rs == 0)\n println(s\"TopLevelTest wkld: ${wkld} size: ${rs}\")\n\n\n var allinputs = points zip scalars\n", "right_context": " val numInputs = allinputs.size / rs\n\n\n //allinputs foreach println\n\n val curve = new EllipticCurve(a, b, p)\n\n for (iter <- 0 until numInputs) {\n //println(s\"iteration $iter\")\n val currentinputs = allinputs.take(rs)\n //currentinputs foreach { case ((x,y), s) => print(s\"(${x},${y}) * ${s} + \")}\n //println(\"\\n\")\n allinputs = allinputs.drop(rs)\n currentinputs.zipWithIndex foreach { case(((x,y), s), i) => // point zipped with scalar zipped with ind\n dut.io.pointsx(i).poke(x.S)\n dut.io.pointsy(i).poke(y.S)\n dut.io.scalars(i).poke(s.S)\n }\n dut.io.load.poke(true.B)\n dut.clock.step()\n dut.io.load.poke(false.B)\n while ((dut.io.valid.peek().litValue() == 0)) dut.clock.step(1)\n\n // expect outputs\n val currPoints = currentinputs map { case ((x,y), s) => new Point(x, y, curve)}\n val currScalars = currentinputs map { case ((x,y), s) => s}\n val result = zksnarkMSM_model(currPoints, currScalars)\n //result.print()\n dut.io.outx.expect(result.x.S)\n dut.io.outy.expect(result.y.S)\n dut.clock.step(2)\n }\n }\n}\n\n/**\n * The main test class. This contains tests for all the modules.\n * Tests are roughly in top down order. Comment them out as you\n * see fit.\n * */\nclass MSMtest extends FreeSpec with ChiselScalatestTester {\n val t = new testfunctions()\n\n // -----------------------------------------------------\n // tests for Top Level Module\n \"TopLevelMSM Tests (size 4) - manual tests\" in {\n test(new TopLevelMSM(8, 8, 0, 17, 4, 4)) { dut =>\n val xs = Seq(1, 5, 6, 12) map (x => x.S(8.W))\n val ys = Seq(5, 9, 6, 1) map (y => y.S(8.W))\n val ss = Seq(2, 4, 6, 8) map (y => y.S(8.W))\n t.TopLevelTest(dut, xs, ys, ss, 12, 1)\n //val xs = Seq(15, 2, 8, 12) map (x => x.S(8.W))\n //val ys = Seq(13,10, 3, 1) map (y => y.S(8.W))\n //val ss = Seq( 1, 2, 3, 4) map (s => s.S(8.W))\n //t.TopLevelTest(dut, xs, ys, ss, 5, 9)\n //val xs1 = Seq(15, 2, 8, 12) map (x => x.S(8.W))\n //val ys1 = Seq(13,10, 3, 1) map (y => y.S(8.W))\n //val ss1 = Seq( 1, 2, 3, 4) map (s => s.S(8.W))\n //t.TopLevelTest(dut, xs1, ys1, ss1, 5, 9)\n //val xs2 = Seq(6, 1,10, 15) map (x => x.S(8.W))\n //val ys2 = Seq(6, 5, 2, 13) map (y => y.S(8.W))\n //val ss2 = Seq( 9,10,11,12) map (s => s.S(8.W))\n //t.TopLevelTest(dut, xs2, ys2, ss2, 1, 12)\n }\n }\n\n /*\"TopLevelMSM Tests (size 8) - manual tests\" in {\n test(new TopLevelMSM(8, 8, 0, 17, 8, 8)) { dut =>\n val xs = Seq(1, 5, 6, 12, 5, 2, 1, 10) map (x => x.S(8.W))\n val ys = Seq(5, 9, 6, 1, 8, 7, 12, 15) map (y => y.S(8.W))\n val ss = Seq(2, 4, 6, 8, 1, 3, 5, 7) map (y => y.S(8.W))\n t.TopLevelTest(dut, xs, ys, ss, 8, 3)\n //t.TopLevelTest(dut, xs, ys, ss, 8, 3) // do it again?\n }\n }*/\n\n // Much more extensive top level tests\n // WARNING: Very time consuming!\n /*val testSizes = Seq(2,4,6,12,16,24) // change this to determine how many tests get run\n tastSizes foreach { s =>\n s\"TopLevelMSM W 1 size ${s} function\" in {\n val size = s\n test (new TopLevelMSM(8,8,0,17,size,size)) { dut =>\n val points = Seq((15,13), (2,10), (8,3), (12,1), (6,6), (5,8), (10,15), (1,12), (6,6), (1,5), (10,2), (15,13))\n val scalars = Seq(1,2,3,4,5,6,7,8,9,10,11,12)\n t.TopLevelTestVariableLength(dut, points, scalars, size, 1, 0, 7, 17)\n }\n }\n s\"TopLevelMSM W 2 size ${s} function\" in {\n val size = s\n test (new TopLevelMSM(8,8,0,17,size,size)) { dut =>\n val points2 = Seq((15,13), (2,10), (8,3), (12,1), (6,6), (6,6), (10,15), (1,12), (6,6), (1,5), (10,2), (15,13))\n val scalars2 = Seq(1,20,2,4, 19,6,7,12, 22,1,11,12)\n t.TopLevelTestVariableLength(dut, points2, scalars2, size, 2, 0, 7, 17)\n }\n }\n }*/\n\n\n // -----------------------------------------------------\n // tests for Point Add Reduction Module\n /*\"PAdd Reduction Tests (size 4) - manual tests\" in {\n test (new PAddReduction2(4, 1size, 0, 17)) { dut =>\n //val xs0 = Seq( 1, 1, 8, 12) map (x => x.S(8.W))\n //val ys0 = Seq( 5, 12, 3, 1) map (y => y.S(8.W))\n //t.PAReductionTest(dut, xs0, ys0, 10, 15)\n //val xs1 = Seq( 1, 3, 8, 12) map (x => x.S(8.W))\n //val ys1 = Seq( 5, 0, 3, 1) map (y => y.S(8.W))\n //t.PAReductionTest(dut, xs1, ys1, 1, 12)\n //val xs2 = Seq( 2, 12, 0, 12) map (x => x.S(8.W))\n //val ys2 = Seq(10, 16, 0, 16) map (y => y.S(8.W))\n //t.PAReductionTest(dut, xs2, ys2, 5, 9)\n val xs2 = Seq( 3, 1, 6, 1) map (x => x.S(8.W)) // last point is inf\n dut.clock.step(20)\n val ys2 = Seq( 0, 5, 11, 5) map (y => y.S(8.W))\n t.PAReductionTest(dut, xs2, ys2, 5, 8)\n }\n }*/\n\n /*\"Reduction Tests (size 4) - manual, better function\" in {\n test (new PAddReduction(4, 16, 0, 17)) { dut =>\n //val points3 = Seq((6,6),(12,1),(5,9),(2,7))\n //t.betterReductionTest(dut, points3, 0, 7, 17)\n //val points2 = Seq((15,13),(12,1),(3,0),(2,7))\n //t.betterReductionTest(dut, points2, 0, 7, 17)\n //val points = Seq((10,15),(0,0),(6,11),(1,5)) // gets no modinv error?\n //t.betterReductionTest(dut, points, 0, 7, 17)\n //val points1 = Seq((3,0), (1,5), (6,11), (0,0))\n //t.betterReductionTest(dut, points1, 0, 7, 17)\n //val points1 = Seq((6,6), (0,0), (6,11), (5,8)) // this needs fixing\n //t.betterReductionTest(dut, points1, 0, 7, 17)\n }\n }*/\n\n /*\"PAdd Reduction Tests (size 17) - manual tests\" in {\n test (new PAddReduction(17, 16, 0, 17)) { dut =>\n val xs1 = Seq(15, 2, 8, 12, 6, 5, 10, 1, 3, 1, 10, 5, 6, 12, 8, 2, 15) map (x => x.S(8.W))\n val ys1 = Seq(13, 10, 3, 1, 6, 8, 15, 12, 0, 5, 2, 9, 11, 16, 14, 7, 4) map (y => y.S(8.W))\n t.PAReductionTest(dut, xs1, ys1, 3, 0)\n }\n }*/\n\n // -----------------------------------------------------\n // tests for Point Multiplication (Bit Serial) Module\n /*\"PMBitSerial Tests - manual tests\" in {\n test (new PMBitSerial(8, 8)) { dut =>\n dut.io.a.poke(0.S)\n dut.io.p.poke(17.S)\n dut.io.px.poke(15.S)\n dut.io.py.poke(13.S)\n dut.io.s.poke(15.S)\n dut.io.load.poke(true.B)\n dut.clock.step()\n dut.io.load.poke(false.B)\n while ((dut.io.valid.peek().litValue() == 0)) dut.clock.step(1)\n }\n }*/\n\n // -----------------------------------------------------\n // tests for Point Multiplication (Naive) Module\n /*\"PointMultNaive Tests - manual tests\" in {\n test (new PMNaive(16, 16)) { dut =>\n t.PMNaiveTest(dut, 0, 17, 15, 13, 0, 0, 0) // mult by zero\n t.PMNaiveTest(dut, 0, 17, 15, 13, 1, 15, 13) // mult by 1\n t.PMNaiveTest(dut, 0, 17, 15, 13, 2, 2, 10)\n t.PMNaiveTest(dut, 0, 17, 15, 13, 3, 8, 3)\n t.PMNaiveTest(dut, 0, 17, 15, 13, 18, 0, 0) // back to point at inf\n t.PMNaiveTest(dut, 0, 17, 15, 13, 17, 15, 4) // back to point at inf\n t.PMNaiveTest(dut, 0, 17, 15, 13, 19, 15, 13) // back to point at inf\n t.PMNaiveTest(dut, 0, 17, 12, 16, 8, 12, 1)\n t.PMNaiveTest(dut, 0, 17, 12, 16, 9, 0, 0)\n t.PMNaiveTest(dut, 0, 17, 12, 16, 8, 12, 1) // this shit copied\n t.PMNaiveTest(dut, 0, 17, 12, 16, 9, 0, 0) // this shit copied\n t.PMNaiveTest(dut, 0, 17, 12, 16, 10, 12, 16) // this shit\n //t.PMNaiveTest(dut, 0, 17, 12, 16, 11, 1, 5)\n //t.PMNaiveTest(dut, 0, 17, 12, 16, 29, 1, 5)\n //t.PMNaiveTest(dut, 0, 17, 12, 16, 34, 1, 12)\n //t.PMNaiveTest(dut, 0, 17, 12, 16, 35, 12, 1)\n //t.PMNaiveTest(dut, 0, 17, 1, 12, 6, 5, 9)\n //t.PMNaiveTest(dut, 0, 17, 12, 1, 4, 2, 7)\n //t.PMNaiveTest(dut, 0, 17, 15, 13, 21, 8, 3)\n t.PMNaiveTest(dut, 0, 17, 2, 10, 20, 12,1)\n }\n }*/\n\n /*\"PointMultNaive Tests - extensive tests\" in {\n test (new PMNaive(32, 32)) { dut =>\n val p1707 = new EllipticCurve(0, 7, 17)\n val g = new Point(15, 13, p1707) // generator point\n for (i <- 0 until 18) {\n val r = g * i\n t.PMNaiveTest(dut, 0, 17, 15, 13, i, r.x, r.y)\n }\n }\n }*/\n\n\n // -----------------------------------------------------\n // tests for Point Addition Module\n /*\"PointAddition Tests - manual tests\" in {\n test (new PointAddition(32)) { dut =>\n t.PointAdditionTest(dut, 0, 17, 15, 13, 15, 13, 2, 10) // point double\n t.PointAdditionTest(dut, 0, 17, 15, 13, 2, 10, 8, 3)\n t.PointAdditionTest(dut, 0, 17, 0, 0, 6, 11, 6, 11) // p1 at inf\n t.PointAdditionTest(dut, 0, 17, 15, 13, 0, 0, 15, 13) // p2 at inf\n t.PointAdditionTest(dut, 0, 17, 3, 0, 6, 11, 12, 1)\n t.PointAdditionTest(dut, 0, 17, 15, 13, 15, 14, 0, 0) //get back to point at inf\n t.PointAdditionTest(dut, 0, 17, 2, 10, 12, 16, 2, 7) //get back to point at inf\n t.PointAdditionTest(dut, 0, 17, 2, 7, 0, 0, 2, 7) //get back to point at inf\n t.PointAdditionTest(dut, 0, 17, 2, 7, 12, 16, 5, 9) //get back to point at inf\n t.PointAdditionTest(dut, 0, 17, 15, 13, 15, 4, 0, 0)\n t.PointAdditionTest(dut, 0, 17, 1, 5, 1, 12, 0, 0)\n }\n }*/\n\n /*\"PointAddition Tests - more extensive, small curve\" in {\n test (new PointAddition(32)) { dut =>\n val p1707 = new EllipticCurve(0, 7, 17)\n val g = new Point(15, 13, p1707) // generator point\n\n for (i <- 0 until 100) {\n val t = g * i\n val r = g + t\n dut.io.a.poke(g.curve.a.S)\n dut.io.p.poke(g.curve.p.S)\n dut.io.p1x.poke(g.x.S)\n dut.io.p1y.poke(g.y.S)\n dut.io.p2x.poke(t.x.S)\n dut.io.p2y.poke(t.y.S)\n dut.io.load.poke(true.B)\n dut.clock.step(1)\n dut.io.load.poke(false.B)\n dut.clock.step(1)\n while ((dut.io.valid.peek().litValue() == 0)) dut.clock.step(1)\n dut.io.outx.expect(r.x.S)\n dut.io.outy.expect(r.y.S)\n }\n }\n }*/\n\n /*\"PointAddition Tests - slightly bigger curve\" in {\n test(new PointAddition(32)) { dut =>\n val p99707a = BigInt(\"-1\")\n val p99707b = BigInt(\"1\")\n val p99707p = BigInt(\"97\")\n val p99707 = new EllipticCurve(p99707a, p99707b, p99707p)\n val xc = BigInt(\"76\")\n val yc = BigInt(\"48\")\n val gp = new Point(xc, yc, p99707)\n dut.io.a.poke(gp.curve.a.S)\n dut.io.p.poke(gp.curve.p.S)\n dut.io.p1x.poke(gp.x.S)\n dut.io.p1y.poke(gp.y.S)\n\n for (n <- 1 until 100) {\n val t = gp * n\n val r = gp + t\n dut.io.p2x.poke(t.x.S)\n dut.io.p2y.poke(t.y.S)\n dut.io.load.poke(true.B)\n dut.clock.step(1)\n dut.io.load.poke(false.B)\n dut.clock.step(1)\n while ((dut.io.valid.peek().litValue() == 0)) dut.clock.step(1)\n dut.io.outx.expect(r.x.S)\n dut.io.outy.expect(r.y.S)\n }\n }\n }*/\n\n\n // -----------------------------------------------------\n // tests for Moduler Inverse Module\n /*\"ModularInverse should find the mod inverse\" in {\n test(new ModularInverse(32)) { dut =>\n dut.io.a.poke(3.S)\n dut.io.p.poke(7.S)\n dut.io.load.poke(true.B)\n dut.clock.step(1)\n dut.io.load.poke(false.B)\n dut.clock.step(1)\n while ((dut.io.valid.peek().litValue() == 0)) dut.clock.step(1)\n dut.io.out.expect(5.S)\n\n dut.io.a.poke(4.S)\n dut.io.p.poke(17.S)\n dut.io.load.poke(true.B)\n dut.clock.step(1)\n dut.io.load.poke(false.B)\n dut.clock.step(1)\n while ((dut.io.valid.peek().litValue() == 0)) dut.clock.step(1)\n dut.io.out.expect(13.S)\n\n dut.io.a.poke(2.S) // case where there is no inverse, returns 0\n dut.io.p.poke(6.S)\n dut.io.load.poke(true.B)\n dut.clock.step(1)\n dut.io.load.poke(false.B)\n dut.clock.step(1)\n while ((dut.io.valid.peek().litValue() == 0)) dut.clock.step(1)\n dut.io.out.expect(0.S)\n\n dut.io.a.poke(-10.S) // case where a is negative\n dut.io.p.poke(17.S)\n dut.io.load.poke(true.B)\n dut.clock.step(1)\n dut.io.load.poke(false.B)\n dut.clock.step(1)\n while ((dut.io.valid.peek().litValue() == 0)) dut.clock.step(1)\n dut.io.out.expect(5.S)\n }\n }*/\n}\n", "groundtruth": " allinputs = (0 until 1000) flatMap { i => allinputs }\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "MultiScalarMultiplication", "path": "MultiScalarMultiplication/src/test/scala/MSM/Point.scala", "left_context": "package MSM\n\nimport Util._\n\n/**\n * This class represents a point on an elliptic curve in a finite field.\n * It takes just two arguments, an X and Y coordinate. There are a number\n * of operations defined for these types of points.\n */\nclass Point(coord_x: BigInt, coord_y: BigInt, ec: EllipticCurve) {\n val x: BigInt = coord_x\n val y: BigInt = coord_y\n val curve: EllipticCurve = ec\n\n def double() = {\n val l = (BigInt(\"3\") * this.x * this.x + this.curve.a) * Util.modinv(BigInt(\"2\") * this.y, this.curve.p)\n var new_x = ((l * l) - this.x - this.x) % this.curve.p\n if (new_x < 0) {\n new_x = new_x + this.curve.p\n }\n var new_y = ((l * (this.x - new_x)) - this.y) % this.curve.p\n if (new_y < 0) {\n new_y = new_y + this.curve.p\n }\n new Point(new_x, new_y, this.curve)\n }\n\n def +(that: Point): Point = {\n if (this == that) {\n return this.double()\n }\n\n if (x == 0 && y == 0) {\n return that\n } else if (that.x == 0 && that.y == 0) {\n return this\n }\n\n\n val modinv = Util.modinv(that.x - this.x, this.curve.p)\n if (modinv == -1) return new Point(0, 0, this.curve)\n val l = (that.y - this.y) * modinv\n var new_x = ((l * l) - this.x - that.x) % this.curve.p\n if (new_x < 0) {\n new_x = new_x + this.curve.p\n }\n var new_y = ((l * (this.x - new_x)) - this.y) % this.curve.p\n if (new_y < 0) {\n new_y = new_y + this.curve.p\n }\n new Point(new_x, new_y, this.curve)\n }\n\n", "right_context": "\n def *(n: Int): Point = {\n if (n == 0) {\n return new Point(0, 0, this.curve)\n }\n def mult_helper(orig: Point, acc: Point, n: Int): Point = {\n if (n == 1) {\n return acc\n } else {\n val new_total = acc + orig\n mult_helper(orig, new_total, n-1)\n }\n }\n mult_helper(this, this, n)\n }\n\n def ==(that: Point) = {\n this.x == that.x && this.y == that.y\n }\n\n def print() = {\n println(s\"I am the point (${this.x}, ${this.y})\")\n }\n}\n", "groundtruth": " def unary_- = new Point(this.x, this.y * -1, this.curve)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "MultiScalarMultiplication", "path": "MultiScalarMultiplication/src/test/scala/MSM/Util.scala", "left_context": "package MSM\n\nobject Util {\n // from github.com/alexmgr/tinyec/blob/master/tinyec/ec.py\n def gcd(a: BigInt, b: BigInt): (BigInt, BigInt, BigInt) = {\n if (a == 0) {\n return (b, 0, 1)\n } else {\n val (g, y, x) = gcd(b % a, a)\n return (g, (x - (b / a) * y), y)\n }\n }\n\n // from github.com/alexmgr/tinyec/blob/master/tinyec/ec.py\n def modinv(a: BigInt, p: BigInt): BigInt = {\n if (a < 0) {\n return p - modinv(-a, p)\n }\n val (g, x, y) = gcd(a, p)\n if (g == 1) {\n return x % p\n }\n return BigInt(\"-1\")\n }\n\n /*\n * this performs bitwise multiplication. There is no need to actually do\n * multiplication this way in pure Scala, but it is a model of how hardware\n * could do this multiplication efficiently. This is just here for personal reference.\n */\n def bitwisemultiplication_Model(a: Int, b: Int): Int = {\n var result = 0\n for (i <- 0 until 32) {\n val operand = b << i\n val mask = a >> i\n if ((mask & 1) == 1) {\n result += operand\n }\n }\n result\n }\n\n /*\n * This mimics what the MSM part of zkSNARK does. It takes in two vectors.\n * One vectors of scalars, and another vector of points. It multiplies each\n * scalar by its corresponding point and them sums up all the points.\n */\n def zksnarkMSM_model(g: Seq[Point], e: Seq[Int]): Point = {\n assert(g.length == e.length, \"vectors should be the same length\")\n // multipy corresponding indexes of arrays and sum them up\n", "right_context": " }\n}\n", "groundtruth": " g zip e map { case (gi, ei) => gi * ei } reduce {_ + _}\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "KyogenRV", "path": "KyogenRV/src/main/scala/bus/simpleio.scala", "left_context": "// See README.md for license details.\npackage bus\n\nimport chisel3.{Bool, _}\n\n// bus ctrl\nclass CtrlSwChannel extends Bundle {\n val halt: Bool = Input(Bool()) // CPU or TraceMaster halt\n\n val r_add: UInt = Output(UInt(32.W)) // for debug: address dump\n val r_dat: UInt = Output(UInt(32.W)) // for test: memory dump\n\n val w_add: UInt = Input(UInt(32.W)) // for test: write address\n val w_dat: UInt = Input(UInt(32.W)) // for test: write data\n\n val g_add: UInt = Input(UInt(32.W)) // General register address (0 to 31)\n val g_dat: UInt = Output(UInt(32.W)) // General register data\n\n val r_pc: UInt = Output(UInt(32.W)) // Program Counter Read register\n val w_pc: UInt = Input(UInt(32.W)) // Program Counter Write register\n// val misc: Bool = Output(Bool()) // misc for test\n\n // EX stage iotester\n val r_ex_raddr1:UInt = Output(UInt(32.W))\n val r_ex_raddr2:UInt = Output(UInt(32.W))\n val r_ex_rs1:UInt = Output(UInt(32.W))\n val r_ex_rs2:UInt = Output(UInt(32.W))\n val r_ex_imm:UInt = Output(UInt(32.W))\n\n // MEM Stage\n val r_mem_alu_out:UInt = Output(UInt(32.W))\n // r_mem_alu_out_cmp\n\n // WB stage\n val r_wb_alu_out:UInt = Output(UInt(32.W))\n val r_wb_rf_wdata:UInt = Output(UInt(32.W))\n val r_wb_rf_waddr:UInt = Output(UInt(32.W))\n\n // STALL Signal\n val r_stall_sig:UInt = Output(UInt(32.W))\n\n // External interrupt signal\n val w_interrupt_sig: Bool = Input(Bool())\n\n // waitrequest signal\n val w_waitrequest_sig: Bool = Input(Bool())\n val w_datawaitreq_sig: Bool = Input(Bool())\n\n // waitrequest data signal\n //val w_waitreqdata_sig: Bool = Input(Bool())\n\n}\n\n// address channel bundle\nclass AddressChannel extends Bundle {\n val addr: UInt = Output(UInt(32.W)) // address (32bit)\n}\n\n// data channel bundle\nclass DataChannel extends Bundle {\n val req: Bool = Input(Bool()) // request signal\n val ack: Bool = Output(Bool()) // data is available ack\n val data: UInt = Output(UInt(32.W)) // data (32bit)\n}\n\nclass wDataChannel extends Bundle {\n val req: Bool = Output(Bool()) // request signal\n val ack: Bool = Input(Bool()) // data is available ack\n val data: UInt = Output(UInt(32.W)) // data (32bit)\n val byteenable: UInt = Output(UInt(4.W)) // byteenable (8bit lane x4 = 32bit)\n}\n\n// HOST :read only(IMem)\n// HOST :read/Write(Dmem)\nclass HostIf extends Bundle {\n // Instruction Memory\n // IO definition\n val imem_add: AddressChannel = new AddressChannel\n val r_imem_dat: DataChannel = Flipped(new DataChannel) // read operation\n val w_imem_dat: wDataChannel = new wDataChannel // write operation\n\n // data Memory\n val dmem_add: AddressChannel = new AddressChannel\n val r_dmem_dat: DataChannel = Flipped(new DataChannel) // read operation\n val w_dmem_dat: wDataChannel = new wDataChannel // write operation\n\n // debug if\n val sw: CtrlSwChannel = new CtrlSwChannel\n}\n\n// Memory-Mapped Slave IF\n// Slave :read/Write(IMem)\n// Slave :read/Write(Dmem)\nclass SlaveIf_Inst extends Bundle {\n // IO definition\n val imem_add: AddressChannel = Flipped(new AddressChannel)\n val r_imem_dat: DataChannel = new DataChannel // read operation\n val w_imem_dat: wDataChannel = Flipped(new wDataChannel) // write operation\n}\n\nclass SlaveIf_Data extends Bundle {\n // data Memory\n // IO definition\n val dmem_add: AddressChannel = Flipped(new AddressChannel)\n", "right_context": " val w_dmem_dat: wDataChannel = Flipped(new wDataChannel) // write operation\n}\n\nclass TestIf extends Bundle {\n val sw: CtrlSwChannel = new CtrlSwChannel\n}", "groundtruth": " val r_dmem_dat: DataChannel = new DataChannel // read operation\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.55, "category_reason": "Code near IO/Bundle"} {"task_id": "KyogenRV", "path": "KyogenRV/src/main/scala/core/ALU.scala", "left_context": "// See README.md for license details.\npackage core\n\nimport chisel3._\nimport chisel3.util._\n\nobject ALU {\n def ALU_ADD: UInt = 0.U(4.W)\n def ALU_SLL: UInt = 1.U(4.W)\n def ALU_SEQ: UInt = 2.U(4.W)\n def ALU_SNE: UInt = 3.U(4.W)\n def ALU_XOR: UInt = 4.U(4.W)\n def ALU_SRL: UInt = 5.U(4.W)\n def ALU_OR: UInt = 6.U(4.W)\n", "right_context": " def ALU_COPY1: UInt = 8.U(4.W)\n def ALU_COPY2: UInt = 9.U(4.W)\n def ALU_SUB: UInt = 10.U(4.W)\n def ALU_SRA: UInt = 11.U(4.W)\n def ALU_SLT: UInt = 12.U(4.W)\n def ALU_SGE: UInt = 13.U(4.W)\n def ALU_SLTU: UInt = 14.U(4.W)\n def ALU_SGEU: UInt = 15.U(4.W)\n\n def ALU_X: UInt = 0.U(4.W) // BitPat(\"b????\")\n\n def isSub(op: UInt): Bool = op(3) // need sub?\n def isCmp(op: UInt): Bool = op >=ALU_SLT // Compare op?\n def isCmpU(op: UInt): Bool = op >= ALU_SLTU // Compare unsigned?\n def isCmpI(op: UInt): Bool = op(0) // need inverse for compare?\n //noinspection ScalaStyle\n def isCmpEq(op: UInt): Bool = !op(3) // EQ or NEQ compare operation?\n}\n\nimport ALU._\n\n//noinspection ScalaStyle\nclass ALU extends Module {\n val io = IO {\n new Bundle {\n val op1: UInt = Input(UInt(32.W))\n val op2: UInt = Input(UInt(32.W))\n val alu_op: UInt = Input(UInt(4.W))\n val out: UInt = Output(UInt(32.W))\n val cmp_out: Bool = Output(Bool())\n }\n }\n\n // Shift\n val op2_inv: UInt = Mux(isSub(io.alu_op), ~io.op2, io.op2).asUInt()\n val sum: UInt = io.op1 + op2_inv + isSub(io.alu_op)\n val shamt: UInt = io.op2(4,0).asUInt\n val shin: UInt = Mux(io.alu_op === ALU_SRA || io.alu_op === ALU_SRL,io.op1,Reverse(io.op1))\n val shift_r: UInt = (Cat(isSub(io.alu_op) & shin(31), shin).asSInt >> shamt)(31, 0)\n val shift_l: UInt = Reverse(shift_r)\n val slt: Bool = Mux(io.op1(31) === io.op2(31), sum(31), Mux(isCmpU(io.alu_op), io.op2(31), io.op1(31)))\n\n val cmp: Bool = isCmpI(io.alu_op) ^ Mux(isCmpEq(io.alu_op), (io.op1 ^ io.op2) === 0.U, slt)\n\n val w_out: UInt =\n Mux(io.alu_op === ALU_ADD || io.alu_op === ALU_SUB, sum,\n Mux(io.alu_op === ALU_SLT || io.alu_op === ALU_SLTU, cmp,\n Mux(io.alu_op === ALU_SRA || io.alu_op === ALU_SRL, shift_r,\n Mux(io.alu_op === ALU_SLL, shift_l,\n Mux(io.alu_op === ALU_AND, io.op1 & io.op2,\n Mux(io.alu_op === ALU_OR, io.op1 | io.op2,\n Mux(io.alu_op === ALU_XOR, io.op1 ^ io.op2,\n Mux(io.alu_op === ALU_COPY1, io.op1 , io.op2))))))))\n\n// w_out := MuxLookup(io.alu_op, io.op2, Seq(\n// ALU_ADD -> (io.op1 + io.op2),\n// ALU_SLL -> (io.op1 << shamt),\n// ALU_SEQ -> (io.op1 === io.op2),\n// ALU_SNE -> (io.op1 =/= io.op2),\n// ALU_XOR -> (io.op1 ^ io.op2),\n// ALU_SRL -> (io.op1 >> shamt),\n// ALU_OR -> (io.op1 | io.op2),\n// ALU_AND -> (io.op1 & io.op2),\n// ALU_SUB -> (io.op1 - io.op2),\n// ALU_SRA -> (io.op1.asSInt >> shamt).asUInt,\n// ALU_SLT -> (io.op1.asSInt() < io.op2.asSInt()),\n// ALU_SGE -> (io.op1.asSInt() >= io.op2.asSInt()),\n// ALU_SLTU -> (io.op1< io.op2),\n// ALU_SGEU -> (io.op1 >= io.op2),\n// ALU_COPY1 -> io.op1, ALU_COPY2 -> io.op2)).asUInt()\n\n io.out := w_out\n io.cmp_out := cmp\n\n\n}", "groundtruth": " def ALU_AND: UInt = 7.U(4.W)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "KyogenRV", "path": "KyogenRV/src/main/scala/core/Instructions.scala", "left_context": "// See README.md for license details.\n\npackage core\n\nimport chisel3.UInt\nimport chisel3.util._\n\n\n\n//noinspection ScalaStyle\n/* Automatically generated by parse-opcodes */\nobject Instructions {\n def BEQ: BitPat = BitPat(\"b?????????????????000?????1100011\")\n def BNE: BitPat = BitPat(\"b?????????????????001?????1100011\")\n def BLT: BitPat = BitPat(\"b?????????????????100?????1100011\")\n def BGE: BitPat = BitPat(\"b?????????????????101?????1100011\")\n def BLTU: BitPat = BitPat(\"b?????????????????110?????1100011\")\n def BGEU: BitPat = BitPat(\"b?????????????????111?????1100011\")\n def JALR: BitPat = BitPat(\"b?????????????????000?????1100111\")\n def JAL: BitPat = BitPat(\"b?????????????????????????1101111\")\n def LUI: BitPat = BitPat(\"b?????????????????????????0110111\")\n def AUIPC: BitPat = BitPat(\"b?????????????????????????0010111\")\n def ADDI: BitPat = BitPat(\"b?????????????????000?????0010011\")\n def SLLI: BitPat = BitPat(\"b0000000??????????001?????0010011\")\n def SLTI: BitPat = BitPat(\"b?????????????????010?????0010011\")\n def SLTIU: BitPat = BitPat(\"b?????????????????011?????0010011\")\n def XORI: BitPat = BitPat(\"b?????????????????100?????0010011\")\n def SRLI: BitPat = BitPat(\"b000000???????????101?????0010011\")\n def SRAI: BitPat = BitPat(\"b010000???????????101?????0010011\")\n def ORI: BitPat = BitPat(\"b?????????????????110?????0010011\")\n def ANDI: BitPat = BitPat(\"b?????????????????111?????0010011\")\n def ADD: BitPat = BitPat(\"b0000000??????????000?????0110011\")\n def SUB: BitPat = BitPat(\"b0100000??????????000?????0110011\")\n def SLL: BitPat = BitPat(\"b0000000??????????001?????0110011\")\n def SLT: BitPat = BitPat(\"b0000000??????????010?????0110011\")\n def SLTU: BitPat = BitPat(\"b0000000??????????011?????0110011\")\n def XOR: BitPat = BitPat(\"b0000000??????????100?????0110011\")\n def SRL: BitPat = BitPat(\"b0000000??????????101?????0110011\")\n def SRA: BitPat = BitPat(\"b0100000??????????101?????0110011\")\n def OR: BitPat = BitPat(\"b0000000??????????110?????0110011\")\n def AND: BitPat = BitPat(\"b0000000??????????111?????0110011\")\n // def ADDIW: BitPat = BitPat(\"b?????????????????000?????0011011\")\n // def SLLIW: BitPat = BitPat(\"b0000000??????????001?????0011011\")\n // def SRLIW: BitPat = BitPat(\"b0000000??????????101?????0011011\")\n // def SRAIW: BitPat = BitPat(\"b0100000??????????101?????0011011\")\n // def ADDW: BitPat = BitPat(\"b0000000??????????000?????0111011\")\n // def SUBW: BitPat = BitPat(\"b0100000??????????000?????0111011\")\n // def SLLW: BitPat = BitPat(\"b0000000??????????001?????0111011\")\n // def SRLW: BitPat = BitPat(\"b0000000??????????101?????0111011\")\n // def SRAW: BitPat = BitPat(\"b0100000??????????101?????0111011\")\n def LB: BitPat = BitPat(\"b?????????????????000?????0000011\")\n def LH: BitPat = BitPat(\"b?????????????????001?????0000011\")\n def LW: BitPat = BitPat(\"b?????????????????010?????0000011\")\n // def LD: BitPat = BitPat(\"b?????????????????011?????0000011\")\n def LBU: BitPat = BitPat(\"b?????????????????100?????0000011\")\n def LHU: BitPat = BitPat(\"b?????????????????101?????0000011\")\n // def LWU: BitPat = BitPat(\"b?????????????????110?????0000011\")\n def SB: BitPat = BitPat(\"b?????????????????000?????0100011\")\n def SH: BitPat = BitPat(\"b?????????????????001?????0100011\")\n def SW: BitPat = BitPat(\"b?????????????????010?????0100011\")\n // def SD: BitPat = BitPat(\"b?????????????????011?????0100011\")\n def FENCE: BitPat = BitPat(\"b?????????????????000?????0001111\")\n def FENCE_I: BitPat = BitPat(\"b?????????????????001?????0001111\")\n // def MUL: BitPat = BitPat(\"b0000001??????????000?????0110011\")\n // def MULH: BitPat = BitPat(\"b0000001??????????001?????0110011\")\n // def MULHSU: BitPat = BitPat(\"b0000001??????????010?????0110011\")\n // def MULHU: BitPat = BitPat(\"b0000001??????????011?????0110011\")\n // def DIV: BitPat = BitPat(\"b0000001??????????100?????0110011\")\n // def DIVU: BitPat = BitPat(\"b0000001??????????101?????0110011\")\n // def REM: BitPat = BitPat(\"b0000001??????????110?????0110011\")\n // def REMU: BitPat = BitPat(\"b0000001??????????111?????0110011\")\n // def MULW: BitPat = BitPat(\"b0000001??????????000?????0111011\")\n // def DIVW: BitPat = BitPat(\"b0000001??????????100?????0111011\")\n // def DIVUW: BitPat = BitPat(\"b0000001??????????101?????0111011\")\n // def REMW: BitPat = BitPat(\"b0000001??????????110?????0111011\")\n // def REMUW: BitPat = BitPat(\"b0000001??????????111?????0111011\")\n // def LR_W: BitPat = BitPat(\"b00010??00000?????010?????0101111\")\n // def SC_W: BitPat = BitPat(\"b00011????????????010?????0101111\")\n // def LR_D: BitPat = BitPat(\"b00010??00000?????011?????0101111\")\n // def SC_D: BitPat = BitPat(\"b00011????????????011?????0101111\")\n def ECALL: BitPat = BitPat(\"b00000000000000000000000001110011\")\n def EBREAK: BitPat = BitPat(\"b00000000000100000000000001110011\")\n // def URET: BitPat = BitPat(\"b00000000001000000000000001110011\")\n", "right_context": " def ERET: BitPat = BitPat(\"b00010000000000000000000001110011\")\n // def DRET: BitPat = BitPat(\"b01111011001000000000000001110011\")\n // def SFENCE_VMA: BitPat = BitPat(\"b0001001??????????000000001110011\")\n // def WFI: BitPat = BitPat(\"b00010000010100000000000001110011\")\n def CSRRW: BitPat = BitPat(\"b?????????????????001?????1110011\")\n def CSRRS: BitPat = BitPat(\"b?????????????????010?????1110011\")\n def CSRRC: BitPat = BitPat(\"b?????????????????011?????1110011\")\n def CSRRWI: BitPat = BitPat(\"b?????????????????101?????1110011\")\n def CSRRSI: BitPat = BitPat(\"b?????????????????110?????1110011\")\n def CSRRCI: BitPat = BitPat(\"b?????????????????111?????1110011\")\n // def CUSTOM0: BitPat = BitPat(\"b?????????????????000?????0001011\")\n // def CUSTOM0_RS1: BitPat = BitPat(\"b?????????????????010?????0001011\")\n // def CUSTOM0_RS1_RS2: BitPat = BitPat(\"b?????????????????011?????0001011\")\n // def CUSTOM0_RD: BitPat = BitPat(\"b?????????????????100?????0001011\")\n // def CUSTOM0_RD_RS1: BitPat = BitPat(\"b?????????????????110?????0001011\")\n // def CUSTOM0_RD_RS1_RS2:BitPat = BitPat(\"b?????????????????111?????0001011\")\n // def CUSTOM1: BitPat = BitPat(\"b?????????????????000?????0101011\")\n // def CUSTOM1_RS1: BitPat = BitPat(\"b?????????????????010?????0101011\")\n // def CUSTOM1_RS1_RS2: BitPat = BitPat(\"b?????????????????011?????0101011\")\n // def CUSTOM1_RD: BitPat = BitPat(\"b?????????????????100?????0101011\")\n // def CUSTOM1_RD_RS1: BitPat = BitPat(\"b?????????????????110?????0101011\")\n // def CUSTOM1_RD_RS1_RS2:BitPat = BitPat(\"b?????????????????111?????0101011\")\n // def CUSTOM2: BitPat = BitPat(\"b?????????????????000?????1011011\")\n // def CUSTOM2_RS1: BitPat = BitPat(\"b?????????????????010?????1011011\")\n // def CUSTOM2_RS1_RS2: BitPat = BitPat(\"b?????????????????011?????1011011\")\n // def CUSTOM2_RD: BitPat = BitPat(\"b?????????????????100?????1011011\")\n // def CUSTOM2_RD_RS1: BitPat = BitPat(\"b?????????????????110?????1011011\")\n // def CUSTOM2_RD_RS1_RS2:BitPat = BitPat(\"b?????????????????111?????1011011\")\n // def CUSTOM3: BitPat = BitPat(\"b?????????????????000?????1111011\")\n // def CUSTOM3_RS1: BitPat = BitPat(\"b?????????????????010?????1111011\")\n // def CUSTOM3_RS1_RS2: BitPat = BitPat(\"b?????????????????011?????1111011\")\n // def CUSTOM3_RD: BitPat = BitPat(\"b?????????????????100?????1111011\")\n // def CUSTOM3_RD_RS1: BitPat = BitPat(\"b?????????????????110?????1111011\")\n // def CUSTOM3_RD_RS1_RS2:BitPat = BitPat(\"b?????????????????111?????1111011\")\n // def SLLI_RV32: BitPat = BitPat(\"b0000000??????????001?????0010011\")\n // def SRLI_RV32: BitPat = BitPat(\"b0000000??????????101?????0010011\")\n // def SRAI_RV32: BitPat = BitPat(\"b0100000??????????101?????0010011\")\n // def RDCYCLE: BitPat = BitPat(\"b11000000000000000010?????1110011\")\n // def RDTIME: BitPat = BitPat(\"b11000000000100000010?????1110011\")\n // def RDINSTRET: BitPat = BitPat(\"b11000000001000000010?????1110011\")\n // def RDCYCLEH: BitPat = BitPat(\"b11001000000000000010?????1110011\")\n // def RDTIMEH: BitPat = BitPat(\"b11001000000100000010?????1110011\")\n // def RDINSTRETH: BitPat = BitPat(\"b11001000001000000010?????1110011\")\n def NOP: UInt = BitPat.bitPatToUInt(BitPat(\"b00000000000000000000000000010011\"))\n}\n\n", "groundtruth": " def MRET: BitPat = BitPat(\"b00110000001000000000000001110011\")\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "KyogenRV", "path": "KyogenRV/src/main/scala/core/constant.scala", "left_context": "// See README.md for license details.\npackage core\n\nimport chisel3._\nimport chisel3.internal.firrtl.Width\nimport chisel3.util._\n\nobject PC_INITS {\n val PC_START = 0x000 // start address\n val PC_EVEC = 0xDEAD // interrupt address\n}\nobject ScalarOpConstants {\n // Control Signals\n def Y: UInt = 1.U(1.W)\n def N: UInt = 0.U(1.W)\n def X: BitPat = BitPat(\"b?\")\n\n // Branch Type\n def BR_N: UInt = 0.U(4.W) // Next\n def BR_J: UInt = 1.U(4.W) // Jump\n def BR_JR: UInt = 2.U(4.W) // Jump Register\n def BR_RET: UInt = 3.U(4.W) // mret / sret\n def BR_NE: UInt = 4.U(4.W) // Branch on NotEqual\n def BR_EQ: UInt = 5.U(4.W) // Branch on Equal\n def BR_GE: UInt = 6.U(4.W) // Branch on Greater/Equal\n def BR_GEU: UInt = 7.U(4.W) // Branch on Greater/Equal Unsigned\n def BR_LT: UInt = 8.U(4.W) // Branch on Less Than\n def BR_LTU: UInt = 9.U(4.W) // Branch on Less Than Unsigned\n\n def BR_X: BitPat = BitPat(\"b????\")\n\n // RS1 Operand Select Signal\n def OP1_RS1: UInt = 1.U(2.W) // Register Source #1\n def OP1_PC: UInt = 2.U(2.W) // PC\n def OP1_X: UInt = 0.U(2.W)\n\n // RS2 Operand Select Signal\n def OP2_RS2: UInt = 1.U(2.W) // Register Source #2\n def OP2_IMM: UInt = 2.U(2.W) // immediate, I-type\n", "right_context": "\n // Register File Write Enable Signal\n def REN_0: UInt = \"b0\".U\n def REN_1: UInt = \"b1\".U\n def REN_X: BitPat = BitPat(\"b?\")\n\n // Writeback Select Signal\n def WB_PC4: UInt = 0.U(2.W)\n def WB_ALU: UInt = 1.U(2.W)\n def WB_MEM: UInt = 2.U(2.W)\n def WB_CSR: UInt = 3.U(2.W)\n def WB_X: BitPat = BitPat(\"b??\")\n\n // imm Type\n def IMM_X: BitPat = BitPat(\"b???\")\n def IMM_I: UInt = 0.U(3.W)\n def IMM_S: UInt = 1.U(3.W)\n def IMM_B: UInt = 2.U(3.W)\n def IMM_U: UInt = 3.U(3.W)\n def IMM_J: UInt = 4.U(3.W)\n def IMM_Z: UInt = 5.U(3.W) //zimm\n}\n\n\nobject MemoryOpConstants\n{\n // Memory Function Type (Read,Write,Fence) Signal\n def MWR_R: UInt = 0.U(2.W)\n def MWR_W: UInt = 1.U(2.W)\n def MWR_F: UInt = 2.U(2.W)\n def MWR_X: BitPat = BitPat(\"b??\")\n\n // Memory Enable Signal\n def MEN_0: UInt = \"b0\".U\n def MEN_1: UInt = \"b1\".U\n def MEN_X: BitPat = BitPat(\"b?\")\n\n // Memory Mask Type Signal\n def MSK_B: UInt = 0.U(3.W)\n def MSK_BU: UInt = 1.U(3.W)\n def MSK_H: UInt = 2.U(3.W)\n def MSK_HU: UInt = 3.U(3.W)\n def MSK_W: UInt = 4.U(3.W)\n def MSK_X: BitPat = BitPat(\"b???\") //4.U(3.W)\n\n\n // Cache Flushes & Sync Primitives\n def M_N: UInt = 0.U(3.W)\n def M_SI: UInt = 1.U(3.W) // sync instruction stream\n def M_SD: UInt = 2.U(3.W) // sync data stream\n def M_FA: UInt = 3.U(3.W) // flush all caches\n def M_FD: UInt = 4.U(3.W) // flush data cache\n\n // Memory Functions (read, write, fence)\n def MT_READ: UInt = 0.U(2.W)\n def MT_WRITE: UInt = 1.U(2.W)\n def MT_FENCE: UInt = 2.U(2.W)\n\n val MT_SZ: Width = 3.W\n def MT_X: BitPat = BitPat(\"b???\") // 0.U(3.W)\n def MT_B: UInt = 1.U(3.W)\n def MT_H: UInt = 2.U(3.W)\n def MT_W: UInt = 3.U(3.W)\n def MT_D: UInt = 4.U(3.W)\n def MT_BU: UInt = 5.U(3.W)\n def MT_HU: UInt = 6.U(3.W)\n def MT_WU: UInt = 7.U(3.W)\n\n val M_SZ: Width = 2.W\n def M_X: UInt = \"b00\".U(2.W)\n def M_XRD: UInt = \"b01\".U(2.W) // int load\n def M_XWR: UInt = \"b10\".U(2.W) // int store\n\n def DPORT = 0\n def IPORT = 1\n}\n\n", "groundtruth": " def OP2_X: UInt = 0.U(2.W)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "KyogenRV", "path": "KyogenRV/src/main/scala/core/control.scala", "left_context": "// See README.md for license details.\npackage core\n\nimport chisel3._\nimport chisel3.util._\nimport _root_.core.ALU._\nimport _root_.core.Instructions._\nimport _root_.core.MemoryOpConstants._\nimport _root_.core.ScalarOpConstants._\n\nimport scala.collection.mutable.ArrayBuffer\nimport scala.language.{implicitConversions, postfixOps}\n\n//noinspection ScalaStyle\nobject util {\n", "right_context": "}\n\nimport util._\n\n// ID-Stage\n\nclass ElementOfInstruction extends Bundle{\n val bits: UInt = UInt(32.W)\n //val op = UInt(7.W) // opcode\n //val fct3 = UInt(3.W) // funct3\n val rd: UInt = UInt(5.W) // rd or imm[4:0]\n val rs1: UInt = UInt(5.W) // rs\n val rs2: UInt = UInt(5.W) // or shamt\n val csr: UInt = UInt(12.W) //\n}\n\nclass CDecoder(x: UInt){\n\n def inst(\n bits: UInt,\n //op: UInt = x(6, 0),\n //fct3: UInt = x(14, 12),\n rd: UInt = x(11, 7),\n rs1: UInt = x(19, 15),\n rs2: UInt = x(24, 20),\n csr: UInt = x(31, 20)\n ): ElementOfInstruction =\n {\n val res = Wire(new ElementOfInstruction)\n res.bits := bits\n //res.op := op\n //res.fct3 := fct3\n res.rd := rd\n res.rs1 := rs1\n res.rs2 := rs2\n //res.imm115 := imm115\n res.csr := csr\n res // return (res)\n }\n}\n\nclass IDModule extends Module{\n val io = IO (\n new Bundle {\n val imem: UInt = Input(UInt(32.W))\n val inst: ElementOfInstruction = Output(new ElementOfInstruction)\n })\n io.inst := new CDecoder(x = io.imem).inst(bits = io.imem)\n}\n\n\n// See also instructions.scala and constant.scala\nclass IDecode {\n val table: Array[(BitPat, List[BitPat])] = Array(\n /* 1bit | 4bit | 2bit | 2bit | IMM_X | 4bit | 2bit | 1bit | 1bit | 1bit| 3bit | 3bit */\n /* val | BR | op1 | op2 | imm | ALU | wb | rf | mem | mem | mask | csr */\n /* inst | type | sel | sel | type | fcn | sel | wen | en | wr | type | cmd */\n LUI -> List(Y, BR_N , OP1_X , OP2_IMM , IMM_U , ALU_COPY2, WB_ALU, REN_1, MEN_0, M_X , MT_X ,CSR.N),\n AUIPC -> List(Y, BR_N , OP1_PC , OP2_IMM , IMM_U , ALU_ADD , WB_ALU, REN_1, MEN_0, M_X , MT_X ,CSR.N),\n\n JAL -> List(Y, BR_J , OP1_PC , OP2_IMM , IMM_J , ALU_ADD , WB_PC4, REN_1, MEN_0, M_X , MT_X ,CSR.N),\n JALR -> List(Y, BR_JR , OP1_RS1, OP2_IMM , IMM_I , ALU_ADD , WB_PC4, REN_1, MEN_0, M_X , MT_X ,CSR.N),\n BEQ -> List(Y, BR_EQ , OP1_RS1, OP2_RS2 , IMM_B , ALU_SEQ , WB_X , REN_0, MEN_0, M_X , MT_X ,CSR.N),\n BNE -> List(Y, BR_NE , OP1_RS1, OP2_RS2 , IMM_B , ALU_SNE , WB_X , REN_0, MEN_0, M_X , MT_X ,CSR.N),\n BLT -> List(Y, BR_LT , OP1_RS1, OP2_RS2 , IMM_B , ALU_SLT , WB_X , REN_0, MEN_0, M_X , MT_X ,CSR.N),\n BGE -> List(Y, BR_GE , OP1_RS1, OP2_RS2 , IMM_B , ALU_SGE , WB_X , REN_0, MEN_0, M_X , MT_X ,CSR.N),\n BLTU -> List(Y, BR_LTU, OP1_RS1, OP2_RS2 , IMM_B , ALU_SLTU, WB_X , REN_0, MEN_0, M_X , MT_X ,CSR.N),\n BGEU -> List(Y, BR_GEU, OP1_RS1, OP2_RS2 , IMM_B , ALU_SGEU, WB_X , REN_0, MEN_0, M_X , MT_X ,CSR.N),\n\n LB -> List(Y, BR_N , OP1_RS1, OP2_IMM , IMM_I , ALU_ADD , WB_MEM, REN_1, MEN_1,M_XRD, MT_B ,CSR.N),\n LH -> List(Y, BR_N , OP1_RS1, OP2_IMM , IMM_I , ALU_ADD , WB_MEM, REN_1, MEN_1,M_XRD, MT_H ,CSR.N),\n LW -> List(Y, BR_N , OP1_RS1, OP2_IMM , IMM_I , ALU_ADD , WB_MEM, REN_1, MEN_1,M_XRD, MT_W ,CSR.N),\n LBU -> List(Y, BR_N , OP1_RS1, OP2_IMM , IMM_I , ALU_ADD , WB_MEM, REN_1, MEN_1,M_XRD, MT_BU,CSR.N),\n LHU -> List(Y, BR_N , OP1_RS1, OP2_IMM , IMM_I , ALU_ADD , WB_MEM, REN_1, MEN_1,M_XRD, MT_HU,CSR.N),\n SB -> List(Y, BR_N , OP1_RS1, OP2_IMM , IMM_S , ALU_ADD , WB_X , REN_0, MEN_1,M_XWR, MT_B ,CSR.N),\n SH -> List(Y, BR_N , OP1_RS1, OP2_IMM , IMM_S , ALU_ADD , WB_X , REN_0, MEN_1,M_XWR, MT_H ,CSR.N),\n SW -> List(Y, BR_N , OP1_RS1, OP2_IMM , IMM_S , ALU_ADD , WB_X , REN_0, MEN_1,M_XWR, MT_W ,CSR.N),\n\n ADDI -> List(Y, BR_N , OP1_RS1, OP2_IMM , IMM_I , ALU_ADD , WB_ALU, REN_1, MEN_0, M_X , MT_X ,CSR.N),\n SLTI -> List(Y, BR_N , OP1_RS1, OP2_IMM , IMM_I , ALU_SLT , WB_ALU, REN_1, MEN_0, M_X , MT_X ,CSR.N),\n SLTIU -> List(Y, BR_N , OP1_RS1, OP2_IMM , IMM_I , ALU_SLTU, WB_ALU, REN_1, MEN_0, M_X , MT_X ,CSR.N),\n XORI -> List(Y, BR_N , OP1_RS1, OP2_IMM , IMM_I , ALU_XOR , WB_ALU, REN_1, MEN_0, M_X , MT_X ,CSR.N),\n ORI -> List(Y, BR_N , OP1_RS1, OP2_IMM , IMM_I , ALU_OR , WB_ALU, REN_1, MEN_0, M_X , MT_X ,CSR.N),\n ANDI -> List(Y, BR_N , OP1_RS1, OP2_IMM , IMM_I , ALU_AND , WB_ALU, REN_1, MEN_0, M_X , MT_X ,CSR.N),\n SLLI -> List(Y, BR_N , OP1_RS1, OP2_IMM , IMM_I , ALU_SLL , WB_ALU, REN_1, MEN_0, M_X , MT_X ,CSR.N),\n SRLI -> List(Y, BR_N , OP1_RS1, OP2_IMM , IMM_I , ALU_SRL , WB_ALU, REN_1, MEN_0, M_X , MT_X ,CSR.N),\n SRAI -> List(Y, BR_N , OP1_RS1, OP2_IMM , IMM_I , ALU_SRA , WB_ALU, REN_1, MEN_0, M_X , MT_X ,CSR.N),\n\n ADD -> List(Y, BR_N , OP1_RS1, OP2_RS2 , IMM_X , ALU_ADD , WB_ALU, REN_1, MEN_0, M_X , MT_X ,CSR.N),\n SUB -> List(Y, BR_N , OP1_RS1, OP2_RS2 , IMM_X , ALU_SUB , WB_ALU, REN_1, MEN_0, M_X , MT_X ,CSR.N),\n SLL -> List(Y, BR_N , OP1_RS1, OP2_RS2 , IMM_X , ALU_SLL , WB_ALU, REN_1, MEN_0, M_X , MT_X ,CSR.N),\n SLT -> List(Y, BR_N , OP1_RS1, OP2_RS2 , IMM_X , ALU_SLT , WB_ALU, REN_1, MEN_0, M_X , MT_X ,CSR.N),\n SLTU -> List(Y, BR_N , OP1_RS1, OP2_RS2 , IMM_X , ALU_SLTU, WB_ALU, REN_1, MEN_0, M_X , MT_X ,CSR.N),\n XOR -> List(Y, BR_N , OP1_RS1, OP2_RS2 , IMM_X , ALU_XOR , WB_ALU, REN_1, MEN_0, M_X , MT_X ,CSR.N),\n SRL -> List(Y, BR_N , OP1_RS1, OP2_RS2 , IMM_X , ALU_SRL , WB_ALU, REN_1, MEN_0, M_X , MT_X ,CSR.N),\n SRA -> List(Y, BR_N , OP1_RS1, OP2_RS2 , IMM_X , ALU_SRA , WB_ALU, REN_1, MEN_0, M_X , MT_X ,CSR.N),\n OR -> List(Y, BR_N , OP1_RS1, OP2_RS2 , IMM_X , ALU_OR , WB_ALU, REN_1, MEN_0, M_X , MT_X ,CSR.N),\n AND -> List(Y, BR_N , OP1_RS1, OP2_RS2 , IMM_X , ALU_AND , WB_ALU, REN_1, MEN_0, M_X , MT_X ,CSR.N),\n\n CSRRWI -> List(Y, BR_N , OP1_X , OP2_IMM , IMM_Z , ALU_X , WB_CSR, REN_1, MEN_0, M_X , MT_X ,CSR.W),\n CSRRSI -> List(Y, BR_N , OP1_X , OP2_IMM , IMM_Z , ALU_X , WB_CSR, REN_1, MEN_0, M_X , MT_X ,CSR.S),\n CSRRCI -> List(Y, BR_N , OP1_X , OP2_IMM , IMM_Z , ALU_X , WB_CSR, REN_1, MEN_0, M_X , MT_X ,CSR.C) ,\n CSRRW -> List(Y, BR_N , OP1_RS1, OP2_X , IMM_X , ALU_COPY1, WB_CSR, REN_1, MEN_0, M_X , MT_X ,CSR.W),\n CSRRS -> List(Y, BR_N , OP1_RS1, OP2_X , IMM_X , ALU_COPY1, WB_CSR, REN_1, MEN_0, M_X , MT_X ,CSR.S),\n CSRRC -> List(Y, BR_N , OP1_RS1, OP2_X , IMM_X , ALU_COPY1, WB_CSR, REN_1, MEN_0, M_X , MT_X ,CSR.C),\n ECALL -> List(Y, BR_N , OP1_X , OP2_X , IMM_X , ALU_X , WB_X , REN_0, MEN_0, M_X , MT_X ,CSR.P),\n MRET -> List(Y , BR_RET, OP1_X , OP2_X , IMM_X , ALU_X , WB_X , REN_0, MEN_0, M_X , MT_X ,CSR.P),\n ERET -> List(Y , BR_N , OP1_X , OP2_X , IMM_X , ALU_X , WB_CSR, REN_0, MEN_0, M_X , MT_X ,CSR.P),\n EBREAK -> List(Y, BR_N , OP1_X , OP2_X , IMM_X , ALU_X , WB_X , REN_0, MEN_0, M_X , MT_X ,CSR.P),\n //WFI -> List(Y , BR_N , OP1_X , OP2_X IMM_X , ALU_X , WB_X , REN_0, MEN_0, M_X , MT_X ,CSR.N),\n // implemented as a NOP IMM_X ,\n FENCE_I -> List(Y, BR_N , OP1_X , OP2_X , IMM_X , ALU_X , WB_X , REN_0, MEN_0, M_X , MT_X ,CSR.N),\n FENCE -> List(Y, BR_N , OP1_X , OP2_X , IMM_X , ALU_X , WB_X , REN_0, MEN_1, M_X , MT_X ,CSR.N)\n // we are already sequentially consistent, so no need to honor the fence instruction\n )\n}\n\n\n// Internal Control Signal Bundle(ALU ctrl, memory ctrl, etc)\n// from Rocket chip Decode.scala\nclass IntCtrlSigs extends Bundle {\n val legal: Bool = Bool()\n val br_type: UInt = Bits(BR_X.getWidth.W)\n\n val alu_op1: UInt = Bits(OP1_X.getWidth.W)\n val alu_op2: UInt = Bits(OP2_X.getWidth.W)\n val imm_type: UInt = Bits(IMM_X.getWidth.W)\n val alu_func: UInt = Bits(ALU_X.getWidth.W)\n \n val wb_sel: UInt = Bits(WB_X.getWidth.W)\n val rf_wen: Bool = Bool()\n val mem_en: Bool = Bool()\n\n val mem_wr: UInt = Bits(M_SZ)\n val mask_type: UInt = Bits(MT_SZ)\n val csr_cmd: UInt = Bits(CSR.N.getWidth.W)\n\n def default: List[BitPat] = {\n List(X, BR_X, OP1_X, OP2_X, IMM_X, ALU_X, WB_X, REN_X, MEN_X, M_X, MT_X ,CSR.N)\n }\n\n //noinspection ScalaStyle\n def decode(\n inst: UInt,\n table: Iterable[(BitPat, List[BitPat])]\n ): IntCtrlSigs =\n {\n val decoder: Seq[UInt] = {\n DecodeLogic(inst, default, mappingIn = table)\n }\n\n val sigs = {\n Seq(legal, br_type, alu_op1, alu_op2, imm_type, alu_func, wb_sel, rf_wen, mem_en, mem_wr, mask_type, csr_cmd)\n }\n \n (sigs zip decoder).foreach({case (s,d) => s := d })\n\n this // return (this)\n }\n}\n\nobject DecodeLogic {\n def apply(addr: UInt, default: Seq[BitPat], mappingIn: Iterable[(BitPat, Seq[BitPat])]): Seq[UInt] = {\n val mapping = ArrayBuffer.fill(default.size)(ArrayBuffer[(BitPat, BitPat)]())\n\n for ((key: BitPat, values: Seq[BitPat]) <- mappingIn)\n (values zipWithIndex)\n .foreach { case (value, i) => mapping(i) += key.->(value) }\n\n for ((thisDefault, thisMapping) <- default zip mapping)\n yield apply(addr, thisDefault, thisMapping)\n }\n \n def apply(addr: UInt, default: BitPat, mapping: Iterable[(BitPat, BitPat)]): UInt = {\n MuxCase(default.value.U, mapping.map{\n case (instBitPat, ctrlSigBitPat) => (addr === instBitPat) -> ctrlSigBitPat.value.U }.toSeq)\n }\n}\n//noinspection ScalaStyle\nobject ImmGen {\n def apply(sel: UInt, inst: UInt): SInt = {\n val sign = Mux(sel === IMM_Z, 0.S, inst(31).asSInt)\n val b30_20 = Mux(sel === IMM_U, inst(30,20).asSInt, sign)\n val b19_12 = Mux(sel =/= IMM_U && sel =/= IMM_J, sign, inst(19,12).asSInt)\n val b11 = Mux(sel === IMM_U || sel === IMM_Z, 0.S,\n Mux(sel === IMM_J, inst(20).asSInt,\n Mux(sel === IMM_B, inst(7).asSInt, sign)))\n val b10_5 = Mux(sel === IMM_U || sel === IMM_Z, 0.U, inst(30,25))\n val b4_1 = Mux(sel === IMM_U, 0.U,\n Mux(sel === IMM_S || sel === IMM_B, inst(11,8),\n Mux(sel === IMM_Z, inst(19,16), inst(24,21))))\n val b0 = Mux(sel === IMM_S, inst(7),\n Mux(sel === IMM_I, inst(20),\n Mux(sel === IMM_Z, inst(15), 0.U)))\n\n Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0).asSInt\n }\n}\n", "groundtruth": " implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "KyogenRV", "path": "KyogenRV/src/main/scala/core/core.scala", "left_context": "// See README.md for license details.\npackage core\n\nimport chisel3._\nimport chisel3.iotesters._\nimport chisel3.util._\nimport chisel3.Clock\n\nimport scala.io.{BufferedSource, Source}\nimport _root_.core.ScalarOpConstants._\nimport MemoryOpConstants._\nimport bus.{HostIf, TestIf}\nimport mem._\n\n\n//noinspection ScalaStyle\nclass KyogenRVCpu extends Module {\n val io: HostIf = IO(new HostIf)\n\n val invClock: Clock = Wire(new Clock)\n invClock := (~clock.asUInt()(0)).asBool.asClock() // Clock reversed\n", "right_context": " def fallingEdge(x: Bool): Bool = !x && RegNext(x)\n\n // ------- START: pipeline registers --------\n // program counter init\n val pc_ini: UInt = PC_INITS.PC_START.U(32.W) // pc start address\n val npc_ini: UInt = pc_ini + 4.U(32.W) // pc next\n val inst_nop: UInt = Instructions.NOP // NOP instruction (addi x0, x0, 0)\n val nop_ctrl: IntCtrlSigs = Wire(new IntCtrlSigs).decode(inst_nop, (new IDecode).table)\n\n // IF stage pipeline register\n val if_pc: UInt = RegInit(pc_ini)\n val if_npc: UInt = RegInit(npc_ini)\n\n // ID stage pipeline register\n val id_inst: UInt = RegInit(inst_nop)\n val id_pc: UInt = RegInit(pc_ini)\n val id_npc: UInt = RegInit(npc_ini)\n //val id_csr_addr: UInt = RegInit(0.U)\n\n // EX stage pipeline register\n val ex_pc: UInt = RegInit(pc_ini)\n val ex_npc: UInt = RegInit(npc_ini)\n val ex_inst: UInt = RegInit(inst_nop)\n val ex_ctrl: IntCtrlSigs = RegInit(nop_ctrl)\n val ex_reg_raddr: Vec[UInt] = RegInit(VecInit(0.U(5.W), 0.U(5.W)))\n val ex_reg_waddr: UInt = RegInit(0.U(5.W))\n val ex_rs: Vec[UInt] = RegInit(VecInit(0.U(32.W), 0.U(32.W)))\n val ex_csr_addr: UInt = RegInit(0.U(32.W))\n val ex_csr_cmd: UInt = RegInit(0.U(32.W))\n val ex_b_check: Bool = RegInit(false.B) // branch check\n val ex_j_check: Bool = RegInit(false.B) // jump check\n\n // MEM stage pipeline register\n val mem_pc: UInt = RegInit(pc_ini)\n val mem_npc: UInt = RegInit(npc_ini)\n val mem_ctrl: IntCtrlSigs = RegInit(nop_ctrl)\n val mem_imm: SInt = RegInit(0.S(32.W))\n val mem_reg_waddr: UInt = RegInit(0.U(5.W))\n val mem_rs: Vec[UInt] = RegInit(VecInit(0.U(32.W), 0.U(32.W)))\n val mem_alu_out: UInt = RegInit(0.U(32.W))\n val mem_alu_cmp_out: Bool = RegInit(false.B)\n val mem_csr_addr: UInt = RegInit(0.U(32.W))\n val mem_csr_data: UInt = RegInit(0.U(32.W))\n\n // WB stage pipeline register\n val wb_npc: UInt = RegInit(npc_ini)\n val wb_ctrl: IntCtrlSigs = RegInit(nop_ctrl)\n val wb_reg_waddr: UInt = RegInit(0.U(5.W))\n val wb_alu_out: UInt = RegInit(0.U(32.W))\n val wb_dmem_read_ack: Bool = RegInit(false.B)\n val wb_csr_addr: UInt = RegInit(0.U(32.W))\n val wb_csr_data: UInt = RegInit(0.U(32.W))\n\n // stall control\n val stall: Bool = Wire(Bool()) //RegInit(true.B)\n\n // branch control\n val inst_kill: Bool = Wire(Bool())\n val inst_kill_branch: Bool = Wire(Bool())\n\n // ------- END: pipeline registers --------\n\n // Program Counter\n val pc_cntr: UInt = RegInit(0.U(32.W)) // pc\n val npc: UInt = pc_cntr + 4.U(32.W) // next pc counter\n\n val r_req: Bool = RegInit(true.B) // fetch signal\n\n val w_req: Bool = RegInit(true.B)\n val w_ack: Bool = RegInit(false.B)\n val w_addr: UInt = RegInit(0.U(32.W))\n val w_data: UInt = RegInit(0.U(32.W))\n\n io.dmem_add.addr := RegInit(0.U(32.W))\n\n // ----- START:initialize logic for avalon-MM -----\n val imem_read_sig: Bool = RegNext(!io.w_imem_dat.req, false.B)\n\n\n //delay_stall is \"cheat\" logic to ready memory mapped logic.\n // stall 3 or 4 clock after reset.\n val delay_stall: UInt = RegInit(0.U(4.W))\n when(imem_read_sig === true.B) {\n when(delay_stall =/= 7.U) {\n delay_stall := delay_stall + 1.U\n }\n }.otherwise {\n delay_stall := 0.U(2.W)\n }\n // ----- END:startup logic for avalon-MM -----\n\n val valid_imem: Bool = RegInit(true.B)\n val imem_wait: Bool = io.sw.w_waitrequest_sig\n val dmem_wait: Bool = io.sw.w_datawaitreq_sig\n val dmem_rd_wait: Bool = wb_ctrl.mem_wr === M_XRD && !io.r_dmem_dat.ack\n val waitrequest: Bool = imem_wait || dmem_wait || dmem_rd_wait\n\n // -------- START: IF stage -------\n val imem_req: Bool = RegInit(false.B)\n val loadstore_in_pipe: Bool = (ex_ctrl.mem_wr =/= M_X) || (mem_ctrl.mem_wr =/= M_X) //|| (wb_ctrl.mem_wr === M_XRD)\n val loadstore_proc: Bool = /*(ex_ctrl.mem_wr =/= M_X) ||*/ (mem_ctrl.mem_wr =/= M_X) || (wb_ctrl.mem_wr =/= M_X)\n\n when(!stall && !inst_kill && !waitrequest && !loadstore_in_pipe) {\n if_pc := pc_cntr\n if_npc := npc\n imem_req := RegNext(imem_read_sig)\n valid_imem := RegNext(true.B)\n }.elsewhen(inst_kill && !waitrequest) {\n if_pc := pc_ini\n if_npc := npc_ini\n imem_req := RegNext(imem_read_sig)\n valid_imem := RegNext(false.B)\n }.otherwise {\n valid_imem := RegNext(false.B) //valid_imem\n when(loadstore_in_pipe) {\n imem_req := RegNext(false.B)\n }\n }\n io.r_imem_dat.req := imem_req\n // -------- END: IF stage --------\n\n\n // -------- START: ID stage -------\n val id_inst_temp: UInt = RegInit(inst_nop)\n val id_pc_temp: UInt = RegInit(pc_ini)\n val id_npc_temp: UInt = RegInit(npc_ini)\n val id_inst2_temp: UInt = RegInit(inst_nop)\n val id_pc2_temp: UInt = RegInit(pc_ini)\n val id_npc2_temp: UInt = RegInit(npc_ini)\n\n val valid_id_inst: Bool = valid_imem && io.r_imem_dat.ack\n val in_loadstore: Bool = RegInit(false.B)\n\n when(mem_ctrl.mem_wr =/= M_X) {\n in_loadstore := true.B\n }.elsewhen(imem_req){\n in_loadstore :=false.B\n }\n\n var temp_lock: Bool = RegInit(false.B)\n when(imem_req && io.r_imem_dat.ack){\n temp_lock := false.B\n }\n\n // when dmem start\n when(/*(stall || waitrequest) &&*/ !inst_kill && !imem_req && io.r_imem_dat.ack && !temp_lock){\n temp_lock := true.B\n id_pc_temp := if_pc //io.r_imem_dat.data\n id_npc_temp := if_npc\n id_inst_temp := io.r_imem_dat.data\n\n id_pc2_temp := id_pc //io.r_imem_dat.data\n id_npc2_temp := id_npc\n id_inst2_temp := id_inst\n\n id_pc := pc_ini\n id_npc := npc_ini\n id_inst := inst_nop\n\n }\n\n when((stall || waitrequest) && !inst_kill && valid_id_inst && imem_req && !temp_lock) {\n temp_lock := true.B\n id_pc_temp := if_pc //io.r_imem_dat.data\n id_npc_temp := if_npc\n id_inst_temp := io.r_imem_dat.data\n\n id_pc2_temp := id_pc//io.r_imem_dat.data\n id_npc2_temp := id_npc\n id_inst2_temp := id_inst\n\n }.elsewhen(valid_id_inst && !stall && !waitrequest && !inst_kill && imem_req) {\n id_pc := if_pc //pc_cntr\n id_npc := if_npc\n id_inst := io.r_imem_dat.data\n\n }.elsewhen(inst_kill && !waitrequest && imem_req) {\n id_pc := pc_ini\n id_npc := npc_ini\n id_inst := inst_nop\n // reset temp\n id_pc_temp := pc_ini\n id_npc_temp := npc_ini\n id_inst_temp := inst_nop\n id_pc2_temp := pc_ini\n id_npc2_temp := npc_ini\n id_inst2_temp := inst_nop\n //temp_lock := false.B\n }.elsewhen(/*!waitrequest &&*/ !inst_kill && !stall && !valid_id_inst && imem_req) {\n when(in_loadstore) {\n id_pc := id_pc2_temp\n id_npc := id_npc2_temp\n id_inst := id_inst2_temp\n\n // reset temp\n //id_pc_temp := pc_ini\n //id_npc_temp := npc_ini\n //id_inst_temp := inst_nop\n temp_lock := false.B\n\n }.elsewhen(!in_loadstore && !waitrequest) {\n when(id_pc2_temp === id_pc_temp && id_pc_temp =/= pc_ini) {\n id_pc := id_pc_temp + 4.U\n id_npc := id_npc_temp + 4.U\n id_inst := id_inst_temp\n }.otherwise{\n id_pc := id_pc_temp\n id_npc := id_npc_temp\n id_inst := id_inst_temp\n }\n\n // reset temp\n id_pc_temp := pc_ini\n id_npc_temp := npc_ini\n id_inst_temp := inst_nop\n\n id_pc2_temp := pc_ini\n id_npc2_temp := npc_ini\n id_inst2_temp := inst_nop\n }\n\n }/*.elsewhen(!imem_req){\n id_pc := pc_ini\n id_npc := npc_ini\n id_inst := inst_nop\n }*/.otherwise {\n id_pc := id_pc\n id_npc := id_npc\n id_inst := id_inst\n }\n\n val idm: IDModule = Module(new IDModule)\n idm.io.imem := id_inst\n\n // instruction decode\n val id_ctrl: IntCtrlSigs = Wire(new IntCtrlSigs).decode(idm.io.inst.bits, (new IDecode).table)\n\n // get rs1,rs2,rd address(x0 - x31)\n val id_raddr1: UInt = idm.io.inst.rs1\n val id_raddr2: UInt = idm.io.inst.rs2\n //val id_raddr: IndexedSeq[UInt] = IndexedSeq(id_raddr1, id_raddr2) // rs1,2 :treat as 64bit-Addressed SRAM\n val id_waddr: UInt = idm.io.inst.rd // rd\n val id_csr_addr: UInt = idm.io.inst.csr // csr address\n\n // read register data\n val rv32i_reg: Vec[UInt] = RegInit(VecInit(Seq.fill(32)(0.U(32.W)))) // x0 - x31:All zero initialized\n val id_rs1: UInt = Mux(id_raddr1 === 0.U, 0.U, rv32i_reg(id_raddr1))\n val id_rs2: UInt = Mux(id_raddr2 === 0.U, 0.U, rv32i_reg(id_raddr2))\n\n // program counter check\n val pc_invalid: Bool = inst_kill_branch || (ex_pc === pc_ini)\n\n // external interrupt signal\n val interrupt_sig: Bool = RegInit(false.B)\n interrupt_sig := io.sw.w_interrupt_sig\n\n val csr: CSR = Module(new CSR)\n // judge if stall needed\n //withClock(invClock) {\n stall := ((ex_reg_waddr === id_raddr1 || ex_reg_waddr === id_raddr2) &&\n ((mem_ctrl.mem_wr === M_XRD) || (ex_ctrl.mem_wr === M_XRD)) && (!inst_kill)) ||\n (id_raddr1 =/= 0.U && id_raddr1 === wb_reg_waddr) && (!inst_kill) ||\n (id_raddr2 =/= 0.U && id_raddr2 === wb_reg_waddr) && (!inst_kill) ||\n // (id_ctrl.mem_wr === M_XWR && ex_ctrl.mem_wr === M_XWR) && (!inst_kill) || // comment me\n (id_ctrl.br_type =/= BR_N && ex_ctrl.br_type =/= BR_N) && (!inst_kill) ||\n ((ex_ctrl.mem_wr =/= M_X) || (mem_ctrl.mem_wr =/= M_X)) && (id_ctrl.br_type =/= BR_N) && (!inst_kill) ||\n (delay_stall =/= 7.U) /*|| imem_wait || dmem_wait*/\n io.sw.r_stall_sig := ex_pc//ex_inst //stall\n //}\n\n // -------- END: ID stage --------\n\n\n // -------- START: EX Stage --------\n when(!stall && !inst_kill && !waitrequest && !loadstore_proc && !in_loadstore) {\n ex_pc := id_pc\n ex_npc := id_npc\n ex_ctrl := id_ctrl\n ex_inst := id_inst //idm.io.inst.bits\n ex_reg_raddr(0) := id_raddr1\n ex_reg_raddr(1) := id_raddr2\n ex_reg_waddr := id_waddr\n ex_rs(0) := id_rs1\n ex_rs(1) := id_rs2\n ex_csr_addr := id_csr_addr\n ex_csr_cmd := id_ctrl.csr_cmd\n ex_j_check := (id_ctrl.br_type === BR_J) || (id_ctrl.br_type === BR_JR)\n ex_b_check := (id_ctrl.br_type > 3.U)\n }.elsewhen((stall || inst_kill || loadstore_proc || in_loadstore) && !waitrequest) {\n ex_pc := pc_ini\n ex_npc := npc_ini\n ex_ctrl := nop_ctrl\n ex_inst := inst_nop\n ex_reg_raddr := VecInit(0.U, 0.U)\n ex_reg_waddr := 0.U\n ex_rs := VecInit(0.U, 0.U)\n ex_csr_addr := 0.U\n ex_csr_cmd := 0.U\n ex_j_check := false.B\n ex_b_check := false.B\n }\n\n val ex_imm: SInt = ImmGen(ex_ctrl.imm_type, ex_inst)\n // forwarding logic\n val ex_reg_rs1_bypass: UInt = Wire(UInt(32.W))\n val ex_reg_rs2_bypass: UInt = Wire(UInt(32.W))\n val ex_op1: UInt = Wire(UInt(32.W))\n val ex_op2: UInt = Wire(UInt(32.W))\n val alu: ALU = Module(new ALU)\n\n ex_reg_rs1_bypass := MuxCase(ex_rs(0), Seq(\n (ex_reg_raddr(0) =/= 0.U && ex_reg_raddr(0) === mem_reg_waddr && mem_ctrl.csr_cmd =/= CSR.N) -> mem_csr_data,\n (ex_reg_raddr(0) =/= 0.U && ex_reg_raddr(0) === mem_reg_waddr && mem_ctrl.rf_wen === REN_1) -> mem_alu_out,\n (ex_reg_raddr(0) =/= 0.U && ex_reg_raddr(0) === wb_reg_waddr && wb_ctrl.rf_wen === REN_1 && wb_ctrl.mem_en === MEN_1 && wb_ctrl.csr_cmd === CSR.N) -> io.r_dmem_dat.data,\n (ex_reg_raddr(0) =/= 0.U && ex_reg_raddr(0) === wb_reg_waddr && wb_ctrl.rf_wen === REN_1 && wb_ctrl.mem_en === MEN_0 && wb_ctrl.csr_cmd === CSR.N) -> wb_alu_out,\n //(ex_reg_raddr(0) =/= 0.U && ex_reg_raddr(0) === wb_reg_waddr && ex_ctrl.rf_wen === REN_0 && ex_ctrl.mem_en === MEN_1) -> wb_alu_out,\n (ex_reg_raddr(0) =/= 0.U && ex_reg_raddr(0) === wb_reg_waddr && wb_ctrl.rf_wen === REN_1 && wb_ctrl.csr_cmd =/= CSR.N) -> wb_csr_data\n ))\n ex_reg_rs2_bypass := MuxCase(ex_rs(1), Seq(\n (ex_reg_raddr(1) =/= 0.U && ex_reg_raddr(1) === mem_reg_waddr && mem_ctrl.csr_cmd =/= CSR.N) -> mem_csr_data,\n (ex_reg_raddr(1) =/= 0.U && ex_reg_raddr(1) === mem_reg_waddr && mem_ctrl.rf_wen === REN_1) -> mem_alu_out,\n (ex_reg_raddr(1) =/= 0.U && ex_reg_raddr(1) === wb_reg_waddr && wb_ctrl.rf_wen === REN_1 && wb_ctrl.mem_en === MEN_1 && wb_ctrl.csr_cmd === CSR.N) -> io.r_dmem_dat.data,\n (ex_reg_raddr(1) =/= 0.U && ex_reg_raddr(1) === wb_reg_waddr && wb_ctrl.rf_wen === REN_1 && wb_ctrl.mem_en === MEN_0 && wb_ctrl.csr_cmd === CSR.N) -> wb_alu_out,\n //(ex_reg_raddr(1) =/= 0.U && ex_reg_raddr(1) === wb_reg_waddr && ex_ctrl.rf_wen === REN_0 && ex_ctrl.mem_en === MEN_1) -> wb_alu_out,\n (ex_reg_raddr(1) =/= 0.U && ex_reg_raddr(1) === wb_reg_waddr && wb_ctrl.rf_wen === REN_1 && wb_ctrl.csr_cmd =/= CSR.N) -> wb_csr_data\n ))\n\n // ALU OP1 selector\n ex_op1 := MuxCase(0.U(32.W), Seq(\n (ex_ctrl.alu_op1 === OP1_RS1) -> ex_reg_rs1_bypass,\n (ex_ctrl.alu_op1 === OP1_PC) -> ex_pc, //(ex_pc - 4.U), // PC = pc_cntr-4.U\n (ex_ctrl.alu_op1 === OP1_X) -> 0.U(32.W)\n ))\n // ALU OP2 selector\n ex_op2 := MuxCase(0.U(32.W), Seq(\n (ex_ctrl.alu_op2 === OP2_RS2) -> ex_reg_rs2_bypass,\n (ex_ctrl.alu_op2 === OP2_IMM) -> ex_imm.asUInt, // IMM\n (ex_ctrl.alu_op2 === OP2_X) -> 0.U(32.W)\n ))\n\n\n // ALU\n alu.io.alu_op := ex_ctrl.alu_func\n alu.io.op1 := ex_op1\n alu.io.op2 := ex_op2\n\n // CSR\n val csr_in: UInt = Mux(ex_ctrl.imm_type === IMM_Z, ex_imm.asUInt(),\n Mux(ex_reg_raddr(0) === mem_reg_waddr, Mux(mem_ctrl.csr_cmd =/= CSR.N, mem_csr_data, mem_alu_out), // todo: mem_alu_out -> (mem_)rf_wdata\n Mux(ex_reg_raddr(0) === wb_reg_waddr, Mux(wb_ctrl.csr_cmd =/= CSR.N, wb_csr_data, wb_alu_out), // todo: wb_alu_out -> (wb_)rf_wdata\n ex_reg_rs1_bypass.asUInt())\n )\n )\n\n //val csr_in: UInt = Mux(ex_ctrl.imm_type === IMM_Z, ex_imm.asUInt(),ex_reg_rs1_bypass)\n csr.io.pc := ex_pc\n csr.io.addr := ex_csr_addr\n csr.io.cmd := ex_csr_cmd\n csr.io.in := csr_in\n csr.io.inst := ex_inst\n csr.io.mem_wr := ex_ctrl.mem_wr\n csr.io.mask_type := ex_ctrl.mask_type\n csr.io.alu_op1 := ex_op1\n csr.io.alu_op2 := ex_op2\n csr.io.legal := (ex_ctrl.legal === true.B)\n csr.io.rs1_addr := ex_inst(19, 15) //ex_rs(0)\n csr.io.stall := stall\n csr.io.pc_invalid := pc_invalid\n csr.io.j_check := ex_j_check\n csr.io.b_check := ex_b_check\n csr.io.interrupt_sig := interrupt_sig\n //csr_stall ((ex_reg_waddr === id_raddr(0) || ex_reg_waddr === id_raddr(1)) && (ex_ctrl.csr_cmd =/= CSR.N)) && !csr.io.expt\n\n // iotesters\n io.sw.r_ex_raddr1 := ex_reg_raddr(0)\n io.sw.r_ex_raddr2 := ex_reg_raddr(1)\n io.sw.r_ex_rs1 := ex_reg_rs1_bypass //ex_rs(0)\n io.sw.r_ex_rs2 := ex_reg_rs2_bypass //ex_rs(1)\n io.sw.r_ex_imm := ex_imm.asUInt\n // -------- END: EX Stage --------\n\n // -------- START: MEM Stage --------\n when(!inst_kill && !waitrequest) {\n mem_pc := ex_pc\n mem_npc := ex_npc\n mem_ctrl := ex_ctrl\n mem_reg_waddr := ex_reg_waddr\n mem_imm := ex_imm\n mem_rs(0) := ex_reg_rs1_bypass\n mem_rs(1) := ex_reg_rs2_bypass\n mem_alu_out := alu.io.out\n mem_alu_cmp_out := alu.io.cmp_out\n mem_csr_addr := ex_csr_addr\n mem_csr_data := csr.io.out\n\n }.elsewhen(inst_kill && !waitrequest) {\n mem_pc := pc_ini\n mem_npc := npc_ini\n mem_ctrl := nop_ctrl\n mem_reg_waddr := 0.U\n mem_imm := 0.S\n mem_rs := VecInit(0.U, 0.U)\n mem_alu_out := 0.U\n mem_alu_cmp_out := false.B\n mem_csr_addr := 0.U\n mem_csr_data := 0.U\n }\n\n // iotesters\n io.sw.r_mem_alu_out := mem_alu_out\n\n //dmem connection\n when(io.sw.halt === false.B) { // CPU active\n //io.w_dmem_add.addr := mem_alu_out\n io.dmem_add.addr := mem_alu_out\n io.w_dmem_dat.req := (mem_ctrl.mem_wr === M_XWR)\n io.w_dmem_dat.data := DontCare\n io.r_dmem_dat.req := (mem_ctrl.mem_wr === M_XRD)\n\n }.otherwise { // CPU halt\n // dmem connection\n io.dmem_add.addr := io.sw.w_add\n io.w_dmem_dat.data := io.sw.w_dat\n io.w_dmem_dat.req := true.B\n io.w_dmem_dat.byteenable := 15.U\n //io.r_dmem_add.addr := 0.U\n io.r_dmem_dat.req := false.B\n\n }\n\n // send bus write size\n io.w_dmem_dat.byteenable := DontCare\n // mem_rs(1)\n when(mem_ctrl.mem_wr === M_XWR) {\n when(mem_ctrl.mask_type === MT_B) { // byte write\n switch(mem_alu_out(1, 0)) {\n is(\"b00\".U) {\n io.w_dmem_dat.byteenable := \"b0001\".U\n io.w_dmem_dat.data := mem_rs(1)\n }\n is(\"b01\".U) {\n io.w_dmem_dat.byteenable := \"b0010\".U\n io.w_dmem_dat.data := mem_rs(1) << 8.U\n }\n is(\"b10\".U) {\n io.w_dmem_dat.byteenable := \"b0100\".U\n io.w_dmem_dat.data := mem_rs(1) << 16.U\n }\n is(\"b11\".U) {\n io.w_dmem_dat.byteenable := \"b1000\".U\n io.w_dmem_dat.data := mem_rs(1) << 24.U\n }\n }\n }.elsewhen(mem_ctrl.mask_type === MT_H) {\n switch(mem_alu_out(1, 0)) {\n is(\"b00\".U) {\n io.w_dmem_dat.byteenable := \"b0011\".U\n io.w_dmem_dat.data := mem_rs(1)\n }\n is(\"b10\".U) {\n io.w_dmem_dat.byteenable := \"b1100\".U\n io.w_dmem_dat.data := (mem_rs(1) << 16.U)\n }\n }\n }.otherwise { // MT_W\n io.w_dmem_dat.byteenable := \"b1111\".U\n io.w_dmem_dat.data := mem_rs(1)\n }\n }.otherwise {\n io.w_dmem_dat.byteenable := 15.U\n }\n\n // bubble logic\n inst_kill_branch := (\n ((mem_ctrl.br_type > 3.U) && mem_alu_cmp_out) || // branch\n (mem_ctrl.br_type === BR_JR) || // jalr\n (mem_ctrl.br_type === BR_J) || // jal\n (mem_ctrl.br_type === BR_RET) // mret / sret\n )\n inst_kill := (inst_kill_branch || csr.io.expt)\n // -------- END: MEM Stage --------\n\n // -------- START: WB Stage --------\n when(!waitrequest) {\n wb_npc := mem_npc\n wb_ctrl := mem_ctrl\n wb_reg_waddr := mem_reg_waddr\n wb_alu_out := mem_alu_out\n wb_dmem_read_ack := io.r_dmem_dat.ack\n wb_csr_addr := mem_csr_addr\n wb_csr_data := mem_csr_data\n }\n val dmem_data: UInt = Wire(UInt(32.W))\n dmem_data := DontCare\n\n when(wb_ctrl.mem_wr === M_XRD) {\n when(wb_ctrl.mask_type === MT_B) { // byte read\n switch(wb_alu_out(1, 0)) {\n is(\"b00\".U) {\n dmem_data := Cat(Fill(24, io.r_dmem_dat.data(7)), io.r_dmem_dat.data(7, 0))\n }\n is(\"b01\".U) {\n dmem_data := Cat(Fill(24, io.r_dmem_dat.data(15)), io.r_dmem_dat.data(15, 8))\n }\n is(\"b10\".U) {\n dmem_data := Cat(Fill(24, io.r_dmem_dat.data(23)), io.r_dmem_dat.data(23, 16))\n }\n is(\"b11\".U) {\n dmem_data := Cat(Fill(24, io.r_dmem_dat.data(31)), io.r_dmem_dat.data(31, 24))\n }\n }\n }.elsewhen(wb_ctrl.mask_type === MT_BU) { // byte read unsigned\n switch(wb_alu_out(1, 0)) {\n is(\"b00\".U) {\n dmem_data := Cat(0.U(24.W), io.r_dmem_dat.data(7, 0))\n }\n is(\"b01\".U) {\n dmem_data := Cat(0.U(24.W), io.r_dmem_dat.data(15, 8))\n }\n is(\"b10\".U) {\n dmem_data := Cat(0.U(24.W), io.r_dmem_dat.data(23, 16))\n }\n is(\"b11\".U) {\n dmem_data := Cat(0.U(24.W), io.r_dmem_dat.data(31, 24))\n }\n }\n }.elsewhen(wb_ctrl.mask_type === MT_H) {\n switch(wb_alu_out(1, 0)) {\n is(\"b00\".U) {\n dmem_data := Cat(Fill(16, io.r_dmem_dat.data(15)), io.r_dmem_dat.data(15, 0))\n }\n is(\"b10\".U) {\n dmem_data := Cat(Fill(16, io.r_dmem_dat.data(31)), io.r_dmem_dat.data(31, 16))\n }\n // others\n is(\"b01\".U) {\n dmem_data := 0.U\n }\n is(\"b11\".U) {\n dmem_data := 0.U\n }\n }\n }.elsewhen(wb_ctrl.mask_type === MT_HU) {\n switch(wb_alu_out(1, 0)) {\n is(\"b00\".U) {\n dmem_data := Cat(0.U(16.W), io.r_dmem_dat.data(15, 0))\n }\n is(\"b10\".U) {\n dmem_data := Cat(0.U(16.W), io.r_dmem_dat.data(31, 16))\n }\n // others\n is(\"b01\".U) {\n dmem_data := 0.U\n }\n is(\"b11\".U) {\n dmem_data := 0.U\n }\n }\n }.otherwise {\n dmem_data := io.r_dmem_dat.data\n }\n }.otherwise {\n dmem_data := io.r_dmem_dat.data\n }\n\n val rf_wen: Bool = wb_ctrl.rf_wen // register write enable flag\n val rf_waddr: UInt = wb_reg_waddr\n val rf_wdata: UInt = MuxCase(wb_alu_out, Seq(\n (wb_ctrl.wb_sel === WB_ALU) -> wb_alu_out, // wb_alu_out,\n (wb_ctrl.wb_sel === WB_PC4) -> wb_npc, // pc_cntr = pc + 4\n (wb_ctrl.wb_sel === WB_CSR) -> wb_csr_data,\n (wb_ctrl.wb_sel === WB_MEM) -> dmem_data //0.U(32.W),\n ))\n\n withClock(invClock) {\n when(rf_wen === REN_1) {\n when(rf_waddr > 0.U && rf_waddr < 32.U) {\n rv32i_reg(rf_waddr) := rf_wdata\n }\n }\n\n // iotesters\n io.sw.r_wb_alu_out := wb_alu_out\n io.sw.r_wb_rf_waddr := rf_waddr\n io.sw.r_wb_rf_wdata := rf_wdata\n }\n // -------- END: WB Stage --------\n\n\n // -------- START: PC update --------\n when(io.sw.halt === false.B) {\n w_req := false.B\n when(!stall && !waitrequest && imem_req) {\n pc_cntr := Mux(csr.io.expt, csr.io.evec,\n Mux(mem_ctrl.br_type === BR_RET, csr.io.epc,\n Mux((mem_ctrl.br_type > 3.U) && mem_alu_cmp_out, mem_pc + mem_imm.asUInt,\n Mux(mem_ctrl.br_type === BR_J, mem_alu_out,\n Mux(mem_ctrl.br_type === BR_JR, mem_alu_out, npc)\n ))))\n }\n }.otherwise { // halt mode\n // enable imem Write Operation\n w_addr := io.sw.w_add //w_addr + 4.U(32.W)\n w_data := io.sw.w_dat\n w_req := true.B\n pc_cntr := io.sw.w_pc\n }\n\n // for imem test\n io.sw.r_dat := id_inst//io.r_imem_dat.data\n io.sw.r_add := pc_cntr\n io.sw.r_pc := id_pc//pc_cntr // program counter\n\n\n // address update\n when(w_req){ // write request\n io.imem_add.addr := w_addr\n }.otherwise{\n io.imem_add.addr := pc_cntr\n }\n\n // write process\n io.w_imem_dat.data := w_data\n io.w_imem_dat.req := w_req\n io.w_imem_dat.byteenable := 15.U\n\n // read process\n //r_ack := io.r_imem_dat.ack\n //r_data := io.r_imem_dat.data\n\n // x0 - x31\n when (io.sw.halt === true.B){\n io.sw.g_dat := rv32i_reg(io.sw.g_add)\n }.otherwise{\n io.sw.g_dat := 0.U\n }\n}\n\nclass CpuBus extends Module {\n val io: TestIf = IO(new TestIf)\n\n val sw_halt: Bool = RegInit(true.B) // input\n val sw_data: UInt = RegInit(0.U(32.W)) // output\n val sw_addr: UInt = RegInit(0.U(32.W)) // output\n val sw_rw: Bool = RegInit(false.B) // input\n val sw_wdata: UInt = RegInit(0.U(32.W)) // input\n val sw_waddr: UInt = RegInit(0.U(32.W)) // input\n\n val w_pc: UInt = RegInit(0.U(32.W))\n\n val sw_gaddr: UInt = RegInit(0.U(32.W)) // general reg.(x0 to x31)\n\n val cpu: KyogenRVCpu = Module(new KyogenRVCpu)\n val imem: IMem = Module(new IMem)\n val dmem: DMem = Module(new DMem)\n\n // Connect Test Module\n sw_halt := io.sw.halt\n sw_data := imem.io.r_imem_dat.data\n sw_addr := imem.io.imem_add.addr\n\n // imem\n sw_wdata := io.sw.w_dat // data to write imem\n sw_waddr := io.sw.w_add\n sw_gaddr := io.sw.g_add\n io.sw.r_dat := sw_data\n io.sw.r_add := sw_addr\n\n // dmem\n // io.sw.r_dadd := cpu.io.sw.r_dadd\n // io.sw.r_ddat := cpu.io.sw.r_ddat\n\n io.sw.g_dat <> cpu.io.sw.g_dat\n io.sw.r_pc <> cpu.io.sw.r_pc\n\n // IOTESTERS: EX Stage\n io.sw.r_ex_raddr1 <> cpu.io.sw.r_ex_raddr1\n io.sw.r_ex_raddr2 <> cpu.io.sw.r_ex_raddr2\n io.sw.r_ex_rs1 <> cpu.io.sw.r_ex_rs1\n io.sw.r_ex_rs2 <> cpu.io.sw.r_ex_rs2\n io.sw.r_ex_imm <> cpu.io.sw.r_ex_imm\n\n //IOTESTERS: MEM Stage\n io.sw.r_mem_alu_out <> cpu.io.sw.r_mem_alu_out\n\n //IOTESTERS: WB Stage\n io.sw.r_wb_alu_out <> cpu.io.sw.r_wb_alu_out\n io.sw.r_wb_rf_wdata <> cpu.io.sw.r_wb_rf_wdata\n io.sw.r_wb_rf_waddr <> cpu.io.sw.r_wb_rf_waddr\n\n //IOTESTERS: STALL\n io.sw.r_stall_sig <> cpu.io.sw.r_stall_sig\n\n //IOTESTERS: External Interrupt Signal\n cpu.io.sw.w_interrupt_sig <> io.sw.w_interrupt_sig\n\n // WAITREQUEST\n cpu.io.sw.w_waitrequest_sig <> io.sw.w_waitrequest_sig\n cpu.io.sw.w_datawaitreq_sig <> io.sw.w_datawaitreq_sig\n w_pc := io.sw.w_pc\n\n cpu.io.sw.halt <> sw_halt\n cpu.io.sw.w_dat <> sw_wdata\n cpu.io.sw.w_add <> sw_waddr\n cpu.io.sw.g_add <> sw_gaddr\n cpu.io.sw.w_pc := w_pc\n\n\n // imem address connection\n imem.io.imem_add.addr <> cpu.io.imem_add.addr\n\n // Read imem\n imem.io.r_imem_dat.req <> cpu.io.r_imem_dat.req\n cpu.io.r_imem_dat.data <> imem.io.r_imem_dat.data\n cpu.io.r_imem_dat.ack <> imem.io.r_imem_dat.ack\n\n // write imem\n imem.io.w_imem_dat.req <> cpu.io.w_imem_dat.req\n imem.io.w_imem_dat.data <> cpu.io.w_imem_dat.data\n cpu.io.w_imem_dat.ack <> imem.io.w_imem_dat.ack\n cpu.io.w_imem_dat.byteenable <> imem.io.w_imem_dat.byteenable\n\n // Read dmem\n dmem.io.r_dmem_dat.req <> cpu.io.r_dmem_dat.req\n dmem.io.dmem_add.addr <> cpu.io.dmem_add.addr\n cpu.io.r_dmem_dat.data <> dmem.io.r_dmem_dat.data\n cpu.io.r_dmem_dat.ack <> dmem.io.r_dmem_dat.ack\n\n // write dmem\n dmem.io.w_dmem_dat.req <> cpu.io.w_dmem_dat.req\n dmem.io.w_dmem_dat.data <> cpu.io.w_dmem_dat.data\n cpu.io.w_dmem_dat.ack <> dmem.io.w_dmem_dat.ack\n cpu.io.w_dmem_dat.byteenable <> dmem.io.w_dmem_dat.byteenable\n\n}\n\n//noinspection ScalaStyle\nobject kyogenrv extends App {\n val name = \"KyogenRVCpu\"\n\n (new stage.ChiselStage).execute(\n Array(\"-td=fpga/chisel_generated\", s\"-o=$name\"),\n Seq(chisel3.stage.ChiselGeneratorAnnotation(\n () => new KyogenRVCpu())))\n}\n\nobject Test extends App {\n iotesters.Driver.execute(args, () => new CpuBus())(testerGen = c => {\n new PeekPokeTester(c) {\n // read from binary file\n val s: BufferedSource = Source.fromFile(\"src/sw/test.hex\")\n var buffs: Array[String] = _\n try {\n buffs = s.getLines.toArray\n } finally {\n s.close()\n }\n step(1)\n poke(signal = c.io.sw.halt, value = true.B)\n poke(c.io.sw.w_waitrequest_sig, false.B)\n poke(c.io.sw.w_datawaitreq_sig, false.B)\n step(1)\n\n for (addr <- 0 until buffs.length * 4 by 4) {\n val mem_val = buffs(addr / 4).replace(\" \", \"\")\n val mem = Integer.parseUnsignedInt(mem_val, 16)\n\n poke(signal = c.io.sw.w_add, value = addr)\n step(1)\n poke(signal = c.io.sw.w_dat, value = mem)\n println(msg = f\"write: addr = 0x$addr%04X,\\tdata = 0x$mem%08X\")\n step(1)\n }\n\n step(1)\n println(msg = \"---------------------------------------------------------\")\n poke(signal = c.io.sw.w_pc, value = 0) // restart pc address\n step(1) // fetch pc\n poke(c.io.sw.w_waitrequest_sig, value = true.B) // after reset, waitrequest = 1\n poke(signal = c.io.sw.halt, value = false.B)\n step(2)\n println(msg = f\"count\\tINST\\t\\t| EX STAGE:rs1 ,\\t\\t\\trs2 ,\\t\\timm\\t\\t\\t| MEM:ALU out\\t| WB:ALU out, rd\\t\\t\\t\\tstall\")\n\n // external interrupt signal(true = rising edge, false = off)\n poke(signal = c.io.sw.w_interrupt_sig, value = false.B)\n\n // about 1000 cycle, we can finish 'riscv-tests'.\n // change parameters on your another projects.\n for (lp <- 0 until 1000 by 1) {\n val a = peek(signal = c.io.sw.r_pc) // pc count\n val d = peek(signal = c.io.sw.r_dat) // instruction\n val exraddr1 = peek(c.io.sw.r_ex_raddr1) // rs1 address\n val exraddr2 = peek(c.io.sw.r_ex_raddr2) // rs2 address\n val exrs1 = peek(c.io.sw.r_ex_rs1) // rs1 data\n val exrs2 = peek(c.io.sw.r_ex_rs2) // rs2 data\n val eximm = peek(c.io.sw.r_ex_imm) // imm\n val memaluo = peek(c.io.sw.r_mem_alu_out) // alu(MEM stage)\n val wbaluo = peek(c.io.sw.r_wb_alu_out) // alu(WB stage)\n val wbaddr = peek(c.io.sw.r_wb_rf_waddr) // write-back rd address\n val wbdata = peek(c.io.sw.r_wb_rf_wdata) // write-back rd data\n val stallsig = peek(c.io.sw.r_stall_sig) // stall signal\n if(lp > 3){\n poke(c.io.sw.w_waitrequest_sig, value = false.B)\n }\n if(lp == 16){\n poke(c.io.sw.w_waitrequest_sig, value = true.B)\n }\n\n // if you need fire external interrupt signal uncomment below\n if(lp == 98 || lp == 99){\n poke(signal = c.io.sw.w_interrupt_sig, value = true.B)\n }\n else{\n poke(signal = c.io.sw.w_interrupt_sig, value = false.B)\n }\n\n step(1)\n println(msg = f\"0x$a%04X,\\t0x$d%08X\\t| x($exraddr1)=>0x$exrs1%08X, x($exraddr2)=>0x$exrs2%08X,\\t0x$eximm%08X\\t| 0x$memaluo%08X\\t| 0x$wbaluo%08X, x($wbaddr%d)\\t<= 0x$wbdata%08X, $stallsig%x\") //peek(c.io.sw.data)\n\n }\n step(1)\n println(\"---------------------------------------------------------\")\n\n poke(signal = c.io.sw.halt, value = true.B)\n step(2)\n for (lp <- 0.U(32.W) to 31.U(32.W) by 1) {\n\n poke(signal = c.io.sw.g_add, value = lp)\n step(1)\n val d = {\n peek(signal = c.io.sw.g_dat)\n }\n\n step(1)\n println(msg = f\"read : x$lp%2d = 0x$d%08X \") //peek(c.io.sw.data)\n }\n }\n })\n}", "groundtruth": " def risingEdge(x: Bool): Bool = x && !RegNext(x)\n", "crossfile_context": "", "category": "Storage Block", "subcategory": "Register-based Storage", "confidence": 0.85, "category_reason": "RegNext register"} {"task_id": "KyogenRV", "path": "KyogenRV/src/main/scala/core/csr.scala", "left_context": "// See README.md for license details.\n/*\n* BSD 3-Clause License\n\nCopyright (c) 2017, The Regents of the University of California (Regents)\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n* Redistributions of source code must retain the above copyright notice, this\n list of conditions and the following disclaimer.\n\n* Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n* Neither the name of the Regents nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\nFOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\nDAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\nSERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\nCAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\nOR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\nOF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n* */\n\npackage core\n\nimport chisel3._\nimport chisel3.internal.firrtl.Width\nimport chisel3.util._\n\nimport scala.collection.immutable._\nimport MemoryOpConstants._\n\nobject CSR {\n // commands\n val SZ: Width = 3.W\n val N: UInt = 0.U(SZ)\n val W: UInt = 1.U(SZ)\n val S: UInt = 2.U(SZ)\n val C: UInt = 3.U(SZ)\n val P: UInt = 4.U(SZ)\n\n}\n\n\nobject PRIV {\n val SZ: Width = 2.W\n val U: UInt = 0.U(SZ) // User Mode\n val S: UInt = 1.U(SZ) // SV mode\n val H: UInt = 2.U(SZ) // Reserved (ex-\"HV mode\")\n val M: UInt = 3.U(SZ) // Machine Mode\n}\n\nobject CsrAddr {\n val SZ: Width = 12.W\n // User-level\n val cycle: UInt = 0xc00.U(SZ)\n val time: UInt = 0xc01.U(SZ)\n val instret: UInt = 0xc02.U(SZ)\n val cycleh: UInt = 0xc80.U(SZ)\n val timeh: UInt = 0xc81.U(SZ)\n val instreth: UInt = 0xc82.U(SZ)\n\n // Supervisor-level\n val satp: UInt = 0x180.U(SZ)\n val cyclew: UInt = 0x900.U(SZ)\n val timew: UInt = 0x901.U(SZ)\n val instretw: UInt = 0x902.U(SZ)\n val cyclehw: UInt = 0x980.U(SZ)\n val timehw: UInt = 0x981.U(SZ)\n val instrethw: UInt = 0x982.U(SZ)\n \n // Machine-level\n // Infomation reg\n val mcpuid: UInt = 0xf00.U(SZ)\n val mvendorid: UInt = 0xf11.U(SZ)\n val marchid: UInt = 0xf12.U(SZ)\n val mimpid: UInt = 0xf13.U(SZ)\n val mhartid: UInt = 0xf14.U(SZ)\n \n // Machine Trap Setup\n val mstatus: UInt = 0x300.U(SZ)\n val misa: UInt = 0x301.U(SZ)\n val medeleg: UInt = 0x302.U(SZ)\n val mideleg: UInt = 0x303.U(SZ)\n val mie: UInt = 0x304.U(SZ)\n val mtvec: UInt = 0x305.U(SZ)\n\n val mtimecmp: UInt = 0x321.U(SZ)\n //val mtval: UInt = 0x343.U(SZ)\n \n // Timers and Counters\n val mtime: UInt = 0x701.U(SZ)\n val mtimeh: UInt = 0x741.U(SZ)\n // Machine Trap Handling\n val mscratch: UInt = 0x340.U(SZ)\n val mepc: UInt = 0x341.U(SZ)\n val mcause: UInt = 0x342.U(SZ)\n val mtval: UInt = 0x343.U(SZ)\n val mip: UInt = 0x344.U(SZ)\n\n // HITF\n val mtohost: UInt = 0x780.U(SZ)\n val mfromhost: UInt = 0x781.U(SZ)\n\n val regs: Seq[UInt] = List(\n cycle, time, instret, cycleh, timeh, instreth,\n satp, cyclew, timew, instretw, cyclehw, timehw, instrethw,\n mcpuid, mimpid, mhartid, mtvec, medeleg, mie,\n mtimecmp, mtime, mtimeh, mscratch, mepc, mcause, mtval, mip,\n mtohost, mfromhost, mstatus\n )\n}\n\n// CAUSES\nobject Cause {\n val InstAddrMisaligned: UInt = 0.U\n val IllegalInst: UInt = 2.U\n val Breakpoint: UInt = 3.U\n val LoadAddrMisaligned: UInt = 4.U\n val StoreAddrMisaligned: UInt = 6.U\n val Ecall: UInt = 8.U\n val ExtInterrupt: UInt = 8.U\n}\n\nclass CsrIO extends Bundle {\n\n val addr: UInt = Input(UInt(32.W)) // csr_addr\n val in: UInt = Input(UInt(32.W)) // rs1 or imm_z\n val out: UInt = Output(UInt(32.W)) // csrdata -> rd\n val cmd: UInt = Input(UInt(32.W)) // csr_cmd\n val rs1_addr: UInt = Input(UInt(32.W)) // rs1 addr\n val legal: Bool = Input(Bool()) // illegal instruction = !(legal)\n\n\n // Excpetion\n val interrupt_sig: Bool = Input(Bool())\n val pc: UInt = Input(UInt(32.W))\n val pc_invalid: Bool = Input(Bool()) // stall || inst_kill_branch || pc === 0.U\n val j_check: Bool = Input(Bool()) // jump check\n val b_check: Bool = Input(Bool()) // branch check\n val stall: Bool = Input(Bool())\n val expt: Bool = Output(Bool())\n val evec: UInt = Output(UInt(32.W))\n val epc: UInt = Output(UInt(32.W))\n val inst: UInt = Input(UInt(32.W)) // RV32I instruction\n val mem_wr: UInt = Input(UInt(M_SZ)) // load/store type\n val mask_type: UInt = Input(UInt(MT_SZ)) // load/store mask type\n val alu_op1: UInt = Input(UInt(32.W))\n val alu_op2: UInt = Input(UInt(32.W))\n}\n\nclass CSR extends Module {\n val io: CsrIO = IO(new CsrIO)\n\n // variables\n val wdata: UInt = MuxLookup(io.cmd, 0.U, Seq(\n CSR.W -> io.in,\n CSR.S -> (io.out | io.in),\n CSR.C -> (io.out.asUInt() & (~io.in).asUInt())\n ))\n val csr_addr: UInt = io.addr\n val rs1_addr: UInt = io.rs1_addr\n val alu_calc_addr: UInt = (io.alu_op1 + io.alu_op2).asUInt()\n\n // user counters\n val time: UInt = RegInit(0.U(32.W))\n val timeh: UInt = RegInit(0.U(32.W))\n val cycle: UInt = RegInit(0.U(32.W))\n val cycleh: UInt = RegInit(0.U(32.W))\n val instret: UInt = RegInit(0.U(32.W))\n val instreth: UInt = RegInit(0.U(32.W))\n val mcpuid: UInt = Cat(0.U(2.W) /* RV32I */, 0.U((32-28).W),\n (1 << ('I' - 'A') /* Base ISA */|\n 1 << ('U' - 'A') /* User Mode */).U(26.W))\n val mimpid: UInt = 0.U(32.W) // not implemented\n val mhartid: UInt = 0.U(32.W) // only one hart\n \n // interrupt enable stack\n val PRV: UInt = RegInit(PRIV.M)\n val PRV1: UInt = RegInit(PRIV.M)\n val PRV2: UInt = 0.U(2.W)\n val PRV3: UInt = 0.U(2.W)\n val IE: Bool = RegInit(false.B)\n val IE1: Bool = RegInit(false.B)\n val IE2: Bool = false.B\n val IE3: Bool = false.B\n\n // virtualization management field\n val VM: UInt = 0.U(5.W)\n\n // memory privilege\n val MPRV: Bool = false.B\n\n // extention context status\n val XS: UInt = 0.U(2.W)\n val FS: UInt = 0.U(2.W)\n val SD: UInt = 0.U(1.W)\n val mstatus: UInt = Cat(SD, 0.U((32-23).W), VM, MPRV, XS, FS, PRV3, IE3, PRV2, IE2, PRV1, IE1, PRV, IE)\n val mtvec: UInt = RegInit(PC_INITS.PC_EVEC.U(32.W)) // see constant.scala\n val medeleg: UInt = 0x0.U(32.W)\n \n // interrupt registers\n val MTIP: Bool = RegInit(false.B)\n val HTIP: Bool = false.B\n val STIP: Bool = false.B\n\n val MEIE: Bool = RegInit(false.B)\n val MTIE: Bool = RegInit(false.B)\n val HTIE: Bool = false.B\n val STIE: Bool = false.B\n\n val MEIP: Bool = RegInit(false.B)\n val MSIP: Bool = RegInit(false.B)\n val HSIP: Bool = false.B\n val SSIP: Bool = false.B\n val MSIE: Bool = RegInit(false.B)\n val HSIE: Bool = false.B\n val SSIE: Bool = false.B\n val mip: UInt = Cat(0.U((32-12).W), MEIP, false.B, false.B, false.B,MTIP, HTIP, STIP, false.B, MSIP, HSIP, SSIP, false.B)\n val mie: UInt = Cat(0.U((32-12).W), MEIE, false.B, false.B, false.B, MTIE, HTIE, STIE, false.B, MSIE, HSIE, SSIE, false.B)\n \n val mtimecmp: UInt = Reg(UInt(32.W))\n val mscratch: UInt = Reg(UInt(32.W))\n \n val mepc: UInt = Reg(UInt(32.W))\n val mcause: UInt = Reg(UInt(32.W))\n \n val mtohost: UInt = RegInit(0.U(32.W))\n val mfromhost: UInt = Reg(UInt(32.W))\n val satp: UInt = RegInit(0.U(32.W))\n val misa: UInt = RegInit(0x40000000L.U(32.W))\n val mtval: UInt = RegInit(Instructions.NOP)\n\n // count if pc is valid\n val valid_pc: UInt = RegInit(0.U(32.W))\n\n val csrFile: Seq[(BitPat, UInt)] = Seq(\n BitPat(CsrAddr.cycle) -> cycle,\n BitPat(CsrAddr.time) -> time,\n BitPat(CsrAddr.instret) -> instret,\n BitPat(CsrAddr.cycleh) -> cycleh,\n BitPat(CsrAddr.timeh) -> timeh,\n BitPat(CsrAddr.instreth) -> instreth,\n BitPat(CsrAddr.cyclew) -> cycle,\n BitPat(CsrAddr.satp) -> satp,\n BitPat(CsrAddr.timew) -> time,\n BitPat(CsrAddr.instretw) -> instret,\n BitPat(CsrAddr.cyclehw) -> cycleh,\n BitPat(CsrAddr.timehw) -> timeh,\n BitPat(CsrAddr.instrethw) -> instreth,\n BitPat(CsrAddr.mcpuid) -> mcpuid,\n BitPat(CsrAddr.mimpid) -> mimpid,\n BitPat(CsrAddr.mhartid) -> mhartid,\n BitPat(CsrAddr.mtvec) -> mtvec,\n BitPat(CsrAddr.medeleg) -> medeleg,\n BitPat(CsrAddr.mie) -> mie,\n BitPat(CsrAddr.mtimecmp) -> mtimecmp,\n BitPat(CsrAddr.mtime) -> time,\n BitPat(CsrAddr.mtimeh) -> timeh,\n BitPat(CsrAddr.mscratch) -> mscratch,\n BitPat(CsrAddr.mepc) -> mepc,\n BitPat(CsrAddr.mcause) -> mcause,\n BitPat(CsrAddr.mip) -> mip,\n BitPat(CsrAddr.mstatus) -> mstatus,\n BitPat(CsrAddr.misa) -> misa,\n BitPat(CsrAddr.mtval) -> mtval\n )\n\n io.out := Lookup(io.addr, 0.U, csrFile).asUInt()\n\n // Counters\n time := time + 1.U\n", "right_context": " cycle := cycle + 1.U\n when(cycle.andR) { cycleh := cycleh + 1.U }\n\n MEIP := io.interrupt_sig // true => external interrupt\n\n //noinspection ScalaStyle\n val privValid: Bool = csr_addr(9, 8) <= PRV\n val privInst: Bool = io.cmd === CSR.P\n //val isTimerInt: Bool = MTIE && MTIP\n val isExtInt: Bool = MEIP && MEIE\n val isEcall: Bool = privInst && !csr_addr(0) && !csr_addr(8)\n val isEbreak: Bool = privInst && csr_addr(0) && !csr_addr(8)\n val wen: Bool = (io.cmd === CSR.W) || io.cmd(1) && rs1_addr.orR //(rs1_addr =/= 0.U)\n\n\n val isIllegal: Bool = !io.legal && !io.pc_invalid\n\n // branch instruction check (for InstAddrMisalign)\n val pre_mepc: UInt = RegInit(0.U(32.W)) // save mepc if branch inst exsists\n val pre_mtval: UInt = RegInit(Instructions.NOP) // save mtval if branch inst exsists\n val pre_calc_addr: UInt = RegInit(0.U(32.W))\n\n when(io.b_check || io.j_check){\n pre_mepc := io.pc\n pre_mtval := io.inst\n pre_calc_addr := alu_calc_addr\n }\n\n // priority: InstAddrMisalign > InvalidInstruction (if both illegal occur)\n val iaddrInvalid_b: Bool = io.pc(1,0).orR\n val iaddrInvalid_j: Bool = io.j_check && alu_calc_addr(1,0).orR\n val laddrInvalid: Bool = MuxCase(false.B, Seq(\n (io.mem_wr === M_XRD && io.mask_type === MT_W) -> alu_calc_addr(1,0).orR,\n (io.mem_wr === M_XRD && io.mask_type === MT_H) -> alu_calc_addr(0),\n (io.mem_wr === M_XRD && io.mask_type === MT_HU) -> alu_calc_addr(0)\n ))\n val saddrInvalid: Bool = MuxCase(false.B, Seq(\n (io.mem_wr === M_XWR && io.mask_type === MT_W) -> alu_calc_addr(1,0).orR,\n (io.mem_wr === M_XWR && io.mask_type === MT_H) -> alu_calc_addr(0)\n ))\n\n val isInstRet: Bool = (io.inst =/= Instructions.NOP) && (!io.expt || isEcall || isEbreak) && !io.stall\n when(isInstRet) { instret := instret + 1.U }\n when(isInstRet && instret.andR) { instreth := instreth + 1.U }\n\n\n io.expt := isEcall || isEbreak || isIllegal || isExtInt || iaddrInvalid_j || iaddrInvalid_b || laddrInvalid || saddrInvalid// exception\n io.evec := mtvec //+ (PRV << 6).asUInt()\n\n io.epc := mepc\n\n when(!io.pc_invalid) {\n valid_pc := io.pc >> 2 << 2\n }\n\n when(!io.stall) {\n when(io.expt) {\n when(isExtInt){\n mepc := valid_pc\n mtval := io.inst\n }.elsewhen(iaddrInvalid_b) {\n mepc := pre_mepc\n mtval := pre_calc_addr//mtval\n }.elsewhen(laddrInvalid || saddrInvalid){\n mepc := io.pc\n mtval := alu_calc_addr\n }.elsewhen(iaddrInvalid_j) {\n mepc := io.pc\n when(alu_calc_addr(0) && !alu_calc_addr(1)) {\n mtval := (alu_calc_addr >> 1 << 1).asUInt() + 2.U // 16bit address mis-align\n }.otherwise {\n mtval := (alu_calc_addr >> 1 << 1).asUInt()\n }\n }.otherwise {\n mepc := io.pc\n mtval := io.inst\n }\n mcause := Mux(isEcall, Cause.Ecall + PRV,\n Mux(isExtInt, (BigInt(1) << (32 - 1)).asUInt | (Cause.ExtInterrupt + PRV).asUInt,\n Mux(isEbreak, Cause.Breakpoint,\n Mux(iaddrInvalid_j || iaddrInvalid_b, Cause.InstAddrMisaligned,\n Mux(isIllegal, Cause.IllegalInst,\n Mux(laddrInvalid, Cause.LoadAddrMisaligned,\n Mux(saddrInvalid, Cause.StoreAddrMisaligned,\n Cause.InstAddrMisaligned)))))))\n\n PRV := PRIV.M\n IE := false.B\n PRV1 := PRV\n IE1 := IE\n //when(iaddrInvalid_j || iaddrInvalid_b || laddrInvalid || saddrInvalid) { mtval := io.pc }\n\n }.elsewhen(wen) {\n when(csr_addr === CsrAddr.mstatus) {\n PRV1 := wdata(5, 4)\n IE1 := wdata(3)\n //PRV := wdata(2, 1)\n IE := wdata(0)\n }.elsewhen(csr_addr === CsrAddr.mip) {\n MTIP := wdata(7)\n MSIP := wdata(3)\n }.elsewhen(csr_addr === CsrAddr.mie) {\n MEIE := wdata(11)\n MTIE := wdata(7)\n MSIE := wdata(3)\n }.elsewhen(csr_addr === CsrAddr.mtime) {\n time := wdata\n }\n .elsewhen(csr_addr === CsrAddr.mtimeh) {\n timeh := wdata\n }\n// .elsewhen(csr_addr === CsrAddr.mtimecmp) {\n// mtimecmp := wdata\n// MTIP := false.B\n// }\n .elsewhen(csr_addr === CsrAddr.mtvec) {\n mtvec := wdata\n }\n .elsewhen(csr_addr === CsrAddr.mscratch) {\n mscratch := wdata\n }\n .elsewhen(csr_addr === CsrAddr.mepc) {\n mepc := wdata >> 2.U << 2.U\n }\n .elsewhen(csr_addr === CsrAddr.mcause) {\n mcause := wdata & (BigInt(1) << (32 - 1) | 0x0f).U\n } // cause12-16:reserved\n //.elsewhen(csr_addr === CsrAddr.mtval) {\n // mtval := wdata\n //}\n .elsewhen(csr_addr === CsrAddr.mtohost) {\n mtohost := wdata\n }\n .elsewhen(csr_addr === CsrAddr.mfromhost) {\n mfromhost := wdata\n }\n .elsewhen(csr_addr === CsrAddr.cyclew) {\n cycle := wdata\n }\n .elsewhen(csr_addr === CsrAddr.timew) {\n time := wdata\n }\n .elsewhen(csr_addr === CsrAddr.instretw) {\n instret := wdata\n }\n .elsewhen(csr_addr === CsrAddr.cyclehw) {\n cycleh := wdata\n }\n .elsewhen(csr_addr === CsrAddr.timehw) {\n timeh := wdata\n }\n .elsewhen(csr_addr === CsrAddr.instrethw) {\n instreth := wdata\n }\n }\n }\n}", "groundtruth": " when(time.andR) { timeh := timeh + 1.U }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "KyogenRV", "path": "KyogenRV/src/main/scala/mem/DMem.scala", "left_context": "// See README.md for license details.\npackage mem\n\nimport chisel3._\nimport chisel3.Bool\nimport bus.SlaveIf_Data\nimport chisel3.util.Cat\n\n//noinspection ScalaStyle\nclass DMem extends Module {\n val io: SlaveIf_Data = IO(new SlaveIf_Data)\n\n val r_ack: Bool = RegInit(false.B)\n val w_ack: Bool = RegInit(false.B)\n\n // data memory 0x2000 - 0x3000\n val valid_address: Bool = (io.dmem_add.addr >= 0x0000.U) && (io.dmem_add.addr <= 0x3000.U)\n //val w_valid_address: Bool = (io.w_dmem_add.addr >= 0x0000.U) && (io.w_dmem_add.addr <= 0x3000.U)\n val byteenable: UInt = io.w_dmem_dat.byteenable\n\n val r_req: Bool = io.r_dmem_dat.req && valid_address\n val w_req: Bool = io.w_dmem_dat.req && valid_address\n\n // initialization\n //val mem: Mem[UInt] = Mem(256*1024, UInt(32.W))\n// val mem_3: Mem[UInt] = Mem(0x3000, UInt(8.W))\n// val mem_2: Mem[UInt] = Mem(0x3000, UInt(8.W))\n// val mem_1: Mem[UInt] = Mem(0x3000, UInt(8.W))\n// val mem_0: Mem[UInt] = Mem(0x3000, UInt(8.W))\n val mem_3: SyncReadMem[UInt] = SyncReadMem(0x3000, UInt(8.W))\n val mem_2: SyncReadMem[UInt] = SyncReadMem(0x3000, UInt(8.W))\n val mem_1: SyncReadMem[UInt] = SyncReadMem(0x3000, UInt(8.W))\n val mem_0: SyncReadMem[UInt] = SyncReadMem(0x3000, UInt(8.W))\n\n val wdat_3: UInt = io.w_dmem_dat.data(31,24)\n val wdat_2: UInt = io.w_dmem_dat.data(23,16)\n val wdat_1: UInt = io.w_dmem_dat.data(15, 8)\n val wdat_0: UInt = io.w_dmem_dat.data( 7, 0)\n\n val addr_align: UInt = Mux(r_req,(io.dmem_add.addr >> 2).asUInt() - 0x0000.U,\n Mux(w_req,(io.dmem_add.addr >> 2).asUInt() - 0x0000.U,\n 0xffffffffL.U))\n\n\n io.w_dmem_dat.ack := w_ack\n io.r_dmem_dat.data := DontCare\n io.r_dmem_dat.ack := r_ack\n\n // read operation\n when(r_req === true.B) {\n when(byteenable === 15.U) {\n io.r_dmem_dat.data := Cat(\n mem_3.read(addr_align),\n mem_2.read(addr_align),\n mem_1.read(addr_align),\n mem_0.read(addr_align)\n )\n }.otherwise{\n io.r_dmem_dat.data := 0.U\n }\n r_ack := true.B\n w_ack := false.B\n }.elsewhen(w_req === true.B) {\n //mem.write(io.w_dmem_add.addr, io.w_dmem_dat.data)\n", "right_context": " when(byteenable(2)){ mem_2.write(addr_align, wdat_2) }\n when(byteenable(1)){ mem_1.write(addr_align, wdat_1) }\n when(byteenable(0)){ mem_0.write(addr_align, wdat_0) }\n //mem_0.write(addr_align, wdat_0)\n w_ack := true.B\n r_ack := false.B\n }.otherwise{\n w_ack := false.B\n r_ack := false.B\n }\n}\n\n", "groundtruth": " when(byteenable(3)){ mem_3.write(addr_align, wdat_3) }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "KyogenRV", "path": "KyogenRV/src/main/scala/mem/IMem.scala", "left_context": "// See README.md for license details.\npackage mem\n\nimport chisel3._\nimport chisel3.Bool\nimport bus.SlaveIf_Inst\nimport chisel3.util.Cat\n\n//noinspection ScalaStyle\nclass IMem extends Module {\n val io: SlaveIf_Inst = IO(new SlaveIf_Inst)\n\n val r_ack: Bool = RegInit(false.B)\n val w_ack: Bool = RegInit(false.B)\n\n // data memory 0x2000 - 0x3000\n val valid_address: Bool = (io.imem_add.addr >= 0x0000.U) && (io.imem_add.addr <= 0x3000.U)\n //val w_valid_address: Bool = (io.w_imem_add.addr >= 0x0000.U) && (io.w_imem_add.addr <= 0x3000.U)\n val byteenable: UInt = io.w_imem_dat.byteenable\n\n val r_req: Bool = io.r_imem_dat.req && valid_address\n val w_req: Bool = io.w_imem_dat.req && valid_address\n\n // initialization\n //val mem: Mem[UInt] = Mem(256*1024, UInt(32.W))\n // val mem_3: Mem[UInt] = Mem(0x3000, UInt(8.W))\n // val mem_2: Mem[UInt] = Mem(0x3000, UInt(8.W))\n // val mem_1: Mem[UInt] = Mem(0x3000, UInt(8.W))\n // val mem_0: Mem[UInt] = Mem(0x3000, UInt(8.W))\n val mem_3: SyncReadMem[UInt] = SyncReadMem(0x3000, UInt(8.W))\n val mem_2: SyncReadMem[UInt] = SyncReadMem(0x3000, UInt(8.W))\n val mem_1: SyncReadMem[UInt] = SyncReadMem(0x3000, UInt(8.W))\n val mem_0: SyncReadMem[UInt] = SyncReadMem(0x3000, UInt(8.W))\n\n val wdat_3: UInt = io.w_imem_dat.data(31,24)\n val wdat_2: UInt = io.w_imem_dat.data(23,16)\n val wdat_1: UInt = io.w_imem_dat.data(15, 8)\n val wdat_0: UInt = io.w_imem_dat.data( 7, 0)\n\n val addr_align: UInt = Mux(r_req,(io.imem_add.addr >> 2).asUInt() - 0x0000.U,\n Mux(w_req,(io.imem_add.addr >> 2).asUInt() - 0x0000.U,\n 0xffffffffL.U))\n\n\n io.w_imem_dat.ack := w_ack\n io.r_imem_dat.data := DontCare//0xFFFFFFFFL.U//DontCare\n io.r_imem_dat.ack := r_ack\n\n // read operation\n when(r_req === true.B) {\n when(byteenable === 15.U) {\n io.r_imem_dat.data := Cat(\n mem_3.read(addr_align),\n mem_2.read(addr_align),\n mem_1.read(addr_align),\n mem_0.read(addr_align)\n )\n }.otherwise{\n io.r_imem_dat.data := 0.U\n }\n r_ack := true.B\n w_ack := false.B\n }.elsewhen(w_req === true.B) {\n //mem.write(io.w_imem_add.addr, io.w_imem_dat.data)\n when(byteenable(3)){ mem_3.write(addr_align, wdat_3) }\n", "right_context": " when(byteenable(1)){ mem_1.write(addr_align, wdat_1) }\n when(byteenable(0)){ mem_0.write(addr_align, wdat_0) }\n //mem_0.write(addr_align, wdat_0)\n w_ack := true.B\n r_ack := false.B\n }.otherwise{\n w_ack := false.B\n r_ack := false.B\n }\n}\n\n", "groundtruth": " when(byteenable(2)){ mem_2.write(addr_align, wdat_2) }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "KyogenRV", "path": "KyogenRV/src/test/scala/core/CpuBusTester.scala", "left_context": "// See README.md for license details.\npackage core\nimport chisel3.iotesters.PeekPokeTester\n\nimport scala.io.{BufferedSource, Source}\nimport java.util.Calendar\n\nimport java.io.{BufferedWriter, FileWriter ,PrintWriter}\n\ncase class CpuBusTester(c: CpuBus, hexname: String, logname: String) extends PeekPokeTester(c) {\n // read from binary file\n val s: BufferedSource = Source.fromFile(hexname)\n var buffs: Array[String] = _\n try {\n buffs = s.getLines.toArray\n } finally {\n s.close()\n }\n step(1)\n poke(c.io.sw.halt, value = 1)\n poke(c.io.sw.w_waitrequest_sig, value = 0)\n poke(c.io.sw.w_datawaitreq_sig, value = 0)\n step(1)\n\n var pw = new PrintWriter(new BufferedWriter(new FileWriter(logname)), true)\n\n for (addr <- 0 until buffs.length * 4 by 4) {\n val mem_val = buffs(addr / 4).replace(\" \", \"\")\n val mem = Integer.parseUnsignedInt(mem_val, 16)\n\n poke(signal = c.io.sw.w_add, value = addr)\n step(1)\n poke(signal = c.io.sw.w_dat, value = mem)\n pw.println(f\"write: addr = 0x$addr%04X,\\tdata = 0x$mem%08X\")\n step(1)\n }\n\n step(1)\n pw.println(f\"---------------------------------------------------------\")\n\n poke(signal = c.io.sw.w_pc, value = 0) // restart pc address\n step(1) // fetch pc\n poke(c.io.sw.w_waitrequest_sig, value = 1) // after reset, waitrequest = 1\n poke(signal = c.io.sw.halt, value = 0)\n step(2)\n pw.println(f\"count\\tINST\\t\\t| EX STAGE:rs1 ,\\t\\t\\trs2 ,\\t\\timm\\t\\t\\t| MEM:ALU out\\t| WB:ALU out, rd\\t\\t\\t\\tstall\")\n\n // external interrupt signal(true = rising edge, 0 = off)\n poke(signal = c.io.sw.w_interrupt_sig, value = 0)\n\n // about 1000 cycle, we can finish 'riscv-tests'.\n // change parameters on your another projects.\n for (lp <- 0 until 1000 by 1) {\n val a = peek(signal = c.io.sw.r_pc) // pc count\n val d = peek(signal = c.io.sw.r_dat) // instruction\n val exraddr1 = peek(c.io.sw.r_ex_raddr1) // rs1 address\n val exraddr2 = peek(c.io.sw.r_ex_raddr2) // rs2 address\n val exrs1 = peek(c.io.sw.r_ex_rs1) // rs1 data\n val exrs2 = peek(c.io.sw.r_ex_rs2) // rs2 data\n val eximm = peek(c.io.sw.r_ex_imm) // imm\n val memaluo = peek(c.io.sw.r_mem_alu_out) // alu(MEM stage)\n val wbaluo = peek(c.io.sw.r_wb_alu_out) // alu(WB stage)\n val wbaddr = peek(c.io.sw.r_wb_rf_waddr) // write-back rd address\n val wbdata = peek(c.io.sw.r_wb_rf_wdata) // write-back rd data\n val stallsig = peek(c.io.sw.r_stall_sig) // stall signal\n // if you need fire external interrupt signal uncomment below\n // if(lp == 96){\n // poke(signal = c.io.sw.w_interrupt_sig, value = 1)\n // }\n // else{\n // poke(signal = c.io.sw.w_interrupt_sig, value = 0)\n // }\n if(lp > 3) {\n poke(c.io.sw.w_waitrequest_sig, value = 0)\n }\n", "right_context": " pw.println(f\"0x$a%04X,\\t0x$d%08X\\t| x($exraddr1)=>0x$exrs1%08X, x($exraddr2)=>0x$exrs2%08X,\\t0x$eximm%08X\\t| 0x$memaluo%08X\\t| 0x$wbaluo%08X, x($wbaddr%d)\\t<= 0x$wbdata%08X, $stallsig%x\") //peek(c.io.sw.data)\n\n }\n step(1)\n pw.println(\"---------------------------------------------------------\")\n\n poke(signal = c.io.sw.halt, value = 1)\n step(2)\n\n for (lp <- 0 to 31 by 1) {\n\n poke(signal = c.io.sw.g_add, value = lp)\n step(1)\n val d = {\n peek(signal = c.io.sw.g_dat)\n }\n\n step(1)\n pw.println(f\"read : x$lp%2d = 0x$d%08X \") //peek(c.io.sw.data)\n }\n\n poke(signal = c.io.sw.g_add, value = 3) // select x3 register (gp)\n step(1)\n\n val d: BigInt = peek(signal = c.io.sw.g_dat)\n step(1)\n if (d == 1) { // if(x3 == 1) then PASS else FAIL\n pw.println(f\"$hexname%s PASS: simulation finished.\")\n } else {\n pw.println(f\"$hexname%s FAIL: simulation finished.\")\n }\n pw.println(f\"simulation finished at \" + Calendar.getInstance().getTime())\n pw.close()\n expect(c.io.sw.g_dat, expected = 1)\n\n}\n\n\n\n", "groundtruth": "/*\n if( (lp >= 20 && lp<=25) || lp == 65 || lp == 90){\n poke(signal = c.io.sw.w_waitrequest_sig, value = 1)\n }\n else{\n", "crossfile_context": "", "category": "Testbench Stimulus and Environment", "subcategory": "Stimulus Generation", "confidence": 0.85, "category_reason": "Chisel test harness (poke/peek/step)"} {"task_id": "KyogenRV", "path": "KyogenRV/src/test/scala/core/TestCoreAll.scala", "left_context": "// See README.md for license details.\npackage core\nimport chisel3.iotesters\nimport chisel3.iotesters.ChiselFlatSpec\n//noinspection ScalaStyle\nclass TestCoreAll extends ChiselFlatSpec {\n\t\"rv32ui-p-add.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-add.hex\", \"src/sw/rv32ui-p-add_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-addi.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-addi.hex\", \"src/sw/rv32ui-p-addi_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-and.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-and.hex\", \"src/sw/rv32ui-p-and_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-andi.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-andi.hex\", \"src/sw/rv32ui-p-andi_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-auipc.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-auipc.hex\", \"src/sw/rv32ui-p-auipc_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-beq.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-beq.hex\", \"src/sw/rv32ui-p-beq_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-bge.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-bge.hex\", \"src/sw/rv32ui-p-bge_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-bgeu.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-bgeu.hex\", \"src/sw/rv32ui-p-bgeu_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-blt.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-blt.hex\", \"src/sw/rv32ui-p-blt_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-bltu.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-bltu.hex\", \"src/sw/rv32ui-p-bltu_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-bne.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-bne.hex\", \"src/sw/rv32ui-p-bne_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-jal.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-jal.hex\", \"src/sw/rv32ui-p-jal_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-jalr.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-jalr.hex\", \"src/sw/rv32ui-p-jalr_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-lb.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-lb.hex\", \"src/sw/rv32ui-p-lb_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-lbu.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-lbu.hex\", \"src/sw/rv32ui-p-lbu_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-lh.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-lh.hex\", \"src/sw/rv32ui-p-lh_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-lhu.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-lhu.hex\", \"src/sw/rv32ui-p-lhu_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-lui.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-lui.hex\", \"src/sw/rv32ui-p-lui_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-lw.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-lw.hex\", \"src/sw/rv32ui-p-lw_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-or.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-or.hex\", \"src/sw/rv32ui-p-or_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-ori.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-ori.hex\", \"src/sw/rv32ui-p-ori_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-sb.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-sb.hex\", \"src/sw/rv32ui-p-sb_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-sh.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-sh.hex\", \"src/sw/rv32ui-p-sh_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-simple.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-simple.hex\", \"src/sw/rv32ui-p-simple_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-sll.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-sll.hex\", \"src/sw/rv32ui-p-sll_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-slli.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-slli.hex\", \"src/sw/rv32ui-p-slli_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-slt.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-slt.hex\", \"src/sw/rv32ui-p-slt_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-slti.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-slti.hex\", \"src/sw/rv32ui-p-slti_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-sltiu.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-sltiu.hex\", \"src/sw/rv32ui-p-sltiu_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-sltu.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-sltu.hex\", \"src/sw/rv32ui-p-sltu_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-sra.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-sra.hex\", \"src/sw/rv32ui-p-sra_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-srai.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-srai.hex\", \"src/sw/rv32ui-p-srai_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-srl.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-srl.hex\", \"src/sw/rv32ui-p-srl_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-srli.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-srli.hex\", \"src/sw/rv32ui-p-srli_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-sub.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-sub.hex\", \"src/sw/rv32ui-p-sub_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-sw.hex tester using iotesters\" should \"be pass test.\" in {\n", "right_context": "\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-xor.hex\", \"src/sw/rv32ui-p-xor_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32ui-p-xori.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-xori.hex\", \"src/sw/rv32ui-p-xori_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32mi-p-breakpoint.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32mi-p-breakpoint.hex\", \"src/sw/rv32mi-p-breakpoint_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32mi-p-csr.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32mi-p-csr.hex\", \"src/sw/rv32mi-p-csr_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32mi-p-illegal.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32mi-p-illegal.hex\", \"src/sw/rv32mi-p-illegal_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32mi-p-ma_addr.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32mi-p-ma_addr.hex\", \"src/sw/rv32mi-p-ma_addr_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32mi-p-ma_fetch.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32mi-p-ma_fetch.hex\", \"src/sw/rv32mi-p-ma_fetch_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32mi-p-mcsr.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32mi-p-mcsr.hex\", \"src/sw/rv32mi-p-mcsr_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32mi-p-sbreak.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32mi-p-sbreak.hex\", \"src/sw/rv32mi-p-sbreak_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32mi-p-scall.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32mi-p-scall.hex\", \"src/sw/rv32mi-p-scall_tester.log\")\n\t\t}) should be (true)\n\t}\n\t\"rv32mi-p-shamt.hex tester using iotesters\" should \"be pass test.\" in {\n\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32mi-p-shamt.hex\", \"src/sw/rv32mi-p-shamt_tester.log\")\n\t\t}) should be (true)\n\t}\n}\n", "groundtruth": "\t\tiotesters.Driver.execute(Array(), () => new CpuBus())(testerGen = c => {\n\t\t\tCpuBusTester(c, \"src/sw/rv32ui-p-sw.hex\", \"src/sw/rv32ui-p-sw_tester.log\")\n\t\t}) should be (true)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "Frenda", "path": "Frenda/src/main/scala/frenda/FirrtlCompiler.scala", "left_context": "package frenda\n\nimport firrtl.options.StageMain\nimport frenda.stage.FrendaStage\n\n/**\n * Entry point of Frenda.\n */\n", "right_context": "", "groundtruth": "object FirrtlCompiler extends StageMain(new FrendaStage)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "Frenda", "path": "Frenda/src/main/scala/frenda/FrendaException.scala", "left_context": "package frenda\n\n/**\n * Represents a Frenda internal exception.\n *\n * @param msg message of the exception\n */\n", "right_context": "", "groundtruth": "class FrendaException(msg: String) extends Exception(msg)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "Frenda", "path": "Frenda/src/main/scala/frenda/stage/FrendaAnnotations.scala", "left_context": "package frenda.stage\n\nimport firrtl.AnnotationSeq\nimport firrtl.annotations.{Annotation, NoTargetAnnotation}\nimport firrtl.ir.Circuit\nimport firrtl.options.{HasShellOptions, ShellOption, Unserializable}\n\nimport java.util.concurrent.Executors\nimport java.util.concurrent.atomic.AtomicInteger\nimport scala.concurrent.{ExecutionContext, Future}\n\nsealed trait FrendaAnnotation extends Unserializable {\n this: Annotation =>\n}\n\ncase class JobsAnnotation(jobs: Int)\n extends NoTargetAnnotation\n with FrendaAnnotation\n\nobject JobsAnnotation extends HasShellOptions {\n val options: Seq[ShellOption[_]] = Seq(\n new ShellOption[Int](\n longOption = \"jobs\",\n shortOption = Some(\"j\"),\n toAnnotationSeq = i => Seq(JobsAnnotation(i)),\n helpText = \"The number of jobs to run simultaneously, default to 1\",\n )\n )\n}\n\ncase class OutputDotFFileAnnotation(file: String)\n extends NoTargetAnnotation\n with FrendaAnnotation\n\nobject OutputDotFFileAnnotation extends HasShellOptions {\n val options: Seq[ShellOption[_]] = Seq(\n new ShellOption[String](\n longOption = \"output-f-file\",\n shortOption = Some(\"off\"),\n toAnnotationSeq = s => Seq(OutputDotFFileAnnotation(s)),\n helpText = \"The output '.f' file\",\n helpValueName = Some(\"\"),\n )\n )\n}\n\ncase object SilentModeAnnotation\n extends NoTargetAnnotation\n with FrendaAnnotation\n with HasShellOptions {\n val options: Seq[ShellOption[_]] = Seq(\n new ShellOption[Unit](\n longOption = \"silent-mode\",\n shortOption = Some(\"s\"),\n toAnnotationSeq = _ => Seq(SilentModeAnnotation),\n helpText = \"Do not display any additional information on the screen\",\n )\n )\n}\n\ncase object CleanBuildAnnotation\n extends NoTargetAnnotation\n with FrendaAnnotation\n with HasShellOptions {\n val options: Seq[ShellOption[_]] = Seq(\n new ShellOption[Unit](\n longOption = \"clean-build\",\n shortOption = Some(\"cb\"),\n toAnnotationSeq = _ => Seq(CleanBuildAnnotation),\n helpText = \"Ignores the build cache and perform a clean build\",\n )\n )\n}\n\nfinal case class FrendaOptions(targetDir: String,\n jobs: Int,\n outputDotF: Option[String],\n silentMode: Boolean,\n cleanBuild: Boolean) {\n class GlobalExecutionContext extends ExecutionContext {\n private val threadPool = Executors.newFixedThreadPool(jobs)\n\n override def execute(runnable: Runnable): Unit = threadPool.submit(runnable)\n\n override def reportFailure(cause: Throwable): Unit = ()\n\n def shutdown(): Unit = threadPool.shutdown()\n }\n\n /** The global execution context of all `Future`s. */\n lazy val executionContext: GlobalExecutionContext = new GlobalExecutionContext\n\n /** Total progress. */\n var totalProgress: Int = 0\n\n /** Current progress. */\n private val currentProgress = new AtomicInteger\n\n /** The print stream of logger. */\n private val stream = System.out\n\n /**\n * Logs message if not in silent mode.\n *\n * @param message the message\n */\n", "right_context": "\n /**\n * Logs message if not in silent mode (thread-safe).\n *\n * @param message the message\n */\n @inline def logSync(message: String): Unit = if (!silentMode) stream.synchronized {\n stream.println(message)\n }\n\n /**\n * Logs message with progress information if not in silent mode (thread-safe).\n *\n * @param message the message\n */\n @inline def logProgress(message: String): Unit = if (!silentMode) {\n val progress = currentProgress.incrementAndGet()\n stream.synchronized {\n stream.println(s\"[$progress/$totalProgress] $message\")\n }\n }\n}\n\nobject FrendaOptions {\n /**\n * Gets `FrendaOptions` from annotations.\n *\n * @param annotations the sequence of annotations\n * @return options\n */\n def fromAnnotations(annotations: AnnotationSeq): FrendaOptions =\n annotations.collectFirst { case FrendaOptionsAnnotation(o) => o }.get\n}\n\ncase class FrendaOptionsAnnotation(frendaOptions: FrendaOptions)\n extends NoTargetAnnotation\n with FrendaAnnotation\n\nfinal case class SplitModule(name: String, circuit: Circuit)\n\ncase class FutureSplitModulesAnnotation(futures: Seq[Future[SplitModule]])\n extends NoTargetAnnotation\n with FrendaAnnotation {\n override def toString: String = s\"FutureSplitModulesAnnotation(${futures.length} x Future)\"\n}\n\ncase class WriteDotFFileAnnotation(files: Seq[String])\n extends NoTargetAnnotation\n with FrendaAnnotation\n", "groundtruth": " @inline def log(message: String): Unit = if (!silentMode) stream.println(message)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "Frenda", "path": "Frenda/src/main/scala/frenda/stage/FrendaCli.scala", "left_context": "package frenda.stage\n\nimport firrtl.options.Shell\n\n/**\n * The command line interface of Frenda.\n */\ntrait FrendaCli {\n", "right_context": " parser.note(\"Frenda Specific Options\")\n Seq(\n JobsAnnotation,\n OutputDotFFileAnnotation,\n SilentModeAnnotation,\n CleanBuildAnnotation,\n ).foreach(_.addOptions(parser))\n}\n", "groundtruth": " this: Shell =>\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "Frenda", "path": "Frenda/src/main/scala/frenda/stage/FrendaPhase.scala", "left_context": "package frenda.stage\n\nimport firrtl.options.{Dependency, PhaseManager}\nimport frenda.stage.phases._\n\n/**\n * All phases required by Frenda.\n */\n", "right_context": "\nobject FrendaPhase {\n val targets: Seq[PhaseManager.PhaseDependency] = Seq(\n Dependency[CheckOptions],\n Dependency[AddCircuit],\n Dependency[PreTransform],\n Dependency[SplitCircuit],\n Dependency[IncrementalCompile],\n Dependency[WriteDotFFile],\n )\n}\n", "groundtruth": "class FrendaPhase extends PhaseManager(FrendaPhase.targets)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "Frenda", "path": "Frenda/src/main/scala/frenda/stage/FrendaStage.scala", "left_context": "package frenda.stage\n\nimport firrtl.AnnotationSeq\nimport firrtl.options.{Shell, Stage}\nimport firrtl.stage.FirrtlCli\n\n/**\n * Main stage of Frenda.\n *\n * The stage will read the input FIRRTL, and then compile it incrementally.\n */\nclass FrendaStage extends Stage {\n val shell: Shell = new Shell(applicationName = \"frenda\") with FrendaCli with FirrtlCli\n\n", "right_context": "", "groundtruth": " def run(annotations: AnnotationSeq): AnnotationSeq = {\n val result = new FrendaPhase().transform(annotations)\n FrendaOptions.fromAnnotations(result).executionContext.shutdown()\n result\n }\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "Frenda", "path": "Frenda/src/main/scala/frenda/stage/phases/AddCircuit.scala", "left_context": "package frenda.stage.phases\n\nimport firrtl.AnnotationSeq\nimport firrtl.options.{Dependency, Phase}\nimport firrtl.stage.phases\nimport firrtl.stage.phases.AddDefaults\nimport frenda.stage.FrendaOptions\n\nclass AddCircuit extends Phase {\n override def prerequisites = Seq(Dependency[CheckOptions], Dependency[AddDefaults])\n\n override def optionalPrerequisites = Seq()\n\n", "right_context": "\n override def invalidates(a: Phase) = false\n\n override def transform(annotations: AnnotationSeq): AnnotationSeq = {\n val options = FrendaOptions.fromAnnotations(annotations)\n options.log(\"Parsing input circuit...\")\n new phases.AddCircuit().transform(annotations)\n }\n}\n", "groundtruth": " override def optionalPrerequisiteOf = Seq()\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "Frenda", "path": "Frenda/src/main/scala/frenda/stage/phases/CheckOptions.scala", "left_context": "package frenda.stage.phases\n\nimport firrtl.AnnotationSeq\nimport firrtl.options.{Phase, TargetDirAnnotation}\nimport firrtl.stage.{FirrtlCircuitAnnotation, FirrtlFileAnnotation, FirrtlSourceAnnotation}\nimport frenda.FrendaException\nimport frenda.stage._\n\n/**\n * Checks command line options, including input and output.\n */\nclass CheckOptions extends Phase {\n override def prerequisites = Seq()\n\n override def optionalPrerequisites = Seq()\n\n override def optionalPrerequisiteOf = Seq()\n\n", "right_context": "\n override def transform(annotations: AnnotationSeq): AnnotationSeq = {\n // check input\n val inputCount = annotations.count {\n case _: FirrtlFileAnnotation => true\n case _: FirrtlSourceAnnotation => true\n case _: FirrtlCircuitAnnotation => true\n case _ => false\n }\n if (inputCount > 1) {\n throw new FrendaException(s\"Error: only one FIRRTL input should be present, but found $inputCount\")\n } else if (inputCount < 1) {\n throw new FrendaException(\"Error: FIRRTL input not found, try -i \")\n }\n // check output\n val targetCount = annotations.count(_.isInstanceOf[TargetDirAnnotation])\n if (targetCount > 1) {\n throw new FrendaException(s\"Error: there can only be 1 target directory, but found $targetCount\")\n }\n val targetDir = annotations collectFirst { case TargetDirAnnotation(s) => s } getOrElse \".\"\n // check Frenda related options\n val jobs = annotations collectFirst { case JobsAnnotation(i) => i } getOrElse 1\n if (jobs < 1) {\n throw new FrendaException(s\"Error: jobs number must be greater than 0, but found $jobs\")\n }\n val outputDotF = annotations.collectFirst { case OutputDotFFileAnnotation(s) => s }\n val silentMode = annotations.exists { case SilentModeAnnotation => true; case _ => false }\n val cleanBuild = annotations.exists { case CleanBuildAnnotation => true; case _ => false }\n annotations ++ Seq(\n FrendaOptionsAnnotation(FrendaOptions(targetDir, jobs, outputDotF, silentMode, cleanBuild))\n )\n }\n}\n", "groundtruth": " override def invalidates(a: Phase) = false\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "Frenda", "path": "Frenda/src/main/scala/frenda/stage/phases/IncrementalCompile.scala", "left_context": "package frenda.stage.phases\n\nimport firrtl.options.{Dependency, Phase}\nimport firrtl.stage.transforms.Compiler\nimport firrtl.{AnnotationSeq, CircuitState, EmitCircuitAnnotation, EmittedVerilogCircuitAnnotation, VerilogEmitter}\nimport frenda.stage.{FrendaOptions, FutureSplitModulesAnnotation, SplitModule, WriteDotFFileAnnotation}\n\nimport java.nio.file.{Files, Paths}\nimport java.security.MessageDigest\nimport scala.concurrent.duration.Duration\nimport scala.concurrent.{Await, ExecutionContext, Future}\n\n/**\n * Compiles split modules incrementally.\n */\nclass IncrementalCompile extends Phase {\n override def prerequisites = Seq(Dependency[SplitCircuit])\n\n", "right_context": "\n override def optionalPrerequisiteOf = Seq()\n\n override def invalidates(a: Phase) = false\n\n /**\n * Checks if the specific module should be compiled.\n * If so, returns a function for updating the hash file of the module.\n *\n * @param options Frenda related options\n * @param splitModule the input module\n * @return some function for updating the hash file if the module should be compiled,\n * otherwise `None`\n */\n private def shouldBeCompiled(options: FrendaOptions,\n splitModule: SplitModule): Option[() => Unit] = {\n // get the hash code of the current `Circuit`\n val hash = MessageDigest.getInstance(\"SHA-256\")\n .digest(splitModule.circuit.serialize.getBytes(\"UTF-8\"))\n // get the hash file of the current module\n val hashFile = Paths.get(options.targetDir, s\"${splitModule.name}.hash\")\n if (options.cleanBuild || Files.notExists(hashFile)) {\n // clean build or hash file not found, just compile\n return Some(() => Files.write(hashFile, hash))\n }\n // check the hash code\n val recompile = !(Files.readAllBytes(hashFile) sameElements hash)\n // if re-compilation required, update the hash file\n Option.when(recompile) { () => Files.write(hashFile, hash) }\n }\n\n /**\n * Compiles the specific module to Verilog.\n *\n * @param options Frenda related options\n * @param annotations sequence of annotations\n * @param splitModule the input module\n * @return path to generated verilog file and recompilation flag\n */\n private def compile(options: FrendaOptions,\n annotations: AnnotationSeq,\n splitModule: SplitModule): Option[(String, Boolean)] = {\n // check if need to be compiled\n shouldBeCompiled(options, splitModule) match {\n case Some(updateHash) =>\n // emit the current circuit\n val circuitAnnotations = annotations ++ Seq(\n EmitCircuitAnnotation(classOf[VerilogEmitter]),\n )\n val state = CircuitState(splitModule.circuit, circuitAnnotations)\n val compiler = new Compiler(Seq(Dependency[VerilogEmitter]), PreTransform.targets)\n val newState = compiler.transform(state)\n // generate output\n options.logProgress(s\"Done compiling module '${splitModule.name}'\")\n newState.annotations.collectFirst {\n case EmittedVerilogCircuitAnnotation(e) =>\n // write to Verilog file and hash file\n val path = Paths.get(options.targetDir, s\"${splitModule.name}.v\")\n Files.writeString(path, e.value)\n updateHash()\n (path.toRealPath().toAbsolutePath.toString, true)\n }\n case None =>\n options.logProgress(s\"Skipping module '${splitModule.name}'\")\n val path = Paths.get(options.targetDir, s\"${splitModule.name}.v\")\n Option.when(Files.exists(path)) {\n (path.toRealPath().toAbsolutePath.toString, false)\n }\n }\n }\n\n override def transform(annotations: AnnotationSeq): AnnotationSeq = annotations.flatMap {\n case FutureSplitModulesAnnotation(futures) =>\n val options = FrendaOptions.fromAnnotations(annotations)\n // create compilation tasks\n implicit val ec: ExecutionContext = options.executionContext\n val tasks = futures.map { f => f.map(compile(options, annotations, _)) }\n // compile and get results\n options.log(s\"Compiling ${futures.length} modules...\")\n val results = Await.result(Future.sequence(tasks), Duration.Inf).flatten\n options.log(s\"Done compiling\")\n // generate annotation if recompiled\n Option.when(results.exists(_._2)) {\n WriteDotFFileAnnotation(results.map(_._1))\n }\n case other => Some(other)\n }\n}\n", "groundtruth": " override def optionalPrerequisites = Seq()\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "Frenda", "path": "Frenda/src/main/scala/frenda/stage/phases/PreTransform.scala", "left_context": "package frenda.stage.phases\n\nimport firrtl.options.{Dependency, Phase}\nimport firrtl.stage.TransformManager.TransformDependency\nimport firrtl.stage.transforms.Compiler\nimport firrtl.stage.{FirrtlCircuitAnnotation, Forms}\nimport firrtl.{AnnotationSeq, CircuitState}\nimport frenda.stage.FrendaOptions\n\n/**\n * Run some necessary cross-module transforms for the input FIRRTL.\n */\nclass PreTransform extends Phase {\n override def prerequisites = Seq(Dependency[AddCircuit])\n\n", "right_context": "\n override def optionalPrerequisiteOf = Seq()\n\n override def invalidates(a: Phase) = false\n\n override def transform(annotations: AnnotationSeq): AnnotationSeq = annotations.map {\n case FirrtlCircuitAnnotation(circuit) =>\n val options = FrendaOptions.fromAnnotations(annotations)\n val compiler = new Compiler(PreTransform.targets)\n val state = CircuitState(circuit, annotations)\n options.log(\"Running pre-transforms...\")\n FirrtlCircuitAnnotation(compiler.transform(state).circuit)\n case other => other\n }\n}\n\nobject PreTransform {\n /** Target transforms. */\n val targets: Seq[TransformDependency] = Forms.HighForm\n}\n", "groundtruth": " override def optionalPrerequisites = Seq()\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "Frenda", "path": "Frenda/src/main/scala/frenda/stage/phases/SplitCircuit.scala", "left_context": "package frenda.stage.phases\n\nimport firrtl.ir.{Circuit, DefInstance, DefModule, ExtModule, Module, Statement}\nimport firrtl.options.{Dependency, Phase}\nimport firrtl.stage.FirrtlCircuitAnnotation\nimport firrtl.{AnnotationSeq, WDefInstanceConnector}\nimport frenda.FrendaException\nimport frenda.stage.{FrendaOptions, SplitModule, FutureSplitModulesAnnotation}\n\nimport scala.collection.mutable.ArrayBuffer\nimport scala.concurrent.{ExecutionContext, Future}\n\n/**\n * Split the input circuit into single-module circuits.\n */\nclass SplitCircuit extends Phase {\n override def prerequisites = Seq(Dependency[PreTransform])\n\n override def optionalPrerequisites = Seq()\n\n", "right_context": "\n override def invalidates(a: Phase) = false\n\n /**\n * Collects all instantiated modules in a module.\n *\n * @param mod the input module\n * @param map all defined modules in the circuit\n * @return sequence of defined modules\n */\n private def collectInstantiatedModules(mod: Module, map: Map[String, DefModule]): Seq[DefModule] = {\n // use list instead of set to maintain order\n val modules = ArrayBuffer.empty[DefModule]\n\n def onStmt(stmt: Statement): Unit = stmt match {\n case DefInstance(_, _, name, _) => modules += map(name)\n case _: WDefInstanceConnector => throw new FrendaException(s\"unrecognized statement: $stmt\")\n case other => other.foreachStmt(onStmt)\n }\n\n onStmt(mod.body)\n modules.distinct.toSeq\n }\n\n /**\n * Split the specific circuit to separated modules.\n *\n * @param circuit the input circuit\n * @return sequence of split FIRRTL modules (circuits)\n */\n private def splitCircuitIntoModules(options: FrendaOptions, circuit: Circuit): Seq[Future[SplitModule]] = {\n val modMap = circuit.modules.map(m => m.name -> m).toMap\n // turn each module into it's own circuit with it as the top and all instantiated modules as `ExtModules`\n circuit.modules.collect {\n case m: Module =>\n implicit val ec: ExecutionContext = options.executionContext\n Future {\n val instModules = collectInstantiatedModules(m, modMap)\n val extModules = instModules.map {\n case Module(info, name, ports, _) => ExtModule(info, name, ports, name, Seq.empty)\n case ext: ExtModule => ext\n }\n val circuit = Circuit(m.info, extModules :+ m, m.name)\n options.logProgress(s\"Done splitting module '${m.name}'\")\n SplitModule(m.name, circuit)\n }\n }\n }\n\n override def transform(annotations: AnnotationSeq): AnnotationSeq = annotations.map {\n case FirrtlCircuitAnnotation(circuit) =>\n val options = FrendaOptions.fromAnnotations(annotations)\n // create tasks for splitting modules\n options.log(\"Splitting circuit...\")\n val tasks = splitCircuitIntoModules(options, circuit)\n // update total progress for splitting and compiling modules\n options.totalProgress = tasks.length * 2\n FutureSplitModulesAnnotation(tasks)\n case other => other\n }\n}\n", "groundtruth": " override def optionalPrerequisiteOf = Seq()\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "Frenda", "path": "Frenda/src/main/scala/frenda/stage/phases/WriteDotFFile.scala", "left_context": "package frenda.stage.phases\n\nimport firrtl.AnnotationSeq\nimport firrtl.options.{Dependency, Phase}\nimport frenda.stage.{FrendaOptions, WriteDotFFileAnnotation}\n\nimport java.nio.file.{Files, Paths}\n\n/**\n * Write paths of generated Verilog file to the output dot f file.\n */\nclass WriteDotFFile extends Phase {\n override def prerequisites = Seq(Dependency[IncrementalCompile])\n\n", "right_context": "\n override def optionalPrerequisiteOf = Seq()\n\n override def invalidates(a: Phase) = false\n\n override def transform(annotations: AnnotationSeq): AnnotationSeq = annotations.flatMap {\n case WriteDotFFileAnnotation(files) =>\n val options = FrendaOptions.fromAnnotations(annotations)\n options.outputDotF.foreach { path =>\n Files.writeString(Paths.get(path), files.mkString(\"\\n\"))\n }\n None\n case other => Some(other)\n }\n}\n", "groundtruth": " override def optionalPrerequisites = Seq()\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "chisel-circt", "path": "chisel-circt/project/Dependencies.scala", "left_context": "import sbt._\n\n", "right_context": "", "groundtruth": "object Dependencies {\n lazy val scalaTest = \"org.scalatest\" %% \"scalatest\" % \"3.2.14\"\n private val chiselVersion = \"3.5.5\"\n lazy val chisel3 = \"edu.berkeley.cs\" %% \"chisel3\" % chiselVersion\n lazy val chiselCompilerPlugin = \"edu.berkeley.cs\" %% \"chisel3-plugin\" % chiselVersion\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.6, "category_reason": "val binding"} {"task_id": "chisel-circt", "path": "chisel-circt/src/main/scala/circt/Implicits.scala", "left_context": "// SPDX-License-Identifier: Apache-2.0\n\npackage circt\n\n/** A collection of implicit classes to provide additional methods to existing types */\nobject Implicits {\n\n /** Helpers for working with Boolean */\n implicit class BooleanImplicits(a: Boolean) {\n\n /** Construct an Option from a Boolean. */\n def option[A](b: => A): Option[A] =\n if (a)\n", "right_context": "", "groundtruth": " Some(b)\n else\n None\n }\n\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "chisel-circt", "path": "chisel-circt/src/main/scala/circt/stage/Annotations.scala", "left_context": "// SPDX-License-Identifier: Apache-2.0\n\npackage circt.stage\n\nimport firrtl.AnnotationSeq\nimport firrtl.annotations.{Annotation, NoTargetAnnotation}\nimport firrtl.options.{CustomFileEmission, HasShellOptions, OptionsException, ShellOption, Unserializable}\nimport firrtl.options.Viewer.view\nimport firrtl.stage.FirrtlOptions\n\n/** An option consumed by [[circt.stage.CIRCTStage CIRCTStage]] */\nsealed trait CIRCTOption extends Unserializable { this: Annotation => }\n\nobject PreserveAggregate extends HasShellOptions {\n sealed trait Type\n object OneDimVec extends Type\n object Vec extends Type\n object All extends Type\n\n override def options = Seq(\n new ShellOption[String](\n longOption = \"preserve-aggregate\",\n toAnnotationSeq = _ match {\n case \"none\" => Seq.empty\n case \"1d-vec\" => Seq(PreserveAggregate(PreserveAggregate.OneDimVec))\n case \"vec\" => Seq(PreserveAggregate(PreserveAggregate.Vec))\n case \"all\" => Seq(PreserveAggregate(PreserveAggregate.All))\n },\n helpText = \"Do not lower aggregate types to ground types\"\n )\n )\n\n}\n\n/** Preserve passive aggregate types in CIRCT.\n */\n", "right_context": "\n/** Object storing types associated with different CIRCT target languages, e.g., RTL or SystemVerilog */\nobject CIRCTTarget {\n\n /** The parent type of all CIRCT targets */\n sealed trait Type\n\n /** The FIRRTL dialect */\n case object FIRRTL extends Type\n\n /** The HW dialect */\n case object HW extends Type\n\n /** The Verilog language */\n case object Verilog extends Type\n\n /** The SystemVerilog language */\n case object SystemVerilog extends Type\n\n}\n\n/** Annotation that tells [[circt.stage.phases.CIRCT CIRCT]] what target to compile to */\ncase class CIRCTTargetAnnotation(target: CIRCTTarget.Type) extends NoTargetAnnotation with CIRCTOption\n\nobject CIRCTTargetAnnotation extends HasShellOptions {\n\n override def options = Seq(\n new ShellOption[String](\n longOption = \"target\",\n toAnnotationSeq = _ match {\n case \"firrtl\" => Seq(CIRCTTargetAnnotation(CIRCTTarget.FIRRTL))\n case \"hw\" => Seq(CIRCTTargetAnnotation(CIRCTTarget.HW))\n case \"verilog\" => Seq(CIRCTTargetAnnotation(CIRCTTarget.Verilog))\n case \"systemverilog\" => Seq(CIRCTTargetAnnotation(CIRCTTarget.SystemVerilog))\n case a => throw new OptionsException(s\"Unknown target name '$a'! (Did you misspell it?)\")\n },\n helpText = \"The CIRCT\",\n helpValueName = Some(\"{firrtl|rtl|systemverilog}\")\n )\n )\n\n}\n\n/** Annotation holding an emitted MLIR string\n *\n * @param filename the name of the file where this should be written\n * @param value a string of MLIR\n * @param suffix an optional suffix added to the filename when this is written to disk\n */\ncase class EmittedMLIR(\n filename: String,\n value: String,\n suffix: Option[String])\n extends NoTargetAnnotation\n with CustomFileEmission {\n\n override protected def baseFileName(annotations: AnnotationSeq): String = filename\n\n override def getBytes = value.getBytes\n\n}\n\ncase class FirtoolOption(option: String) extends NoTargetAnnotation with CIRCTOption\n", "groundtruth": "case class PreserveAggregate(mode: PreserveAggregate.Type) extends NoTargetAnnotation with CIRCTOption\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Type Definition", "confidence": 0.7, "category_reason": "Case class definition"} {"task_id": "chisel-circt", "path": "chisel-circt/src/main/scala/circt/stage/CIRCTOptions.scala", "left_context": "// SPDX-License-Identifier: Apache-2.0\n\npackage circt.stage\n\nimport java.io.File\n\n/** Options associated with CIRCT\n *\n * @param inputFile the name of an input FIRRTL IR file\n * @param outputFile the name of the file where the result will be written, if not split\n * @param preserveAggregate causes CIRCT to not lower aggregate FIRRTL IR types\n * @param target the specific IR or language target that CIRCT should compile to\n */\nclass CIRCTOptions private[stage] (\n val inputFile: Option[File] = None,\n val outputFile: Option[File] = None,\n val preserveAggregate: Option[PreserveAggregate.Type] = None,\n val target: Option[CIRCTTarget.Type] = None,\n", "right_context": " inputFile: Option[File] = inputFile,\n outputFile: Option[File] = outputFile,\n preserveAggregate: Option[PreserveAggregate.Type] = preserveAggregate,\n target: Option[CIRCTTarget.Type] = target,\n firtoolOptions: Seq[String] = firtoolOptions\n ): CIRCTOptions = new CIRCTOptions(inputFile, outputFile, preserveAggregate, target, firtoolOptions)\n\n}\n", "groundtruth": " val firtoolOptions: Seq[String] = Seq.empty) {\n\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "chisel-circt", "path": "chisel-circt/src/main/scala/circt/stage/CIRCTStage.scala", "left_context": "// SPDX-License-Identifier: Apache-2.0\n\npackage circt.stage\n\nimport chisel3.stage.ChiselGeneratorAnnotation\n\nimport firrtl.AnnotationSeq\nimport firrtl.options.{Dependency, Phase, PhaseManager, Shell, Stage, StageMain}\nimport firrtl.stage.FirrtlCli\n\ntrait CLI { this: Shell =>\n parser.note(\"CIRCT (MLIR FIRRTL Compiler) options\")\n Seq(\n CIRCTTargetAnnotation,\n PreserveAggregate,\n ChiselGeneratorAnnotation\n ).foreach(_.addOptions(parser))\n}\n\n/** A [[firrtl.options.Stage Stage]] used to compile FIRRTL IR using CIRCT. This is a drop-in replacement for\n * [[firrtl.stage.FirrtlStage]].\n *\n * @see [[https://github.com/llvm/circt llvm/circt]]\n */\nclass CIRCTStage extends Stage {\n\n override def prerequisites = Seq.empty\n override def optionalPrerequisites = Seq(Dependency[firrtl.stage.phases.Compiler])\n override def optionalPrerequisiteOf = Seq.empty\n override def invalidates(a: Phase) = false\n\n override val shell: Shell = new Shell(\"circt\") with CLI with FirrtlCli\n\n final val phaseManager = new PhaseManager(\n targets = Seq(\n Dependency[circt.stage.phases.CIRCT]\n ),\n currentState = Seq(\n Dependency[firrtl.stage.phases.AddImplicitEmitter]\n )\n )\n\n", "right_context": "\n}\n\n/** Command line utility for [[CIRCTStage]]. */\nobject CIRCTMain extends StageMain(new CIRCTStage)\n", "groundtruth": " override def run(annotations: AnnotationSeq): AnnotationSeq = phaseManager.transform(annotations)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "chisel-circt", "path": "chisel-circt/src/main/scala/circt/stage/ChiselStage.scala", "left_context": "// SPDX-License-Identifier: Apache-2.0\n\npackage circt.stage\n\nimport chisel3.RawModule\nimport chisel3.stage.{ChiselGeneratorAnnotation, NoRunFirrtlCompilerAnnotation}\n\nimport firrtl.{AnnotationSeq, EmittedVerilogCircuitAnnotation}\nimport firrtl.options.{Dependency, Phase, PhaseManager, Shell, Stage, StageMain}\nimport firrtl.options.Viewer.view\nimport firrtl.stage.{Forms, RunFirrtlTransformAnnotation}\n\n/** Entry point for running Chisel with the CIRCT compiler.\n *\n * This is intended to be a replacement for [[chisel3.stage.ChiselStage]].\n *\n * @note The companion object, [[ChiselStage$]], has a cleaner API for compiling and returning a string.\n */\nclass ChiselStage extends Stage {\n\n override def prerequisites = Seq.empty\n override def optionalPrerequisites = Seq.empty\n override def optionalPrerequisiteOf = Seq.empty\n", "right_context": "\n override val shell = new Shell(\"circt\") with CLI\n\n override def run(annotations: AnnotationSeq): AnnotationSeq = {\n\n val pm = new PhaseManager(\n targets = Seq(\n Dependency[chisel3.stage.ChiselStage],\n Dependency[firrtl.stage.phases.AddImplicitOutputFile],\n Dependency[circt.stage.phases.Checks],\n Dependency[circt.stage.CIRCTStage]\n ),\n currentState = Seq(\n Dependency[firrtl.stage.phases.AddDefaults],\n Dependency[firrtl.stage.phases.Checks]\n )\n )\n pm.transform(NoRunFirrtlCompilerAnnotation +: annotations)\n }\n\n}\n\n/** Utilities for compiling Chisel */\nobject ChiselStage {\n\n /** Elaborate a Chisel circuit into a CHIRRTL string */\n def emitCHIRRTL(gen: => RawModule): String = chisel3.stage.ChiselStage.emitChirrtl(gen)\n\n /** A phase shared by all the CIRCT backends */\n private def phase = new PhaseManager(\n Seq(\n Dependency[chisel3.stage.phases.Checks],\n Dependency[chisel3.stage.phases.Elaborate],\n Dependency[chisel3.stage.phases.Convert],\n Dependency[firrtl.stage.phases.AddImplicitOutputFile],\n Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile],\n Dependency[circt.stage.phases.Checks],\n Dependency[circt.stage.phases.CIRCT]\n )\n )\n\n /** Compile a Chisel circuit to FIRRTL dialect */\n def emitFIRRTLDialect(gen: => RawModule): String = phase\n .transform(\n Seq(\n ChiselGeneratorAnnotation(() => gen),\n CIRCTTargetAnnotation(CIRCTTarget.FIRRTL)\n )\n )\n .collectFirst {\n case EmittedMLIR(_, a, _) => a\n }\n .get\n\n /** Compile a Chisel circuit to HWS dialect */\n def emitHWDialect(gen: => RawModule): String = phase\n .transform(\n Seq(\n ChiselGeneratorAnnotation(() => gen),\n CIRCTTargetAnnotation(CIRCTTarget.HW)\n )\n )\n .collectFirst {\n case EmittedMLIR(_, a, _) => a\n }\n .get\n\n /** Compile a Chisel circuit to SystemVerilog\n * @param gen a call-by-name Chisel module\n * @param args additional command line arguments to pass to Chisel\n * @param firtoolOpts additional [[circt.stage.FirtoolOption]] to pass to firtool\n * @return a string containing the Verilog output\n */\n def emitSystemVerilog(\n gen: => RawModule,\n args: Array[String] = Array.empty,\n firtoolOpts: Array[String] = Array.empty\n ): String =\n phase\n .transform(\n Seq(\n ChiselGeneratorAnnotation(() => gen),\n CIRCTTargetAnnotation(CIRCTTarget.SystemVerilog)\n ) ++ (new circt.stage.ChiselStage).shell.parse(args) ++ firtoolOpts.map(FirtoolOption(_))\n )\n .collectFirst {\n case EmittedVerilogCircuitAnnotation(a) => a\n }\n .get\n .value\n\n /** Compile a Chisel circuit to SystemVerilog with file output\n * @param gen a call-by-name Chisel module\n * @param args additional command line arguments to pass to Chisel\n * @param firtoolOpts additional command line options to pass to firtool\n * @return a string containing the Verilog output\n */\n def emitSystemVerilogFile(\n gen: => RawModule,\n args: Array[String] = Array.empty,\n firtoolOpts: Array[String] = Array.empty\n ) = {\n val chiselArgs = Array(\"--target\", \"systemverilog\") ++ args\n (new circt.stage.ChiselStage).execute(\n chiselArgs,\n Seq(ChiselGeneratorAnnotation(() => gen)) ++ firtoolOpts.map(FirtoolOption(_))\n )\n }\n}\n\n/** Command line entry point to [[ChiselStage]] */\nobject ChiselMain extends StageMain(new ChiselStage)\n", "groundtruth": " override def invalidates(a: Phase) = false\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "chisel-circt", "path": "chisel-circt/src/main/scala/circt/stage/package.scala", "left_context": "// SPDX-License-Identifier: Apache-2.0\n\npackage circt\n\nimport circt.stage.{CIRCTOption, CIRCTTargetAnnotation, PreserveAggregate}\n\nimport firrtl.AnnotationSeq\nimport firrtl.options.OptionsView\nimport firrtl.stage.{FirrtlFileAnnotation, FirrtlOption, OutputFileAnnotation}\n\nimport java.io.File\n\npackage object stage {\n\n implicit object CIRCTOptionsView extends OptionsView[CIRCTOptions] {\n\n def view(annotations: AnnotationSeq): CIRCTOptions =\n annotations.collect {\n", "right_context": " case OutputFileAnnotation(a) => acc.copy(outputFile = Some(new File(a)))\n case CIRCTTargetAnnotation(a) => acc.copy(target = Some(a))\n case PreserveAggregate(a) => acc.copy(preserveAggregate = Some(a))\n case FirtoolOption(a) => acc.copy(firtoolOptions = acc.firtoolOptions :+ a)\n case _ => acc\n }\n }\n\n }\n\n}\n", "groundtruth": " case a: CIRCTOption => a\n case a: FirrtlOption => a\n case a: FirrtlFileAnnotation => a\n }\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "chisel-circt", "path": "chisel-circt/src/main/scala/circt/stage/phases/AddFIRRTLInputFile.scala", "left_context": "// SPDX-License-Identifier: Apache-2.0\n\npackage circt.stage.phases\n\nimport firrtl.AnnotationSeq\nimport firrtl.options.{Dependency, Phase}\nimport firrtl.stage.{FirrtlCircuitAnnotation, FirrtlFileAnnotation}\n\nimport chisel3.stage.CircuitSerializationAnnotation\n\nprivate[stage] class AddFIRRTLInputFile extends Phase {\n\n override def prerequisites = Seq.empty\n override def optionalPrerequisites = Seq.empty\n override def optionalPrerequisiteOf = Seq(Dependency[circt.stage.CIRCTStage])\n", "right_context": "\n override def transform(annotations: AnnotationSeq): AnnotationSeq = annotations.flatMap {\n case a: CircuitSerializationAnnotation => Some(FirrtlFileAnnotation(a.filename(annotations).toString))\n case a: FirrtlCircuitAnnotation => None\n case a => Some(a)\n }\n\n}\n", "groundtruth": " override def invalidates(a: Phase) = false\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "chisel-circt", "path": "chisel-circt/src/main/scala/circt/stage/phases/CIRCT.scala", "left_context": "// SPDX-License-Identifier: Apache-2.0\n\npackage circt.stage.phases\n\nimport circt.Implicits.BooleanImplicits\nimport circt.stage.{CIRCTOptions, CIRCTTarget, EmittedMLIR, PreserveAggregate}\n\nimport firrtl.{AnnotationSeq, EmittedVerilogCircuit, EmittedVerilogCircuitAnnotation}\nimport firrtl.annotations.JsonProtocol\nimport firrtl.options.{\n CustomFileEmission,\n Dependency,\n OptionsException,\n OutputAnnotationFileAnnotation,\n Phase,\n StageError,\n StageOptions,\n StageUtils\n}\nimport firrtl.options.phases.WriteOutputAnnotations\nimport firrtl.options.Viewer.view\nimport firrtl.stage.{FirrtlOptions, RunFirrtlTransformAnnotation}\nimport _root_.logger.LogLevel\n\nimport java.io.File\n\nprivate object Helpers {\n implicit class LogLevelHelpers(logLevel: LogLevel.Value) {\n def toCIRCTOptions: Seq[String] = logLevel match {\n case LogLevel.Error => Seq.empty\n case LogLevel.Warn => Seq.empty\n case LogLevel.Info => Seq(\"-verbose-pass-executions\")\n case LogLevel.Debug => Seq(\"-verbose-pass-executions\")\n case LogLevel.Trace => Seq(\"-verbose-pass-executions\", \"-print-ir-after-all\")\n case LogLevel.None => Seq.empty\n }\n }\n\n /** Extract the JSON-encoded Annotation region from a single file output.\n *\n * @todo This is very janky and should be changed to something more stable.\n */\n def extractAnnotationFile(string: String, filename: String): AnnotationSeq = {\n var inAnno = false\n val filtered: String = string.lines.filter {\n case line if line.startsWith(\"// ----- 8< ----- FILE\") && line.contains(filename) =>\n inAnno = true\n false\n case line if line.startsWith(\"// ----- 8< ----- FILE\") =>\n inAnno = false\n false\n case line if inAnno =>\n true\n\n case _ => false\n }.toArray\n .mkString(\"\\n\")\n filtered.forall(_.isWhitespace) match {\n case false => JsonProtocol.deserialize(filtered, false)\n case true => Seq.empty\n }\n }\n}\n\n/** A phase that calls and runs CIRCT, specifically `firtool`, while preserving an [[AnnotationSeq]] API.\n *\n * This is analogous to [[firrtl.stage.phases.Compiler]].\n */\nclass CIRCT extends Phase {\n\n import Helpers._\n import scala.sys.process._\n\n override def prerequisites = Seq(\n Dependency[firrtl.stage.phases.AddDefaults],\n Dependency[firrtl.stage.phases.AddImplicitEmitter],\n Dependency[firrtl.stage.phases.AddImplicitOutputFile]\n )\n override def optionalPrerequisites = Seq.empty\n override def optionalPrerequisiteOf = Seq.empty\n override def invalidates(a: Phase) = false\n\n override def transform(annotations: AnnotationSeq): AnnotationSeq = {\n val circtOptions = view[CIRCTOptions](annotations)\n val firrtlOptions = view[FirrtlOptions](annotations)\n val stageOptions = view[StageOptions](annotations)\n\n var blackbox, inferReadWrite = false\n var imcp = true\n var logLevel = _root_.logger.LogLevel.None\n var split = false\n\n val annotationsx: AnnotationSeq = annotations.flatMap {\n case a: CustomFileEmission => {\n val filename = a.filename(annotations)\n a.replacements(filename)\n }\n case _: firrtl.EmitCircuitAnnotation => Nil\n case _: firrtl.EmitAllModulesAnnotation => {\n split = true\n Nil\n }\n case a @ RunFirrtlTransformAnnotation(transform) =>\n transform match {\n /* Inlining/Flattening happen by default, so these can be dropped. */\n case _: firrtl.passes.InlineInstances | _: firrtl.transforms.Flatten => Nil\n /* ReplSeqMem is converted to a firtool option */\n case _: firrtl.passes.memlib.ReplSeqMem =>\n blackbox = true\n Nil\n /* Any emitters should not be passed to firtool. */\n case _: firrtl.Emitter => Nil\n /* Default case: leave the annotation around and let firtool warn about it. */\n case _ => Seq(a)\n }\n case firrtl.passes.memlib.InferReadWriteAnnotation =>\n inferReadWrite = true\n Nil\n case firrtl.transforms.NoConstantPropagationAnnotation =>\n imcp = false\n Nil\n case anno: _root_.logger.LogLevelAnnotation =>\n logLevel = anno.globalLogLevel\n Nil\n /* The following can be dropped. */\n case _: firrtl.transforms.CombinationalPath => Nil\n case _: _root_.logger.ClassLogLevelAnnotation => Nil\n /* Default case: leave the annotation around and let firtool warn about it. */\n case a => Seq(a)\n }\n\n /* Filter the annotations to only those things which CIRCT should see. */\n (new WriteOutputAnnotations).transform(annotationsx)\n\n val input: String = firrtlOptions.firrtlCircuit match {\n case None => throw new OptionsException(\"No input file specified!\")\n case Some(circuit) => circuit.serialize\n }\n\n val chiselAnnotationFilename: Option[String] =\n stageOptions.annotationFileOut.map(stageOptions.getBuildFileName(_, Some(\".anno.json\")))\n\n val circtAnnotationFilename = \"circt.anno.json\"\n\n val binary = \"firtool\"\n\n val cmd =\n Seq(binary, \"-format=fir\", \"-warn-on-unprocessed-annotations\", \"-verify-each=false\", \"-dedup\") ++\n Seq(\"-output-annotation-file\", circtAnnotationFilename) ++\n circtOptions.firtoolOptions ++\n logLevel.toCIRCTOptions ++\n /* The following options are on by default, so we disable them if they are false. */\n (circtOptions.preserveAggregate match {\n case Some(PreserveAggregate.OneDimVec) => Seq(\"-preserve-aggregate=1d-vec\")\n case Some(PreserveAggregate.Vec) => Seq(\"-preserve-aggregate=vec\")\n case Some(PreserveAggregate.All) => Seq(\"-preserve-aggregate=all\")\n case None => None\n }) ++\n circtOptions.preserveAggregate.map(_ => \"-preserve-public-types=0\") ++\n (!inferReadWrite).option(\"-disable-infer-rw\") ++\n (!imcp).option(\"-disable-imcp\") ++\n /* The following options are off by default, so we enable them if they are true. */\n (blackbox).option(\"-blackbox-memory\") ++\n /* Communicate the annotation file through a file. */\n (chiselAnnotationFilename.map(a => Seq(\"-annotation-file\", a))).getOrElse(Seq.empty) ++\n /* Convert the target to a firtool-compatible option. */\n ((circtOptions.target, split) match {\n case (Some(CIRCTTarget.FIRRTL), false) => Seq(\"-ir-fir\")\n case (Some(CIRCTTarget.HW), false) => Seq(\"-ir-hw\")\n case (Some(CIRCTTarget.Verilog), true) => Seq(\"--split-verilog\", s\"-o=${stageOptions.targetDir}\")\n case (Some(CIRCTTarget.Verilog), false) => None\n case (Some(CIRCTTarget.SystemVerilog), true) => Seq(\"--split-verilog\", s\"-o=${stageOptions.targetDir}\")\n case (Some(CIRCTTarget.SystemVerilog), false) => None\n case (None, _) =>\n throw new Exception(\n \"No 'circtOptions.target' specified. This should be impossible if dependencies are satisfied!\"\n )\n case (_, true) =>\n throw new Exception(\n s\"The circtOptions.target specified (${circtOptions.target}) does not support running with an EmitAllModulesAnnotation as CIRCT only supports one-file-per-module for Verilog or SystemVerilog targets.\"\n )\n case _ =>\n throw new Exception(\n", "right_context": " )\n })\n\n try {\n logger.info(s\"\"\"Running CIRCT: '${cmd.mkString(\" \")} < $$input'\"\"\")\n println(s\"\"\"Running CIRCT: '${cmd.mkString(\" \")} < $$input'\"\"\")\n val stdoutStream, stderrStream = new java.io.ByteArrayOutputStream\n val stdoutWriter = new java.io.PrintWriter(stdoutStream)\n val stderrWriter = new java.io.PrintWriter(stderrStream)\n val exitValue = (cmd #< new java.io.ByteArrayInputStream(input.getBytes))\n .!(ProcessLogger(stdoutWriter.println, stderrWriter.println))\n stdoutWriter.close()\n stderrWriter.close()\n val result = stdoutStream.toString\n logger.info(result)\n val errors = stderrStream.toString\n if (exitValue != 0) {\n StageUtils.dramaticError(s\"${binary} failed.\\nExitCode:\\n${exitValue}\\nSTDOUT:\\n${result}\\nSTDERR:\\n${errors}\")\n throw new StageError()\n }\n if (split) {\n logger.info(result)\n val file = new File(stageOptions.getBuildFileName(circtAnnotationFilename, Some(\".anno.json\")))\n file match {\n case file if !file.canRead() => Seq.empty\n case file => {\n val foo = JsonProtocol.deserialize(file, false)\n foo\n }\n }\n } else { // if split it has already been written out to the file system stdout not necessary.\n val outputFileName: String = stageOptions.getBuildFileName(firrtlOptions.outputFileName.get)\n val outputAnnotations = extractAnnotationFile(result, circtAnnotationFilename)\n outputAnnotations ++ (circtOptions.target match {\n case Some(CIRCTTarget.FIRRTL) =>\n Seq(EmittedMLIR(outputFileName, result, Some(\".fir.mlir\")))\n case Some(CIRCTTarget.HW) =>\n Seq(EmittedMLIR(outputFileName, result, Some(\".hw.mlir\")))\n case Some(CIRCTTarget.Verilog) =>\n Seq(EmittedVerilogCircuitAnnotation(EmittedVerilogCircuit(outputFileName, result, \".v\")))\n case Some(CIRCTTarget.SystemVerilog) =>\n Seq(EmittedVerilogCircuitAnnotation(EmittedVerilogCircuit(outputFileName, result, \".sv\")))\n case None =>\n throw new Exception(\n \"No 'circtOptions.target' specified. This should be impossible if dependencies are satisfied!\"\n )\n })\n }\n } catch {\n case a: java.io.IOException =>\n StageUtils.dramaticError(s\"Binary '$binary' was not found on the $$PATH. (Do you have CIRCT installed?)\")\n throw new StageError(cause = a)\n }\n\n }\n\n}\n", "groundtruth": " s\"Invalid combination of circtOptions.target ${circtOptions.target} and split ${split}\"\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "chisel-circt", "path": "chisel-circt/src/main/scala/circt/stage/phases/Checks.scala", "left_context": "// SPDX-License-Identifier: Apache-2.0\n\npackage circt.stage.phases\n\nimport circt.stage.CIRCTTargetAnnotation\n\nimport firrtl.{AnnotationSeq, EmitAllModulesAnnotation, Emitter, SystemVerilogEmitter}\nimport firrtl.annotations.Annotation\nimport firrtl.options.{Dependency, OptionsException, Phase, TargetDirAnnotation}\nimport firrtl.stage.OutputFileAnnotation\n\n/** Check properties of an [[AnnotationSeq]] to look for errors before running CIRCT. */\nclass Checks extends Phase {\n\n override def prerequisites = Seq.empty\n override def optionalPrerequisiteOf = Seq(Dependency[circt.stage.phases.CIRCT])\n", "right_context": "\n override def transform(annotations: AnnotationSeq): AnnotationSeq = {\n val target, outputFile, split, targetDir = collection.mutable.ArrayBuffer[Annotation]()\n\n annotations.foreach {\n case a: OutputFileAnnotation => outputFile += a\n case a: EmitAllModulesAnnotation => split += a\n case a: TargetDirAnnotation => targetDir += a\n case a: CIRCTTargetAnnotation => target += a\n case _ =>\n }\n if ((split.size > 0) && (outputFile.size != 0)) {\n throw new OptionsException(\"Cannot specify both an OutputFileAnnotation and an EmitAllModulesAnnotation\")\n }\n if ((split.size == 0) && (outputFile.size != 1)) {\n throw new OptionsException(\"An output file must be specified\")\n }\n\n if ((split.size > 0) && (targetDir.size != 1)) {\n throw new OptionsException(\"If EmitAllModulesAnnotation is specified one TargetDirAnnotation is needed\")\n }\n\n if (target.size != 1) {\n throw new OptionsException(\"Exactly one CIRCT target must be specified\")\n }\n\n annotations\n }\n\n}\n", "groundtruth": " override def invalidates(a: Phase) = false\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "chisel-circt", "path": "chisel-circt/src/test/scala/circtTests/stage/CIRCTStageSpec.scala", "left_context": "// SPDX-License-Identifier: Apache-2.0\n\npackage circtTests.stage\n\nimport circt.stage.CIRCTStage\n\nimport firrtl.stage.{FirrtlFileAnnotation, OutputFileAnnotation}\n\nimport java.io.File\nimport java.io.{PrintWriter, Writer}\n\nimport org.scalatest.funspec.AnyFunSpec\nimport org.scalatest.matchers.should.Matchers\n\nimport scala.io.Source\n\nclass CIRCTStageSpec extends AnyFunSpec with Matchers {\n\n private def writeFile(file: File, string: String): Unit = {\n val writer = {\n file.getParentFile.mkdirs()\n new PrintWriter(file)\n }\n writer.write(string)\n writer.close()\n }\n\n describe(\"CIRCTStage\") {\n\n it(\"should compile a FIRRTL file to Verilog\") {\n\n val input =\n \"\"\"|circuit Foo:\n | module Foo:\n | input a: UInt<1>\n | output b: UInt<1>\n | b <= not(a)\n |\"\"\".stripMargin\n\n val targetDir = new File(\"test_run_dir/CIRCTStage\")\n val inputFile = new File(targetDir, \"Foo.fir\")\n\n writeFile(inputFile, input)\n\n val outputFile = new File(targetDir, \"Foo.sv\")\n", "right_context": " targetDir.toString,\n \"--input-file\",\n inputFile.toString\n ),\n Seq.empty\n )\n\n info(s\"output file '$outputFile' was created\")\n outputFile should exist\n\n info(s\"file looks like Verilog\")\n Source.fromFile(outputFile).getLines.mkString should include(\"endmodule\")\n\n }\n\n }\n\n}\n", "groundtruth": " outputFile.delete()\n\n val stage = new CIRCTStage\n\n stage.execute(\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.6, "category_reason": "val binding"} {"task_id": "chisel-circt", "path": "chisel-circt/src/test/scala/circtTests/stage/ChiselStageSpec.scala", "left_context": "// SPDX-License-Identifier: Apache-2.0\n\npackage circtTests.stage\n\nimport chisel3.stage.ChiselGeneratorAnnotation\n\nimport circt.stage.{ChiselStage, FirtoolOption, PreserveAggregate}\n\nimport firrtl.annotations.DeletedAnnotation\nimport firrtl.EmittedVerilogCircuitAnnotation\nimport firrtl.stage.FirrtlCircuitAnnotation\n\nimport java.io.File\n\nimport org.scalatest.funspec.AnyFunSpec\nimport org.scalatest.matchers.should.Matchers\n\nobject ChiselStageSpec {\n\n import chisel3._\n\n class FooBundle extends Bundle {\n val a = Input(Bool())\n val b = Output(Bool())\n }\n\n class Foo extends RawModule {\n val a = IO(new FooBundle)\n val b = IO(Flipped(new FooBundle))\n b <> a\n }\n\n class Bar extends RawModule {\n val sel = IO(Input(UInt(3.W)))\n val in = IO(Input(Vec(8, UInt(8.W))))\n val out = IO(Output(UInt(8.W)))\n out := in(sel)\n }\n\n class BazBundle extends Bundle {\n val a = Input(UInt(3.W))\n val b = Input(UInt(4.W))\n }\n\n class Baz extends RawModule {\n val in = IO(Input(new BazBundle))\n val out = IO(Output(new BazBundle))\n out := in\n }\n}\n\n/** A fixture used that exercises features of the Trace API.\n */\nclass TraceSpec {\n\n import chisel3._\n import chisel3.experimental.Trace\n import chisel3.util.experimental.InlineInstance\n\n /** A mutable Chisel reference to an internal wire inside Bar. This is done to enable later use of the Trace API to find this wire. */\n var id: Option[Bool] = None\n\n /** A submodule that will be inlined into the parent, Foo. */\n class Bar extends RawModule with InlineInstance {\n\n /** The wire that we want to trace. */\n val a = WireDefault(false.B)\n id = Some(a)\n dontTouch(a)\n Trace.traceName(a)\n }\n\n /** The top module. */\n class Foo extends RawModule {\n val bar = Module(new Bar)\n }\n\n}\n\nclass ChiselStageSpec extends AnyFunSpec with Matchers {\n\n describe(\"ChiselStage\") {\n\n it(\"should compile a Chisel module to FIRRTL dialect\") {\n\n val targetDir = new File(\"test_run_dir/ChiselStageSpec\")\n\n val args: Array[String] = Array(\n \"--target\",\n \"firrtl\",\n \"--target-dir\",\n targetDir.toString\n )\n\n val expectedOutput = new File(targetDir, \"Foo.fir.mlir\")\n expectedOutput.delete()\n\n (new ChiselStage).execute(args, Seq(ChiselGeneratorAnnotation(() => new ChiselStageSpec.Foo)))\n\n info(s\"'$expectedOutput' exists\")\n expectedOutput should (exist)\n\n }\n\n it(\"should compile a Chisel module to RTL dialect\") {\n\n val targetDir = new File(\"test_run_dir/ChiselStageSpec\")\n\n val args: Array[String] = Array(\n \"--target\",\n \"hw\",\n \"--target-dir\",\n targetDir.toString\n )\n\n val expectedOutput = new File(targetDir, \"Foo.hw.mlir\")\n expectedOutput.delete()\n\n (new ChiselStage).execute(args, Seq(ChiselGeneratorAnnotation(() => new ChiselStageSpec.Foo)))\n\n info(s\"'$expectedOutput' exists\")\n expectedOutput should (exist)\n\n }\n\n it(\"should compile a Chisel module to SystemVerilog\") {\n\n val targetDir = new File(\"test_run_dir/ChiselStageSpec\")\n\n val args: Array[String] = Array(\n \"--target\",\n \"systemverilog\",\n \"--target-dir\",\n targetDir.toString\n )\n\n val expectedOutput = new File(targetDir, \"Foo.sv\")\n expectedOutput.delete()\n\n (new ChiselStage)\n .execute(args, Seq(ChiselGeneratorAnnotation(() => new ChiselStageSpec.Foo)))\n .map {\n case DeletedAnnotation(_, a) => a\n case a => a\n }\n\n info(s\"'$expectedOutput' exists\")\n expectedOutput should (exist)\n\n }\n\n it(\"should support custom firtool options\") {\n val targetDir = new File(\"test_run_dir/ChiselStageSpec\")\n\n val args: Array[String] = Array(\n \"--target\",\n \"systemverilog\",\n \"--target-dir\",\n targetDir.toString\n )\n\n info(s\"output contains a case statement using --lowering-options=disallowPackedArrays\")\n (new ChiselStage)\n .execute(\n args,\n Seq(\n ChiselGeneratorAnnotation(() => new ChiselStageSpec.Bar),\n FirtoolOption(\"--lowering-options=disallowPackedArrays\")\n )\n )\n .collectFirst {\n case EmittedVerilogCircuitAnnotation(a) => a\n }\n .get\n .value should include(\"case\")\n }\n\n it(\"should support aggregate preservation mode\") {\n val targetDir = new File(\"test_run_dir/ChiselStageSpec\")\n\n val args: Array[String] = Array(\n \"--target\",\n \"systemverilog\",\n \"--target-dir\",\n targetDir.toString\n )\n\n info(s\"output contains a verilog struct using preserve-aggregate option\")\n (new ChiselStage)\n .execute(\n args,\n Seq(ChiselGeneratorAnnotation(() => new ChiselStageSpec.Baz), PreserveAggregate(PreserveAggregate.All))\n )\n .collectFirst {\n case EmittedVerilogCircuitAnnotation(a) => a\n }\n .get\n .value should include(\"struct\")\n }\n }\n\n describe(\"ChiselStage custom transform support\") {\n\n it(\"should work with InlineInstance\") {\n\n import chisel3._\n import chisel3.util.experimental.InlineInstance\n\n trait SimpleIO { this: RawModule =>\n val a = IO(Input(Bool()))\n val b = IO(Output(Bool()))\n }\n\n class Bar extends RawModule with SimpleIO with InlineInstance {\n b := ~a\n }\n\n class Foo extends RawModule with SimpleIO {\n val bar = Module(new Bar)\n bar.a := a\n b := bar.b\n }\n\n val targetDir = new File(\"test_run_dir/InlineInstance\")\n\n val args: Array[String] = Array(\n \"--target\",\n \"systemverilog\",\n \"--target-dir\",\n targetDir.toString\n )\n\n ((new ChiselStage)\n .execute(args, Seq(ChiselGeneratorAnnotation(() => new Foo)))\n .collectFirst {\n case EmittedVerilogCircuitAnnotation(a) => a\n }\n .get\n .value should not).include(\"module Bar\")\n }\n\n it(\"should work with FlattenInstance\") {\n\n import chisel3._\n import chisel3.util.experimental.FlattenInstance\n\n trait SimpleIO { this: RawModule =>\n val a = IO(Input(Bool()))\n val b = IO(Output(Bool()))\n }\n\n class Baz extends RawModule with SimpleIO {\n b := ~a\n }\n\n class Bar extends RawModule with SimpleIO {\n val baz = Module(new Baz)\n baz.a := a\n b := baz.b\n }\n\n class Foo extends RawModule with SimpleIO {\n val bar = Module(new Bar with FlattenInstance)\n bar.a := a\n b := bar.b\n }\n\n val targetDir = new File(\"test_run_dir/FlattenInstance\")\n\n val args: Array[String] = Array(\n \"--target\",\n \"systemverilog\",\n \"--target-dir\",\n targetDir.toString\n )\n\n val verilog = (new ChiselStage)\n .execute(args, Seq(ChiselGeneratorAnnotation(() => new Foo)))\n .collectFirst {\n case EmittedVerilogCircuitAnnotation(a) => a\n }\n .get\n .value\n\n (verilog should not).include(\"module Baz\")\n (verilog should not).include(\"module Bar\")\n\n }\n\n it(\"should work with the Trace API for unified output\") {\n\n import chisel3.experimental.Trace\n\n val fixture = new TraceSpec\n\n val targetDir = new File(\"test_run_dir/TraceAPIUnified\")\n\n val args: Array[String] = Array(\n \"--target\",\n \"systemverilog\",\n \"--target-dir\",\n targetDir.toString\n )\n\n val annos = (new ChiselStage).execute(\n args,\n Seq(\n ChiselGeneratorAnnotation(() => new fixture.Foo)\n )\n )\n\n val finalTargets = Trace.finalTarget(annos)(fixture.id.get)\n info(\"there is one final target\")\n finalTargets should have size (1)\n\n val expectedTarget = firrtl.annotations.CircuitTarget(\"Foo\").module(\"Foo\").ref(\"bar_a\")\n info(s\"the final target is $expectedTarget\")\n finalTargets.head should be(expectedTarget)\n\n }\n\n it(\"should work with the Trace API for split verilog output\") {\n\n import chisel3.experimental.Trace\n\n val fixture = new TraceSpec\n\n val targetDir = new File(\"test_run_dir/TraceAPISplit\")\n\n val args: Array[String] = Array(\n \"--target\",\n \"systemverilog\",\n \"--target-dir\",\n targetDir.toString\n )\n\n val annos = (new ChiselStage).execute(\n args,\n Seq(\n ChiselGeneratorAnnotation(() => new fixture.Foo),\n firrtl.EmitAllModulesAnnotation(classOf[firrtl.SystemVerilogEmitter])\n )\n )\n\n val finalTargets = Trace.finalTarget(annos)(fixture.id.get)\n info(\"there is one final target\")\n finalTargets should have size (1)\n\n val expectedTarget = firrtl.annotations.CircuitTarget(\"Foo\").module(\"Foo\").ref(\"bar_a\")\n info(s\"the final target is $expectedTarget\")\n finalTargets.head should be(expectedTarget)\n\n }\n\n }\n\n describe(\"ChiselStage DontTouchAnnotation support\") {\n\n it(\"should block removal of wires and nodes\") {\n\n import chisel3._\n\n class Foo extends RawModule {\n val a = IO(Input(Bool()))\n val b = IO(Output(Bool()))\n\n val w = WireDefault(a)\n dontTouch(w)\n\n val n = ~w\n dontTouch(n)\n\n b := n\n }\n\n val targetDir = new File(\"test_run_dir/DontTouch\")\n\n val args: Array[String] = Array(\n \"--target\",\n \"systemverilog\",\n \"--target-dir\",\n targetDir.toString\n )\n\n val verilog = (new ChiselStage)\n .execute(args, Seq(ChiselGeneratorAnnotation(() => new Foo)))\n .collectFirst {\n case EmittedVerilogCircuitAnnotation(a) => a\n }\n .get\n .value\n\n verilog should include(\"wire w\")\n verilog should include(\"wire n\")\n\n }\n\n }\n\n describe(\"ChiselStage forceName support\") {\n\n it(\"should work when forcing a module name\") {\n\n import chisel3._\n import chisel3.util.experimental.{forceName, InlineInstance}\n\n trait SimpleIO { this: RawModule =>\n val a = IO(Input(Bool()))\n val b = IO(Output(Bool()))\n }\n\n class Baz extends RawModule with SimpleIO {\n b := ~a\n }\n\n class Bar extends RawModule with SimpleIO with InlineInstance {\n val baz = Module(new Baz)\n baz.a := a\n b := baz.b\n }\n\n class Foo extends RawModule with SimpleIO {\n val bar = Module(new Bar)\n bar.a := a\n b := bar.b\n\n forceName(bar.baz)\n }\n\n val targetDir = new File(\"test_run_dir/ForceName\")\n\n val args: Array[String] = Array(\n \"--target\",\n \"systemverilog\",\n \"--target-dir\",\n targetDir.toString\n )\n\n val verilog: String = (new ChiselStage)\n .execute(args, Seq(ChiselGeneratorAnnotation(() => new Foo)))\n .collectFirst {\n case EmittedVerilogCircuitAnnotation(a) => a\n }\n .get\n .value\n\n verilog should include(\"module Baz\")\n\n }\n\n }\n\n describe(\"ChiselStage dedup behavior\") {\n\n it(\"should be on by default and work\") {\n\n import chisel3._\n\n class Baz extends RawModule {\n val a = IO(Input(Bool()))\n val b = IO(Output(Bool()))\n\n b := a\n }\n\n class Bar extends RawModule {\n val a = IO(Input(Bool()))\n val b = IO(Output(Bool()))\n\n b := a\n }\n\n class Foo extends RawModule {\n val a = IO(Input(Bool()))\n val b = IO(Output(Bool()))\n\n val bar = Module(new Bar)\n val baz = Module(new Baz)\n bar.a := a\n baz.a := a\n b := bar.b ^ baz.b\n }\n\n val targetDir = new File(\"test_run_dir/Dedup\")\n\n val args: Array[String] = Array(\n \"--target\",\n \"systemverilog\",\n \"--target-dir\",\n targetDir.toString\n )\n\n val verilog: String = (new ChiselStage)\n .execute(args, Seq(ChiselGeneratorAnnotation(() => new Foo)))\n .collectFirst {\n case EmittedVerilogCircuitAnnotation(a) => a\n }\n .get\n .value\n\n verilog should include(\"module Bar\")\n (verilog should not).include(\"module Baz\")\n\n }\n\n it(\"should respect the doNotDedup API\") {\n\n import chisel3._\n import chisel3.experimental.doNotDedup\n\n class Baz extends RawModule {\n val a = IO(Input(Bool()))\n val b = IO(Output(Bool()))\n\n b := a\n }\n\n class Bar extends RawModule {\n val a = IO(Input(Bool()))\n val b = IO(Output(Bool()))\n\n b := a\n }\n\n class Foo extends RawModule {\n val a = IO(Input(Bool()))\n val b = IO(Output(Bool()))\n\n val bar = Module(new Bar)\n val baz = Module(new Baz)\n bar.a := a\n baz.a := a\n b := bar.b ^ baz.b\n doNotDedup(baz)\n }\n\n val targetDir = new File(\"test_run_dir/Dedup\")\n\n val args: Array[String] = Array(\n \"--target\",\n \"systemverilog\",\n \"--target-dir\",\n targetDir.toString\n )\n\n val verilog: String = (new ChiselStage)\n .execute(args, Seq(ChiselGeneratorAnnotation(() => new Foo)))\n .collectFirst {\n case EmittedVerilogCircuitAnnotation(a) => a\n }\n .get\n .value\n\n verilog should include(\"module Bar\")\n verilog should include(\"module Baz\")\n\n }\n\n }\n\n describe(\"ChiselStage$\") {\n\n", "right_context": "\n }\n\n it(\"should emit SystemVerilog to string\") {\n\n ChiselStage.emitSystemVerilog(new ChiselStageSpec.Foo) should include(\"endmodule\")\n\n }\n it(\"should emit SystemVerilog to string with firtool options\") {\n\n val sv = ChiselStage\n .emitSystemVerilog(\n new ChiselStageSpec.Foo,\n firtoolOpts = Array(\"--strip-debug-info\")\n )\n (sv should not).include(\"// :\")\n\n }\n it(\"should emit SystemVerilog to string with chisel arguments and firtool options\") {\n\n val sv = ChiselStage.emitSystemVerilog(\n new ChiselStageSpec.Foo,\n Array(\"--show-registrations\"),\n Array(\"--strip-debug-info\")\n )\n sv should include(\"Generated by CIRCT\")\n\n }\n\n it(\"emitSystemVerilogFile should support custom Chisel args and firtool options\") {\n val targetDir = new File(\"test_run_dir/ChiselStageSpec/generated\")\n\n val args: Array[String] = Array(\n \"--target-dir\",\n targetDir.toString\n )\n\n info(s\"output contains a case statement using --lowering-options=disallowPackedArrays\")\n ChiselStage\n .emitSystemVerilogFile(\n new ChiselStageSpec.Bar,\n args,\n Array(\"--lowering-options=disallowPackedArrays\")\n )\n .collectFirst {\n case EmittedVerilogCircuitAnnotation(a) => a\n }\n .get\n .value should include(\"case\")\n\n val expectedOutput = new File(targetDir, \"Bar.sv\")\n expectedOutput should (exist)\n info(s\"'$expectedOutput' exists\")\n }\n\n }\n}\n", "groundtruth": " it(\"should emit FIRRTL dialect\") {\n\n ChiselStage.emitFIRRTLDialect(new ChiselStageSpec.Foo) should include(\" firrtl.module\")\n\n }\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "Pythia-HDL", "path": "Pythia-HDL/src/main/scala/pythia/IndexGen.scala", "left_context": "/**********************************************************\n * Author: Rahul Bera\n * Description: Implements the index generation circuitry\n * from state information\n * ********************************************************/\npackage pythia\n\nimport chisel3._\nimport chisel3.util._\n\nclass IndexGen (val iType:Int, val plane_offset:Int) extends Module {\n val io = IO(new Bundle {\n val pc = Input(UInt(32.W))\n val offset = Input(UInt(6.W))\n val delta_path = Input(UInt(32.W))\n val index = Output(UInt(7.W))\n })\n\n", "right_context": " val temp = (raw_val ^ plane_offset.asUInt)\n\n // Robert Jenkin's 32 bit mix function for hashing\n val t0 = temp + (temp << 12)\n val t1 = t0 ^ (temp >> 22)\n val t2 = t1 + (temp << 4)\n val t3 = t2 ^ (temp >> 9)\n val t4 = t3 + (temp << 10)\n val t5 = t4 ^ (temp >> 2)\n val t6 = t5 + (temp << 7)\n val t7 = t6 ^ (temp >> 12)\n\n // Modulo 128\n io.index := t7(6, 0)\n // printf(\"[INDEXGEN] index %d\\n\", io.index)\n}\n", "groundtruth": " val raw_val = if(iType == 1) {Cat(io.pc, io.offset)} else {io.delta_path}\n", "crossfile_context": "", "category": "Computation Block", "subcategory": "Type Casting and Conversion", "confidence": 0.75, "category_reason": "Cat/Fill operation"} {"task_id": "Pythia-HDL", "path": "Pythia-HDL/src/main/scala/pythia/MasterModule.scala", "left_context": "/**********************************************************\n * Author: Rahul Bera\n * Description: The top-level Pythia module which orchestrates everything\n * ********************************************************/\npackage pythia\n\nimport chisel3._\nimport chisel3.util._\n\nclass MasterModule extends Module\n{\n val io = IO(new Bundle {\n val sigUpdate = Input(Bool())\n val sigQuery = Input(Bool())\n // query inputs/outputs\n val qPC = Input(UInt(32.W))\n val qOffset = Input(UInt(6.W))\n val qDeltaPath = Input(UInt(32.W))\n val qAction = Output(UInt(4.W))\n // update input/outputs\n val uPC = Input(UInt(32.W))\n val uOffset = Input(UInt(6.W))\n val uDeltaPath = Input(UInt(32.W))\n val uAction = Input(UInt(4.W))\n val uReward = Input(UInt(8.W))\n })\n\n // Modules for PC+Offset feature\n val pcoIndexGen0 = Module(new IndexGen(iType = 1, plane_offset = 0xdead)) // index generator\n val pcoIndexGen1 = Module(new IndexGen(iType = 1, plane_offset = 0xdada)) // index generator\n val pcoIndexGen2 = Module(new IndexGen(iType = 1, plane_offset = 0xdeaf)) // index generator\n val vault0 = Module(new Vault()) // vault\n\n // Modules for delta_path feature\n val dpIndexGen0 = Module(new IndexGen(iType = 1, plane_offset = 0xdead)) // index generator\n val dpIndexGen1 = Module(new IndexGen(iType = 1, plane_offset = 0xdada)) // index generator\n val dpIndexGen2 = Module(new IndexGen(iType = 1, plane_offset = 0xdeaf)) // index generator\n val vault1 = Module(new Vault()) // vault\n\n // Global modules\n val qvcompare0 = Module(new QVCompare()) // Q-value comparator, one for each vault-read ports\n val qvcompare1 = Module(new QVCompare()) // Q-value comparator, one for each vault-read ports\n val max3 = Module(new MaxN()) // max reducer\n\n // machine states\n val ( s_idle\n :: s_update_planeR :: s_update_planeW\n :: s_query_read2 :: s_query_read4 :: s_query_read6 :: s_query_read8 :: s_query_read10 :: s_query_read12 :: s_query_read14 :: s_query_read16\n :: Nil) = Enum(11)\n val state = RegInit(s_idle)\n\n val update_reward = RegEnable(io.uReward, io.sigUpdate)\n\n //=========== Connections for PC+Offset Index Generation Modules ============//\n pcoIndexGen0.io.pc := Mux(io.sigUpdate, io.uPC, io.qPC)\n pcoIndexGen0.io.offset := Mux(io.sigUpdate, io.uOffset, io.qOffset)\n pcoIndexGen0.io.delta_path <> DontCare\n pcoIndexGen1.io.pc := Mux(io.sigUpdate, io.uPC, io.qPC)\n pcoIndexGen1.io.offset := Mux(io.sigUpdate, io.uOffset, io.qOffset)\n pcoIndexGen1.io.delta_path <> DontCare\n pcoIndexGen2.io.pc := Mux(io.sigUpdate, io.uPC, io.qPC)\n pcoIndexGen2.io.offset := Mux(io.sigUpdate, io.uOffset, io.qOffset)\n pcoIndexGen2.io.delta_path <> DontCare\n //===========================================================================//\n\n //========== Connections for Delta_path Index Generation Modules ============//\n dpIndexGen0.io.pc <> DontCare\n dpIndexGen0.io.offset <> DontCare\n dpIndexGen0.io.delta_path := Mux(io.sigUpdate, io.uDeltaPath, io.qDeltaPath)\n dpIndexGen1.io.pc <> DontCare\n dpIndexGen1.io.offset <> DontCare\n dpIndexGen1.io.delta_path := Mux(io.sigUpdate, io.uDeltaPath, io.qDeltaPath)\n dpIndexGen2.io.pc <> DontCare\n dpIndexGen2.io.offset <> DontCare\n dpIndexGen2.io.delta_path := Mux(io.sigUpdate, io.uDeltaPath, io.qDeltaPath)\n //===========================================================================//\n\n //====================== Connections for PC+Offset Vault Module =======================//\n when(io.sigUpdate){\n vault0.io.rdrow0(0) := pcoIndexGen0.io.index; vault0.io.rdrow0(1) := pcoIndexGen1.io.index; vault0.io.rdrow0(2) := pcoIndexGen2.io.index;\n }.elsewhen(io.sigQuery){\n vault0.io.rdrow0(0) := pcoIndexGen0.io.index; vault0.io.rdrow0(1) := pcoIndexGen1.io.index; vault0.io.rdrow0(2) := pcoIndexGen2.io.index;\n }.otherwise{\n vault0.io.rdrow0(0) := 0.U; vault0.io.rdrow0(1) := 0.U; vault0.io.rdrow0(2) := 0.U;\n }\n\n when(io.sigUpdate){\n vault0.io.rdcol0 := io.uAction\n }.elsewhen(io.sigQuery){\n when(state === s_query_read2) { vault0.io.rdcol0 := 0.U }\n .elsewhen(state === s_query_read4) { vault0.io.rdcol0 := 2.U }\n .elsewhen(state === s_query_read6) { vault0.io.rdcol0 := 4.U }\n .elsewhen(state === s_query_read8) { vault0.io.rdcol0 := 6.U }\n .elsewhen(state === s_query_read10) { vault0.io.rdcol0 := 8.U }\n .elsewhen(state === s_query_read12) { vault0.io.rdcol0 := 10.U }\n", "right_context": " .elsewhen(state === s_query_read16) { vault0.io.rdcol0 := 14.U }\n .otherwise { vault0.io.rdcol0 := 0.U }\n }.otherwise{\n vault0.io.rdcol0 := 0.U\n }\n\n when(io.sigUpdate){\n vault0.io.rdrow1(0) := 0.U; vault0.io.rdrow1(1) := 0.U; vault0.io.rdrow1(2) := 0.U;\n }.elsewhen(io.sigQuery){\n vault0.io.rdrow1(0) := pcoIndexGen0.io.index; vault0.io.rdrow1(1) := pcoIndexGen1.io.index; vault0.io.rdrow1(2) := pcoIndexGen2.io.index;\n }.otherwise{\n vault0.io.rdrow1(0) := 0.U; vault0.io.rdrow1(1) := 0.U; vault0.io.rdrow1(2) := 0.U;\n }\n\n when(io.sigUpdate){\n vault0.io.rdcol1 := 0.U\n }.elsewhen(io.sigQuery){\n when(state === s_query_read2) { vault0.io.rdcol1 := 1.U }\n .elsewhen(state === s_query_read4) { vault0.io.rdcol1 := 3.U }\n .elsewhen(state === s_query_read6) { vault0.io.rdcol1 := 5.U }\n .elsewhen(state === s_query_read8) { vault0.io.rdcol1 := 7.U }\n .elsewhen(state === s_query_read10) { vault0.io.rdcol1 := 9.U }\n .elsewhen(state === s_query_read12) { vault0.io.rdcol1 := 11.U }\n .elsewhen(state === s_query_read14) { vault0.io.rdcol1 := 13.U }\n .elsewhen(state === s_query_read16) { vault0.io.rdcol1 := 15.U }\n .otherwise { vault0.io.rdcol1 := 0.U }\n }.otherwise{\n vault0.io.rdcol1 := 0.U\n }\n\n vault0.io.re := false.B\n\n vault0.io.wrrow(0) := RegEnable(pcoIndexGen0.io.index, io.sigUpdate); vault0.io.wrrow(1) := RegEnable(pcoIndexGen1.io.index, io.sigUpdate); vault0.io.wrrow(2) := RegEnable(pcoIndexGen2.io.index, io.sigUpdate);\n vault0.io.wrcol := RegEnable(io.uAction, io.sigUpdate)\n vault0.io.wrdata(0) := RegEnable((vault0.io.rddata0(0) >> 1) + update_reward, state === s_update_planeR)\n vault0.io.wrdata(1) := RegEnable((vault0.io.rddata0(1) >> 1) + update_reward, state === s_update_planeR)\n vault0.io.wrdata(2) := RegEnable((vault0.io.rddata0(2) >> 1) + update_reward, state === s_update_planeR)\n vault0.io.we := false.B\n //======================================================================================//\n\n //====================== Connections for Delta_path Vault Module =======================//\n when(io.sigUpdate){\n vault1.io.rdrow0(0) := dpIndexGen0.io.index; vault1.io.rdrow0(1) := dpIndexGen1.io.index; vault1.io.rdrow0(2) := dpIndexGen2.io.index;\n }.elsewhen(io.sigQuery){\n vault1.io.rdrow0(0) := dpIndexGen0.io.index; vault1.io.rdrow0(1) := dpIndexGen1.io.index; vault1.io.rdrow0(2) := dpIndexGen2.io.index;\n }.otherwise{\n vault1.io.rdrow0(0) := 0.U; vault1.io.rdrow0(1) := 0.U; vault1.io.rdrow0(2) := 0.U;\n }\n\n when(io.sigUpdate){\n vault1.io.rdcol0 := io.uAction\n }.elsewhen(io.sigQuery){\n when(state === s_query_read2) { vault1.io.rdcol0 := 0.U }\n .elsewhen(state === s_query_read4) { vault1.io.rdcol0 := 2.U }\n .elsewhen(state === s_query_read6) { vault1.io.rdcol0 := 4.U }\n .elsewhen(state === s_query_read8) { vault1.io.rdcol0 := 6.U }\n .elsewhen(state === s_query_read10) { vault1.io.rdcol0 := 8.U }\n .elsewhen(state === s_query_read12) { vault1.io.rdcol0 := 10.U }\n .elsewhen(state === s_query_read14) { vault1.io.rdcol0 := 12.U }\n .elsewhen(state === s_query_read16) { vault1.io.rdcol0 := 14.U }\n .otherwise { vault1.io.rdcol0 := 0.U }\n }.otherwise{\n vault1.io.rdcol0 := 0.U\n }\n\n when(io.sigUpdate){\n vault1.io.rdrow1(0) := 0.U; vault1.io.rdrow1(1) := 0.U; vault1.io.rdrow1(2) := 0.U;\n }.elsewhen(io.sigQuery){\n vault1.io.rdrow1(0) := dpIndexGen0.io.index; vault1.io.rdrow1(1) := dpIndexGen1.io.index; vault1.io.rdrow1(2) := dpIndexGen2.io.index;\n }.otherwise{\n vault1.io.rdrow1(0) := 0.U; vault1.io.rdrow1(1) := 0.U; vault1.io.rdrow1(2) := 0.U;\n }\n\n when(io.sigUpdate){\n vault1.io.rdcol1 := 0.U\n }.elsewhen(io.sigQuery){\n when(state === s_query_read2) { vault1.io.rdcol1 := 1.U }\n .elsewhen(state === s_query_read4) { vault1.io.rdcol1 := 3.U }\n .elsewhen(state === s_query_read6) { vault1.io.rdcol1 := 5.U }\n .elsewhen(state === s_query_read8) { vault1.io.rdcol1 := 7.U }\n .elsewhen(state === s_query_read10) { vault1.io.rdcol1 := 9.U }\n .elsewhen(state === s_query_read12) { vault1.io.rdcol1 := 11.U }\n .elsewhen(state === s_query_read14) { vault1.io.rdcol1 := 13.U }\n .elsewhen(state === s_query_read16) { vault1.io.rdcol1 := 15.U }\n .otherwise { vault1.io.rdcol1 := 0.U }\n }.otherwise{\n vault1.io.rdcol1 := 0.U\n }\n\n vault1.io.re := false.B\n\n vault1.io.wrrow(0) := RegEnable(dpIndexGen0.io.index, io.sigUpdate); vault1.io.wrrow(1) := RegEnable(dpIndexGen1.io.index, io.sigUpdate); vault1.io.wrrow(2) := RegEnable(dpIndexGen2.io.index, io.sigUpdate);\n vault1.io.wrcol := RegEnable(io.uAction, io.sigUpdate)\n vault1.io.wrdata(0) := RegEnable((vault1.io.rddata0(0) >> 1) + update_reward, state === s_update_planeR)\n vault1.io.wrdata(1) := RegEnable((vault1.io.rddata0(1) >> 1) + update_reward, state === s_update_planeR)\n vault1.io.wrdata(2) := RegEnable((vault1.io.rddata0(2) >> 1) + update_reward, state === s_update_planeR)\n vault1.io.we := false.B\n //=============================================================================//\n\n //===================== Connections for QVCompare Module0 =====================//\n when(io.sigQuery){\n when(state === s_idle) {qvcompare0.io.qv0_p0 := 0.U}\n .otherwise {qvcompare0.io.qv0_p0 := vault0.io.rddata0(0)}\n }.otherwise{\n qvcompare0.io.qv0_p0 := 0.U\n }\n when(io.sigQuery){\n when(state === s_idle) {qvcompare0.io.qv0_p1 := 0.U}\n .otherwise {qvcompare0.io.qv0_p1 := vault0.io.rddata0(1)}\n }.otherwise{\n qvcompare0.io.qv0_p1 := 0.U\n }\n when(io.sigQuery){\n when(state === s_idle) {qvcompare0.io.qv0_p2 := 0.U}\n .otherwise {qvcompare0.io.qv0_p2 := vault0.io.rddata0(2)}\n }.otherwise{\n qvcompare0.io.qv0_p2 := 0.U\n }\n\n when(io.sigQuery){\n when(state === s_idle) {qvcompare0.io.qv1_p0 := 0.U}\n .otherwise {qvcompare0.io.qv1_p0 := vault1.io.rddata0(0)}\n }.otherwise{\n qvcompare0.io.qv1_p0 := 0.U\n }\n when(io.sigQuery){\n when(state === s_idle) {qvcompare0.io.qv1_p1 := 0.U}\n .otherwise {qvcompare0.io.qv1_p1 := vault1.io.rddata0(1)}\n }.otherwise{\n qvcompare0.io.qv1_p1 := 0.U\n }\n when(io.sigQuery){\n when(state === s_idle) {qvcompare0.io.qv1_p2 := 0.U}\n .otherwise {qvcompare0.io.qv1_p2 := vault1.io.rddata0(2)}\n }.otherwise{\n qvcompare0.io.qv1_p2 := 0.U\n }\n // Add delta path signature's QV values here\n // qvcompare0.io.qv1_p0 := 0.U\n // qvcompare0.io.qv1_p1 := 0.U\n // qvcompare0.io.qv1_p2 := 0.U\n //============================================================================//\n\n //===================== Connections for QVCompare Module1 =====================//\n when(io.sigQuery){\n when(state === s_idle) {qvcompare1.io.qv0_p0 := 0.U}\n .otherwise {qvcompare1.io.qv0_p0 := vault0.io.rddata1(0)}\n }.otherwise{\n qvcompare1.io.qv0_p0 := 0.U\n }\n when(io.sigQuery){\n when(state === s_idle) {qvcompare1.io.qv0_p1 := 0.U}\n .otherwise {qvcompare1.io.qv0_p1 := vault0.io.rddata1(1)}\n }.otherwise{\n qvcompare1.io.qv0_p1 := 0.U\n }\n when(io.sigQuery){\n when(state === s_idle) {qvcompare1.io.qv0_p2 := 0.U}\n .otherwise {qvcompare1.io.qv0_p2 := vault0.io.rddata1(2)}\n }.otherwise{\n qvcompare1.io.qv0_p2 := 0.U\n }\n\n when(io.sigQuery){\n when(state === s_idle) {qvcompare1.io.qv1_p0 := 0.U}\n .otherwise {qvcompare1.io.qv1_p0 := vault1.io.rddata1(0)}\n }.otherwise{\n qvcompare1.io.qv1_p0 := 0.U\n }\n when(io.sigQuery){\n when(state === s_idle) {qvcompare1.io.qv1_p1 := 0.U}\n .otherwise {qvcompare1.io.qv1_p1 := vault1.io.rddata1(1)}\n }.otherwise{\n qvcompare1.io.qv1_p1 := 0.U\n }\n when(io.sigQuery){\n when(state === s_idle) {qvcompare1.io.qv1_p2 := 0.U}\n .otherwise {qvcompare1.io.qv1_p2 := vault1.io.rddata1(2)}\n }.otherwise{\n qvcompare1.io.qv1_p2 := 0.U\n }\n // Add delta path signature's QV values here\n // qvcompare1.io.qv1_p0 := 0.U\n // qvcompare1.io.qv1_p1 := 0.U\n // qvcompare1.io.qv1_p2 := 0.U\n //============================================================================//\n\n //========================= Connections for Max Module =======================//\n when(io.sigQuery){\n when(state === s_idle) {max3.io.nums(0) := 0.U}\n .otherwise {max3.io.nums(0) := RegNext(max3.io.maxNum)}\n }.otherwise{\n max3.io.nums(0) := 0.U\n }\n when(io.sigQuery){\n max3.io.nums(1) := qvcompare0.io.qv_out\n }.otherwise{\n max3.io.nums(1) := 0.U\n }\n when(io.sigQuery){\n max3.io.nums(2) := qvcompare1.io.qv_out\n }.otherwise{\n max3.io.nums(2) := 0.U\n }\n\n when(io.sigQuery){\n when(state === s_idle) {max3.io.ids(0) := 0.U}\n .otherwise {max3.io.ids(0) := RegNext(max3.io.maxId)}\n }.otherwise{\n max3.io.ids(0) := 0.U\n }\n when(io.sigQuery){\n when(state === s_query_read2) {max3.io.ids(1) := 0.U}\n .elsewhen(state === s_query_read4) {max3.io.ids(1) := 2.U}\n .elsewhen(state === s_query_read6) {max3.io.ids(1) := 4.U}\n .elsewhen(state === s_query_read8) {max3.io.ids(1) := 6.U}\n .elsewhen(state === s_query_read10) {max3.io.ids(1) := 8.U}\n .elsewhen(state === s_query_read12) {max3.io.ids(1) := 10.U}\n .elsewhen(state === s_query_read14) {max3.io.ids(1) := 12.U}\n .elsewhen(state === s_query_read16) {max3.io.ids(1) := 14.U}\n .otherwise {max3.io.ids(1) := 0.U}\n }.otherwise{\n max3.io.ids(1) := 0.U\n }\n when(io.sigQuery){\n when(state === s_query_read2) {max3.io.ids(2) := 1.U}\n .elsewhen(state === s_query_read4) {max3.io.ids(2) := 3.U}\n .elsewhen(state === s_query_read6) {max3.io.ids(2) := 5.U}\n .elsewhen(state === s_query_read8) {max3.io.ids(2) := 7.U}\n .elsewhen(state === s_query_read10) {max3.io.ids(2) := 9.U}\n .elsewhen(state === s_query_read12) {max3.io.ids(2) := 11.U}\n .elsewhen(state === s_query_read14) {max3.io.ids(2) := 13.U}\n .elsewhen(state === s_query_read16) {max3.io.ids(2) := 15.U}\n .otherwise {max3.io.ids(2) := 0.U}\n }.otherwise{\n max3.io.ids(2) := 0.U\n }\n //=====================================================================//\n\n // Output Connection\n io.qAction := Mux(io.sigQuery && state === s_query_read16, max3.io.maxId, 0.U)\n\n\n\n // *********************************************************************//\n // *********************** STATE MACHINE DEFINITION ********************//\n // *********************************************************************//\n when(state === s_idle){\n // printf(\"[IDLE] ================ CHILLING HOMES ===============\\n\")\n vault0.io.re := false.B\n vault0.io.we := false.B\n vault1.io.re := false.B\n vault1.io.we := false.B\n when (io.sigUpdate){\n state := s_update_planeR\n }.elsewhen(io.sigQuery){\n state := s_query_read2\n }\n }\n .elsewhen(state === s_update_planeR){\n vault0.io.re := true.B // read the old value from plane\n vault0.io.we := false.B\n vault1.io.re := true.B // read the old value from plane\n vault1.io.we := false.B\n state := s_update_planeW\n // printf(\"[UPDATE-VAULT0-R-PLANE-0] row %d col %d value-read %d\\n\", vault0.io.rdrow0(0), vault0.io.rdcol0, vault0.io.rddata0(0))\n // printf(\"[UPDATE-VAULT0-R-PLANE-1] row %d col %d value-read %d\\n\", vault0.io.rdrow0(1), vault0.io.rdcol0, vault0.io.rddata0(1))\n // printf(\"[UPDATE-VAULT0-R-PLANE-2] row %d col %d value-read %d\\n\", vault0.io.rdrow0(2), vault0.io.rdcol0, vault0.io.rddata0(2))\n // printf(\"[UPDATE-VAULT1-R-PLANE-0] row %d col %d value-read %d\\n\", vault1.io.rdrow0(0), vault1.io.rdcol0, vault1.io.rddata0(0))\n // printf(\"[UPDATE-VAULT1-R-PLANE-1] row %d col %d value-read %d\\n\", vault1.io.rdrow0(1), vault1.io.rdcol0, vault1.io.rddata0(1))\n // printf(\"[UPDATE-VAULT1-R-PLANE-2] row %d col %d value-read %d\\n\", vault1.io.rdrow0(2), vault1.io.rdcol0, vault1.io.rddata0(2))\n }\n .elsewhen(state === s_update_planeW){\n vault0.io.re := false.B\n vault0.io.we := true.B // write the new value\n vault1.io.re := false.B\n vault1.io.we := true.B // write the new value\n state := s_idle\n // printf(\"[UPDATE-VAULT0-W-PLANE-0] row %d col %d value-written %d\\n\", vault0.io.wrrow(0), vault0.io.wrcol, vault0.io.wrdata(0))\n // printf(\"[UPDATE-VAULT0-W-PLANE-1] row %d col %d value-written %d\\n\", vault0.io.wrrow(1), vault0.io.wrcol, vault0.io.wrdata(1))\n // printf(\"[UPDATE-VAULT0-W-PLANE-2] row %d col %d value-written %d\\n\", vault0.io.wrrow(2), vault0.io.wrcol, vault0.io.wrdata(2))\n // printf(\"[UPDATE-VAULT1-W-PLANE-0] row %d col %d value-written %d\\n\", vault1.io.wrrow(0), vault1.io.wrcol, vault1.io.wrdata(0))\n // printf(\"[UPDATE-VAULT1-W-PLANE-1] row %d col %d value-written %d\\n\", vault1.io.wrrow(1), vault1.io.wrcol, vault1.io.wrdata(1))\n // printf(\"[UPDATE-VAULT1-W-PLANE-2] row %d col %d value-written %d\\n\", vault1.io.wrrow(2), vault1.io.wrcol, vault1.io.wrdata(2))\n }\n // query state transitions\n .elsewhen(state === s_query_read2 || state === s_query_read4 || state === s_query_read6 || state === s_query_read8 || state === s_query_read10 || state === s_query_read12 || state === s_query_read14 || state === s_query_read16){\n vault0.io.re := true.B\n vault1.io.re := true.B\n // printf(\"[QUERY-VAULT0-PLANE-0] row0 %d col0 %d val0 %d\\n\", vault0.io.rdrow0(0), vault0.io.rdcol0, vault0.io.rddata0(0))\n // printf(\"[QUERY-VAULT0-PLANE-1] row0 %d col0 %d val0 %d\\n\", vault0.io.rdrow0(1), vault0.io.rdcol0, vault0.io.rddata0(1))\n // printf(\"[QUERY-VAULT0-PLANE-2] row0 %d col0 %d val0 %d\\n\", vault0.io.rdrow0(2), vault0.io.rdcol0, vault0.io.rddata0(2))\n // printf(\"[QUERY-VAULT0-PLANE-0] row1 %d col1 %d val1 %d\\n\", vault0.io.rdrow1(0), vault0.io.rdcol1, vault0.io.rddata1(0))\n // printf(\"[QUERY-VAULT0-PLANE-1] row1 %d col1 %d val1 %d\\n\", vault0.io.rdrow1(1), vault0.io.rdcol1, vault0.io.rddata1(1))\n // printf(\"[QUERY-VAULT0-PLANE-2] row1 %d col1 %d val1 %d\\n\", vault0.io.rdrow1(2), vault0.io.rdcol1, vault0.io.rddata1(2))\n //\n // printf(\"[QUERY-VAULT1-PLANE-0] row0 %d col0 %d val0 %d\\n\", vault1.io.rdrow0(0), vault1.io.rdcol0, vault1.io.rddata0(0))\n // printf(\"[QUERY-VAULT1-PLANE-1] row0 %d col0 %d val0 %d\\n\", vault1.io.rdrow0(1), vault1.io.rdcol0, vault1.io.rddata0(1))\n // printf(\"[QUERY-VAULT1-PLANE-2] row0 %d col0 %d val0 %d\\n\", vault1.io.rdrow0(2), vault1.io.rdcol0, vault1.io.rddata0(2))\n // printf(\"[QUERY-VAULT1-PLANE-0] row1 %d col1 %d val1 %d\\n\", vault1.io.rdrow1(0), vault1.io.rdcol1, vault1.io.rddata1(0))\n // printf(\"[QUERY-VAULT1-PLANE-1] row1 %d col1 %d val1 %d\\n\", vault1.io.rdrow1(1), vault1.io.rdcol1, vault1.io.rddata1(1))\n // printf(\"[QUERY-VAULT1-PLANE-2] row1 %d col1 %d val1 %d\\n\", vault1.io.rdrow1(2), vault1.io.rdcol1, vault1.io.rddata1(2))\n //\n // printf(\"[QUERY-VAULT0] max3 %d maxId %d\\n\", max3.io.maxNum, max3.io.maxId)\n\n when(state === s_query_read2) { state := s_query_read4 }\n .elsewhen(state === s_query_read4) { state := s_query_read6 }\n .elsewhen(state === s_query_read6) { state := s_query_read8 }\n .elsewhen(state === s_query_read8) { state := s_query_read10 }\n .elsewhen(state === s_query_read10) { state := s_query_read12 }\n .elsewhen(state === s_query_read12) { state := s_query_read14 }\n .elsewhen(state === s_query_read14) { state := s_query_read16 }\n .elsewhen(state === s_query_read16) { state := s_idle }\n .otherwise { state := s_idle }\n }\n // *********************************************************************//\n}\n", "groundtruth": " .elsewhen(state === s_query_read14) { vault0.io.rdcol0 := 12.U }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": ".elsewhen conditional"} {"task_id": "Pythia-HDL", "path": "Pythia-HDL/src/main/scala/pythia/MaxN.scala", "left_context": "/* Author: computes Max of N numbers */\npackage pythia\n\nimport chisel3._\n\nclass MaxN extends Module\n{\n // private def Max2(x:UInt, y:UInt) = Mux(x>=y, x, y)\n\n val io = IO(new Bundle{\n val nums = Input(Vec(3, UInt(16.W)))\n val ids = Input(Vec(3, UInt(4.W)))\n val maxNum = Output(UInt(16.W))\n val maxId = Output(UInt(4.W))\n })\n\n io.maxNum := 0.U\n io.maxId := 0.U\n\n // TODO: make the ugly definition more generic\n when(io.nums(0) >= io.nums(1)){\n when(io.nums(0) >= io.nums(2)){\n io.maxId := io.ids(0)\n io.maxNum := io.nums(0)\n }.otherwise{\n io.maxId := io.ids(2)\n io.maxNum := io.nums(2)\n }\n }.otherwise{\n when(io.nums(1) >= io.nums(2)){\n", "right_context": "}\n", "groundtruth": " io.maxId := io.ids(1)\n io.maxNum := io.nums(1)\n }.otherwise{\n io.maxId := io.ids(2)\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.8, "category_reason": ".otherwise clause"} {"task_id": "Pythia-HDL", "path": "Pythia-HDL/src/main/scala/pythia/Plane.scala", "left_context": "/**********************************************************\n * Author: Rahul Bera\n * Description: Implements a 128x16 plane of QVStore\n * Read ports: 2\n * Write ports: 1\n * ********************************************************/\n\npackage pythia\n\nimport chisel3._\nimport chisel3.util._\n\nclass Plane extends Module {\n val io = IO(new Bundle {\n val we = Input(Bool())\n val wrrow = Input(UInt(7.W))\n val wrcol = Input(UInt(4.W))\n val wrdata = Input(UInt(16.W))\n val re = Input(Bool())\n val rdrow0 = Input(UInt(7.W))\n val rdcol0 = Input(UInt(4.W))\n val rddata0 = Output(UInt(16.W))\n val rdrow1 = Input(UInt(7.W))\n val rdcol1 = Input(UInt(4.W))\n val rddata1 = Output(UInt(16.W))\n })\n\n val mem = Mem(2048, UInt(16.W))\n\n val rdindex0 = Wire(UInt(11.W))\n val rdindex1 = Wire(UInt(11.W))\n val wrindex = Wire(UInt(11.W))\n rdindex0 := (io.rdrow0 << 4) + io.rdcol0\n rdindex1 := (io.rdrow1 << 4) + io.rdcol1\n", "right_context": " when(io.re) {\n io.rddata0 := mem(rdindex0)\n io.rddata1 := mem(rdindex1)\n // printf(\"[PLANE READ] row0 %d col0 %d index0 %d val %d\\n\", io.rdrow0, io.rdcol0, rdindex0, io.rddata0)\n // printf(\"[PLANE READ] row1 %d col1 %d index1 %d val %d\\n\", io.rdrow1, io.rdcol1, rdindex1, io.rddata1)\n }\n}\n", "groundtruth": " wrindex := (io.wrrow << 4) + io.wrcol\n\n when(io.we) {\n mem(wrindex) := io.wrdata\n // printf(\"[PLANE WRITE] row %d col %d index %d val %d\\n\", io.wrrow, io.wrcol, wrindex, io.wrdata)\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "Pythia-HDL", "path": "Pythia-HDL/src/main/scala/pythia/QVCompare.scala", "left_context": "/*******************************************************************\n * Author: Rahul Bera\n * Description: This is purely combinatorial circuit\n * Given two sets of partial Q-values read from each vault,\n * this circuit sums up all partial Q-values for a given feature\n * and compares a max across Q-values of all features\n * *****************************************************************/\npackage pythia\n\nimport chisel3._\nimport chisel3.util._\n\nclass QVCompare extends Module{\n val io = IO(new Bundle{\n val qv0_p0 = Input(UInt(16.W))\n val qv0_p1 = Input(UInt(16.W))\n val qv0_p2 = Input(UInt(16.W))\n val qv1_p0 = Input(UInt(16.W))\n val qv1_p1 = Input(UInt(16.W))\n val qv1_p2 = Input(UInt(16.W))\n val qv_out = Output(UInt(16.W))\n })\n", "right_context": "\n io.qv_out := Mux(qv0 > qv1, qv0, qv1)\n}\n", "groundtruth": "\n val qv0 = io.qv0_p0 + io.qv0_p1 + io.qv0_p2\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.6, "category_reason": "val binding"} {"task_id": "Pythia-HDL", "path": "Pythia-HDL/src/main/scala/pythia/Valut.scala", "left_context": "/**********************************************************\n * Author: Rahul Bera\n * Description: Implements a valut of a QVStore.\n * Num of planes in a valut: 3\n * Each plane supports two read ports, and one write port\n * ********************************************************/\npackage pythia\n\nimport chisel3._\nimport chisel3.util._\n\nclass Vault extends Module {\n val io = IO(new Bundle{\n val re = Input(Bool())\n val rdrow0 = Input(Vec(3, UInt(7.W)))\n val rdcol0 = Input(UInt(4.W))\n", "right_context": " val rddata1 = Output(Vec(3, UInt(16.W)))\n val we = Input(Bool())\n val wrrow = Input(Vec(3, UInt(7.W)))\n val wrcol = Input(UInt(4.W))\n val wrdata = Input(Vec(3, UInt(16.W)))\n })\n\n // constituent planes\n val plane0 = Module(new Plane())\n val plane1 = Module(new Plane())\n val plane2 = Module(new Plane())\n\n plane0.io.rdrow0 := io.rdrow0(0)\n plane0.io.rdcol0 := io.rdcol0\n plane0.io.rdrow1 := io.rdrow1(0)\n plane0.io.rdcol1 := io.rdcol1\n plane0.io.re := io.re\n\n plane1.io.rdrow0 := io.rdrow0(1)\n plane1.io.rdcol0 := io.rdcol0\n plane1.io.rdrow1 := io.rdrow1(1)\n plane1.io.rdcol1 := io.rdcol1\n plane1.io.re := io.re\n\n plane2.io.rdrow0 := io.rdrow0(2)\n plane2.io.rdcol0 := io.rdcol0\n plane2.io.rdrow1 := io.rdrow1(2)\n plane2.io.rdcol1 := io.rdcol1\n plane2.io.re := io.re\n\n // Return a vector of read data\n io.rddata0(0) := plane0.io.rddata0\n io.rddata0(1) := plane1.io.rddata0\n io.rddata0(2) := plane2.io.rddata0\n io.rddata1(0) := plane0.io.rddata1\n io.rddata1(1) := plane1.io.rddata1\n io.rddata1(2) := plane2.io.rddata1\n\n plane0.io.wrrow := io.wrrow(0)\n plane0.io.wrcol := io.wrcol\n plane0.io.wrdata := io.wrdata(0)\n plane0.io.we := io.we\n\n plane1.io.wrrow := io.wrrow(1)\n plane1.io.wrcol := io.wrcol\n plane1.io.wrdata := io.wrdata(1)\n plane1.io.we := io.we\n\n plane2.io.wrrow := io.wrrow(2)\n plane2.io.wrcol := io.wrcol\n plane2.io.wrdata := io.wrdata(2)\n plane2.io.we := io.we\n}\n", "groundtruth": " val rdrow1 = Input(Vec(3, UInt(7.W)))\n val rdcol1 = Input(UInt(4.W))\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.8, "category_reason": "Input or Output in Bundle/IO context"} {"task_id": "Pythia-HDL", "path": "Pythia-HDL/src/test/scala/pythia/Launcher.scala", "left_context": "// See LICENSE.txt for license details.\npackage pythia\n\nimport chisel3._\nimport chisel3.iotesters.{Driver, TesterOptionsManager}\nimport utils.PythiaRunner\n\nobject Launcher {\n val tests = Map(\n \"IndexGen\" -> { (manager: TesterOptionsManager) =>\n Driver.execute(() => new IndexGen(iType = 1, plane_offset = 0xdead), manager) {\n (c) => new IndexGenTests(c)\n }\n },\n \"MaxN\" -> { (manager: TesterOptionsManager) =>\n Driver.execute(() => new MaxN(), manager) {\n (c) => new MaxNTests(c)\n }\n },\n \"Plane\" -> { (manager: TesterOptionsManager) =>\n Driver.execute(() => new Plane(), manager) {\n (c) => new PlaneTests(c)\n }\n },\n \"Vault\" -> { (manager: TesterOptionsManager) =>\n Driver.execute(() => new Vault(), manager) {\n (c) => new VaultTests(c)\n }\n },\n \"MasterModule\" -> { (manager: TesterOptionsManager) =>\n Driver.execute(() => new MasterModule(), manager) {\n (c) => new MasterModuleTests(c)\n }\n },\n \"QVCompare\" -> { (manager: TesterOptionsManager) =>\n Driver.execute(() => new QVCompare(), manager) {\n (c) => new QVCompareTests(c)\n }\n }\n )\n\n", "right_context": "", "groundtruth": " def main(args: Array[String]): Unit = {\n PythiaRunner(\"pythia\", tests, args)\n }\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "Pythia-HDL", "path": "Pythia-HDL/src/test/scala/pythia/MasterModuleTests.scala", "left_context": "package pythia\n\nimport chisel3.iotesters.{PeekPokeTester, Driver, ChiselFlatSpec}\n\nclass MasterModuleTests(c: MasterModule) extends PeekPokeTester(c) {\n\n def updateQVStore(pc:Int, offset:Int, delta_path:Int, action:Int, reward:Int) = {\n poke(c.io.uPC, pc)\n poke(c.io.uOffset, offset)\n poke(c.io.uDeltaPath, delta_path)\n poke(c.io.uAction, action)\n poke(c.io.uReward, reward)\n poke(c.io.sigUpdate, 1)\n", "right_context": " def queryQVStore(pc:Int, offset:Int, delta_path:Int, action:Int) = {\n poke(c.io.qPC, pc)\n poke(c.io.qOffset, offset)\n poke(c.io.qDeltaPath, delta_path)\n poke(c.io.sigQuery, 1)\n step(8)\n expect(c.io.qAction, action)\n poke(c.io.sigQuery, 0)\n // step(1)\n }\n\n val pc = 0x7fff3028\n val delta_path = 0x00000219\n updateQVStore(pc, 5, delta_path, 2, 6)\n queryQVStore(pc, 5, delta_path, 2)\n // updateQVStore(pc, 5, delta_path, 2, 10)\n // queryQVStore(pc, 5, delta_path, 2)\n}\n\nclass MasterModuleTester extends ChiselFlatSpec {\n behavior of \"MasterModule\"\n backends foreach {backend =>\n it should s\"correctly add randomly generated numbers and show carry in $backend\" in {\n Driver(() => new MasterModule, backend)((c) => new MasterModuleTests(c)) should be (true)\n }\n }\n}\n", "groundtruth": " step(3)\n poke(c.io.sigUpdate, 0)\n // step(1)\n", "crossfile_context": "", "category": "Testbench Stimulus and Environment", "subcategory": "Stimulus Generation", "confidence": 0.85, "category_reason": "Chisel test harness (poke/peek/step)"} {"task_id": "Pythia-HDL", "path": "Pythia-HDL/src/test/scala/pythia/MaxNTests.scala", "left_context": "package pythia\n\nimport chisel3.iotesters.{PeekPokeTester, Driver, ChiselFlatSpec}\n\nclass MaxNTests(c: MaxN) extends PeekPokeTester(c) {\n poke(c.io.nums(0), 143)\n poke(c.io.nums(1), 540)\n poke(c.io.nums(2), 376)\n poke(c.io.ids(0), 4)\n poke(c.io.ids(1), 3)\n poke(c.io.ids(2), 9)\n step(1)\n expect(c.io.maxNum, 540)\n expect(c.io.maxId, 3)\n}\n\nclass MaxNTester extends ChiselFlatSpec {\n behavior of \"MaxN\"\n", "right_context": "", "groundtruth": " backends foreach {backend =>\n it should s\"correctly add randomly generated numbers and show carry in $backend\" in {\n Driver(() => new MaxN, backend)((c) => new MaxNTests(c)) should be (true)\n }\n }\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "Pythia-HDL", "path": "Pythia-HDL/src/test/scala/pythia/PlaneTests.scala", "left_context": "package pythia\n\nimport chisel3.iotesters.{PeekPokeTester, Driver, ChiselFlatSpec}\n\n\nclass PlaneTests(c: Plane) extends PeekPokeTester(c) {\n def PlaneRead(row0:Int, col0:Int, data0:Int, row1:Int, col1:Int, data1:Int){\n poke(c.io.rdrow0, row0)\n poke(c.io.rdcol0, col0)\n poke(c.io.rdrow1, row1)\n poke(c.io.rdcol1, col1)\n poke(c.io.re, 1)\n step(1)\n expect(c.io.rddata0, data0)\n expect(c.io.rddata1, data1)\n }\n def PlaneWrite(row:Int, col:Int, data:Int){\n poke(c.io.wrrow, row)\n poke(c.io.wrcol, col)\n poke(c.io.wrdata, data)\n poke(c.io.we, 1)\n step(1)\n }\n for(t <- 0 until 9){\n val row0 = rnd.nextInt(128)\n val col0 = rnd.nextInt(16)\n val data0 = rnd.nextInt(65536)\n val row1 = rnd.nextInt(128)\n val col1 = rnd.nextInt(16)\n val data1 = rnd.nextInt(65536)\n", "right_context": " PlaneWrite(row1, col1, data1)\n PlaneRead(row0, col0, data0, row1, col1, data1)\n }\n}\n\nclass PlaneTester extends ChiselFlatSpec {\n behavior of \"Plane\"\n backends foreach {backend =>\n it should s\"correctly add randomly generated numbers and show carry in $backend\" in {\n Driver(() => new Plane, backend)((c) => new PlaneTests(c)) should be (true)\n }\n }\n}\n", "groundtruth": " PlaneWrite(row0, col0, data0)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "Pythia-HDL", "path": "Pythia-HDL/src/test/scala/pythia/QVComapreTests.scala", "left_context": "package pythia\n\nimport chisel3.iotesters.{PeekPokeTester, Driver, ChiselFlatSpec}\n\nclass QVCompareTests(c: QVCompare) extends PeekPokeTester(c) {\n def test(qv0_p0:Int, qv0_p1:Int, qv0_p2:Int, qv1_p0:Int, qv1_p1:Int, qv1_p2:Int) = {\n poke(c.io.qv0_p0, qv0_p0)\n poke(c.io.qv0_p1, qv0_p1)\n poke(c.io.qv0_p2, qv0_p2)\n poke(c.io.qv1_p0, qv1_p0)\n poke(c.io.qv1_p1, qv1_p1)\n poke(c.io.qv1_p2, qv1_p2)\n step(1)\n val qv0 = qv0_p0 + qv0_p1 + qv0_p2\n val qv1 = qv1_p0 + qv1_p1 + qv1_p2\n", "right_context": " expect(c.io.qv_out, max)\n }\n\n test(1,2,3, 1,2,9)\n test(1,2,5, 1,2,9)\n test(1,2,10, 1,2,9)\n}\n\nclass QVCompareTester extends ChiselFlatSpec {\n behavior of \"QVCompare\"\n backends foreach {backend =>\n it should s\"correctly add randomly generated numbers and show carry in $backend\" in {\n Driver(() => new QVCompare, backend)((c) => new QVCompareTests(c)) should be (true)\n }\n }\n}\n", "groundtruth": " val max = if (qv0 >= qv1) {qv0} else {qv1}\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.6, "category_reason": "val binding"} {"task_id": "Pythia-HDL", "path": "Pythia-HDL/src/test/scala/pythia/VaultTests.scala", "left_context": "package pythia\n\nimport chisel3.iotesters.{PeekPokeTester, Driver, ChiselFlatSpec}\n\nclass VaultTests(c: Vault) extends PeekPokeTester(c) {\n def VaultRead(row0_p0:Int, row0_p1:Int, row0_p2:Int, col0:Int, data0:Int,\n row1_p0:Int, row1_p1:Int, row1_p2:Int, col1:Int, data1:Int) = {\n poke(c.io.rdrow0(0), row0_p0)\n poke(c.io.rdrow0(1), row0_p1)\n poke(c.io.rdrow0(2), row0_p2)\n poke(c.io.rdcol0, col0)\n poke(c.io.rdrow1(0), row1_p0)\n poke(c.io.rdrow1(1), row1_p1)\n poke(c.io.rdrow1(2), row1_p2)\n poke(c.io.rdcol1, col1)\n poke(c.io.re, 1)\n step(1)\n expect(c.io.rddata0(0), data0)\n", "right_context": " expect(c.io.rddata1(1), data1)\n expect(c.io.rddata1(2), data1)\n }\n def VaultWrite(row_p0:Int, row_p1:Int, row_p2:Int, col:Int, data:Int) = {\n poke(c.io.wrrow(0), row_p0)\n poke(c.io.wrrow(1), row_p1)\n poke(c.io.wrrow(2), row_p2)\n poke(c.io.wrcol, col)\n poke(c.io.wrdata(0), data)\n poke(c.io.wrdata(1), data)\n poke(c.io.wrdata(2), data)\n poke(c.io.we, 1)\n step(1)\n }\n def test(row0_p0:Int, row0_p1:Int, row0_p2:Int, col0:Int, data0:Int,\n row1_p0:Int, row1_p1:Int, row1_p2:Int, col1:Int, data1:Int) = {\n VaultWrite(row0_p0, row0_p1, row0_p2, col0, data0)\n VaultWrite(row1_p0, row1_p1, row1_p2, col1, data1)\n VaultRead(row0_p0, row0_p1, row0_p2, col0, data0, row1_p0, row1_p1, row1_p2, col1, data1)\n }\n\n test(2,3,9,5,10, 4,6,7,1,18)\n test(3,4,12,5,7891, 4,9,78,32,2390)\n test(96,48,67,42,9056, 28,90,69,25,4863)\n test(40,83,23,12,7813, 104,39,85,7,12986)\n test(1,100,69,27,785, 5,111,51,19,2308)\n}\n\nclass VaultTester extends ChiselFlatSpec {\n behavior of \"Vault\"\n backends foreach {backend =>\n it should s\"correctly add randomly generated numbers and show carry in $backend\" in {\n Driver(() => new Vault, backend)((c) => new VaultTests(c)) should be (true)\n }\n }\n}\n", "groundtruth": " expect(c.io.rddata0(1), data0)\n expect(c.io.rddata0(2), data0)\n", "crossfile_context": "", "category": "Monitoring and Checking Logic", "subcategory": "Error Reporting and Logging", "confidence": 0.85, "category_reason": "Chisel expect (golden check)"} {"task_id": "Pythia-HDL", "path": "Pythia-HDL/src/test/scala/utils/PythiaRunner.scala", "left_context": "// See LICENSE.txt for license details.\npackage utils\n\nimport scala.collection.mutable.ArrayBuffer\nimport chisel3.iotesters._\n\nobject OptionsCopy {\n def apply(t: TesterOptionsManager): TesterOptionsManager = {\n new TesterOptionsManager {\n testerOptions = t.testerOptions.copy()\n interpreterOptions = t.interpreterOptions.copy()\n chiselOptions = t.chiselOptions.copy()\n firrtlOptions = t.firrtlOptions.copy()\n treadleOptions = t.treadleOptions.copy()\n }\n }\n}\n\nobject PythiaRunner {\n def apply(section: String, pythiaMap: Map[String, TesterOptionsManager => Boolean], args: Array[String]): Unit = {\n var successful = 0\n val errors = new ArrayBuffer[String]\n\n val optionsManager = new TesterOptionsManager()\n optionsManager.doNotExitOnHelp()\n\n optionsManager.parse(args)\n\n val programArgs = optionsManager.commonOptions.programArgs\n\n if(programArgs.isEmpty) {\n println(\"Available Pythia modules\")\n for(x <- pythiaMap.keys) {\n println(x)\n }\n println(\"all\")\n System.exit(0)\n }\n\n val problemsToRun = if(programArgs.exists(x => x.toLowerCase() == \"all\")) {\n pythiaMap.keys\n }\n else {\n programArgs\n }\n\n for(testName <- problemsToRun) {\n pythiaMap.get(testName) match {\n case Some(test) =>\n println(s\"Starting pythia module $testName\")\n try {\n // Start with a (relatively) clean set of options.\n val testOptionsManager = OptionsCopy(optionsManager)\n testOptionsManager.setTopName(testName)\n testOptionsManager.setTargetDirName(s\"test_run_dir/$section/$testName\")\n if(test(testOptionsManager)) {\n successful += 1\n }\n else {\n errors += s\"Pythia module $testName: test error occurred\"\n }\n }\n catch {\n case exception: Exception =>\n exception.printStackTrace()\n errors += s\"Pythia module $testName: exception ${exception.getMessage}\"\n case t : Throwable =>\n", "right_context": " }\n case _ =>\n errors += s\"Bad pythia module name: $testName\"\n }\n\n }\n if(successful > 0) {\n println(s\"Pythia modules passing: $successful\")\n }\n if(errors.nonEmpty) {\n println(\"=\" * 80)\n println(s\"Errors: ${errors.length}: in the following pythia modules\")\n println(errors.mkString(\"\\n\"))\n println(\"=\" * 80)\n System.exit(1)\n }\n }\n}\n", "groundtruth": " errors += s\"Pythia module $testName: throwable ${t.getMessage}\"\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "dma", "path": "dma/chisel/src/main/scala/aha/dma/controller/Controller.scala", "left_context": "package aha\npackage dma\n\n/* Chisel Imports */\nimport chisel3._\nimport chisel3.experimental.ChiselEnum\nimport chisel3.util.{Decoupled, is, switch}\n\n/* Project Imports */\nimport aha.dma.CmdBundle\nimport aha.dma.util.AXILiteIntf\n\n/**\n * DMA Control Engine\n *\n * @constructor constructs a DMA control engine with provided address\n * bus width, data bus width, transfer bundle for reader,\n * transfer bundle for writer, and the value for the ID\n * register in the register file\n * @tparam R transfer command bundle type for reader\n * @tparam W transfer command bundle type for writer\n * @param AddrWidth the width of AXI address busses (AWADDR and ARADDR)\n * @param DataWidth the width of AXI data busses (WDATA and RDATA)\n * @param RdCmd the bundle to use for read transfer commands\n * @param WrCmd the bundle to use for write transfer commands\n * @param RegFileName the name of the register file type to instantiate\n * @param MagicID the value to use for the ID register in the register file\n *\n * @note transfer addresses must be aligned to the data bus width (DataWidth)\n */\nclass Controller[R <: CmdBundle, W <: CmdBundle] (\n AddrWidth : Int,\n DataWidth : Int,\n RdCmd : R,\n WrCmd : W,\n RegFileName : String,\n MagicID : Int = 0x5A5A5A5A ) extends RawModule {\n\n import Controller.State\n import Controller.State._\n\n // =========================================================================\n // I/O\n // =========================================================================\n\n // Clock and Reset\n val ACLK = IO(Input(Clock()))\n val ARESETn = IO(Input(Bool()))\n\n // Interrupt\n val Irq = IO(Output(Bool()))\n\n // AXI-Lite Register Interface\n lazy val RegIntf = IO(Flipped(reg_file.getRegFileIntf))\n\n // Read Command/Status Interfaces\n val RdCmdIntf = IO(Decoupled(RdCmd))\n val RdStatIntf = IO(Flipped(Decoupled(UInt(2.W))))\n\n // Write Command/Status Interfaces\n val WrCmdIntf = IO(Decoupled(WrCmd))\n val WrStatIntf = IO(Flipped(Decoupled(UInt(2.W))))\n\n // =========================================================================\n // Chisel Work-Around for Active-Low Reset\n // =========================================================================\n\n val reset = (!ARESETn).asAsyncReset\n\n // =========================================================================\n // Internal Logic\n // =========================================================================\n\n val state = withClockAndReset(ACLK, reset) { RegInit(sIDLE) }\n\n //\n // Control Signals (from RegFile)\n //\n val go_pulse = Wire(Bool())\n val irq_enable = Wire(Bool())\n val irq_clear_pulse = Wire(Bool())\n val src_addr = Wire(UInt(32.W))\n val dst_addr = Wire(UInt(32.W))\n val length = Wire(UInt(32.W))\n\n //\n // Status Signals (to RegFile)\n //\n val busy = withClockAndReset(ACLK, reset) { RegInit(false.B) }\n val irq_status = withClockAndReset(ACLK, reset) { RegInit(false.B) }\n val stat_code = withClockAndReset(ACLK, reset) { RegInit(0.U(2.W)) }\n\n //\n // Connect RegFile\n //\n val reg_file: RegFile = Module(RegFile.get(\n RegFileName,\n RegFileConfig(32, 32, MagicID)\n ))\n\n reg_file.ACLK := ACLK\n reg_file.ARESETn := ARESETn\n reg_file.RegIntf <> RegIntf\n reg_file.Busy := busy\n reg_file.IRQStatus := irq_status\n reg_file.StatCode := stat_code\n go_pulse := reg_file.GO_Pulse\n irq_enable := reg_file.IRQEnable\n irq_clear_pulse := reg_file.IRQClear_Pulse\n src_addr := reg_file.SrcAddr\n dst_addr := reg_file.DstAddr\n length := reg_file.Length\n\n //\n // Instantiate Splitter for Read Engine\n //\n val rd_trans_cmd_ready = Wire(Bool())\n val rd_trans_cmd_valid = withClockAndReset(ACLK, reset) { RegInit(false.B) }\n val rd_trans_cmd_bits = withClockAndReset(ACLK, reset) {\n RegInit(0.U.asTypeOf(new TransBundle(AddrWidth)))\n }\n val rd_trans_stat_ready = Wire(Bool())\n val rd_trans_stat_valid = Wire(Bool())\n val rd_trans_stat_bits = Wire(UInt(2.W))\n\n val rd_splitter = Module( new Splitter(\n new TransBundle(AddrWidth),\n new CmdBundle(AddrWidth),\n AddrWidth,\n DataWidth\n )\n )\n\n rd_splitter.ACLK := ACLK\n rd_splitter.ARESETn := ARESETn\n rd_trans_cmd_ready := rd_splitter.TransCmdIntf.ready\n rd_splitter.TransCmdIntf.valid := rd_trans_cmd_valid\n rd_splitter.TransCmdIntf.bits := rd_trans_cmd_bits\n rd_splitter.TransStatIntf.ready := rd_trans_stat_ready\n rd_trans_stat_valid := rd_splitter.TransStatIntf.valid\n rd_trans_stat_bits := rd_splitter.TransStatIntf.bits\n rd_splitter.XferCmdIntf <> RdCmdIntf\n rd_splitter.XferStatIntf <> RdStatIntf\n\n //\n // Instantiate Splitter for Write Engine\n //\n val wr_trans_cmd_ready = Wire(Bool())\n val wr_trans_cmd_valid = withClockAndReset(ACLK, reset) { RegInit(false.B) }\n val wr_trans_cmd_bits = withClockAndReset(ACLK, reset) {\n RegInit(0.U.asTypeOf(new TransBundle(AddrWidth)))\n }\n val wr_trans_stat_ready = Wire(Bool())\n val wr_trans_stat_valid = Wire(Bool())\n val wr_trans_stat_bits = Wire(UInt(2.W))\n\n val wr_splitter = Module( new Splitter(\n new TransBundle(AddrWidth),\n new CmdBundle(AddrWidth),\n AddrWidth,\n DataWidth\n )\n )\n\n wr_splitter.ACLK := ACLK\n wr_splitter.ARESETn := ARESETn\n wr_trans_cmd_ready := wr_splitter.TransCmdIntf.ready\n wr_splitter.TransCmdIntf.valid := wr_trans_cmd_valid\n wr_splitter.TransCmdIntf.bits := wr_trans_cmd_bits\n wr_splitter.TransStatIntf.ready := wr_trans_stat_ready\n wr_trans_stat_valid := wr_splitter.TransStatIntf.valid\n wr_trans_stat_bits := wr_splitter.TransStatIntf.bits\n wr_splitter.XferCmdIntf <> WrCmdIntf\n wr_splitter.XferStatIntf <> WrStatIntf\n\n //\n // Internal Signals\n //\n", "right_context": " val write_cmd_posted = withClockAndReset(ACLK, reset) { RegInit(false.B) }\n val read_stat_posted = withClockAndReset(ACLK, reset) { RegInit(false.B) }\n val write_stat_posted = withClockAndReset(ACLK, reset) { RegInit(false.B) }\n val read_stat = withClockAndReset(ACLK, reset) { RegInit(0.U(2.W))}\n val write_stat = withClockAndReset(ACLK, reset) { RegInit(0.U(2.W))}\n val err_stat = withClockAndReset(ACLK, reset) { RegInit(0.U(2.W))}\n\n withClockAndReset(ACLK, reset) {\n\n //\n // State Register Update Logic\n //\n switch (state) {\n is (sIDLE) {\n when (go_pulse && (length === 0.U)) {\n state := sSTAT\n }.elsewhen (go_pulse) {\n state := sPOST\n }\n } // sIDLE\n is (sPOST) {\n when (read_cmd_posted && write_cmd_posted) {\n state := sSTAT\n }\n } // sPOST\n is (sSTAT) {\n when (read_stat_posted && write_stat_posted) {\n state := sIDLE\n }\n } // sSTAT\n } // switch (state)\n\n //\n // Interrupt Logic\n //\n Irq := irq_status && irq_enable\n\n //\n // Error Status Code\n //\n switch (state) {\n is (sIDLE) {\n when (go_pulse && (length === 0.U)) {\n err_stat := 2.U\n }.otherwise {\n err_stat := 0.U\n }\n } // sIDLE\n } // switch (state)\n\n //\n // Busy Signal\n // (Can be made un-registered to avoid 1 cycle delay if necessary)\n //\n busy := state =/= sIDLE\n\n //\n // IRQ Status\n //\n when ((state === sSTAT) && read_stat_posted && write_stat_posted) {\n irq_status := true.B\n }.elsewhen (irq_clear_pulse) {\n irq_status := false.B\n }\n\n //\n // Transaction Status Code\n //\n switch (state) {\n is (sSTAT) {\n when (read_stat_posted && write_stat_posted) {\n when (err_stat =/= 0.U) {\n stat_code := err_stat\n }.elsewhen (read_stat =/= 0.U) {\n stat_code := read_stat\n }.otherwise {\n stat_code := write_stat\n }\n }\n } // sSTAT\n } // switch (state)\n\n //\n // Read Status\n // (read_stat and read_stat_posted)\n //\n switch (state) {\n is (sIDLE) {\n read_stat := 0.U\n read_stat_posted := false.B\n } // sIDLE\n is (sSTAT) {\n when (rd_trans_stat_valid || (err_stat =/= 0.U)) {\n read_stat := rd_trans_stat_bits\n read_stat_posted := true.B\n }\n } // sSTAT\n } // switch (state)\n\n rd_trans_stat_ready := state === sSTAT\n\n //\n // Write Status\n // (write_stat and write_stat_posted)\n //\n switch (state) {\n is (sIDLE) {\n write_stat := 0.U\n write_stat_posted := false.B\n } // sIDLE\n is (sSTAT) {\n when (wr_trans_stat_valid || (err_stat =/= 0.U)) {\n write_stat := wr_trans_stat_bits\n write_stat_posted := true.B\n }\n } // sSTAT\n } // switch (state)\n\n wr_trans_stat_ready := state === sSTAT\n\n //\n // Read Transaction Command\n //\n switch (state) {\n is (sIDLE) {\n read_cmd_posted := false.B\n when (go_pulse && (length =/= 0.U)) {\n rd_trans_cmd_valid := true.B\n rd_trans_cmd_bits.NumBytes := length\n rd_trans_cmd_bits.Address := src_addr\n }.otherwise {\n rd_trans_cmd_valid := false.B\n }\n } // sIDLE\n is (sPOST) {\n when (rd_trans_cmd_ready) {\n read_cmd_posted := true.B\n rd_trans_cmd_valid := false.B\n }\n } // sPOST\n } // switch (state)\n\n //\n // Write Transaction Command\n //\n switch (state) {\n is (sIDLE) {\n write_cmd_posted := false.B\n when (go_pulse && (length =/= 0.U)) {\n wr_trans_cmd_valid := true.B\n wr_trans_cmd_bits.NumBytes := length\n wr_trans_cmd_bits.Address := dst_addr\n }.otherwise {\n wr_trans_cmd_valid := false.B\n }\n } // sIDLE\n is (sPOST) {\n when (wr_trans_cmd_ready) {\n write_cmd_posted := true.B\n wr_trans_cmd_valid := false.B\n }\n } // sPOST\n } // switch (state)\n\n\n\n } // withClockAndReset(ACLK, reset)\n\n} // class Controller\n\n/**\n * Provides the states for the [[Controller]] finite state machine\n */\nobject Controller {\n\n /**\n * States for Controller FSM\n */\n object State extends ChiselEnum {\n val sIDLE, sPOST, sSTAT = Value\n }\n} // object Controller\n", "groundtruth": " val read_cmd_posted = withClockAndReset(ACLK, reset) { RegInit(false.B) }\n", "crossfile_context": "", "category": "Storage Block", "subcategory": "Register-based Storage", "confidence": 0.85, "category_reason": "RegInit register"} {"task_id": "dma", "path": "dma/chisel/src/main/scala/aha/dma/controller/DataMover.scala", "left_context": "package aha\npackage dma\n\n/* Chisel Imports */\nimport chisel3._\nimport chisel3.experimental.dataview._\nimport chisel3.util.Decoupled\n\n/* Project Imports */\nimport aha.dma.CmdBundle\nimport aha.dma.util.{AXI4Intf, AXI4WrIntfView, AXI4RdIntfView, PeekQueue}\n\n/**\n * AXI4 Data Mover\n *\n * @constructor constructs a data mover with the provided AXI ID width,\n * address bus width, data bus width, the transfer bundle\n * for the reader, the transfer bundle for the\n * writer, and the depth of the store-and-forward fifo\n * @tparam R transfer command bundle type for reader\n * @tparam W transfer command bundle type for writer\n * @param IdWidth the width of AXI ID signals (AWID, BID, ARID, and RID)\n * @param AddrWidth the width of AXI address busses (AWADDR and ARADDR)\n * @param DataWidth the width of AXI data busses (WDATA and RDATA)\n * @param RdCmd the bundle to use for read transfer commands\n * @param WrCmd the bundle to use for write transfer commands\n * @param FifoDepth the depth of the store-and-forward fifo\n *\n * @note transfer addresses must be aligned to the data bus width (DataWidth)\n * @note transfers must not cross the [[MAX_BURST_BYTES]]\n */\nclass DataMover[R <: CmdBundle, W <: CmdBundle] (\n IdWidth : Int,\n AddrWidth : Int,\n DataWidth : Int,\n RdCmd : R,\n WrCmd : W,\n FifoDepth : Int ) extends RawModule {\n\n // =========================================================================\n // I/O\n // =========================================================================\n\n // Clock and Reset\n val ACLK = IO(Input(Clock()))\n val ARESETn = IO(Input(Bool()))\n\n // Reader Command/Stat Interfaces\n val RdCmdIntf = IO(Flipped(Decoupled(RdCmd)))\n val RdStatIntf = IO(Decoupled(UInt(2.W)))\n\n // Writer Command/Stat Interfaces\n val WrCmdIntf = IO(Flipped(Decoupled(WrCmd)))\n val WrStatIntf = IO(Decoupled(UInt(2.W)))\n\n // AXI4 Interface\n val M_AXI = IO(new AXI4Intf(IdWidth, AddrWidth, DataWidth))\n\n // =========================================================================\n // Internal Logic\n // =========================================================================\n\n //\n // AXI4 Read and Write Views\n //\n val axi4RdView = M_AXI.viewAs[AXI4RdIntfView]\n val axi4WrView = M_AXI.viewAs[AXI4WrIntfView]\n\n //\n // Instantiate Reader, Writer, and PeekQueue\n //\n val reader = Module(new Reader(IdWidth, AddrWidth, DataWidth, RdCmd))\n val writer = Module(new Writer(IdWidth, AddrWidth, DataWidth, WrCmd))\n val peekQueue = Module(new PeekQueue(UInt(DataWidth.W), FifoDepth))\n\n //\n // Reader Connections\n //\n reader.ACLK := ACLK\n reader.ARESETn := ARESETn\n reader.CmdIntf <> RdCmdIntf\n reader.StatIntf <> RdStatIntf\n reader.ReadIntf <> axi4RdView\n\n //\n // Writer Connections\n //\n writer.ACLK := ACLK\n writer.ARESETn := ARESETn\n writer.CmdIntf <> WrCmdIntf\n writer.StatIntf <> WrStatIntf\n writer.WriteIntf <> axi4WrView\n\n //\n // PeekQueue Connections\n", "right_context": " peekQueue.EnqIntf <> reader.DataIntf\n peekQueue.DeqIntf <> writer.DataIntf\n}\n", "groundtruth": " //\n peekQueue.ACLK := ACLK\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.55, "category_reason": ":= connection"} {"task_id": "dma", "path": "dma/chisel/src/main/scala/aha/dma/controller/Splitter.scala", "left_context": "package aha\npackage dma\n\n/* Chisel Imports */\nimport chisel3._\nimport chisel3.experimental.ChiselEnum\nimport chisel3.util.{Decoupled, is, isPow2, switch}\n\n/* Project Imports */\nimport aha.dma.{CmdBundle, log2 , MAX_BURST_BYTES, MAX_BURST_LENGTH, TransBundle}\n\n/**\n * Transaction Splitter (splits a transaction into transfers)\n *\n * @constructor constructs a transaction splitter with the provided\n * bundle type for transaction, bundle type for transfers,\n * address bus width and data bus width\n * @param TransCmd bundle type for transaction commands\n * @param XferCmd bundle type for transfer commands\n * @param AddrWidth the width of AXI address busses (AWADDR and ARADDR)\n * @param DataWidth the width of AXI data busses (WDATA and RDATA)\n *\n * @note transfer addresses must be aligned to the data bus width (DataWidth)\n */\nclass Splitter[C1 <: TransBundle, C2 <: CmdBundle] (\n TransCmd : C1,\n XferCmd : C2,\n AddrWidth : Int,\n DataWidth : Int ) extends RawModule {\n\n import Splitter.State\n import Splitter.State._\n\n // =========================================================================\n // I/O\n // =========================================================================\n\n // Clock and Reset\n val ACLK = IO(Input(Clock()))\n val ARESETn = IO(Input(Bool()))\n\n // Transaction Cmd/Status Interface\n val TransCmdIntf = IO(Flipped(Decoupled(TransCmd)))\n val TransStatIntf = IO(Decoupled(UInt(2.W)))\n\n // Transfer Cmd/Status Interface\n val XferCmdIntf = IO(Decoupled(XferCmd))\n val XferStatIntf = IO(Flipped(Decoupled(UInt(2.W))))\n\n // =========================================================================\n // Chisel Work-Around for Active-Low Reset\n // =========================================================================\n\n val reset = (!ARESETn).asAsyncReset\n\n // =========================================================================\n // Internal Logic\n // =========================================================================\n\n // Maximum Number of Bytes in a Transfer\n val n_lanes = DataWidth / 8\n val max_link_bytes = MAX_BURST_LENGTH * n_lanes\n val max_xfer_bytes = if (max_link_bytes < MAX_BURST_BYTES)\n max_link_bytes\n else\n MAX_BURST_BYTES\n val max_xfer_bytes_log = log2(max_xfer_bytes)\n\n // max_xfer_bytes must be a power of 2\n require (isPow2(max_xfer_bytes))\n\n", "right_context": " val cur_num_bytes = withClockAndReset(ACLK, reset) { RegInit(0.U(32.W)) }\n val rem_bytes = withClockAndReset(ACLK, reset) { RegInit(0.U(32.W)) }\n val bBytes = max_xfer_bytes.U - TransCmdIntf.bits.Address(max_xfer_bytes_log - 1, 0)\n val cur_addr = withClockAndReset(ACLK, reset) { RegInit(0.U(AddrWidth.W)) }\n val next_addr = ((cur_addr >> max_xfer_bytes_log.U) + 1.U) << max_xfer_bytes_log.U\n val trans_status = withClockAndReset(ACLK, reset) { RegInit(0.U(2.W)) }\n\n\n withClockAndReset(ACLK, reset) {\n //\n // State Register Update Logic\n //\n switch (state) {\n is (sIDLE) {\n when (TransCmdIntf.valid) {\n state := sSPLIT\n }\n } // sIDLE\n is (sSPLIT) {\n when (XferCmdIntf.ready) {\n state := sWAIT\n }\n } // sSPLIT\n is (sWAIT) {\n when (XferStatIntf.valid) {\n when (rem_bytes > 0.U) {\n state := sSPLIT\n }.otherwise {\n state := sSTAT\n }\n }\n } // sWAIT\n is (sSTAT) {\n when (TransStatIntf.ready) {\n state := sIDLE\n }\n } // sSTAT\n } // switch(state)\n\n //\n // Transaction Address Splitting\n //\n switch (state) {\n is (sIDLE) {\n when (TransCmdIntf.valid) {\n cur_addr := TransCmdIntf.bits.Address\n }\n } // sIDLE\n is (sWAIT) {\n when (XferStatIntf.valid) {\n cur_addr := next_addr\n }\n }\n } // switch (state)\n\n //\n // Transaction Size (bytes count) Splitting\n //\n switch (state) {\n is (sIDLE) {\n when (TransCmdIntf.valid) {\n when (bBytes <= TransCmdIntf.bits.NumBytes) {\n cur_num_bytes := bBytes\n rem_bytes := TransCmdIntf.bits.NumBytes - bBytes\n }.otherwise {\n cur_num_bytes := TransCmdIntf.bits.NumBytes\n rem_bytes := 0.U\n }\n }\n } // sIDLE\n is (sWAIT) {\n when (XferStatIntf.valid) {\n when (rem_bytes > max_xfer_bytes.U) {\n cur_num_bytes := max_xfer_bytes.U\n rem_bytes := rem_bytes - max_xfer_bytes.U\n }.otherwise {\n cur_num_bytes := rem_bytes\n rem_bytes := 0.U\n }\n }\n } // sWAIT\n } // switch (state)\n\n //\n // Transaction Status\n //\n switch (state) {\n is (sIDLE) {\n trans_status := 0.U\n } // sIDLE\n is (sWAIT) {\n when (XferStatIntf.valid && (TransStatIntf.bits === 0.U)) {\n trans_status := XferStatIntf.bits\n }\n }\n } // switch (state)\n\n TransStatIntf.bits := trans_status\n\n //\n // Transaction Cmd/Status\n //\n TransCmdIntf.ready := state === sIDLE\n TransStatIntf.valid := state === sSTAT\n\n //\n // Transfer Status Ready\n //\n XferStatIntf.ready := state === sWAIT\n\n //\n // Transfer Command\n //\n XferCmdIntf.valid := state === sSPLIT\n XferCmdIntf.bits.NumBytes := cur_num_bytes\n XferCmdIntf.bits.Address := cur_addr\n\n } // withClockAndReset(ACLK, reset)\n\n} // class Splitter\n\n/**\n * Provides the states for the [[Splitter]] finite state machine\n */\nobject Splitter {\n\n /**\n * States for Splitter FSM\n */\n object State extends ChiselEnum {\n val sIDLE, sSPLIT, sWAIT, sSTAT = Value\n } // object State\n\n} // object Splitter\n", "groundtruth": " val state = withClockAndReset(ACLK, reset) { RegInit(sIDLE) }\n", "crossfile_context": "", "category": "Storage Block", "subcategory": "Register-based Storage", "confidence": 0.85, "category_reason": "RegInit register"} {"task_id": "dma", "path": "dma/chisel/src/main/scala/aha/dma/package.scala", "left_context": "package aha\n\n/* Scala Imports */\nimport scala.math._\n\n/* Chisel Imports */\nimport chisel3._\n\n/**\n * Provides project-wide constants, transfer and transaction bundle types, and\n * some utility functions\n */\npackage object dma {\n\n // =========================================================================\n // AXI Parameters\n // =========================================================================\n\n /**\n * Maximum Number of Bytes in an AXI Burst\n */\n val MAX_BURST_BYTES = 4096\n\n /**\n * Maximum Burst Length Supported in INCR Mode\n * AXI4 = 256\n * AXI3 = 16\n */\n val MAX_BURST_LENGTH = 256\n\n /**\n * Transfer command bundle\n *\n * @constructor constructs a transfer command bundle with a specified\n * AXI address bus width\n * @param AddrWidth the width of AXI address busses (AWADDR and ARADDR)\n */\n class CmdBundle(AddrWidth: Int) extends Bundle {\n val NumBytes = UInt(clog2(MAX_BURST_BYTES).W)\n val Address = UInt(AddrWidth.W)\n }\n\n /**\n * Transaction command bundle\n *\n * @constructor constructs a transaction command bundle with a specified\n * AXI address bus width\n * @param AddrWidth the width of AXI address busses (AWADDR and ARADDR)\n */\n", "right_context": " *\n * @param x the number of which the clog2 is computed\n * @return the log2 of x rounded up\n */\n def clog2(x: Int) : Int = {\n require(x >= 0)\n ceil(log(x)/log(2)).toInt\n }\n\n /**\n * Returns log2 of a number\n *\n * @param x the number of which the log2 is computed\n * @return the log2 of x\n */\n def log2(x: Int) : Int = {\n require(x >= 0)\n (log(x)/log(2)).toInt\n }\n}\n", "groundtruth": " class TransBundle(AddrWidth: Int) extends Bundle {\n val NumBytes = UInt(32.W)\n val Address = UInt(AddrWidth.W)\n }\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.9, "category_reason": "Bundle class definition"} {"task_id": "dma", "path": "dma/chisel/src/main/scala/aha/dma/reader/Reader.scala", "left_context": "package aha\npackage dma\n\n/* Chisel Imports */\nimport chisel3._\nimport chisel3.experimental.ChiselEnum\nimport chisel3.util.{Decoupled, is, switch}\n\n/* Project Imports */\nimport aha.dma.{CmdBundle, log2}\nimport aha.dma.util.{AXI4RdIntfView, AXI4AddrPayload}\n\n/**\n * AXI4 Read Engine\n *\n * @constructor constructs a AXI4 read engine with an AXI ID width,\n * address bus width, data bus width, and the type of a\n * transfer command bundle\n * @tparam R transfer command bundle type for reader\n * @param IdWidth the width of AXI ID signals (AWID, BID, ARID, and RID)\n * @param AddrWidth the width of AXI address busses (AWADDR and ARADDR)\n * @param DataWidth the width of AXI data busses (WDATA and RDATA)\n * @param Cmd the bundle to use for transfer commands\n *\n * @note transfer addresses must be aligned to the data bus width (DataWidth)\n * @note transfers must not cross the [[MAX_BURST_BYTES]]\n */\nclass Reader[R <: CmdBundle](IdWidth: Int,\n AddrWidth: Int,\n DataWidth: Int,\n Cmd : R) extends RawModule {\n\n import Reader.State\n import Reader.State._\n\n // =========================================================================\n // I/O\n // =========================================================================\n\n // Clock and Reset\n val ACLK = IO(Input(Clock()))\n val ARESETn = IO(Input(Bool()))\n\n // Command/Stat Interfaces\n val CmdIntf = IO(Flipped(Decoupled(Cmd)))\n val StatIntf = IO(Decoupled(UInt(2.W)))\n\n // Data Packet Interface\n val DataIntf = IO(Decoupled(UInt(DataWidth.W)))\n\n // AXI4 Read Interface\n val ReadIntf = IO(new AXI4RdIntfView(IdWidth, AddrWidth, DataWidth))\n\n // =========================================================================\n // Chisel Work-Around for Active-Low Reset\n // =========================================================================\n\n val reset = (!ARESETn).asAsyncReset\n\n // =========================================================================\n // Internal Logic\n // =========================================================================\n\n", "right_context": " val last_beat = Wire(Bool())\n val read_resp = withClockAndReset(ACLK, reset) { RegInit(0.U(2.W)) }\n\n // AR Channel Signals\n val ar_size = log2(DataWidth/8)\n val ar_addr = (CmdIntf.bits.Address >> ar_size.U) << ar_size.U\n val ar_len = Wire(UInt(8.W))\n val ar_valid = withClockAndReset(ACLK, reset) { RegInit(false.B) }\n val ar_payload = withClockAndReset(ACLK, reset) {\n RegInit(0.U.asTypeOf(new AXI4AddrPayload(IdWidth, AddrWidth)))\n }\n\n // R Channel Signal\n val r_ready = Wire(Bool())\n\n withClockAndReset(ACLK, reset) {\n //\n // State Register Update Logic\n //\n switch (state) {\n is (sIDLE) {\n when (CmdIntf.valid) {\n state := sADDR\n }\n } // sIDLE\n is (sADDR) {\n when (ReadIntf.AR.ready) {\n state := sDATA\n }\n } // sADDR\n is (sDATA) {\n when (last_beat) {\n state := sSTAT\n }\n } // sDATA\n is (sSTAT) {\n when (StatIntf.ready) {\n state := sIDLE\n }\n } // sSTAT\n } // switch(state)\n\n //\n // AR Channel Signals\n //\n switch (state) {\n is (sIDLE) {\n when (CmdIntf.valid) {\n ar_valid := true.B\n ar_payload.ID := 0.U\n ar_payload.ADDR := ar_addr\n ar_payload.LEN := ar_len\n ar_payload.SIZE := ar_size.U\n ar_payload.BURST := 1.U\n ar_payload.LOCK := false.B\n ar_payload.CACHE := 2.U\n ar_payload.PROT := 2.U\n }.otherwise {\n ar_valid := false.B\n }\n } // sIDLE\n is (sADDR) {\n when (ReadIntf.AR.ready) {\n ar_valid := false.B\n }\n } // sADDR\n } // switch(state)\n\n ReadIntf.AR.valid := ar_valid\n ReadIntf.AR.bits := ar_payload\n\n //\n // Internal Read Response Accumulation\n // (read errors are sticky)\n //\n switch (state) {\n is (sIDLE) {\n read_resp := 0.U\n } // sIDLE\n is (sDATA) {\n when (ReadIntf.R.valid && ReadIntf.R.ready) {\n when (read_resp === 0.U) {\n read_resp := ReadIntf.R.bits.RESP\n }\n }\n } // sDATA\n } // switch(state)\n\n //\n // RREADY\n //\n when (state === sDATA) {\n r_ready := DataIntf.ready\n }.otherwise {\n r_ready := false.B\n }\n\n ReadIntf.R.ready := r_ready\n\n //\n // Internal Signals\n //\n last_beat := ReadIntf.R.valid && ReadIntf.R.ready && ReadIntf.R.bits.LAST\n ar_len := ((CmdIntf.bits.NumBytes >> ar_size.U) +\n CmdIntf.bits.NumBytes(ar_size-1, 0).orR) - 1.U\n\n //\n // Status Signals\n //\n StatIntf.valid := state === sSTAT\n StatIntf.bits := read_resp\n\n //\n // Data Interface Signals\n //\n DataIntf.valid := (state === sDATA) && ReadIntf.R.valid\n DataIntf.bits := ReadIntf.R.bits.DATA\n\n //\n // Command Interface Ready\n //\n CmdIntf.ready := state === sIDLE\n\n } // withClockAndReset(ACLK, reset)\n\n} // class Reader\n\n/**\n * Provides the states for the [[Reader]] finite state machine\n */\nobject Reader {\n\n /**\n * States for Reader FSM\n */\n object State extends ChiselEnum {\n val sIDLE, sADDR, sDATA, sSTAT = Value\n } // object State\n} // object Reader\n", "groundtruth": " val state = withClockAndReset(ACLK, reset) { RegInit(sIDLE) }\n", "crossfile_context": "", "category": "Storage Block", "subcategory": "Register-based Storage", "confidence": 0.85, "category_reason": "RegInit register"} {"task_id": "dma", "path": "dma/chisel/src/main/scala/aha/dma/regfile/APBRegFile.scala", "left_context": "package aha\npackage dma\n\n/* Chisel Imports */\nimport chisel3._\nimport chisel3.util.{Cat, is, switch}\n\n/* Project Imports */\nimport aha.dma.util.APBIntf\n\n/**\n * DMA Register File with APB interface\n *\n * @constructor constructs a register file with the provided value for\n * the ID register\n * @param MagicID the value for the ID register\n */\nclass APBRegFile(val MagicID: Int = 0x5A5A5A5A) extends RegFile {\n\n // Type of Register File Interface\n type RegIntfTy = APBIntf\n\n // AXI-Lite Interface\n def getRegFileIntf = new APBIntf(32, 32)\n\n // =========================================================================\n // Chisel Work-Around for Active-Low Reset\n // =========================================================================\n\n val reset = (!ARESETn).asAsyncReset\n\n // =========================================================================\n // Internal Logic\n // =========================================================================\n\n //\n // Registers\n //\n val reg_go_pulse = withClockAndReset(ACLK, reset) { RegInit(false.B) }\n val reg_ie = withClockAndReset(ACLK, reset) { RegInit(false.B) }\n val reg_intclr_pulse = withClockAndReset(ACLK, reset) { RegInit(false.B) }\n val reg_src_addr = withClockAndReset(ACLK, reset) { RegInit(0.U(32.W)) }\n val reg_dst_addr = withClockAndReset(ACLK, reset) { RegInit(0.U(32.W)) }\n val reg_length = withClockAndReset(ACLK, reset) { RegInit(0.U(32.W)) }\n\n //\n // Internal Signals\n //\n val prdata = withClockAndReset(ACLK, reset) { RegInit(0.U(32.W)) }\n val pready = Wire(Bool())\n val pslverr = withClockAndReset(ACLK, reset) { RegInit(false.B) }\n\n val reg_data_out = Wire(UInt(32.W))\n val setup_phase = Wire(Bool())\n val wr_en = Wire(Bool())\n val rd_en = Wire(Bool())\n\n setup_phase := RegIntf.PSEL && ~RegIntf.PENABLE\n wr_en := setup_phase && RegIntf.PWRITE\n rd_en := setup_phase && ~RegIntf.PWRITE\n\n //\n // APB Connections\n //\n RegIntf.PRDATA := prdata\n RegIntf.PREADY := pready\n RegIntf.PSLVERR := pslverr\n\n\n withClockAndReset(ACLK, reset) {\n\n //\n // Generate GO Pulse\n //\n when (wr_en && (RegIntf.PADDR(4, 2) === 0.U)) {\n reg_go_pulse := RegIntf.PWDATA(0).asBool\n }.otherwise {\n reg_go_pulse := false.B\n }\n\n GO_Pulse := reg_go_pulse\n\n //\n // Generate Interrupt Clear Pulse\n //\n when (wr_en && (RegIntf.PADDR(4, 2) === 2.U)) {\n reg_intclr_pulse := RegIntf.PWDATA(1).asBool\n }.otherwise {\n reg_intclr_pulse := false.B\n }\n\n IRQClear_Pulse := reg_intclr_pulse\n\n //\n // Interrupt Enable Register Update Logic\n //\n when (wr_en && (RegIntf.PADDR(4, 2) === 0.U)) {\n reg_ie := RegIntf.PWDATA(1).asBool\n }\n\n IRQEnable := reg_ie\n\n //\n // Source Address Register\n //\n when (wr_en && (RegIntf.PADDR(4, 2) === 3.U)) {\n reg_src_addr := RegIntf.PWDATA\n }\n\n SrcAddr := reg_src_addr\n\n //\n // Destination Address Register\n //\n when (wr_en && (RegIntf.PADDR(4, 2) === 4.U)) {\n reg_dst_addr := RegIntf.PWDATA\n }\n\n DstAddr := reg_dst_addr\n\n //\n // Length Register\n //\n when (wr_en && (RegIntf.PADDR(4, 2) === 5.U)) {\n reg_length := RegIntf.PWDATA\n }\n\n Length := reg_length\n\n //\n // Output Data Select Logic\n //\n reg_data_out := 0.U\n switch (RegIntf.PADDR(4, 2)) {\n is (0.U) { reg_data_out := Cat(reg_ie, 0.U(1.W)) }\n is (1.U) { reg_data_out := Cat(StatCode, IRQStatus.asUInt, Busy.asUInt) }\n is (3.U) { reg_data_out := reg_src_addr }\n", "right_context": " is (5.U) { reg_data_out := reg_length }\n is (6.U) { reg_data_out := MagicID.U }\n }\n\n //\n // prdata\n //\n when (rd_en) {\n prdata := reg_data_out\n }\n\n //\n // pready\n //\n pready := true.B // Always Ready\n\n //\n // pslverr\n //\n when (rd_en) {\n when (RegIntf.PADDR(4, 2) > 6.U) {\n pslverr := true.B\n }.otherwise {\n pslverr := false.B\n }\n }.otherwise {\n pslverr := false.B\n }\n\n } // withClockAndReset(ACLK, reset)\n} // class RegFile\n", "groundtruth": " is (4.U) { reg_data_out := reg_dst_addr }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.75, "category_reason": "is() in switch context"} {"task_id": "dma", "path": "dma/chisel/src/main/scala/aha/dma/regfile/AXILiteRegFile.scala", "left_context": "package aha\npackage dma\n\n/* Chisel Imports */\nimport chisel3._\nimport chisel3.util.{Cat, is, switch}\n\n/* Project Imports */\nimport aha.dma.util.AXILiteIntf\n\n/**\n * DMA Register File with AXI-Lite interface\n *\n * @constructor constructs a register file with the provided value for\n * the ID register\n * @param MagicID the value for the ID register\n */\nclass AXILiteRegFile(val MagicID: Int = 0x5A5A5A5A) extends RegFile {\n\n // Type of Register File Interface\n type RegIntfTy = AXILiteIntf\n\n // AXI-Lite Interface\n def getRegFileIntf = new AXILiteIntf(32, 32)\n\n // =========================================================================\n // Chisel Work-Around for Active-Low Reset\n // =========================================================================\n\n val reset = (!ARESETn).asAsyncReset\n\n // =========================================================================\n // Internal Logic\n // =========================================================================\n\n //\n // Registers\n //\n val reg_go_pulse = withClockAndReset(ACLK, reset) { RegInit(false.B) }\n val reg_ie = withClockAndReset(ACLK, reset) { RegInit(false.B) }\n val reg_intclr_pulse = withClockAndReset(ACLK, reset) { RegInit(false.B) }\n val reg_src_addr = withClockAndReset(ACLK, reset) { RegInit(0.U(32.W)) }\n val reg_dst_addr = withClockAndReset(ACLK, reset) { RegInit(0.U(32.W)) }\n val reg_length = withClockAndReset(ACLK, reset) { RegInit(0.U(32.W)) }\n\n //\n // Internal Signals\n //\n val axi_awaddr = withClockAndReset(ACLK, reset) { RegInit(0.U(32.W)) }\n val axi_awready = withClockAndReset(ACLK, reset) { RegInit(false.B) }\n val aw_en = withClockAndReset(ACLK, reset) { RegInit(true.B) }\n val axi_wready = withClockAndReset(ACLK, reset) { RegInit(false.B) }\n val axi_bvalid = withClockAndReset(ACLK, reset) { RegInit(false.B) }\n val axi_bresp = withClockAndReset(ACLK, reset) { RegInit(0.U(2.W)) }\n val axi_araddr = withClockAndReset(ACLK, reset) { RegInit(0.U(32.W)) }\n val axi_arready = withClockAndReset(ACLK, reset) { RegInit(false.B) }\n val axi_rdata = withClockAndReset(ACLK, reset) { RegInit(0.U(32.W)) }\n val axi_rresp = withClockAndReset(ACLK, reset) { RegInit(0.U(2.W)) }\n val axi_rvalid = withClockAndReset(ACLK, reset) { RegInit(false.B) }\n\n val slv_reg_rden = Wire(Bool())\n val slv_reg_wren = Wire(Bool())\n val reg_data_out = Wire(UInt(32.W))\n\n //\n // AXI-Lite Connections\n //\n RegIntf.AWREADY := axi_awready\n RegIntf.WREADY := axi_wready\n RegIntf.BRESP := axi_bresp\n RegIntf.BVALID := axi_bvalid\n RegIntf.ARREADY := axi_arready\n RegIntf.RDATA := axi_rdata\n RegIntf.RRESP := axi_rresp\n RegIntf.RVALID := axi_rvalid\n\n withClockAndReset(ACLK, reset) {\n\n //\n // axi_awready and aw_en\n //\n when (~axi_awready && RegIntf.AWVALID && RegIntf.WVALID && aw_en) {\n axi_awready := true.B\n aw_en := false.B\n }.elsewhen (RegIntf.BREADY && axi_bvalid) {\n axi_awready := false.B\n aw_en := true.B\n }.otherwise {\n axi_awready := false.B\n }\n\n //\n // axi_awaddr\n //\n when (~axi_awready && RegIntf.AWVALID && RegIntf.WVALID && aw_en) {\n axi_awaddr := RegIntf.AWADDR\n }\n\n //\n // axi_wready\n //\n when (~axi_wready && RegIntf.WVALID && RegIntf.AWVALID && aw_en) {\n axi_wready := true.B\n }.otherwise {\n axi_wready := false.B\n }\n\n //\n // axi_bvalid and axi_bresp\n //\n when (axi_awready && RegIntf.AWVALID && ~axi_bvalid && axi_wready && RegIntf.WVALID) {\n axi_bvalid := true.B\n axi_bresp := 0.U\n }.elsewhen (RegIntf.BREADY && axi_bvalid) {\n axi_bvalid := false.B\n }\n\n //\n // Write Enable Signal\n //\n slv_reg_wren := axi_awready && RegIntf.AWVALID && axi_wready && RegIntf.WVALID\n\n //\n // Generate GO Pulse\n //\n when (slv_reg_wren && (axi_awaddr(4, 2) === 0.U) && (RegIntf.WSTRB(0) === 1.U)) {\n reg_go_pulse := RegIntf.WDATA(0).asBool\n }.otherwise {\n reg_go_pulse := false.B\n }\n\n GO_Pulse := reg_go_pulse\n\n //\n // Generate Interrupt Clear Pulse\n //\n when (slv_reg_wren && (axi_awaddr(4, 2) === 2.U) && (RegIntf.WSTRB(0) === 1.U)) {\n reg_intclr_pulse := RegIntf.WDATA(1).asBool\n }.otherwise {\n reg_intclr_pulse := false.B\n }\n\n IRQClear_Pulse := reg_intclr_pulse\n\n //\n // Interrupt Enable Register Update Logic\n //\n when (slv_reg_wren && (axi_awaddr(4, 2) === 0.U) && (RegIntf.WSTRB(0) === 1.U)) {\n reg_ie := RegIntf.WDATA(1).asBool\n }\n\n IRQEnable := reg_ie\n\n //\n // Source Address Register\n //\n val reg_src_addr_v = Wire(Vec(4, UInt(8.W)))\n reg_src_addr_v := reg_src_addr.asTypeOf(Vec(4, UInt(8.W)))\n\n when (slv_reg_wren && (axi_awaddr(4, 2) === 3.U)) {\n", "right_context": "\n //\n // Destination Address Register\n //\n val reg_dst_addr_v = Wire(Vec(4, UInt(8.W)))\n reg_dst_addr_v := reg_dst_addr.asTypeOf(Vec(4, UInt(8.W)))\n\n when (slv_reg_wren && (axi_awaddr(4, 2) === 4.U)) {\n for (n <- 0 to 3) {\n when (RegIntf.WSTRB(n) === 1.U) {\n reg_dst_addr_v(n) := RegIntf.WDATA(n*8+7, n*8)\n }\n }\n reg_dst_addr := reg_dst_addr_v.asTypeOf(UInt(32.W))\n }\n\n DstAddr := reg_dst_addr\n\n //\n // Length Register\n //\n val reg_length_v = Wire(Vec(4, UInt(8.W)))\n reg_length_v := reg_length.asTypeOf(Vec(4, UInt(8.W)))\n\n when (slv_reg_wren && (axi_awaddr(4, 2) === 5.U)) {\n for (n <- 0 to 3) {\n when (RegIntf.WSTRB(n) === 1.U) {\n reg_length_v(n) := RegIntf.WDATA(n*8+7, n*8)\n }\n }\n reg_length := reg_length_v.asTypeOf(UInt(32.W))\n }\n\n Length := reg_length\n\n //\n // axi_arready and axi_araddr\n //\n when (~axi_arready && RegIntf.ARVALID) {\n axi_arready := true.B\n axi_araddr := RegIntf.ARADDR\n }.otherwise {\n axi_arready := false.B\n }\n\n //\n // axi_rvalid and axi_rresp\n //\n when (axi_arready && RegIntf.ARVALID && ~axi_rvalid) {\n axi_rvalid := true.B\n axi_rresp := 0.U\n }.elsewhen (axi_rvalid && RegIntf.RREADY) {\n axi_rvalid := false.B\n }\n\n //\n // Read Enable Signal\n //\n slv_reg_rden := axi_arready && RegIntf.ARVALID && ~axi_rvalid\n\n //\n // Output Select Logic\n //\n reg_data_out := 0.U\n switch (axi_araddr(4, 2)) {\n is (0.U) { reg_data_out := Cat(reg_ie, 0.U(1.W)) }\n is (1.U) { reg_data_out := Cat(StatCode, IRQStatus.asUInt, Busy.asUInt) }\n is (3.U) { reg_data_out := reg_src_addr }\n is (4.U) { reg_data_out := reg_dst_addr }\n is (5.U) { reg_data_out := reg_length }\n is (6.U) { reg_data_out := MagicID.U }\n }\n\n //\n // axi_rdata\n //\n when (slv_reg_rden) {\n axi_rdata := reg_data_out\n }\n\n } // withClockAndReset(ACLK, reset)\n} // class RegFile\n", "groundtruth": " for (n <- 0 to 3) {\n when (RegIntf.WSTRB(n) === 1.U) {\n reg_src_addr_v(n) := RegIntf.WDATA(n*8+7, n*8)\n }\n }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "dma", "path": "dma/chisel/src/main/scala/aha/dma/regfile/RegFile.scala", "left_context": "package aha\npackage dma\n\n/* Chisel Imports */\nimport chisel3._\n\n/**\n * Configuration of a Register File\n *\n * @constructor constructs a configuration object for a register file\n * @param AddrWidth the width of the address bus on the register file interface\n * @param DataWidth the width of the data bus on the register file interface\n * @param MagicID the value of the ID register in the registe file\n */\n", "right_context": "\n/**\n * RegFile Trait\n */\ntrait RegFile extends RawModule {\n\n // Clock and Reset\n val ACLK = IO(Input(Clock()))\n val ARESETn = IO(Input(Bool()))\n\n // Control Signals\n val GO_Pulse = IO(Output(Bool()))\n val IRQEnable = IO(Output(Bool()))\n val IRQClear_Pulse = IO(Output(Bool()))\n val SrcAddr = IO(Output(UInt(32.W)))\n val DstAddr = IO(Output(UInt(32.W)))\n val Length = IO(Output(UInt(32.W)))\n\n // Status Signals\n val Busy = IO(Input(Bool()))\n val IRQStatus = IO(Input(Bool()))\n val StatCode = IO(Input(UInt(2.W)))\n\n // Register File Interface\n lazy val RegIntf = IO(Flipped(getRegFileIntf))\n\n // Type of Register File Interface\n type RegIntfTy <: Bundle\n\n // Register File Interface\n def getRegFileIntf : RegIntfTy\n\n} // trait RegFile\n\n/**\n * RegFile Factory\n */\nobject RegFile {\n\n /**\n * Build a register file based on the name and configuration provided\n */\n @throws(classOf[RuntimeException])\n def get(name: String, config: RegFileConfig) : RegFile = {\n\n if ((config.AddrWidth != 32) || (config.DataWidth != 32)) {\n throw new RuntimeException(\n \"\"\"register interfaces supports only address bus width\n of 32 and data bus width of 32\"\"\")\n } else {\n\n name.toLowerCase() match {\n\n // AXI Lite\n case \"axilite\" | \"axi-lite\" | \"axi_lite\" => new AXILiteRegFile(config.MagicID)\n\n // APB\n case \"apb\" => new APBRegFile(config.MagicID)\n\n // Unsupported\n case x => throw new RuntimeException(s\"unsupported register file type $x\")\n }\n\n }\n }\n}\n", "groundtruth": "case class RegFileConfig(AddrWidth: Int, DataWidth: Int, MagicID: Int)\n", "crossfile_context": "", "category": "Design Structure", "subcategory": "Parameterization and Configuration", "confidence": 0.85, "category_reason": "Params/Config case class"} {"task_id": "dma", "path": "dma/chisel/src/main/scala/aha/dma/top/DMA.scala", "left_context": "package aha\npackage dma\n\n/* Chisel Imports */\nimport chisel3._\nimport chisel3.util.isPow2\n\n/* Project Imports */\nimport aha.dma.CmdBundle\nimport aha.dma.util.{AXI4Intf, AXILiteIntf}\n\n/**\n * DMA Top-Level Module\n *\n * @constructor constructs a DMA engine with an AXI ID width, address bus\n * width, data bus width, store-and-forward fifo depth, and\n * the value of the peripheral ID register\n * @param IdWidth the width of AXI ID signals (AWID, BID, ARID, and RID)\n * @param AddrWidth the width of AXI address busses (AWADDR and ARADDR)\n * @param DataWidth the width of AXI data busses (WDATA and RDATA)\n * @param FifoDepth the depth of the store-and-forward fifo\n * @param RegFileName the name of the register file type to instantiate\n * @param MagicID the ID value to read from the ID_REG register\n *\n * @note transfer addresses must be aligned to the data bus width (DataWidth)\n * @note FifoDepth must be a power of 2\n */\nclass DMA ( IdWidth : Int,\n AddrWidth : Int,\n DataWidth : Int,\n FifoDepth : Int,\n RegFileName : String,\n MagicID : Int = 0x5A5A5A5A ) extends RawModule {\n\n // FifoDepth must be a power of 2\n require(isPow2(FifoDepth))\n\n // =========================================================================\n // I/O\n // =========================================================================\n\n // Clock and Rese\n val ACLK = IO(Input(Clock()))\n val ARESETn = IO(Input(Bool()))\n\n // Interrupt\n val Irq = IO(Output(Bool()))\n\n // AXI-Lite Register Interface\n lazy val RegIntf = IO(Flipped(controller.reg_file.getRegFileIntf))\n\n // AXI4 Interface\n val M_AXI = IO(new AXI4Intf(IdWidth, AddrWidth, DataWidth))\n\n // =========================================================================\n // Internal Logic\n // =========================================================================\n\n //\n // Instantiate Controller\n //\n val controller = Module( new Controller(\n AddrWidth,\n DataWidth,\n new CmdBundle(AddrWidth),\n new CmdBundle(AddrWidth),\n RegFileName,\n MagicID\n )\n )\n\n //\n // Instantiate DataMover\n //\n val data_mover = Module( new DataMover(\n IdWidth,\n AddrWidth,\n DataWidth,\n new CmdBundle(AddrWidth),\n new CmdBundle(AddrWidth),\n FifoDepth\n )\n )\n\n //\n", "right_context": " data_mover.ARESETn := ARESETn\n data_mover.M_AXI <> M_AXI\n\n controller.RdCmdIntf <> data_mover.RdCmdIntf\n controller.RdStatIntf <> data_mover.RdStatIntf\n\n controller.WrCmdIntf <> data_mover.WrCmdIntf\n controller.WrStatIntf <> data_mover.WrStatIntf\n\n //\n // Change Top-Level Name of the Register File Interface Bundle\n //\n RegIntf.suggestName(\"RegIntf\")\n\n} // class DMA\n", "groundtruth": " // Connections\n //\n\n controller.ACLK := ACLK\n controller.ARESETn := ARESETn\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.55, "category_reason": ":= connection"} {"task_id": "dma", "path": "dma/chisel/src/main/scala/aha/dma/top/Top.scala", "left_context": "package aha\npackage dma\n\n/* Scala Imports */\nimport scopt.OParser\n\n/* Chisel Imports */\nimport chisel3._\nimport chisel3.stage.ChiselStage\n\n/* Project Imports */\nimport aha.dma.util._\n\n/**\n * DMA Configuration\n */\ncase class DMAConfig (\n // Width of AXI ID\n IdWidth: Int = 2,\n", "right_context": " // (Supported: axi-lite and apb)\n RegFileName: String = \"apb\",\n // Depth of Internal Store-and-Forward FIFO\n FifoDepth: Int = 256,\n // Value of ID Register\n MagicID: Int = 0x5A5A5A5A,\n // Artifact Output Folder\n OutputDir: String = \"output/\"\n)\n\n\nobject Main extends App {\n\n val builder = OParser.builder[DMAConfig]\n\n val parser = {\n import builder._\n OParser.sequence(\n programName(\"dma-builder\"),\n head(\"aha-dma\", \"1.0\"),\n\n opt[Int]('i', \"id-width\")\n .action((x, c) => c.copy(IdWidth = x))\n .text(\"width of AXI ID fields\"),\n\n opt[Int]('a', \"addr-width\")\n .action((x, c) => c.copy(AddrWidth = x))\n .text(\"width of AXI address busses\"),\n\n opt[Int]('d', \"data-width\")\n .action((x, c) => c.copy(DataWidth = x))\n .text(\"width of AXI data busses\"),\n\n opt[String]('r', \"reg-file\")\n .action((x, c) => c.copy(RegFileName = x))\n .text(\"name of the type of register file to use (axi-lite or apb)\"),\n\n opt[Int]('f', \"fifo-depth\")\n .action((x, c) => c.copy(FifoDepth = x))\n .text(\"depth of internal store-and-forward fifo (must be power of 2)\"),\n\n opt[Int]('m', \"magic-id\")\n .action((x, c) => c.copy(MagicID = x))\n .text(\"value of ID register\"),\n\n opt[String]('o', \"output-dir\")\n .action((x, c) => c.copy(OutputDir = x))\n .text(\"artifact output directory\")\n )\n }\n\n OParser.parse(parser, args, DMAConfig()) match {\n case Some(config) => new ChiselStage().emitSystemVerilog(\n new DMA(\n config.IdWidth,\n config.AddrWidth,\n config.DataWidth,\n config.FifoDepth,\n config.RegFileName,\n config.MagicID\n ),\n Array(\"--target-dir\", config.OutputDir)\n )\n case _ => ()\n }\n} // object Main\n", "groundtruth": " // Width of AXI Address Bus\n AddrWidth: Int = 32,\n // Width of AXI Data Bus\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "dma", "path": "dma/chisel/src/main/scala/aha/dma/util/APB.scala", "left_context": "package aha\npackage dma\npackage util\n\n/* Chisel Imports */\nimport chisel3._\n\n/**\n * AMBA 3 APB Protocol v1.0 Interface\n *\n * @constructor constructs an APB interface bundle with the provided\n * address bus width and data bus width\n * @param AddrWidth the width of the APB address bus (PADDR)\n * @param DataWidth the width of the APB data busses (PWDATA and PRDATA)\n */\nclass APBIntf(AddrWidth: Int, DataWidth: Int) extends Bundle {\n val PADDR = Output(UInt(AddrWidth.W))\n", "right_context": "", "groundtruth": " val PSEL = Output(Bool())\n val PENABLE = Output(Bool())\n val PWRITE = Output(Bool())\n val PWDATA = Output(UInt(DataWidth.W))\n val PREADY = Input(Bool())\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.85, "category_reason": "Input/Output port declarations"} {"task_id": "dma", "path": "dma/chisel/src/main/scala/aha/dma/util/AXI4.scala", "left_context": "package aha\npackage dma\npackage util\n\n/* Chisel Imports */\nimport chisel3._\nimport chisel3.util.Decoupled\nimport chisel3.experimental.dataview._\n\n/**\n * AXI-Lite interface bundle\n *\n * @constructor constructs an AXI-Lite interface bundle with the provided\n * address bus width and data bus width\n * @param AddrWidth the width of AXI address busses (AWADDR and ARADDR)\n * @param DataWidth the width of AXI data busses (WDATA and RDATA)\n */\nclass AXILiteIntf(AddrWidth: Int, DataWidth: Int) extends Bundle {\n\n // AW Channel\n val AWREADY = Input(Bool())\n val AWVALID = Output(Bool())\n val AWADDR = Output(UInt(AddrWidth.W))\n val AWPROT = Output(UInt(3.W))\n\n // W Channel\n val WREADY = Input(Bool())\n val WVALID = Output(Bool())\n val WDATA = Output(UInt(DataWidth.W))\n val WSTRB = Output(UInt((DataWidth/8).W))\n\n // B Channel\n val BREADY = Output(Bool())\n val BVALID = Input(Bool())\n val BRESP = Input(UInt(2.W))\n\n // AR Channel\n val ARREADY = Input(Bool())\n val ARVALID = Output(Bool())\n val ARADDR = Output(UInt(AddrWidth.W))\n val ARPROT = Output(UInt(3.W))\n\n // R Channel\n val RREADY = Output(Bool())\n val RVALID = Input(Bool())\n val RDATA = Input(UInt(DataWidth.W))\n val RRESP = Input(UInt(2.W))\n}\n\n/**\n * Full AXI4 interface bundle\n *\n * @constructor constructs an AXI4 interface bundle with the provided\n * AXI ID width, address bus width and data bus width\n * @param AddrWidth the width of AXI address busses (AWADDR and ARADDR)\n * @param DataWidth the width of AXI data busses (WDATA and RDATA)\n */\nclass AXI4Intf(val IdWidth: Int,\n val AddrWidth: Int,\n val DataWidth: Int) extends Bundle {\n\n //\n // Write Address Channel\n //\n val AWID = Output(UInt(IdWidth.W))\n val AWADDR = Output(UInt(AddrWidth.W))\n val AWLEN = Output(UInt(8.W))\n val AWSIZE = Output(UInt(3.W))\n val AWBURST = Output(UInt(2.W))\n val AWLOCK = Output(Bool())\n val AWCACHE = Output(UInt(4.W))\n val AWPROT = Output(UInt(3.W))\n val AWVALID = Output(Bool())\n val AWREADY = Input(Bool())\n\n //\n // Write Data Channel\n //\n val WDATA = Output(UInt(DataWidth.W))\n val WSTRB = Output(UInt((DataWidth/8).W))\n val WLAST = Output(Bool())\n val WVALID = Output(Bool())\n val WREADY = Input(Bool())\n\n //\n // Write Response Channel\n //\n val BID = Input(UInt(IdWidth.W))\n val BRESP = Input(UInt(2.W))\n val BVALID = Input(Bool())\n val BREADY = Output(Bool())\n\n //\n // Read Address Channel\n //\n val ARID = Output(UInt(IdWidth.W))\n val ARADDR = Output(UInt(AddrWidth.W))\n val ARLEN = Output(UInt(8.W))\n val ARSIZE = Output(UInt(3.W))\n val ARBURST = Output(UInt(2.W))\n val ARLOCK = Output(Bool())\n val ARCACHE = Output(UInt(4.W))\n val ARPROT = Output(UInt(3.W))\n val ARVALID = Output(Bool())\n val ARREADY = Input(Bool())\n\n //\n // Read Data Channel\n //\n val RID = Input(UInt(IdWidth.W))\n val RDATA = Input(UInt(DataWidth.W))\n val RRESP = Input(UInt(2.W))\n val RLAST = Input(Bool())\n val RVALID = Input(Bool())\n val RREADY = Output(Bool())\n}\n\n\n/**\n * Bundle providing the write view of an AXI4 interface\n *\n * @constructor constructs an AXI4 write-view interface bundle with the\n * provided AXI ID width, address bus width and data bus width\n * @param IdWidth the width of AXI ID signals (AWID, BID, ARID, and RID)\n * @param AddrWidth the width of AXI address busses (AWADDR and ARADDR)\n * @param DataWidth the width of AXI data busses (WDATA and RDATA)\n */\nclass AXI4WrIntfView(val IdWidth: Int,\n val AddrWidth: Int,\n val DataWidth: Int) extends Bundle {\n\n val AW = Decoupled(new AXI4AddrPayload(IdWidth, AddrWidth))\n val W = Decoupled(new AXI4WrDataPayload(DataWidth))\n val B = Flipped(Decoupled(new AXI4WrRespPayload(IdWidth)))\n}\n\n/**\n * Provide the Chisel DataView implicit converters to allow viewing an AXI4 full\n * interface in write-view\n * {{\n * val fullAxi = new AXI4Intf(IdWIdth, AddrWidth, DataWidth)\n * val writeView = fullAxi.views[AXI4WrIntfView]\n * }}\n */\nobject AXI4WrIntfView {\n implicit val wrIntfView = PartialDataView[AXI4Intf, AXI4WrIntfView] (\n\n // Interface Mapping\n axi4 => new AXI4WrIntfView(axi4.IdWidth, axi4.AddrWidth, axi4.DataWidth),\n\n // Signal Mapping for AW Channel\n _.AWID -> _.AW.bits.ID,\n _.AWADDR -> _.AW.bits.ADDR,\n _.AWLEN -> _.AW.bits.LEN,\n _.AWSIZE -> _.AW.bits.SIZE,\n _.AWBURST -> _.AW.bits.BURST,\n _.AWLOCK -> _.AW.bits.LOCK,\n _.AWCACHE -> _.AW.bits.CACHE,\n _.AWPROT -> _.AW.bits.PROT,\n _.AWVALID -> _.AW.valid,\n _.AWREADY -> _.AW.ready,\n\n // Signal Mapping for W Channel\n _.WDATA -> _.W.bits.DATA,\n _.WSTRB -> _.W.bits.STRB,\n _.WLAST -> _.W.bits.LAST,\n _.WVALID -> _.W.valid,\n _.WREADY -> _.W.ready,\n\n // Signal Mapping for B Channel\n _.BID -> _.B.bits.ID,\n _.BRESP -> _.B.bits.RESP,\n _.BVALID -> _.B.valid,\n _.BREADY -> _.B.ready\n )\n}\n\n/**\n * Bundle providing the read view of an AXI4 interface\n *\n * @constructor constructs an AXI4 read-view interface bundle with the\n * provided AXI ID width, address bus width and data bus width\n * @param IdWidth the width of AXI ID signals (AWID, BID, ARID, and RID)\n * @param AddrWidth the width of AXI address busses (AWADDR and ARADDR)\n * @param DataWidth the width of AXI data busses (WDATA and RDATA)\n */\nclass AXI4RdIntfView(val IdWidth: Int,\n val AddrWidth: Int,\n val DataWidth: Int) extends Bundle {\n\n val AR = Decoupled(new AXI4AddrPayload(IdWidth, AddrWidth))\n val R = Flipped(Decoupled(new AXI4RdDataPayload(IdWidth, DataWidth)))\n}\n\n/**\n * Provide the Chisel DataView implicit converters to allow viewing an AXI4 full\n * interface in read-view\n * {{\n * val fullAxi = new AXI4Intf(IdWIdth, AddrWidth, DataWidth)\n * val readView = fullAxi.views[AXI4RdIntfView]\n * }}\n */\nobject AXI4RdIntfView {\n implicit val rdIntfView = PartialDataView[AXI4Intf, AXI4RdIntfView] (\n\n // Interface Mapping\n axi4 => new AXI4RdIntfView(axi4.IdWidth, axi4.AddrWidth, axi4.DataWidth),\n\n // Signal Mapping for AR Channel\n _.ARID -> _.AR.bits.ID,\n _.ARADDR -> _.AR.bits.ADDR,\n _.ARLEN -> _.AR.bits.LEN,\n _.ARSIZE -> _.AR.bits.SIZE,\n _.ARBURST -> _.AR.bits.BURST,\n _.ARLOCK -> _.AR.bits.LOCK,\n _.ARCACHE -> _.AR.bits.CACHE,\n _.ARPROT -> _.AR.bits.PROT,\n _.ARVALID -> _.AR.valid,\n _.ARREADY -> _.AR.ready,\n\n // Signal Mapping for R Channel\n _.RID -> _.R.bits.ID,\n _.RDATA -> _.R.bits.DATA,\n _.RRESP -> _.R.bits.RESP,\n _.RLAST -> _.R.bits.LAST,\n _.RVALID -> _.R.valid,\n _.RREADY -> _.R.ready\n )\n}\n\n/**\n * AXI4 address bus bundle\n *\n * @constructor constructs axi AXI4 address bundle with the provided\n * AXI ID width and address bus width\n * @param IdWidth the width of AXI ID signals (AWID, BID, ARID, and RID)\n * @param AddrWidth the width of AXI address busses (AWADDR and ARADDR)\n */\nclass AXI4AddrPayload(IdWidth: Int, AddrWidth: Int) extends Bundle {\n val ID = UInt(IdWidth.W)\n val ADDR = UInt(AddrWidth.W)\n val LEN = UInt(8.W)\n val SIZE = UInt(3.W)\n val BURST = UInt(2.W)\n val LOCK = Bool()\n val CACHE = UInt(4.W)\n val PROT = UInt(3.W)\n}\n\n/**\n * AXI4 write data bus bundle\n *\n * @constructor constructs axi AXI4 write data bundle with the provided\n * AXI data bus width\n * @param DataWidth the width of AXI data busses (WDATA and RDATA)\n */\nclass AXI4WrDataPayload(DataWidth: Int) extends Bundle {\n val DATA = UInt(DataWidth.W)\n val STRB = UInt((DataWidth/8).W)\n val LAST = Bool()\n}\n\n/**\n * AXI4 write response bus bundle\n *\n * @constructor constructs axi AXI4 write response bundle with the provided\n * AXI ID width\n * @param IdWidth the width of AXI ID signals (AWID, BID, ARID, and RID)\n */\nclass AXI4WrRespPayload(IdWidth: Int) extends Bundle {\n val ID = UInt(IdWidth.W)\n val RESP = UInt(2.W)\n}\n\n/**\n * AXI4 read data bus bundle\n *\n * @constructor constructs axi AXI4 read data bundle with the provided\n * AXI ID width and data bus width\n * @param IdWidth the width of AXI ID signals (AWID, BID, ARID, and RID)\n * @param DataWidth the width of AXI data busses (WDATA and RDATA)\n */\nclass AXI4RdDataPayload(IdWidth: Int, DataWidth: Int) extends Bundle {\n val ID = UInt(IdWidth.W)\n val DATA = UInt(DataWidth.W)\n", "right_context": "", "groundtruth": " val RESP = UInt(2.W)\n val LAST = Bool()\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.6, "category_reason": "val binding"} {"task_id": "dma", "path": "dma/chisel/src/main/scala/aha/dma/util/PeekQueue.scala", "left_context": "package aha\npackage dma\npackage util\n\n/* Chisel Imports */\nimport chisel3._\nimport chisel3.util.{Decoupled, isPow2}\n\n/* Project Imports */\nimport aha.dma.clog2\n\n/**\n * Peek queue (always puts the current value pointed to by the read pointer on\n * the dequeue interface)\n *\n * @constructor constructs a PeekQueue with the provided element type and\n * depth\n * @tparam T the type of elements to store in the queue\n * @param Depth the depth of the queue (must be a power of 2)\n */\nclass PeekQueue[T <: Data](Elem: T, Depth: Int) extends RawModule {\n\n // Depth must be a power of 2\n require(isPow2(Depth))\n\n // =========================================================================\n // I/O\n // =========================================================================\n\n // Clock and Reset\n val ACLK = IO(Input(Clock()))\n val ARESETn = IO(Input(Bool()))\n\n // Enqueue Interface\n val EnqIntf = IO(Flipped(Decoupled(Elem)))\n\n // Dequeue Interface\n val DeqIntf = IO(Decoupled(Elem))\n\n // =========================================================================\n // Chisel Work-Around for Active-Low Reset\n // =========================================================================\n\n val reset = (!ARESETn).asAsyncReset\n\n // =========================================================================\n // Internal Logic\n // =========================================================================\n\n val ADDR_WIDTH = clog2(Depth);\n\n val counter = withClockAndReset(ACLK, reset) { RegInit(0.U((ADDR_WIDTH + 1).W)) }\n", "right_context": " val wrptr = withClockAndReset(ACLK, reset) { RegInit(0.U(ADDR_WIDTH.W)) }\n\n // Internal Memory\n val mem = Mem(Depth, Elem)\n\n withClockAndReset(ACLK, reset) {\n\n //\n // Counter Update Logic\n //\n when (EnqIntf.ready && EnqIntf.valid && DeqIntf.ready && DeqIntf.valid) {\n // Simultaneous Enqueue and Dequeue\n counter := counter\n }.elsewhen (EnqIntf.ready && EnqIntf.valid) {\n // Enqueue\n counter := counter + 1.U\n }.elsewhen (DeqIntf.ready && DeqIntf.valid) {\n // Dequeue\n counter := counter - 1.U\n }\n\n //\n // Read Pointer Update Logic\n //\n when (DeqIntf.ready && DeqIntf.valid) {\n rdptr := rdptr + 1.U\n }\n\n //\n // Write Pointer Update Logic\n //\n when (EnqIntf.ready && EnqIntf.valid) {\n wrptr := wrptr + 1.U\n }\n\n //\n // Enqueue Operation (Synchronous)\n //\n when (EnqIntf.ready && EnqIntf.valid) {\n mem(wrptr) := EnqIntf.bits\n }\n\n //\n // Read Operation (Asynchronous)\n //\n DeqIntf.bits := mem(rdptr)\n\n //\n // Enqueue Ready and Dequeue Valid\n //\n EnqIntf.ready := counter =/= Depth.U\n DeqIntf.valid := counter =/= 0.U\n\n } // withClockAndReset(ACLK, reset_n)\n}\n", "groundtruth": " val rdptr = withClockAndReset(ACLK, reset) { RegInit(0.U(ADDR_WIDTH.W)) }\n", "crossfile_context": "", "category": "Storage Block", "subcategory": "Register-based Storage", "confidence": 0.85, "category_reason": "RegInit register"} {"task_id": "dma", "path": "dma/chisel/src/main/scala/aha/dma/writer/Writer.scala", "left_context": "package aha\npackage dma\n\n/* Chisel Imports */\nimport chisel3._\nimport chisel3.experimental.ChiselEnum\nimport chisel3.util.{Decoupled, Fill, is, switch}\n\n/* Project Imports */\nimport aha.dma.{clog2, CmdBundle, log2, MAX_BURST_BYTES}\nimport aha.dma.util.{AXI4WrIntfView, AXI4AddrPayload}\n\n/**\n * AXI4 Write Engine\n *\n * @constructor constructs a AXI4 write engine with an AXI ID width,\n * address bus width, data bus width, and the type of a\n * transfer command bundle\n * @tparam W transfer command bundle type for writer\n * @param IdWidth the width of AXI ID signals (AWID, BID, ARID, and RID)\n * @param AddrWidth the width of AXI address busses (AWADDR and ARADDR)\n * @param DataWidth the width of AXI data busses (WDATA and RDATA)\n * @param Cmd the bundle to use for transfer commands\n *\n * @note transfer addresses must be aligned to the data bus width (DataWidth)\n * @note transfers must not cross the [[MAX_BURST_BYTES]]\n */\nclass Writer[W <: CmdBundle](IdWidth: Int,\n AddrWidth: Int,\n DataWidth: Int,\n Cmd : W) extends RawModule {\n\n import Writer.State\n import Writer.State._\n\n // =========================================================================\n // I/O\n // =========================================================================\n\n // Clock and Reset\n val ACLK = IO(Input(Clock()))\n val ARESETn = IO(Input(Bool()))\n\n // Command/Stat Interfaces\n val CmdIntf = IO(Flipped(Decoupled(Cmd)))\n val StatIntf = IO(Decoupled(UInt(2.W)))\n\n // Data Packet Interface\n val DataIntf = IO(Flipped(Decoupled(UInt(DataWidth.W))))\n\n // AXI4 Write Interface\n val WriteIntf = IO(new AXI4WrIntfView(IdWidth, AddrWidth, DataWidth))\n\n // =========================================================================\n // Chisel Work-Around for Active-Low Reset\n // =========================================================================\n\n val reset = (!ARESETn).asAsyncReset\n\n // =========================================================================\n // Internal Logic\n // =========================================================================\n\n val n_lanes = DataWidth/8\n\n val state = withClockAndReset(ACLK, reset) { RegInit(sIDLE) }\n val write_resp = withClockAndReset(ACLK, reset) { RegInit(0.U(2.W)) }\n val num_bytes = withClockAndReset(ACLK, reset) { RegInit(0.U(clog2(MAX_BURST_BYTES).W)) }\n val last_beat = Wire(Bool())\n\n // AW Channel Signals\n val aw_size = log2(DataWidth/8)\n val aw_addr = (CmdIntf.bits.Address >> aw_size.U) << aw_size.U\n val aw_len = Wire(UInt(8.W))\n", "right_context": " val aw_payload = withClockAndReset(ACLK, reset) {\n RegInit(0.U.asTypeOf(new AXI4AddrPayload(IdWidth, AddrWidth)))\n }\n\n // W Channel Signals\n val w_strb = Wire(UInt((DataWidth/8).W))\n val w_valid = Wire(Bool())\n val w_last = Wire(Bool())\n\n withClockAndReset(ACLK, reset) {\n\n //\n // State Register Update Logic\n //\n switch (state) {\n is (sIDLE) {\n when (CmdIntf.valid) {\n state := sADDR\n }\n } // sIDLE\n is (sADDR) {\n when (WriteIntf.AW.ready) {\n state := sDATA\n }\n } // sADDR\n is (sDATA) {\n when (last_beat) {\n state := sRESP\n }\n } // sDATA\n is (sRESP) {\n when (WriteIntf.B.valid) {\n state := sSTAT\n }\n } // sRESP\n is (sSTAT) {\n when (StatIntf.ready) {\n state := sIDLE\n }\n }\n } // switch(state)\n\n //\n // AW Channel Signals\n //\n switch (state) {\n is (sIDLE) {\n when (CmdIntf.valid) {\n aw_valid := true.B\n aw_payload.ID := 0.U\n aw_payload.ADDR := aw_addr\n aw_payload.LEN := aw_len\n aw_payload.SIZE := aw_size.U\n aw_payload.BURST := 1.U\n aw_payload.LOCK := false.B\n aw_payload.CACHE := 2.U\n aw_payload.PROT := 2.U\n }.otherwise {\n aw_valid := false.B\n }\n } // sIDLE\n is (sADDR) {\n when (WriteIntf.AW.ready) {\n aw_valid := false.B\n }\n } // sADDR\n } // switch(state)\n\n WriteIntf.AW.valid := aw_valid\n WriteIntf.AW.bits := aw_payload\n\n //\n // Write Response Capture\n //\n switch (state) {\n is (sIDLE) {\n write_resp := 0.U\n } // sIDLE\n is (sRESP) {\n when (WriteIntf.B.valid) {\n write_resp := WriteIntf.B.bits.RESP\n }\n } // sRESP\n } // switch (state)\n\n //\n // WDATA\n //\n when (state === sDATA) {\n WriteIntf.W.bits.DATA := DataIntf.bits\n }.otherwise {\n WriteIntf.W.bits.DATA := 0.U\n }\n\n //\n // num_bytes\n //\n switch (state) {\n is (sIDLE) {\n when (CmdIntf.valid) {\n num_bytes := CmdIntf.bits.NumBytes\n }.otherwise {\n num_bytes := 0.U\n }\n } // sIDLE\n is (sDATA) {\n when (WriteIntf.W.valid && WriteIntf.W.ready) {\n when (num_bytes > n_lanes.U) {\n num_bytes := num_bytes - n_lanes.U\n }\n }\n } // sDATA\n is (sRESP) {\n num_bytes := 0.U\n } // sRESP\n } // switch (state)\n\n //\n // WSTRB\n //\n val choices = VecInit((0 until n_lanes).map(x => (1 << x) - 1).map(_.U))\n when (state === sDATA) {\n when (num_bytes >= n_lanes.U) {\n w_strb := Fill(n_lanes, 1.U(1.W))\n }.otherwise {\n w_strb := choices(num_bytes(log2(n_lanes)-1, 0))\n }\n }.otherwise {\n w_strb := 0.U\n }\n\n WriteIntf.W.bits.STRB := w_strb\n\n //\n // WVALID\n //\n when (state === sDATA) {\n w_valid := DataIntf.valid\n }.otherwise {\n w_valid := false.B\n }\n\n WriteIntf.W.valid := w_valid\n\n //\n // WLAST\n //\n when (state === sDATA) {\n w_last := num_bytes <= n_lanes.U\n }.otherwise {\n w_last := false.B\n }\n\n WriteIntf.W.bits.LAST := w_last\n\n //\n // Internal Signals\n //\n last_beat := WriteIntf.W.valid && WriteIntf.W.ready && WriteIntf.W.bits.LAST\n aw_len := ((CmdIntf.bits.NumBytes >> aw_size.U) +\n CmdIntf.bits.NumBytes(aw_size-1, 0).orR) - 1.U\n\n //\n // BREADY\n //\n WriteIntf.B.ready := state === sRESP\n\n //\n // Status Signals\n //\n StatIntf.valid := state === sSTAT\n StatIntf.bits := write_resp\n\n //\n // Command Interface Ready\n //\n CmdIntf.ready := state === sIDLE\n\n //\n // Data Interface Ready\n //\n DataIntf.ready := (state === sDATA) && WriteIntf.W.ready\n\n } // withClockAndReset(ACLK, reset)\n}\n\n/**\n * Provides the states for the [[Writer]] finite state machine\n */\nobject Writer {\n\n /**\n * States for Writer FSM\n */\n object State extends ChiselEnum {\n val sIDLE, sADDR, sDATA, sRESP, sSTAT = Value\n } // object State\n} // object Writer\n", "groundtruth": " val aw_valid = withClockAndReset(ACLK, reset) { RegInit(false.B) }\n", "crossfile_context": "", "category": "Storage Block", "subcategory": "Register-based Storage", "confidence": 0.85, "category_reason": "RegInit register"} {"task_id": "icenet", "path": "icenet/src/main/scala/Aligner.scala", "left_context": "package icenet\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.unittest.UnitTest\nimport IceNetConsts._\n\nclass Aligner(dataBits: Int) extends Module {\n val dataBytes = dataBits / 8\n\n val io = IO(new StreamIO(dataBits))\n\n val data = RegInit(0.U(dataBits.W))\n val keep = RegInit(0.U(dataBytes.W))\n val last = RegInit(false.B)\n val nbytes = RegInit(0.U(log2Ceil(dataBytes + 1).W))\n\n assert(!io.in.valid || io.in.bits.keep.orR,\n \"Aligner cannot handle an empty flit\")\n\n val rshift = PriorityEncoder(io.in.bits.keep)\n val full_keep = ((io.in.bits.keep >> rshift) << nbytes) | keep\n\n val in_mask = FillInterleaved(8, io.in.bits.keep)\n val in_data = io.in.bits.data & in_mask\n\n val rshift_bit = Cat(rshift, 0.U(3.W))\n val nbits = Cat(nbytes, 0.U(3.W))\n val bitmask = FillInterleaved(8, keep)\n val full_data = ((in_data >> rshift_bit) << nbits) | (data & bitmask)\n val full_nbytes = PopCount(full_keep)\n val fwd_last = io.in.bits.last && (full_keep >> dataBytes.U) === 0.U\n\n io.out.valid := (last && nbytes > 0.U) ||\n (io.in.valid && (fwd_last || full_nbytes >= dataBytes.U))\n io.out.bits.data := Mux(last, data, full_data(dataBits-1, 0))\n io.out.bits.keep := Mux(last, keep, full_keep(dataBytes-1, 0))\n io.out.bits.last := last || fwd_last\n\n io.in.ready := full_nbytes < dataBytes.U ||\n (io.out.ready && !last)\n\n when (io.in.fire && io.out.fire) {\n data := full_data >> dataBits.U\n keep := full_keep >> dataBytes.U\n last := io.in.bits.last && !fwd_last\n nbytes := Mux(fwd_last, 0.U, full_nbytes - dataBytes.U)\n } .elsewhen (io.in.fire) {\n data := full_data\n keep := full_keep\n last := io.in.bits.last\n nbytes := full_nbytes\n } .elsewhen (io.out.fire) {\n data := 0.U\n keep := 0.U\n last := false.B\n nbytes := 0.U\n }\n}\n\nclass AlignerTest extends UnitTest {\n val inData = VecInit(\n \"h0011223344556677\".U,\n \"h8899AABBCCDDEEFF\".U,\n \"h0123456789ABCDEF\".U,\n \"hFEDCBA9876543210\".U)\n val inKeep = VecInit(\n \"b11111100\".U,\n \"b01111000\".U,\n \"b00001111\".U,\n \"b11110000\".U)\n val inLast = VecInit(false.B, false.B, true.B, true.B)\n\n val outData = VecInit(\n \"hBBCC001122334455\".U,\n \"h000089ABCDEF99AA\".U,\n \"h00000000FEDCBA98\".U)\n val outKeep = VecInit(\n \"b11111111\".U,\n \"b00111111\".U,\n \"b00001111\".U)\n val outLast = VecInit(false.B, true.B, true.B)\n\n val started = RegInit(false.B)\n val sending = RegInit(false.B)\n val receiving = RegInit(false.B)\n\n val aligner = Module(new Aligner(NET_IF_WIDTH))\n\n val (inIdx, inDone) = Counter(aligner.io.in.fire, inData.size)\n val (outIdx, outDone) = Counter(aligner.io.out.fire, outData.size)\n\n aligner.io.in.valid := sending\n aligner.io.in.bits.data := inData(inIdx)\n aligner.io.in.bits.keep := inKeep(inIdx)\n aligner.io.in.bits.last := inLast(inIdx)\n aligner.io.out.ready := receiving\n\n when (io.start && !started) {\n started := true.B\n sending := true.B\n receiving := true.B\n }\n", "right_context": " when (outDone) { receiving := false.B }\n\n io.finished := started && !sending && !receiving\n\n def compareData(a: UInt, b: UInt, keep: UInt) = {\n val bitmask = FillInterleaved(8, keep)\n (a & bitmask) === (b & bitmask)\n }\n\n assert(!aligner.io.out.valid ||\n (compareData(\n aligner.io.out.bits.data,\n outData(outIdx),\n aligner.io.out.bits.keep) &&\n aligner.io.out.bits.keep === outKeep(outIdx) &&\n aligner.io.out.bits.last === outLast(outIdx)),\n \"AlignerTest: output does not match expected\")\n}\n", "groundtruth": " when (inDone) { sending := false.B }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "icenet", "path": "icenet/src/main/scala/Buffer.scala", "left_context": "package icenet\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.unittest.UnitTest\nimport freechips.rocketchip.util.TwoWayCounter\nimport scala.util.Random\nimport IceNetConsts._\n\nclass BufferBRAM[T <: Data](n: Int, typ: T) extends Module {\n val addrBits = log2Ceil(n)\n val io = IO(new Bundle {\n // The value in data becomes valid one cycle after enable is asserted.\n // The value is held so long as enable is false\n val read = new Bundle {\n val en = Input(Bool())\n val addr = Input(UInt(addrBits.W))\n val data = Output(typ)\n }\n val write = new Bundle {\n val en = Input(Bool())\n val addr = Input(UInt(addrBits.W))\n val data = Input(typ)\n }\n })\n\n val ram = Mem(n, typ)\n\n val wen = RegNext(io.write.en, false.B)\n val waddr = RegNext(io.write.addr)\n val wdata = RegNext(io.write.data)\n\n when (wen) { ram.write(waddr, wdata) }\n\n val rread_data = RegEnable(ram.read(io.read.addr), io.read.en)\n val rbypass = RegEnable(io.read.addr === waddr && wen, io.read.en)\n val rbypass_data = RegEnable(wdata, io.read.en)\n\n io.read.data := Mux(rbypass, rbypass_data, rread_data)\n}\n\n/**\n * Buffers incoming packets without backpressuring\n * Drops at packet boundaries if buffer fills us.\n * @bufWords Number of flits held by the buffer\n * @maxBytes Maximum number of bytes in a packet\n * @headerBytes Number of bytes in a header\n * @headerType Bundle type for header\n * @wordBytes Number of bytes in a flit\n * @dropChecks Sequence of functions that can trigger a drop by asserting Bool\n * @dropless If true, dropped packet causes assertion failure\n */\nclass NetworkPacketBuffer[T <: Data](\n bufWords: Int,\n maxBytes: Int = ETH_JUMBO_MAX_BYTES,\n headerBytes: Int = ETH_HEAD_BYTES,\n headerType: T = new EthernetHeader,\n wordBytes: Int = NET_IF_WIDTH / 8,\n dropChecks: Seq[(T, StreamChannel, Bool) => Bool] = Nil,\n dropless: Boolean = false) extends Module {\n\n val maxWords = (maxBytes - 1) / wordBytes + 1\n val headerWords = headerBytes / wordBytes\n val wordBits = wordBytes * 8\n val nPackets = (bufWords - 1) / (headerWords + 1) + 1\n\n require(headerBytes % wordBytes == 0)\n\n val idxBits = log2Ceil(bufWords)\n val phaseBits = log2Ceil(nPackets + 1)\n val lenBits = log2Ceil(maxBytes + 1)\n val byteOffset = log2Ceil(wordBytes)\n\n val io = IO(new Bundle {\n val stream = new StreamIO(wordBytes * 8)\n val length = Valid(UInt(lenBits.W))\n val count = Output(UInt(log2Ceil(nPackets+1).W))\n val free = Output(UInt(8.W))\n })\n\n def discontinuous(bits: UInt, w: Int): Bool =\n (1 until w).map(i => bits(i) && !bits(i-1)).reduce(_ || _)\n\n assert(!io.stream.in.valid ||\n Mux(io.stream.in.bits.last,\n !discontinuous(io.stream.in.bits.keep, wordBytes),\n io.stream.in.bits.keep.andR),\n \"NetworkPacketBuffer does not handle missing data\")\n\n val dataBuffer = Module(new BufferBRAM(bufWords, Bits(wordBits.W)))\n val headerVec = Reg(Vec(headerWords, Bits(wordBits.W)))\n val header = headerVec.asTypeOf(headerType)\n\n val lenBuffer = Module(new BufferBRAM(nPackets, UInt(lenBits.W)))\n\n val bufHead = RegInit(0.U(idxBits.W))\n val bufTail = RegInit(0.U(idxBits.W))\n val startHead = Reg(UInt(idxBits.W))\n val revertHead = WireInit(false.B)\n\n val maybeFull = RegInit(false.B)\n val ptrMatch = bufHead === bufTail\n val bufFull = maybeFull && ptrMatch\n val bufEmpty = !maybeFull && ptrMatch\n\n val inIdx = RegInit(0.U(idxBits.W))\n val inDrop = RegInit(false.B)\n val inLen = RegInit(0.U(lenBits.W))\n val outIdx = RegInit(0.U(idxBits.W))\n\n val inPhase = RegInit(0.U(phaseBits.W))\n val outPhase = RegInit(0.U(phaseBits.W))\n val pktCount = RegInit(0.U(phaseBits.W))\n val nextLen = inLen + PopCount(io.stream.in.bits.keep)\n val hasPackets = pktCount > 0.U\n\n assert(pktCount <= nPackets.U, \"Accepted more packets than possible\")\n\n def bytesToWords(nbytes: UInt): UInt =\n nbytes(lenBits-1, byteOffset) + nbytes(byteOffset-1, 0).orR\n\n def finalKeep(nbytes: UInt): UInt = {\n val remBytes = nbytes(byteOffset-1, 0)\n val finalBytes = Mux(remBytes.orR, remBytes, wordBytes.U)\n (1.U << finalBytes) - 1.U\n }\n\n val length = lenBuffer.io.read.data\n val numWords = bytesToWords(length)\n // Need one cycle to read out packet length\n val lengthKnown = RegInit(false.B)\n val readLen = !lengthKnown && hasPackets\n\n val outLast = outIdx === (numWords - 1.U)\n val outValidReg = RegInit(false.B)\n\n val ren = (io.stream.out.ready || !outValidReg) && lengthKnown && !bufEmpty\n val wen = WireInit(false.B)\n val hwen = wen && inIdx < headerWords.U\n\n val setLength = WireInit(false.B)\n val clearLength = ren && outLast\n\n pktCount := pktCount + setLength - clearLength\n\n val outLastReg = RegEnable(outLast, ren)\n val outIdxReg = RegEnable(outIdx, ren)\n\n io.stream.out.valid := outValidReg\n io.stream.out.bits.data := dataBuffer.io.read.data\n io.stream.out.bits.last := outLastReg\n io.stream.out.bits.keep := Mux(outLastReg, finalKeep(length), ~0.U(wordBytes.W))\n io.stream.in.ready := true.B\n io.length.bits := lenBuffer.io.read.data\n io.length.valid := lengthKnown\n io.count := pktCount\n\n def wrapInc(x: UInt, n: Int) = Mux(x === (n - 1).U, 0.U, x + 1.U)\n\n dataBuffer.io.read.en := ren\n dataBuffer.io.read.addr := bufTail\n dataBuffer.io.write.en := wen\n dataBuffer.io.write.addr := bufHead\n dataBuffer.io.write.data := io.stream.in.bits.data\n\n lenBuffer.io.read.en := readLen\n lenBuffer.io.read.addr := outPhase\n lenBuffer.io.write.en := setLength\n lenBuffer.io.write.addr := inPhase\n lenBuffer.io.write.data := nextLen\n\n val headerValid = inIdx >= headerWords.U\n val customDrop = dropChecks.map(check => check(\n header,\n io.stream.in.bits,\n io.stream.in.fire && headerValid))\n .foldLeft(false.B)(_ || _)\n val startDropping =\n (inPhase === outPhase && hasPackets) ||\n (inIdx === maxWords.U) || bufFull\n\n val capDrop = startDropping || inDrop\n val nonCapDrop = !headerValid || customDrop\n val anyDrop = capDrop || nonCapDrop\n val dropLastFire = anyDrop && io.stream.in.fire && io.stream.in.bits.last\n\n // io.free indicates the number of flits being freed up on a cycle\n io.free := ren + Mux(dropLastFire, inIdx + 1.U, 0.U)\n\n when (io.stream.out.fire) { outValidReg := false.B }\n\n when (readLen) { lengthKnown := true.B }\n\n when (ren) {\n outValidReg := true.B\n bufTail := wrapInc(bufTail, bufWords)\n outIdx := outIdx + 1.U\n\n when (outLast) {\n outIdx := 0.U\n outPhase := wrapInc(outPhase, nPackets)\n lengthKnown := false.B\n }\n }\n\n when (hwen) { headerVec(inIdx) := io.stream.in.bits.data }\n\n when (wen) { bufHead := wrapInc(bufHead, bufWords) }\n\n when (ren =/= wen) { maybeFull := wen }\n\n when (io.stream.in.fire) {\n", "right_context": " when (startDropping) { inDrop := true.B }\n wen := !startDropping && !inDrop\n when (inIdx =/= (bufWords - 1).U) { inIdx := inIdx + 1.U }\n\n inLen := nextLen\n\n when (io.stream.in.bits.last) {\n val nextPhase = wrapInc(inPhase, nPackets)\n // Drop packets if there aren't more than headerBytes amount of data\n when (!anyDrop) {\n setLength := true.B\n inPhase := nextPhase\n } .otherwise {\n wen := false.B\n revertHead := inIdx =/= 0.U\n if (dropless) {\n assert(!capDrop,\n \"Packet dropped by buffer due to insufficient capacity\")\n } else {\n printf(\"WARNING: dropped packet with %d flits\\n\", inIdx + 1.U)\n }\n }\n inIdx := 0.U\n inLen := 0.U\n inDrop := false.B\n }\n }\n\n when (revertHead) {\n bufHead := startHead\n maybeFull := false.B\n }\n}\n\nclass NetworkPacketBufferTest extends UnitTest(100000) {\n val buffer = Module(new NetworkPacketBuffer(\n bufWords = 12,\n maxBytes = 32,\n headerBytes = 8,\n headerType = UInt(64.W),\n wordBytes = 4))\n\n val inPackets = Seq(\n (10, false), // drop because too long\n (4, true),\n (1, false), // drop because too short\n (5, false),\n (7, true),\n (8, false),\n (6, false), // drop because buffer full\n (4, true),\n (3, false),\n (5, true),\n (6, false),\n (4, true),\n (5, true))\n\n val outPackets = Seq(\n (4, true),\n (5, false),\n (7, true),\n (8, false),\n (4, true),\n (3, false),\n (5, true),\n (6, true),\n (4, false),\n (5, true))\n\n val phaseBits = log2Ceil(inPackets.length)\n val idxBits = 4\n\n val inPacketLengths = VecInit(inPackets.map {\n case (x, _) => (x - 1).U(idxBits.W)\n })\n val inPacketSwitch = VecInit(inPackets.map(_._2.B))\n\n val outPacketLengths = VecInit(outPackets.map {\n case (x, _) => (x - 1).U(idxBits.W)\n })\n val outPacketSwitch = VecInit(outPackets.map(_._2.B))\n\n val inPhase = RegInit(0.U(phaseBits.W))\n val outPhase = RegInit(0.U(phaseBits.W))\n\n val inIdx = RegInit(0.U(idxBits.W))\n val outIdx = RegInit(0.U(idxBits.W))\n\n val s_start :: s_input :: s_output :: s_done :: Nil = Enum(4)\n val state = RegInit(s_start)\n\n buffer.io.stream.in.valid := state === s_input\n buffer.io.stream.in.bits.data := inIdx\n buffer.io.stream.in.bits.keep := ~0.U(32.W)\n buffer.io.stream.in.bits.last := inIdx === inPacketLengths(inPhase)\n buffer.io.stream.out.ready := state === s_output\n\n when (io.start && state === s_start) {\n state := s_input\n }\n\n when (buffer.io.stream.in.fire) {\n inIdx := inIdx + 1.U\n when (buffer.io.stream.in.bits.last) {\n inIdx := 0.U\n inPhase := inPhase + 1.U\n when (inPacketSwitch(inPhase)) { state := s_output }\n }\n }\n\n when (buffer.io.stream.out.fire) {\n outIdx := outIdx + 1.U\n when (buffer.io.stream.out.bits.last) {\n outIdx := 0.U\n outPhase := outPhase + 1.U\n when (outPacketSwitch(outPhase)) { state := s_input }\n when (outPhase === (outPackets.length - 1).U) { state := s_done }\n }\n }\n\n assert(!buffer.io.stream.out.valid || buffer.io.stream.out.bits.data === outIdx,\n \"NetworkPacketBufferTest: got wrong output data\")\n assert(!buffer.io.stream.out.valid || !buffer.io.stream.out.bits.last ||\n outIdx === outPacketLengths(outPhase),\n \"NetworkPacketBufferTest: got output packet with wrong length\")\n\n io.finished := state === s_done\n}\n\nclass ReservationBufferAlloc(nXacts: Int, nWords: Int) extends Bundle {\n private val xactIdBits = log2Ceil(nXacts)\n private val countBits = log2Ceil(nWords + 1)\n\n val id = UInt(xactIdBits.W)\n val count = UInt(countBits.W)\n\n}\n\nclass ReservationBufferData(nXacts: Int, dataBits: Int) extends Bundle {\n private val xactIdBits = log2Ceil(nXacts)\n\n val id = UInt(xactIdBits.W)\n val data = new StreamChannel(dataBits)\n\n}\n\nclass ReservationBuffer(nXacts: Int, nWords: Int, dataBits: Int) extends Module {\n private val xactIdBits = log2Ceil(nXacts)\n private val countBits = log2Ceil(nWords + 1)\n\n require(nXacts <= nWords)\n\n val io = IO(new Bundle {\n val alloc = Flipped(Decoupled(new ReservationBufferAlloc(nXacts, nWords)))\n val in = Flipped(Decoupled(new ReservationBufferData(nXacts, dataBits)))\n val out = Decoupled(new StreamChannel(dataBits))\n })\n\n def incWrap(cur: UInt, inc: UInt): UInt = {\n val unwrapped = cur +& inc\n Mux(unwrapped >= nWords.U, unwrapped - nWords.U, unwrapped)\n }\n\n val buffer = Module(new BufferBRAM(nWords, new StreamChannel(dataBits)))\n val bufValid = RegInit(0.U(nWords.W))\n\n val head = RegInit(0.U(countBits.W))\n val tail = RegInit(0.U(countBits.W))\n val count = RegInit(0.U(countBits.W))\n\n val full = (count + io.alloc.bits.count) > nWords.U\n val xactHeads = Reg(Vec(nXacts, UInt(countBits.W)))\n val curXactHead = xactHeads(io.in.bits.id)\n\n val occupied = RegInit(false.B)\n val ren = (!occupied || io.out.ready) && (bufValid >> tail)(0)\n\n count := count +\n Mux(io.alloc.fire, io.alloc.bits.count, 0.U) -\n Mux(io.out.fire, 1.U, 0.U)\n bufValid := (bufValid | Mux(io.in.fire, UIntToOH(curXactHead), 0.U)) &\n ~Mux(ren, UIntToOH(tail), 0.U)\n\n io.alloc.ready := !full\n io.in.ready := true.B\n io.out.valid := occupied\n io.out.bits := buffer.io.read.data\n\n buffer.io.write.en := io.in.fire\n buffer.io.write.addr := curXactHead\n buffer.io.write.data := io.in.bits.data\n buffer.io.read.en := ren\n buffer.io.read.addr := tail\n\n when (io.alloc.fire) {\n xactHeads(io.alloc.bits.id) := head\n head := incWrap(head, io.alloc.bits.count)\n }\n\n when (io.in.fire) {\n xactHeads(io.in.bits.id) := incWrap(curXactHead, 1.U)\n }\n\n when (io.out.fire) { occupied := false.B }\n\n when (ren) {\n occupied := true.B\n tail := incWrap(tail, 1.U)\n }\n}\n\nclass PacketCollectionBuffer(bufWords: Int) extends Module {\n val io = IO(new StreamIO(NET_IF_WIDTH))\n\n val headerWords = ETH_HEAD_BYTES / NET_IF_BYTES\n val maxPackets = (bufWords - 1) / (headerWords + 1) + 1\n\n val queue = Module(new Queue(new StreamChannel(NET_IF_WIDTH), bufWords))\n val pktCount = TwoWayCounter(\n queue.io.enq.fire && queue.io.enq.bits.last,\n queue.io.deq.fire && queue.io.deq.bits.last,\n maxPackets)\n val canDequeue = pktCount > 0.U\n\n queue.io.enq <> io.in\n io.out.valid := queue.io.deq.valid && canDequeue\n io.out.bits := queue.io.deq.bits\n queue.io.deq.ready := io.out.ready && canDequeue\n}\n", "groundtruth": " when (inIdx === 0.U) { startHead := bufHead }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "icenet", "path": "icenet/src/main/scala/Checksum.scala", "left_context": "package icenet\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.unittest.UnitTest\nimport freechips.rocketchip.util.{DecoupledHelper, UIntIsOneOf}\nimport IceNetConsts._\nimport NetworkHelpers._\n\nclass ChecksumCalcRequest extends Bundle {\n val check = Bool()\n val start = UInt(16.W)\n val init = UInt(16.W)\n}\n\nclass ChecksumRewriteRequest extends Bundle {\n val check = Bool()\n val offset = UInt(16.W)\n val start = UInt(16.W)\n val init = UInt(16.W)\n}\n\nclass ChecksumCalc(dataBits: Int) extends Module {\n val dataBytes = dataBits / 8\n\n val io = IO(new Bundle {\n val req = Flipped(Decoupled(new ChecksumCalcRequest))\n val stream = new StreamIO(dataBits)\n val result = Decoupled(UInt(16.W))\n })\n\n val csum = Reg(UInt((dataBits + 16).W))\n val check = Reg(Bool())\n val start = Reg(UInt(16.W))\n val startPos = Reg(UInt(16.W))\n val nextStartPos = startPos + dataBytes.U\n val sumMask = (0 until dataBytes).map { i =>\n io.stream.in.bits.keep(i) && (startPos + i.U) >= start\n }\n val sumData = io.stream.in.bits.data & FillInterleaved(8, sumMask)\n\n val s_req :: s_stream :: s_fold :: s_result :: Nil = Enum(4)\n val state = RegInit(s_req)\n\n io.req.ready := state === s_req\n io.stream.out.valid := state === s_stream && io.stream.in.valid\n io.stream.in.ready := state === s_stream && io.stream.out.ready\n io.stream.out.bits := io.stream.in.bits\n io.result.valid := state === s_result\n io.result.bits := csum(15, 0)\n\n when (io.req.fire) {\n check := io.req.bits.check\n start := io.req.bits.start\n csum := io.req.bits.init\n startPos := 0.U\n state := s_stream\n }\n\n when (io.stream.in.fire) {\n when (check) {\n csum := csum + sumData\n startPos := nextStartPos\n }\n\n when (io.stream.in.bits.last) {\n state := Mux(check, s_fold, s_req)\n }\n }\n\n when (state === s_fold) {\n val upper = csum(15 + dataBits, 16)\n val lower = csum(15, 0)\n\n when (upper === 0.U) {\n csum := ~lower\n state := s_result\n } .otherwise {\n csum := upper + lower\n }\n }\n\n when (io.result.fire) { state := s_req }\n}\n\nclass ChecksumRewrite(dataBits: Int, nBufFlits: Int) extends Module {\n val dataBytes = dataBits / 8\n\n val io = IO(new Bundle {\n val req = Flipped(Decoupled(new ChecksumRewriteRequest))\n val stream = new StreamIO(dataBits)\n })\n\n val reqq = Module(new Queue(new ChecksumRewriteRequest, 2))\n val calc = Module(new ChecksumCalc(dataBits))\n val buffer = Module(new Queue(new StreamChannel(dataBits), nBufFlits))\n val offset = Reg(UInt(16.W))\n val check = Reg(Bool())\n val csum = Reg(UInt(16.W))\n\n val reqHelper = DecoupledHelper(\n io.req.valid,\n calc.io.req.ready,\n reqq.io.enq.ready)\n\n io.req.ready := reqHelper.fire(io.req.valid)\n calc.io.req.valid := reqHelper.fire(calc.io.req.ready)\n calc.io.req.bits.check := io.req.bits.check\n calc.io.req.bits.start := io.req.bits.start\n calc.io.req.bits.init := io.req.bits.init\n reqq.io.enq.valid := reqHelper.fire(reqq.io.enq.ready)\n reqq.io.enq.bits := io.req.bits\n calc.io.stream.in <> io.stream.in\n buffer.io.enq <> calc.io.stream.out\n\n val byteOffBits = log2Ceil(dataBytes)\n val startPos = Reg(UInt(16.W))\n val nextStartPos = startPos + dataBytes.U\n val baseData = buffer.io.deq.bits.data\n val shiftAmt = Cat((offset - startPos)(byteOffBits-1, 0), 0.U(3.W))\n val dataMask = ~(~0.U(16.W) << shiftAmt)\n val csumShifted = csum << shiftAmt\n val replace = check && (offset >= startPos) && (offset < nextStartPos)\n val outData = Mux(replace, (baseData & dataMask) | csumShifted, baseData)\n\n val s_req :: s_wait :: s_flush :: Nil = Enum(3)\n val state = RegInit(s_req)\n\n when (reqq.io.deq.fire) {\n check := reqq.io.deq.bits.check\n offset := reqq.io.deq.bits.offset\n startPos := 0.U\n state := Mux(reqq.io.deq.bits.check, s_wait, s_flush)\n }\n\n when (calc.io.result.fire) {\n csum := calc.io.result.bits\n state := s_flush\n }\n\n when (io.stream.out.fire) {\n startPos := nextStartPos\n when (io.stream.out.bits.last) { state := s_req }\n }\n\n val deqOK = (state === s_flush || nextStartPos <= offset)\n\n reqq.io.deq.ready := state === s_req\n calc.io.result.ready := state === s_wait\n\n io.stream.out.valid := buffer.io.deq.valid && deqOK\n buffer.io.deq.ready := io.stream.out.ready && deqOK\n io.stream.out.bits := buffer.io.deq.bits\n io.stream.out.bits.data := outData\n}\n\nclass ChecksumTest extends UnitTest {\n val offset = 6\n val init = 0x4315\n val start = 2\n val data = Seq(0xdead, 0xbeef, 0x7432, 0x0000, 0xf00d, 0x3163, 0x9821, 0x1543)\n val take = Seq(true, true, true, true, true, true, true, false)\n", "right_context": "\n var csum = init + data.zip(take).drop(start/2)\n .filter(_._2).map(_._1).reduce(_ + _)\n while (csum > 0xffff) {\n csum = (csum >> 16) + (csum & 0xffff)\n }\n csum = ~csum & 0xffff\n\n val expected = data.take(offset/2) ++\n Seq(csum) ++ data.drop(offset/2+1)\n\n def seqToVec(seq: Seq[Int], step: Int, nbits: Int) = {\n VecInit((0 until seq.length by step).map { i =>\n Cat((i until (i + step)).map(seq(_).U(nbits.W)).reverse)\n })\n }\n\n val dataBits = 32\n val dataBytes = dataBits / 8\n val shortsPerFlit = dataBits / 16\n val dataVec = seqToVec(data, shortsPerFlit, 16)\n val expectedVec = seqToVec(expected, shortsPerFlit, 16)\n val keepVec = seqToVec(keep, shortsPerFlit, 2)\n\n val s_start :: s_req :: s_input :: s_output :: s_done :: Nil = Enum(5)\n val state = RegInit(s_start)\n\n val rewriter = Module(new ChecksumRewrite(\n dataBits, data.length/shortsPerFlit))\n\n val (inIdx, inDone) = Counter(rewriter.io.stream.in.fire, dataVec.length)\n val (outIdx, outDone) = Counter(rewriter.io.stream.out.fire, expectedVec.length)\n\n rewriter.io.req.valid := state === s_req\n rewriter.io.req.bits.check := true.B\n rewriter.io.req.bits.start := start.U\n rewriter.io.req.bits.init := init.U\n rewriter.io.req.bits.offset := offset.U\n rewriter.io.stream.in.valid := state === s_input\n rewriter.io.stream.in.bits.data := dataVec(inIdx)\n rewriter.io.stream.in.bits.keep := keepVec(inIdx)\n rewriter.io.stream.in.bits.last := inIdx === (dataVec.length-1).U\n rewriter.io.stream.out.ready := state === s_output\n io.finished := state === s_done\n\n when (state === s_start && io.start) { state := s_req }\n when (rewriter.io.req.fire) { state := s_input }\n when (inDone) { state := s_output }\n when (outDone) { state := s_done }\n\n assert(!rewriter.io.stream.out.valid ||\n rewriter.io.stream.out.bits.data === expectedVec(outIdx),\n \"ChecksumTest: got wrong data\")\n\n assert(!rewriter.io.stream.out.valid ||\n rewriter.io.stream.out.bits.keep === keepVec(outIdx),\n \"ChecksumTest: got wrong keep\")\n}\n\nclass TCPChecksumOffloadResult extends Bundle {\n val correct = Bool()\n val checked = Bool()\n}\n\nclass TCPChecksumOffload(dataBits: Int) extends Module {\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new StreamChannel(dataBits)))\n val result = Decoupled(new TCPChecksumOffloadResult)\n })\n\n class FullHeader extends Bundle {\n val tcp = new TCPHeader\n val ipv4 = new IPv4Header\n val eth = new EthernetHeader\n }\n class PseudoHeader extends Bundle {\n val tcp = new TCPHeader\n val length = UInt(16.W)\n val protocol = UInt(8.W)\n val zeros = UInt(8.W)\n val dest_ip = UInt(32.W)\n val source_ip = UInt(32.W)\n }\n\n val dataBytes = dataBits/8\n\n val headerBytes = ETH_HEAD_BYTES + IPV4_HEAD_BYTES + TCP_HEAD_BYTES\n val headerWords = headerBytes / dataBytes\n val headerVec = Reg(Vec(headerWords, UInt(dataBits.W)))\n val header = headerVec.asTypeOf(new FullHeader)\n val headerIdx = RegInit(0.U(log2Ceil(headerWords).W))\n\n val pseudoHeaderBytes = 12 + TCP_HEAD_BYTES\n val pseudoHeaderWords = pseudoHeaderBytes / dataBytes\n val pseudoHeader = Wire(new PseudoHeader)\n val pseudoHeaderVec = pseudoHeader.asTypeOf(\n Vec(pseudoHeaderWords, UInt(dataBits.W)))\n\n pseudoHeader.tcp := header.tcp\n pseudoHeader.length := htons(ntohs(header.ipv4.total_length) - IPV4_HEAD_BYTES.U)\n pseudoHeader.protocol := header.ipv4.protocol\n pseudoHeader.zeros := 0.U\n pseudoHeader.dest_ip := header.ipv4.dest_ip\n pseudoHeader.source_ip := header.ipv4.source_ip\n\n require(dataBits >= 16)\n require(headerBytes % dataBytes == 0)\n require(pseudoHeaderBytes % dataBytes == 0)\n\n val (s_header_in :: s_csum_req ::\n s_header_csum :: s_body_csum ::\n s_passthru :: s_result :: Nil) = Enum(6)\n val state = RegInit(s_header_in)\n\n val headerOK =\n header.eth.ethType === IPV4_ETHTYPE.U &&\n header.ipv4.protocol === TCP_PROTOCOL.U &&\n header.ipv4.ihl === 5.U\n val headerChannel = Wire(new StreamChannel(dataBits))\n headerChannel.data := pseudoHeaderVec(headerIdx)\n headerChannel.keep := ~0.U(dataBits.W)\n headerChannel.last := false.B\n\n val resultExpected = RegInit(false.B)\n\n val csum = Module(new ChecksumCalc(dataBits))\n\n csum.io.req.valid := state === s_csum_req\n csum.io.req.bits.check := true.B\n csum.io.req.bits.start := 0.U\n csum.io.req.bits.init := 0.U\n\n csum.io.stream.in.valid :=\n (state === s_header_csum) || (state === s_body_csum && io.in.valid)\n csum.io.stream.in.bits := Mux(\n state === s_header_csum, headerChannel, io.in.bits)\n csum.io.stream.out.ready := true.B // just ignore output\n\n io.in.ready := state.isOneOf(s_header_in, s_passthru) ||\n (state === s_body_csum && csum.io.stream.in.ready)\n\n io.result.valid := state === s_result && (!resultExpected || csum.io.result.valid)\n io.result.bits.correct := csum.io.result.bits === 0.U\n io.result.bits.checked := resultExpected\n csum.io.result.ready := state === s_result && resultExpected && io.result.ready\n\n when (io.in.fire) {\n when (io.in.bits.last) {\n state := s_result\n } .elsewhen (state === s_header_in) {\n headerVec(headerIdx) := io.in.bits.data\n headerIdx := headerIdx + 1.U\n when (headerIdx === (headerWords-1).U) {\n resultExpected := headerOK\n state := Mux(headerOK, s_csum_req, s_passthru)\n }\n }\n }\n\n when (csum.io.req.fire) {\n headerIdx := 0.U\n state := s_header_csum\n }\n\n when (state === s_header_csum && csum.io.stream.in.ready) {\n headerIdx := headerIdx + 1.U\n when (headerIdx === (pseudoHeaderWords-1).U) {\n state := s_body_csum\n }\n }\n\n when (io.result.fire) {\n headerIdx := 0.U\n resultExpected := false.B\n state := s_header_in\n }\n}\n\nclass ChecksumTCPVerify extends UnitTest {\n val packets = Seq(\"\"\"00 00 00 12 6d 00 00 03 00 12 6d 00 00 02 08 00\n |45 00 00 3c 45 9b 40 00 40 06 9c fb ac 10 00 02\n |ac 10 00 03 c2 a8 14 51 22 ad 9e d6 00 00 00 00\n |a0 02 72 10 bf 07 00 00 02 04 05 b4 04 02 08 0a\n |43 ec e2 58 00 00 00 00 01 03 03 07 00 00 00 00\"\"\",\n \"\"\"00 00 00 12 6d 00 00 02 00 12 6d 00 00 03 08 06\n |00 01 08 00 06 04 00 02 00 12 6d 00 00 03 ac 10\n |00 03 00 12 6d 00 00 02 ac 10 00 02 00 02 00 00\"\"\")\n val dataBytes = packets.map(packetStr =>\n packetStr.stripMargin.replaceAll(\"\\n\", \" \")\n .split(\" \").map(BigInt(_, 16)))\n val dataWords = VecInit(dataBytes.flatMap(\n bytes => (0 until bytes.length by 8).map(\n i => Cat(bytes.slice(i, i + 8).map(_.U(8.W)).reverse))))\n val dataLast = VecInit(dataBytes.map(_.length / 8).flatMap(\n nWords => Seq.fill(nWords-1)(false.B) :+ true.B))\n\n val expectedResults = VecInit(3.U, 2.U)\n\n val started = RegInit(false.B)\n val inputValid = RegInit(false.B)\n val outputReady = RegInit(false.B)\n val resultReady = RegInit(false.B)\n\n val offload = Module(new TCPChecksumOffload(NET_IF_WIDTH))\n\n val (inIdx, inDone) = Counter(offload.io.in.fire, dataWords.length)\n val (resultIdx, resultDone) = Counter(offload.io.result.fire, expectedResults.length)\n\n offload.io.in.valid := inputValid\n offload.io.in.bits.data := dataWords(inIdx)\n offload.io.in.bits.keep := NET_FULL_KEEP\n offload.io.in.bits.last := dataLast(inIdx)\n offload.io.result.ready := resultReady\n io.finished := started && !inputValid && !resultReady\n\n when (!started && io.start) {\n started := true.B\n inputValid := true.B\n resultReady := true.B\n }\n when (inDone) { inputValid := false.B }\n when (resultDone) { resultReady := false.B }\n\n assert(!offload.io.result.valid ||\n offload.io.result.bits.asUInt === expectedResults(resultIdx),\n \"ChecksumTCPVerify: checksum was not correct\")\n}\n", "groundtruth": " val keep = take.map(if (_) 0x3 else 0x0)\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Loop-based Control", "confidence": 0.75, "category_reason": "Functional iteration"} {"task_id": "icenet", "path": "icenet/src/main/scala/Configs.scala", "left_context": "package icenet\n\nimport chisel3._\nimport freechips.rocketchip.subsystem.BaseSubsystemConfig\nimport org.chipsalliance.cde.config.{Parameters, Config}\nimport freechips.rocketchip.unittest.UnitTests\n\nclass WithIceNetUnitTests extends Config((site, here, up) => {\n case NICKey => Some(NICConfig())\n case UnitTests => (p: Parameters) => {\n Seq(\n Module(new NetworkPacketBufferTest),\n Module(new PauserTest),\n Module(new NetworkTapTest),\n Module(new RateLimiterTest),\n Module(new AlignerTest),\n Module(new ChecksumTest),\n Module(new ChecksumTCPVerify),\n Module(new IceNicSendTestWrapper()(p)),\n Module(new IceNicRecvTestWrapper()(p)),\n Module(new IceNicTestWrapper()(p)),\n Module(new MisalignedTestWrapper()(p)))\n }\n})\n\n", "right_context": "class WithIceNIC(inBufFlits: Int = 1800, usePauser: Boolean = false, ctrlQueueDepth: Int = 64)\n extends Config((site, here, up) => {\n case NICKey => Some(NICConfig(\n inBufFlits = inBufFlits,\n ctrlQueueDepth = ctrlQueueDepth,\n usePauser = usePauser,\n checksumOffload = true))\n})\n\nclass WithNoIceNIC extends Config((site, here, up) => {\n case NICKey => None\n})\n", "groundtruth": "class IceNetUnitTestConfig extends Config(\n new WithIceNetUnitTests ++ new BaseSubsystemConfig)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "icenet", "path": "icenet/src/main/scala/Consts.scala", "left_context": "package icenet\n\nimport chisel3._\n\nobject IceNetConsts {\n val NET_IF_WIDTH = 64\n val NET_IF_BYTES = NET_IF_WIDTH/8\n val NET_LEN_BITS = 16\n\n val NET_IP_ALIGN = 2\n val ETH_HEAD_BYTES = 16\n\n val ETH_STANDARD_MTU = 1500\n val ETH_STANDARD_MAX_BYTES = ETH_STANDARD_MTU + ETH_HEAD_BYTES\n val ETH_STANDARD_MAX_FLITS = (ETH_STANDARD_MAX_BYTES - 1) / NET_IF_BYTES + 1\n\n val ETH_JUMBO_MTU = 9000\n val ETH_JUMBO_MAX_BYTES = ETH_JUMBO_MTU + ETH_HEAD_BYTES\n val ETH_JUMBO_MAX_FLITS = (ETH_JUMBO_MAX_BYTES - 1) / NET_IF_BYTES + 1\n\n val ETH_SUPER_JUMBO_MTU = 64 << 10\n val ETH_SUPER_JUMBO_MAX_BYTES = ETH_SUPER_JUMBO_MTU + ETH_HEAD_BYTES\n val ETH_SUPER_JUMBO_MAX_FLITS = (ETH_SUPER_JUMBO_MAX_BYTES - 1) / NET_IF_BYTES + 1\n\n val ETH_MAC_BITS = 48\n val ETH_TYPE_BITS = 16\n val ETH_PAD_BITS = 16\n\n val IPV4_HEAD_BYTES = 20\n val UDP_HEAD_BYTES = 8\n val TCP_HEAD_BYTES = 20\n\n val RLIMIT_MAX_INC = 256\n val RLIMIT_MAX_PERIOD = 256\n val RLIMIT_MAX_SIZE = 256\n\n", "right_context": " def ETH_BCAST_MAC = ~0.U(ETH_MAC_BITS.W)\n\n val IPV4_ETHTYPE = 0x0008\n val TCP_PROTOCOL = 0x06\n}\n", "groundtruth": " def NET_FULL_KEEP = ~0.U(NET_IF_BYTES.W)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "icenet", "path": "icenet/src/main/scala/DMA.scala", "left_context": "package icenet\n\nimport chisel3._\nimport chisel3.util._\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, IdRange}\nimport freechips.rocketchip.util.DecoupledHelper\nimport freechips.rocketchip.tilelink._\n\nclass StreamReadRequest extends Bundle {\n val address = UInt(48.W)\n val length = UInt(15.W)\n val partial = Bool()\n}\n\nclass StreamReader(nXacts: Int, outFlits: Int, maxBytes: Int)\n (implicit p: Parameters) extends LazyModule {\n\n val core = LazyModule(new StreamReaderCore(nXacts, outFlits, maxBytes))\n val node = core.node\n\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this) {\n val dataBits = core.module.dataBits\n\n val io = IO(new Bundle {\n val req = Flipped(Decoupled(new StreamReadRequest))\n val resp = Decoupled(Bool())\n val out = Decoupled(new StreamChannel(dataBits))\n })\n\n core.module.io.req <> io.req\n io.resp <> core.module.io.resp\n\n val buffer = Module(new ReservationBuffer(nXacts, outFlits, dataBits))\n buffer.io.alloc <> core.module.io.alloc\n buffer.io.in <> core.module.io.out\n\n val aligner = Module(new Aligner(dataBits))\n aligner.io.in <> buffer.io.out\n io.out <> aligner.io.out\n }\n}\n\nclass StreamReaderCore(nXacts: Int, outFlits: Int, maxBytes: Int)\n (implicit p: Parameters) extends LazyModule {\n val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters(\n name = \"stream-reader\", sourceId = IdRange(0, nXacts))))))\n\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this) {\n val (tl, edge) = node.out(0)\n val dataBits = tl.params.dataBits\n val beatBytes = dataBits / 8\n val byteAddrBits = log2Ceil(beatBytes)\n val addrBits = tl.params.addressBits\n val lenBits = 15\n\n require (edge.manager.minLatency > 0)\n\n val io = IO(new Bundle {\n val req = Flipped(Decoupled(new StreamReadRequest))\n val resp = Decoupled(Bool())\n val alloc = Decoupled(new ReservationBufferAlloc(nXacts, outFlits))\n val out = Decoupled(new ReservationBufferData(nXacts, dataBits))\n })\n\n val s_idle :: s_read :: s_resp :: Nil = Enum(3)\n val state = RegInit(s_idle)\n\n // Physical (word) address in memory\n val sendaddr = Reg(UInt(addrBits.W))\n // Number of words to send\n val sendlen = Reg(UInt(lenBits.W))\n // 0 if last packet in sequence, 1 otherwise\n val sendpart = Reg(Bool())\n\n val xactBusy = RegInit(0.U(nXacts.W))\n val xactOnehot = PriorityEncoderOH(~xactBusy)\n val xactId = OHToUInt(xactOnehot)\n val xactLast = Reg(UInt(nXacts.W))\n val xactLeftKeep = Reg(Vec(nXacts, UInt(beatBytes.W)))\n val xactRightKeep = Reg(Vec(nXacts, UInt(beatBytes.W)))\n\n val reqSize = MuxCase(byteAddrBits.U,\n (log2Ceil(maxBytes) until byteAddrBits by -1).map(lgSize =>\n // Use the largest size (beatBytes <= size <= maxBytes)\n // s.t. sendaddr % size == 0 and sendlen > size\n (sendaddr(lgSize-1,0) === 0.U &&\n (sendlen >> lgSize.U) =/= 0.U) -> lgSize.U))\n val isLast = (xactLast >> tl.d.bits.source)(0) && edge.last(tl.d)\n val canSend = state === s_read && !xactBusy.andR\n\n val fullKeep = ~0.U(beatBytes.W)\n val loffset = Reg(UInt(byteAddrBits.W))\n val roffset = Reg(UInt(byteAddrBits.W))\n val lkeep = fullKeep << loffset\n val rkeep = fullKeep >> roffset\n val first = Reg(Bool())\n\n xactBusy := (xactBusy | Mux(tl.a.fire, xactOnehot, 0.U)) &\n ~Mux(tl.d.fire && edge.last(tl.d),\n UIntToOH(tl.d.bits.source), 0.U)\n\n val helper = DecoupledHelper(tl.a.ready, io.alloc.ready)\n\n io.req.ready := state === s_idle\n io.alloc.valid := helper.fire(io.alloc.ready, canSend)\n io.alloc.bits.id := xactId\n io.alloc.bits.count := (1.U << (reqSize - byteAddrBits.U))\n tl.a.valid := helper.fire(tl.a.ready, canSend)\n tl.a.bits := edge.Get(\n fromSource = xactId,\n toAddress = sendaddr,\n lgSize = reqSize)._2\n\n val outLeftKeep = xactLeftKeep(tl.d.bits.source)\n val outRightKeep = xactRightKeep(tl.d.bits.source)\n\n io.out.valid := tl.d.valid\n io.out.bits.id := tl.d.bits.source\n io.out.bits.data.data := tl.d.bits.data\n io.out.bits.data.keep := MuxCase(fullKeep, Seq(\n (edge.first(tl.d) && edge.last(tl.d)) -> (outLeftKeep & outRightKeep),\n edge.first(tl.d) -> outLeftKeep,\n edge.last(tl.d) -> outRightKeep))\n io.out.bits.data.last := isLast\n tl.d.ready := io.out.ready\n io.resp.valid := state === s_resp\n io.resp.bits := true.B\n\n when (io.req.fire) {\n val req = io.req.bits\n val lastaddr = req.address + req.length\n val startword = req.address(addrBits-1, byteAddrBits)\n val endword = lastaddr(addrBits-1, byteAddrBits) +\n Mux(lastaddr(byteAddrBits-1, 0) === 0.U, 0.U, 1.U)\n\n loffset := req.address(byteAddrBits-1, 0)\n roffset := Cat(endword, 0.U(byteAddrBits.W)) - lastaddr\n first := true.B\n\n sendaddr := Cat(startword, 0.U(byteAddrBits.W))\n sendlen := Cat(endword - startword, 0.U(byteAddrBits.W))\n sendpart := req.partial\n state := s_read\n\n assert(req.length > 0.U, \"request length must be >0\")\n }\n\n when (tl.a.fire) {\n val reqBytes = 1.U << reqSize\n sendaddr := sendaddr + reqBytes\n sendlen := sendlen - reqBytes\n when (sendlen === reqBytes) {\n xactLast := (xactLast & ~xactOnehot) | Mux(sendpart, 0.U, xactOnehot)\n xactRightKeep(xactId) := rkeep\n state := s_resp\n } .otherwise {\n xactLast := xactLast & ~xactOnehot\n xactRightKeep(xactId) := fullKeep\n }\n when (first) {\n first := false.B\n xactLeftKeep(xactId) := lkeep\n } .otherwise {\n xactLeftKeep(xactId) := fullKeep\n }\n }\n\n when (io.resp.fire) {\n state := s_idle\n }\n }\n}\n\nclass StreamWriteRequest extends Bundle {\n val address = UInt(48.W)\n val length = UInt(16.W)\n}\n\nclass StreamWriter(nXacts: Int, maxBytes: Int)\n (implicit p: Parameters) extends LazyModule {\n val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters(\n name = \"stream-writer\", sourceId = IdRange(0, nXacts))))))\n\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this) {\n val (tl, edge) = node.out(0)\n val dataBits = tl.params.dataBits\n val beatBytes = dataBits / 8\n val byteAddrBits = log2Ceil(beatBytes)\n val addrBits = tl.params.addressBits\n val lenBits = 16\n\n require (edge.manager.minLatency > 0)\n\n val io = IO(new Bundle {\n val req = Flipped(Decoupled(new StreamWriteRequest))\n val resp = Decoupled(UInt(lenBits.W))\n val in = Flipped(Decoupled(new StreamChannel(dataBits)))\n })\n\n val s_idle :: s_data :: s_resp :: Nil = Enum(3)\n val state = RegInit(s_idle)\n\n val length = Reg(UInt(lenBits.W))\n val baseAddr = Reg(UInt(addrBits.W))\n val offset = Reg(UInt(addrBits.W))\n val addrMerged = baseAddr + offset\n val bytesToSend = length - offset\n val baseByteOff = baseAddr(byteAddrBits-1, 0)\n val byteOff = addrMerged(byteAddrBits-1, 0)\n val extraBytes = Mux(baseByteOff === 0.U, 0.U, beatBytes.U - baseByteOff)\n\n val xactBusy = RegInit(0.U(nXacts.W))\n val xactOnehot = PriorityEncoderOH(~xactBusy)\n val xactId = OHToUInt(xactOnehot)\n\n val maxBeats = maxBytes / beatBytes\n val beatIdBits = log2Ceil(maxBeats)\n\n val beatsLeft = Reg(UInt(beatIdBits.W))\n val headAddr = Reg(UInt(addrBits.W))\n val headXact = Reg(UInt(log2Ceil(nXacts).W))\n val headSize = Reg(UInt(log2Ceil(maxBytes + 1).W))\n\n val newBlock = beatsLeft === 0.U\n val canSend = !xactBusy.andR || !newBlock\n\n val reqSize = MuxCase(0.U,\n (log2Ceil(maxBytes) until 0 by -1).map(lgSize =>\n (addrMerged(lgSize-1,0) === 0.U &&\n (bytesToSend >> lgSize.U) =/= 0.U) -> lgSize.U))\n\n xactBusy := (xactBusy | Mux(tl.a.fire && newBlock, xactOnehot, 0.U)) &\n ~Mux(tl.d.fire, UIntToOH(tl.d.bits.source), 0.U)\n\n val overhang = RegInit(0.U(dataBits.W))\n val sendTrail = bytesToSend <= extraBytes\n val fulldata = (overhang | (io.in.bits.data << Cat(baseByteOff, 0.U(3.W))))\n\n val fromSource = Mux(newBlock, xactId, headXact)\n val toAddress = Mux(newBlock, addrMerged, headAddr)\n val lgSize = Mux(newBlock, reqSize, headSize)\n val wdata = fulldata(dataBits-1, 0)\n val wmask = Cat((0 until beatBytes).map(\n i => (i.U >= byteOff) && (i.U < bytesToSend)).reverse)\n val wpartial = !wmask.andR\n\n val putPartial = edge.Put(\n fromSource = xactId,\n toAddress = addrMerged & ~(beatBytes-1).U(addrBits.W),\n lgSize = log2Ceil(beatBytes).U,\n data = Mux(sendTrail, overhang, wdata),\n mask = wmask)._2\n\n val putFull = edge.Put(\n fromSource = fromSource,\n toAddress = toAddress,\n lgSize = lgSize,\n data = wdata)._2\n\n io.req.ready := state === s_idle\n tl.a.valid := (state === s_data) && (io.in.valid || sendTrail) && canSend\n tl.a.bits := Mux(wpartial, putPartial, putFull)\n tl.d.ready := xactBusy.orR\n io.in.ready := state === s_data && canSend && !sendTrail && tl.a.ready\n io.resp.valid := state === s_resp && !xactBusy.orR\n io.resp.bits := length\n\n when (io.req.fire) {\n offset := 0.U\n baseAddr := io.req.bits.address\n length := io.req.bits.length\n beatsLeft := 0.U\n state := s_data\n }\n\n when (tl.a.fire) {\n when (!newBlock) {\n beatsLeft := beatsLeft - 1.U\n } .elsewhen (reqSize > byteAddrBits.U) {\n val nBeats = 1.U << (reqSize - byteAddrBits.U)\n beatsLeft := nBeats - 1.U\n headAddr := addrMerged\n headXact := xactId\n headSize := reqSize\n }\n\n val bytesSent = PopCount(wmask)\n offset := offset + bytesSent\n overhang := fulldata >> dataBits.U\n\n when (bytesSent === bytesToSend) { state := s_resp }\n }\n\n", "right_context": " }\n}\n", "groundtruth": " when (io.resp.fire) { state := s_idle }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "icenet", "path": "icenet/src/main/scala/Headers.scala", "left_context": "package icenet\n\nimport chisel3._\nimport chisel3.util._\nimport IceNetConsts._\n\nobject NetworkHelpers {\n def reverse_bytes(a: UInt, n: Int) = {\n val bytes = (0 until n).map(i => a((i + 1) * 8 - 1, i * 8))\n Cat(bytes)\n }\n", "right_context": " def ntohl(a: UInt) = reverse_bytes(a, 4)\n def htons(a: UInt) = reverse_bytes(a, 2)\n def ntohs(a: UInt) = reverse_bytes(a, 2)\n}\n\nclass EthernetHeader extends Bundle {\n val ethType = UInt(ETH_TYPE_BITS.W)\n val srcmac = UInt(ETH_MAC_BITS.W)\n val dstmac = UInt(ETH_MAC_BITS.W)\n val padding = UInt(ETH_PAD_BITS.W)\n\n def toWords(w: Int = NET_IF_WIDTH) =\n this.asTypeOf(Vec(ETH_HEAD_BYTES * 8 / w, UInt(w.W)))\n}\n\nobject EthernetHeader {\n def apply(dstmac: UInt, srcmac: UInt, ethType: UInt) = {\n val header = Wire(new EthernetHeader)\n header.dstmac := dstmac\n header.srcmac := srcmac\n header.ethType := ethType\n header.padding := DontCare\n header\n }\n\n def apply(words: Seq[UInt], w: Int = NET_IF_WIDTH) = {\n val headerWords = ETH_HEAD_BYTES * 8 / w\n Cat(words.take(headerWords).reverse).asTypeOf(new EthernetHeader)\n }\n}\n\nclass IPv4Header extends Bundle {\n val dest_ip = UInt(32.W)\n val source_ip = UInt(32.W)\n val header_checksum = UInt(16.W)\n val protocol = UInt(8.W)\n val ttl = UInt(8.W)\n val frag_off2 = UInt(8.W)\n val flags = UInt(3.W)\n val frag_off1 = UInt(5.W)\n val ident = UInt(16.W)\n val total_length = UInt(16.W)\n val dcsp = UInt(6.W)\n val ecn = UInt(2.W)\n val version = UInt(4.W)\n val ihl = UInt(4.W)\n}\n\nclass UDPHeader extends Bundle {\n val checksum = UInt(16.W)\n val length = UInt(16.W)\n val dest_port = UInt(16.W)\n val source_port = UInt(16.W)\n}\n\nclass TCPHeader extends Bundle {\n val urgent_pointer = UInt(16.W)\n val checksum = UInt(16.W)\n val window_size = UInt(16.W)\n val cwr = Bool()\n val ece = Bool()\n val urg = Bool()\n val ack = Bool()\n val psh = Bool()\n val rst = Bool()\n val syn = Bool()\n val fin = Bool()\n val data_offset = UInt(4.W)\n val reserved = UInt(3.W)\n val ns = Bool()\n val acknum = UInt(32.W)\n val seqnum = UInt(32.W)\n val dest_port = UInt(16.W)\n val source_port = UInt(16.W)\n}\n", "groundtruth": " def htonl(a: UInt) = reverse_bytes(a, 4)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "icenet", "path": "icenet/src/main/scala/Limiter.scala", "left_context": "package icenet\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.unittest.UnitTest\nimport IceNetConsts._\n\nclass RateLimiterSettings extends Bundle {\n val incBits = log2Ceil(RLIMIT_MAX_INC)\n val periodBits = log2Ceil(RLIMIT_MAX_PERIOD)\n val sizeBits = log2Ceil(RLIMIT_MAX_SIZE)\n\n /*\n * Given a clock frequency of X, you can achieve an output bandwidth\n * of Y = X * (N / D), where N <= D, by setting inc to N and period to (D - 1).\n * The field size should be set to the number of consecutive beats that\n * can be sent before rate-limiting kicks in.\n */\n val inc = UInt(incBits.W)\n val period = UInt(periodBits.W)\n val size = UInt(sizeBits.W)\n}\n\nclass RateLimiter[T <: Data](typ: T) extends Module {\n val incBits = log2Ceil(RLIMIT_MAX_INC)\n val periodBits = log2Ceil(RLIMIT_MAX_PERIOD)\n val sizeBits = log2Ceil(RLIMIT_MAX_SIZE)\n\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(typ))\n val out = Decoupled(typ)\n val settings = Input(new RateLimiterSettings)\n })\n\n val tokens = RegInit(0.U(sizeBits.W))\n val counter = RegInit(0.U(periodBits.W))\n\n when (counter === 0.U) {\n counter := io.settings.period\n } .otherwise {\n counter := counter - 1.U\n }\n\n val inc_trigger = counter === 0.U\n val ok_to_send = tokens > 0.U\n\n io.in.ready := io.out.ready && ok_to_send\n io.out.valid := io.in.valid && ok_to_send\n io.out.bits := io.in.bits\n\n def uint_min(a: UInt, b: UInt) = Mux(a < b, a, b)\n\n when (inc_trigger && io.out.fire) {\n val next_tokens = tokens +& (io.settings.inc - 1.U)\n tokens := uint_min(next_tokens, io.settings.size)\n } .elsewhen (inc_trigger) {\n val next_tokens = tokens +& io.settings.inc\n tokens := uint_min(next_tokens, io.settings.size)\n } .elsewhen (io.out.fire) {\n tokens := tokens - 1.U\n }\n}\n\nobject RateLimiter {\n def apply[T <: Data](in: DecoupledIO[T], inc: Int, period: Int, size: Int) = {\n if (period > 1) {\n val limiter = Module(new RateLimiter(in.bits.cloneType))\n limiter.io.in <> in\n limiter.io.settings.inc := inc.U\n limiter.io.settings.period := (period - 1).U\n limiter.io.settings.size := size.U\n limiter.io.out\n", "right_context": " }\n}\n\nclass RateLimiterTest extends UnitTest {\n val nFlits = 48\n val started = RegInit(false.B)\n val sending = RegInit(false.B)\n val receiving = RegInit(false.B)\n\n val limiter = Module(new RateLimiter(Bool()))\n limiter.io.in.valid := sending\n limiter.io.in.bits := true.B\n limiter.io.out.ready := receiving\n limiter.io.settings.inc := 1.U\n limiter.io.settings.period := 3.U\n limiter.io.settings.size := 2.U\n\n val (sendCount, sendDone) = Counter(limiter.io.in.fire, nFlits)\n val (recvCount, recvDone) = Counter(limiter.io.out.fire, nFlits)\n\n when (io.start && !started) {\n started := true.B\n sending := true.B\n receiving := true.B\n }\n\n when (sendDone) { sending := false.B }\n when (recvDone) { receiving := false.B }\n\n io.finished := started && !sending && !receiving\n}\n", "groundtruth": " } else { in }\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "icenet", "path": "icenet/src/main/scala/NIC.scala", "left_context": "package icenet\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.reflect.DataMirror\nimport freechips.rocketchip.subsystem.{BaseSubsystem, TLBusWrapperLocation, PBUS, FBUS}\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.prci._\nimport freechips.rocketchip.regmapper._\nimport freechips.rocketchip.interrupts._\nimport freechips.rocketchip.tilelink._\nimport freechips.rocketchip.util._\nimport IceNetConsts._\n\n// This is copied from testchipip to avoid dependencies\nclass ClockedIO[T <: Data](private val gen: T) extends Bundle {\n val clock = Output(Clock())\n val bits = DataMirror.internal.chiselTypeClone[T](gen)\n}\n\n/**\n * @inBufFlits How many flits in the input buffer(s)\n * @outBufFlits Number of flits in the output buffer\n * @nMemXacts Maximum number of transactions that the send/receive path can send to memory\n * @maxAcquireBytes Cache block size\n * @ctrlQueueDepth Depth of the MMIO control queues\n * @usePauser Hardware support for Ethernet pause frames\n * @checksumOffload TCP checksum offload engine\n * @packetMaxBytes Maximum number of bytes in a packet (header size + MTU)\n */\ncase class NICConfig(\n inBufFlits: Int = 2 * ETH_STANDARD_MAX_BYTES / NET_IF_BYTES,\n outBufFlits: Int = 2 * ETH_STANDARD_MAX_BYTES / NET_IF_BYTES,\n nMemXacts: Int = 8,\n maxAcquireBytes: Int = 64,\n ctrlQueueDepth: Int = 10,\n usePauser: Boolean = false,\n checksumOffload: Boolean = false,\n packetMaxBytes: Int = ETH_STANDARD_MAX_BYTES)\n\ncase class NICAttachParams(\n masterWhere: TLBusWrapperLocation = FBUS,\n slaveWhere: TLBusWrapperLocation = PBUS\n)\n\ncase object NICKey extends Field[Option[NICConfig]](None)\ncase object NICAttachKey extends Field[NICAttachParams](NICAttachParams())\n\ntrait HasNICParameters {\n implicit val p: Parameters\n val nicExternal = p(NICKey).get\n val inBufFlits = nicExternal.inBufFlits\n val outBufFlits = nicExternal.outBufFlits\n val nMemXacts = nicExternal.nMemXacts\n val maxAcquireBytes = nicExternal.maxAcquireBytes\n val ctrlQueueDepth = nicExternal.ctrlQueueDepth\n val usePauser = nicExternal.usePauser\n val checksumOffload = nicExternal.checksumOffload\n val packetMaxBytes = nicExternal.packetMaxBytes\n}\n\nabstract class NICLazyModule(implicit p: Parameters)\n extends LazyModule with HasNICParameters\n\nabstract class NICModule(implicit val p: Parameters)\n extends Module with HasNICParameters\n\nabstract class NICBundle(implicit val p: Parameters)\n extends Bundle with HasNICParameters\n\nclass PacketArbiter(arbN: Int, rr: Boolean = false)\n extends HellaPeekingArbiter(\n new StreamChannel(NET_IF_WIDTH), arbN,\n (ch: StreamChannel) => ch.last, rr = rr)\n\nclass IceNicSendIO extends Bundle {\n val req = Decoupled(UInt(NET_IF_WIDTH.W))\n val comp = Flipped(Decoupled(Bool()))\n}\n\nclass IceNicRecvIO extends Bundle {\n val req = Decoupled(UInt(NET_IF_WIDTH.W))\n val comp = Flipped(Decoupled(UInt(NET_LEN_BITS.W)))\n}\n\ntrait IceNicControllerBundle extends Bundle {\n val send = new IceNicSendIO\n val recv = new IceNicRecvIO\n val macAddr = Input(UInt(ETH_MAC_BITS.W))\n val txcsumReq = Decoupled(new ChecksumRewriteRequest)\n val rxcsumRes = Flipped(Decoupled(new TCPChecksumOffloadResult))\n val csumEnable = Output(Bool())\n}\n\ncase class IceNicControllerParams(address: BigInt, beatBytes: Int)\n\n/*\n * Take commands from the CPU over TL2, expose as Queues\n */\nclass IceNicController(c: IceNicControllerParams)(implicit p: Parameters)\n extends RegisterRouter(RegisterRouterParams(\"ice-nic\", Seq(\"ucb-bar,ice-nic\"),\n c.address, beatBytes=c.beatBytes))\n with HasTLControlRegMap\n with HasInterruptSources\n with HasNICParameters {\n override def nInterrupts = 2\n def tlRegmap(mapping: RegField.Map*): Unit = regmap(mapping:_*)\n override lazy val module = new IceNiCControllerModuleImp(this)\n}\n\nclass IceNiCControllerModuleImp(outer: IceNicController)(implicit p: Parameters) extends LazyModuleImp(outer) with HasNICParameters {\n val io = IO(new Bundle with IceNicControllerBundle)\n\n val sendCompDown = WireInit(false.B)\n\n val qDepth = ctrlQueueDepth\n require(qDepth < (1 << 8))\n\n def queueCount[T <: Data](qio: QueueIO[T], depth: Int): UInt =\n TwoWayCounter(qio.enq.fire, qio.deq.fire, depth)\n\n // hold (len, addr) of packets that we need to send out\n val sendReqQueue = Module(new HellaQueue(qDepth)(UInt(NET_IF_WIDTH.W)))\n val sendReqCount = queueCount(sendReqQueue.io, qDepth)\n // hold addr of buffers we can write received packets into\n val recvReqQueue = Module(new HellaQueue(qDepth)(UInt(NET_IF_WIDTH.W)))\n val recvReqCount = queueCount(recvReqQueue.io, qDepth)\n // count number of sends completed\n val sendCompCount = TwoWayCounter(io.send.comp.fire, sendCompDown, qDepth)\n // hold length of received packets\n val recvCompQueue = Module(new HellaQueue(qDepth)(UInt(NET_LEN_BITS.W)))\n val recvCompCount = queueCount(recvCompQueue.io, qDepth)\n\n val sendCompValid = sendCompCount > 0.U\n val intMask = RegInit(0.U(2.W))\n\n io.send.req <> sendReqQueue.io.deq\n io.recv.req <> recvReqQueue.io.deq\n io.send.comp.ready := sendCompCount < qDepth.U\n recvCompQueue.io.enq <> io.recv.comp\n\n outer.interrupts(0) := sendCompValid && intMask(0)\n outer.interrupts(1) := recvCompQueue.io.deq.valid && intMask(1)\n\n val sendReqSpace = (qDepth.U - sendReqCount)\n val recvReqSpace = (qDepth.U - recvReqCount)\n\n def sendCompRead = (ready: Bool) => {\n sendCompDown := sendCompValid && ready\n (sendCompValid, true.B)\n }\n\n val txcsumReqQueue = Module(new HellaQueue(qDepth)(UInt(49.W)))\n val rxcsumResQueue = Module(new HellaQueue(qDepth)(UInt(2.W)))\n val csumEnable = RegInit(false.B)\n\n io.txcsumReq.valid := txcsumReqQueue.io.deq.valid\n io.txcsumReq.bits := txcsumReqQueue.io.deq.bits.asTypeOf(new ChecksumRewriteRequest)\n txcsumReqQueue.io.deq.ready := io.txcsumReq.ready\n\n rxcsumResQueue.io.enq.valid := io.rxcsumRes.valid\n rxcsumResQueue.io.enq.bits := io.rxcsumRes.bits.asUInt\n io.rxcsumRes.ready := rxcsumResQueue.io.enq.ready\n\n io.csumEnable := csumEnable\n\n outer.tlRegmap(\n 0x00 -> Seq(RegField.w(NET_IF_WIDTH, sendReqQueue.io.enq)),\n 0x08 -> Seq(RegField.w(NET_IF_WIDTH, recvReqQueue.io.enq)),\n 0x10 -> Seq(RegField.r(1, sendCompRead)),\n 0x12 -> Seq(RegField.r(NET_LEN_BITS, recvCompQueue.io.deq)),\n 0x14 -> Seq(\n RegField.r(8, sendReqSpace),\n RegField.r(8, recvReqSpace),\n RegField.r(8, sendCompCount),\n RegField.r(8, recvCompCount)),\n 0x18 -> Seq(RegField.r(ETH_MAC_BITS, io.macAddr)),\n 0x20 -> Seq(RegField(2, intMask)),\n 0x28 -> Seq(RegField.w(49, txcsumReqQueue.io.enq)),\n 0x30 -> Seq(RegField.r(2, rxcsumResQueue.io.deq)),\n 0x31 -> Seq(RegField(1, csumEnable)))\n}\n\nclass IceNicSendPath(nInputTaps: Int = 0)(implicit p: Parameters)\n extends NICLazyModule {\n val reader = LazyModule(new StreamReader(\n nMemXacts, outBufFlits, maxAcquireBytes))\n val node = reader.node\n\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this) {\n val io = IO(new Bundle {\n val send = Flipped(new IceNicSendIO)\n val tap = Flipped(Vec(nInputTaps, Decoupled(new StreamChannel(NET_IF_WIDTH))))\n val out = Decoupled(new StreamChannel(NET_IF_WIDTH))\n val rlimit = Input(new RateLimiterSettings)\n val csum = checksumOffload.option(new Bundle {\n val req = Flipped(Decoupled(new ChecksumRewriteRequest))\n val enable = Input(Bool())\n })\n })\n\n val readreq = reader.module.io.req\n io.send.req.ready := readreq.ready\n readreq.valid := io.send.req.valid\n readreq.bits.address := io.send.req.bits(47, 0)\n readreq.bits.length := io.send.req.bits(62, 48)\n readreq.bits.partial := io.send.req.bits(63)\n io.send.comp <> reader.module.io.resp\n\n val preArbOut = if (checksumOffload) {\n val readerOut = reader.module.io.out\n val arb = Module(new PacketArbiter(2))\n val bufFlits = (packetMaxBytes - 1) / NET_IF_BYTES + 1\n val rewriter = Module(new ChecksumRewrite(NET_IF_WIDTH, bufFlits))\n val enable = io.csum.get.enable\n\n rewriter.io.req <> io.csum.get.req\n\n arb.io.in(0) <> rewriter.io.stream.out\n arb.io.in(1).valid := !enable && readerOut.valid\n arb.io.in(1).bits := readerOut.bits\n rewriter.io.stream.in.valid := enable && readerOut.valid\n rewriter.io.stream.in.bits := readerOut.bits\n readerOut.ready := Mux(enable,\n rewriter.io.stream.in.ready, arb.io.in(1).ready)\n\n arb.io.out\n } else { reader.module.io.out }\n\n val unlimitedOut = if (nInputTaps > 0) {\n val bufWords = (packetMaxBytes - 1) / NET_IF_BYTES + 1\n val inputs = (preArbOut +: io.tap).map { in =>\n // The packet collection buffer doesn't allow sending the first flit\n // of a packet until the last flit is received.\n // This ensures that we don't lock the arbiter while waiting for data\n // to arrive, which could cause deadocks.\n val buffer = Module(new PacketCollectionBuffer(bufWords))\n buffer.io.in <> in\n buffer.io.out\n }\n val arb = Module(new PacketArbiter(inputs.size, rr = true))\n arb.io.in <> inputs\n arb.io.out\n } else { preArbOut }\n\n val limiter = Module(new RateLimiter(new StreamChannel(NET_IF_WIDTH)))\n limiter.io.in <> unlimitedOut\n limiter.io.settings := io.rlimit\n io.out <> limiter.io.out\n }\n}\n\nclass IceNicWriter(implicit p: Parameters) extends NICLazyModule {\n val writer = LazyModule(new StreamWriter(nMemXacts, maxAcquireBytes))\n val node = writer.node\n\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this) {\n val io = IO(new Bundle {\n val recv = Flipped(new IceNicRecvIO)\n val in = Flipped(Decoupled(new StreamChannel(NET_IF_WIDTH)))\n val length = Flipped(Valid(UInt(NET_LEN_BITS.W)))\n })\n\n val streaming = RegInit(false.B)\n val byteAddrBits = log2Ceil(NET_IF_BYTES)\n val helper = DecoupledHelper(\n io.recv.req.valid,\n writer.module.io.req.ready,\n io.length.valid, !streaming)\n\n writer.module.io.req.valid := helper.fire(writer.module.io.req.ready)\n writer.module.io.req.bits.address := io.recv.req.bits\n writer.module.io.req.bits.length := io.length.bits\n io.recv.req.ready := helper.fire(io.recv.req.valid)\n\n writer.module.io.in.valid := io.in.valid && streaming\n writer.module.io.in.bits := io.in.bits\n io.in.ready := writer.module.io.in.ready && streaming\n\n io.recv.comp <> writer.module.io.resp\n\n when (io.recv.req.fire) { streaming := true.B }\n when (io.in.fire && io.in.bits.last) { streaming := false.B }\n }\n}\n\n/*\n * Recv frames\n */\nclass IceNicRecvPath(val tapFuncs: Seq[EthernetHeader => Bool] = Nil)\n (implicit p: Parameters) extends LazyModule {\n val writer = LazyModule(new IceNicWriter)\n val node = TLIdentityNode()\n node := writer.node\n lazy val module = new IceNicRecvPathModule(this)\n}\n\nclass IceNicRecvPathModule(val outer: IceNicRecvPath)\n extends LazyModuleImp(outer) with HasNICParameters {\n val io = IO(new Bundle {\n val recv = Flipped(new IceNicRecvIO)\n val in = Flipped(Decoupled(new StreamChannel(NET_IF_WIDTH))) // input stream\n val tap = Vec(outer.tapFuncs.length, Decoupled(new StreamChannel(NET_IF_WIDTH)))\n val csum = checksumOffload.option(new Bundle {\n val res = Decoupled(new TCPChecksumOffloadResult)\n val enable = Input(Bool())\n })\n val buf_free = Output(Vec(1 + outer.tapFuncs.length, UInt(8.W)))\n })\n\n def tapOutToDropCheck(tapOut: EthernetHeader => Bool) = {\n (header: EthernetHeader, ch: StreamChannel, update: Bool) => {\n val first = RegInit(true.B)\n val drop = tapOut(header) && first\n val dropReg = RegInit(false.B)\n\n when (update && first) { first := false.B; dropReg := drop }\n when (update && ch.last) { first := true.B; dropReg := false.B }\n\n drop || dropReg\n }\n }\n\n def duplicateStream(in: DecoupledIO[StreamChannel], outs: Seq[DecoupledIO[StreamChannel]]) = {\n outs.foreach { out =>\n out.valid := in.valid\n out.bits := in.bits\n }\n in.ready := outs.head.ready\n val outReadys = Cat(outs.map(_.ready))\n assert(outReadys.andR || !outReadys.orR,\n \"Duplicated streams must all be ready simultaneously\")\n outs\n }\n\n def invertCheck(check: (EthernetHeader, StreamChannel, Bool) => Bool) =\n (eth: EthernetHeader, ch: StreamChannel, up: Bool) => !check(eth, ch, up)\n\n val tapDropChecks = outer.tapFuncs.map(func => tapOutToDropCheck(func))\n", "right_context": " val allDropChecks =\n // Drop checks for the primary buffer\n // Drop if the packet should be tapped out or is a pause frame\n Seq(tapDropChecks ++ pauseDropCheck.toSeq) ++\n // Drop checks for the tap buffers\n // For each tap, drop if the packet doesn't match the tap function or is a pause frame\n tapDropChecks.map(check => invertCheck(check) +: pauseDropCheck.toSeq)\n\n val buffers = allDropChecks.map(dropChecks =>\n Module(new NetworkPacketBuffer(\n inBufFlits,\n maxBytes = packetMaxBytes,\n dropChecks = dropChecks, dropless = usePauser)))\n duplicateStream(io.in, buffers.map(_.io.stream.in))\n\n io.buf_free := buffers.map(_.io.free)\n\n io.tap <> buffers.tail.map(_.io.stream.out)\n val bufout = buffers.head.io.stream.out\n val buflen = buffers.head.io.length\n\n val (csumout, recvreq) = (if (checksumOffload) {\n val offload = Module(new TCPChecksumOffload(NET_IF_WIDTH))\n val offloadReady = offload.io.in.ready || !io.csum.get.enable\n\n val out = Wire(Decoupled(new StreamChannel(NET_IF_WIDTH)))\n val recvreq = Wire(Decoupled(UInt(NET_IF_WIDTH.W)))\n val reqq = Module(new Queue(UInt(NET_IF_WIDTH.W), 1))\n\n val enqHelper = DecoupledHelper(\n io.recv.req.valid, reqq.io.enq.ready, recvreq.ready)\n val deqHelper = DecoupledHelper(\n bufout.valid, offloadReady, out.ready, reqq.io.deq.valid)\n\n reqq.io.enq.valid := enqHelper.fire(reqq.io.enq.ready)\n reqq.io.enq.bits := io.recv.req.bits\n io.recv.req.ready := enqHelper.fire(io.recv.req.valid)\n recvreq.valid := enqHelper.fire(recvreq.ready)\n recvreq.bits := io.recv.req.bits\n\n out.valid := deqHelper.fire(out.ready)\n out.bits := bufout.bits\n offload.io.in.valid := deqHelper.fire(offloadReady, io.csum.get.enable)\n offload.io.in.bits := bufout.bits\n bufout.ready := deqHelper.fire(bufout.valid)\n reqq.io.deq.ready := deqHelper.fire(reqq.io.deq.valid, bufout.bits.last)\n\n io.csum.get.res <> offload.io.result\n\n (out, recvreq)\n } else { (bufout, io.recv.req) })\n\n val writer = outer.writer.module\n writer.io.recv.req <> Queue(recvreq, 1)\n io.recv.comp <> writer.io.recv.comp\n writer.io.in <> csumout\n writer.io.length.valid := buflen.valid\n writer.io.length.bits := buflen.bits\n}\n\nclass NICIO extends StreamIO(NET_IF_WIDTH) {\n val macAddr = Input(UInt(ETH_MAC_BITS.W))\n val rlimit = Input(new RateLimiterSettings)\n val pauser = Input(new PauserSettings)\n\n}\n\n/*\n * A simple NIC\n *\n * Expects ethernet frames (see below), but uses a custom transport\n * (see ExtBundle)\n *\n * Ethernet Frame format:\n * 2 bytes | 6 bytes | 6 bytes | 2 bytes | 46-1500B\n * Padding | Dest Addr | Source Addr | Type/Len | Data\n *\n * @address Starting address of MMIO control registers\n * @beatBytes Width of memory interface (in bytes)\n * @tapOutFuncs Sequence of functions for each output tap.\n * Each function takes the header of an Ethernet frame\n * and returns Bool that is true if matching and false if not.\n * @nInputTaps Number of input taps\n *\n */\nclass IceNIC(address: BigInt, beatBytes: Int = 8,\n tapOutFuncs: Seq[EthernetHeader => Bool] = Nil,\n nInputTaps: Int = 0)\n (implicit p: Parameters) extends NICLazyModule {\n\n val control = LazyModule(new IceNicController(\n IceNicControllerParams(address, beatBytes)))\n val sendPath = LazyModule(new IceNicSendPath(nInputTaps))\n val recvPath = LazyModule(new IceNicRecvPath(tapOutFuncs))\n\n val mmionode = TLIdentityNode()\n val dmanode = TLIdentityNode()\n val intnode = control.intXing(NoCrossing)\n\n control.node := TLAtomicAutomata() := mmionode\n dmanode := TLWidthWidget(NET_IF_BYTES) := sendPath.node\n dmanode := TLWidthWidget(NET_IF_BYTES) := recvPath.node\n\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this) {\n val io = IO(new Bundle {\n val ext = new NICIO\n val tapOut = Vec(tapOutFuncs.length, Decoupled(new StreamChannel(NET_IF_WIDTH)))\n val tapIn = Flipped(Vec(nInputTaps, Decoupled(new StreamChannel(NET_IF_WIDTH))))\n })\n\n sendPath.module.io.send <> control.module.io.send\n recvPath.module.io.recv <> control.module.io.recv\n\n // connect externally\n if (usePauser) {\n val pauser = Module(new Pauser(inBufFlits, 1 + tapOutFuncs.length))\n pauser.io.int.out <> sendPath.module.io.out\n recvPath.module.io.in <> pauser.io.int.in\n io.ext.out <> pauser.io.ext.out\n pauser.io.ext.in <> io.ext.in\n pauser.io.in_free := recvPath.module.io.buf_free\n pauser.io.macAddr := io.ext.macAddr\n pauser.io.settings := io.ext.pauser\n } else {\n recvPath.module.io.in <> io.ext.in\n io.ext.out <> sendPath.module.io.out\n }\n\n control.module.io.macAddr := io.ext.macAddr\n sendPath.module.io.rlimit := io.ext.rlimit\n\n io.tapOut <> recvPath.module.io.tap\n sendPath.module.io.tap <> io.tapIn\n\n if (checksumOffload) {\n sendPath.module.io.csum.get.req <> control.module.io.txcsumReq\n sendPath.module.io.csum.get.enable := control.module.io.csumEnable\n control.module.io.rxcsumRes <> recvPath.module.io.csum.get.res\n recvPath.module.io.csum.get.enable := control.module.io.csumEnable\n } else {\n control.module.io.txcsumReq.ready := false.B\n control.module.io.rxcsumRes.valid := false.B\n control.module.io.rxcsumRes.bits := DontCare\n }\n }\n}\n\nclass SimNetwork extends BlackBox with HasBlackBoxResource {\n val io = IO(new Bundle {\n val clock = Input(Clock())\n val reset = Input(Bool())\n val net = Flipped(new NICIOvonly)\n })\n addResource(\"/vsrc/SimNetwork.v\")\n addResource(\"/csrc/SimNetwork.cc\")\n addResource(\"/csrc/device.h\")\n addResource(\"/csrc/device.cc\")\n addResource(\"/csrc/switch.h\")\n addResource(\"/csrc/switch.cc\")\n addResource(\"/csrc/packet.h\")\n}\n\n\nclass NICIOvonly extends Bundle {\n val in = Flipped(Valid(new StreamChannel(NET_IF_WIDTH)))\n val out = Valid(new StreamChannel(NET_IF_WIDTH))\n val macAddr = Input(UInt(ETH_MAC_BITS.W))\n val rlimit = Input(new RateLimiterSettings)\n val pauser = Input(new PauserSettings)\n\n}\n\nobject NICIOvonly {\n def apply(nicio: NICIO): NICIOvonly = {\n val vonly = Wire(new NICIOvonly)\n vonly.out.valid := nicio.out.valid\n vonly.out.bits := nicio.out.bits\n nicio.out.ready := true.B\n nicio.in.valid := vonly.in.valid\n nicio.in.bits := vonly.in.bits\n assert(!vonly.in.valid || nicio.in.ready, \"NIC input not ready for valid\")\n nicio.macAddr := vonly.macAddr\n nicio.rlimit := vonly.rlimit\n nicio.pauser := vonly.pauser\n vonly\n }\n}\n\nobject NICIO {\n def apply(vonly: NICIOvonly): NICIO = {\n val nicio = Wire(new NICIO)\n assert(!vonly.out.valid || nicio.out.ready)\n nicio.out.valid := vonly.out.valid\n nicio.out.bits := vonly.out.bits\n vonly.in.valid := nicio.in.valid\n vonly.in.bits := nicio.in.bits\n nicio.in.ready := true.B\n vonly.macAddr := nicio.macAddr\n vonly.rlimit := nicio.rlimit\n vonly.pauser := nicio.pauser\n nicio\n }\n\n}\ntrait CanHavePeripheryIceNIC { this: BaseSubsystem =>\n private val address = BigInt(0x10016000)\n private val portName = \"Ice-NIC\"\n\n\n val icenicOpt = p(NICKey).map { params =>\n val manager = locateTLBusWrapper(p(NICAttachKey).slaveWhere)\n val client = locateTLBusWrapper(p(NICAttachKey).masterWhere)\n // TODO: currently the controller is in the clock domain of the bus which masters it\n // we assume this is same as the clock domain of the bus the controller masters\n val domain = manager.generateSynchronousDomain.suggestName(\"icenic_domain\")\n\n val icenic = domain { LazyModule(new IceNIC(address, manager.beatBytes)) }\n\n manager.coupleTo(portName) { icenic.mmionode := TLFragmenter(manager.beatBytes, manager.blockBytes) := _ }\n client.coupleFrom(portName) { _ :=* icenic.dmanode }\n ibus.fromSync := icenic.intnode\n\n val inner_io = domain { InModuleBody {\n val inner_io = IO(new NICIOvonly).suggestName(\"nic\")\n inner_io <> NICIOvonly(icenic.module.io.ext)\n inner_io\n } }\n\n val outer_io = InModuleBody {\n val outer_io = IO(new ClockedIO(new NICIOvonly)).suggestName(\"nic\")\n outer_io.bits <> inner_io\n outer_io.clock := domain.module.clock\n outer_io\n }\n outer_io\n }\n}\n\n\nobject NicLoopback {\n def connect(net: Option[NICIOvonly], nicConf: Option[NICConfig], qDepth: Int, latency: Int = 10): Unit = {\n net.foreach { netio =>\n import PauseConsts.BT_PER_QUANTA\n val packetWords = nicConf.get.packetMaxBytes / NET_IF_BYTES\n val packetQuanta = (nicConf.get.packetMaxBytes * 8) / BT_PER_QUANTA\n netio.macAddr := PlusArg(\"macaddr\")\n netio.rlimit.inc := PlusArg(\"rlimit-inc\", 1)\n netio.rlimit.period := PlusArg(\"rlimit-period\", 1)\n netio.rlimit.size := PlusArg(\"rlimit-size\", 8)\n netio.pauser.threshold := PlusArg(\"pauser-threshold\", 2 * packetWords + latency)\n netio.pauser.quanta := PlusArg(\"pauser-quanta\", 2 * packetQuanta)\n netio.pauser.refresh := PlusArg(\"pauser-refresh\", packetWords)\n\n if (nicConf.get.usePauser) {\n val pauser = Module(new PauserComplex(qDepth))\n pauser.io.ext.flipConnect(NetDelay(NICIO(netio), latency))\n pauser.io.int.out <> pauser.io.int.in\n pauser.io.macAddr := netio.macAddr + (1 << 40).U\n pauser.io.settings := netio.pauser\n } else {\n\n netio.in := Pipe(netio.out, latency)\n }\n netio.in.bits.keep := NET_FULL_KEEP\n }\n }\n\n def connect(net: NICIOvonly, nicConf: NICConfig): Unit = {\n val packetWords = nicConf.packetMaxBytes / NET_IF_BYTES\n NicLoopback.connect(Some(net), Some(nicConf), 4 * packetWords)\n }\n}\n\nobject SimNetwork {\n def connect(net: Option[NICIOvonly], clock: Clock, reset: Bool) {\n net.foreach { netio =>\n val sim = Module(new SimNetwork)\n sim.io.clock := clock\n sim.io.reset := reset\n sim.io.net <> netio\n }\n }\n}\n", "groundtruth": " val pauseDropCheck = if (usePauser) Some(PauseDropCheck(_, _, _)) else None\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.6, "category_reason": "val binding"} {"task_id": "icenet", "path": "icenet/src/main/scala/NICTests.scala", "left_context": "package icenet\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.devices.tilelink.TLROM\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\nimport freechips.rocketchip.unittest.{UnitTest, UnitTestIO}\nimport freechips.rocketchip.util.{LatencyPipe, TwoWayCounter, UIntIsOneOf}\nimport scala.math.max\nimport IceNetConsts._\n\nclass IceNicTestSendDriver(\n sendReqs: Seq[(Int, Int, Boolean)],\n sendData: Seq[BigInt])(implicit p: Parameters) extends LazyModule {\n val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters(\n name = \"test-send-driver\", sourceId = IdRange(0, 1))))))\n\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this) {\n val io = IO(new Bundle with UnitTestIO {\n val send = new IceNicSendIO\n })\n\n val (tl, edge) = node.out(0)\n val dataBits = tl.params.dataBits\n val beatBytes = dataBits / 8\n val byteAddrBits = log2Ceil(beatBytes)\n val lenBits = NET_LEN_BITS - 1\n val addrBits = NET_IF_WIDTH - NET_LEN_BITS\n\n val (s_start :: s_write_req :: s_write_resp ::\n s_send :: s_done :: Nil) = Enum(5)\n val state = RegInit(s_start)\n\n val sendReqVec = VecInit(sendReqs.map {\n case (addr, len, part) => Cat(part.B, len.U(lenBits.W), addr.U(addrBits.W))})\n\n val sendReqAddrVec = VecInit(sendReqs.map{case (addr, _, _) => addr.U(addrBits.W)})\n val sendReqCounts = sendReqs.map { case (_, len, _) => len / beatBytes }\n val sendReqCountVec = VecInit(sendReqCounts.map(_.U))\n val sendReqBase = VecInit((0 +: (1 until sendReqs.size).map(\n i => sendReqCounts.slice(0, i).reduce(_ + _))).map(_.U(addrBits.W)))\n val maxMemCount = sendReqCounts.reduce(max(_, _))\n val totalMemCount = sendReqCounts.reduce(_ + _)\n\n require(totalMemCount == sendData.size)\n\n val sendDataVec = VecInit(sendData.map(_.U(dataBits.W)))\n\n val reqIdx = Reg(UInt(log2Ceil(sendReqs.size).W))\n val memIdx = Reg(UInt(log2Ceil(totalMemCount).W))\n\n val outSend = TwoWayCounter(\n io.send.req.fire, io.send.comp.fire, sendReqs.size)\n\n val writeAddr = sendReqAddrVec(reqIdx) + (memIdx << byteAddrBits.U)\n val writeData = sendDataVec(sendReqBase(reqIdx) + memIdx)\n\n tl.a.valid := state === s_write_req\n tl.a.bits := edge.Put(\n fromSource = 0.U,\n toAddress = writeAddr,\n lgSize = byteAddrBits.U,\n data = writeData)._2\n tl.d.ready := state === s_write_resp\n\n io.send.req.valid := state === s_send\n io.send.req.bits := sendReqVec(reqIdx)\n io.send.comp.ready := outSend =/= 0.U\n\n io.finished := state === s_done && outSend === 0.U\n\n when (state === s_start && io.start) {\n reqIdx := 0.U\n memIdx := 0.U\n state := s_write_req\n }\n\n when (tl.a.fire) { state := s_write_resp }\n\n when (tl.d.fire) {\n memIdx := memIdx + 1.U\n state := s_write_req\n\n when (memIdx === (sendReqCountVec(reqIdx) - 1.U)) {\n memIdx := 0.U\n reqIdx := reqIdx + 1.U\n when (reqIdx === (sendReqs.size - 1).U) {\n reqIdx := 0.U\n state := s_send\n }\n }\n }\n\n when (io.send.req.fire) {\n reqIdx := reqIdx + 1.U\n when (reqIdx === (sendReqs.size - 1).U) {\n reqIdx := 0.U\n state := s_done\n }\n }\n }\n}\n\nclass IceNicTestRecvDriver(recvReqs: Seq[Int], recvData: Seq[BigInt])\n (implicit p: Parameters) extends LazyModule {\n val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters(\n name = \"test-recv-driver\", sourceId = IdRange(0, 1))))))\n\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this) {\n val io = IO(new Bundle with UnitTestIO {\n val recv = new IceNicRecvIO\n })\n\n val (tl, edge) = node.out(0)\n val dataBits = tl.params.dataBits\n val beatBytes = dataBits / 8\n val byteAddrBits = log2Ceil(beatBytes)\n\n val (s_start :: s_recv :: s_wait ::\n s_check_req :: s_check_resp :: s_done :: Nil) = Enum(6)\n val state = RegInit(s_start)\n\n val recvReqVec = VecInit(recvReqs.map(_.U(NET_IF_WIDTH.W)))\n val recvDataVec = VecInit(recvData.map(_.U(dataBits.W)))\n\n val reqIdx = Reg(UInt(log2Ceil(recvReqs.size).W))\n val memIdx = Reg(UInt(log2Ceil(recvData.size).W))\n\n val outRecv = TwoWayCounter(\n io.recv.req.fire, io.recv.comp.fire, recvReqVec.size)\n\n tl.a.valid := state === s_check_req\n tl.a.bits := edge.Get(\n fromSource = 0.U,\n toAddress = recvReqVec.head + (memIdx << byteAddrBits.U),\n lgSize = byteAddrBits.U)._2\n tl.d.ready := state === s_check_resp\n\n io.recv.req.valid := state === s_recv\n io.recv.req.bits := recvReqVec(reqIdx)\n io.recv.comp.ready := outRecv =/= 0.U\n\n io.finished := state === s_done\n\n when (state === s_start && io.start) {\n reqIdx := 0.U\n memIdx := 0.U\n state := s_recv\n }\n\n when (io.recv.req.fire) {\n reqIdx := reqIdx + 1.U\n when (reqIdx === (recvReqVec.size - 1).U) {\n reqIdx := 0.U\n state := s_wait\n }\n }\n\n when (state === s_wait && outRecv === 0.U) {\n state := s_check_req\n }\n\n when (state === s_check_req && tl.a.ready) {\n state := s_check_resp\n }\n\n when (state === s_check_resp && tl.d.valid) {\n memIdx := memIdx + 1.U\n state := s_check_req\n when (memIdx === (recvData.size - 1).U) {\n memIdx := 0.U\n state := s_done\n }\n }\n\n assert(!tl.d.valid || tl.d.bits.data === recvDataVec(memIdx),\n \"IceNicTest: Received wrong data\")\n }\n}\n\nclass IceNicRecvTest(implicit p: Parameters) extends NICLazyModule {\n val recvReqs = Seq(0, 1440, 1464)\n // The 90-flit packet should be dropped\n val recvLens = Seq(180, 3, 90, 7)\n val testData = Seq.tabulate(280) { i => BigInt(i << 4) }\n val recvData = testData.take(183) ++ testData.drop(273)\n\n val nicParams = p.alterPartial({\n case NICKey => Some(p(NICKey).get.copy(inBufFlits = 200))\n })\n val recvDriver = LazyModule(new IceNicTestRecvDriver(recvReqs, recvData))\n val recvPath = LazyModule(new IceNicRecvPath()(nicParams))\n val xbar = LazyModule(new TLXbar)\n val mem = LazyModule(new TLRAM(\n AddressSet(0, 0x7ff), beatBytes = NET_IF_BYTES))\n\n val MEM_LATENCY = 32\n val RLIMIT_INC = 1\n val RLIMIT_PERIOD = 4\n val RLIMIT_SIZE = 8\n\n xbar.node := recvDriver.node\n xbar.node := recvPath.node\n mem.node := TLFragmenter(NET_IF_BYTES, maxAcquireBytes) := TLBuffer.chainNode(MEM_LATENCY) := xbar.node\n\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this) {\n val io = IO(new Bundle with UnitTestIO)\n\n val gen = Module(new PacketGen(recvLens, testData))\n gen.io.start := io.start\n recvDriver.module.io.start := gen.io.finished\n recvPath.module.io.recv <> recvDriver.module.io.recv\n recvPath.module.io.in <> RateLimiter(\n gen.io.out, RLIMIT_INC, RLIMIT_PERIOD, RLIMIT_SIZE)\n io.finished := recvDriver.module.io.finished\n }\n}\n\nclass IceNicRecvTestWrapper(implicit p: Parameters) extends UnitTest(20000) {\n val test = Module(LazyModule(new IceNicRecvTest).module)\n test.io.start := io.start\n io.finished := test.io.finished\n}\n\nclass IceNicSendTest(implicit p: Parameters) extends LazyModule {\n val sendReqs = Seq(\n (2, 10, true),\n (17, 6, false),\n (24, 12, false))\n val sendData = Seq(\n BigInt(\"7766554433221100\", 16),\n BigInt(\"FFEEDDCCBBAA9988\", 16),\n BigInt(\"0123456789ABCDEF\", 16),\n BigInt(\"FEDCBA9876543210\", 16),\n BigInt(\"76543210FDECBA98\", 16))\n\n val recvData = Seq(\n BigInt(\"9988776655443322\", 16),\n BigInt(\"23456789ABCDBBAA\", 16),\n BigInt(\"FEDCBA9876543210\", 16),\n BigInt(\"00000000FDECBA98\", 16))\n val recvKeep = Seq(0xFF, 0xFF, 0xFF, 0x0F)\n val recvLast = Seq(false, true, false, true)\n\n val sendPath = LazyModule(new IceNicSendPath)\n val rom = LazyModule(new TLROM(0, 64,\n sendData.flatMap(\n data => (0 until 8).map(i => ((data >> (i * 8)) & 0xff).toByte)),\n beatBytes = 8))\n\n rom.node := TLFragmenter(NET_IF_BYTES, 16) := TLBuffer() := sendPath.node\n\n val RLIMIT_INC = 1\n val RLIMIT_PERIOD = 0\n val RLIMIT_SIZE = 8\n\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this) {\n val io = IO(new Bundle with UnitTestIO)\n\n val sendPathIO = sendPath.module.io\n val sendReqVec = VecInit(sendReqs.map { case (start, len, part) =>\n Cat(part.B, len.U(15.W), start.U(48.W))\n })\n val (sendReqIdx, sendReqDone) = Counter(sendPathIO.send.req.fire, sendReqs.size)\n val (sendCompIdx, sendCompDone) = Counter(sendPathIO.send.comp.fire, sendReqs.size)\n\n val started = RegInit(false.B)\n val requesting = RegInit(false.B)\n val completing = RegInit(false.B)\n\n sendPathIO.send.req.valid := requesting\n sendPathIO.send.req.bits := sendReqVec(sendReqIdx)\n sendPathIO.send.comp.ready := completing\n\n when (!started && io.start) {\n requesting := true.B\n completing := true.B\n }\n when (sendReqDone) { requesting := false.B }\n", "right_context": "\n sendPathIO.rlimit.inc := RLIMIT_INC.U\n sendPathIO.rlimit.period := RLIMIT_PERIOD.U\n sendPathIO.rlimit.size := RLIMIT_SIZE.U\n\n val check = Module(new PacketCheck(recvData, recvKeep, recvLast))\n check.io.in <> sendPathIO.out\n io.finished := check.io.finished && !completing && !requesting\n }\n}\n\nclass IceNicSendTestWrapper(implicit p: Parameters) extends UnitTest {\n val test = Module(LazyModule(new IceNicSendTest).module)\n test.io.start := io.start\n io.finished := test.io.finished\n}\n\nclass IceNicTest(implicit p: Parameters) extends NICLazyModule {\n val sendReqs = Seq(\n (0, 128, true),\n (144, 160, false),\n (320, 64, false))\n val recvReqs = Seq(256, 544)\n val testData = Seq.tabulate(44)(i => BigInt(i << 4))\n\n val sendDriver = LazyModule(new IceNicTestSendDriver(sendReqs, testData))\n val recvDriver = LazyModule(new IceNicTestRecvDriver(recvReqs, testData))\n val sendPath = LazyModule(new IceNicSendPath)\n val recvPath = LazyModule(new IceNicRecvPath)\n val xbar = LazyModule(new TLXbar)\n val mem = LazyModule(new TLRAM(\n AddressSet(0, 0x1ff), beatBytes = NET_IF_BYTES))\n\n val NET_LATENCY = 64\n val MEM_LATENCY = 32\n val RLIMIT_INC = 1\n val RLIMIT_PERIOD = 0\n val RLIMIT_SIZE = 8\n\n xbar.node := sendDriver.node\n xbar.node := recvDriver.node\n xbar.node := sendPath.node\n xbar.node := recvPath.node\n mem.node := TLFragmenter(NET_IF_BYTES, maxAcquireBytes) := TLBuffer.chainNode(MEM_LATENCY) := xbar.node\n\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this) {\n val io = IO(new Bundle with UnitTestIO)\n\n sendPath.module.io.send <> sendDriver.module.io.send\n recvPath.module.io.recv <> recvDriver.module.io.recv\n\n sendPath.module.io.rlimit.inc := RLIMIT_INC.U\n sendPath.module.io.rlimit.period := RLIMIT_PERIOD.U\n sendPath.module.io.rlimit.size := RLIMIT_SIZE.U\n\n recvPath.module.io.in <> LatencyPipe(sendPath.module.io.out, NET_LATENCY)\n\n sendDriver.module.io.start := io.start\n recvDriver.module.io.start := io.start\n io.finished := sendDriver.module.io.finished && recvDriver.module.io.finished\n\n val count_start :: count_up :: count_print :: count_done :: Nil = Enum(4)\n val count_state = RegInit(count_start)\n val cycle_count = Reg(UInt(64.W))\n val recv_count = Reg(UInt(1.W))\n\n when (count_state === count_start && sendPath.module.io.send.req.fire) {\n count_state := count_up\n cycle_count := 0.U\n recv_count := 1.U\n }\n when (count_state === count_up) {\n cycle_count := cycle_count + 1.U\n when (recvPath.module.io.recv.comp.fire) {\n recv_count := recv_count - 1.U\n when (recv_count === 0.U) { count_state := count_print }\n }\n }\n when (count_state === count_print) {\n printf(\"NIC test completed in %d cycles\\n\", cycle_count)\n count_state := count_done\n }\n }\n}\n\nclass IceNicTestWrapper(implicit p: Parameters) extends UnitTest(50000) {\n val test = Module(LazyModule(new IceNicTest).module)\n test.io.start := io.start\n io.finished := test.io.finished\n}\n\nclass MisalignedTestDriver(implicit p: Parameters) extends Module {\n val io = IO(new Bundle with UnitTestIO {\n val net = new StreamIO(NET_IF_WIDTH)\n val send = new IceNicSendIO\n val recv = new IceNicRecvIO\n })\n\n val fullData = Seq(\n \"hDEADBEEF\", \"h01234567\", \"h555999ff\", \"h09341423\",\n \"h1384AEDF\", \"hABCD1234\", \"h1093567A\", \"hBADD00D1\",\n \"hA325B246\", \"h49230923\", \"h11113333\", \"hAEDC1445\").map(_.U(32.W))\n\n val outData1 = VecInit(\n Cat(fullData(8), fullData(7)),\n Cat(fullData(10), fullData(9)),\n Cat(0.U(32.W), fullData(11)))\n val outKeep1 = VecInit(Seq.fill(2)(~0.U(8.W)) :+ \"h0f\".U)\n\n val outData2 = VecInit(\n Cat(fullData(1), fullData(0)),\n Cat(fullData(3), fullData(2)),\n Cat(fullData(5), fullData(4)),\n Cat(0.U(32.W), fullData(6)))\n val outKeep2 = VecInit(Seq.fill(3)(~0.U(8.W)) :+ \"h0f\".U)\n\n val expData = VecInit(\n Cat(fullData(6), fullData(5)),\n Cat(fullData(8), fullData(7)),\n Cat(fullData(10), fullData(9)))\n\n val (s_start :: s_sendreq :: s_sendcomp :: s_recvreq :: s_recvcomp ::\n s_outdata1 :: s_outdata2 :: s_indata :: s_done :: Nil) = Enum(9)\n val state = RegInit(s_start)\n\n val (recvReqIdx, recvReqDone) = Counter(io.recv.req.fire, 2)\n val (recvCompIdx, recvCompDone) = Counter(io.recv.comp.fire, 2)\n\n val (outIdx1, outDone1) = Counter(\n state === s_outdata1 && io.net.out.ready, outData1.size)\n val (outIdx2, outDone2) = Counter(\n state === s_outdata2 && io.net.out.ready, outData2.size)\n val (inIdx, inDone) = Counter(io.net.in.fire, expData.size)\n\n val outBits1 = Wire(new StreamChannel(NET_IF_WIDTH))\n outBits1.data := outData1(outIdx1)\n outBits1.keep := outKeep1(outIdx1)\n outBits1.last := outIdx1 === (outData1.size - 1).U\n\n val outBits2 = Wire(new StreamChannel(NET_IF_WIDTH))\n outBits2.data := outData2(outIdx2)\n outBits2.keep := outKeep2(outIdx2)\n outBits2.last := outIdx2 === (outData2.size - 1).U\n\n io.send.req.valid := state === s_sendreq\n io.send.req.bits := Cat((expData.size * 8).U(16.W), 20.U(48.W))\n io.send.comp.ready := state === s_sendcomp\n\n io.recv.req.valid := state === s_recvreq\n io.recv.req.bits := Mux(recvReqIdx === 0.U, 28.U, 0.U)\n io.recv.comp.ready := state === s_recvcomp\n\n io.net.out.valid := state.isOneOf(s_outdata1, s_outdata2)\n io.net.out.bits := Mux(state === s_outdata1, outBits1, outBits2)\n io.net.in.ready := state === s_indata\n\n io.finished := state === s_done\n\n when (state === s_start && io.start) { state := s_recvreq }\n\n when (recvReqDone) { state := s_outdata1 }\n\n when (outDone1) { state := s_outdata2 }\n when (outDone2) { state := s_recvcomp }\n\n when (recvCompDone) { state := s_sendreq }\n\n when (io.send.req.fire) { state := s_indata }\n\n when (inDone) { state := s_done }\n\n assert(!io.net.in.valid || io.net.in.bits.data === expData(inIdx),\n \"MisalignedTest: input data does not match expected\")\n assert(!io.net.in.valid || io.net.in.bits.keep.andR,\n \"MisalignedTest: input keep does not match expected\")\n assert(!io.net.in.valid || io.net.in.bits.last === (inIdx === (expData.size-1).U),\n \"MisalignedTest: input last does not match expected\")\n\n}\n\nclass MisalignedTest(implicit p: Parameters) extends NICLazyModule {\n val sendpath = LazyModule(new IceNicSendPath)\n val recvpath = LazyModule(new IceNicRecvPath)\n\n val xbar = LazyModule(new TLXbar)\n val mem = LazyModule(new TLRAM(\n AddressSet(0, 0x7ff), beatBytes = NET_IF_BYTES))\n\n xbar.node := sendpath.node\n xbar.node := recvpath.node\n mem.node := TLFragmenter(NET_IF_BYTES, maxAcquireBytes) :=\n TLBuffer() := xbar.node\n\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this) {\n val io = IO(new Bundle with UnitTestIO)\n\n val driver = Module(new MisalignedTestDriver)\n\n driver.io.start := io.start\n io.finished := driver.io.finished\n\n driver.io.net.in <> sendpath.module.io.out\n recvpath.module.io.in <> driver.io.net.out\n\n sendpath.module.io.send.req <> Queue(driver.io.send.req, 1)\n recvpath.module.io.recv.req <> Queue(driver.io.recv.req, 2)\n driver.io.send.comp <> Queue(sendpath.module.io.send.comp, 1)\n driver.io.recv.comp <> Queue(recvpath.module.io.recv.comp, 2)\n\n val rlimit = sendpath.module.io.rlimit\n rlimit.inc := 1.U\n rlimit.period := 0.U\n rlimit.size := 8.U\n }\n}\n\nclass MisalignedTestWrapper(implicit p: Parameters) extends UnitTest {\n val test = Module(LazyModule(new MisalignedTest).module)\n test.io.start := io.start\n io.finished := test.io.finished\n}\n", "groundtruth": " when (sendCompDone) { completing := false.B }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "icenet", "path": "icenet/src/main/scala/Pauser.scala", "left_context": "package icenet\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.util.{HellaPeekingArbiter}\nimport freechips.rocketchip.unittest.UnitTest\nimport IceNetConsts._\n\nobject PauseConsts {\n val MAC_ETHTYPE = 0x8808\n val PAUSE_CTRL = 0x0001\n val BT_PER_QUANTA = 512\n val CYCLES_PER_QUANTA = BT_PER_QUANTA / NET_IF_WIDTH\n val MULTICAST_MACADDR = 0x010000C28001L\n}\nimport PauseConsts._\n\ntrait NetworkEndianHelpers {\n def ntohs(x: UInt) = Cat(x(7, 0), x(15, 8))\n def htons(x: UInt) = ntohs(x)\n def ntohl(x: UInt) = Cat(ntohs(x(15, 0)), ntohs(x(31, 16)))\n def htonl(x: UInt) = ntohl(x)\n}\n\nclass PauserSettings extends Bundle {\n val threshold = UInt(16.W)\n val quanta = UInt(16.W)\n val refresh = UInt(16.W)\n}\n\nobject PauseDropCheck extends NetworkEndianHelpers {\n def apply(header: EthernetHeader, ch: StreamChannel, update: Bool): Bool = {\n val first = RegInit(true.B)\n val isPause = ntohs(header.ethType) === MAC_ETHTYPE.U &&\n ntohs(ch.data(15, 0)) === PAUSE_CTRL.U && first\n val isPauseReg = RegInit(false.B)\n\n when (update && first) { first := false.B; isPauseReg := isPause }\n when (update && ch.last) { first := true.B; isPauseReg := false.B }\n\n isPause || isPauseReg\n }\n}\n\n/**\n * Flow control unit using Ethernet pause frames\n * See https://en.wikipedia.org/wiki/Ethernet_flow_control#Pause_frame\n * @creditInit Size of each buffer being tracked\n * @nBuckets Number of buffers being tracked\n */\nclass Pauser(creditInit: Int, nBuckets: Int) extends Module\n with NetworkEndianHelpers {\n val timerBits = 16 + log2Ceil(CYCLES_PER_QUANTA)\n val creditBits = log2Ceil(creditInit + 1)\n\n val io = IO(new Bundle {\n val ext = new StreamIO(NET_IF_WIDTH)\n val int = Flipped(new StreamIO(NET_IF_WIDTH))\n val in_free = Input(Vec(nBuckets, UInt(8.W)))\n val macAddr = Input(UInt(48.W))\n val settings = Input(new PauserSettings)\n })\n\n val credits = RegInit(VecInit(Seq.fill(nBuckets)(creditInit.U(16.W))))\n val outPauseTimer = RegInit(0.U(timerBits.W))\n val outPaused = outPauseTimer > 0.U\n\n io.int.in <> io.ext.in\n\n val headerBeats = ETH_HEAD_BYTES / NET_IF_BYTES\n val inHeaderVec = Reg(Vec(headerBeats, UInt(NET_IF_WIDTH.W)))\n val inHeader = inHeaderVec.asTypeOf(new EthernetHeader)\n\n val s_head :: s_mac :: s_tail :: Nil = Enum(3)\n val state = RegInit(s_head)\n\n val inHeadIdx = RegInit(0.U(log2Ceil(headerBeats).W))\n\n when (outPaused) { outPauseTimer := outPauseTimer - 1.U }\n\n when (io.int.in.fire) {\n val data = io.int.in.bits.data\n\n switch (state) {\n is (s_head) {\n inHeaderVec(inHeadIdx) := data\n inHeadIdx := inHeadIdx + 1.U\n when (inHeadIdx === (headerBeats-1).U) { state := s_mac }\n }\n is (s_mac) {\n val isMac = ntohs(inHeader.ethType) === MAC_ETHTYPE.U\n val isPause = ntohs(data(15, 0)) === PAUSE_CTRL.U\n val quanta = ntohs(data(31, 16))\n val cycles = quanta << log2Ceil(CYCLES_PER_QUANTA).U\n when (isMac && isPause) { outPauseTimer := cycles }\n state := s_tail\n }\n }\n\n when (io.int.in.bits.last) {\n state := s_head\n inHeadIdx := 0.U\n }\n }\n\n for (i <- 0 until nBuckets) {\n credits(i) := credits(i) - io.int.in.fire + io.in_free(i)\n }\n\n val arb = Module(new PacketArbiter(2))\n\n val outHeader = EthernetHeader(\n MULTICAST_MACADDR.U,\n io.macAddr,\n htons(MAC_ETHTYPE.U(16.W)))\n val outVec = VecInit(outHeader.toWords() :+ Cat(\n htons(io.settings.quanta), htons(PAUSE_CTRL.U(16.W))))\n val sendPause = RegInit(false.B)\n val (outIdx, outDone) = Counter(arb.io.in(0).fire, outVec.size)\n\n arb.io.in(0).valid := sendPause\n arb.io.in(0).bits.data := outVec(outIdx)\n arb.io.in(0).bits.keep := NET_FULL_KEEP\n arb.io.in(0).bits.last := outIdx === (outVec.size-1).U\n\n val inPauseTimer = RegInit(0.U(16.W))\n val inPaused = inPauseTimer > 0.U\n\n val creditsLow = credits.map(_ < io.settings.threshold).reduce(_ || _)\n\n when (outDone) {\n inPauseTimer := io.settings.refresh\n sendPause := false.B\n }\n when (inPaused) { inPauseTimer := inPauseTimer - 1.U }\n when (creditsLow && !sendPause && !inPaused) {\n sendPause := true.B\n }\n\n val outInProgress = RegInit(false.B)\n val canForward = !outPaused || outInProgress\n\n arb.io.in(1).valid := canForward && io.int.out.valid\n arb.io.in(1).bits := io.int.out.bits\n io.int.out.ready := canForward && arb.io.in(1).ready\n\n when (arb.io.in(1).fire) {\n when (!outInProgress) { outInProgress := true.B }\n", "right_context": " }\n\n io.ext.out <> arb.io.out\n}\n\nclass PauserComplex(nFlits: Int) extends Module {\n val creditBits = log2Ceil(nFlits + 1)\n val io = IO(new Bundle {\n val ext = new StreamIO(NET_IF_WIDTH)\n val int = Flipped(new StreamIO(NET_IF_WIDTH))\n val macAddr = Input(UInt(48.W))\n val settings = Input(new PauserSettings)\n })\n\n val pauser = Module(new Pauser(nFlits, 1))\n val buffer = Module(new NetworkPacketBuffer(\n nFlits, dropChecks = Seq(PauseDropCheck(_, _, _)), dropless = true))\n\n io.ext <> pauser.io.ext\n pauser.io.macAddr := io.macAddr\n pauser.io.settings := io.settings\n\n pauser.io.int.out <> io.int.out\n buffer.io.stream.in <> pauser.io.int.in\n pauser.io.in_free(0) := buffer.io.free\n io.int.in <> buffer.io.stream.out\n}\n\nclass PauserTest extends UnitTest {\n val nFlits = 400\n val latency = 128\n val packetWords = ETH_STANDARD_MAX_BYTES / NET_IF_BYTES\n val threshold = latency + packetWords\n val pauseQuanta = threshold / CYCLES_PER_QUANTA\n val pauseRefresh = packetWords\n\n val lcomplex = Module(new PauserComplex(nFlits))\n val rcomplex = Module(new PauserComplex(nFlits))\n\n rcomplex.io.ext.flipConnect(NetDelay(lcomplex.io.ext, latency))\n rcomplex.io.int.out <> rcomplex.io.int.in\n\n val lmacaddr = (0x2L << 40).U(48.W)\n val rmacaddr = (0x3L << 40).U(48.W)\n\n lcomplex.io.macAddr := lmacaddr\n rcomplex.io.macAddr := rmacaddr\n lcomplex.io.settings.threshold := threshold.U\n rcomplex.io.settings.threshold := threshold.U\n lcomplex.io.settings.quanta := pauseQuanta.U\n rcomplex.io.settings.quanta := pauseQuanta.U\n lcomplex.io.settings.refresh := pauseRefresh.U\n rcomplex.io.settings.refresh := pauseRefresh.U\n\n val ethHeader = EthernetHeader(rmacaddr, lmacaddr, 0x0000.U)\n val pktData = VecInit(\n ethHeader.toWords() ++ Seq.tabulate(130)(_.U(NET_IF_WIDTH.W)))\n val nPackets = 8\n\n val started = RegInit(false.B)\n\n val sending = RegInit(false.B)\n val (sendIdx, sendPktDone) = Counter(lcomplex.io.int.out.fire, pktData.size)\n val (sendPhase, sendDone) = Counter(sendPktDone, nPackets)\n\n val receiving = RegInit(false.B)\n val (recvIdx, recvPktDone) = Counter(lcomplex.io.int.in.fire, pktData.size)\n val (recvPhase, recvDone) = Counter(recvPktDone, nPackets)\n\n lcomplex.io.int.out.valid := sending\n lcomplex.io.int.out.bits.data := pktData(sendIdx)\n lcomplex.io.int.out.bits.keep := NET_FULL_KEEP\n lcomplex.io.int.out.bits.last := sendIdx === (pktData.size-1).U\n lcomplex.io.int.in.ready := receiving\n\n when (!started && io.start) {\n started := true.B\n sending := true.B\n receiving := true.B\n }\n when (sendDone) { sending := false.B }\n when (recvDone) { receiving := false.B }\n\n val recv = lcomplex.io.int.in\n assert(!recv.valid ||\n (recv.bits.data === pktData(recvIdx) &&\n recv.bits.keep === NET_FULL_KEEP &&\n recv.bits.last === (recvIdx === (pktData.size-1).U)),\n \"PauserTest: received incorrect data, keep, or last\")\n\n io.finished := started && !sending && !receiving\n}\n", "groundtruth": " when (arb.io.in(1).bits.last) { outInProgress := false.B }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "icenet", "path": "icenet/src/main/scala/Stream.scala", "left_context": "package icenet\n\nimport chisel3._\nimport chisel3.util._\n\n// These classes originated in testchipip, but are copied\n// here to reduce dependencies\nclass StreamChannel(val w: Int) extends Bundle {\n val data = UInt(w.W)\n val keep = UInt((w/8).W)\n val last = Bool()\n}\n\nclass StreamIO(val w: Int) extends Bundle {\n val in = Flipped(Decoupled(new StreamChannel(w)))\n val out = Decoupled(new StreamChannel(w))\n\n", "right_context": "", "groundtruth": " def flipConnect(other: StreamIO) {\n in <> other.out\n other.in <> out\n }\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "icenet", "path": "icenet/src/main/scala/TCAM.scala", "left_context": "package icenet\n\nimport chisel3._\nimport chisel3.util._\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nclass TCAMMatchIO(n: Int, dataBits: Int) extends Bundle {\n val addrBits = log2Ceil(n)\n val data = Output(UInt(dataBits.W))\n val addr = Input(UInt(addrBits.W))\n val found = Input(Bool())\n\n}\n\nclass TCAM(address: BigInt, val n: Int, val dataBits: Int, val nPorts: Int)\n (implicit p: Parameters) extends LazyModule {\n val addrBits = log2Ceil(n)\n val byteAddrBits = log2Ceil(dataBits / 8)\n val beatBytes = 1 << byteAddrBits\n val addrMask = (1 << (1 + addrBits + byteAddrBits)) - 1\n\n val node = TLManagerNode(Seq(TLSlavePortParameters.v1(Seq(TLSlaveParameters.v1(\n address = Seq(AddressSet(address, addrMask)),\n regionType = RegionType.PUT_EFFECTS,\n supportsGet = TransferSizes(1, beatBytes),\n supportsPutFull = TransferSizes(1, beatBytes))), beatBytes)))\n\n lazy val module = new TCAMModule(this)\n}\n\nclass TCAMModule(outer: TCAM) extends LazyModuleImp(outer) {\n val io = IO(new Bundle {\n val tcam = Flipped(\n Vec(outer.nPorts, new TCAMMatchIO(outer.n, outer.dataBits)))\n })\n\n val (tl, edge) = outer.node.in(0)\n\n val dataArr = Reg(Vec(outer.n, UInt(outer.dataBits.W)))\n val maskArr = Reg(Vec(outer.n, UInt(outer.dataBits.W)))\n\n val acq = Queue(tl.a, 1)\n val regsel = acq.bits.address(outer.addrBits + outer.byteAddrBits)\n val wordaddr = acq.bits.address(\n outer.addrBits + outer.byteAddrBits - 1, outer.byteAddrBits)\n\n tl.d.valid := acq.valid\n acq.ready := tl.d.ready\n tl.d.bits := edge.AccessAck(acq.bits, 0.U)\n tl.d.bits.opcode := Mux(edge.hasData(acq.bits),\n TLMessages.AccessAck, TLMessages.AccessAckData)\n tl.d.bits.data := Mux(regsel, maskArr(wordaddr), dataArr(wordaddr))\n\n when (acq.fire && edge.hasData(acq.bits)) {\n when (regsel) {\n", "right_context": "\n io.tcam.foreach { m =>\n val matches = dataArr.zip(maskArr).map { case (data, mask) =>\n !((m.data ^ data) & mask).orR\n }\n m.addr := PriorityEncoder(matches)\n m.found := matches.reduce(_ || _)\n }\n}\n", "groundtruth": " maskArr(wordaddr) := acq.bits.data(outer.dataBits - 1, 0)\n } .otherwise {\n dataArr(wordaddr) := acq.bits.data(outer.dataBits - 1, 0)\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.8, "category_reason": ".otherwise clause"} {"task_id": "icenet", "path": "icenet/src/main/scala/Tap.scala", "left_context": "package icenet\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.unittest.UnitTest\nimport freechips.rocketchip.util.UIntIsOneOf\nimport scala.math.max\nimport IceNetConsts._\n\nclass NetworkTap[T <: Data](\n selectFuncs: Seq[T => Bool],\n headerTyp: T = new EthernetHeader,\n headerBytes: Int = ETH_HEAD_BYTES,\n wordBytes: Int = NET_IF_WIDTH / 8) extends Module {\n\n val wordBits = wordBytes * 8\n val headerWords = headerBytes / wordBytes\n val n = selectFuncs.length\n\n val io = IO(new Bundle {\n val inflow = Flipped(Decoupled(new StreamChannel(wordBits)))\n val passthru = Decoupled(new StreamChannel(wordBits))\n val tapout = Vec(n, Decoupled(new StreamChannel(wordBits)))\n })\n\n assert(n > 0, \"NetworkTap must have at least one output tap\")\n\n val headerVec = Reg(Vec(headerWords, UInt(wordBits.W)))\n val header = headerVec.asTypeOf(headerTyp)\n\n val idxBits = log2Ceil(headerWords)\n val headerIdx = RegInit(0.U(idxBits.W))\n val headerLen = Reg(UInt(idxBits.W))\n val bodyLess = Reg(Bool())\n\n val (s_collect_header :: s_check_header ::\n s_output_header :: s_forward_body :: Nil) = Enum(4)\n val state = RegInit(s_collect_header)\n val route = Reg(Vec(n, Bool()))\n\n val selectedReady = MuxCase(io.passthru.ready,\n route.zip(io.tapout.map(_.ready)))\n\n io.inflow.ready := MuxLookup(state, false.B)(Seq(\n s_collect_header -> true.B,\n s_forward_body -> selectedReady))\n\n val hasTapout = route.reduce(_ || _)\n\n io.passthru.valid := MuxLookup(Cat(state, hasTapout), false.B)(Seq(\n Cat(s_output_header, false.B) -> true.B,\n Cat(s_forward_body, false.B) -> io.inflow.valid))\n io.passthru.bits.data := MuxLookup(Cat(state, hasTapout), 0.U)(Seq(\n Cat(s_output_header, false.B) -> headerVec(headerIdx),\n Cat(s_forward_body, false.B) -> io.inflow.bits.data))\n io.passthru.bits.last := MuxLookup(Cat(state, hasTapout), false.B)(Seq(\n Cat(s_output_header, false.B) -> (bodyLess && headerIdx === headerLen),\n Cat(s_forward_body, false.B) -> io.inflow.bits.last))\n io.passthru.bits.keep := NET_FULL_KEEP\n\n io.tapout.zip(route).foreach { case (tapout, sel) =>\n tapout.valid := MuxLookup(Cat(state, sel), false.B)(Seq(\n Cat(s_output_header, true.B) -> true.B,\n Cat(s_forward_body, true.B) -> io.inflow.valid))\n tapout.bits.data := MuxLookup(Cat(state, sel), 0.U)(Seq(\n Cat(s_output_header, true.B) -> headerVec(headerIdx),\n Cat(s_forward_body, true.B) -> io.inflow.bits.data))\n tapout.bits.last := MuxLookup(Cat(state, sel), false.B)(Seq(\n Cat(s_output_header, true.B) -> (bodyLess && headerIdx === headerLen),\n Cat(s_forward_body, true.B) -> io.inflow.bits.last))\n tapout.bits.keep := NET_FULL_KEEP\n }\n\n when (state === s_collect_header && io.inflow.valid) {\n headerIdx := headerIdx + 1.U\n headerVec(headerIdx) := io.inflow.bits.data\n\n val headerLast = headerIdx === (headerWords-1).U\n\n when (io.inflow.bits.last || headerLast) {\n headerLen := headerIdx\n headerIdx := 0.U\n bodyLess := io.inflow.bits.last\n\n when (headerLast) {\n state := s_check_header\n } .otherwise {\n route.foreach(_ := false.B)\n state := s_output_header\n }\n }\n }\n\n when (state === s_check_header) {\n route := selectFuncs.map(_(header))\n state := s_output_header\n }\n\n val headerFire = state === s_output_header && selectedReady\n val bodyFire = state === s_forward_body && io.inflow.fire\n\n when (headerFire) {\n headerIdx := headerIdx + 1.U\n when (headerIdx === headerLen) {\n headerIdx := 0.U\n state := Mux(bodyLess, s_collect_header, s_forward_body)\n }\n }\n\n when (bodyFire && io.inflow.bits.last) { state := s_collect_header }\n}\n\nclass NetworkTapTest extends UnitTest {\n val sendPayloads = Seq(\n Seq(0L, 0x800L << 48, 23L, 13L, 56L, 12L),\n Seq(0L, 0x800L << 48),\n Seq(0L, 0x801L << 48, 22, 16),\n Seq(0L))\n val sendLengths = sendPayloads.map(_.size)\n val sendData = sendPayloads.flatten.map(l => BigInt(l))\n\n val genIn = Module(new PacketGen(sendLengths, sendData))\n genIn.io.start := io.start\n\n val tapPayloads = sendPayloads.take(2)\n val tapData = tapPayloads.flatten.map(l => BigInt(l))\n val tapKeep = Seq.fill(tapData.size) { 0xff }\n val tapLast = tapPayloads.flatMap {\n\n }\n val checkTap = Module(new PacketCheck(tapData, tapKeep, tapLast))\n\n val passPayloads = sendPayloads.drop(2)\n val passData = passPayloads.flatten.map(l => BigInt(l))\n val passKeep = Seq.fill(passData.size) { 0xff }\n val passLast = passPayloads.flatMap {\n", "right_context": " }\n val checkPass = Module(new PacketCheck(passData, passKeep, passLast))\n\n val tap = Module(new NetworkTap(\n Seq((header: EthernetHeader) => header.ethType === 0x800.U)))\n tap.io.inflow <> genIn.io.out\n checkTap.io.in <> tap.io.tapout(0)\n checkPass.io.in <> tap.io.passthru\n\n io.finished := checkTap.io.finished || checkPass.io.finished\n}\n", "groundtruth": " pl => (Seq.fill(pl.size-1) { false } ++ Seq(true))\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "icenet", "path": "icenet/src/main/scala/TestUtils.scala", "left_context": "package icenet\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.util.LatencyPipe\nimport scala.math.max\nimport IceNetConsts._\n\nclass PacketGen(lengths: Seq[Int], genData: Seq[BigInt]) extends Module {\n val io = IO(new Bundle {\n val start = Input(Bool())\n val finished = Output(Bool())\n val out = Decoupled(new StreamChannel(NET_IF_WIDTH))\n })\n\n val maxLength = lengths.reduce(max(_, _))\n val totalLength = lengths.reduce(_ + _)\n val lengthVec = VecInit(lengths.map(_.U))\n val dataVec = VecInit(genData.map(_.U(NET_IF_WIDTH.W)))\n\n require(totalLength == genData.size)\n\n val pktIdx = Reg(UInt(log2Ceil(lengths.size).W))\n val pktOffset = Reg(UInt(log2Ceil(maxLength).W))\n val dataIdx = Reg(UInt(log2Ceil(totalLength).W))\n val sending = RegInit(false.B)\n val started = RegInit(false.B)\n\n when (!sending && io.start) {\n started := true.B\n sending := true.B\n pktIdx := 0.U\n pktOffset := 0.U\n dataIdx := 0.U\n }\n\n when (io.out.fire) {\n dataIdx := dataIdx + 1.U\n pktOffset := pktOffset + 1.U\n when (io.out.bits.last) {\n pktIdx := pktIdx + 1.U\n pktOffset := 0.U\n when (pktIdx === (lengths.size - 1).U) {\n sending := false.B\n }\n }\n }\n\n io.out.valid := sending\n io.out.bits.data := dataVec(dataIdx)\n io.out.bits.keep := NET_FULL_KEEP\n io.out.bits.last := pktOffset === lengthVec(pktIdx) - 1.U\n io.finished := started && !sending\n}\n\nclass PacketCheck(\n checkData: Seq[BigInt],\n checkKeep: Seq[Int],\n checkLast: Seq[Boolean]) extends Module {\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new StreamChannel(NET_IF_WIDTH)))\n val finished = Output(Bool())\n })\n\n val checkDataVec = VecInit(checkData.map(_.U(NET_IF_WIDTH.W)))\n val checkKeepVec = VecInit(checkKeep.map(_.U(NET_IF_BYTES.W)))\n val checkLastVec = VecInit(checkLast.map(_.B))\n\n val (checkIdx, checkDone) = Counter(io.in.fire, checkDataVec.length)\n\n val finished = RegInit(false.B)\n\n io.in.ready := !finished\n io.finished := finished\n\n", "right_context": "\n def compareData(a: UInt, b: UInt, keep: UInt) = {\n val bitmask = FillInterleaved(8, keep)\n (a & bitmask) === (b & bitmask)\n }\n\n assert(!io.in.valid ||\n (compareData(io.in.bits.data, checkDataVec(checkIdx), io.in.bits.keep) &&\n io.in.bits.keep === checkKeepVec(checkIdx) &&\n io.in.bits.last === checkLastVec(checkIdx)),\n \"PacketCheck: input does not match\")\n\n}\n\nclass NetDelay(latency: Int) extends Module {\n val io = IO(new Bundle {\n val left = new StreamIO(NET_IF_WIDTH)\n val right = Flipped(new StreamIO(NET_IF_WIDTH))\n })\n\n io.left.out <> LatencyPipe(io.right.out, latency)\n io.right.in <> LatencyPipe(io.left.in, latency)\n}\n\nobject NetDelay {\n def apply(right: StreamIO, latency: Int): StreamIO = {\n val delay = Module(new NetDelay(latency))\n delay.io.right.out <> right.out\n right.in <> delay.io.right.in\n delay.io.left\n }\n}\n", "groundtruth": " when (checkDone) { finished := true.B }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "icenet", "path": "icenet/src/main/scala/TraceROM.scala", "left_context": "package icenet\n\nimport chisel3._\nimport chisel3.util._\nimport IceNetConsts.NET_IF_WIDTH\n\nclass TraceROM extends BlackBox with HasBlackBoxResource{\n", "right_context": " addResource(\"/csrc/TraceROM.cc\")\n}\n", "groundtruth": " val io = IO(new Bundle {\n val clock = Input(Clock())\n val reset = Input(Bool())\n val stream = Decoupled(new StreamChannel(NET_IF_WIDTH))\n val macAddr = Output(UInt(48.W))\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.9, "category_reason": "IO bundle definition"} {"task_id": "rjrouter", "path": "rjrouter/src/main/scala/gcd/DecoupledGCD.scala", "left_context": "// See README.md for license details.\n\npackage gcd\n\nimport chisel3._\nimport chisel3.util.Decoupled\n\nclass GcdInputBundle(val w: Int) extends Bundle {\n val value1 = UInt(w.W)\n val value2 = UInt(w.W)\n}\n\nclass GcdOutputBundle(val w: Int) extends Bundle {\n val value1 = UInt(w.W)\n val value2 = UInt(w.W)\n val gcd = UInt(w.W)\n}\n\n/**\n * Compute Gcd using subtraction method.\n * Subtracts the smaller from the larger until register y is zero.\n * value input register x is then the Gcd.\n * Unless first input is zero then the Gcd is y.\n * Can handle stalls on the producer or consumer side\n */\nclass DecoupledGcd(width: Int) extends MultiIOModule {\n val input = IO(Flipped(Decoupled(new GcdInputBundle(width))))\n val output = IO(Decoupled(new GcdOutputBundle(width)))\n\n val xInitial = Reg(UInt())\n val yInitial = Reg(UInt())\n val x = Reg(UInt())\n val y = Reg(UInt())\n val busy = RegInit(false.B)\n val resultValid = RegInit(false.B)\n\n input.ready := ! busy\n output.valid := resultValid\n output.bits := DontCare\n\n when(busy) {\n when(x > y) {\n x := x - y\n }.otherwise {\n y := y - x\n }\n when(x === 0.U || y === 0.U) {\n when(x === 0.U) {\n output.bits.gcd := y\n }.otherwise {\n output.bits.gcd := x\n }\n\n output.bits.value1 := xInitial\n", "right_context": " when(input.valid) {\n val bundle = input.deq()\n x := bundle.value1\n y := bundle.value2\n xInitial := bundle.value1\n yInitial := bundle.value2\n busy := true.B\n }\n }\n}\n", "groundtruth": " output.bits.value2 := yInitial\n resultValid := true.B\n\n when(output.ready && resultValid) {\n busy := false.B\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "rjrouter", "path": "rjrouter/src/main/scala/gcd/GCD.scala", "left_context": "// See README.md for license details.\n\npackage gcd\n\nimport chisel3._\n\n/**\n * Compute GCD using subtraction method.\n * Subtracts the smaller from the larger until register y is zero.\n * value in register x is then the GCD\n */\nclass GCD extends Module {\n val io = IO(new Bundle {\n val value1 = Input(UInt(16.W))\n val value2 = Input(UInt(16.W))\n val loadingValues = Input(Bool())\n val outputGCD = Output(UInt(16.W))\n val outputValid = Output(Bool())\n })\n\n val x = Reg(UInt())\n val y = Reg(UInt())\n\n", "right_context": " .otherwise { y := y - x }\n\n when(io.loadingValues) {\n x := io.value1\n y := io.value2\n }\n\n io.outputGCD := x\n io.outputValid := y === 0.U\n}\n", "groundtruth": " when(x > y) { x := x - y }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "rjrouter", "path": "rjrouter/src/main/scala/router/Bundles.scala", "left_context": "package router\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.BundleLiterals._\n\nclass RouterConfig(val nIfaces: Int = 4) extends Bundle {\n val iface = Vec(\n nIfaces,\n new Bundle {\n val mac = new MacAddr\n val ipv4 = new Ipv4Addr\n val mask = new Ipv4Addr\n }\n )\n}\n\nclass WrapBits(w: Int) extends Bundle {\n val bits = Bits(w.W)\n def ===(that: WrapBits) = bits === that.bits\n def =/=(that: WrapBits) = bits =/= that.bits\n}\n\nclass MacAddr extends WrapBits(48) {\n override def toPrintable: Printable = {\n asTypeOf(Vec(6, UInt(8.W))).reverse\n", "right_context": " .reduce((a, b) => a + \":\" + b)\n }\n}\n\nobject MacAddr {\n def apply(s: String) =\n (new MacAddr).Lit(_.bits -> (\"h\" + s.replace(\":\", \"\")).U)\n def apply(bytes: Array[Byte]) =\n (new MacAddr).Lit(_.bits -> (\"h\" + bytes.map(b => f\"$b%02x\").mkString).U)\n val BROADCAST = MacAddr(\"ff:ff:ff:ff:ff:ff\")\n}\n\nclass Ipv4Addr extends WrapBits(32) {\n override def toPrintable: Printable = {\n asTypeOf(Vec(4, UInt(8.W))).reverse\n .map(b => p\"$b\")\n .reduce((a, b) => a + \".\" + b)\n }\n def &(that: Ipv4Addr) = (bits & that.bits).asTypeOf(new Ipv4Addr)\n}\n\nobject Ipv4Addr {\n def apply(s: String) =\n (new Ipv4Addr).Lit(\n _.bits -> (\"h\" + s.split(\"\\\\.\").map(d => f\"${d.toInt}%02x\").mkString).U\n )\n val LOCALHOST = Ipv4Addr(\"127.0.0.1\")\n}\n\nclass EthType extends WrapBits(16) {}\n\nobject EthType {\n private def apply(s: Short) = (new EthType).Lit(_.bits -> s.U)\n val ARP = EthType(0x0806)\n val IPV4 = EthType(0x0800)\n}\n\nclass EtherHeader extends Bundle {\n val ethDst = new MacAddr\n val ethSrc = new MacAddr\n val ethType = new EthType\n val payload = Bits((34 * 8).W)\n}\n\nclass ArpHeader extends Bundle {\n val hardwareType = UInt(16.W)\n val protocolType = new EthType\n val hardwareSize = UInt(8.W)\n val protocolSize = UInt(8.W)\n val opcode = UInt(16.W)\n val srcMac = new MacAddr\n val srcIpv4 = new Ipv4Addr\n val dstMac = new MacAddr\n val dstIpv4 = new Ipv4Addr\n val payload = Bits((6 * 8).W)\n\n def isValid =\n hardwareType === 1.U &&\n protocolType === EthType.IPV4 &&\n hardwareSize === 6.U &&\n protocolSize === 4.U &&\n (opcode === 1.U || opcode === 2.U)\n\n def setTypeSize() {\n hardwareType := 1.U\n protocolType := EthType.IPV4\n hardwareSize := 6.U\n protocolSize := 4.U\n }\n}\n\nobject ArpOpcode {\n val Request = 1.U\n val Response = 2.U\n}\n\nclass Ipv4Header extends Bundle {\n val version = UInt(4.W)\n val headerLen = UInt(4.W)\n val dscp_ecn = UInt(8.W)\n val totalLen = UInt(16.W)\n val id = UInt(16.W)\n\n val flags_reserved = UInt(1.W)\n val dontFrag = UInt(1.W)\n val moreFrag = UInt(1.W)\n val fragOffset = UInt(13.W)\n\n val ttl = UInt(8.W)\n val protocol = UInt(8.W)\n val checksum = UInt(16.W)\n val src = new Ipv4Addr\n val dst = new Ipv4Addr\n\n val payload = Bits((14 * 8).W)\n\n def isValid =\n version === 4.U &&\n headerLen === 5.U\n\n def calcChecksum() = {\n val s1 = asTypeOf(Vec(17, UInt(16.W)))\n .slice(7, 17)\n .map(_.asTypeOf(UInt(32.W)))\n .reduce((a, b) => a + b)\n val s2 = s1.head(16) +& s1.tail(16)\n s2.head(1) + s2.tail(1)\n }\n\n def setChecksum(x: UInt) {\n checksum := x(x.getWidth - 1, 16) + x(15, 0)\n }\n}\n\nobject IpProtocol {\n val UDP = 17.U\n}\n\nclass UdpHeader extends Bundle {\n val srcPort = UInt(16.W)\n val dstPort = UInt(16.W)\n val length = UInt(16.W)\n val checksum = UInt(16.W)\n val payload = Bits((6 * 8).W)\n}\n", "groundtruth": " .map(b => p\"${Hexadecimal(b)}\")\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Loop-based Control", "confidence": 0.75, "category_reason": "Functional iteration"} {"task_id": "rjrouter", "path": "rjrouter/src/main/scala/router/pipeline/ArpPipeline.scala", "left_context": "package router.pipeline\n\nimport chisel3._\nimport chisel3.util._\nimport router._\nimport router.table._\n\n// Process ARP packet\nclass ArpPipeline extends Pipeline(hasArpModify = true) {\n\n when(io.in.valid && isFirstBeat) {\n val ethIn = io.in.bits.data.asTypeOf(new EtherHeader())\n val arpIn = ethIn.payload.asTypeOf(new ArpHeader())\n when(ethIn.ethType === EthType.ARP) {\n // by default drop this frame\n dropRest()\n\n when(arpIn.isValid) {\n val id = io.in.bits.id\n val iface = io.config.iface(id)\n val targetIsMe = arpIn.dstIpv4 === iface.ipv4\n // update ARP cache\n io.arpModify.get.op := Mux(targetIsMe, ArpOp.Insert, ArpOp.Update)\n", "right_context": " val arpOut = WireInit(arpIn)\n // construct reply\n ethOut.ethSrc := iface.mac\n ethOut.ethDst := ethIn.ethSrc\n arpOut.opcode := ArpOpcode.Response\n arpOut.srcMac := iface.mac\n arpOut.dstMac := ethIn.ethSrc\n arpOut.srcIpv4 := iface.ipv4\n arpOut.dstIpv4 := arpIn.srcIpv4\n arpOut.payload := 0.U\n // output reply\n val ARP_LEN = 42\n ethOut.payload := arpOut.asUInt\n out.valid := true.B\n out.bits.id := io.in.bits.id\n out.bits.data := ethOut.asUInt\n out.bits.keep := AXIStreamData.keep(ARP_LEN, 48)\n out.bits.last := true.B\n }\n }\n }\n }\n}\n", "groundtruth": " io.arpModify.get.ipv4 := arpIn.srcIpv4\n io.arpModify.get.mac := arpIn.srcMac\n\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.6, "category_reason": ":= in when/switch context"} {"task_id": "rjrouter", "path": "rjrouter/src/main/scala/router/pipeline/Ipv4Check.scala", "left_context": "package router.pipeline\n\nimport chisel3._\nimport chisel3.util._\nimport router._\n\n// Check IPv4 header and drop invalid frames.\nclass Ipv4Check extends Pipeline {\n\n when(io.in.valid && isFirstBeat) {\n val ethIn = io.in.bits.data.asTypeOf(new EtherHeader())\n val ipv4In = ethIn.payload.asTypeOf(new Ipv4Header())\n when(ethIn.ethType === EthType.IPV4) {\n // FIXME: checksum causes timing error!\n // when(!ipv4In.isValid || ipv4In.calcChecksum() =/= 0xFFFF.U) {\n", "right_context": " }\n }\n }\n}\n", "groundtruth": " when(!ipv4In.isValid) {\n dropRest()\n }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "rjrouter", "path": "rjrouter/src/main/scala/router/pipeline/Ipv4Forward.scala", "left_context": "package router.pipeline\n\nimport chisel3._\nimport chisel3.util._\nimport router._\n\n// Query forward table\n// update IPv4 header\n// set (iface, nextHop) at eth.ethDst.\nclass Ipv4Forward extends Pipeline {\n\n when(io.in.valid && isFirstBeat) {\n val ethIn = io.in.bits.data.asTypeOf(new EtherHeader())\n val ipv4In = ethIn.payload.asTypeOf(new Ipv4Header())\n when(ethIn.ethType === EthType.IPV4) {\n // TODO: query forward table\n\n // to me\n for (iface <- io.config.iface) {\n when(ipv4In.dst === iface.ipv4) {\n dropRest()\n }\n }\n\n // default route\n", "right_context": " for ((iface, i) <- io.config.iface.zipWithIndex) {\n when((ipv4In.dst & iface.mask) === (iface.ipv4 & iface.mask)) {\n outIface := i.U\n nextHop := ipv4In.dst\n }\n }\n\n // update IPv4 header\n val ipv4Out = WireInit(ipv4In)\n ipv4Out.ttl := ipv4In.ttl - 1.U\n ipv4Out.setChecksum(ipv4In.checksum +& 0x0100.U)\n\n // set nexthop at Eth.ethDst\n val ethDstOut = WireInit(ethIn.ethDst.asTypeOf(new NextHop))\n ethDstOut.iface := outIface\n ethDstOut.nextHop := nextHop\n\n // output\n val ethOut = WireInit(ethIn)\n ethOut.ethDst := ethDstOut.asTypeOf(new MacAddr)\n ethOut.payload := ipv4Out.asUInt\n out.bits.data := ethOut.asUInt\n }\n }\n}\n\nclass NextHop extends Bundle {\n val iface = UInt(16.W)\n val nextHop = new Ipv4Addr\n}\n", "groundtruth": " val outIface = WireInit(3.U)\n val nextHop = WireInit(Ipv4Addr(\"10.0.3.2\"))\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.85, "category_reason": "Wire declaration"} {"task_id": "rjrouter", "path": "rjrouter/src/main/scala/router/pipeline/Ipv4SetMac.scala", "left_context": "package router.pipeline\n\nimport chisel3._\nimport chisel3.util._\nimport router._\n\n// Query ARP cache and set ethernet header.\nclass Ipv4SetMac extends Pipeline(hasArpQuery = true) {\n\n when(io.in.valid && isFirstBeat) {\n val ethIn = io.in.bits.data.asTypeOf(new EtherHeader())\n val ipv4In = ethIn.payload.asTypeOf(new Ipv4Header())\n val nextHop = ethIn.ethDst.asTypeOf(new NextHop())\n when(ethIn.ethType === EthType.IPV4) {\n // debug print\n // printf(p\"$ipv4In checksum=${ipv4In.calcChecksum()}\\n\")\n // when(ipv4In.protocol === IpProtocol.UDP) {\n // val udpIn = ipv4In.payload.asTypeOf(new UdpHeader())\n // printf(p\" $udpIn\\n\")\n // }\n\n // query ARP cache\n io.arpQuery.get.ipv4 := nextHop.nextHop\n val dstMac = io.arpQuery.get.mac\n\n", "right_context": " out.bits.id := nextHop.iface\n out.bits.data := ethOut.asUInt\n }.otherwise {\n dropRest()\n // generate ARP request\n val ethOut = WireInit(ethIn)\n ethOut.ethSrc := iface.mac\n ethOut.ethDst := MacAddr.BROADCAST\n ethOut.ethType := EthType.ARP\n val arpOut = Wire(new ArpHeader)\n arpOut.setTypeSize()\n arpOut.opcode := ArpOpcode.Request\n arpOut.srcMac := iface.mac\n arpOut.dstMac := MacAddr.BROADCAST\n arpOut.srcIpv4 := iface.ipv4\n arpOut.dstIpv4 := nextHop.nextHop\n arpOut.payload := 0.U\n ethOut.payload := arpOut.asUInt\n\n // output\n out.valid := true.B\n out.bits.id := nextHop.iface\n out.bits.data := ethOut.asUInt\n out.bits.keep := AXIStreamData.keep(42, 48)\n out.bits.last := true.B\n }\n }\n }\n}\n", "groundtruth": " val iface = io.config.iface(nextHop.iface)\n when(dstMac.valid) {\n // update ethernet header\n val ethOut = WireInit(ethIn)\n ethOut.ethSrc := iface.mac\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "rjrouter", "path": "rjrouter/src/main/scala/router/pipeline/L2Filter.scala", "left_context": "package router.pipeline\n\nimport chisel3._\nimport router._\n\n// Filter out packets with the wrong destination MAC address or the wrong type\nclass L2Filter extends Pipeline {\n\n when(io.in.valid && isFirstBeat) {\n val ethIn = io.in.bits.data.asTypeOf(new EtherHeader())\n", "right_context": " when(!(dstIsMe || ethIn.ethDst === MacAddr.BROADCAST)) {\n dropRest()\n }\n when(!(ethIn.ethType === EthType.ARP || ethIn.ethType === EthType.IPV4)) {\n dropRest()\n }\n }\n}\n", "groundtruth": " val dstIsMe = ethIn.ethDst === io.config.iface(io.in.bits.id).mac\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.6, "category_reason": "val binding"} {"task_id": "rjrouter", "path": "rjrouter/src/main/scala/router/pipeline/Loopback.scala", "left_context": "package router.pipeline\n\nimport chisel3._\nimport chisel3.util._\nimport router._\n\n// Reverse src and dst MAC then send to the origin iface.\nclass LoopbackPipeline extends Pipeline {\n io.out <> io.in\n when(isFirstBeat) {\n", "right_context": "", "groundtruth": " val ethIn = io.in.bits.data.asTypeOf(new EtherHeader())\n // swap src and dst MAC\n val ethOut = WireDefault(ethIn)\n ethOut.ethSrc := ethIn.ethDst\n ethOut.ethDst := ethIn.ethSrc\n", "crossfile_context": "", "category": "Computation Block", "subcategory": "Type Casting and Conversion", "confidence": 0.8, "category_reason": "Type casting"} {"task_id": "rjrouter", "path": "rjrouter/src/main/scala/router/pipeline/Pipeline.scala", "left_context": "// Definations of pipeline\n\npackage router.pipeline\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.BundleLiterals._\nimport router._\nimport router.table.{ArpModify, ArpQuery}\n\n// The input and output of pipeline.\nclass AXIStreamData(val w: Int = 48 * 8) extends Bundle {\n private val wb = w / 8\n\n // transmited payload. only valid when both `valid` and `ready` is true.\n val data = Bits(w.W)\n // valid for each bytes in the last cycle. only valid when `last` is true.\n val keep = Bits(wb.W)\n // is the last cycle?\n val last = Bool()\n // iface ID of the packet\n val id = UInt(3.W)\n\n def litToBytes(): Seq[Byte] = {\n var bytes = data.litValue.toByteArray.toSeq\n bytes = if (bytes.length > wb) {\n bytes.slice(bytes.length - wb, bytes.length)\n } else if (bytes.length < wb) {\n", "right_context": " } else {\n bytes\n }\n if (last.litToBoolean) {\n bytes.slice(0, keep.litValue().bitCount)\n } else {\n bytes\n }\n }\n}\n\nobject AXIStreamData {\n // Generate keep literal\n def keep(n: Int, wb: Int) = (((BigInt(1) << n) - 1) << (wb - n)).U(wb.W)\n\n // Convert packet to AXIStream.\n def fromPacket(\n id: Int,\n packet: Array[Byte],\n width: Int\n ): Seq[AXIStreamData] = {\n val wb = width / 8\n packet\n .grouped(wb)\n .zipWithIndex\n .map {\n case (data, i) =>\n (new AXIStreamData(width)).Lit(\n _.data -> BigInt(\n Array(0.toByte) ++ data ++ Array.fill(wb - data.length) {\n 0.toByte\n }\n ).U(width.W),\n _.keep -> keep(data.length, wb),\n _.last -> ((i + 1) * wb >= packet.length).B,\n _.id -> id.U\n )\n }\n .toSeq\n }\n\n // Convert AXIStream to packet.\n def toPacket(\n datas: Array[AXIStreamData]\n ): (Int, Array[Byte]) = {\n val id = datas.head.id.litValue().toInt\n val data = datas.flatMap(_.litToBytes)\n (id, data)\n }\n}\n\nclass PipelineBundle extends Bundle {\n val in = Flipped(Decoupled(new AXIStreamData(48 * 8)))\n val out = Decoupled(new AXIStreamData(48 * 8))\n val config = Input(new RouterConfig())\n}\n\nclass Pipeline(\n hasArpQuery: Boolean = false,\n hasArpModify: Boolean = false\n) extends Module {\n val io = IO(new PipelineBundle {\n val arpQuery = if (hasArpQuery) Some(new ArpQuery) else None\n val arpModify = if (hasArpModify) Some(new ArpModify) else None\n })\n\n val isFirstBeat = RegInit(true.B)\n when(io.in.fire) {\n isFirstBeat := io.in.bits.last\n }\n\n // drop current and rest beat?\n private val drop = RegInit(false.B)\n // auto reset after last beat\n when(io.in.fire && io.in.bits.last) {\n drop := false.B\n }\n // for implementor\n def dropRest() {\n out.valid := false.B\n out.bits := DontCare\n drop := !io.in.bits.last\n }\n\n // output for implementor\n val out = Wire(Valid(new AXIStreamData))\n out.valid := io.in.valid\n out.bits := io.in.bits\n\n // default output\n io.in.ready := io.out.ready || drop\n io.out.valid := RegEnable(out.valid && !drop, false.B, io.out.ready)\n io.out.bits := RegEnable(out.bits, io.out.ready)\n if (hasArpModify) {\n io.arpModify.get.setNone()\n }\n if (hasArpQuery) {\n io.arpQuery.get.setNone()\n }\n}\n", "groundtruth": " Seq.fill(wb - bytes.length) { 0.toByte } ++ bytes\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "rjrouter", "path": "rjrouter/src/main/scala/router/pipeline/Router.scala", "left_context": "package router.pipeline\n\nimport chisel3._\nimport chisel3.util._\nimport router._\nimport router.table._\n\nclass Router extends Pipeline {\n // config\n val config = Wire(new RouterConfig())\n for ((iface, i) <- config.iface.zipWithIndex) {\n iface.ipv4 := Ipv4Addr(s\"10.0.$i.1\")\n iface.mask := Ipv4Addr(\"255.255.255.0\")\n iface.mac := MacAddr(s\"RJGG_$i\".map(_.toByte).toArray)\n }\n\n // the output of last pipeline\n var in = io.in\n def addPipeline[T <: Pipeline](m: T): T = {\n m.io.config <> config\n", "right_context": " in = m.io.out\n m\n }\n\n val l2filter = addPipeline(Module(new L2Filter))\n val arp = addPipeline(Module(new ArpPipeline))\n val ipv4Check = addPipeline(Module(new Ipv4Check))\n val ipv4Forward = addPipeline(Module(new Ipv4Forward))\n val ipv4SetMac = addPipeline(Module(new Ipv4SetMac))\n in <> io.out\n\n val arpCache = Module(new ArpCache)\n arp.io.arpModify.get <> arpCache.io.modify\n ipv4SetMac.io.arpQuery.get <> arpCache.io.query\n}\n\nobject Gen {\n def main(args: Array[String]): Unit = {\n chisel3.Driver.execute(args, () => new Router())\n }\n}\n", "groundtruth": " in <> m.io.in\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "rjrouter", "path": "rjrouter/src/main/scala/router/table/ArpCache.scala", "left_context": "package router.table\n\nimport chisel3._\nimport chisel3.util._\nimport router._\n\nclass ArpQuery extends Bundle {\n val ipv4 = Output(new Ipv4Addr)\n val mac = Input(Valid(new MacAddr))\n\n def setNone() = {\n ipv4 := Ipv4Addr(\"0.0.0.0\")\n }\n}\n\nclass ArpModify extends Bundle {\n val op = Output(UInt(3.W))\n val ipv4 = Output(new Ipv4Addr)\n val mac = Output(new MacAddr)\n\n def setNone() = {\n op := ArpOp.None\n ipv4 := DontCare\n mac := DontCare\n }\n}\n\nobject ArpOp {\n val None = 0.U\n val Insert = 1.U\n val Update = 2.U\n val Remove = 3.U\n val Clear = 4.U\n}\n\n// ARP Cache. Direct mapping.\nclass ArpCache(val SIZE_LOG2: Int = 4) extends Module {\n val io = IO(new Bundle {\n val query = Flipped(new ArpQuery)\n val modify = Flipped(new ArpModify)\n })\n val SIZE = 1 << SIZE_LOG2\n\n class ArpEntry extends Bundle {\n val ipv4 = new Ipv4Addr\n val mac = new MacAddr\n }\n val table = Mem(SIZE, Valid(new ArpEntry))\n\n def hashIndex(ipv4: Ipv4Addr) =\n ipv4\n .asTypeOf(Vec(4, UInt(8.W)))\n .reduce((a, b) => a ^ b)\n .apply(SIZE_LOG2 - 1, 0)\n\n // reset | clear\n when(reset.asBool || io.modify.op === ArpOp.Clear) {\n for (i <- 0 until SIZE) {\n table(i).valid := false.B\n }\n }\n // query\n val key = io.query.ipv4\n val entry = table(hashIndex(key))\n io.query.mac.valid := entry.valid && entry.bits.ipv4 === key\n io.query.mac.bits := entry.bits.mac\n\n val idx = hashIndex(io.modify.ipv4)\n when(io.modify.op === ArpOp.Insert) {\n table(idx).valid := true.B\n table(idx).bits.ipv4 := io.modify.ipv4\n table(idx).bits.mac := io.modify.mac\n }\n when(io.modify.op === ArpOp.Update) {\n when(table(idx).valid && table(idx).bits.ipv4 === io.modify.ipv4) {\n table(idx).bits.mac := io.modify.mac\n }\n }\n", "right_context": "", "groundtruth": " when(io.modify.op === ArpOp.Remove) {\n when(table(idx).bits.ipv4 === io.modify.ipv4) {\n table(idx).valid := false.B\n }\n }\n", "crossfile_context": "", "category": "Interface", "subcategory": "Handshake and Flow Control", "confidence": 0.8, "category_reason": "Ready/valid handshake assignment"} {"task_id": "rjrouter", "path": "rjrouter/src/test/scala/gcd/GCDMain.scala", "left_context": "// See README.md for license details.\n\npackage gcd\n\nimport chisel3._\n\n/**\n * This provides an alternate way to run tests, by executing then as a main\n * From sbt (Note: the test: prefix is because this main is under the test package hierarchy):\n * {{{\n * test:runMain gcd.GCDMain\n * }}}\n * To see all command line options use:\n * {{{\n * test:runMain gcd.GCDMain --help\n * }}}\n * To run with verilator:\n * {{{\n * test:runMain gcd.GCDMain --backend-name verilator\n * }}}\n * To run with verilator from your terminal shell use:\n * {{{\n * sbt 'test:runMain gcd.GCDMain --backend-name verilator'\n * }}}\n */\nobject GCDMain extends App {\n", "right_context": "/**\n * This provides a way to run the firrtl-interpreter REPL (or shell)\n * on the lowered firrtl generated by your circuit. You will be placed\n * in an interactive shell. This can be very helpful as a debugging\n * technique. Type help to see a list of commands.\n *\n * To run from sbt\n * {{{\n * test:runMain gcd.GCDRepl\n * }}}\n * To run from sbt and see the half a zillion options try\n * {{{\n * test:runMain gcd.GCDRepl --help\n * }}}\n */\nobject GCDRepl extends App {\n iotesters.Driver.executeFirrtlRepl(args, () => new GCD)\n}", "groundtruth": " iotesters.Driver.execute(args, () => new GCD) {\n c => new GCDUnitTester(c)\n }\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "rjrouter", "path": "rjrouter/src/test/scala/gcd/GCDUnitTest.scala", "left_context": "// See README.md for license details.\n\npackage gcd\n\nimport java.io.File\n\nimport chisel3.iotesters\nimport chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester}\n\nclass GCDUnitTester(c: GCD) extends PeekPokeTester(c) {\n /**\n * compute the gcd and the number of steps it should take to do it\n *\n * @param a positive integer\n * @param b positive integer\n * @return the GCD of a and b\n */\n def computeGcd(a: Int, b: Int): (Int, Int) = {\n var x = a\n var y = b\n var depth = 1\n while(y > 0 ) {\n if (x > y) {\n x -= y\n }\n else {\n y -= x\n }\n depth += 1\n }\n (x, depth)\n }\n\n private val gcd = c\n\n for(i <- 1 to 40 by 3) {\n for (j <- 1 to 40 by 7) {\n poke(gcd.io.value1, i)\n poke(gcd.io.value2, j)\n poke(gcd.io.loadingValues, 1)\n step(1)\n poke(gcd.io.loadingValues, 0)\n\n val (expected_gcd, steps) = computeGcd(i, j)\n\n step(steps - 1) // -1 is because we step(1) already to toggle the enable\n expect(gcd.io.outputGCD, expected_gcd)\n expect(gcd.io.outputValid, 1)\n }\n }\n}\n\n/**\n * This is a trivial example of how to run this Specification\n * From within sbt use:\n * {{{\n * testOnly gcd.GCDTester\n * }}}\n * From a terminal shell use:\n * {{{\n * sbt 'testOnly gcd.GCDTester'\n * }}}\n */\nclass GCDTester extends ChiselFlatSpec {\n", "right_context": " }\n for ( backendName <- backendNames ) {\n \"GCD\" should s\"calculate proper greatest common denominator (with $backendName)\" in {\n Driver(() => new GCD, backendName) {\n c => new GCDUnitTester(c)\n } should be (true)\n }\n }\n\n \"Basic test using Driver.execute\" should \"be used as an alternative way to run specification\" in {\n iotesters.Driver.execute(Array(), () => new GCD) {\n c => new GCDUnitTester(c)\n } should be (true)\n }\n\n if(backendNames.contains(\"verilator\")) {\n \"using --backend-name verilator\" should \"be an alternative way to run using verilator\" in {\n iotesters.Driver.execute(Array(\"--backend-name\", \"verilator\"), () => new GCD) {\n c => new GCDUnitTester(c)\n } should be(true)\n }\n }\n\n \"running with --is-verbose\" should \"show more about what's going on in your tester\" in {\n iotesters.Driver.execute(Array(\"--is-verbose\"), () => new GCD) {\n c => new GCDUnitTester(c)\n } should be(true)\n }\n\n /**\n * By default verilator backend produces vcd file, and firrtl and treadle backends do not.\n * Following examples show you how to turn on vcd for firrtl and treadle and how to turn it off for verilator\n */\n\n \"running with --generate-vcd-output on\" should \"create a vcd file from your test\" in {\n iotesters.Driver.execute(\n Array(\"--generate-vcd-output\", \"on\", \"--target-dir\", \"test_run_dir/make_a_vcd\", \"--top-name\", \"make_a_vcd\"),\n () => new GCD\n ) {\n\n c => new GCDUnitTester(c)\n } should be(true)\n\n new File(\"test_run_dir/make_a_vcd/GCD.vcd\").exists should be (true)\n }\n\n \"running with --generate-vcd-output off\" should \"not create a vcd file from your test\" in {\n iotesters.Driver.execute(\n Array(\"--generate-vcd-output\", \"off\", \"--target-dir\", \"test_run_dir/make_no_vcd\", \"--top-name\", \"make_no_vcd\",\n \"--backend-name\", \"verilator\"),\n () => new GCD\n ) {\n\n c => new GCDUnitTester(c)\n } should be(true)\n\n new File(\"test_run_dir/make_no_vcd/make_a_vcd.vcd\").exists should be (false)\n\n }\n\n}\n", "groundtruth": " private val backendNames = if(firrtl.FileUtils.isCommandAvailable(Seq(\"verilator\", \"--version\"))) {\n Array(\"firrtl\", \"verilator\")\n }\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.6, "category_reason": "val binding"} {"task_id": "rjrouter", "path": "rjrouter/src/test/scala/gcd/GcdTesters2.scala", "left_context": "// See README.md for license details.\n\npackage gcd\n\nimport chisel3._\nimport chisel3.tester._\nimport org.scalatest.FreeSpec\nimport chisel3.experimental.BundleLiterals._\n\n/**\n * This is a trivial example of how to run this Specification\n * From within sbt use:\n * {{{\n * testOnly gcd.GcdDecoupledTester\n * }}}\n * From a terminal shell use:\n * {{{\n * sbt 'testOnly gcd.GcdDecoupledTester'\n * }}}\n */\n//scalastyle:off magic.number\nclass GcdTesters2 extends FreeSpec with ChiselScalatestTester {\n\n \"Gcd should calculate proper greatest common denominator\" in {\n test(new DecoupledGcd(16)) { dut =>\n dut.input.initSource()\n", "right_context": "\n val testValues = for { x <- 0 to 10; y <- 0 to 10} yield (x, y)\n val inputSeq = testValues.map { case (x, y) => (new GcdInputBundle(16)).Lit(_.value1 -> x.U, _.value2 -> y.U) }\n val resultSeq = testValues.map { case (x, y) =>\n (new GcdOutputBundle(16)).Lit(_.value1 -> x.U, _.value2 -> y.U, _.gcd -> BigInt(x).gcd(BigInt(y)).U)\n }\n\n fork {\n // push inputs into the calculator, stall for 11 cycles one third of the way\n val (seq1, seq2) = inputSeq.splitAt(resultSeq.length / 3)\n dut.input.enqueueSeq(seq1)\n dut.clock.step(11)\n dut.input.enqueueSeq(seq2)\n }.fork {\n // retrieve computations from the calculator, stall for 10 cycles one half of the way\n val (seq1, seq2) = resultSeq.splitAt(resultSeq.length / 2)\n dut.output.expectDequeueSeq(seq1)\n dut.clock.step(10)\n dut.output.expectDequeueSeq(seq2)\n }.join()\n\n }\n }\n}\n", "groundtruth": " dut.input.setSourceClock(dut.clock)\n dut.output.initSink()\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "rjrouter", "path": "rjrouter/src/test/scala/router/pipeline/Pipeline.scala", "left_context": "package router.pipeline\n\nimport org.pcap4j.core._;\nimport java.io.File\nimport java.io.EOFException\nimport java.nio.ByteBuffer\nimport chisel3._\nimport chisel3.tester._\nimport org.scalatest.FreeSpec\nimport chisel3.util.Decoupled\nimport scala.collection.mutable.ArrayBuffer\nimport router._\n\nclass RouterTester extends PipelineTester {\n \"Router generate output\" in {\n test(new Router()) { dut =>\n initAndInput(dut, \"src/test/resources/test_in.pcap\")\n .fork {\n dumpOutput(dut, \"src/test/resources/test_out.pcap\")\n }\n .join()\n }\n }\n}\n\nclass LoopbackTester extends PipelineTester {\n \"Loopback generate output\" in {\n test(new LoopbackPipeline()) { dut =>\n initAndInput(dut, \"src/test/resources/test_in.pcap\")\n .fork {\n dumpOutput(dut, \"src/test/resources/loopback_out.pcap\")\n }\n .join()\n }\n }\n}\n\nclass ArpPipelineTester extends PipelineTester {\n \"ArpPipeline should works\" in {\n test(new ArpPipeline()) { dut =>\n initAndInput(dut, \"src/test/resources/arp_in.pcap\")\n // .fork {\n // dumpOutput(dut, \"src/test/resources/arp_out.pcap\")\n // }\n .fork {\n val output = loadAxisFromPcap(\"src/test/resources/arp_ans.pcap\")\n dut.io.out.expectDequeueSeq(output)\n }\n .join()\n }\n }\n}\n\nclass NopTester extends PipelineTester {\n \"Nop should works\" in {\n test(new Pipeline {\n io.out <> io.in\n }) { dut =>\n initAndInput(dut, \"src/test/resources/test_in.pcap\")\n .fork {\n val output = loadAxisFromPcap(\"src/test/resources/test_in.pcap\")\n dut.io.out.expectDequeueSeq(output)\n }\n .join()\n }\n }\n}\n\nclass PipelineTester extends FreeSpec with ChiselScalatestTester {\n\n def initAndInput(dut: Pipeline, filePath: String) = {\n dut.io.in.initSource().setSourceClock(dut.clock)\n dut.io.out.initSink().setSinkClock(dut.clock)\n for ((iface, i) <- dut.io.config.iface.zipWithIndex) {\n iface.ipv4.poke(Ipv4Addr(s\"10.0.$i.1\"))\n iface.mask.poke(Ipv4Addr(\"255.255.255.0\"))\n iface.mac.poke(MacAddr(s\"RJGG_$i\".map(_.toByte).toArray))\n }\n fork {\n val input = loadAxisFromPcap(filePath)\n for (elt <- input) {\n dut.io.in.enqueue(elt)\n dut.clock.step(5)\n }\n }\n }\n\n def dumpOutput(dut: Pipeline, filePath: String) = {\n val buf = ArrayBuffer[Byte]()\n val packets = ArrayBuffer[(Int, Array[Byte])]()\n var end = false\n while (!end) {\n dut.io.out.ready.poke(true.B)\n fork\n .withRegion(Monitor) {\n // wait for valid\n var count = 0\n val timeout = 100\n while (\n dut.io.out.valid.peek().litToBoolean == false && count < timeout\n ) {\n dut.clock.step(1)\n count += 1\n }\n if (count == timeout) {\n end = true\n } else {\n val bits = dut.io.out.bits.peek()\n val id = bits.id.litValue.toInt\n val last = bits.last.litToBoolean\n val data = bits.litToBytes\n buf ++= data\n if (last) {\n // Console.println(id, buf.map { b => f\"$b%02x\" }.mkString(\" \"))\n packets += ((id, buf.toArray[Byte]))\n buf.clear()\n }\n }\n }\n .joinAndStep(dut.clock)\n dut.io.out.ready.poke(false.B)\n dut.clock.step(5)\n }\n storePackets(filePath, packets)\n }\n\n def loadAxisFromPcap(filePath: String): Seq[AXIStreamData] =\n loadPackets(filePath).flatMap {\n case (id, data) => AXIStreamData.fromPacket(id, data, 8 * 48)\n }\n\n def loadPackets(filePath: String): Seq[(Int, Array[Byte])] = {\n val handle = Pcaps.openOffline(filePath)\n val packets = ArrayBuffer[(Int, Array[Byte])]()\n try {\n while (true) {\n val packet = handle.getNextRawPacketEx()\n // extract Vlan ID\n val id = ByteBuffer\n .allocate(2)\n .put(packet.slice(14, 16))\n .flip\n .getShort() - 1000\n val data = packet.slice(0, 12) ++ packet.splitAt(16)._2\n packets += ((id, data))\n }\n } catch {\n", "right_context": " }\n handle.close()\n packets\n }\n\n def storePackets(filePath: String, packets: Seq[(Int, Array[Byte])]) {\n val handle =\n Pcaps.openOffline(\"src/test/resources/test_in.pcap\").dumpOpen(filePath)\n for ((id, data) <- packets) {\n val (head, tail) = data.splitAt(12)\n val buf = ByteBuffer\n .allocate(data.length + 4)\n .put(head)\n .putShort(0x8100.toShort)\n .putShort((1000 + id).toShort)\n .put(tail)\n handle.dumpRaw(buf.array())\n }\n handle.close()\n }\n}\n", "groundtruth": " case e: EOFException => {}\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "rjrouter", "path": "rjrouter/src/test/scala/router/table/ArpCache.scala", "left_context": "package router.table\n\nimport chisel3._\nimport chisel3.tester._\nimport org.scalatest._\nimport router._\n\nclass ArpCacheTester extends FlatSpec with ChiselScalatestTester {\n behavior of \"ArpCache\"\n\n it should \"works\" in {\n test(new ArpCache(2)) { dut =>\n val query = dut.io.query\n val modify = dut.io.modify\n\n def insert(key: Ipv4Addr, value: MacAddr) = {\n modify.op.poke(ArpOp.Insert)\n modify.ipv4.poke(key)\n modify.mac.poke(value)\n dut.clock.step(1)\n }\n\n def remove(key: Ipv4Addr) = {\n modify.op.poke(ArpOp.Remove)\n modify.ipv4.poke(key)\n dut.clock.step(1)\n }\n\n def clear() = {\n modify.op.poke(ArpOp.Clear)\n dut.clock.step(1)\n }\n\n def check(key: Ipv4Addr, value: Option[MacAddr]) = {\n query.ipv4.poke(key)\n query.mac.valid.expect(value.isDefined.B)\n if (value.isDefined) {\n query.mac.bits.expect(value.get)\n }\n }\n\n // Insert\n insert(Ipv4Addr(\"192.168.1.1\"), MacAddr(\"00:00:00:00:00:01\"))\n check(Ipv4Addr(\"192.168.1.1\"), Some(MacAddr(\"00:00:00:00:00:01\")))\n\n // Insert override value\n insert(Ipv4Addr(\"192.168.1.1\"), MacAddr(\"ff:ff:ff:ff:ff:ff\"))\n check(Ipv4Addr(\"192.168.1.1\"), Some(MacAddr(\"ff:ff:ff:ff:ff:ff\")))\n\n // Insert override key\n insert(Ipv4Addr(\"192.168.0.0\"), MacAddr(\"00:00:00:00:00:00\"))\n", "right_context": " // Remove same hash\n remove(Ipv4Addr(\"192.168.1.1\"))\n check(Ipv4Addr(\"192.168.0.0\"), Some(MacAddr(\"00:00:00:00:00:00\")))\n\n // Remove\n remove(Ipv4Addr(\"192.168.0.0\"))\n check(Ipv4Addr(\"192.168.0.0\"), None)\n\n // Insert to full\n for (i <- 1 until 5) {\n insert(Ipv4Addr(s\"192.168.1.$i\"), MacAddr(s\"00:00:00:00:00:0$i\"))\n }\n for (i <- 1 until 5) {\n check(Ipv4Addr(s\"192.168.1.$i\"), Some(MacAddr(s\"00:00:00:00:00:0$i\")))\n }\n\n // Clear\n clear()\n for (i <- 1 until 6) {\n check(Ipv4Addr(s\"192.168.1.$i\"), None)\n }\n }\n }\n}\n", "groundtruth": " check(Ipv4Addr(\"192.168.0.0\"), Some(MacAddr(\"00:00:00:00:00:00\")))\n check(Ipv4Addr(\"192.168.1.1\"), None)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "FPGA-Application-Development-and-Simulation", "path": "FPGA-Application-Development-and-Simulation/chisel/src/main/scala/gen_verilog.scala", "left_context": "/*\n * MIT License\n *\n * Copyright (c) 2025 loykylewong (loywong@gmail.com)\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n */\n\nimport chisel3.RawModule\nimport circt.stage.{ChiselStage, FirtoolOption}\nimport chisel3.stage.ChiselGeneratorAnnotation\n\nimport java.nio.file.{Files, Paths}\nimport scala.util.matching.Regex\nimport loywong._\nimport loywong.examples._\n\nobject gen_verilog extends App {\n \n /**\n * Top level module(s) specified here.\n */\n val genModules = Array[() => RawModule](\n () => new test_fp,\n () => new encoder_example(),\n () => new decoder_example(),\n () => new shift_reg_example,\n () => new delay_chain_example,\n () => new counter_example(),\n () => new counter_oneshot_example(),\n () => new counter_max_example(),\n () => new count_down_example,\n () => new counterHrMinSec,\n () => new accumulator_example,\n () => new spram_example,\n () => new spram_with_init_example,\n () => new spramrf_example,\n () => new spramrf_with_init_example,\n () => new spramwf_example,\n () => new spramra_example,\n () => new sdpram_example,\n () => new sdpramrf_example,\n () => new sdpramwf_example,\n () => new sdpramra_example,\n () => new dpram_example,\n () => new sdcram_example,\n () => new dcram_example,\n () => new scfifo2_example,\n () => new anti_metastable_example,\n () => new edge2en_example,\n () => new ccd_trigger_example,\n () => new ccd_counter_example,\n () => new dcfifo_example,\n () => new str_frs_example,\n () => new str_birs_example,\n () => new hscomb1_example,\n () => new hscomb2_example,\n () => new str_dwc_example,\n () => new str_keep_remover_example,\n () => new str_dcfifo_example,\n () => new str_stage_example_0(),\n () => new str_stage_example_1(),\n () => new str_stage_example_2(),\n () => new Axi4LiteToLocalMemoryMapWrapper(6, 4),\n () => new cordic_example\n )\n \n /**\n * Directory where generated verilog/systemverilog file placed,\n * default using value predefined in build.sbt.\n */\n val targetDir: String = ProjectInfo.BuildInfo.targetVerilogDir\n \n /**\n * Whether generate \"old school\" verilog for compatible with old hdl\n * synthesis tools. It's useful for directly \"Add Module ...\" in Vivado\n * block design.\n */\n val genOldSchoolVerilog: Boolean = true\n \n /**\n * Whether generate split files for each module.\n */\n val genSplitFiles: Boolean = false\n \n println(\"================================\")\n println(s\"Project Info: ${ProjectInfo.BuildInfo.toString}\")\n println(\"--------------------------------\")\n println(\"Pre-processing...\")\n \n private val chiselStageArgs = Array(\n \"--target-dir\", targetDir,\n \"--target\", if (genOldSchoolVerilog) \"verilog\" else \"systemverilog\",\n", "right_context": " )\n \n private val chiselStageAnnotations =\n if (genOldSchoolVerilog)\n Seq(\n // ChiselGeneratorAnnotation(genModule),\n FirtoolOption(\"-strip-debug-info\"),\n FirtoolOption(\"--disable-all-randomization\"),\n FirtoolOption(\"--lowering-options=\" +\n \"noAlwaysComb,\" +\n \"disallowLocalVariables,\" +\n \"disallowPortDeclSharing,\" +\n \"disallowPackedArrays,\" +\n \"disallowPackedStructAssignments\"),\n FirtoolOption(\"--verilog\"),\n FirtoolOption(\"-format=fir\")\n )\n else\n Seq(\n // ChiselGeneratorAnnotation(genModule),\n FirtoolOption(\"-strip-debug-info\"),\n FirtoolOption(\"--disable-all-randomization\"),\n FirtoolOption(\"--lowering-options=\" +\n \"disallowLocalVariables,\" +\n \"disallowPortDeclSharing,\" +\n \"explicitBitcast\"),\n FirtoolOption(\"-format=fir\")\n )\n \n println(\"Done.\")\n println(\"--------------------------------\")\n println(\"Emitting Verilog...\")\n \n genModules.zipWithIndex.foreach {\n case (genModule, i) => {\n (new ChiselStage).execute(\n chiselStageArgs,\n Seq(ChiselGeneratorAnnotation(genModule)) ++ chiselStageAnnotations\n )\n println(s\"${1+i}/${genModules.length} done.\")\n }\n }\n \n println(\"Done.\")\n println(\"--------------------------------\")\n println(\"Post-processing...\")\n \n /**\n * In which file(s), chisel style AXI4, AXI4-Lite and AXI4-Stream IO ports\n * name will be renamed to AMBA & Vivado IP conventions.\n */\n val filesToBeRenamed = List(\n \"str_frs_example\",\n \"Axi4LiteToLocalMemoryMapWrapper_64x32\"\n ).map(targetDir + \"/\" + _)\n RenamePorts2AmbaConventions(false, filesToBeRenamed: _*)\n \n println(\"Done.\")\n println(\"================================\")\n}\n\nobject RenamePorts2AmbaConventions {\n /**\n * rename ports to AMBA conventions,\n * see `RenamePorts2AmbaConventions.md` for details.\n * @param deleteOriginal whether delete original file(s)\n * @param files in these files (file names with path without\n * extension), all eligible identifiers will be\n * renamed\n */\n def apply(deleteOriginal: Boolean, files: String*): Unit = {\n \n val axi4sPattern: Regex = \"\"\"([sm][^\\W_]*(_[^\\W_]+)*_axis[^\\W_]*(_[^\\W_]+)*)_(t?(valid|ready)|[^\\W_]+_t?(last|data|user|id|keep|strb))\\b\"\"\".r\n val axi4sReplace: String = \"$1_t$5$6\"\n val axi4Pattern: Regex = \"\"\"([sm][^\\W_]*(_[^\\W_]+)*_(axi|axi[^\\W_s][^\\W_]*)(_[^\\W_]+)*)_(aw|w|b|ar|r)(_[^\\W_]+)?_t?(ready|valid|addr|prot|data|strb|resp|id|len|size|burst|lock|cache|qos|region|user)\\b\"\"\".r\n val axi4Replace: String = \"$1_$5$7\"\n files.foreach {\n file => {\n val ext: String =\n if (Files.exists(Paths.get(file + \".v\"))) {\n \".v\"\n }\n else if (Files.exists(Paths.get(file + \".sv\"))) {\n \".sv\"\n }\n else {\n \"\"\n }\n if (ext.isEmpty) {\n println(s\"\\u001b[33m[warning]\\u001b[0m in Rename2AmbaConventions: file \\\"${file}.v\\\" or \\\"${file}.sv\\\" not found.\")\n }\n else {\n var source = Files.readString(Paths.get(file + ext))\n source = axi4sPattern.replaceAllIn(source, axi4sReplace)\n source = axi4Pattern.replaceAllIn(source, axi4Replace)\n Files.writeString(Paths.get(file + \"_renamed\" + ext), source)\n println(s\"\\u001b[32m[info]\\u001b[0m File \\\"${file}_renamed${ext}\\\" created.\")\n if (deleteOriginal) {\n Files.delete(Paths.get(file + ext))\n println(s\"\\u001b[32m[info]\\u001b[0m File \\\"${file}${ext}\\\" deleted.\")\n }\n }\n }\n }\n }\n}\n", "groundtruth": " if (genSplitFiles) \"--split-verilog\" else \"\"\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "FPGA-Application-Development-and-Simulation", "path": "FPGA-Application-Development-and-Simulation/chisel/src/main/scala/loywong/accumulator.scala", "left_context": "/*\n * MIT License\n *\n * Copyright (c) 2025 loykylewong (loywong@gmail.com)\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n */\n\npackage loywong\n\nimport chisel3._\nimport chisel3.util._\n\nclass Accumulator(modu: Int) extends Module {\n require(modu > 1)\n val dw = log2Up(modu)\n val idw = dw + 2\n val io = IO(new Bundle {\n val en = Input(Bool())\n val step = Input(SInt(dw.W))\n val accu = Output(UInt(dw.W))\n val wrapUp = Output(Bool())\n val wrapDown = Output(Bool())\n })\n \n val accu = RegInit(0.U(dw.W))\n val nextRaw = Wire(SInt(idw.W))\n val wrapUp = WireDefault(nextRaw >= modu.S)\n val wrapDown = WireDefault(nextRaw < 0.S)\n val nextWrap = Wire(UInt(dw.W))\n nextRaw := (0.U(1.W) ## accu).asSInt +& io.step\n nextWrap := MuxCase(nextRaw(dw - 1, 0), Seq(\n wrapUp -> (nextRaw - modu.S)(dw - 1, 0),\n wrapDown -> (nextRaw + modu.S)(dw - 1, 0)\n ))\n", "right_context": " io.wrapDown := wrapDown && io.en\n}\n\npackage examples {\n class accumulator_example extends Module {\n val modu = 100\n val io = IO(new Bundle {\n val en = Input(Bool())\n val step = Input(SInt(7.W))\n val accu = Output(UInt(7.W))\n val wrapUp = Output(Bool())\n val wrapDown = Output(Bool())\n })\n val theAccu = Module(new Accumulator(modu))\n io <> theAccu.io\n \n }\n}", "groundtruth": " when(io.en) {\n accu := nextWrap\n }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "FPGA-Application-Development-and-Simulation", "path": "FPGA-Application-Development-and-Simulation/chisel/src/main/scala/loywong/axi4lite_to_localmm.scala", "left_context": "/*\n * MIT License\n *\n * Copyright (c) 2025 loykylewong (loywong@gmail.com)\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n */\n\npackage loywong\n\nimport chisel3._\nimport chisel3.util._\n\n/**\n * Local Memory Map I.F. with:\n * - address : the register address, not the byte address\n * - write : write enable signal for issuing a write transaction\n * - writeData: data to be written to the address when write asserted\n * - writeByteEn : byte enable for writeData in a write transaction\n * - read : read enable signal for issuing a read transaction\n * - readData : data read from the address when read asserted\n * @param addrWidth width of the address\n * @param dataBytes number of bytes of data\n * @note\n * - In write transaction, `address`, `writeData` and `writeByteEn` must be\n * active in the same cycle when write asserted, that is:\n * - Write Wait = 0\n * - Write Latency = 0\n * - In read transaction, `address` must be active in the same cycle when read\n * asserted, and readData must be valid in the very next cycle, that is:\n * - Read Wait = 0\n * - Read Latency = 1\n */\nclass LocalMemoryMapIO(addrWidth: Int, dataBytes: Int = 4) extends Bundle {\n val address = Output(UInt(addrWidth.W))\n val write = Output(Bool())\n val writeData = Output(UInt((dataBytes*8).W))\n val writeByteEn = Output(UInt(dataBytes.W))\n val read = Output(Bool())\n val readData = Input(UInt((dataBytes*8).W))\n}\n\nobject LocalMemoryMap {\n /**\n * Create a instance of Local Memory Map Master IO\n * @param addrWidth Width of register word address\n * @param dataBytes Number of data bytes\n * @return Instance created\n */\n def MasterIO(addrWidth: Int, dataBytes: Int = 4) = {\n new LocalMemoryMapIO(addrWidth, dataBytes)\n }\n\n /**\n * Create a instance of Local Memory Map Slave IO\n * @param addrWidth Width of register word address\n * @param dataBytes Number of data bytes\n * @return Instance created\n */\n def SlaveIO(addrWidth: Int, dataBytes: Int = 4) = {\n Flipped(new LocalMemoryMapIO(addrWidth, dataBytes))\n }\n}\n\nclass Axi4LiteIO(addrWidth: Int, dataBytes: Int = 4) extends Bundle {\n class AWBits extends Bundle {\n val addr = UInt(addrWidth.W)\n val prot = UInt(3.W)\n }\n class WBits extends Bundle {\n val data = UInt((dataBytes*8).W)\n val strb = UInt(dataBytes.W)\n }\n class BBits extends Bundle {\n val resp = UInt(2.W)\n }\n class ARBits extends Bundle {\n val addr = UInt(addrWidth.W)\n val prot = UInt(3.W)\n }\n class RBits extends Bundle {\n val data = UInt((dataBytes*8).W)\n val resp = UInt(2.W)\n }\n val aw = Irrevocable(new AWBits)\n val w = Irrevocable(new WBits)\n val b = Flipped(Irrevocable(new BBits))\n val ar = Irrevocable(new ARBits)\n val r = Flipped(Irrevocable(new RBits))\n}\n\nobject Axi4Lite {\n /**\n * Create a instance of AXI4-Lite Master IO\n * @param addrWidth Width of address (byte address)\n * @param dataBytes Number of data bytes\n * @return Instance created\n */\n def MasterIO(addrWidth: Int, dataBytes: Int = 4) = {\n new Axi4LiteIO(addrWidth, dataBytes)\n }\n /**\n * Create a instance of AXI4-Lite Slave IO\n * @param addrWidth Width of address (byte address)\n * @param dataBytes Number of data bytes\n * @return Instance created\n */\n def SlaveIO(addrWidth: Int, dataBytes: Int = 4) = {\n Flipped(new Axi4LiteIO(addrWidth, dataBytes))\n }\n}\n\n/**\n * Represent a hardware AXI4-Lite Slave to local memory map master bridge\n * module.\n * @param regAddrWidth Width of register word address (not the byte address)\n * @param regDataBytes Number of bytes of tdata in AXI4-Lite and local memory\n * map I.F.\n */\nclass Axi4LiteToLocalMemoryMap(regAddrWidth: Int, regDataBytes: Int = 4) extends Module {\n require(regAddrWidth >= 0)\n require(isPow2(regDataBytes))\n\n override def desiredName: String = super.desiredName +\n", "right_context": "\n val byteAddrExt = log2Ceil(regDataBytes)\n val byteAddrWidth = regAddrWidth + byteAddrExt\n\n val io = IO(new Bundle {\n val axi4l = Axi4Lite.SlaveIO(byteAddrWidth, regDataBytes)\n val lmm = LocalMemoryMap.MasterIO(regAddrWidth, regDataBytes)\n })\n\n val regs_wr = WireDefault(Bool(), io.axi4l.w.fire)\n val regs_rd = WireDefault(Bool(), io.axi4l.ar.fire)\n\n // ==== aw channel ====\n io.axi4l.aw.ready := true.B // always ready\n val waddr_reg = RegInit(0.U(regAddrWidth.W))\n when(io.axi4l.aw.valid) {\n waddr_reg := io.axi4l.aw.bits.addr >> byteAddrExt\n }\n // ==== w channel ====\n val wready = RegInit(false.B)\n when(io.axi4l.aw.valid) {\n wready := true.B\n }.elsewhen(io.axi4l.w.fire) {\n wready := false.B\n }\n io.axi4l.w.ready := wready\n // ==== b channel ====\n io.axi4l.b.bits.resp := \"b00\".U(2.W) // always OK\n val bvalid = RegInit(false.B)\n when(io.axi4l.w.fire) {\n bvalid := true.B\n }.elsewhen(io.axi4l.b.fire) {\n bvalid := false.B\n }\n io.axi4l.b.valid := bvalid\n // ==== ar channel ====\n val raddr_reg = RegInit(0.U(regAddrWidth.W))\n when(io.axi4l.ar.valid) {\n raddr_reg := io.axi4l.ar.bits.addr >> byteAddrExt\n }\n val arready = RegInit(false.B)\n when(io.axi4l.ar.valid && !io.axi4l.ar.ready) {\n arready := true.B\n }.elsewhen(io.axi4l.ar.fire) {\n arready := false.B\n }\n io.axi4l.ar.ready := arready\n // ==== r channel ====\n io.axi4l.r.bits.resp := 0.U(2.W) // always OK\n val rvalid = RegInit(false.B)\n when(io.axi4l.ar.fire) {\n rvalid := true.B\n }.elsewhen(io.axi4l.r.fire) {\n rvalid := false.B\n }\n io.axi4l.r.valid := rvalid\n // ==== lmm ====\n io.lmm.address := Mux(regs_wr, waddr_reg, raddr_reg)\n io.lmm.write := regs_wr\n io.lmm.writeData := io.axi4l.w.bits.data\n io.lmm.writeByteEn := io.axi4l.w.bits.strb\n io.lmm.read := regs_rd\n io.axi4l.r.bits.data := io.lmm.readData\n}\n\nclass Axi4LiteToLocalMemoryMapWrapper(regAddrWidth: Int, regDataBytes: Int = 4) extends RawModule {\n require(regAddrWidth >= 0)\n require(isPow2(regDataBytes))\n\n override def desiredName: String = super.desiredName +\n s\"_${1 << regAddrWidth}x${regDataBytes * 8}\"\n\n val byteAddrExt = log2Ceil(regDataBytes)\n val byteAddrWidth = regAddrWidth + byteAddrExt\n\n val aclk = IO(Input(Clock()))\n val areset_n = IO(Input(Bool()))\n val axi4l = IO(Axi4Lite.SlaveIO(byteAddrWidth, regDataBytes)).suggestName(\"s_axi4l\")\n val lmm = IO(LocalMemoryMap.MasterIO(regAddrWidth, regDataBytes))\n\n val axi4l_to_lmm = withClockAndReset(aclk, !areset_n) {\n Module(new Axi4LiteToLocalMemoryMap(regAddrWidth, regDataBytes))\n }\n\n axi4l <> axi4l_to_lmm.io.axi4l\n lmm <> axi4l_to_lmm.io.lmm\n}\n", "groundtruth": " s\"_${1 << regAddrWidth}x${regDataBytes * 8}\"\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.55, "category_reason": "Code near IO/Bundle"} {"task_id": "FPGA-Application-Development-and-Simulation", "path": "FPGA-Application-Development-and-Simulation/chisel/src/main/scala/loywong/cordic.scala", "left_context": "/*\n * MIT License\n *\n * Copyright (c) 2025 loykylewong (loywong@gmail.com)\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n */\n\npackage loywong\n\nimport chisel3._\nimport chisel3.util._\nimport loywong.util._\n\nobject CordicCoordinates extends Enumeration {\n val Circular = Value(1)\n val Linear = Value(0)\n val Hyperbolic = Value(-1)\n}\n\nobject CordicMode extends Enumeration {\n val Rotation = Value(0)\n val Vectoring = Value(1)\n}\n\nclass CordicIOStrBits(xyDW: Int, zDW: Int) extends StrBits {\n val x = SInt(xyDW.W)\n val y = SInt(xyDW.W)\n val z = SInt(zDW.W)\n}\n\n/**\n * Represent a hardware stream stage implemented one iteration step of CORDIC.\n * @param gen generator of CORDIC IO bits, must be inherited from\n * `CordicIOStrBits`\n * @param stgIdx index of iteration step\n * @param zFW fraction width of `z` (angle)\n * @param coordinates coordinate system\n * @param mode rotation or vectoring mode\n * @tparam T type of CORDIC IO bits\n * @note Do NOT use this class.\n */\nclass CordicStage[T <: CordicIOStrBits](gen: T, stgIdx: Int, zFW: Int,\n coordinates: CordicCoordinates.Value,\n mode: CordicMode.Value)\n extends StrActiveStage(gen, gen)() {\n\n val xyDW = gen.x.getWidth\n val zDW = gen.z.getWidth\n\n coordinates match {\n case CordicCoordinates.Circular =>\n require(stgIdx >= 0)\n case CordicCoordinates.Hyperbolic =>\n require(stgIdx >= 1)\n case _ => { }\n }\n\n def atanh(x: Double): Double = {\n if (x.abs >= 1) Double.NaN\n else 0.5 * math.log((1 + x) / (1 - x))\n }\n\n // ---- parameters ----\n val deltaZDouble: Double = coordinates match {\n // for circular, map angle from [-pi, pi) to [-1, 1) (Qx.FW)\n case CordicCoordinates.Circular => math.atan(math.pow(2.0, -stgIdx)) / math.Pi\n case CordicCoordinates.Linear => math.pow(2.0, -stgIdx)\n case CordicCoordinates.Hyperbolic => atanh(math.pow(2.0, -stgIdx))\n }\n val deltaZ = Math.round(deltaZDouble * math.pow(2.0, zFW)).asSInt\n\n val sigma: Bool = mode match {\n case CordicMode.Rotation => !io.us.bits.z.signBit\n case CordicMode.Vectoring => io.us.bits.y.signBit\n }\n\n // ==== override `ds_bits_next` in `StrActiveStage` ====\n private def shiftRight(x: SInt, n: Int): Bits = {\n if (n >= 0) x >> n\n else x << -n\n }\n // ---- x ----\n coordinates match {\n case CordicCoordinates.Linear =>\n ds_bits_next.x := io.us.bits.x\n case CordicCoordinates.Circular =>\n when(sigma) {\n ds_bits_next.x := io.us.bits.x - shiftRight(io.us.bits.y, stgIdx).asSInt\n }.otherwise {\n ds_bits_next.x := io.us.bits.x + shiftRight(io.us.bits.y, stgIdx).asSInt\n }\n case CordicCoordinates.Hyperbolic =>\n when(sigma) {\n ds_bits_next.x := io.us.bits.x + shiftRight(io.us.bits.y, stgIdx).asSInt\n }.otherwise {\n ds_bits_next.x := io.us.bits.x - shiftRight(io.us.bits.y, stgIdx).asSInt\n }\n }\n // ---- y ----\n when(sigma) {\n ds_bits_next.y := io.us.bits.y + shiftRight(io.us.bits.x, stgIdx).asSInt\n }.otherwise {\n ds_bits_next.y := io.us.bits.y - shiftRight(io.us.bits.x, stgIdx).asSInt\n }\n // ---- z ----\n when(sigma) {\n ds_bits_next.z := io.us.bits.z - deltaZ\n }.otherwise {\n ds_bits_next.z := io.us.bits.z + deltaZ\n }\n}\n\nclass CordicCircularQuadrantTrans[T <: CordicIOStrBits](gen: T, mode: CordicMode.Value)\n extends StrActiveStage(gen, gen)() {\n\n val xyDW = gen.x.getWidth\n val zDW = gen.z.getWidth\n\n val zInQuad2or3 = io.us.bits.z(zDW - 1, zDW - 2).xorR\n val xInQuad2or3 = io.us.bits.x(xyDW - 1)\n\n mode match {\n case CordicMode.Rotation => {\n when(zInQuad2or3) {\n ds_bits_next.x := -io.us.bits.x\n ds_bits_next.y := -io.us.bits.y\n ds_bits_next.z := io.us.bits.z ^ (1.U << (zDW - 1)).asSInt\n }.otherwise {\n ds_bits_next.x := io.us.bits.x\n ds_bits_next.y := io.us.bits.y\n ds_bits_next.z := io.us.bits.z\n }\n }\n case CordicMode.Vectoring => {\n when(xInQuad2or3) {\n ds_bits_next.x := -io.us.bits.x\n ds_bits_next.y := -io.us.bits.y\n ds_bits_next.z := io.us.bits.z ^ (1.U << (zDW - 1)).asSInt\n }.otherwise {\n ds_bits_next.x := io.us.bits.x\n ds_bits_next.y := io.us.bits.y\n ds_bits_next.z := io.us.bits.z\n }\n }\n }\n}\n\nclass CordicLinearVectoringQuadrantTrans[T <: CordicIOStrBits](gen: T)\n extends StrActiveStage(gen, gen)() {\n\n val xyDW = gen.x.getWidth\n\n val xInQuad2or3 = io.us.bits.x(xyDW - 1)\n\n when(xInQuad2or3) {\n ds_bits_next.x := -io.us.bits.x\n ds_bits_next.y := -io.us.bits.y\n ds_bits_next.z := io.us.bits.z\n }.otherwise {\n ds_bits_next.x := io.us.bits.x\n ds_bits_next.y := io.us.bits.y\n ds_bits_next.z := io.us.bits.z\n }\n}\n\nclass CordicHyperbolicVectoringQuadrantTrans[T <: CordicIOStrBits](gen: T)\n extends StrActiveStage(gen, gen)() {\n\n val xyDW = gen.x.getWidth\n\n val xInQuad2or3 = io.us.bits.x(xyDW - 1)\n\n when(xInQuad2or3) {\n ds_bits_next.x := -io.us.bits.x\n ds_bits_next.y := -io.us.bits.y\n ds_bits_next.z := io.us.bits.z\n }.otherwise {\n ds_bits_next.x := io.us.bits.x\n ds_bits_next.y := io.us.bits.y\n ds_bits_next.z := io.us.bits.z\n }\n}\n\n/**\n * Represent a hardware module of CORDIC algorithm\n *\n * @param gen generator of generator of CORDIC IO bits, must be inherited from\n * `CordicIOStrBits`\n * @param nStages number of iterations (pipe stages)\n * @param xyFW fraction width of x and y\n * @param zFW fraction width of z (angle)\n * @param coordinates coordinate system\n * @param mode rotation or vectoring mode\n * @param linStgStart stage index start for linear coordinates,\n * - in Rotation mode, range of abs(z) < 2^(1 - linStgStart)^,\n * - in Vectoring mode, range of abs(y/x) < 2^(1 - linStgStart)^,\n * - x & y widths must make range of abs(x or y) covers\n * max{x_in, y_in} * 2^-linStgStart^, x_out, y_out}.\n * @tparam T type of CORDIC IO bits\n * @note\n * - it's the user's responsibility to make sure the data width and fraction\n * width match the CORDIC's input and output value domain.\n */\nclass Cordic[T <: CordicIOStrBits](gen: T, nStages: Int, xyFW: Int, zFW: Int,\n coordinates: CordicCoordinates.Value,\n mode: CordicMode.Value, linStgStart: Int = 0\n ) extends Module {\n\n val xyDW = gen.x.getWidth\n val zDW = gen.z.getWidth\n\n val nIterStages = nStages\n val nTotalStages = nIterStages + { coordinates match {\n case CordicCoordinates.Circular => 2 // quadTrans & scaleComp\n case CordicCoordinates.Hyperbolic => mode match {\n case CordicMode.Rotation => 1 // scaleComp\n case CordicMode.Vectoring => 2 // quadTrans & scaleComp\n }\n case CordicCoordinates.Linear => mode match {\n case CordicMode.Rotation => 0\n case CordicMode.Vectoring => 1 // quadTrans\n }\n }}\n\n if (coordinates == CordicCoordinates.Circular)\n require(zDW == zFW + 1)\n else if (coordinates == CordicCoordinates.Linear)\n require(linStgStart < zDW - zFW - 1)\n\n private def hyperbolicIter(i: Int): Int = {\n if (i <= 4) i // repeat 4\n else if (i <= 14) i - 1 // repeat 13\n else i - 2\n }\n\n val stageIdxSeq = coordinates match {\n case CordicCoordinates.Circular =>\n (0 until nStages).toList\n case CordicCoordinates.Hyperbolic =>\n (1 to nStages).map(i => hyperbolicIter(i))\n case CordicCoordinates.Linear =>\n (linStgStart until linStgStart + nStages).toList\n }\n\n val scale = coordinates match {\n case CordicCoordinates.Circular =>\n stageIdxSeq.map(i => math.sqrt(1.0 + math.pow(2.0, -2.0 * i))).foldLeft(1.0)(_ * _)\n case CordicCoordinates.Hyperbolic =>\n stageIdxSeq.map(i => math.sqrt(1.0 - math.pow(2.0, -2.0 * i))).foldLeft(1.0)(_ * _)\n case CordicCoordinates.Linear => 1.0\n }\n\n val io = IO(new Bundle {\n val us = Flipped(Irrevocable(gen))\n val ds = Irrevocable(gen)\n })\n\n class ScaleCompStage extends StrActiveStage(gen, gen)() {\n val scaleComp =\n if (coordinates == CordicCoordinates.Circular)\n (1.0 / scale).toFixPoint(xyDW.W, xyFW)\n else\n (1.0 / scale).toFixPoint((xyDW + 1).W, xyFW)\n ds_bits_next.x := (this.io.us.bits.x.asFixPoint(xyFW) * scaleComp).truncate(xyFW).getBits\n ds_bits_next.y := (this.io.us.bits.y.asFixPoint(xyFW) * scaleComp).truncate(xyFW).getBits\n }\n\n val scaleCompStage =\n if(coordinates != CordicCoordinates.Linear)\n Some(Module(new ScaleCompStage))\n else\n None\n\n val cordicStages = stageIdxSeq.map(s => {\n Module(new CordicStage(gen, s, zFW, coordinates, mode))\n })\n\n for (i <- 1 until cordicStages.length) {\n cordicStages(i - 1).io.ds <> cordicStages(i).io.us\n }\n\n coordinates match {\n case CordicCoordinates.Circular => {\n val quadTrans = Module(new CordicCircularQuadrantTrans(gen, mode))\n io.us <> quadTrans.io.us\n quadTrans.io.ds <> scaleCompStage.get.io.us\n scaleCompStage.get.io.ds <> cordicStages.head.io.us\n cordicStages.last.io.ds <> io.ds\n }\n case CordicCoordinates.Linear => {\n mode match {\n case CordicMode.Rotation => {\n io.us <> cordicStages.head.io.us\n }\n case CordicMode.Vectoring => {\n val quadTrans = Module(new CordicLinearVectoringQuadrantTrans(gen))\n io.us <> quadTrans.io.us\n quadTrans.io.ds <> cordicStages.head.io.us\n }\n }\n cordicStages.last.io.ds <> io.ds\n }\n case CordicCoordinates.Hyperbolic => {\n mode match {\n case CordicMode.Rotation => {\n io.us <> cordicStages.head.io.us\n }\n case CordicMode.Vectoring => {\n val quadTrans = Module(new CordicHyperbolicVectoringQuadrantTrans(gen))\n io.us <> quadTrans.io.us\n quadTrans.io.ds <> cordicStages.head.io.us\n }\n }\n cordicStages.last.io.ds <> scaleCompStage.get.io.us\n scaleCompStage.get.io.ds <> io.ds\n }\n", "right_context": " }\n}\n\npackage examples {\n class cordic_example extends Module {\n val xyDW = 12\n val xyFW = 10\n val zDW = 12\n val zFW = 11\n class CordicBits extends CordicIOStrBits(xyDW, zDW) {\n val sideband = UInt(8.W)\n }\n val io = IO(new Bundle {\n val us = Flipped(Irrevocable(new CordicBits))\n val ds = Irrevocable(new CordicBits)\n })\n val cordic = Module(new Cordic(new CordicBits,\n 8, xyFW, zFW,\n CordicCoordinates.Circular,\n CordicMode.Rotation\n ))\n io.us <> cordic.io.us\n cordic.io.ds <> io.ds\n }\n}\n", "groundtruth": " case _ => { }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.7, "category_reason": "Scala case/match expression"} {"task_id": "FPGA-Application-Development-and-Simulation", "path": "FPGA-Application-Development-and-Simulation/chisel/src/main/scala/loywong/counter.scala", "left_context": "/*\n * MIT License\n *\n * Copyright (c) 2025 loykylewong (loywong@gmail.com)\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n */\n\npackage loywong\n\nimport chisel3._\nimport chisel3.util._\n\npackage examples {\n class counter_example(m: Int = 256) extends Module {\n val io = IO(new Bundle {\n val en = Input(Bool())\n val out = Output(UInt(log2Ceil(m).W))\n val co = Output(Bool())\n })\n // use chisel3.util.Counter !\n val (cnt, co) = Counter(io.en, m)\n io.out := cnt\n io.co := co\n }\n}\n\nobject CounterOneShot {\n def apply(m:BigInt, en:Bool, continue:Bool = false.B): (UInt, Bool) = {\n val w = log2Ceil(m)\n val cnt = RegInit(0.U(w.W))\n val wrap = cnt === (m-1).U\n when(en) {\n when(wrap) {\n cnt := Mux(continue, 0.U(w.W), cnt)\n }.otherwise {\n cnt := cnt + 1.U(w.W)\n }\n }\n (cnt, en && wrap && continue)\n }\n}\n\npackage examples {\n class counter_oneshot_example extends Module {\n val io = FlatIO(new Bundle {\n val en = Input(Bool())\n val dly_rst = Output(Bool())\n })\n val (cnt, _) = CounterOneShot(100, io.en)\n io.dly_rst := cnt === 99.U\n }\n}\n\nobject CounterMax {\n def apply(width:Int, max:UInt, en:Bool): (UInt, Bool) = {\n val cnt = RegInit(0.U(width.W))\n val wrap = cnt === max\n", "right_context": " }\n }\n (cnt, en && wrap)\n }\n}\n\nobject CounterMaxOneShot {\n def apply(width:Int, max:UInt, en:Bool, continue:Bool = false.B): (UInt, Bool) = {\n val cnt = RegInit(0.U(width.W))\n val wrap = cnt === max\n when(en) {\n when(wrap) {\n cnt := Mux(continue, 0.U(width.W), cnt)\n }.otherwise {\n cnt := cnt + 1.U(width.W)\n }\n }\n (cnt, en && wrap && continue)\n }\n}\n\npackage examples {\n class counter_max_example(width: Int = 8) extends Module {\n val io = IO(new Bundle {\n val max = Input(UInt(width.W))\n val en = Input(Bool())\n val out = Output(UInt(width.W))\n val co = Output(Bool())\n })\n val (out, co) = CounterMax(width, io.max, io.en)\n io.out := out\n io.co := co\n }\n\n class count_down_example extends Module {\n val io = FlatIO(new Bundle {\n val dly_rst = Output(Bool())\n })\n\n val en = Wire(Bool())\n val (cnt, wrap) = {\n Counter((99 to 0 by -1), en)\n }\n en := cnt =/= 0.U\n\n io.dly_rst := !en\n }\n\n class counterHrMinSec extends Module {\n val io = FlatIO(new Bundle {\n val en = Input(Bool())\n val sec = Output(UInt(6.W))\n val min = Output(UInt(6.W))\n val hr = Output(UInt(5.W))\n val en_day = Output(Bool())\n })\n val (_, en_sec) = Counter(io.en, 100e6.toInt)\n val (sec, en_min) = Counter(en_sec, 60)\n val (min, en_hr) = Counter(en_min, 60)\n val (hr, en_day) = Counter(en_hr, 24)\n io.sec := sec\n io.min := min\n io.hr := hr\n io.en_day := en_day\n\n }\n}\n", "groundtruth": " when(en) {\n when(wrap) {\n cnt := 0.U(width.W)\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "FPGA-Application-Development-and-Simulation", "path": "FPGA-Application-Development-and-Simulation/chisel/src/main/scala/loywong/cross_clock_domain.scala", "left_context": "/*\n * MIT License\n *\n * Copyright (c) 2025 loykylewong (loywong@gmail.com)\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n */\n\npackage loywong\n\nimport chisel3._\nimport chisel3.util.RegEnable\n// import chisel3.util._\n\n/**\n * Utility class for anti-metastable by using 2 or more synchronize stages\n * (flip-flops).\n * @param gen Generator of data\n * @param nStages Number of synchronize stages\n * @param init Function for generating reset value(s), default generate\n * all 0s, set to None for generating no reset logic.\n * @tparam T Type of data\n * @note You may prefer to use the homonymous factory object.\n * @example {{{\n * val ams_1 = new AntiMetastable(UInt(8.W))(\n * Some(()=>{ 255.U(8.W) }))\n * // Or using the factory\n * // val ams_1 = AntiMetastable(UInt(8.W))(\n * // Some(()=>{ 255.U(8.W) }))\n * io.some_out := ams_1.input(io.some_in)\n * }}}\n */\nclass AntiMetastable[T <: Data](gen: T, nStages: Int = 2)\n (init: Option[()=>T] = Some(()=>0.U.asTypeOf(gen))) {\n require(nStages >=1, \"In AntiMetastable, nStages must be >= 1.\")\n val stgs = init match {\n case Some(f) => RegInit(VecInit(Seq.fill(nStages)(f())))\n case None => Reg(Vec(nStages, gen))\n }\n\n /**\n * Insert synchronize stages between input and output.\n * @param data Input data signal\n * @tparam T Type of data\n * @return Output after the synchronize stages\n */\n def input[T <: Data](data: T) = {\n stgs.zipWithIndex.foreach{ case(stg, i) => {\n if(i == 0) stg := data\n else stg := stgs(i - 1)\n }}\n stgs(nStages - 1)\n }\n}\n\nobject AntiMetastable {\n /**\n * Instantiate a utility class for anti-metastable by using 2 or more\n * synchronize stages (flip-flops).\n * @param gen Generator of data\n * @param init Initialization function for resetting data\n * @param nStages Number of synchronize stages\n * @tparam T Type of data\n * @note You may prefer to use the homonymous factory object.\n * @example {{{\n * val ams_1 = AntiMetastable(UInt(8.W))(\n * Some(()=>{ 255.U(8.W) }))\n * io.some_out := ams_1.input(io.some_in)\n * }}}\n */\n def apply[T <: Data](gen: T, nStages: Int = 2)\n (init: Option[()=>T] = Some(()=>0.U.asTypeOf(gen))) = {\n new AntiMetastable(gen, nStages)(init)\n }\n\n /**\n * Utility method for inserting a 2-synchronize-stage anti-metastable circuit.\n * @param data Input data signal\n * @param init Function to generate init value, generate all 0s by\n * default, generate no reset logic if set to None\n * @tparam T Type of data\n * @return Output data after 2 synchronize stages\n * @note No reset in inserted stages.\n */\n def _2ff[T <: Data](data: T)\n (init: Option[()=>T] = Some(()=>0.U.asTypeOf(data))) = {\n val stgs = init match {\n case None => Reg(Vec(2, data.cloneType))\n case Some(f) => RegInit(VecInit(Seq.fill(2)(f())))\n }\n stgs(0) := data\n stgs(1) := stgs(0)\n stgs(1)\n }\n\n /**\n * Utility method for inserting a 3-synchronize-stage anti-metastable circuit.\n * @param data Input data signal\n * @param init Function to generate init value, generate all 0s by\n * default, generate no reset logic if set to None\n * @tparam T Type of data\n * @return Output data after 3 synchronize stages\n * @note No reset in inserted stages.\n */\n def _3ff[T <: Data](data: T)\n (init: Option[()=>T] = Some(()=>0.U.asTypeOf(data))) = {\n val stgs = init match {\n case None => Reg(Vec(3, data.cloneType))\n case Some(f) => RegInit(VecInit(Seq.fill(3)(f())))\n }\n stgs(0) := data\n stgs(1) := stgs(0)\n stgs(2) := stgs(1)\n stgs(2)\n }\n}\n\nobject Edge2En {\n /**\n * Convert edges of \"slow\" signal to single cycle enable.\n * @param in Input signal\n * @param initOnes Reset synchronize stages to 1s if true\n * @param nStages Number of synchronize stages\n * @return (rising, falling, output)\n * rising : enable signal for rising edge\n * falling: enable signal for falling edge\n * output : input signal via synchronize stages\n * @example {{{\n * (xx_rising, _, _) := Edge2En(xx)\n * }}}\n */\n def apply(in:Bool, initOnes:Boolean = false, nStages:Int = 2): (Bool, Bool, Bool) = {\n require(nStages >= 0, \"In Edge2En, nStages must be >= 0.\")\n val dly_init = if(initOnes) {\n // Fill(nStages + 1, 1.U(1.W))\n ~0.U((nStages + 1).W)\n } else {\n 0.U((nStages + 1).W)\n }\n val dly = RegInit(dly_init.cloneType, dly_init)\n val rising = WireInit(false.B)\n val falling = WireInit(false.B)\n if(nStages == 0) {\n dly(0) := in\n rising := \"b01\".U === dly(0) ## in\n falling := \"b10\".U === dly(0) ## in\n }\n else {\n dly := (dly << 1) | in.asUInt\n rising := \"b01\".U === dly(nStages) ## dly(nStages - 1)\n falling := \"b10\".U === dly(nStages) ## dly(nStages - 1)\n }\n (rising, falling, dly(nStages))\n }\n}\n\n/*\n/**\n * Utility class for cross clock domain trigger by toggle flip-flop and\n * synchronize stages.\n * @param fromClock Clock of the clock domain in which trigger signal sent\n * @param toClock Clock of the clock domain in which trigger signal received\n * @param fromReset Reset in `fromClock` domain\n * @param toReset Reset in `toClock` domain\n * @param nStages Number of synchronize stages for anti-metastable between\n * clock domains\n * @note You may prefer to use the homonymous factory object.\n * @example {{{\n * val ccd_trig = new CcdTrigger(clk_a, clk_b)()\n * withClock(clk_a) { when(xx_a) { ccd_trig.trigger() } }\n * withClock(clk_b) { xx_b := ccd_trig.out() }\n * // Or, use the factory\n * // val ccd_trig = CcdTrigger(clk_a, clk_b)()\n * // withClock(clk_a) { when(xx_a) { ccd_trig.trigger() } }\n * // withClock(clk_b) { xx_b := ccd_trig.out() }\n * }}}\n */\nclass CcdTriggerInline(fromClock: Clock, toClock: Clock,\n fromReset: Bool, toReset: Bool)\n (nStages: Int = 2) {\n require(nStages >=1, \"nStages must be >= 1 in CcdTrigger\")\n val toggle_a = withClockAndReset(fromClock, fromReset) {\n RegInit(false.B)\n }\n val toggle_b = withClockAndReset(toClock, toReset) {\n RegInit(0.U((nStages+1).W))\n }\n withClock(toClock) {\n toggle_b := (toggle_b << 1) | toggle_a\n }\n\n /**\n * Send a trigger signal, use in `fromClock` domain.\n */\n def trigger(en: Bool = true.B): Unit = {\n withClock(fromClock) {\n when(en) {\n toggle_a := !toggle_a\n }\n }\n }\n\n /**\n * Assigned to a wire for receiving trigger signal, use in `toClock`\n * domain. The wire assigned will be high for one clock period due to each\n * trigger signal sent from `fromClock`\n * domain.\n * @return Signal indicates trigger received.\n */\n def out(): Bool = {\n toggle_b(nStages, nStages - 1).xorR\n }\n}\n\nobject CcdTriggerInline {\n /**\n * Create an instance of cross clock domain trigger.\n * @param fromClock Clock of the clock domain in which trigger signal sent\n * @param toClock Clock of the clock domain in which trigger signal received\n * @param fromReset Reset in `fromClock` domain, optional, default false\n * @param toReset Reset in `toClock` domain, optional, default false\n * @param nStages Number of synchronize stages for anti-metastable between\n * clock domains\n * @return Instance created\n * @note You may prefer to use the homonymous factory object\n * @example {{{\n * val ccd_trig = CcdTrigger(clk_a, clk_b)()\n * withClock(clk_a) { when(xx_a) { ccd_trig.trigger() } }\n * withClock(clk_b) { xx_b := ccd_trig.out() }\n * }}}\n */\n def apply(fromClock: Clock, toClock: Clock,\n fromReset: Bool, toReset: Bool)\n (nStages: Int = 2): CcdTrigger = {\n new CcdTriggerInline(fromClock, toClock, fromReset, toReset)(nStages)\n }\n}\n */\n\n/**\n * Represent a hardware Cross Clock Domain Trigger module.\n * @param nStages Number of synchronize stages for anti-metastable\n */\nclass CcdTrigger(nStages: Int = 2) extends RawModule {\n val io = IO(new Bundle {\n val fromClock = Input(Clock())\n val toClock = Input(Clock())\n val fromReset = Input(Bool())\n val toReset = Input(Bool())\n val triggerIn = Input(Bool())\n val triggerOut = Output(Bool())\n })\n require(nStages >=1, \"In CcdTrigger, nStages must be >= 1.\")\n\n val toggle_a = withClockAndReset(io.fromClock, io.fromReset) {\n RegInit(false.B)\n }\n val toggle_b = withClockAndReset(io.toClock, io.toReset) {\n RegInit(0.U((nStages+1).W))\n }\n withClock(io.toClock) {\n toggle_b := (toggle_b << 1) | toggle_a\n }\n\n withClock(io.fromClock) {\n when(io.triggerIn) {\n toggle_a := !toggle_a\n }\n }\n io.triggerOut := toggle_b(nStages, nStages - 1).xorR\n}\n\nobject CcdTrigger {\n /**\n * Create an instance of class CcdTrigger and make connections.\n * @param fromClock Clock of clock domain in which trigger signal sent\n * @param toClock Clock of clock domain in which trigger signal received\n * @param fromReset Reset of `fromClock` domain\n * @param toReset Reset of `toClock` domain\n * @param triggerIn Trigger signal input\n * @param nStages Number of synchronize stages for anti-metastable\n * @return Trigger signal output\n * @example {{{\n * val trig_out = CcdTrigger(clk_a, clk_b, rst_a, rst_b)(\n * trig_in)\n * }}}\n */\n def apply(fromClock: Clock, toClock: Clock,\n fromReset: Bool, toReset: Bool)(triggerIn: Bool, nStages: Int = 2): Bool = {\n val ccd_trigger = Module(new CcdTrigger(nStages))\n ccd_trigger.io.fromClock := fromClock\n ccd_trigger.io.toClock := toClock\n ccd_trigger.io.fromReset := fromReset\n ccd_trigger.io.toReset := toReset\n ccd_trigger.io.triggerIn := triggerIn\n ccd_trigger.io.triggerOut\n }\n}\n\n/*\n/**\n * Utility class for transferring counting status between clock domains.\n * @param fromClock Clock of the clock domain in which status transferred\n * @param toClock Clock of the clock domain in which status received\n * @param fromReset Reset in `fromClock` domain\n * @param toReset Reset in `toClock` domain\n * @param width Width in bits of the counter\n */\nclass CcdCounter(fromClock: Clock, toClock: Clock,\n fromReset: Bool, toReset: Bool)\n (width: Int){\n require(width >= 1, \"In CcdCounter, width must be >= 1.\")\n\n private val cnt_a = withClockAndReset(fromClock, fromReset) {\n RegInit(0.U(width.W))\n }\n private val gray = withClockAndReset(fromClock, fromReset) {\n RegInit(0.U(width.W))\n }\n private val gray_sync = withClockAndReset(toClock, toReset) {\n val gray_ams = AntiMetastable(UInt(width.W))()\n gray_ams.input(gray)\n }\n private val bin_next = cnt_a + 1.U(width.W)\n private val gray_next = if(width > 1) bin_next ^ (bin_next >> 1).asUInt\n else bin_next\n\n /**\n * Increase the counter by one step, use in `fromClock` domain.\n */\n def inc(en: Bool = true.B): Unit = {\n withClock(fromClock) {\n when(en) {\n cnt_a := bin_next\n gray := gray_next\n }\n }\n }\n\n /**\n * Assign to wire for getting the counter value, use in `fromClock` domain.\n * @return Counter value in `fromClock` domain.\n */\n def cnt_from(): UInt = {\n cnt_a\n }\n\n /**\n * Assign to wire for getting the counter value, use in `toClock` domain.\n * @return Counter value in `toClock` domain.\n */\n def cnt_to(): UInt = {\n (0 until width).foldLeft(0.U) { (acc, i) => {\n acc | ((gray_sync >> i).xorR << i)\n }}\n }\n}\n\nobject CcdCounter {\n /**\n * Create an instance of Cross Clock Domain Counter.\n * @param fromClock Clock of the clock domain in which status transferred\n * @param toClock Clock of the clock domain in which status received\n * @param fromReset Reset in `fromClock` domain\n * @param toReset Reset in `toClock` domain\n * @param width Width in bits of the counter\n * @return The instance created\n */\n def apply(fromClock: Clock, toClock: Clock,\n fromReset: Bool, toReset: Bool)\n (width: Int) = {\n new CcdCounter(fromClock, toClock, fromReset, toReset)(width)\n }\n}\n*/\n\n/**\n * Represent a hardware Cross Clock Domain Counter module.\n * @param width Width in bits of the counter\n */\nclass CcdCounterModule(width: Int) extends RawModule {\n require(width >= 1, \"In CcdCounterModule, width must be >= 1.\")\n override def desiredName: String = super.desiredName + s\"_${width}b\"\n\n val io = IO(new Bundle {\n val fromClock = Input(Clock())\n val toClock = Input(Clock())\n val fromReset = Input(Bool())\n val toReset = Input(Bool())\n val inc_from = Input(Bool())\n val cnt_from = Output(UInt(width.W))\n val cnt_to = Output(UInt(width.W))\n })\n\n private val cnt_from = withClockAndReset(io.fromClock, io.fromReset) {\n RegInit(0.U(width.W))\n }\n private val gray = withClockAndReset(io.fromClock, io.fromReset) {\n RegInit(0.U(width.W))\n }\n private val gray_sync = withClockAndReset(io.toClock, io.toReset) {\n AntiMetastable._2ff(gray)()\n }\n private val bin_next = cnt_from + 1.U(width.W)\n private val gray_next =\n if(width > 1) bin_next ^ (bin_next >> 1).asUInt\n else bin_next\n\n withClock(io.fromClock) {\n when(io.inc_from) {\n cnt_from := bin_next\n gray := gray_next\n }\n }\n\n io.cnt_from := cnt_from\n io.cnt_to :=\n (0 until width).foldLeft(0.U) {\n (acc, i) => {\n acc | ((gray_sync >> i).xorR << i)\n }\n }\n}\n\n/**\n * A wrapper class of CcdCounterModule for ease of use\n * @param fromClock Clock of clock domain in which the counter increase\n * @param toClock Clock of clock domain in which the counter value received\n * @param fromReset Reset of `fromClock` domain\n * @param toReset Reset of `toClock` domain\n * @param width Width in bits of the counter\n * @param incCond The condition of counter increasing\n */\nclass CcdCounter(fromClock: Clock, toClock: Clock,\n fromReset: Bool, toReset: Bool)(\n width: Int, incCond: Bool) {\n require(width > 0, \"In CcdCounter, width must be >= 1.\")\n\n val ccd_cnt = Module(new CcdCounterModule(width))\n ccd_cnt.io.fromClock := fromClock\n ccd_cnt.io.toClock := toClock\n ccd_cnt.io.fromReset := fromReset\n ccd_cnt.io.toReset := toReset\n ccd_cnt.io.inc_from := incCond\n\n /**\n * Get the counter value in `fromClock` domain\n *\n * @return The counter value\n */\n def cnt_from(): UInt = {\n ccd_cnt.io.cnt_from\n }\n\n /**\n * Get the counter value in `toClock` domain\n *\n * @return The counter value\n */\n def cnt_to(): UInt = {\n ccd_cnt.io.cnt_to\n }\n}\n\nobject CcdCounter {\n /**\n * Create an instance of CcdCounter, with a CcdCounterModule in it and make\n * some connections.\n * @param fromClock Clock of clock domain in which the counter increase\n * @param toClock Clock of clock domain in which the counter value received\n * @param fromReset Reset of `fromClock` domain\n * @param toReset Reset of `toClock` domain\n * @param width Width in bits of the counter\n * @param incCond The condition of counter increasing\n * @return The instance created\n */\n def apply(fromClock: Clock, toClock: Clock, fromReset: Bool, toReset: Bool)(width: Int, incCond: Bool) = {\n new CcdCounter(fromClock, toClock, fromReset, toReset)(width, incCond)\n }\n}\n\n/**\n * Represent a hardware Dual Clock Fifo with native fifo interfaces.\n * @param gen Generator of data\n * @param addrWidth Width in bits of the inner address,\n * fifo depth = 2**addrWidth - 1\n * @param wrHasDataCnt Set to true if data count is needed in write side\n * @param rdHasDataCnt Set to true if data count is needed in read side\n * @param wrHasWrRdCnt Set to true if write count and read count are needed\n * in write side\n * @param rdHasWrRdCnt Set to true if write count and read count are needed\n * in read side\n * @tparam T Type of data\n */\nclass DcFifo[T <: Data](gen: T, addrWidth: Int,\n wrHasDataCnt: Boolean = false,\n rdHasDataCnt: Boolean = false,\n wrHasWrRdCnt: Boolean = false,\n rdHasWrRdCnt: Boolean = false) extends RawModule {\n require(addrWidth >= 1 && addrWidth < 64, \"In DcFifo, addrWidth must be in [1, 63]\")\n require(!(!wrHasDataCnt && wrHasWrRdCnt), \"In DcFifo, when wrHasDataCnt == false, wrHasWrRdCnt is not allowed to be true!\")\n require(!(!rdHasDataCnt && rdHasWrRdCnt), \"In DcFifo, when rdHasDataCnt == false, rdHasWrRdCnt is not allowed to be true!\")\n\n", "right_context": "\n val io = IO(new Bundle {\n val wrClock = Input(Clock())\n val rdClock = Input(Clock())\n val wrReset = Input(Bool())\n val rdReset = Input(Bool())\n val w = FifoIO.Writee(gen)\n val wcnt = if(wrHasDataCnt) Some(FifoIO.CntProvider(addrWidth, wrHasWrRdCnt))\n else None\n val r = FifoIO.Readee(gen)\n val rcnt = if(rdHasDataCnt) Some(FifoIO.CntProvider(addrWidth, rdHasWrRdCnt))\n else None\n })\n val m: BigInt = 1 << addrWidth\n val capacity: BigInt = m - 1\n\n val ccd_wr_cnt = CcdCounter(io.wrClock, io.rdClock,\n io.wrReset, io.rdReset)(addrWidth, io.w.write)\n val ccd_rd_cnt = CcdCounter(io.rdClock, io.wrClock,\n io.rdReset, io.wrReset)(addrWidth, io.r.read)\n\n val sdc_ram = SyncReadMem(m, gen)\n when(io.w.write) { sdc_ram.write(ccd_wr_cnt.cnt_from(), io.w.data, io.wrClock) }\n val qout_b = sdc_ram.read(ccd_rd_cnt.cnt_from(), io.rdClock)\n\n withClockAndReset(io.rdClock, io.rdReset) {\n val rd_dly = RegNext(io.r.read, false.B)\n val qout_b_reg = RegEnable(qout_b, 0.U.asTypeOf(gen), rd_dly)\n io.r.data := Mux(rd_dly, qout_b, qout_b_reg)\n }\n\n val w_data_cnt = ccd_wr_cnt.cnt_from() - ccd_rd_cnt.cnt_to()\n io.w.full := w_data_cnt === capacity.U\n val r_data_cnt = ccd_wr_cnt.cnt_to() - ccd_rd_cnt.cnt_from()\n io.r.empty := r_data_cnt === 0.U\n\n io.wcnt.foreach(wc => {\n wc.dataCnt := w_data_cnt\n wc.writeCnt.foreach(_ := ccd_wr_cnt.cnt_from())\n wc.readCnt.foreach(_ := ccd_rd_cnt.cnt_to())\n })\n io.rcnt.foreach(rc => {\n rc.dataCnt := r_data_cnt\n rc.writeCnt.foreach(_ := ccd_wr_cnt.cnt_to())\n rc.readCnt.foreach(_ := ccd_rd_cnt.cnt_from())\n })\n}\n\n/*\nobject DcFifo {\n /**\n * Create an instance of DcFifo.\n *\n * @param gen Generator of data\n * @param addrWidth Width in bits of the inner address,\n * fifo depth = 2**addrWidth - 1\n * @param wrHasDataCnt Set to true if data count is needed in write side\n * @param rdHasDataCnt Set to true if data count is needed in read side\n * @param wrHasWrRdCnt Set to true if write count and read count are needed\n * in write side\n * @param rdHasWrRdCnt Set to true if write count and read count are needed\n * in read side\n * @tparam T Type of data\n * @return The instance created\n * @example {{{\n * val dcfifo = DcFifo(UInt(32.W), 10, true, true)\n * dcfifo.wrClock := clk_wr\n * dcfifo.rdClock := clk_rd\n * dcfifo.wrReset := rst_wr\n * dcfifo.rdReset := rst_rd\n * io.fifo_wr <> dcfifo.w\n * io.fifo_rd <> dcfifo.r\n * io.fifo_wrcnt <> dcfifo.wcnt.get\n * io.fifo_rdcnt <> dcfifo.rcnt.get\n * }}}\n */\n def apply[T <: Data](gen: T, addrWidth: Int,\n wrHasDataCnt: Boolean = false, rdHasDataCnt: Boolean = false,\n wrHasWrRdCnt: Boolean = false, rdHasWrRdCnt: Boolean = false): DcFifo[T] = {\n Module(new DcFifo(gen, addrWidth,\n wrHasDataCnt, rdHasDataCnt,\n wrHasWrRdCnt, rdHasWrRdCnt))\n }\n}\n */\n\npackage examples {\n class anti_metastable_example extends Module {\n val io = IO(new Bundle {\n val in0 = Input(UInt(8.W))\n val out0 = Output(UInt(8.W))\n val in1 = Input(UInt(4.W))\n val out1 = Output(UInt(4.W))\n })\n val ams = AntiMetastable(UInt(8.W), 3)()\n io.out0 := ams.input(io.in0)\n io.out1 := AntiMetastable._2ff(io.in1)(\n Some(() => {\n (~0.U).asTypeOf(io.in1)\n })\n )\n }\n\n class edge2en_example extends Module {\n val io = IO(new Bundle {\n val in = Input(Bool())\n val out = Output(Bool())\n val rising = Output(Bool())\n val falling = Output(Bool())\n })\n val (r, f, o) = Edge2En(io.in, true)\n io.rising := r\n io.falling := f\n io.out := o\n }\n\n class ccd_trigger_example extends RawModule {\n val io = IO(new Bundle {\n val clk_a = Input(Clock())\n val clk_b = Input(Clock())\n val rst_a = Input(Bool())\n val rst_b = Input(Bool())\n val trig_in = Input(Bool())\n val trig_out = Output(Bool())\n })\n io.trig_out := CcdTrigger(io.clk_a, io.clk_b, io.rst_a, io.rst_b)(io.trig_in)\n }\n\n class ccd_counter_example extends RawModule {\n val io = IO(new Bundle {\n val clk_a = Input(Clock())\n val clk_b = Input(Clock())\n val rst_a = Input(Bool())\n val rst_b = Input(Bool())\n val inc_a = Input(Bool())\n val cnt_a = Output(UInt(8.W))\n val cnt_b = Output(UInt(8.W))\n })\n val ccdcnt = CcdCounter(io.clk_a, io.clk_b, io.rst_a, io.rst_b)(8, io.inc_a)\n io.cnt_a := ccdcnt.cnt_from()\n io.cnt_b := ccdcnt.cnt_to()\n }\n\n class dcfifo_example extends RawModule {\n val dType = UInt(32.W)\n val aw = 10\n val w_has_dc = true\n val r_has_dc = true\n val w_has_wrc = false\n val r_has_wrc = false\n val io = FlatIO(new Bundle {\n val clk_wr = Input(Clock())\n val clk_rd = Input(Clock())\n val reset_wr = Input(Bool())\n val reset_rd = Input(Bool())\n val w = FifoIO.Writee(dType)\n val wc = if (w_has_dc) Some(FifoIO.CntProvider(aw, w_has_wrc)) else None\n val r = FifoIO.Readee(dType)\n val rc = if (r_has_dc) Some(FifoIO.CntProvider(aw, r_has_wrc)) else None\n })\n val dcfifo = Module(new DcFifo(dType, aw, w_has_dc, r_has_dc, w_has_wrc, r_has_wrc))\n io.clk_wr <> dcfifo.io.wrClock\n io.clk_rd <> dcfifo.io.rdClock\n io.reset_wr <> dcfifo.io.wrReset\n io.reset_rd <> dcfifo.io.rdReset\n io.w <> dcfifo.io.w\n io.r <> dcfifo.io.r\n if (w_has_dc)\n io.wc.get <> dcfifo.io.wcnt.get\n if (r_has_dc)\n io.rc.get <> dcfifo.io.rcnt.get\n }\n}\n", "groundtruth": " override def desiredName: String = super.desiredName + s\"_${(1<\n bias + math.round(amp * math.sin(omega * i + phase))\n }\n }\n\n /**\n * Generate a cosine wave Seq\n *\n * @param length Length of the Seq to be generated\n * @param dataWidth Width (bits) of each element in Seq\n * @param phase Phase shift of generated sine wave\n * @param fullScale Dynamic range of generated sine wave, default full\n * @param cycles Number of cycles of the sine wave\n * @param isSigned True for 2's compliment data, false for binary offset data\n * @return The generated cosine wave Seq\n */\n def CosineWave(length: Int, dataWidth: Int, phase: Double = 0.0, fullScale: Double = 1.0, cycles: Double = 1.0, isSigned: Boolean = true): IndexedSeq[Long] = {\n SineWava(length, dataWidth, phase + math.Pi / 2.0, fullScale, cycles, isSigned)\n }\n\n /**\n * Write memory initialize data file, which can be used by `$readmemh` system call in verilog\n *\n * @param fileName Path and name of the data file\n * @param data Data Seq to be written in the file\n * @param bitWidth Data with of ram elements to be init\n * @tparam T Type of data (element in Seq), must be Int or Long\n */\n def Write[T: Integral](fileName: String, data: Seq[T], bitWidth: Int): Try[Unit] = {\n require(1 <= bitWidth && bitWidth <= 64)\n val hexWidth = (bitWidth - 1) / 4 + 1\n val hexFormat = s\"%0${hexWidth}X\"\n Using(new PrintWriter(new FileWriter(fileName))) { writer =>\n data.foreach { d => {\n val str = hexFormat.format(Integral[T].toLong(d)).takeRight(hexWidth)\n writer.println(str)\n }\n }\n }\n }\n}\n\n/**\n * Collection of RAM IOs\n */\nobject RamIO {\n /**\n * Represent a hardware RAM IO of Single port Read and Write.\n * @param nWords Number of Words (elements) in RAM\n * @param gen Generator of Data\n * @tparam T Type of Data\n */\n class RW[T <: Data](nWords: Long, gen: T) extends Bundle {\n require(nWords >= 2, \"nWords must be >= 2 in RamIO.RW.\")\n val addr = Input(UInt(log2Up(nWords).W))\n val we = Input(Bool())\n val din = Input(gen)\n val dout = Output(gen)\n }\n\n /**\n * Represent a hardware RAM IO of Single Port Read.\n * @param nWords Number of Words (elements) in RAM\n * @param gen Generator of Data\n * @tparam T Type of Data\n */\n class R[T <: Data](nWords: Long, gen: T) extends Bundle {\n require(nWords >= 2, \"nWords must be >= 2 in RamIO.R.\")\n val addr = Input(UInt(log2Up(nWords).W))\n val dout = Output(gen)\n }\n\n /**\n * Represent a hardware RAM IO of Single Port Write.\n * @param nWords Number of Words (elements) in RAM\n * @param gen Generator of Data\n * @tparam T Type of Data\n */\n class W[T <: Data](nWords: Long, gen: T) extends Bundle {\n require(nWords >= 2, \"nWords must be >= 2 in RamIO.W.\")\n val addr = Input(UInt(log2Up(nWords).W))\n val en = Input(Bool())\n val din = Input(gen)\n }\n\n /**\n * Represent a hardware RAM IO of Single port Read and Write with Clock.\n * @param nWords Number of Words (elements) in RAM\n * @param gen Generator of Data\n * @tparam T Type of Data\n */\n class CRW[T <: Data](nWords: Long, gen: T) extends Bundle {\n require(nWords >= 2, \"nWords must be >= 2 in RamIO.CRW.\")\n val clock = Input(Clock())\n val addr = Input(UInt(log2Up(nWords).W))\n val we = Input(Bool())\n val din = Input(gen)\n val dout = Output(gen)\n }\n\n /**\n * Represent a hardware RAM IO of Single Port Read with Clock.\n * @param nWords Number of Words (elements) in RAM\n * @param gen Generator of Data\n * @tparam T Type of Data\n */\n class CR[T <: Data](nWords: Long, gen: T) extends Bundle {\n require(nWords >= 2, \"nWords must be >= 2 in RamIO.CR.\")\n val clock = Input(Clock())\n val addr = Input(UInt(log2Up(nWords).W))\n val dout = Output(gen)\n }\n\n /**\n * Represent a hardware RAM IO of Single Port Write with Clock.\n * @param nWords Number of Words (elements) in RAM\n * @param gen Generator of Data\n * @tparam T Type of Data\n */\n class CW[T <: Data](nWords: Long, gen: T) extends Bundle {\n require(nWords >= 2, \"nWords must be >= 2 in RamIO.CW.\")\n val clock = Input(Clock())\n val addr = Input(UInt(log2Up(nWords).W))\n val en = Input(Bool())\n val din = Input(gen)\n }\n}\n\n// Unfortunately, SyncReadMem.ReadFirst and WriteFirst seems not work.\n//class SpRamRf[T <: Data](nWords: Int, gen: T) extends Module {\n// val io = IO(new RamIO.SRW(nWords, gen))\n// // It's recommended using chisel3.SyncReadMem directly in code,\n// // No need to wrap a module like this.\n// val mem = SyncReadMem(nWords, gen, SyncReadMem.ReadFirst)\n// io.dout := mem.read(io.addr)\n// when(io.we) {\n// mem.write(io.addr, io.din)\n// }\n//}\n//class SpRamWf[T <: Data](nWords: Int, gen: T) extends Module {\n// val io = IO(new RamIO.SRW(nWords, gen))\n// // It's recommended using chisel3.SyncReadMem directly in code,\n// // No need to wrap a module like this.\n// val mem = SyncReadMem(nWords, gen, SyncReadMem.WriteFirst)\n// io.dout := mem.read(io.addr)\n// when(io.we) {\n// mem.write(io.addr, io.din)\n// }\n//}\n\n/**\n * Represent a hardware Read First Simple Dual Port Synchronous Read RAM module,\n * when reading the word being written, read the old data.\n * @param nWords Number of Words (elements) in RAM\n * @param dataWidth Data Width\n * @param initFile Hex data file for initializing RAM by internally using\n * verilog system call `$readmemh()`, default `None` for no\n * initializing.\n */\nclass SdpRamRfInline(nWords: Long, dataWidth: Int, initFile: Option[String] = None) extends HasBlackBoxInline {\n require(nWords > 0 && dataWidth > 0)\n override def desiredName = s\"${super.desiredName}_${nWords}x${dataWidth}b\"\n\n val io = IO(new Bundle {\n val clock = Input(Clock())\n val waddr = Input(UInt(log2Up(nWords).W))\n val we = Input(Bool())\n val din = Input(UInt(dataWidth.W))\n val raddr = Input(UInt(log2Up(nWords).W))\n val qout = Output(UInt(dataWidth.W))\n })\n setInline(s\"${desiredName}.v\",\n s\"\"\"\n |module ${desiredName} #(\n | parameter DW = ${dataWidth}, WORDS = ${nWords}\n |)(\n | input wire clock,\n | input wire [$$clog2(WORDS) - 1 : 0] waddr,\n | input wire we ,\n | input wire [DW - 1 : 0] din ,\n | input wire [$$clog2(WORDS) - 1 : 0] raddr,\n | output reg [DW - 1 : 0] qout\n |);\n | reg [DW - 1 : 0] ram[0 : WORDS - 1];\n | ${if (initFile.isDefined) s\"initial $$readmemh(\\\"${initFile.get}\\\", ram);\" else \"\"}\n | always@(posedge clock) begin\n | if(we) ram[waddr] <= din;\n | qout <= ram[raddr];\n | end\n |endmodule\n |\"\"\".stripMargin\n )\n}\n\n/**\n * Represent a hardware Write First Simple Dual Port Synchronous Read RAM module,\n * when reading the word being written, read the new data.\n * @param nWords Number of Words (elements) in RAM\n * @param dataWidth Data Width\n * @param initFile Hex data file for initializing RAM by internally using\n * verilog system call `$readmemh()`, default `None` for no\n * initializing.\n */\nclass SdpRamWfInline(nWords: Long, dataWidth: Int, initFile: Option[String] = None) extends HasBlackBoxInline {\n require(nWords > 0 && dataWidth > 0)\n override def desiredName = s\"${super.desiredName}_${nWords}x${dataWidth}b\"\n\n val io = IO(new Bundle {\n val clock = Input(Clock())\n val waddr = Input(UInt(log2Up(nWords).W))\n val we = Input(Bool())\n val din = Input(UInt(dataWidth.W))\n val raddr = Input(UInt(log2Up(nWords).W))\n val qout = Output(UInt(dataWidth.W))\n })\n setInline(s\"${desiredName}.v\",\n s\"\"\"\n |module ${desiredName} #(\n | parameter DW = ${dataWidth}, WORDS = ${nWords}\n |)(\n | input wire clock,\n | input wire [$$clog2(WORDS) - 1 : 0] waddr,\n | input wire we ,\n | input wire [DW - 1 : 0] din ,\n | input wire [$$clog2(WORDS) - 1 : 0] raddr,\n | output reg [DW - 1 : 0] qout\n |);\n | reg [DW - 1 : 0] ram[0 : WORDS - 1];\n | ${if (initFile.isDefined) s\"initial $$readmemh(\\\"${initFile.get}\\\", ram);\" else \"\"}\n | always@(posedge clock) begin\n | if(we) begin\n | ram[waddr] <= din;\n | end\n | end\n | always@(posedge clock) begin\n | if(we && raddr == waddr)\n | qout <= din\n | else\n | qout <= ram[raddr]\n | end\n |endmodule\n |\"\"\".stripMargin\n )\n}\n\n/**\n * Represent a hardware Simple Dual Port Asynchronous Read RAM module.\n * @param nWords Number of Words (elements) in RAM\n * @param dataWidth Data Width\n * @param initFile Hex data file for initializing RAM by internally using\n * verilog system call `$readmemh()`, default `None` for no\n * initializing.\n */\nclass SdpRamRaInline(nWords: Long, dataWidth: Int, initFile: Option[String] = None) extends HasBlackBoxInline {\n require(nWords > 0 && dataWidth > 0)\n override def desiredName = s\"${super.desiredName}_${nWords}x${dataWidth}b\"\n\n val io = IO(new Bundle {\n val clock = Input(Clock())\n val waddr = Input(UInt(log2Up(nWords).W))\n val we = Input(Bool())\n val din = Input(UInt(dataWidth.W))\n val raddr = Input(UInt(log2Up(nWords).W))\n val dout = Output(UInt(dataWidth.W))\n })\n setInline(s\"${desiredName}.v\",\n s\"\"\"\n |module ${desiredName} #( // asynchronous read\n | parameter DW = ${dataWidth}, WORDS = ${nWords}\n |)(\n | input wire clock,\n | input wire [$$clog2(WORDS) - 1 : 0] waddr,\n | input wire we ,\n | input wire [DW - 1 : 0] din ,\n | input wire [$$clog2(WORDS) - 1 : 0] raddr,\n | output reg [DW - 1 : 0] dout\n |);\n | reg [DW - 1 : 0] ram[0 : WORDS - 1];\n | ${if (initFile.isDefined) s\"initial $$readmemh(\\\"${initFile.get}\\\", ram);\" else \"\"}\n | always@(posedge clock) begin\n | if(we) ram[waddr] <= din;\n | end\n | assign dout = ram[raddr];\n |endmodule\n |\n |\"\"\".stripMargin\n )\n}\n\n/**\n * Represent a hardware True Dual Port Synchronous Read RAM module.\n * @param nWords Number of Words (elements) in RAM\n * @param dataWidth Data Width\n * @param initFile Hex data file for initializing RAM by internally using\n * verilog system call `$readmemh()`, default `None` for no\n * initializing.\n * @note\n * - Write First inner each port.\n * - Read First between ports, but not guaranteed when inferred using\n * blockRAM by FPGA synthesizer, it's the user's responsibilities to\n * check the actual behavior or guarantee no simultaneously access to\n * same address at both ports.\n */\nclass DpRamInline(nWords: Long, dataWidth: Int, initFile: Option[String] = None) extends HasBlackBoxInline {\n require(nWords > 0 && dataWidth > 0)\n override def desiredName = s\"${super.desiredName}_${nWords}x${dataWidth}b\"\n\n val io = IO(new Bundle {\n val clock = Input(Clock())\n val addr_a = Input(UInt(log2Up(nWords).W))\n val wr_a = Input(Bool())\n val din_a = Input(UInt(dataWidth.W))\n val qout_a = Output(UInt(dataWidth.W))\n val addr_b = Input(UInt(log2Up(nWords).W))\n val wr_b = Input(Bool())\n val din_b = Input(UInt(dataWidth.W))\n val qout_b = Output(UInt(dataWidth.W))\n })\n setInline(s\"${desiredName}.v\",\n s\"\"\"\n |module ${desiredName} #(\n | parameter DW = ${dataWidth}, WORDS = ${nWords}\n |)(\n | input wire clock ,\n | input wire [$$clog2(WORDS) - 1 : 0] addr_a,\n | input wire wr_a ,\n | input wire [DW - 1 : 0] din_a ,\n | output reg [DW - 1 : 0] qout_a,\n | input wire [$$clog2(WORDS) - 1 : 0] addr_b,\n | input wire wr_b ,\n | input wire [DW - 1 : 0] din_b ,\n | output reg [DW - 1 : 0] qout_b\n |);\n | reg [DW - 1 : 0] ram[0 : WORDS - 1];\n | ${if (initFile.isDefined) s\"initial $$readmemh(\\\"${initFile.get}\\\", ram);\" else \"\"}\n | always@(posedge clock) begin\n | if(wr_a) begin\n | ram[addr_a] <= din_a;\n | qout_a <= din_a;\n | end\n | else qout_a <= ram[addr_a];\n | end\n | always@(posedge clock) begin\n | if(wr_b) begin\n | ram[addr_b] <= din_b;\n | qout_b <= din_b;\n | end\n | else qout_b <= ram[addr_b];\n | end\n |endmodule\n |\"\"\".stripMargin\n )\n}\n\n/**\n * Represent a hardware True Dual Clock Synchronous Read RAM module.\n * @param nWords Number of Words (elements) in RAM\n * @param dataWidth Data Width\n * @param initFile Hex data file for initializing RAM by internally using\n * verilog system call `$readmemh()`, default `None` for no\n * initializing.\n * @note\n * - Write First inner each port.\n * - Read First between ports, but not guaranteed when inferred using\n * blockRAM by FPGA synthesizer, it's the user's responsibilities to\n * check the actual behavior or guarantee no simultaneously access to\n * same address at both ports.\n */\nclass DcRamInline(nWords: Long, dataWidth: Int, initFile: Option[String] = None) extends HasBlackBoxInline {\n require(nWords > 0 && dataWidth > 0)\n override def desiredName = s\"${super.desiredName}_${nWords}x${dataWidth}b\"\n\n val io = IO(new Bundle {\n val clock_a = Input(Clock())\n val addr_a = Input(UInt(log2Up(nWords).W))\n val wr_a = Input(Bool())\n val din_a = Input(UInt(dataWidth.W))\n val qout_a = Output(UInt(dataWidth.W))\n val clock_b = Input(Clock())\n val addr_b = Input(UInt(log2Up(nWords).W))\n val wr_b = Input(Bool())\n val din_b = Input(UInt(dataWidth.W))\n val qout_b = Output(UInt(dataWidth.W))\n })\n setInline(s\"${desiredName}.v\",\n s\"\"\"\n |module ${desiredName} #(\n | parameter DW = ${dataWidth}, WORDS = ${nWords}\n |)(\n | input wire clock_a ,\n | input wire [$$clog2(WORDS) - 1 : 0] addr_a ,\n | input wire wr_a ,\n | input wire [DW - 1 : 0] din_a ,\n | output reg [DW - 1 : 0] qout_a ,\n | input wire clock_b ,\n | input wire [$$clog2(WORDS) - 1 : 0] addr_b ,\n | input wire wr_b ,\n | input wire [DW - 1 : 0] din_b ,\n | output reg [DW - 1 : 0] qout_b\n |);\n | reg [DW - 1 : 0] ram[0 : WORDS - 1];\n | ${if (initFile.isDefined) s\"initial $$readmemh(\\\"${initFile.get}\\\", ram);\" else \"\"}\n | always@(posedge clock_a) begin\n | if(wr_a) begin\n | ram[addr_a] <= din_a;\n | qout_a <= din_a;\n | end\n | else qout_a <= ram[addr_a];\n | end\n | always@(posedge clock_b) begin\n | if(wr_b) begin\n | ram[addr_b] <= din_b;\n | qout_b <= din_b;\n | end\n | else qout_b <= ram[addr_b];\n | end\n |endmodule\n |\"\"\".stripMargin\n )\n}\n\n/**\n * A Read First version of SyncReadMem.\n *\n * @param nWords Number of words in RAM\n * @param gen Generator of data\n * @param clock [implicit] Clock of the RAM\n * @param initFile Hex data file for initializing RAM by internally using\n * verilog system call `$readmemh()`, default `None` for no\n * initializing.\n * @tparam T Type of data\n * @note You may prefer to use the homonymous factory object\n * @example {{{\n * val ram_rf = new SyncReadMemReadFirst\n * (256, UInt(32.W))(clock)\n * // Or use the factory method\n * // val ram_rf = SyncReadMemReadFirst\n * // (256, UInt(32.W))(clock)\n * io.rdata := ram_rf.read(io.raddr)\n * ram_rf.write(io.waddr, io.wdata, io.wen)\n * }}}\n */\nclass SyncReadMemReadFirst[T <: Data](nWords: Long, gen: T, initFile: Option[String] = None)(implicit val clock: Clock) {\n private val sdpramrf = Module(new SdpRamRfInline(nWords, gen.getWidth, initFile))\n sdpramrf.io.clock := clock\n\n /**\n * The read operation\n * @param addr Address of the read operation\n * @return Result of the read operation\n */\n def read(addr: UInt): T = {\n sdpramrf.io.raddr := addr\n sdpramrf.io.qout.asTypeOf(gen)\n }\n\n /**\n * The write operation\n * @param addr Address of the write operation\n * @param data Data to be written\n * @param en Enable of the write operation\n */\n def write(addr: UInt, data: T, en: Bool): Unit = {\n sdpramrf.io.waddr := addr\n sdpramrf.io.we := en\n sdpramrf.io.din := data.asUInt\n }\n}\n\nobject SyncReadMemReadFirst {\n /**\n * Create a Synchronous Read Memory (Read-First) instance.\n * @param nWords Number of words in RAM\n * @param gen Generator of data\n * @param clock [implicit] Clock of the SyncReadMemReadFirst instance\n * @param initFile Hex data file for initializing RAM by internally using\n * verilog system call `$readmemh()`, default `None` for no\n * initializing.\n * @tparam T Type of data\n * @return The instance created.\n * @example {{{\n * val ram_rf = SyncReadMemReadFirst\n * (256, UInt(32.W))(clock)\n * io.rdata := ram_rf.read(io.raddr)\n * ram_rf.write(io.waddr, io.wdata, io.wen)\n * }}}\n */\n def apply[T <: Data](nWords: Long, gen: T, initFile: Option[String] = None)(implicit clock: Clock): SyncReadMemReadFirst[T] = {\n new SyncReadMemReadFirst(nWords, gen, initFile)\n }\n}\n\n/**\n * A Write First version of SyncReadMem.\n * @param nWords Number of words in RAM\n * @param gen Generator of data\n * @param clock [implicit] Clock of the RAM\n * @param initFile Hex data file for initializing RAM by internally using\n * verilog system call `$readmemh()`, default `None` for no\n * initializing.\n * @tparam T Type of data\n * @note You may prefer to use the homonymous factory object\n * @example {{{\n * val ram_wf = new SyncReadMemWriteFirst\n * (256, UInt(32.W))(clock)\n * // Or use the factory method\n * // val ram_wf = SyncReadMemWriteFirst\n * // (256, UInt(32.W))(clock)\n * io.rdata := ram_wf.read(io.raddr)\n * ram_wf.write(io.waddr, io.wdata, io.wen)\n * }}}\n */\nclass SyncReadMemWriteFirst[T <: Data](nWords: Long, gen: T, initFile: Option[String] = None)(implicit val clock: Clock) {\n private val sdpramwf = Module(new SdpRamWfInline(nWords, gen.getWidth, initFile))\n sdpramwf.io.clock := clock\n\n /**\n * The read operation\n * @param addr Address of the read operation\n * @return Result of the read operation\n */\n def read(addr: UInt): T = {\n sdpramwf.io.raddr := addr\n sdpramwf.io.qout.asTypeOf(gen)\n }\n\n /**\n * The write operation\n * @param addr Address of the write operation\n * @param data Data to be written\n * @param en Enable of the write operation\n */\n def write(addr: UInt, data: T, en: Bool): Unit = {\n sdpramwf.io.waddr := addr\n sdpramwf.io.we := en\n sdpramwf.io.din := data.asUInt\n }\n}\n\nobject SyncReadMemWriteFirst {\n /**\n * Create a Synchronous Read Memory (Write-First) instance.\n * @param nWords Number of words in RAM\n * @param gen Generator of data\n * @param clock [implicit] Clock of the SyncReadMemWriteFirst instance\n * @param initFile Hex data file for initializing RAM by internally using\n * verilog system call `$readmemh()`, default `None` for no\n * initializing.\n * @tparam T Type of data\n * @return The instance created.\n * @example {{{\n * val ram_wf = SyncReadMemWriteFirst\n * (256, UInt(32.W))(clock)\n * io.rdata := ram_wf.read(io.raddr)\n * ram_wf.write(io.waddr, io.wdata, io.wen)\n * }}}\n */\n def apply[T <: Data](nWords: Long, gen: T, initFile: Option[String] = None)(implicit clock: Clock): SyncReadMemWriteFirst[T] = {\n new SyncReadMemWriteFirst(nWords, gen, initFile)\n }\n}\n\n/**\n * An Asynchronous Read Memory.\n * @param nWords Number of words in RAM\n * @param gen Generator of data\n * @param clock [implicit] Clock of the RAM\n * @param initFile Hex data file for initializing RAM by internally using\n * verilog system call `$readmemh()`, default `None` for no\n * initializing.\n * @tparam T Type of data\n * @note You may prefer to use the homonymous factory object\n * @example {{{\n * val ram_ra = new AsyncReadMem\n * (256, UInt(32.W))(clock)\n * // Or use the factory method\n * // val ram_ra = AsyncReadMem\n * // (256, UInt(32.W))(clock)\n * io.rdata := ram_ra.read(io.raddr)\n * ram_ra.write(io.waddr, io.wdata, io.wen)\n * }}}\n */\nclass AsyncReadMem[T <: Data](nWords: Long, gen: T, initFile: Option[String] = None)(implicit val clock: Clock) {\n private val sdpramra = Module(new SdpRamRaInline(nWords, gen.getWidth, initFile))\n sdpramra.io.clock := clock\n\n /**\n * The read operation\n * @param addr Address of the read operation\n * @return Result of the read operation\n */\n def read(addr: UInt): T = {\n sdpramra.io.raddr := addr\n sdpramra.io.dout.asTypeOf(gen)\n }\n\n /**\n * The write operation\n * @param addr Address of the write operation\n * @param data Data to be written\n * @param en Enable of the write operation\n */\n def write(addr: UInt, data: T, en: Bool): Unit = {\n sdpramra.io.waddr := addr\n sdpramra.io.we := en\n sdpramra.io.din := data.asUInt\n }\n}\n\nobject AsyncReadMem {\n /**\n * Create an Asynchronous Read Memory instance.\n * @param nWords Number of words in RAM\n * @param gen Generator of data\n * @param clock [implicit] Clock of the AsyncReadMem instance\n * @param initFile Hex data file for initializing RAM by internally using\n * verilog system call `$readmemh()`, default `None` for no\n * initializing.\n * @tparam T Type of data\n * @return The instance created.\n * @example {{{\n * val ram_ra = AsyncReadMem\n * (256, UInt(32.W))(clock)\n * io.rdata := ram_ra.read(io.raddr)\n * ram_ra.write(io.waddr, io.wdata, io.wen)\n * }}}\n */\n def apply[T <: Data](nWords: Long, gen: T, initFile: Option[String] = None)(implicit clock: Clock): AsyncReadMem[T] = {\n new AsyncReadMem(nWords, gen, initFile)\n }\n}\n\n/**\n * A True Dual Port Synchronous Read Mem.\n * @param nWords Number of words in RAM\n * @param gen Generator of data\n * @param clock [implicit] Clock of the RAM\n * @param initFile Hex data file for initializing RAM by internally using\n * verilog system call `$readmemh()`, default `None` for no\n * initializing.\n * @tparam T Type of data\n * @note\n * - You may prefer to use the homonymous factory object.\n * - Write First inner each port.\n * - Read First between ports, but not guaranteed when inferred using\n * blockRAM by FPGA synthesizer, it's the user's responsibilities to\n * check the actual behavior or guarantee no simultaneously access to\n * same address at both ports.\n * @example {{{\n * val dpram = new DualPortSyncReadMem\n * (256, UInt(32.W))(clock)\n * // Or use the factory method\n * // val dpram = DualPortSyncReadMem\n * // (256, UInt(32.W))(clock)\n * io.port_a.rdata := dpram.access_a(\n * io.port_a.addr,\n * io.port_a.wdata,\n * io.port_a.wen )\n * io.port_b.rdata := dpram.access_b(\n * io.port_b.addr,\n * io.port_b.wdata,\n * io.port_b.wen )\n * }}}\n */\nclass DualPortSyncReadMem[T <: Data](nWords: Long, gen: T, initFile: Option[String] = None)(implicit val clock: Clock) {\n private val dpram = Module(new DpRamInline(nWords, gen.getWidth, initFile))\n dpram.io.clock := clock\n\n /**\n * The access operation of port a\n * @param addr Address of the operation (both read and write)\n * @param data Data to be written\n * @param wen Write enable\n * @return Data read out\n */\n def access_a(addr: UInt, data: T, wen: Bool): T = {\n dpram.io.addr_a := addr\n dpram.io.wr_a := wen\n dpram.io.din_a := data.asUInt\n dpram.io.qout_a.asTypeOf(gen)\n }\n /**\n * The access operation of port b\n * @param addr Address of the operation (both read and write)\n * @param data Data to be written\n * @param wen Write enable\n * @return Data read out\n */\n def access_b(addr: UInt, data: T, wen: Bool): T = {\n dpram.io.addr_b := addr\n dpram.io.wr_b := wen\n dpram.io.din_b := data.asUInt\n dpram.io.qout_b.asTypeOf(gen)\n }\n}\n\nobject DualPortSyncReadMem {\n /**\n * Create a True Dual Port Synchronous Read Memory instance.\n * @param nWords Number of words in RAM\n * @param gen Generator of data\n * @param clock [implicit] Clock of the DualPortSyncReadMem instance\n * @param initFile Hex data file for initializing RAM by internally using\n * verilog system call `$readmemh()`, default `None` for no\n * initializing.\n * @tparam T Type of data\n * @return The instance created.\n * @note\n * - Write First inner each port.\n * - Read First between ports, but not guaranteed when inferred using\n * blockRAM by FPGA synthesizer, it's the user's responsibilities to\n * check the actual behavior or guarantee no simultaneously access to\n * same address at both ports.\n * @example {{{\n * val dpram = DualPortSyncReadMem\n * (256, UInt(32.W))(clock)\n * io.port_a.rdata := dpram.access_a(\n * io.port_a.addr,\n * io.port_a.wdata,\n * io.port_a.wen )\n * io.port_b.rdata := dpram.access_b(\n * io.port_b.addr,\n * io.port_b.wdata,\n * io.port_b.wen )\n * }}}\n */\n def apply[T <: Data](nWords: Long, gen: T, initFile: Option[String] = None)(implicit clock: Clock): DualPortSyncReadMem[T] = {\n new DualPortSyncReadMem(nWords, gen, initFile)\n }\n}\n\n/**\n * A True Dual Clock Synchronous Read Mem\n * @param nWords Number of words in RAM\n * @param gen Generator of data\n * @param initFile Hex data file for initializing RAM by internally using\n * verilog system call `$readmemh()`, default `None` for no\n * initializing.\n * @tparam T Type of data\n * @note\n * - You may prefer to use the homonymous factory object.\n * - Write First inner each port.\n * @example {{{\n * val dcram = new DualClockSyncReadMem(256, UInt(32.W))\n * // Or use the factory method\n * // val dpram = DualPortSyncReadMem(256, UInt(32.W))\n * io.port_a.rdata := dcram.access_a(\n * io.port_a.clock,\n * io.port_a.addr,\n * io.port_a.wdata,\n * io.port_a.wen )\n * io.port_b.rdata := dcram.access_b(\n * io.port_b.clock,\n * io.port_b.addr,\n * io.port_b.wdata,\n * io.port_b.wen )\n * }}}\n */\nclass DualClockSyncReadMem[T <: Data](nWords: Long, gen: T, initFile: Option[String] = None) {\n private val dcram = Module(new DcRamInline(nWords, gen.getWidth, initFile))\n\n /**\n * The access operation of port a\n * @param clock Clock of port a\n * @param addr Address of the operation (both read and write)\n * @param data Data to be written\n * @param wen Write enable\n * @return Data read out\n */\n def access_a(clock: Clock, addr: UInt, data: T, wen: Bool): T = {\n dcram.io.clock_a := clock\n dcram.io.addr_a := addr\n dcram.io.din_a := data.asUInt\n dcram.io.wr_a := wen\n dcram.io.qout_a.asTypeOf(gen)\n }\n /**\n * The access operation of port b\n * @param clock Clock of port b\n * @param addr Address of the operation (both read and write)\n * @param data Data to be written\n * @param wen Write enable\n * @return Data read out\n */\n def access_b(clock: Clock, addr: UInt, data: T, wen: Bool): T = {\n dcram.io.clock_b := clock\n dcram.io.addr_b := addr\n dcram.io.din_b := data.asUInt\n dcram.io.wr_b := wen\n dcram.io.qout_b.asTypeOf(gen)\n }\n}\n\nobject DualClockSyncReadMem {\n /**\n * Create a True Dual Clock Synchronous Read Memory instance.\n * @param nWords Number of words in RAM\n * @param gen Generator of data\n * @param initFile Hex data file for initializing RAM by internally using\n * verilog system call `$readmemh()`, default `None` for no\n * initializing.\n * @tparam T Type of data\n * @return The instance created.\n * @note\n * - Write First inner each port.\n * @example {{{\n * val dcram = DualClockSyncReadMem(256, UInt(32.W))(clock)\n * io.port_a.rdata := dcram.access_a(\n * io.port_a.clock,\n * io.port_a.addr ,\n * io.port_a.wdata,\n * io.port_a.wen )\n * io.port_b.rdata := dcram.access_b(\n * io.port_b.clock,\n * io.port_b.addr ,\n * io.port_b.wdata,\n * io.port_b.wen )\n * }}}\n */\n def apply[T <: Data](nWords: Long, gen: T, initFile: Option[String] = None): DualClockSyncReadMem[T] = {\n new DualClockSyncReadMem(nWords, gen, initFile)\n }\n}\n\n/**\n * Represent a hardware module of Single Port RAM, with the behavior of reading\n * when writing is Undefined.\n * @param nWords Number of Words (elements) in RAM\n * @param gen Generator of Data\n * @tparam T Type of Data\n * @note\n * - Normally, you should use chisel3.SyncReadMem directly in your\n * module, instead of using this.\n * - Use chisel3.util.experimental.loadMemoryFromFileInline() if initializing\n * is needed.\n */\nclass SpRam[T <: Data](nWords: Long, gen: T) extends Module {\n require(nWords > 0)\n override def desiredName = s\"${super.desiredName}_${nWords}_x_${gen.typeName}\"\n\n val io = IO(new RamIO.RW(nWords, gen))\n // It's recommended using chisel3.SyncReadMem directly in code,\n // No need to wrap a module like this.\n val mem = SyncReadMem(nWords, gen, SyncReadMem.Undefined)\n io.dout := mem.read(io.addr)\n when(io.we) {\n mem.write(io.addr, io.din)\n }\n}\n\n/**\n * Represent a hardware module of Single Port RAM, with the behavior of reading\n * when writing is Read First.\n * @param nWords Number of Words (elements) in RAM\n * @param gen Generator of Data\n * @param initFile Hex data file for initializing RAM by internally using\n * verilog system call `$readmemh()`, default `None` for no\n * initializing.\n * @tparam T Type of Data\n * @note Normally, you should use SyncReadMemReadFirst directly in your\n * module, instead of using this.\n */\nclass SpRamRf[T <: Data](nWords: Long, gen: T, initFile: Option[String] = None) extends Module {\n require(nWords > 0)\n override def desiredName = s\"${super.desiredName}_${nWords}_x_${gen.typeName}\"\n\n val io = IO(new RamIO.RW(nWords, gen))\n val spramrf = SyncReadMemReadFirst(nWords, gen, initFile)(clock)\n io.dout := spramrf.read(io.addr)\n spramrf.write(io.addr, io.din, io.we)\n}\n\n/**\n * Represent a hardware module of Single Port RAM, with the behavior of reading\n * when writing is Write First.\n * @param nWords Number of Words (elements) in RAM\n * @param gen Generator of Data\n * @param initFile Hex data file for initializing RAM by internally using\n * verilog system call `$readmemh()`, default `None` for no\n * initializing.\n * @tparam T Type of Data\n * @note Normally, you should use SyncReadMemWriteFirst directly in your\n * module, instead of using this.\n */\nclass SpRamWf[T <: Data](nWords: Long, gen: T, initFile: Option[String] = None) extends Module {\n require(nWords > 0)\n override def desiredName = s\"${super.desiredName}_${nWords}_x_${gen.typeName}\"\n\n val io = IO(new RamIO.RW(nWords, gen))\n val spramwf = SyncReadMemWriteFirst(nWords, gen, initFile)(clock)\n io.dout := spramwf.read(io.addr)\n spramwf.write(io.addr, io.din, io.we)\n}\n\n/**\n * Represent a hardware module of Single Port Asynchronous Read RAM.\n * @param nWords Number of Words (elements) in RAM\n * @param gen Generator of Data\n * @param initFile Hex data file for initializing RAM by internally using\n * verilog system call `$readmemh()`, default `None` for no\n * initializing.\n * @tparam T Type of Data\n * @note Normally, you should use AsyncReadMem directly in your module,\n * instead of using this.\n */\nclass SpRamRa[T <: Data](nWords: Long, gen: T, initFile: Option[String] = None) extends Module {\n require(nWords > 0)\n override def desiredName = s\"${super.desiredName}_${nWords}_x_${gen.typeName}\"\n\n val io = IO(new RamIO.RW(nWords, gen))\n val spramra = AsyncReadMem(nWords, gen, initFile)(clock)\n io.dout := spramra.read(io.addr)\n spramra.write(io.addr, io.din, io.we)\n}\n\n/**\n * Represent a hardware module of Simple Dual Port Synchronous Read RAM,\n * with the behavior of reading when writing is Undefined.\n * @param nWords Number of Words (elements) in RAM\n * @param gen Generator of Data\n * @tparam T Type of Data\n * @note\n * - Normally, you should use chisel3.SyncReadMem directly in your\n * module, instead of using this.\n * - Use chisel3.util.experimental.loadMemoryFromFileInline() if initializing\n * is needed.\n */\nclass SdpRam[T <: Data](nWords: Long, gen: T) extends Module {\n require(nWords > 0)\n override def desiredName = s\"${super.desiredName}_${nWords}_x_${gen.typeName}\"\n\n val io = IO(new Bundle {\n val r = new RamIO.R(nWords, gen)\n val w = new RamIO.W(nWords, gen)\n })\n val sdpram = SyncReadMem(nWords, gen)\n io.r.dout := sdpram.read(io.r.addr)\n when(io.w.en) {\n sdpram.write(io.w.addr, io.w.din)\n }\n}\n\n/**\n * Represent a hardware module of Simple Dual Port Synchronous Read RAM,\n * with the behavior of reading when writing is Read First.\n * @param nWords Number of Words (elements) in RAM\n * @param gen Generator of Data\n * @param initFile Hex data file for initializing RAM by internally using\n * verilog system call `$readmemh()`, default `None` for no\n * initializing.\n * @tparam T Type of Data\n * @note Normally, you should use SyncReadMemReadFirst directly in your module,\n * instead of using this.\n */\nclass SdpRamRf[T <: Data](nWords: Long, gen: T, initFile: Option[String] = None) extends Module {\n require(nWords > 0)\n override def desiredName = s\"${super.desiredName}_${nWords}_x_${gen.typeName}\"\n\n val io = IO(new Bundle {\n val w = new RamIO.W(nWords, gen)\n val r = new RamIO.R(nWords, gen)\n })\n val sdpramrf = SyncReadMemReadFirst(nWords, gen, initFile)(clock)\n io.r.dout := sdpramrf.read(io.r.addr)\n sdpramrf.write(io.w.addr, io.w.din, io.w.en)\n}\n\n/**\n * Represent a hardware module of Simple Dual Port Synchronous Read RAM,\n * with the behavior of reading when writing is Write First.\n * @param nWords Number of Words (elements) in RAM\n * @param gen Generator of Data\n * @param initFile Hex data file for initializing RAM by internally using\n * verilog system call `$readmemh()`, default `None` for no\n * initializing.\n * @tparam T Type of Data\n * @note Normally, you should use SyncReadMemWriteFirst directly in your module,\n * instead of using this.\n */\nclass SdpRamWf[T <: Data](nWords: Long, gen: T, initFile: Option[String] = None) extends Module {\n require(nWords > 0)\n override def desiredName = s\"${super.desiredName}_${nWords}_x_${gen.typeName}\"\n\n val io = IO(new Bundle {\n val w = new RamIO.W(nWords, gen)\n val r = new RamIO.R(nWords, gen)\n })\n val sdpramwf = SyncReadMemWriteFirst(nWords, gen, initFile)(clock)\n io.r.dout := sdpramwf.read(io.r.addr)\n sdpramwf.write(io.w.addr, io.w.din, io.w.en)\n}\n\n/**\n * Represent a hardware module of Simple Dual Port Asynchronous Read RAM.\n * @param nWords Number of Words (elements) in RAM\n * @param gen Generator of Data\n * @param initFile Hex data file for initializing RAM by internally using\n * verilog system call `$readmemh()`, default `None` for no\n * initializing.\n * @tparam T Type of Data\n * @note Normally, you should use AsyncReadMem directly in your module,\n * instead of using this.\n */\nclass SdpRamRa[T <: Data](nWords: Long, gen: T, initFile: Option[String] = None) extends Module {\n require(nWords > 0)\n override def desiredName = s\"${super.desiredName}_${nWords}_x_${gen.typeName}\"\n\n val io = IO(new Bundle {\n val w = new RamIO.W(nWords, gen)\n val r = new RamIO.R(nWords, gen)\n })\n val sdpramra = AsyncReadMem(nWords, gen, initFile)(clock)\n io.r.dout := sdpramra.read(io.r.addr)\n sdpramra.write(io.w.addr, io.w.din, io.w.en)\n}\n\n/**\n * Represent a hardware module of True Dual Port Synchronous Read RAM.\n * @param nWords Number of Words (elements) in RAM\n * @param gen Generator of Data\n * @param initFile Hex data file for initializing RAM by internally using\n * verilog system call `$readmemh()`, default `None` for no\n * initializing.\n * @tparam T Type of Data\n * @note\n * - Normally, you should use DualPortSyncReadMem directly in your module,\n * instead of using this.\n * - Write First inner each port.\n * - Read First between ports, but not guaranteed when inferred using\n * blockRAM by FPGA synthesizer, it's the user's responsibilities to\n * check the actual behavior or guarantee no simultaneously access to\n * same address at both ports.\n */\nclass DpRam[T <: Data](nWords: Long, gen: T, initFile: Option[String] = None) extends Module {\n require(nWords > 0)\n override def desiredName = s\"${super.desiredName}_${nWords}_x_${gen.typeName}\"\n\n val io = IO(new Bundle {\n val a = new RamIO.RW(nWords, gen)\n val b = new RamIO.RW(nWords, gen)\n })\n val dpram = DualPortSyncReadMem(nWords, gen, initFile)(clock)\n io.a.dout := dpram.access_a(io.a.addr, io.a.din, io.a.we)\n io.b.dout := dpram.access_b(io.b.addr, io.b.din, io.b.we)\n}\n\n/**\n * Represent a hardware module of Simple Dual Clock Synchronous Read RAM.\n * @param nWords Number of Words in RAM\n * @param gen Generator of Data\n * @tparam T Type of Data\n * @note\n * - Normally, you should use chisel3.SyncReadMem directly in your module,\n * instead of using this.\n * - Use chisel3.util.experimental.loadMemoryFromFileInline() if initializing\n * is needed.\n */\nclass SdcRam[T <: Data](nWords: Long, gen: T) extends RawModule {\n require(nWords > 0)\n override def desiredName = s\"${super.desiredName}_${nWords}_x_${gen.typeName}\"\n\n val io = IO(new Bundle {\n val a = new RamIO.CR(nWords, gen)\n val b = new RamIO.CW(nWords, gen)\n })\n val sdcram = SyncReadMem(nWords, gen)\n io.a.dout := sdcram.read(io.a.addr, io.a.clock)\n when(io.b.en) {\n sdcram.write(io.b.addr, io.b.din, io.b.clock)\n }\n}\n\n/**\n * Represent a hardware module of True Dual Clock Synchronous Read RAM.\n * @param nWords Number of Words (elements) in RAM\n * @param gen Generator of Data\n * @param initFile Hex data file for initializing RAM by internally using\n * verilog system call `$readmemh()`, default `None` for no\n * initializing.\n * @tparam T Type of Data\n * @note\n * - Normally, you should use DualClockSyncReadMem directly in your\n * module, instead of using this.\n * - Write First inner each port.\n */\nclass DcRam[T <: Data](nWords: Long, gen: T, initFile: Option[String] = None) extends RawModule {\n require(nWords > 0)\n", "right_context": "\n val io = IO(new Bundle {\n val a = new RamIO.CRW(nWords, gen)\n val b = new RamIO.CRW(nWords, gen)\n })\n val dcram = DualClockSyncReadMem(nWords, gen, initFile)\n io.a.dout := dcram.access_a(io.a.clock, io.a.addr, io.a.din, io.a.we)\n io.b.dout := dcram.access_b(io.b.clock, io.b.addr, io.b.din, io.b.we)\n}\n\npackage examples {\n /**\n * A Single Port RAM example for emitting verilog directly,\n * with the behavior of reading when writing is Undefined.\n */\n class spram_example extends Module {\n val nWords = 256\n val dType = UInt(8.W)\n val io = IO(new RamIO.RW(nWords, dType))\n val ram = Module(new SpRam(nWords, dType))\n io <> ram.io\n }\n\n /**\n * A Single Port RAM example for emitting verilog directly,\n * with the behavior of reading when writing is Undefined,\n * with initializing.\n */\n class spram_with_init_example extends Module {\n val nWords = 256\n val width = 8\n val dType = UInt(width.W)\n val io = IO(new RamIO.RW(nWords, dType))\n val ram = Module(new SpRam(nWords, dType))\n io <> ram.io\n\n val fn: String = s\"${desiredName}_meminit_sine${nWords}x${width}bit.dat\"\n val fnWithPath: String = s\"${ProjectInfo.BuildInfo.targetVerilogDir}/${fn}\"\n MemoryInitFiles.Write(fnWithPath, MemoryInitFiles.SineWava(nWords, width), width)\n chisel3.util.experimental.loadMemoryFromFileInline(ram.mem, fn)\n }\n\n /**\n * A Single Port RAM example for emitting verilog directly,\n * with the behavior of reading when writing is Read First.\n */\n class spramrf_example extends Module {\n val nWords = 256\n val dType = UInt(8.W)\n val io = IO(new RamIO.RW(nWords, dType))\n val ram = Module(new SpRamRf(nWords, dType))\n io <> ram.io\n }\n\n /**\n * A Single Port RAM example for emitting verilog directly,\n * with the behavior of reading when writing is Read First,\n * with initializing.\n */\n class spramrf_with_init_example extends Module {\n val nWords = 256\n val width = 8\n val dType = UInt(width.W)\n\n val fn = s\"${desiredName}_meminit_unsigned_cosine${nWords}x${width}bit.dat\"\n val fnWithPath = s\"${ProjectInfo.BuildInfo.targetVerilogDir}/${fn}\"\n MemoryInitFiles.Write(fnWithPath, MemoryInitFiles.CosineWave(nWords, width, isSigned = false), width)\n\n val io = IO(new RamIO.RW(nWords, dType))\n val ram = Module(new SpRamRf(nWords, dType, Some(fn)))\n io <> ram.io\n }\n\n /**\n * A Single Port RAM example for emitting verilog directly,\n * with the behavior of reading when writing is Write First.\n */\n class spramwf_example extends Module {\n val nWords = 256\n val dType = UInt(8.W)\n val io = IO(new RamIO.RW(nWords, dType))\n val ram = Module(new SpRamWf(nWords, dType))\n io <> ram.io\n }\n\n /**\n * A Single Port Asynchronous Read RAM example for emitting verilog\n * directly.\n */\n class spramra_example extends Module {\n val nWords = 256\n val dType = UInt(8.W)\n val io = IO(new RamIO.RW(nWords, dType))\n val ram = Module(new SpRamRa(nWords, dType))\n io <> ram.io\n }\n\n /**\n * A Simple Dual Port RAM example for emitting verilog directly,\n * with the behavior of reading when writing is Undefined.\n */\n class sdpram_example extends Module {\n val nWords = 256\n val dType = UInt(8.W)\n val io = IO(new Bundle {\n val r = new RamIO.R(nWords, dType)\n val w = new RamIO.W(nWords, dType)\n })\n val ram = Module(new SdpRam(nWords, dType))\n io <> ram.io\n }\n\n /**\n * A Simple Dual Port RAM example for emitting verilog directly,\n * with the behavior of reading when writing is Read First.\n */\n class sdpramrf_example extends Module {\n val nWords = 256\n val dType = UInt(8.W)\n val io = IO(new Bundle {\n val r = new RamIO.R(nWords, dType)\n val w = new RamIO.W(nWords, dType)\n })\n val ram = Module(new SdpRamRf(nWords, dType))\n io <> ram.io\n }\n\n /**\n * A Simple Dual Port RAM example for emitting verilog directly,\n * with the behavior of reading when writing is Write First.\n */\n class sdpramwf_example extends Module {\n val nWords = 256\n val dType = UInt(8.W)\n val io = IO(new Bundle {\n val r = new RamIO.R(nWords, dType)\n val w = new RamIO.W(nWords, dType)\n })\n val ram = Module(new SdpRamWf(nWords, dType))\n io <> ram.io\n }\n\n /**\n * A Simple Dual Port Asynchronous Read RAM example for emitting verilog\n * directly.\n */\n class sdpramra_example extends Module {\n val nWords = 256\n val dType = UInt(8.W)\n val io = IO(new Bundle {\n val r = new RamIO.R(nWords, dType)\n val w = new RamIO.W(nWords, dType)\n })\n val ram = Module(new SdpRamRa(nWords, dType))\n io <> ram.io\n }\n\n /**\n * A True Dual Port Synchronous Read RAM example for emitting verilog\n * directly.\n */\n class dpram_example extends Module {\n val nWords = 256\n val dType = UInt(8.W)\n val io = IO(new Bundle {\n val a = new RamIO.RW(nWords, dType)\n val b = new RamIO.RW(nWords, dType)\n })\n val ram = Module(new DpRam(nWords, dType))\n io <> ram.io\n }\n\n /**\n * A Simple Dual Clock Synchronous Read RAM example for emitting verilog\n * directly.\n */\n class sdcram_example extends RawModule {\n val nWords = 256\n val dType = UInt(8.W)\n val io = IO(new Bundle {\n val a = new RamIO.CR(nWords, dType)\n val b = new RamIO.CW(nWords, dType)\n })\n val ram = Module(new SdcRam(nWords, dType))\n io <> ram.io\n }\n\n /**\n * A True Dual Clock Synchronous Read RAM example for emitting verilog\n * directly.\n */\n class dcram_example extends RawModule {\n val nWords = 256\n val dType = UInt(8.W)\n val io = IO(new Bundle {\n val a = new RamIO.CRW(nWords, dType)\n val b = new RamIO.CRW(nWords, dType)\n })\n val ram = Module(new DcRam(nWords, dType))\n io <> ram.io\n }\n}\n", "groundtruth": " override def desiredName = s\"${super.desiredName}_${nWords}_x_${gen.typeName}\"\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "FPGA-Application-Development-and-Simulation", "path": "FPGA-Application-Development-and-Simulation/chisel/src/main/scala/loywong/scfifo.scala", "left_context": "/*\n * MIT License\n *\n * Copyright (c) 2025 loykylewong (loywong@gmail.com)\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n */\n\npackage loywong\n\nimport chisel3._\nimport chisel3.util._\n\n/**\n * Collection of native FIFO interfaces.\n */\nobject FifoIO {\n /**\n * Interface of fifo writer.\n * @param gen Generator of data\n * @tparam T Type of data\n */\n class WriterIO[+T <: Data]\n (gen: T = UInt(8.W)) extends Bundle {\n val data = Output(gen)\n val write = Output(Bool())\n val full = Input(Bool())\n }\n\n /**\n * Create an interface of fifo writer\n * @param gen Generator of data\n * @tparam T Type of data\n * @return Interface created\n */\n def Writer[T <: Data](gen: T = UInt(8.W)) = {\n new WriterIO(gen)\n }\n\n /**\n * Create an interface of fifo writee (which is in FIFO)\n * @param gen Generator of data\n * @tparam T Type of data\n * @return Interface created\n */\n def Writee[T <: Data](gen: T = UInt(8.W)) = {\n Flipped(new WriterIO(gen))\n }\n\n /**\n * Interface of fifo reader.\n * @param gen Generator of data\n * @tparam T Type of data\n */\n class ReaderIO[+T <: Data]\n (gen: T = UInt(8.W)) extends Bundle {\n val data = Input(gen)\n val read = Output(Bool())\n val empty = Input(Bool())\n }\n\n /**\n * Create an interface of fifo reader\n * @param gen Generator of data\n * @tparam T Type of data\n * @return Interface created\n */\n def Reader[T <: Data](gen: T = UInt(8.W)) = {\n new ReaderIO(gen)\n }\n\n /**\n * Create an interface of fifo readee (which is in FIFO)\n * @param gen Generator of data\n * @tparam T Type of data\n * @return Interface created\n */\n def Readee[T <: Data](gen: T = UInt(8.W)) = {\n Flipped(new ReaderIO(gen))\n }\n\n /**\n * Interface for providing counter information of FIFO\n * @param width Width of Counter, must be >= the actual width\n * of those counters in FIFO\n * @param hasWriteReadCount True if `writeCnt` and `readCnt` are existed\n */\n class CounterIO(width: Int, hasWriteReadCount: Boolean = false) extends Bundle {\n val dataCnt = Output(UInt(width.W))\n val writeCnt = if (hasWriteReadCount) Some(Output(UInt(width.W))) else None\n val readCnt = if (hasWriteReadCount) Some(Output(UInt(width.W))) else None\n }\n\n /**\n * Create an interface of counter information provider (which is in FIFO)\n * @param width Width of Counter, must be >= the actual width\n * of those counters in FIFO\n * @param hasWriteReadCount True if `writeCnt` and `readCnt` are existed\n * @return The interface created\n */\n def CntProvider(width: Int, hasWriteReadCount: Boolean = false) = {\n new CounterIO(width, hasWriteReadCount)\n }\n\n /**\n * Create an interface of counter information User\n * @param width Width of Counter, must be >= the actual width\n * of those counters in FIFO\n * @param hasWriteReadCount True if `writeCnt` and `readCnt` are existed\n * @return The interface created\n */\n def CntUser(width: Int, hasWriteReadCount: Boolean = false) = {\n Flipped(new CounterIO(width, hasWriteReadCount))\n }\n}\n\n/**\n * Represent a hardware Single Clock FIFO module.\n * @param gen Generator of data\n * @param addrWidth Width of inner address, FIFO depth = 2**addrWidth - 1\n * @param hasDataCnt True if `dataCnt` are needed\n * @param hasWrRdCnt True if `writeCnt` and `readCnt` are needed\n * @tparam T Type of data\n * @note If `hasWrRdCnt` is true, `hasDataCnt` must also be true.\n */\nclass ScFifo2[T <: Data](gen: T, addrWidth: Int,\n hasDataCnt: Boolean = false,\n hasWrRdCnt: Boolean = false) extends Module {\n require(!(!hasDataCnt && hasWrRdCnt), \"In ScFifo2, when hasDataCnt == false, hasWrRdCnt is not allowed to be true!\")\n", "right_context": "\n val io = IO(new Bundle {\n val w = FifoIO.Writee(gen)\n val r = FifoIO.Readee(gen)\n val c = if(hasDataCnt) Some(FifoIO.CntProvider(addrWidth, hasWrRdCnt)) else None\n })\n\n val m: Int = 1 << addrWidth\n val capacity: Int = m - 1\n val (wr_cnt, _) = Counter(io.w.write, m)\n val (rd_cnt, _) = Counter(io.r.read, m)\n val data_cnt = WireDefault(wr_cnt - rd_cnt)\n\n io.c.foreach(c => {\n c.dataCnt := data_cnt\n c.readCnt.foreach(_ := rd_cnt)\n c.writeCnt.foreach(_ := wr_cnt)\n })\n io.w.full := data_cnt === capacity.U\n io.r.empty := data_cnt === 0.U\n\n val rd_dly = RegNext(io.r.read, false.B)\n\n val the_ram = SyncReadMem(m, gen)\n when(io.w.write) { the_ram.write(wr_cnt, io.w.data) }\n val qout_b = the_ram.read(rd_cnt)\n\n val qout_b_reg = RegEnable(qout_b, 0.U.asTypeOf(gen), rd_dly)\n io.r.data := Mux(rd_dly, qout_b, qout_b_reg)\n}\n\nobject ScFifo2 {\n /**\n * Create an instance of Single Clock FIFO module.\n * @param gen Generator of data\n * @param addrWidth Width of inner address, FIFO depth = 2**addrWidth-1\n * @param hasDataCnt True if `dataCnt` are needed\n * @param hasWrRdCnt True if `writeCnt` and `readCnt` are needed\n * @tparam T Type of data\n * @return The instance created\n * @note If `hasWrRdCnt` is true, `hasDataCnt` must also be true.\n * @example {{{\n * val fifo = ScFifo2(UInt(8.W), 10, true)\n * io.fifo_wr <> fifo.w\n * io.fifo_rd <> fifo.c\n * io.fifo_cnt <> fifo.c.get // c is Option[FifoIO.CounterIO]\n * }}}\n */\n def apply[T <: Data](gen: T, addrWidth: Int, hasDataCnt: Boolean = false, hasWrRdCnt: Boolean = false) = {\n Module(new ScFifo2(gen, addrWidth, hasDataCnt, hasWrRdCnt))\n }\n\n /**\n * Create an instance of Single Clock FIFO module, and make some\n * connections.\n * @param gen Generator of data\n * @param addrWidth Width of inner address, FIFO depth = 2**addrWidth-1\n * @param hasDataCnt True if `dataCnt` are needed\n * @param hasWrRdCnt True if `writeCnt` and `readCnt` are needed\n * @param wr The FifoIO.Writer to be connected to FIFO\n * @tparam T Type of data\n * @return (readee, cnt) :\n * readee: the readee(FifoIO.Readee) of the FIFO\n * cnt : the cnt(FifoIO.CntProvider) of the FIFO\n * @example {{{\n * val (rd, cnt) = ScFifo2.withConnect(UInt(8.W), 10, true)(io.fifo_writer)\n * io.fifo_reader <> rd\n * io.fifo_cnt <> cnt.get // cnt is Option[FifoIO.CounterIO]\n * }}}\n */\n def withConnect[T <: Data](gen: T, addrWidth: Int, hasDataCnt: Boolean = false, hasWrRdCnt: Boolean = false)(wr: FifoIO.WriterIO[T]) = {\n val scfifo2 = Module(new ScFifo2(gen, addrWidth, hasDataCnt, hasWrRdCnt))\n scfifo2.io.w <> wr\n (scfifo2.io.r, scfifo2.io.c)\n }\n}\n\npackage examples {\n /**\n * A scfifo2 example for emitting verilog.\n */\n class scfifo2_example extends Module {\n val dType = UInt(8.W)\n val addrWidth = 10\n val hasDataCnt = true\n val hasWrRdCnt = true\n val io = IO(new Bundle {\n val w = FifoIO.Writee(dType)\n val r = FifoIO.Readee(dType)\n val c = if (hasDataCnt) Some(FifoIO.CntProvider(addrWidth, hasWrRdCnt)) else None\n })\n val (r, c) = ScFifo2.withConnect(dType, addrWidth, hasDataCnt, hasWrRdCnt)(io.w)\n io.r <> r\n if (hasDataCnt) {\n io.c.get <> c.get\n }\n }\n}\n", "groundtruth": " override def desiredName = s\"${super.desiredName}_${gen.typeName}\"\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "FPGA-Application-Development-and-Simulation", "path": "FPGA-Application-Development-and-Simulation/chisel/src/main/scala/loywong/shift_reg.scala", "left_context": "/*\n * MIT License\n *\n * Copyright (c) 2025 loykylewong (loywong@gmail.com)\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n */\n\npackage loywong\n\nimport chisel3._\n\n/*class ShiftReg(nBits: Int) extends Module {\n val io = IO(new Bundle {\n val shift = Input(Bool())\n val load = Input(Bool())\n val din = Input(UInt(nBits.W))\n val sin = Input(Bool())\n val qout = Output(UInt(nBits.W))\n })\n val regs = RegInit(0.U(nBits.W))\n /*regs := MuxCase(regs, Seq(\n ((io.shift ## io.load) === \"b10\".U) -> regs(nBits - 2, 0) ## io.sin,\n ((io.shift ## io.load) === \"b01\".U) -> io.din,\n ((io.shift ## io.load) === \"b11\".U) -> io.din(nBits - 2, 0) ## io.sin\n ))*/\n switch (io.shift ## io.load) {\n is(\"b10\".U) { regs := regs(nBits - 2, 0) ## io.sin }\n is(\"b01\".U) { regs := io.din }\n is(\"b11\".U) { regs := io.din(nBits - 2, 0) ## io.sin }\n }\n io.qout := regs\n}*/\n\nclass ShiftReg(nBits: Int) {\n val regs = RegInit(0.U(nBits.W))\n def load(din: UInt): UInt = {\n regs := din\n regs\n }\n def shift(sin: Bool): UInt = {\n regs := regs(nBits - 2, 0) ## sin\n regs\n }\n", "right_context": "}\n\npackage examples {\n class shift_reg_example extends Module {\n val dw = 10\n val io = IO(new Bundle {\n val shift = Input(Bool())\n val load = Input(Bool())\n val din = Input(UInt(dw.W))\n val sin = Input(Bool())\n val qout = Output(UInt(dw.W))\n })\n val sr = new ShiftReg(dw)\n when(io.shift) {\n sr.shift(io.sin)\n }\n when(io.load) {\n sr.load(io.din)\n }\n io.qout := sr.qout\n }\n}\n", "groundtruth": " def qout: UInt = regs\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "FPGA-Application-Development-and-Simulation", "path": "FPGA-Application-Development-and-Simulation/chisel/src/main/scala/loywong/str_common.scala", "left_context": "/*\n * MIT License\n *\n * Copyright (c) 2025 loykylewong (loywong@gmail.com)\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n */\n\npackage loywong\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.requireIsChiselType\n// import chisel3.experimental.prefix\nimport loywong.util._\n\n/**\n * In down-stream port of StrDateWidthConverter, StrKeepRemover and some other\n * modules, use `id` associated with which byte as output in a beat?\n * - LowestByte: Use the `id` input with the lowest output byte\n * - HighestByte: Use the `id` input with the highest output byte\n */\nobject StrIdAssociation extends Enumeration {\n val LowestByte, HighestByte = Value\n}\n/**\n * In down-stream port of StrDateWidthConverter, StrKeepRemover and some other\n * modules, use `dest` associated with which byte as output in a beat?\n * - LowestByte: Use the `dest` input with the lowest output byte\n * - HighestByte: Use the `dest` input with the highest output byte\n */\nobject StrDestAssociation extends Enumeration {\n val LowestByte, HighestByte = Value\n}\n\n/**\n * In down-stream port of StrDateWidthConverter, StrKeepRemover and some other\n * modules, use `user` associated with which byte as output in a beat?\n * - LowestByte: Use the `user` input with the lowest output byte\n * - HighestByte: Use the `user` input with the highest output byte\n * - SpreadInByte: Split `user` equally and associate each `user` bit slices\n * to each data bytes, require width of `user` in bits is\n * multiple of data width in bytes\n */\nobject StrUserAssociation extends Enumeration {\n val LowestByte, HighestByte, SpreadInBytes = Value\n}\n\n// Inherit this trait for stream bits (IrrevocableIO.bits) is recommended\ntrait StrBits extends Bundle\n\n// Inherit this trait if data exist in stream bits\ntrait StrHasData extends StrBits {\n def data: Bits // CAUTION: Use `lazy val` when overriding\n}\n\n// Inherit this trait if strb (and data) signal exist in stream bits\ntrait StrHasStrb extends StrHasData {\n def strb: UInt // CAUTION: Use `lazy val` when overriding\n require(data.getWidth == strb.getWidth * 8,\n s\"In Str Bits, data width must be 8x strb width, but got ${data.getWidth} and ${strb.getWidth}.\")\n}\n\n// Inherit this trait if keep (and data) signal exist in stream bits\ntrait StrHasKeep extends StrHasData {\n def keep: UInt // CAUTION: Use `lazy val` when overriding\n require(data.getWidth == keep.getWidth * 8,\n s\"In Str Bits, data width must be 8x keep width, but got ${data.getWidth} and ${keep.getWidth}.\")\n}\n\n// Inherit this trait if last signal exist in stream bits\ntrait StrHasLast extends StrBits {\n def last: Bool\n}\n\n// Inherit this trait if id signal exist in stream bits\ntrait StrHasId extends StrBits {\n val idAssociation: StrIdAssociation.Value = StrIdAssociation.LowestByte\n def id: UInt\n}\n\n// Inherit this trait if dest signal exist in stream bits\ntrait StrHasDest extends StrBits {\n val destAssociation: StrDestAssociation.Value = StrDestAssociation.LowestByte\n def dest: UInt\n}\n\n// Inherit this trait if user signal exist in stream bits\ntrait StrHasUser extends StrBits {\n val userAssociation: StrUserAssociation.Value = StrUserAssociation.SpreadInBytes\n def user: Bits\n}\n\n/**\n * Represents a hardware stream forward reg-slice with configurable data type.\n *\n * Can be used to break up combination data path for better timing.\n *\n * @note Notes:\n * 1. `ready` path can not be broken by this, use `str_birs` instead.\n *\n * @tparam T Data type of payload (IrrevocableIO.bits)\n * @param gen Data type generator for payload (e.g. UInt(8.W))\n * @param init Initialization function for reset value of payload\n */\nclass StrFrs[+T <: Data]\n(gen: T = Bool(), init: Option[() => T] = None) extends Module {\n requireIsChiselType(gen)\n override def desiredName = s\"${super.desiredName}_${gen.typeName}\"\n\n val io = IO(new Bundle {\n val us = Flipped(Irrevocable(gen))\n val ds = Irrevocable(gen)\n })\n\n io.us.ready := io.ds.ready || !io.ds.valid\n\n val ds_valid = RegInit(false.B)\n ds_valid := MuxCase(ds_valid, Seq(\n io.us.fire -> true.B,\n io.ds.ready -> false.B\n ))\n io.ds.valid := ds_valid\n\n val ds_bits = init match {\n case Some(f) => RegInit(f())\n case None => RegInit(0.U.asTypeOf(gen))\n }\n when(io.us.fire) { ds_bits := io.us.bits }\n io.ds.bits := ds_bits\n}\n\n/**\n * Represents a hardware stream bi-direction reg-slice with configurable data\n * type.\n *\n * Can be used to break up combination data path and `ready` for better timing.\n *\n * @tparam T Data type of payload (IrrevocableIO.bits)\n * @param gen Data type generator for payload (e.g. UInt(8.W))\n * @param init Initialization function for reset value of payload\n */\nclass StrBirs[T <: Data]\n(gen: T = Bool(), init: Option[() => T] = None) extends Module {\n requireIsChiselType(gen)\n override def desiredName = s\"${super.desiredName}_${gen.typeName}\"\n\n val io = IO(new Bundle {\n val us = Flipped(Irrevocable(gen))\n val ds = Irrevocable(gen)\n })\n\n val ush = io.us.fire\n val dsh = io.ds.fire\n\n val buffer = init match {\n case Some(f) => RegInit(VecInit(f(), f()))\n case None => RegInit(VecInit(Seq.fill(2)(0.U.asTypeOf(gen))))\n }\n\n val wp = RegInit(0.U(1.W))\n val rp = RegInit(0.U(1.W))\n val dc = RegInit(0.U(2.W))\n\n io.us.ready := dc < 2.U(2.W)\n io.ds.valid := dc > 0.U(2.W)\n\n when(ush) { wp := ~wp }\n when(dsh) { rp := ~rp }\n\n switch( ush ## dsh ) {\n is(\"b10\".U) { dc := dc + 1.U(2.W) }\n is(\"b01\".U) { dc := dc - 1.U(2.W) }\n }\n\n when(ush) { buffer(wp) := io.us.bits }\n io.ds.bits := buffer(rp)\n}\n\n/**\n * Represents a hardware multi-upstream multi-downstream handshake logic module.\n *\n * Use this for synchronizing multiple upstreams and multiple downstreams.\n *\n * @note Notes:\n * - This is a pure combination logic module.\n * - Deadlock occurs if d.s. ready depends on u.s. valid.\n * - Deadlock occurs if series 2 str_hscombs.\n * - Follow a str_fifo or a reg-slice (str_firs or str_birs) can break\n * up deadlock.\n * @param nUS Number of upstream port(s)\n * @param nDS Number of downstream port(s)\n */\nclass StrHsCombModule (nUS: Int = 2, nDS: Int = 2) extends Module {\n\n require(nUS > 0 && nDS > 0,\n s\"In ${desiredName}, nUS and nDS must be > 0, got ${nUS} and ${nDS}.\")\n\n override def desiredName = s\"${super.desiredName}_${nUS}to${nDS}\"\n\n val io = IO(new Bundle {\n val us_valid = Input(UInt(nUS.W))\n val us_ready = Output(UInt(nUS.W))\n val ds_valid = Output(UInt(nDS.W))\n val ds_ready = Input(UInt(nDS.W))\n })\n\n val ds_valid = Wire(Vec(nDS, Bool()))\n val dre = Wire(Vec(nDS, UInt(nDS.W)))\n for(i:Int <- 0 until nDS) {\n dre(i) := io.ds_ready | (1.U(nDS.W) << i).asUInt\n ds_valid(i) := (io.us_valid ## dre(i)).andR\n }\n io.ds_valid := ds_valid.asUInt\n\n val us_ready = Wire(Vec(nUS, Bool()))\n val uve = Wire(Vec(nUS, UInt(nUS.W)))\n for(i:Int <- 0 until nUS) {\n uve(i) := io.us_valid | (1.U(nUS.W) << i).asUInt\n us_ready(i) := (io.ds_ready ## uve(i)).andR\n }\n io.us_ready := us_ready.asUInt\n}\n\n/**\n * A utility class for ease of connecting StrHsCombModule.\n * @param nUS Number of upstream port(s)\n * @param nDS Number of downstream port(s)\n * @note Notes:\n * - The StrHsCombModule is a pure combination logic module.\n * - Deadlock may occur if d.s. ready depends on u.s. valid.\n * - Deadlock may occur if series 2 StrHsCombs.\n * - Follow a str_fifo or a reg-slice (str_firs or str_birs) can break\n * up deadlock.\n */\nclass StrHsComb (nUS: Int, nDS: Int) {\n val cb = Module(new StrHsCombModule(nUS, nDS))\n\n /**\n * Connect valid(s) of up-stream(s)\n *\n * @param valids Valid(s) of up-stream(s)\n * @example {{{\n * hscmb.usValids(us0.io.ds.valid, us1.io.ds.valid, ...)\n * // OR\n * hscmb.usValids(usValidsSeq: _*)\n * }}}\n *\n */\n def usValids(valids: Bool*): Unit = {\n require(valids.length == nUS,\n s\"In StrHsComb.usValids(), length of arg valids and nUS in StrHsComb not match.\")\n cb.io.us_valid :=\n valids.foldLeft(0.U(nUS.W))((acc, v) => {\n (acc << 1) | v\n })\n }\n\n /**\n * Connect ready(s) of up-stream(s)\n * @param readys Ready(s) of up-stream(s)\n * @example {{{\n * hscmb.usReadys(us0.io.ds.ready, us1.io.ds.ready, ...)\n * // OR\n * hscmb.usReadys(usReadysSeq: _*)\n * }}}\n */\n def usReadys(readys: Bool*): Unit = {\n require(readys.length == nUS,\n s\"In StrHsComb.usReadys(), length of arg readys and nUS in StrHsComb not match.\")\n readys.zipWithIndex.foreach{ case(r, i) => {\n r := cb.io.us_ready(nUS - 1 - i)\n }}\n }\n\n /**\n * Connect valid(s) of down-stream(s)\n * @param valids Valid(s) of down-stream(s)\n * @example {{{\n * hscmb.dsValids(ds0.io.us.valid, ds1.io.us.valid, ...)\n * // OR\n * hscmb.dsValids(dsValidsSeq: _*)\n * }}}\n *\n */\n def dsValids(valids: Bool*): Unit = {\n require(valids.length == nDS,\n s\"In StrHsComb.dsValids(), length of arg valids and nDS in StrHsComb not match.\")\n valids.zipWithIndex.foreach { case(v, i) => {\n v := cb.io.ds_valid(nDS - 1 - i)\n }}\n }\n\n /**\n * Connect ready(s) of down-stream(s)\n * @param readys Ready(s) of down-stream(s)\n * @example {{{\n * hscmb.dsReadys(ds0.io.us.ready, ds1.io.us.ready, ...)\n * // OR\n * hscmb.dsReadys(dsReadysSeq: _*)\n * }}}\n */\n def dsReadys(readys: Bool*): Unit = {\n require(readys.length == nDS,\n s\"In StrHsComb.dsReadys(), length of arg readys and nDS in StrHsComb not match.\")\n cb.io.ds_ready :=\n readys.foldLeft(0.U(nDS.W))((acc, r) => {\n (acc << 1 | r)\n })\n }\n\n}\n\nobject StrHsComb {\n /**\n * Create an instance of StrHsComb, in which a StrHsCombModule is\n * instantiated.\n *\n * @param nUS Number of upstream port(s)\n * @param nDS Number of downstream port(s)\n * @note Notes:\n * - The StrHsCombModule is a pure combination logic module.\n * - Deadlock occurs if d.s. ready depends on u.s. valid.\n * - Deadlock occurs if series 2 StrHsCombs.\n * - Follow a str_fifo or a reg-slice (str_firs or str_birs) can break\n * up deadlock.\n */\n def apply(nUS: Int, nDS: Int): StrHsComb = {\n new StrHsComb(nUS, nDS)\n }\n}\n\n/**\n * Represent a hardware module for detecting gapping between packages.\n */\nclass StrPkgGapping extends Module {\n val io = IO(new Bundle {\n val valid = Input(Bool())\n val ready = Input(Bool())\n val last = Input(Bool())\n val gapping = Output(Bool())\n })\n val shake = WireDefault(io.valid && io.ready)\n val gapped = RegEnable(io.last, true.B, shake)\n io.gapping := shake && io.last || gapped && (!shake)\n}\n\nobject StrPkgGapping {\n /**\n * Create an instance of StrPkgGapping, and connect IOs.\n * @param valid valid signal of stream to be detected.\n * @param ready ready signal of stream to be detected.\n * @param last last signal of stream to be detected.\n * @return output gapping signal.\n */\n def apply[T <: IrrevocableIO[StrHasLast]](str: T): Bool = {\n val strPkgGapping = Module(new StrPkgGapping)\n strPkgGapping.io.valid := str.valid\n strPkgGapping.io.ready := str.ready\n strPkgGapping.io.last := str.bits.last\n strPkgGapping.io.gapping\n }\n}\n\n/**\n * Represents a hardware stream pipeline module.\n *\n * Use this for matching path latency with others.\n *\n * @note Notes:\n * 1. If the latencies can not to be or can hardly be predetermined,\n * str_fifo and str_hscomb are recommended for matching latencies.\n * @param nStage Number of pipeline stages\n * @param gen Data type generator for payload\n * @param init Initialization function for reset value of payload\n * @tparam T Data type of payload\n */\nclass StrPipeStages[+T <: Data]\n(nStage: Int = 4, gen: T = Bool(), init: Option[()=>T] = None) extends Module {\n\n requireIsChiselType(gen)\n require(nStage > 0, s\"In ${desiredName}, arg nStage must > 0, got ${nStage}.\")\n\n override def desiredName = s\"${super.desiredName}_${gen.typeName}\"\n\n val io = IO(new Bundle {\n val us = Flipped(Irrevocable(gen))\n val ds = Irrevocable(gen)\n })\n\n val stages = Seq.fill(nStage)(Module(new StrFrs(gen, init)))\n\n stages.zipWithIndex.foreach{ case(stg, i) => {\n if(i == 0) stg.io.us <> io.us\n else stg.io.us <> stages(i-1).io.ds\n if(i == nStage - 1) io.ds <> stg.io.ds\n }}\n}\n\nclass StrSinkToFifoWriter[+T <: Data](gen:T = UInt(8.W)) extends Module {\n requireIsChiselType(gen)\n override def desiredName = s\"${super.desiredName}_${gen.typeName}\"\n\n val io = IO(new Bundle {\n val us = Flipped(Irrevocable(gen))\n val writer = FifoIO.Writer(gen)\n })\n io.us.ready := !io.writer.full\n io.writer.write := io.us.fire\n io.writer.data := io.us.bits\n}\n\nobject StrSinkToFifoWriter {\n def apply[T <: Data](fifoWriter: FifoIO.WriterIO[T]): IrrevocableIO[T] = {\n val sink2writer = Module(new StrSinkToFifoWriter(chiselTypeOf(fifoWriter.data)))\n sink2writer.io.writer <> fifoWriter\n sink2writer.io.us\n }\n}\n\nclass StrSourceFromFifoReader[+T <: Data](gen:T = UInt(8.W)) extends Module {\n requireIsChiselType(gen)\n override def desiredName = s\"${super.desiredName}_${gen.typeName}\"\n\n val io = IO(new Bundle {\n val reader = FifoIO.Reader(gen)\n val ds = Irrevocable(gen)\n })\n io.reader.read := !io.reader.empty && (!io.ds.valid || io.ds.ready)\n io.ds.bits := io.reader.data\n val ds_valid = RegInit(false.B)\n ds_valid := MuxCase(ds_valid, Seq(\n io.reader.read -> true.B,\n io.ds.ready -> false.B\n ))\n io.ds.valid := ds_valid\n}\n\nobject StrSourceFromFifoReader {\n def apply[T <: Data](fifoReader: FifoIO.ReaderIO[T]): IrrevocableIO[T] = {\n val reader2source = Module(new StrSourceFromFifoReader(chiselTypeOf(fifoReader.data)))\n reader2source.io.reader <> fifoReader\n reader2source.io.ds\n }\n}\n\n/**\n * Represents a hardware stream FIFO with configurable depth and data type.\n *\n * This module implements a synchronous stream FIFO using BRAM(s).\n *\n * @note Notes:\n * 1. Using chisel3.util.Queue directly is recommended, since this class\n * is using chisel3.util.Queue internally.\n * 2. nDepth must be a power of 2 for optimal BRAM utilization.\n * @example {{{\n * val fifo = Module(new FIFO(nDepth=16, UInt(8.W)))\n * }}}\n * @tparam T Data type of FIFO elements\n * @param nDepth Number of entries in the FIFO\n * @param gen Data type generator (e.g. `UInt(8.W)`) for elements\n * @param hasFlush Generate io.flush or not\n */\nclass StrFifo[T <: Data]\n(gen:T, nDepth:Int, hasFlush:Boolean = false) extends Module {\n\n requireIsChiselType(gen, s\"In ${desiredName}, gen must be a chisel type.\")\n require(nDepth > 0, s\"In ${desiredName}, arg nDepth must be > 0, got ${nDepth}.\")\n\n override def desiredName = s\"${super.desiredName}_${gen.typeName}\"\n\n val io = IO(new Bundle {\n val us = Flipped(Irrevocable(gen))\n val ds = Irrevocable(gen)\n val flush = if(hasFlush) Some(Input(Bool())) else None\n })\n\n // use chisel3.util.Queue!\n val fifo = Queue.irrevocable(\n enq = io.us\n , entries = nDepth\n , pipe = true\n , flow = false\n , useSyncReadMem = true\n , flush = io.flush\n )\n\n io.ds <> fifo\n}\n\n/**\n * Represent a hardware Dual clock FIFO module with stream interface\n * @param gen Generator of data\n * @param addrWidth Address width of internal RAM, actual FIFO depth = 2^addrWidth-1\n * @param usHasDataCnt True if `dataCnt` of upstream port is needed\n * @param dsHasDataCnt True if `dataCnt` of downstream port is needed\n * @param usHasWrRdCnt True if `writeCnt` and `readCnt` of upstream port are needed\n * @param dsHasWrRdCnt True if `writeCnt` and `readCnt` of downstream port are needed\n * @tparam T Type of data\n */\nclass StrDcFifo[T <: Data](gen: T,\n addrWidth: Int,\n usHasDataCnt: Boolean = false,\n dsHasDataCnt: Boolean = false,\n usHasWrRdCnt: Boolean = false,\n dsHasWrRdCnt: Boolean = false\n ) extends RawModule {\n\n require(addrWidth >= 1 && addrWidth < 64, s\"In ${desiredName}, addrWidth must be in [1, 63]\")\n require(!(!usHasDataCnt && usHasWrRdCnt), s\"In ${desiredName}, when wrHasDataCnt == false, wrHasWrRdCnt is not allowed to be true!\")\n require(!(!dsHasDataCnt && dsHasWrRdCnt), s\"In ${desiredName}, when rdHasDataCnt == false, rdHasWrRdCnt is not allowed to be true!\")\n requireIsChiselType(gen, s\"In ${desiredName}, gen must be a chisel type.\")\n\n override def desiredName = s\"${super.desiredName}_${gen.typeName}\"\n\n val io = IO(new Bundle {\n val usClock = Input(Clock())\n val dsClock = Input(Clock())\n val usReset = Input(Bool())\n val dsReset = Input(Bool())\n val us = Flipped(Irrevocable(gen))\n val ds = Irrevocable(gen)\n val usCnt =\n if(usHasDataCnt)\n Some(FifoIO.CntProvider(addrWidth, usHasWrRdCnt))\n else\n None\n val dsCnt =\n if(dsHasDataCnt)\n Some(FifoIO.CntProvider(addrWidth, dsHasWrRdCnt))\n else\n None\n })\n\n val dcfifo = Module(new DcFifo(gen, addrWidth,\n usHasDataCnt, dsHasDataCnt, usHasWrRdCnt, dsHasWrRdCnt))\n dcfifo.io.wrClock := io.usClock\n dcfifo.io.rdClock := io.dsClock\n dcfifo.io.wrReset := io.usReset\n dcfifo.io.rdReset := io.dsReset\n if(usHasDataCnt)\n dcfifo.io.wcnt.get <> io.usCnt.get\n if(dsHasDataCnt)\n dcfifo.io.rcnt.get <> io.dsCnt.get\n\n withClockAndReset(io.usClock, io.usReset) {\n val us = StrSinkToFifoWriter(dcfifo.io.w)\n io.us <> us\n }\n\n withClockAndReset(io.dsClock, io.dsReset) {\n val ds = StrSourceFromFifoReader(dcfifo.io.r)\n io.ds <> ds\n }\n}\n\n/**\n * Represent a hardware module for converting stream data width\n *\n * @param genUs generator of up-stream bits of IrrevocableIO\n * @param genDs generator of down-stream bits of IrrevocableIO\n * @tparam U type of up-stream bits of IrrevocableIO\n * @tparam D type of down-stream bits of IrrevocableIO\n * @note It's the user's responsibility to make sure that `id` changing,\n * `dest` changing and `last` assert only occurs on boundary of\n * `LCM(us.dataBytes, ds.dataBytes)` bytes, if `userAssociation !=\n * StrUserAssociation.SpreadInBytes`, so as `user`. Otherwise, `id`,\n * `dest` and/or `user` may mess up, `last` may lost.\n */\nclass StrDataWidthConverter[U <: StrHasData, D <: StrHasData](\n genUs: U, genDs: D) extends Module {\n\n requireIsChiselType(genUs)\n requireIsChiselType(genDs)\n\n // ---- check data width ----\n require(genUs.dataWidth % 8 == 0,\n s\"In ${desiredName}, width of io.us.bits.data must be multiple of 8, got ${genUs.dataWidth}\")\n require(genDs.dataWidth % 8 == 0,\n s\"In ${desiredName}, width of io.ds.bits.data must be multiple of 8, got ${genDs.dataWidth}\")\n\n // ---- check strb width ----\n require(!(genUs.hasStrb ^ genDs.hasStrb),\n s\"In ${desiredName}, io.us.bits ${if (genUs.hasStrb) \"HAS\" else \"HAS NO\"} strb signal, but \" +\n s\"io.ds.bits ${if (genDs.hasStrb) \"HAS\" else \"HAS NO\"} strb signal.\")\n require(!genUs.hasStrb || genUs.strbWidth == genUs.dataBytesCeil,\n s\"In ${desiredName}, width of io.us.strb (got ${genUs.strbWidth}) must be 1/8 width of io.us.data (got ${genUs.dataWidth}).\")\n require(!genDs.hasStrb || genDs.strbWidth == genDs.dataBytesCeil,\n s\"In ${desiredName}, width of io.ds.strb (got ${genDs.strbWidth}) must be 1/8 width of io.ds.data (got ${genDs.dataWidth}).\")\n\n // ---- check keep width ----\n require(!(genUs.hasKeep ^ genDs.hasKeep),\n s\"In ${desiredName}, io.us.bits ${if (genUs.hasKeep) \"HAS\" else \"HAS NO\"} keep signal, but \" +\n s\"io.ds.bits ${if (genDs.hasKeep) \"HAS\" else \"HAS NO\"} keep signal.\")\n require(!genUs.hasKeep || genUs.keepWidth == genUs.dataBytesCeil,\n s\"In ${desiredName}, width of io.us.keep (got ${genUs.keepWidth}) must be 1/8 of width of io.us.data (got ${genUs.dataWidth}).\")\n require(!genDs.hasKeep || genDs.keepWidth == genDs.dataBytesCeil,\n s\"In ${desiredName}, width of io.ds.keep (got ${genDs.keepWidth}) must be 1/8 of width of io.ds.data (got ${genDs.dataWidth}).\")\n\n // ---- check last matching ----\n require(!(genUs.hasLast ^ genDs.hasLast),\n s\"In ${desiredName}, io.us.bits ${if (genUs.hasLast) \"HAS\" else \"HAS NO\"} last signal, but \" +\n s\"io.ds.bits ${if (genDs.hasLast) \"HAS\" else \"HAS NO\"} last signal.\")\n\n // ---- check id matching ----\n require(!(genUs.hasId ^ genDs.hasId),\n s\"In ${desiredName}, io.us.bits ${if (genUs.hasId) \"HAS\" else \"HAS NO\"} id signal, but \" +\n s\"io.ds.bits ${if (genDs.hasId) \"HAS\" else \"HAS NO\"} id signal.\")\n require(genUs.idWidth == genDs.idWidth,\n s\"In ${desiredName}, width of io.us.bits.id (got ${genUs.idWidth}) must be equal to io.ds.bits.id (got ${genDs.idWidth}).\")\n\n // ---- check dest matching ----\n require(!(genUs.hasDest ^ genDs.hasDest),\n s\"In ${desiredName}, io.us.bits ${if (genUs.hasDest) \"HAS\" else \"HAS NO\"} id signal, but \" +\n s\"io.ds.bits ${if (genDs.hasDest) \"HAS\" else \"HAS NO\"} id signal.\")\n require(genUs.destWidth == genDs.destWidth,\n s\"In ${desiredName}, width of io.us.bits.id (got ${genUs.destWidth}) must be equal to io.ds.bits.id (got ${genDs.destWidth}).\")\n\n // ---- check user matching ----\n require(!(genUs.hasUser ^ genDs.hasUser),\n s\"In ${desiredName}, io.us.bits ${if (genUs.hasUser) \"HAS\" else \"HAS NO\"} user signal, but \" +\n s\"io.ds.bits ${if (genDs.hasUser) \"HAS\" else \"HAS NO\"} user signal.\")\n \n genDs match {\n case genDs: StrHasUser => {\n if (genDs.userAssociation == StrUserAssociation.SpreadInBytes) {\n require(genUs.userWidth % genUs.dataBytesCeil == 0,\n s\"In ${desiredName}, width of io.us.bits.user in bits must be multiple of width of io.us.bits.data in bytes when userAssociation == StrUserAssociation.SpreadInBytes.\")\n require(genDs.userWidth % genDs.dataBytesCeil == 0,\n s\"In ${desiredName}, width of io.ds.bits.user in bits must be multiple of width of io.ds.bits.data in bytes when userAssociation == StrUserAssociation.SpreadInBytes.\")\n require(genUs.userWidth / genUs.dataBytesCeil == genDs.userWidth / genDs.dataBytesCeil,\n s\"In ${desiredName}, number of user bits associated with each byte of data in io.us.bits and io.ds.bits must be equal\" +\n \" when userAssociation == StrUserAssociation.SpreadInBytes.\")\n }\n else {\n require(genUs.userWidth == genDs.userWidth,\n s\"In ${desiredName}, width of io.us.bits.user (got ${genUs.userWidth}) must be equal to io.ds.bits.user (got ${genDs.userWidth}).\")\n }\n }\n case _ => {}\n }\n\n // ---- io ----\n val io = IO(new Bundle {\n val us = Flipped(Irrevocable(genUs))\n val ds = Irrevocable(genDs)\n })\n\n // ---- parameters ----\n val nUsBytes = io.us.bits.dataWidth / 8\n val nDsBytes = io.ds.bits.dataWidth / 8\n val nBytesLcm = LCM(nUsBytes, nDsBytes)\n val nBytesMax = math.max(nUsBytes, nDsBytes)\n val nBufBytes =\n if (nBytesLcm >= 2 * nBytesMax) nBytesLcm\n else 2 * nBytesLcm\n val nUserUnitBits = io.us.bits.userBitsPerDataByte\n val ptrWidth = log2Up(nBufBytes)\n val cntWidth = log2Up(nBufBytes + 1)\n\n // ---- bufs ----\n val dataBuf = RegInit(VecInit.fill(nBufBytes)(0.U(8.W)))\n val strbBuf =\n if (!genUs.hasStrb) None\n else Some(RegInit(VecInit.fill(nBufBytes)(false.B)))\n val keepBuf =\n if (!genUs.hasKeep) None\n else Some(RegInit(VecInit.fill(nBufBytes)(false.B)))\n val lastBuf =\n if (!genUs.hasLast) None\n else Some(RegInit(VecInit.fill(nBufBytes)(false.B)))\n val idBuf =\n if (!genUs.hasId) None\n else Some(RegInit(VecInit.fill(nBufBytes)(0.U.asTypeOf(genUs.asInstanceOf[StrHasId].id))))\n val destBuf =\n if (!genUs.hasDest) None\n else Some(RegInit(VecInit.fill(nBufBytes)(0.U.asTypeOf(genUs.asInstanceOf[StrHasDest].dest))))\n val userBuf =\n if (!genUs.hasUser) None\n else {\n if (genDs.asInstanceOf[StrHasUser].userAssociation == StrUserAssociation.SpreadInBytes) {\n Some(RegInit(VecInit.fill(nBufBytes)(0.U(nUserUnitBits.W))))\n }\n else {\n Some(RegInit(VecInit.fill(nBufBytes)(0.U.asTypeOf(genUs.asInstanceOf[StrHasUser].user))))\n }\n }\n\n // ---- pointers ----\n val wPtr = RegInit(0.U(ptrWidth.W))\n val rPtr = RegInit(0.U(ptrWidth.W))\n val dCnt = RegInit(0.U(cntWidth.W))\n\n // ---- hand shakes ----\n val cap = WireDefault(nBufBytes.U(cntWidth.W))\n io.us.ready := cap - dCnt >= nUsBytes.U\n io.ds.valid := dCnt >= nDsBytes.U\n\n // ---- dcnt ----\n dCnt := MuxCase(dCnt, Seq(\n (io.us.fire && io.ds.fire) -> (dCnt - nDsBytes.U + nUsBytes.U),\n (io.us.fire ) -> (dCnt + nUsBytes.U),\n (io.ds.fire ) -> (dCnt - nDsBytes.U )\n ))\n\n // ---- write ----\n when(io.us.fire) {\n when(wPtr === cap - nUsBytes.U) {\n wPtr := 0.U(ptrWidth.W)\n }.otherwise {\n wPtr := wPtr + nUsBytes.U\n }\n for (i <- 0 until nUsBytes) {\n dataBuf(wPtr + i.asUInt) := io.us.bits.data(i * 8 + 7, i * 8)\n io.us.bits match {\n case bits: StrHasStrb => strbBuf.get(wPtr + i.asUInt) := bits.strb(i)\n case _ => {}\n }\n io.us.bits match {\n case bits: StrHasKeep => keepBuf.get(wPtr + i.asUInt) := bits.keep(i)\n case _ => {}\n }\n io.us.bits match {\n case bits: StrHasLast => lastBuf.get(wPtr + i.asUInt) := bits.last && i.asUInt === (nUsBytes - 1).asUInt\n case _ => {}\n }\n io.us.bits match {\n case bits: StrHasId => idBuf.get(wPtr + i.asUInt) := bits.id\n case _ => {}\n }\n io.us.bits match {\n case bits: StrHasDest => destBuf.get(wPtr + i.asUInt) := bits.dest\n case _ => {}\n }\n io.us.bits match {\n case bits: StrHasUser => {\n if (genDs.asInstanceOf[StrHasUser].userAssociation == StrUserAssociation.SpreadInBytes) {\n userBuf.get(wPtr + i.asUInt) := bits.user((i + 1) * nUserUnitBits - 1, i * nUserUnitBits)\n }\n else {\n userBuf.get(wPtr + i.asUInt) := bits.user\n }\n }\n case _ => {}\n }\n }\n }\n\n // ---- read ----\n val dsData = WireDefault(VecInit.fill(nDsBytes)(0.U(8.W)))\n val dsStrb =\n if (!genDs.hasStrb) None\n else Some(WireDefault(VecInit.fill(nDsBytes)(false.B)))\n val dsKeep =\n if (!genDs.hasKeep) None\n else Some(WireDefault(VecInit.fill(nDsBytes)(false.B)))\n val dsLast =\n if (!genDs.hasLast) None\n else Some(WireDefault(false.B))\n val dsId =\n if (!genDs.hasId) None\n else Some(WireDefault(0.U.asTypeOf(genDs.asInstanceOf[StrHasId].id)))\n val dsDest =\n if (!genDs.hasDest) None\n else Some(WireDefault(0.U.asTypeOf(genDs.asInstanceOf[StrHasDest].dest)))\n val dsUser =\n if (!genDs.hasUser) None\n else if (genDs.asInstanceOf[StrHasUser].userAssociation == StrUserAssociation.SpreadInBytes)\n Some(WireDefault(VecInit.fill(nDsBytes)(0.U(nUserUnitBits.W))))\n else\n Some(WireDefault(0.U.asTypeOf(genDs.asInstanceOf[StrHasUser].user)))\n when(io.ds.fire) {\n when(rPtr === cap - nDsBytes.U) {\n rPtr := 0.U(ptrWidth.W)\n }.otherwise {\n rPtr := rPtr + nDsBytes.U\n }\n }\n \n dsData.zipWithIndex.foreach {\n case (d, i) => d := dataBuf(rPtr + i.asUInt)\n }\n dsStrb.foreach { strb => strb.zipWithIndex.foreach{\n case (s, i) => s := strbBuf.get(rPtr + i.asUInt)\n }}\n dsKeep.foreach { keep => keep.zipWithIndex.foreach {\n case (k, i) => k := keepBuf.get(rPtr + i.asUInt)\n }}\n dsLast.foreach { last => last := lastBuf.get(rPtr + (nDsBytes - 1).U) }\n dsId.foreach { id => id := {\n if (genDs.asInstanceOf[StrHasId].idAssociation == StrIdAssociation.LowestByte)\n idBuf.get(rPtr)\n else\n idBuf.get(rPtr + (nDsBytes - 1).U)\n }}\n dsDest.foreach { dest => dest := {\n if (genDs.asInstanceOf[StrHasDest].destAssociation == StrDestAssociation.LowestByte)\n destBuf.get(rPtr)\n else\n destBuf.get(rPtr + (nDsBytes - 1).U)\n }}\n dsUser.foreach { user => {\n val userAssociation = genDs.asInstanceOf[StrHasUser].userAssociation\n if (userAssociation == StrUserAssociation.LowestByte) {\n user.asInstanceOf[UInt] := userBuf.get(rPtr)\n }\n else if (userAssociation == StrUserAssociation.HighestByte) {\n user.asInstanceOf[UInt] := userBuf.get(rPtr + (nDsBytes - 1).U)\n }\n else { //if(userAssociation == StrUserAssociation.SpreadInBytes) {\n user.asInstanceOf[Vec[UInt]].zipWithIndex.foreach {\n case (u, i) => u := userBuf.get(rPtr + i.asUInt)\n }\n }\n }}\n \n io.ds.bits.data := dsData.asUInt\n if (genDs.hasStrb) io.ds.bits.asInstanceOf[StrHasStrb].strb := dsStrb.get.asUInt\n if (genDs.hasKeep) io.ds.bits.asInstanceOf[StrHasKeep].keep := dsKeep.get.asUInt\n if (genDs.hasLast) io.ds.bits.asInstanceOf[StrHasLast].last := dsLast.get\n if (genDs.hasId) io.ds.bits.asInstanceOf[StrHasId].id := dsId.get\n if (genDs.hasDest) io.ds.bits.asInstanceOf[StrHasDest].dest := dsDest.get\n if (genDs.hasUser) io.ds.bits.asInstanceOf[StrHasUser].user := dsUser.get.asUInt\n}\n\n/**\n * Represent a hardware keep remover and data width convert module.\n *\n * \"keep remove\" : remove byte(s) with the corresponding keep bit(s) is low.\n *\n * example: {{{\n * clock /^^\\__/^^\\__/^^\\__/^^\\__/^^\\__/^^\\__/^\n * us.bits.data[23:16] X D1 XXXXXXX D2 X D5 X...\n * us.bits.data[15: 8] XXXXXXXXXXXXXXXXXXX D4 X...\n * us.bits.data[ 7: 0] X D0 XXXXXXXXXXXXX D3 X...\n * us.bits.keep[ 2: 0] X 5 X 0 X 4 X 7 X...\n * ds.bits.data[15: 8] XXXXXXX D1 XXXXXXXXXXXXX D3 X D5 X\n * ds.bits.data[ 7: 0] XXXXXXX D0 XXXXXXXXXXXXX D2 X D4 X\n * }}}\n *\n * @param genUs generator of up-stream bits of IrrevocableIO\n * @param genDs generator of down-stream bits of IrrevocableIO\n * @tparam U type of up-stream bits of IrrevocableIO\n * @tparam D type of down-stream bits of IrrevocableIO\n * @note CAUTION:\n * It's the user's responsibility to make sure that `id` changing,\n * `dest` changing and `last` assert only occurs on boundary of\n * `LCM(us.dataBytes, ds.dataBytes)` bytes, if `userAssociation !=\n * StrUserAssociation.SpreadInBytes`, so as `user`. Otherwise, `id`,\n * `dest` and/or `user` may mess up, `last` may lost.\n */\nclass StrKeepRemover[U <: StrHasKeep, D <: StrHasData](\n genUs: U, genDs: D) extends Module {\n\n requireIsChiselType(genUs)\n requireIsChiselType(genDs)\n \n // ---- check data width ----\n require(genDs.dataWidth % 8 == 0,\n s\"In ${desiredName}, width of io.ds.bits.data must be multiple of 8, got ${genDs.dataWidth}\")\n \n // ---- check strb ----\n require(!(genUs.hasStrb ^ genDs.hasStrb),\n s\"In ${desiredName}, io.us.bits ${if (genUs.hasStrb) \"HAS\" else \"HAS NO\"} strb signal, but \" +\n s\"io.ds.bits ${if (genDs.hasStrb) \"HAS\" else \"HAS NO\"} strb signal.\")\n \n // ---- check last ----\n require(!(genUs.hasLast ^ genDs.hasLast),\n s\"In ${desiredName}, io.us.bits ${if (genUs.hasLast) \"HAS\" else \"HAS NO\"} last signal, but \" +\n s\"io.ds.bits ${if (genDs.hasLast) \"HAS\" else \"HAS NO\"} last signal.\")\n \n // ---- check id ----\n require(!(genUs.hasId ^ genDs.hasId),\n s\"In ${desiredName}, io.us.bits ${if (genUs.hasId) \"HAS\" else \"HAS NO\"} id signal, but \" +\n s\"io.ds.bits ${if (genDs.hasId) \"HAS\" else \"HAS NO\"} id signal.\")\n require(genUs.idWidth == genDs.idWidth,\n s\"In ${desiredName}, width of io.us.bits.id (got ${genUs.idWidth}) must be equal to io.ds.bits.id (got ${genDs.idWidth}).\")\n \n // ---- check dest matching ----\n require(!(genUs.hasDest ^ genDs.hasDest),\n s\"In ${desiredName}, io.us.bits ${if (genUs.hasDest) \"HAS\" else \"HAS NO\"} id signal, but \" +\n s\"io.ds.bits ${if (genDs.hasDest) \"HAS\" else \"HAS NO\"} id signal.\")\n require(genUs.destWidth == genDs.destWidth,\n s\"In ${desiredName}, width of io.us.bits.id (got ${genUs.destWidth}) must be equal to io.ds.bits.id (got ${genDs.destWidth}).\")\n \n // ---- check user matching ----\n require(!(genUs.hasUser ^ genDs.hasUser),\n s\"In ${desiredName}, io.us.bits ${if (genUs.hasUser) \"HAS\" else \"HAS NO\"} user signal, but \" +\n s\"io.ds.bits ${if (genDs.hasUser) \"HAS\" else \"HAS NO\"} user signal.\")\n genDs match {\n case genDs: StrHasUser => {\n if (genDs.userAssociation == StrUserAssociation.SpreadInBytes) {\n require(genUs.userWidth % genUs.dataBytesCeil == 0,\n s\"In ${desiredName}, width of io.us.bits.user in bits must be multiple of width of io.us.bits.data in bytes when userAssociation == StrUserAssociation.SpreadInBytes.\")\n require(genDs.userWidth % genDs.dataBytesCeil == 0,\n s\"In ${desiredName}, width of io.ds.bits.user in bits must be multiple of width of io.ds.bits.data in bytes when userAssociation == StrUserAssociation.SpreadInBytes.\")\n require(genUs.userWidth / genUs.dataBytesCeil == genDs.userWidth / genDs.dataBytesCeil,\n s\"In ${desiredName}, number of user bits associated with each byte of data in io.us.bits and io.ds.bits must be equal\" +\n \" when userAssociation == StrUserAssociation.SpreadInBytes.\")\n }\n else {\n require(genUs.userWidth == genDs.userWidth,\n s\"In ${desiredName}, width of io.us.bits.user (got ${genUs.userWidth}) must be equal to io.ds.bits.user (got ${genDs.userWidth}).\")\n }\n }\n case _ => {}\n }\n \n override def desiredName: String = s\"${super.desiredName}_${genUs.typeName}_to_${genDs.typeName}\"\n\n val usBytes = genUs.dataWidth / 8\n val dsBytes = genDs.dataWidth / 8\n\n val bufSize = 2 * math.max(usBytes, dsBytes)\n val nUserUnitBits = genUs.userBitsPerDataByte\n val ptrWidth = log2Up(bufSize)\n val cntWidth = log2Up(bufSize + 1)\n\n val io = IO(new Bundle {\n val us = Flipped(Irrevocable(genUs))\n val ds = Irrevocable(genDs)\n })\n\n // ---- bufs ----\n val dataBuf = RegInit(VecInit(Seq.fill(bufSize)(0.U(8.W))))\n val strbBuf =\n if (!genUs.hasStrb) None\n else Some(RegInit(VecInit.fill(bufSize)(false.B)))\n val lastBuf =\n if (!genUs.hasLast) None\n else Some(RegInit(VecInit.fill(bufSize)(false.B)))\n val idBuf =\n if (!genUs.hasId) None\n else Some(RegInit(VecInit.fill(bufSize)(0.U.asTypeOf(genUs.asInstanceOf[StrHasId].id))))\n val destBuf =\n if (!genUs.hasDest) None\n else Some(RegInit(VecInit.fill(bufSize)(0.U.asTypeOf(genUs.asInstanceOf[StrHasDest].dest))))\n val userBuf =\n if (!genUs.hasUser) None\n else {\n if (genDs.asInstanceOf[StrHasUser].userAssociation == StrUserAssociation.SpreadInBytes) {\n Some(RegInit(VecInit.fill(bufSize)(0.U(nUserUnitBits.W))))\n }\n else {\n Some(RegInit(VecInit.fill(bufSize)(0.U.asTypeOf(genUs.asInstanceOf[StrHasUser].user))))\n }\n }\n \n // ---- pointers ----\n val wPtr = RegInit(0.U(ptrWidth.W))\n val rPtr = RegInit(0.U(ptrWidth.W))\n val dCnt = RegInit(0.U(cntWidth.W))\n \n // ---- hand shakes ----\n val cap = WireDefault(bufSize.U(cntWidth.W))\n io.us.ready := (cap - dCnt) >= usBytes.U\n io.ds.valid := dCnt >= dsBytes.U\n\n // ---- wptr map ----\n // most significant high bit in keep, for mark last when last assert\n val lastOneIdx = usBytes.U - 1.U - PriorityEncoder(io.us.bits.keep.asBools.reverse)\n // shift of wr ptr for each byte in us\n val wPtrShift = Wire(Vec(usBytes + 1, UInt(ptrWidth.W))).suggestName(\"wptr_shifts\")\n // wr_ptr + shifts regardless of wrapping\n val wPtrRaw = Wire(Vec(usBytes + 1, UInt((ptrWidth + 1).W))).suggestName(\"wptr_raw\")\n // wr_ptr + shifts considered wrapping\n val wPtrWrap = Wire(Vec(usBytes + 1, UInt(ptrWidth.W))).suggestName(\"wptr_wrap\")\n // actual wr_ptr for each byte in us\n val wPtrMap = Wire(Vec(usBytes + 1, UInt(ptrWidth.W))).suggestName(\"wptr_map\")\n dontTouch(wPtrShift)\n dontTouch(wPtrMap)\n wPtrShift.zipWithIndex.foreach {\n case (s, i) => /*prefix(s\"loop_$i\")*/ {\n if (i == 0) {\n s := 0.U\n }\n else {\n // s := io.us.bits.keep(i - 1, 0).asBools.map(_.asUInt).reduce(_ +& _)\n s := PopCount(io.us.bits.keep(i - 1, 0))\n }\n }\n }\n wPtrMap.zipWithIndex.foreach {\n case (p, i) => /*prefix(s\"loop_$i\")*/ {\n wPtrRaw(i) := wPtr +& wPtrShift(i)\n wPtrWrap(i) := wPtr +& wPtrShift(i) - bufSize.U\n p := Mux(wPtrRaw(i) >= bufSize.U, wPtrWrap(i), wPtrRaw(i))\n }\n }\n \n // ---- dcnt ----\n dCnt := MuxCase(dCnt, Seq(\n (io.us.fire && io.ds.fire) -> (dCnt - dsBytes.U + wPtrShift(usBytes)),\n (io.us.fire ) -> (dCnt + wPtrShift(usBytes)),\n (io.ds.fire ) -> (dCnt - dsBytes.U )\n ))\n \n // ---- write ----\n when(io.us.fire) {\n wPtr := wPtrMap(usBytes)\n for (i <- 0 until usBytes) {\n when(io.us.bits.keep(i)) {\n dataBuf(wPtrMap(i)) := io.us.bits.data(i * 8 + 7, i * 8)\n io.us.bits match {\n case bits: StrHasStrb => strbBuf.get(wPtrMap(i)) := bits.strb(i)\n\n }\n io.us.bits match {\n case bits: StrHasLast => lastBuf.get(wPtrMap(i)) := bits.last && (i.asUInt === lastOneIdx)\n", "right_context": " }\n io.us.bits match {\n case bits: StrHasId => idBuf.get(wPtrMap(i)) := bits.id\n case _ => {}\n }\n io.us.bits match {\n case bits: StrHasDest => destBuf.get(wPtrMap(i)) := bits.dest\n case _ => {}\n }\n io.us.bits match {\n case bits: StrHasUser => {\n if (genDs.asInstanceOf[StrHasUser].userAssociation == StrUserAssociation.SpreadInBytes) {\n userBuf.get(wPtrMap(i)) := bits.user((i + 1) * nUserUnitBits - 1, i * nUserUnitBits)\n }\n else {\n userBuf.get(wPtrMap(i)) := bits.user\n }\n }\n case _ => {}\n }\n }\n }\n }\n\n // ---- rptr map ----\n val rPtrRaw = Wire(Vec(dsBytes, UInt((ptrWidth + 1).W))).suggestName(\"rptr_raw\")\n val rPtrWrap = Wire(Vec(dsBytes, UInt(ptrWidth.W))).suggestName(\"rptr_wrap\")\n val rPtrMap = Wire(Vec(dsBytes, UInt(ptrWidth.W))).suggestName(\"rptr_map\")\n dontTouch(rPtrMap)\n rPtrMap.zipWithIndex.foreach {\n case (p, i) => /*prefix(s\"loop_$i\")*/ {\n rPtrRaw(i) := rPtr +& i.asUInt\n rPtrWrap(i) := rPtr +& i.asUInt - bufSize.U\n p := Mux(rPtrRaw(i) >= bufSize.U,\n rPtrWrap(i),\n rPtrRaw(i)\n )\n }\n }\n \n // ---- read ----\n val rWrap = WireInit(rPtr +& dsBytes.U >= bufSize.U)\n when(io.ds.fire) {\n rPtr := Mux(rWrap,\n rPtr +& dsBytes.U - bufSize.U,\n rPtr +& dsBytes.U\n )\n }\n\n val dsData = Wire(Vec(dsBytes, UInt(8.W)))\n val dsStrb =\n if (!genDs.hasStrb) None\n else Some(Wire(Vec(dsBytes, Bool())))\n val dsLast =\n if (!genDs.hasLast) None\n else Some(Wire(Bool()))\n val dsId =\n if (!genDs.hasId) None\n else Some(Wire(genDs.asInstanceOf[StrHasId].id.cloneType))\n val dsDest =\n if (!genDs.hasDest) None\n else Some(Wire(genDs.asInstanceOf[StrHasDest].dest.cloneType))\n val dsUser =\n if (!genDs.hasUser) None\n else if (genDs.asInstanceOf[StrHasUser].userAssociation == StrUserAssociation.SpreadInBytes)\n Some(Wire(Vec(dsBytes, UInt(nUserUnitBits.W))))\n else\n Some(Wire(genDs.asInstanceOf[StrHasUser].user.cloneType))\n \n dsData.zipWithIndex.foreach {\n case (d, i) => d := dataBuf(rPtrMap(i))\n }\n dsStrb.foreach{ strb => strb.zipWithIndex.foreach {\n case (s, i) => s := strbBuf.get(rPtrMap(i))\n }}\n dsLast.foreach { last => last := lastBuf.get(rPtrMap(dsBytes - 1))}\n dsId.foreach { id => id := {\n if (genDs.asInstanceOf[StrHasId].idAssociation == StrIdAssociation.LowestByte)\n idBuf.get(rPtrMap(0))\n else\n idBuf.get(rPtrMap(dsBytes - 1))\n }}\n dsDest.foreach { dest => dest := {\n if (genDs.asInstanceOf[StrHasDest].destAssociation == StrDestAssociation.LowestByte)\n destBuf.get(rPtrMap(0))\n else\n destBuf.get(rPtrMap(dsBytes - 1))\n }}\n dsUser.foreach { user => {\n val userAssociation = genDs.asInstanceOf[StrHasUser].userAssociation\n if (userAssociation == StrUserAssociation.LowestByte) {\n user.asInstanceOf[UInt] := userBuf.get(rPtrMap(0))\n }\n else if (userAssociation == StrUserAssociation.HighestByte) {\n user.asInstanceOf[UInt] := userBuf.get(rPtrMap(dsBytes - 1))\n }\n else { //if(userAssociation == StrUserAssociation.SpreadInBytes) {\n user.asInstanceOf[Vec[UInt]].zipWithIndex.foreach {\n case (u, i) => u := userBuf.get(rPtrMap(i))\n }\n }\n }}\n \n io.ds.bits.data := dsData.asUInt\n if (genDs.hasStrb) io.ds.bits.asInstanceOf[StrHasStrb].strb := dsStrb.get.asUInt\n if (genDs.hasKeep) io.ds.bits.asInstanceOf[StrHasKeep].keep := ~0.U(genDs.keepWidth.W)\n if (genDs.hasLast) io.ds.bits.asInstanceOf[StrHasLast].last := dsLast.get\n if (genDs.hasId) io.ds.bits.asInstanceOf[StrHasId].id := dsId.get\n if (genDs.hasDest) io.ds.bits.asInstanceOf[StrHasDest].dest := dsDest.get\n if (genDs.hasUser) io.ds.bits.asInstanceOf[StrHasUser].user := dsUser.get.asUInt\n}\n\n\npackage examples {\n class str_frs_example extends Module {\n class bits extends StrHasData with StrHasLast {\n val last = Bool()\n lazy val data = SInt(8.W)\n }\n\n val us = IO(Flipped(Irrevocable(new bits))).suggestName(\"s0a_abc_axis1b_def\")\n val ds = IO(Irrevocable(new bits)).suggestName(\"m0a_abc_axis1b_def\")\n\n val frs = Module(new StrFrs(new bits))\n us <> frs.io.us\n frs.io.ds <> ds\n }\n\n class str_birs_example extends RawModule {\n class bits extends StrHasData with StrHasLast {\n val last = Bool()\n lazy val data = SInt(8.W)\n }\n\n val io = FlatIO(new Bundle {\n val aclk = Input(Clock())\n val areset_n = Input(Bool())\n val us = Flipped(Irrevocable(new bits))\n val ds = Irrevocable(new bits)\n })\n\n withClockAndReset(io.aclk, !io.areset_n) {\n val firs = Module(new StrBirs(new bits, Some(() => {\n val b = Wire(new bits)\n b.last := false.B\n b.data := \"h15\".U(8.W).asSInt\n b\n })))\n io.us <> firs.io.us\n firs.io.ds <> io.ds\n }\n }\n\n class hscomb1_example extends Module {\n class usbits extends StrHasData with StrHasLast {\n val last = Bool()\n lazy val data = SInt(8.W)\n }\n\n class dsbits extends StrHasData with StrHasLast {\n val last = Bool()\n lazy val data = SInt(8.W)\n }\n\n val io = FlatIO(new Bundle {\n val us0 = Flipped(Irrevocable(new usbits))\n val us1 = Flipped(Irrevocable(new usbits))\n val ds0 = Irrevocable(new dsbits)\n val ds1 = Irrevocable(new dsbits)\n })\n\n io.us0 <> io.ds0\n io.us1 <> io.ds1\n\n val cb = Module(new StrHsCombModule(2, 2))\n cb.io.us_valid := io.us1.valid ## io.us0.valid\n io.us0.ready := cb.io.us_ready(0)\n io.us1.ready := cb.io.us_ready(1)\n io.ds0.valid := cb.io.ds_valid(0)\n io.ds1.valid := cb.io.ds_valid(1)\n cb.io.ds_ready := io.ds1.ready ## io.ds0.ready\n\n io.ds0.bits.data <> -io.us0.bits.data\n io.ds1.bits.data <> -io.us1.bits.data\n }\n\n class hscomb2_example extends Module {\n class usbits extends StrHasData with StrHasLast {\n val last = Bool()\n lazy val data = SInt(8.W)\n }\n\n class dsbits extends StrHasData with StrHasLast {\n val last = Bool()\n lazy val data = SInt(8.W)\n }\n\n val io = FlatIO(new Bundle {\n val us0 = Flipped(Irrevocable(new usbits))\n val us1 = Flipped(Irrevocable(new usbits))\n val ds0 = Irrevocable(new dsbits)\n val ds1 = Irrevocable(new dsbits)\n })\n\n io.us0 <> io.ds0\n io.us1 <> io.ds1\n\n val cb = StrHsComb(2, 2)\n cb.usValids(io.us1.valid, io.us0.valid)\n cb.usReadys(io.us1.ready, io.us0.ready)\n cb.dsValids(io.ds1.valid, io.ds0.valid)\n cb.dsReadys(io.ds1.ready, io.ds0.ready)\n\n io.ds0.bits.data <> -io.us0.bits.data\n io.ds1.bits.data <> -io.us1.bits.data\n }\n\n class str_dcfifo_example extends RawModule {\n class pl extends StrHasData with StrHasLast {\n val last = Bool()\n lazy val data = UInt(8.W)\n }\n val aw = 4\n val wr_has_dcnt = true\n val rd_has_dcnt = true\n val wr_has_rwcnt = false\n val rd_has_rwcnt = false\n val io = FlatIO(new Bundle {\n val clk_us = Input(Clock())\n val clk_ds = Input(Clock())\n val rst_us = Input(Bool())\n val rst_ds = Input(Bool())\n val us = Flipped(Irrevocable(new pl))\n val ds = Irrevocable(new pl)\n val cnt_us = if(wr_has_dcnt) Some(FifoIO.CntProvider(aw, wr_has_rwcnt)) else None\n val cnt_ds = if(rd_has_dcnt) Some(FifoIO.CntProvider(aw, rd_has_rwcnt)) else None\n })\n\n val str_dcfifo = Module(new StrDcFifo(new pl, aw, wr_has_dcnt, rd_has_dcnt, wr_has_rwcnt, rd_has_rwcnt))\n\n str_dcfifo.io.usClock := io.clk_us\n str_dcfifo.io.dsClock := io.clk_ds\n str_dcfifo.io.usReset := io.rst_us\n str_dcfifo.io.dsReset := io.rst_ds\n\n str_dcfifo.io.us <> io.us\n str_dcfifo.io.ds <> io.ds\n\n if(wr_has_dcnt)\n str_dcfifo.io.usCnt.get <> io.cnt_us.get\n if(rd_has_dcnt)\n str_dcfifo.io.dsCnt.get <> io.cnt_ds.get\n }\n\n class str_dwc_example extends Module {\n val usBytes = 6\n val dsBytes = 4\n val idWidth = 4\n val destWidth = 6\n val userUnitWidth = 2\n val idAsso = StrIdAssociation.LowestByte\n val destAsso = StrDestAssociation.LowestByte\n val userAsso = StrUserAssociation.SpreadInBytes\n class UsBits extends StrHasStrb with StrHasKeep with StrHasLast with StrHasId with StrHasDest with StrHasUser {\n lazy val data: UInt = UInt((usBytes * 8).W)\n lazy val strb: UInt = UInt(usBytes.W)\n lazy val keep: UInt = UInt(usBytes.W)\n val last: Bool = Bool()\n val id: UInt = UInt(idWidth.W)\n val dest: UInt = UInt(destWidth.W)\n val user: UInt = UInt((userUnitWidth * usBytes).W)\n }\n class DsBits extends StrHasStrb with StrHasKeep with StrHasLast with StrHasId with StrHasDest with StrHasUser {\n lazy val data: UInt = UInt((dsBytes * 8).W)\n lazy val strb: UInt = UInt(dsBytes.W)\n lazy val keep: UInt = UInt(dsBytes.W)\n val last: Bool = Bool()\n val id: UInt = UInt(idWidth.W)\n val dest: UInt = UInt(destWidth.W)\n val user: UInt = UInt((userUnitWidth * dsBytes).W)\n override val idAssociation = idAsso\n override val destAssociation = destAsso\n override val userAssociation = userAsso\n }\n val io = IO(new Bundle {\n val us = Flipped(Irrevocable(new UsBits))\n val ds = Irrevocable(new DsBits)\n })\n val dwc = Module(new StrDataWidthConverter(new UsBits, new DsBits/*, idAsso, destAsso, userAsso*/))\n io.us <> dwc.io.us\n dwc.io.ds <> io.ds\n }\n\n class str_keep_remover_example extends Module {\n val usBytes = 8\n val dsBytes = 8\n class usBits extends StrHasKeep with StrHasLast {\n lazy val data: UInt = UInt((usBytes * 8).W)\n lazy val keep: UInt = UInt(usBytes.W)\n val last: Bool = Bool()\n }\n class dsBits extends StrHasKeep with StrHasLast {\n lazy val data: UInt = UInt((dsBytes * 8).W)\n lazy val keep: UInt = UInt(dsBytes.W)\n val last: Bool = Bool()\n }\n val io = IO(new Bundle {\n val us = Flipped(Irrevocable(new usBits))\n val ds = Irrevocable(new dsBits)\n })\n\n val theKeepRemover = Module(new StrKeepRemover(new usBits, new dsBits))\n\n theKeepRemover.io.us <> io.us\n theKeepRemover.io.ds <> io.ds\n }\n}", "groundtruth": " case _ => {}\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.7, "category_reason": "Scala case/match expression"} {"task_id": "FPGA-Application-Development-and-Simulation", "path": "FPGA-Application-Development-and-Simulation/chisel/src/main/scala/loywong/str_pipe_control.scala", "left_context": "/*\n * MIT License\n *\n * Copyright (c) 2025 loykylewong (loywong@gmail.com)\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n */\n\npackage loywong\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.requireIsChiselType\n\n/**\n * Represents a hardware active pipeline stage.\n *\n * An \"active\" pipeline stage handles handshaking in each stage, and generate\n * `en` signal for controlling data flow, which can be used for\n * `str_passive_stage` or user defined logic.\n *\n * @param genUS Data type generator for upstream payload\n * @param genDS Data type generator for downstream payload\n * @param initDS Initialization function for reset value of downstream\n * payload, default `None` makes init value all zero\n * @param worker Function for processing upstream payload into downstream\n * payload\n * @tparam U Data type of upstream payload\n * @tparam D Data type of downstream payload\n * @note Recommended usage:\n * 1. Instantiate with arg `worker` represent operations needed.\n * 1. Extends and override `ds_bits_next := ...` or `ds_bits_next.xxx := ...`\n */\nclass StrActiveStage[+U <: Data, +D <: Data]\n(genUS: U = Bool(), genDS: D = Bool(), initDS: Option[()=>D] = None)\n(worker: U => D = (x: U) => x.asTypeOf(genDS)) extends Module {\n requireIsChiselType(genUS)\n requireIsChiselType(genDS)\n\n override def desiredName = s\"${super.desiredName}_${genUS.typeName}_to_${genDS.typeName}\"\n\n val io = FlatIO(new Bundle {\n val us = Flipped(Irrevocable(genUS))\n val ds = Irrevocable(genDS)\n val en = Output(Bool())\n })\n\n io.en := io.us.fire\n io.us.ready := io.ds.ready || !io.ds.valid\n\n val ds_valid = RegInit(false.B)\n // ds_valid := Mux(io.en, true.B, Mux(io.ds.ready, false.B, ds_valid))\n ds_valid := MuxCase(ds_valid, Seq(\n io.us.fire -> true.B,\n io.ds.ready -> false.B\n ))\n io.ds.valid := ds_valid\n\n val ds_bits_next: D = WireDefault(0.U.asTypeOf(genDS))\n ds_bits_next := worker(io.us.bits)\n\n val ds_bits = initDS match {\n case Some(f) => RegInit(f())\n case None => RegInit(0.U.asTypeOf(genDS))\n }\n ds_bits := Mux(io.en, ds_bits_next, ds_bits)\n io.ds.bits := ds_bits\n}\n\n/**\n * Represents a hardware passive pipeline stage.\n *\n * A \"passive\" pipeline stage passively control data flow by using `en` signal\n * which can be provided by `str_active_stage` or user logic.\n *\n * @param genUS Data type generator for upstream payload\n * @param genDS Data type generator for downstream payload\n * @param initDS Initialization function for reset value of downstream\n * payload\n * @param worker Function for processing upstream payload into downstream\n * payload\n * @tparam U Data type of upstream payload\n * @tparam D Data type of downstream payload\n * @note Recommended usage:\n * 1. Instantiate with arg `worker` represent operations needed.\n * 1. Extends and override `ds_bits_next := ...` or `ds_bits_next.xxx := ...`\n */\nclass StrPassiveStage[+U <: Data, +D <: Data]\n(genUS: U = Bool(), genDS: D = Bool(), initDS: Option[()=>D] = None)\n(worker: U => D = (x: U) => x.asTypeOf(genDS)) extends Module {\n requireIsChiselType(genUS)\n requireIsChiselType(genDS)\n\n", "right_context": "\n val io = FlatIO(new Bundle {\n val en = Input(Bool())\n val us_bits = Input(genUS)\n val ds_bits = Output(genDS)\n })\n\n val ds_bits_next = WireDefault(0.U.asTypeOf(genDS))\n ds_bits_next := worker(io.us_bits)\n\n val ds_bits = initDS match {\n case Some(f) => RegInit(f())\n case None => RegInit(0.U.asTypeOf(genDS))\n }\n ds_bits := Mux(io.en, ds_bits_next, ds_bits)\n io.ds_bits := ds_bits\n}\n\npackage examples {\n class str_stage_example_0(dw: Int = 8) extends Module {\n class us_bits extends Bundle {\n val real = SInt(dw.W)\n val imag = SInt(dw.W)\n }\n\n class ds_bits extends Bundle {\n val power = SInt((dw * 2).W)\n }\n\n val io = FlatIO(new Bundle {\n val us = Flipped(Irrevocable(new us_bits))\n val ds = Irrevocable(new ds_bits)\n })\n\n class sq_bits extends Bundle {\n val r_sq = SInt((dw * 2).W)\n val i_sq = SInt((dw * 2).W)\n }\n\n val stg_sq = Module(new StrActiveStage(\n new us_bits,\n new sq_bits,\n )(\n (x: us_bits) => {\n val y = Wire(new sq_bits)\n y.r_sq := x.real * x.real\n y.i_sq := x.imag * x.imag\n y\n }\n ))\n val stg_add = Module(new StrActiveStage(\n new sq_bits,\n new ds_bits,\n )(\n (x: sq_bits) => {\n val y = Wire(new ds_bits)\n y.power := x.r_sq + x.i_sq\n y\n }\n ))\n\n io.us <> stg_sq.io.us\n stg_sq.io.ds <> stg_add.io.us\n stg_add.io.ds <> io.ds\n }\n\n class str_stage_example_1(dw: Int = 8, sbw: Int = 8) extends Module {\n class us_bits extends Bundle {\n val real = SInt(dw.W)\n val imag = SInt(dw.W)\n val sideband = UInt(sbw.W)\n }\n\n class ds_bits extends Bundle {\n val power = SInt((dw * 2).W)\n val sideband = UInt(sbw.W)\n }\n\n val io = FlatIO(new Bundle {\n val us = Flipped(Irrevocable(new us_bits))\n val ds = Irrevocable(new ds_bits)\n })\n\n class sq_bits extends Bundle {\n val r_sq = SInt((dw * 2).W)\n val i_sq = SInt((dw * 2).W)\n val sideband = UInt(sbw.W)\n }\n\n val stg_sq = Module(new StrActiveStage(\n new us_bits,\n new sq_bits,\n )(\n (x: us_bits) => {\n val y = Wire(new sq_bits)\n y.sideband := x.sideband\n y.r_sq := x.real * x.real\n y.i_sq := x.imag * x.imag\n y\n }\n ))\n val stg_add = Module(new StrActiveStage(\n new sq_bits,\n new ds_bits,\n )(\n (x: sq_bits) => {\n val y = Wire(new ds_bits)\n y.sideband := x.sideband\n y.power := x.r_sq + x.i_sq\n y\n }\n ))\n\n io.us <> stg_sq.io.us\n stg_sq.io.ds <> stg_add.io.us\n stg_add.io.ds <> io.ds\n }\n\n class str_stage_example_2(dw: Int = 8, sbw: Int = 8) extends Module {\n class us_bits extends StrHasLast {\n override val last = Bool()\n val real = SInt(dw.W)\n val imag = SInt(dw.W)\n val sideband = UInt(sbw.W)\n }\n\n class ds_bits extends StrHasLast {\n override val last = Bool()\n val power = SInt((dw * 2).W)\n val sideband = UInt(sbw.W)\n }\n\n val io = FlatIO(new Bundle {\n val us = Flipped(Irrevocable(new us_bits))\n val ds = Irrevocable(new ds_bits)\n })\n\n class sq_bits extends Bundle {\n val r_sq = SInt((dw * 2).W)\n val i_sq = SInt((dw * 2).W)\n }\n\n val stg_sq = Module(new StrActiveStage()())\n val stg_add = Module(new StrActiveStage()())\n\n io.us.valid <> stg_sq.io.us.valid\n io.us.ready <> stg_sq.io.us.ready\n io.us.bits.last <> stg_sq.io.us.bits\n\n stg_sq.io.ds <> stg_add.io.us\n\n stg_add.io.ds.valid <> io.ds.valid\n stg_add.io.ds.ready <> io.ds.ready\n stg_add.io.ds.bits <> io.ds.bits.last\n\n val sq_regs = Reg(new sq_bits)\n when(stg_sq.io.en) {\n sq_regs.r_sq := io.us.bits.real * io.us.bits.real\n sq_regs.i_sq := io.us.bits.imag * io.us.bits.imag\n }\n\n val pw_regs = Reg(SInt((dw * 2).W))\n when(stg_add.io.en) {\n pw_regs := sq_regs.r_sq + sq_regs.i_sq\n }\n\n io.ds.bits.power := pw_regs\n\n val stg_sideband = Array.fill(2) {\n Module(new StrPassiveStage(UInt(sbw.W), UInt(sbw.W))())\n }\n stg_sideband(0).io.us_bits <> io.us.bits.sideband\n stg_sideband(0).io.en <> stg_sq.io.en\n stg_sideband(1).io.en <> stg_add.io.en\n for (i <- 1 until 2) {\n stg_sideband(i).io.us_bits := stg_sideband(i - 1).io.ds_bits\n }\n io.ds.bits.sideband <> stg_sideband(1).io.ds_bits\n }\n}\n", "groundtruth": " override def desiredName = s\"${super.desiredName}_${genUS.typeName}_to_${genDS.typeName}\"\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "FPGA-Application-Development-and-Simulation", "path": "FPGA-Application-Development-and-Simulation/chisel/src/main/scala/loywong/util.scala", "left_context": "package loywong\n\nimport scala.math._\nimport chisel3._\nimport chisel3.util._\nimport chiseltest._\n\nobject util {\n implicit class BitsUtil(private val x: Bits) extends AnyVal {\n /**\n * Get the minimum width divisible by 8 and no less than the data width\n *\n * @return The minimum width divisible by 8\n */\n def getWidthUp8: Int = ((x.getWidth - 1) / 8 + 1) * 8\n\n /**\n * Get the minimum number of bytes that can hold data\n *\n * @return The minimum number of bytes\n */\n def getBytesCeil: Int = (x.getWidth - 1) / 8 + 1\n\n /**\n * Extend width by padding 0 to MSB side\n *\n * @param toBits Desired width of return data\n * @return Extended data\n */\n def extend(toBits: Int): Bits = {\n require(toBits >= x.getWidth)\n if (toBits > x.getWidth) {\n 0.U((toBits - x.getWidth).W) ## x\n }\n else {\n x\n }\n }\n\n /**\n * Extend width to integer number of bytes\n *\n * @return Extended data\n */\n def extendToBytes: Bits = {\n x match {\n case u: UInt => u.extendToBytes\n case s: SInt => s.extendToBytes\n case _ => x.extendToBytes\n }\n }\n\n /**\n * Slice Bits into slices according to width of sinks and connect them\n * to sinks\n *\n * @param sinks Sinks to be connected\n * @example {{{\n * val x = Wire(UInt(12.W))\n * val a = Wire(UInt(4.W))\n * val b = Wire(SInt(8.W))\n * x.sliceTo(a, b)\n * }}}\n */\n def sliceTo(sinks: Bits*): Unit = {\n var lsb = 0\n sinks.reverse.foreach(y => {\n y match {\n case s: SInt => s := x(lsb + s.getWidth - 1, lsb).asSInt\n case u: UInt => u := x(lsb + u.getWidth - 1, lsb)\n case _ => y := x(lsb + y.getWidth - 1, lsb)\n }\n lsb += y.getWidth\n })\n }\n\n /**\n * Slice Bits into slices according to widths\n *\n * @param widths Widths of each slices\n * @return Seq of slices\n */\n def slices(widths: Int*): Seq[UInt] = {\n val res = widths.map(w => Wire(UInt(w.W)))\n sliceTo(res: _*)\n res\n }\n\n /**\n * Concat multiple Bits and connect them to this Bits\n *\n * @param sources The multiple bits to be concatenated\n */\n def catFrom(sources: Bits*): Unit = {\n x := Cat(sources)\n }\n\n /**\n * Slice Bits into slices according to `widthUp8` of sinks and connect\n * them to sinks\n *\n * @param sinks Sinks to be connected\n * @example {{{\n * val x = Wire(UInt(24W))\n * val a = Wire(UInt(6.W))\n * val b = Wire(UInt(12.W))\n * // a := x(21, 16)\n * // b := x(11, 0)\n * x.sliceTo(a, b)\n * }}}\n */\n def sliceByteWiseTo(sinks: Bits*): Unit = {\n var lsb = 0\n sinks.reverse.foreach(y => {\n y match {\n case s: SInt => s := x(lsb + s.getWidth - 1, lsb).asSInt\n case u: UInt => u := x(lsb + u.getWidth - 1, lsb)\n case _ => y := x(lsb + y.getWidth - 1, lsb)\n }\n lsb += y.getWidthUp8\n })\n }\n\n /**\n * Slice Bits into slices according to \"up8\" of specified widths\n *\n * @param widths Widths of each slices\n * @return Seq of slices\n */\n def slicesByteWise(widths: Int*): Seq[UInt] = {\n val res = widths.map(w => Wire(UInt(w.W)))\n sliceByteWiseTo(res: _*)\n res\n }\n\n /**\n * Extend multiple Bits to \"up8\" widths, concat, and connect them to this Bits\n *\n * @param sources The multiple bits to be concatenated\n */\n def catByteWiseFrom(sources: Bits*): Unit = {\n if (sources.isEmpty)\n x := 0.U\n else\n x := Cat(sources.map(s => s.extendToBytes))\n }\n\n /**\n * Reinterpret this Bits as a Fixed-Point with specified frac width\n * @param fw Width of fractional part\n * @return Fixed-Point Wire\n */\n def asFixPoint(fw: Int): FixPoint = {\n val res = Wire(FixPoint(x.getWidth.W, fw))\n res.bits := x.asSInt\n res\n }\n }\n\n implicit class UIntUtil(private val x: UInt) extends AnyVal {\n /**\n * Extend width by padding 0 to MSB side\n *\n * @param toBits Desired width of return data\n * @return Extended data\n */\n def extend(toBits: Int): UInt = {\n require(toBits >= x.getWidth)\n if (toBits > x.getWidth) {\n 0.U((toBits - x.getWidth).W) ## x\n }\n else {\n x\n }\n }\n\n /**\n * Extend width to integer number of bytes\n *\n * @return Extended data\n */\n def extendToBytes: UInt = {\n x.extend(x.getWidthUp8)\n }\n\n /**\n * Repeat data bits, same as `Fill(n, data)` or `{n{data}}` in verilog\n *\n * @param n Times to repeat\n * @return Data with original data bits repeat n times in it.\n */\n def repeat(n: Int): UInt = {\n require(n >= 0)\n Fill(n, x)\n }\n\n def isPositive: Bool = {\n x =/= 0.U\n }\n\n def isNegative: Bool = false.B\n\n /**\n * @return maximum value this UInt can represents\n */\n def highestInBigInt: BigInt = {\n val w = x.getWidth\n val m = BigInt(1) << w\n m - 1\n }\n\n /**\n * @return minimum value this UInt can represents\n */\n def lowestInBigInt: BigInt = {\n BigInt(0)\n }\n\n /**\n * @return maximum value this UInt can present\n */\n def highest: UInt = {\n this.highestInBigInt.U(x.getWidth.W)\n }\n\n /**\n * @return minimum value this UInt can represents\n */\n def lowest: UInt = {\n this.lowestInBigInt.U(x.getWidth.W)\n }\n }\n\n implicit class SIntUtil(private val x: SInt) extends AnyVal {\n /**\n * Extend width by padding sign bit to MSB side\n *\n * @param toBits Desired width of return data\n * @return Extended data\n */\n def extend(toBits: Int): SInt = {\n require(toBits >= x.getWidth)\n if (toBits > x.getWidth)\n (Fill(toBits - x.getWidth, x.asUInt(x.getWidth - 1)) ## x.asUInt).asSInt\n else\n x\n }\n\n /**\n * Extend width to integer number of bytes\n *\n * @return Extended data\n */\n def extendToBytes: SInt = {\n x.extend(x.getWidthUp8)\n }\n\n def isPositive: Bool = {\n x > 0.S\n }\n\n def isNegative: Bool = {\n x(x.getWidth - 1) === 1.U\n }\n\n /**\n * @return Sign bit of this SInt\n */\n def signBit: Bool = x(x.getWidth - 1).asBool\n\n /**\n * @return maximum value this SInt can represents\n */\n def highestInBigInt: BigInt = {\n val w = x.getWidth\n val m = BigInt(1) << (w - 1)\n m - 1\n }\n\n /**\n * @return minimum value this SInt can represents\n */\n def lowestInBigInt: BigInt = {\n val w = x.getWidth\n val m = BigInt(1) << (w - 1)\n -m\n }\n\n /**\n * @return maximum value this SInt can present\n */\n def highest: SInt = {\n this.highestInBigInt.S(x.getWidth.W)\n }\n\n /**\n * @return minimum value this SInt can represents\n */\n def lowest: SInt = {\n this.lowestInBigInt.S(x.getWidth.W)\n }\n\n private def shiftLeft(n: Int): SInt = {\n val w: Int = x.getWidth\n (x(w - 1) ## (x(w - 2, 0) << n).take(w - 1)).asSInt\n }\n\n private def shiftRight(n: Int): SInt = {\n val w: Int = x.getWidth\n (x >> n).asSInt.extend(w)\n }\n\n private def shiftLeft(n: UInt): SInt = {\n val w: Int = x.getWidth\n (x(w - 1) ## (x(w - 2, 0) << n).take(w - 1)).asSInt\n }\n\n private def shiftRight(n: UInt): SInt = {\n val w: Int = x.getWidth\n (x >> n).asSInt.extend(w)\n }\n\n /**\n * Same behavior as it in Verilog/SystemVerilog when `n >= 0`,\n * and extends function when `n < 0` (eqv.: x >>> (-n) ).\n * @param n bits to be shifted.\n * @return shift result.\n * @note CAUTION: may cause value overflow.\n */\n final def <<<(n: Int): SInt = {\n if(n > 0) shiftLeft(n)\n else if(n < 0) shiftRight(-n)\n else x\n }\n\n /**\n * Same behavior as it in Verilog/SystemVerilog when `n >= 0`,\n * and extends function when `n < 0` (eqv.: x <<< (-n) ).\n * @param n bits to be shifted.\n * @return shift result.\n * @note CAUTION: may cause value overflow when `n < 0`.\n */\n final def >>>(n: Int): SInt = {\n if(n > 0) shiftRight(n)\n else if(n < 0) shiftLeft(-n)\n else x\n }\n\n /**\n * Same behavior as it in Verilog/SystemVerilog when `n >= 0`,\n * and extends function when `n < 0` (eqv.: x >>> (-n) ).\n * @param n bits to be shifted.\n * @return shift result.\n * @note CAUTION: may cause value overflow.\n */\n final def <<<(n: SInt): SInt = {\n MuxCase(x, Seq(\n (n > 0.S) -> shiftLeft(n.asUInt),\n (n < 0.S) -> shiftRight((-n).asUInt)\n ))\n }\n\n /**\n * Same behavior as it in Verilog/SystemVerilog when `n >= 0`,\n * and extends function when `n < 0` (eqv.: x >>> (-n) ).\n * @param n bits to be shifted.\n * @return shift result.\n * @note CAUTION: may cause value overflow when `n < 0`.\n */\n final def >>>(n: SInt): SInt = {\n MuxCase(x, Seq(\n (n > 0.S) -> shiftRight(n.asUInt),\n (n < 0.S) -> shiftLeft((-n).asUInt)\n ))\n }\n\n /**\n * Same behavior as it in Verilog/SystemVerilog.\n * @param n bits to be shifted.\n * @return shift result.\n * @note CAUTION: may cause value overflow.\n */\n final def <<<(n: UInt): SInt = shiftLeft(n)\n\n /**\n * Same behavior as it in Verilog/SystemVerilog.\n * @param n bits to be shifted.\n * @return shift result.\n */\n final def >>>(n: UInt): SInt = shiftRight(n)\n }\n\n /**\n * Extend each data to integer number of bytes, and then concat.\n *\n * @param x Seq of data\n * @return Concat result in UInt\n */\n def CatByteWise(x: Bits*): UInt = {\n if (x.isEmpty)\n 0.U\n else\n Cat(x.map(u => u.extendToBytes))\n }\n\n /**\n * Extend each BigInt to integer number of bytes, and then concat.\n *\n * @param isSigned Seq of signedness of each data\n * @param w Seq of width of each data\n * @param x Seq of BigInts, lower w(i) bits of each is the actual data to\n * be concat\n * @return Concat result in BigInt\n */\n def CatByteWise(isSigned: Seq[Boolean], w: Seq[Int], x: BigInt*): BigInt = {\n require(x.length == w.length)\n if (x.isEmpty)\n BigInt(0)\n else {\n var lsb = 0\n var res = BigInt(0)\n for (i <- x.length - 1 to 0 by -1) {\n val data = x(i)\n val width = w(i)\n if (isSigned(i))\n res |= data.asSigned(width).asUnsigned(width.up8) << lsb\n else\n res |= data.asUnsigned(width) << lsb\n lsb += width.up8\n }\n res.asUnsigned(lsb)\n }\n }\n\n implicit class BigIntUtils(private val x: BigInt) extends AnyVal {\n /**\n * @return The minimum number divisible by 8 and no less than this\n * BigInt\n */\n def up8: BigInt = if (x < 0) 0 else ((x - 1) / 8 + 1) * 8\n\n /**\n * @return The number of high bit in this BigInt\n */\n def popCount: Int = {\n var n = 0\n for (i <- 0 until x.bitLength) {\n if (x.testBit(i))\n n = n + 1\n }\n n\n }\n\n /**\n * @param mask Bits to be tested\n * @return True if `(x & mask) == mask`\n */\n def testBits(mask: BigInt): Boolean = {\n (x & mask) == mask\n }\n\n /**\n * @param mask Bits to be tested\n * @param bits Bits to be compared\n * @return True if `(x & mask) == bits`\n */\n def testBits(mask: BigInt, bits: BigInt): Boolean = {\n (x & mask) == bits\n }\n\n /**\n * @param nBit Number of lower bits to be reinterpreted\n * @return Reinterpret the lower nBit as unsigned\n */\n def asUnsigned(nBit: Int): BigInt = {\n x & ((BigInt(1) << nBit) - 1)\n }\n\n /**\n * @param nBit Number of lower bits to be reinterpreted\n * @return Reinterpret the lower nBit as signed\n */\n def asSigned(nBit: Int): BigInt = {\n if (x.testBits(BigInt(1) << (nBit - 1))) { // negative\n x.asUnsigned(nBit) - (BigInt(1) << nBit)\n }\n else { // positive\n x.asUnsigned(nBit)\n }\n }\n\n /**\n * Get bits by specifying MSB and LSB in this BigInt\n * @param msb Most significant bit pos\n * @param lsb Least significant bit pos\n * @return Bits in BigInt (this[msb : lsb])\n */\n def bitSlice(msb: Int, lsb: Int): BigInt = {\n (x >> lsb) & ((BigInt(2) << (msb - lsb)) - 1)\n }\n\n /**\n * Slice BigInt into slices according to widths\n *\n * @param widths Widths of each slices\n * @return Seq of slices\n */\n def bitSlices(widths: Int*): Seq[BigInt] = {\n var lsb = 0\n widths.reverse.map(w => {\n val res = x.bitSlice(lsb + w - 1, lsb)\n lsb += w\n res\n }).reverse\n }\n\n /**\n * Slice BigInt into slices according to \"up8\" of specified widths\n *\n * @param widths Widths of each slices\n * @return result slices\n */\n def bitSlicesByteWise(widths: Int*): Seq[BigInt] = {\n var lsb = 0\n widths.reverse.map(w => {\n val res = x.bitSlice(lsb + w - 1, lsb)\n lsb += w.up8\n res\n }).reverse\n }\n\n /**\n * Get the value if treat the lower width bits as a Fixed-Point with\n * specified frac width.\n *\n * @param width Width of effective bits\n * @param fracWidth Width of fractional part\n * @return Value of the Fixed-Point\n */\n def valueAsFixPoint(width: Int, fracWidth: Int): Double = {\n x.asSigned(width).toDouble * math.pow(2.0, -fracWidth)\n }\n\n /**\n * Get the value if treat the lower width bits as a Fixed-Point with\n * specified frac width.\n *\n * @param width Width of effective bits\n * @param fracWidth Width of fractional part\n * @return Value of the Fixed-Point\n * @note This BigDecimal version of `valueAsFixPoint` is more accurate\n * than the Double version, when width or fracWidth is larger\n * than or near to 64, this version is recommended.\n */\n def valueAsFixPointInBigDecimal(width: Int, fracWidth: Int): BigDecimal = {\n BigDecimal(x.asSigned(width)) * BigDecimal(2.0).pow(-fracWidth)\n }\n }\n\n implicit class LongUtils(private val x: Long) extends AnyVal {\n /**\n * @return The minimum number divisible by 8 and no less than this Long\n */\n def up8: Long = if (x < 0) 0 else ((x - 1) / 8 + 1) * 8\n\n /**\n * @param mask Bits to be tested\n * @return True if `(x & mask) == mask`\n */\n def testBits(mask: Long): Boolean = {\n (x & mask) == mask\n }\n\n /**\n * @param mask Bits to be tested\n * @param bits Bits to be compared\n * @return True if `(x & mask) == bits`\n */\n def testBits(mask: Long, bits: Long): Boolean = {\n (x & mask) == bits\n }\n\n /**\n * @param nBit Number of lower bits to be reinterpreted\n * @return Reinterpret the lower nBit as unsigned\n */\n def asUnsigned(nBit: Int): Long = {\n require(nBit < 64)\n x & ((1L << nBit) - 1)\n }\n\n /**\n * @param nBit Number of lower bits to be reinterpreted\n * @return Reinterpret the lower nBit as signed\n */\n def asSigned(nBit: Int): Long = {\n require(nBit <= 64)\n if (nBit == 64) {\n x\n }\n else if (x.testBits(1L << (nBit - 1))) { // negative\n x.asUnsigned(nBit) - (1L << nBit)\n }\n else { // positive\n x.asUnsigned(nBit)\n }\n }\n\n def toBigInt: BigInt = BigInt(x)\n }\n\n implicit class IntUtils(private val x: Int) extends AnyVal {\n /**\n * @return The minimum number divisible by 8 and no less than this Int\n */\n def up8: Int = if (x < 0) 0 else ((x - 1) / 8 + 1) * 8\n\n /**\n * @param mask Bits to be tested\n * @return True if `(x & mask) == mask`\n */\n def testBits(mask: Int): Boolean = {\n (x & mask) == mask\n }\n\n /**\n * @param mask Bits to be tested\n * @param bits Bits to be compared\n * @return True if `(x & mask) == bits`\n */\n def testBits(mask: Int, bits: Int): Boolean = {\n (x & mask) == bits\n }\n\n /**\n * @param nBit Number of lower bits to be reinterpreted\n * @return Reinterpret the lower nBit as unsigned\n */\n def asUnsigned(nBit: Int): Int = {\n require(nBit < 32)\n x & ((1 << nBit) - 1)\n }\n\n /**\n * @param nBit Number of lower bits to be reinterpreted\n * @return Reinterpret the lower nBit as signed\n */\n def asSigned(nBit: Int): Int = {\n require(nBit <= 32)\n if (nBit == 32) {\n x\n }\n else if (x.testBits(1 << (nBit - 1))) { // negative\n x.asUnsigned(nBit) - (1 << nBit)\n }\n else { // positive\n x.asUnsigned(nBit)\n }\n }\n\n def toBigInt: BigInt = BigInt(x)\n }\n\n implicit class ByteSeqReinterpret(private val bytes: Seq[Byte]) extends AnyVal {\n def asS8(idx: Int): Int = {\n require(idx + 1 <= bytes.length)\n bytes(idx).toInt\n }\n\n def asU8(idx: Int): Int = {\n require(idx + 1 <= bytes.length)\n bytes(idx) & 0xFF\n }\n\n def asS16(idx: Int, isBigEndian: Boolean = false): Int = {\n require(idx + 2 <= bytes.length)\n val x: Int = if (isBigEndian) {\n bytes.slice(idx, idx + 2).foldLeft(0)((acc, byte) => (acc << 8) | (byte & 0xFF))\n }\n else {\n bytes.slice(idx, idx + 2).foldRight(0)((byte, acc) => (byte & 0xFF) | (acc << 8))\n }\n x.asSigned(16)\n }\n\n def asU16(idx: Int, isBigEndian: Boolean = false): Int = {\n require(idx + 2 <= bytes.length)\n val x: Int = if (isBigEndian) {\n bytes.slice(idx, idx + 2).foldLeft(0)((acc, byte) => (acc << 8) | (byte & 0xFF))\n }\n else {\n bytes.slice(idx, idx + 2).foldRight(0)((byte, acc) => (byte & 0xFF) | (acc << 8))\n }\n x\n }\n\n def asS32(idx: Int, isBigEndian: Boolean = false): Int = {\n require(idx + 4 <= bytes.length)\n val x: Int = if (isBigEndian) {\n bytes.slice(idx, idx + 4).foldLeft(0)((acc, byte) => (acc << 8) | (byte & 0xFF))\n }\n else {\n bytes.slice(idx, idx + 4).foldRight(0)((byte, acc) => (byte & 0xFF) | (acc << 8))\n }\n x\n }\n\n def asU32(idx: Int, isBigEndian: Boolean = false): Long = {\n require(idx + 4 <= bytes.length)\n val x: Long = if (isBigEndian) {\n bytes.slice(idx, idx + 4).foldLeft(0L)((acc, byte) => (acc << 8) | (byte & 0xFF))\n }\n else {\n bytes.slice(idx, idx + 4).foldRight(0L)((byte, acc) => (byte & 0xFF) | (acc << 8))\n }\n x.asUnsigned(32)\n }\n\n def asS64(idx: Int, isBigEndian: Boolean = false): Long = {\n require(idx + 8 <= bytes.length)\n val x: Long = if (isBigEndian) {\n bytes.slice(idx, idx + 8).foldLeft(0L)((acc, byte) => (acc << 8) | (byte & 0xFF))\n }\n else {\n bytes.slice(idx, idx + 8).foldRight(0L)((byte, acc) => (byte & 0xFF) | (acc << 8))\n }\n x\n }\n\n def asU64(idx: Int, isBigEndian: Boolean = false): BigInt = {\n require(idx + 8 <= bytes.length)\n val x: BigInt = if (isBigEndian) {\n bytes.slice(idx, idx + 8).foldLeft(BigInt(0))((acc, byte) => (acc << 8) | (byte & 0xFF))\n }\n else {\n bytes.slice(idx, idx + 8).foldRight(BigInt(0))((byte, acc) => (byte & 0xFF) | (acc << 8))\n }\n x.asUnsigned(64)\n }\n\n def asUInt(idx: Int, nBit: Int, isBigEndian: Boolean = false): BigInt = {\n require(nBit > 0, s\"In Seq[Byte].asUInt(), nBit must be > 0, got ${nBit}.\")\n val nBytes = (nBit - 1) / 8 + 1\n require(idx + nBytes <= bytes.length)\n val x: BigInt = if (isBigEndian) {\n bytes.slice(idx, idx + nBytes).foldLeft(BigInt(0))((acc, byte) => (acc << 8) | (byte & 0xFF))\n }\n else {\n bytes.slice(idx, idx + nBytes).foldRight(BigInt(0))((byte, acc) => (byte & 0xFF) | (acc << 8))\n }\n x.asUnsigned(nBit)\n }\n\n def asSInt(idx: Int, nBit: Int, isBigEndian: Boolean = false): BigInt = {\n require(nBit > 0, s\"In Seq[Byte].asInt(), nBit must be > 0, got ${nBit}.\")\n val nBytes = (nBit - 1) / 8 + 1\n require(idx + nBytes <= bytes.length)\n val y: BigInt = if (isBigEndian) {\n bytes.slice(idx, idx + nBytes).foldLeft(BigInt(0))((acc, byte) => (acc << 8) | (byte & 0xFF))\n }\n else {\n bytes.slice(idx, idx + nBytes).foldRight(BigInt(0))((byte, acc) => (byte & 0xFF) | (acc << 8))\n }\n y.asSigned(nBit)\n }\n }\n\n implicit class StrBitsUtils[+T <: StrBits](private val x: T) extends AnyVal {\n def hasData: Boolean = x.isInstanceOf[StrHasData]\n\n def hasStrb: Boolean = x.isInstanceOf[StrHasStrb]\n\n def hasKeep: Boolean = x.isInstanceOf[StrHasKeep]\n\n def hasLast: Boolean = x.isInstanceOf[StrHasLast]\n\n def hasId: Boolean = x.isInstanceOf[StrHasId]\n\n def hasDest: Boolean = x.isInstanceOf[StrHasDest]\n\n def hasUser: Boolean = x.isInstanceOf[StrHasUser]\n\n def dataWidth: Int = {\n x match {\n case y: StrHasData => y.data.getWidth\n case _ => 0\n }\n }\n\n def pokeDataIfExist(data: BigInt): Option[BigInt] = {\n x match {\n case y: StrHasData => {\n y.data match {\n case d: UInt => d.poke(data)\n case d: SInt => d.poke(data)\n case _ => y.data.poke(data.asUInt)\n }\n Some(data)\n }\n case _ => None\n }\n }\n\n def peekDataIfExist: Option[BigInt] = {\n x match {\n case y: StrHasData => {\n y.data match {\n case d: UInt => Some(d.peekInt())\n case d: SInt => Some(d.peekInt())\n case _ => Some(y.data.asUInt.peekInt())\n }\n }\n case _ => None\n }\n }\n\n def dataBytesCeil: Int = {\n x match {\n case y: StrHasData => (y.data.getWidth - 1) / 8 + 1\n case _ => 0\n }\n }\n\n def bytesPerBeat: Int = {\n x match {\n case y: StrHasData => (y.data.getWidth - 1) / 8 + 1\n case _ => 0\n }\n }\n\n def strbWidth: Int = {\n x match {\n case y: StrHasStrb => y.strb.getWidth\n case _ => 0\n }\n }\n\n def strbMask: BigInt = {\n (BigInt(1) << dataBytesCeil) - 1\n }\n\n def pokeStrbIfExist(strb: BigInt): Option[BigInt] = {\n x match {\n case y: StrHasStrb => {\n y.strb.poke(strb)\n Some(strb)\n }\n case _ => None\n }\n }\n\n def peekStrbIfExist: Option[BigInt] = {\n x match {\n case y: StrHasStrb => Some(y.strb.peekInt())\n case _ => None\n }\n }\n\n def peekStrbImplicit: BigInt = {\n x match {\n case y: StrHasStrb => y.strb.peekInt()\n case _ => strbMask\n }\n }\n\n def keepWidth: Int = {\n x match {\n case y: StrHasKeep => y.keep.getWidth\n case _ => 0\n }\n }\n\n def keepMask: BigInt = {\n (BigInt(1) << dataBytesCeil) - 1\n }\n\n def pokeKeepIfExist(keep: BigInt): Option[BigInt] = {\n x match {\n case y: StrHasKeep => {\n y.keep.poke(keep)\n Some(keep)\n }\n case _ => None\n }\n }\n\n def peekKeepIfExist: Option[BigInt] = {\n x match {\n case y: StrHasKeep => Some(y.keep.peekInt())\n case _ => None\n }\n }\n\n def peekKeepImplicit: BigInt = {\n x match {\n case y: StrHasKeep => y.keep.peekInt()\n case _ => keepMask\n }\n }\n\n def pokeLastIfExist(last: Boolean): Option[Boolean] = {\n x match {\n case y: StrHasLast => {\n y.last.poke(last)\n Some(last)\n }\n case _ => None\n }\n }\n\n def peekLastIfExist: Option[Boolean] = {\n x match {\n case y: StrHasLast => Some(y.last.peekBoolean())\n case _ => None\n }\n }\n\n def idWidth: Int = {\n x match {\n case y: StrHasId => y.id.getWidth\n case _ => 0\n }\n }\n\n def pokeIdIfExist(id: Long): Option[Long] = {\n x match {\n case y: StrHasId => {\n y.id.poke(BigInt(id))\n Some(id)\n }\n case _ => None\n }\n }\n\n def peekIdIfExist: Option[Long] = {\n x match {\n case y: StrHasId => Some(y.id.peekInt().toLong)\n case _ => None\n }\n }\n\n def destWidth: Int = {\n x match {\n case y: StrHasDest => y.dest.getWidth\n case _ => 0\n }\n }\n\n def pokeDestIfExist(dest: Long): Option[Long] = {\n x match {\n case y: StrHasDest => {\n y.dest.poke(BigInt(dest))\n Some(dest)\n }\n case _ => None\n }\n }\n\n def peekDestIfExist: Option[Long] = {\n x match {\n case y: StrHasDest => Some(y.dest.peekInt().toLong)\n case _ => None\n }\n }\n\n def userWidth: Int = {\n x match {\n case y: StrHasUser => y.user.getWidth\n case _ => 0\n }\n }\n\n def userBitsPerDataByte: Int = {\n require(x.isInstanceOf[StrHasData])\n val bpb = (x.asInstanceOf[StrHasData].data.getWidth - 1) / 8 + 1\n x match {\n case y: StrHasUser => (y.user.getWidth - 1) / bpb + 1\n case _ => 0\n }\n }\n\n def pokeUserIfExist(user: BigInt): Option[BigInt] = {\n x match {\n case y: StrHasUser => {\n y.user match {\n case u: UInt => u.poke(user)\n case u: SInt => u.poke(user)\n case _ => y.user.poke(user.asUInt)\n }\n // y.user.poke(user)\n Some(user)\n }\n case _ => None\n }\n }\n\n def peekUserIfExist: Option[BigInt] = {\n x match {\n case y: StrHasUser => {\n y.user match {\n case u: UInt => Some(u.peekInt())\n case u: SInt => Some(u.peekInt())\n case _ => Some(y.user.asUInt.peekInt())\n }\n // Some(y.user.peekInt())\n }\n case _ => None\n }\n }\n }\n\n /**\n * Chisel type or hardware of a FixPoint\n * @param bits Raw bits of FixPoint\n * @param fw Width of fractional part\n * @note\n * - Chisel type if bits is a chisel type (e.g.: SInt(16.W))\n * - Chisel hardware if bits is a chisel hardware (e.g.: 123.S(16.W))\n */\n sealed class FixPoint(val bits: SInt, private val fw: Int) extends Bundle {\n require(0 <= fw && fw < 128, s\"In FixPoint, fw must be >= 0 and < 128, but fw=${fw} got.\")\n require(bits.widthKnown)\n require(!bits.isLit)\n\n /**\n * @return total width\n */\n def getTotalWidth: Int = this.bits.getWidth\n\n /**\n * @return width of integer part (including sign bit).\n */\n def getIntWidth: Int = this.bits.getWidth - fw\n\n /**\n * @return width of fractional part.\n */\n def getFracWidth: Int = fw\n\n /**\n * @return Zero.\n */\n def zero: FixPoint = FixPoint.zero(bits.getWidth, fw)\n\n /**\n * @return Negative (0.0 - this).\n * @note width of result will be original width + 1.\n */\n def negative: FixPoint = FixPoint(0.S -& bits, fw)\n\n /**\n * @return Lowest FixPoint (negative with max abs).\n */\n def lowest: FixPoint = FixPoint.lowest(bits.getWidth, fw)\n\n /**\n * @return Highest FixPoint (positive with max abs).\n */\n def highest: FixPoint = FixPoint.highest(bits.getWidth, fw)\n\n /**\n * @return Epsilon FixPoint (positive with min abs).\n */\n def epsilon: FixPoint = FixPoint.epsilon(bits.getWidth, fw)\n\n /**\n * @return True if this is the lowest value (negative with max abs).\n */\n def isLowest: Bool = this.bits.asUInt === (1.U(1.W) ## 0.U((bits.getWidth - 1).W))\n\n /**\n * @return True if this is the highest value (positive with max abs).\n */\n def isHighest: Bool = this.bits.asUInt === (0.U(1.W) ## Fill(bits.getWidth - 1, 1.U(1.W)))\n\n /**\n * @return True if this is the epsilon value (positive with min abs).\n */\n def isEpsilon: Bool = this.bits.asUInt === (1.U(bits.getWidth.W))\n\n /**\n * Set this to the lowest value (negative with max abs).\n */\n def setToLowest: Unit = this.bits := (1.U(1.W) ## 0.U((bits.getWidth - 1).W)).asSInt\n\n /**\n * Set this to the highest value (positive with max abs).\n */\n def setToHighest: Unit = this.bits := (0.U(1.W) ## Fill(bits.getWidth - 1, 1.U(1.W))).asSInt\n\n /**\n * Set this to the epsilon value (positive with min abs).\n */\n def setToEpsilon: Unit = this.bits := 1.U(bits.getWidth.W).asSInt\n\n /**\n * @param value the value to be represented.\n */\n def setTo(value: Double): Unit = {\n require(inRangeAfterRound(value), s\"In FixPoint.setTo, ${value} can not fit in fix point binary with width=${bits.getWidth} and fw=${fw}.\")\n // this.bits := (value * math.pow(2.0, fw)).round.asSInt\n this.bits := FixPoint.round(value * math.pow(2.0, fw)).asSInt\n }\n\n /**\n * @param value the value to be represented.\n */\n def setTo(value: BigDecimal): Unit = {\n require(inRangeAfterRound(value))\n this.bits := FixPoint.round(value * BigDecimal(2.0).pow(fw)).asSInt\n }\n\n /**\n * @return Lowest value (negative with max abs) in Double.\n */\n def lowestInDouble: Double = FixPoint.lowestInDouble(bits.getWidth, fw)\n\n /**\n * @return Highest value (positive with max abs) in Double.\n */\n def highestInDouble: Double = FixPoint.highestInDouble(bits.getWidth, fw)\n\n /**\n * @return Epsilon value (positive with min abs) in Double.\n */\n def epsilonInDouble: Double = FixPoint.epsilonInDouble(fw)\n\n /**\n * @return Lowest value (negative with max abs) in BigDecimal.\n */\n def lowestInBigDecimal: BigDecimal = FixPoint.lowestInBigDecimal(bits.getWidth, fw)\n\n /**\n * @return Highest value (positive with max abs) in BigDecimal.\n */\n def highestInBigDecimal: BigDecimal = FixPoint.highestInBigDecimal(bits.getWidth, fw)\n\n /**\n * @return Epsilon value (positive with min abs) in BigDecimal.\n */\n def epsilonInBigDecimal: BigDecimal = FixPoint.epsilonInBigDecimal(fw)\n\n /**\n * Test whether the value can be fit into this FixPoint.\n * @param value The value to be tested.\n * @return True if the value can be fit into this FixPoint.\n */\n def inRange(value: Double): Boolean = FixPoint.inRange(bits.getWidth, fw, value)\n\n /**\n * Test whether the value can be fit into this FixPoint after rounded to nearest quantitative step.\n * @param value The value to be tested.\n * @return True if the rounded value can be fit into this FixPoint.\n * @note The round mode is specified in FixPoint.roundMode.\n */\n def inRangeAfterRound(value: Double): Boolean = FixPoint.inRangeAfterRound(bits.getWidth, fw, value)\n\n /**\n * Test whether the value can be fit into this FixPoint.\n * @param value The value to be test.\n * @return True if the value can be fit into this FixPoint.\n */\n def inRange(value: BigDecimal): Boolean = FixPoint.inRange(bits.getWidth, fw, value)\n\n /**\n * Test whether the value can be fit into this FixPoint after rounded to nearest quantitative step.\n * @param value The value to be tested.\n * @return True if the rounded value can be fit into this FixPoint.\n * @note The round mode is specified in FixPoint.roundMode.\n */\n def inRangeAfterRound(value: BigDecimal): Boolean = FixPoint.inRangeAfterRound(bits.getWidth, fw, value)\n\n /**\n * @param value assign a double constant/parameter\n * @note due to the characteristics of Fixpoint, value will be quantified (loss precision)\n */\n final def :=(value: Double): Unit = {\n require(inRangeAfterRound(value), s\"In FixPoint, ${value} can not fit in fix point binary with width=${bits.getWidth} and fw=${fw}.\")\n // this.bits := (value * math.pow(2.0, fw)).round.asSInt\n this.bits := FixPoint.round(value * math.pow(2.0, fw)).asSInt\n }\n\n /**\n * @param value assign a BigDecimal constant/parameter\n * @note due to the characteristics of Fixpoint, value will be quantified (loss precision)\n */\n final def :=(value: BigDecimal): Unit = {\n require(inRangeAfterRound(value), s\"In FixPoint, ${value} can not fit in fix point binary with width=${bits.getWidth} and fw=${fw}.\")\n // this.bits := (value * BigDecimal(2.0).pow(fw)).setScale(0, BigDecimal.RoundingMode.HALF_UP).toBigInt.asSInt\n this.bits := FixPoint.round(value * BigDecimal(2.0).pow(fw)).asSInt\n }\n\n /**\n * @param sint assign a SInt to integer part and clear fractional part.\n */\n final def :=(sint: SInt): Unit = {\n this.bits := (sint << fw)\n }\n\n /**\n * @param that assign another FixPoint\n * @note\n * - if fw of destination is larger, zeros will be fill in lsb.\n * - if fw of destination is smaller, tail bits in source will be discarded (loss precision).\n * - if iw of destination is larger, sign bit will be fill in msb.\n * - if iw of destination is smaller, msb will be discarded (overflow).\n */\n final def :=(that: FixPoint): Unit = {\n val bits = {\n if (this.fw > that.fw) (that.bits << (this.fw - that.fw)).asSInt\n else if (this.fw < that.fw) (that.bits >> (that.fw - this.fw)).asSInt\n else that.bits\n }\n this.bits := bits\n }\n\n private def matchPoint(that: FixPoint): (SInt, SInt, Int) = {\n val fw = math.max(this.fw, that.fw)\n val lBits = (this.bits << (fw - this.fw)).asSInt\n val rBits = (that.bits << (fw - that.fw)).asSInt\n (lBits, rBits, fw)\n }\n\n /**\n * @return Sum of 2 FixPoint\n * @note\n * - IW of result = max{opd1.IW, opd2.IW} + 1\n * - FW of result = max{opd1.FW, opd2.FW}\n */\n final def +(that: FixPoint): FixPoint = {\n val (l, r, fw) = matchPoint(that)\n val bits: SInt = l +& r\n new FixPoint(bits, fw)\n }\n\n /**\n * @return Subs of 2 FixPoint\n * @note\n * - IW of result = max{opd1.IW, opd2.IW} + 1\n * - FW of result = max{opd1.FW, opd2.FW}\n */\n final def -(that: FixPoint): FixPoint = {\n val (l, r, fw) = matchPoint(that)\n val bits: SInt = l -& r\n new FixPoint(bits, fw)\n }\n\n /**\n * @return Productor of 2 FixPoint\n * @note\n * - IW of result = opd1.IW + opd2.IW\n * - FW of result = opd1.FW + opd2.FW\n */\n final def *(that: FixPoint): FixPoint = {\n val fw = this.fw + that.fw\n val bits: SInt = this.bits * that.bits\n new FixPoint(bits, fw)\n }\n\n /**\n * @return True if 2 opd equals exactly\n */\n final def ===(that: FixPoint): Bool = {\n val (l, r, _) = matchPoint(that)\n Mux(l === r, true.B, false.B)\n }\n\n /**\n * @return True if 2 opd NOT exactly equals\n */\n final def =/=(that: FixPoint): Bool = {\n val (l, r, _) = matchPoint(that)\n Mux(l =/= r, true.B, false.B)\n }\n\n /**\n * @return True if left opd is less than right opd\n */\n final def <(that: FixPoint): Bool = {\n val (l, r, _) = matchPoint(that)\n Mux(l < r, true.B, false.B)\n }\n\n /**\n * @return True if left opd is less than or equal to right opd\n */\n final def <=(that: FixPoint): Bool = {\n val (l, r, _) = matchPoint(that)\n Mux(l <= r, true.B, false.B)\n }\n\n /**\n * @return True if left opd is larger than or equal to right opd\n */\n final def >=(that: FixPoint): Bool = {\n val (l, r, _) = matchPoint(that)\n Mux(l >= r, true.B, false.B)\n }\n\n /**\n * @return True if left opd is larger than to right opd\n */\n final def >(that: FixPoint): Bool = {\n val (l, r, _) = matchPoint(that)\n Mux(l > r, true.B, false.B)\n }\n\n private def shiftLeft(n: Int): FixPoint = {\n val w: Int = this.bits.getWidth\n (bits(w - 1) ## (bits(w - 2, 0) << n).take(w - 1)).asFixPoint(fw)\n }\n\n private def shiftRight(n: Int): FixPoint = {\n val w: Int = this.bits.getWidth\n (bits >> n).asSInt.extend(w).asFixPoint(fw)\n }\n\n private def shiftLeft(n: UInt): FixPoint = {\n val w: Int = this.bits.getWidth\n (bits(w - 1) ## (bits(w - 2, 0) << n).take(w - 1)).asFixPoint(fw)\n }\n\n private def shiftRight(n: UInt): FixPoint = {\n val w: Int = this.bits.getWidth\n (bits >> n).asSInt.extend(w).asFixPoint(fw)\n }\n\n /**\n * Keep sign bit and shift other bits, eqv. to x * 2**n.\n * @param n bits to be shifted, n can be negative.\n * @return shift result.\n * @note CAUTION: may cause value overflow.\n */\n final def <<<(n: Int): FixPoint = {\n if(n > 0)\n shiftLeft(n)\n else if(n < 0)\n shiftRight(-n)\n else\n this\n }\n\n /**\n * Keep sign bit and shift other bits, eqv. to x / 2**n.\n * @param n bits to be shifted, n can be negative.\n * @return shift result.\n * @note CAUTION: may cause value overflow when `n < 0`.\n */\n final def >>>(n: Int): FixPoint = {\n if(n > 0)\n shiftRight(n)\n else if(n < 0)\n shiftLeft(-n)\n else\n this\n }\n\n /**\n * Keep sign bit and shift other bits, eqv. to x * 2**n.\n * @param n bits to be shifted, n can be negative.\n * @return shift result.\n * @note CAUTION: may cause value overflow.\n */\n final def <<<(n: SInt): FixPoint = {\n MuxCase(this, Seq(\n (n > 0.S) -> shiftLeft(n.asUInt),\n (n < 0.S) -> shiftRight((-n).asUInt)\n ))\n }\n\n /**\n * Keep sign bit and shift other bits, eqv. to x / 2**n.\n * @param n bits to be shifted, n can be negative.\n * @return shift result.\n * @note CAUTION: may cause value overflow when `n < 0`.\n */\n final def >>>(n: SInt): FixPoint = {\n MuxCase(this, Seq(\n (n > 0.S) -> shiftRight(n.asUInt),\n (n < 0.S) -> shiftLeft((-n).asUInt)\n ))\n }\n\n /**\n * Keep sign bit and shift other bits, eqv. to x * 2**n.\n * @param n bits to be shifted.\n * @return shift result.\n */\n", "right_context": "\n /**\n * Keep sign bit and shift other bits, eqv. to x / 2**n.\n * @param n bits to be shifted.\n * @return shift result.\n */\n final def >>>(n: UInt): FixPoint = shiftRight(n)\n\n /**\n * Truncate\n *\n * @param newFracWidth Width of fractional part of result\n * @return Truncated result\n * @note same as Floor()\n */\n def truncate(newFracWidth: Int = 0): FixPoint = {\n require(0 <= newFracWidth && newFracWidth < fw)\n val shift = fw - newFracWidth\n new FixPoint((this.bits >> shift).asSInt, newFracWidth)\n }\n\n /**\n * Floor\n *\n * @param newFracWidth Width of fractional part of result\n * @return Floor result\n * @note\n * - Fraction width of result = newFracWidth\n * - Integer width of result = original integer width\n */\n def floor(newFracWidth: Int = 0): FixPoint = {\n require(0 <= newFracWidth && newFracWidth < fw)\n val shift = fw - newFracWidth\n new FixPoint((this.bits >> shift).asSInt, newFracWidth)\n }\n\n /**\n * Ceil\n *\n * @param newFracWidth Width of fractional part of result\n * @return Ceil result\n * @note\n * - Fraction width of result = newFracWidth\n * - Integer width of result = original integer width + 1\n */\n def ceil(newFracWidth: Int = 0): FixPoint = {\n require(0 <= newFracWidth && newFracWidth < fw)\n val shift = fw - newFracWidth\n val bits = 0.S -& this.bits\n new FixPoint(-(bits >>> shift).asSInt, newFracWidth)\n }\n\n /**\n * Truncate by rounding (half ceiling, rounding to +inf)\n *\n * @param newFracWidth Width of fractional part of result\n * @return Truncated result\n * @note\n * - this \"round\" is actually half ceiling (round half to +inf).\n * - due to implementation complexity, this is the most economy\n * rounding type, and other rounding types are not implemented.\n */\n def round(newFracWidth: Int = 0): FixPoint = {\n require(newFracWidth < fw)\n val shift = fw - newFracWidth\n val bits = Mux(\n this.bits(shift - 1),\n 1.S + (this.bits >> shift).asSInt,\n (this.bits >> shift).asSInt\n )\n new FixPoint(bits, newFracWidth)\n }\n\n /**\n * @return Raw bits of fractional part\n */\n def getFractionBits: UInt = {\n this.bits(this.getFracWidth - 1, 0).asUInt\n }\n\n /**\n * @return FixPoint represents only pure fractional part (clear integer part).\n * @note\n * - fractional width = original fractional width\n * - integer width = 1\n */\n def getPureFraction: FixPoint = {\n (0.U(1.W) ## this.getFractionBits).asFixPoint(this.getFracWidth)\n }\n\n /**\n * @return Raw bits of this FixPoint\n */\n def asSInt: SInt = this.bits\n\n /**\n * @param fw new fractional part width\n * @return Reinterpret as a FixPoint with new fractional part width\n */\n def asFixPoint(fw: Int): FixPoint = {\n new FixPoint(bits, fw)\n }\n\n /**\n * @return Raw bits of this FixPoint\n */\n def getBits: SInt = this.bits\n\n /**\n * @return Convert to SInt by truncate fractional part\n * @note Same as floorToSInt\n */\n def toSInt: SInt = this.truncate().bits\n\n /**\n * @return Maximum SInt not larger than this FixPoint\n */\n def floorToSInt: SInt = this.floor().bits\n\n /**\n * @return Minimum SInt not smaller than this FixPoint\n */\n def ceilToSInt: SInt = this.ceil().bits\n\n /**\n * @return Nearest SInt to this FixPoint\n * @note\n * - this \"round\" is actually half ceiling (round half to +inf).\n * - due to implementation complexity, this is the most economy\n * rounding type, and other rounding types are not implemented yet.\n */\n def roundToSInt: SInt = this.round().bits\n \n /**\n * @param fw new fractional part width\n * @return Convert to new FixPoint with specified fractional part width\n */\n def toFixPoint(fw: Int): FixPoint = {\n val bits = {\n if(fw > this.fw) this.bits << (fw - this.fw)\n else if(fw < this.fw) this.bits >> (this.fw - fw)\n else this.bits\n }\n new FixPoint(bits.asSInt, fw)\n }\n\n /**\n * @return Peek value as Double\n */\n def peekDouble(): Double = {\n val d = this.bits.peekInt()\n d.toDouble * math.pow(2.0, -fw)\n }\n\n /**\n * @return Peek value as BigDecimal\n */\n def peekBigDecimal(): BigDecimal = {\n val d = this.bits.peekInt()\n BigDecimal(d) * BigDecimal(2.0).pow(-fw)\n }\n }\n\n object FixPoint {\n\n /**\n * RoundMode.Up: round half away from 0.\n * RoundMode.Down: round half near to 0.\n * RoundMode.Even: round half to even number.\n * RoundMode.Ceil: round half to +inf.\n * RoundMode.Floor: round half to -inf.\n */\n object RoundMode extends Enumeration {\n val Up, Down, Even, Ceil, Floor = Value\n }\n\n /**\n * Change this to specified rounding behavior for quantifying Double or\n * BigDecimal value to FixPoint.\n */\n val roundMode: RoundMode.Value = RoundMode.Even\n\n def round(x: Double): Long = {\n roundMode match {\n case RoundMode.Up => x.halfUp\n case RoundMode.Down => x.halfDown\n case RoundMode.Even => x.halfEven\n case RoundMode.Ceil => x.halfCeil\n case RoundMode.Floor => x.halfFloor\n }\n }\n\n def round(x: BigDecimal): BigInt = {\n roundMode match {\n case RoundMode.Up => x.halfUp\n case RoundMode.Down => x.halfDown\n case RoundMode.Even => x.halfEven\n case RoundMode.Ceil => x.halfCeil\n case RoundMode.Floor => x.halfFloor\n }\n }\n\n /**\n * Create a Chisel type of FixPoint\n *\n * @param width total width\n * @param fw fraction width (or binary point position)\n * @return a Chisel type\n */\n def apply(width: Width, fw: Int): FixPoint = {\n new FixPoint(SInt(width), fw)\n }\n\n /**\n * Create a hardware of FixPoint\n *\n * @param bits Raw bits for Fixpoint hardware, width of bits is the\n * total width of FixPoint\n * @param fw fraction width (or binary point position)\n * @return a hardware of FixPoint\n */\n def apply(bits: SInt, fw: Int): FixPoint = {\n val res = Wire(FixPoint(bits.getWidth.W, fw))\n res.bits := bits\n res\n }\n\n /**\n * Create a hardware of FixPoint\n *\n * @param width total width\n * @param fw fraction width (or binary point position)\n * @param value double value to be represent\n * @return the FixPoint hardware created\n */\n def apply(width: Width, fw: Int, value: Double): FixPoint = {\n val res = Wire(FixPoint(width, fw))\n res := value\n res\n }\n\n /**\n * Create a Chisel type of FixPoint by specified possible lowest value\n * instead of width.\n *\n * @param fw Width of fractional part.\n * @param possibleLowest Possible lowest value may be presented by the\n * returned FixPoint.\n * @return Chisel type of FixPoint.\n */\n def byLowest(fw: Int, possibleLowest: Double): FixPoint = {\n require(fw >= 0)\n require(possibleLowest <= -1.0)\n // val m = (-possibleLowest * math.pow(2.0, fw)).round\n val m = FixPoint.round(-possibleLowest * math.pow(2.0, fw))\n val width = log2Up(m) + 1\n new FixPoint(SInt(width.W), fw)\n }\n\n /**\n * Create a Chisel type of FixPoint by specified possible highest value\n * instead of width.\n *\n * @param fw Width of fractional part.\n * @param possibleHighest Possible highest value may be presented by the\n * returned FixPoint.\n * @return Chisel type of FixPoint.\n */\n def byHighest(fw: Int, possibleHighest: Double): FixPoint = {\n require(fw >= 0)\n require(possibleHighest >= 0.0)\n // val m = 1 + (possibleHighest * math.pow(2.0, fw)).round\n val m = 1 + FixPoint.round(possibleHighest * math.pow(2.0, fw))\n val width = log2Up(m) + 1\n new FixPoint(SInt(width.W), fw)\n }\n\n /**\n * Create a Chisel type of FixPoint by specified value range instead\n * of width.\n *\n * @param fw Width of fractional part.\n * @param lowest Possible lowest value may be presented by the returned\n * FixPoint.\n * @param highest Possible highest value may be presented by the\n * returned Fixpoint.\n * @return Chisel type of FixPoint.\n */\n def byRange(fw: Int, lowest: Double, highest: Double): FixPoint = {\n require(fw >= 0)\n require(lowest <= -1.0 && highest >= 0.0)\n val epsilon = math.pow(0.5, fw)\n val upLimit =\n if(-lowest > highest + epsilon)\n -lowest\n else\n highest + epsilon\n // val m = (upLimit * math.pow(2.0, fw)).round\n val m = FixPoint.round(upLimit * math.pow(2.0, fw))\n val width = log2Up(m) + 1\n new FixPoint(SInt(width.W), fw)\n }\n\n /**\n * Create a Chisel type of FixPoint by specified possible lowest value\n * instead of width.\n *\n * @param possibleLowest Possible lowest value may be presented by the\n * returned FixPoint.\n * @param fw Width of fractional part.\n * @return Chisel type of FixPoint.\n */\n def byLowest(fw: Int, possibleLowest: BigDecimal): FixPoint = {\n require(fw >= 0)\n require(possibleLowest <= -1.0)\n // val m = (-possibleLowest * BigDecimal(2.0).pow(fw)).setScale(0, BigDecimal.RoundingMode.HALF_UP).toBigInt\n val m = FixPoint.round(-possibleLowest * BigDecimal(2.0).pow(fw))\n val width = log2Up(m) + 1\n new FixPoint(SInt(width.W), fw)\n }\n\n /**\n * Create a Chisel type of FixPoint by specified possible highest value\n * instead of width.\n *\n * @param possibleHighest Possible highest value may be presented by the\n * returned FixPoint.\n * @param fw Width of fractional part.\n * @return Chisel type of FixPoint.\n */\n def byHighest(fw: Int, possibleHighest: BigDecimal): FixPoint = {\n require(fw >= 0)\n require(possibleHighest >= 0.0)\n // val m = 1 + (possibleHighest * BigDecimal(2.0).pow(fw)).setScale(0, BigDecimal.RoundingMode.HALF_UP).toBigInt\n val m = 1 + FixPoint.round(possibleHighest * BigDecimal(2.0).pow(fw))\n val width = log2Up(m) + 1\n new FixPoint(SInt(width.W), fw)\n }\n\n /**\n * Create a Chisel type of FixPoint by specified value range instead\n * of width.\n *\n * @param fw Width of fractional part.\n * @param lowest Possible lowest value may be presented by the returned\n * FixPoint.\n * @param highest Possible highest value may be presented by the\n * returned Fixpoint.\n * @return Chisel type of FixPoint.\n */\n def byRange(fw: Int, lowest: BigDecimal, highest: BigDecimal): FixPoint = {\n require(fw >= 0)\n require(lowest <= -1.0 && highest >= 0.0)\n val epsilon = BigDecimal(0.5).pow(fw)\n val upLimit =\n if(-lowest > highest + epsilon)\n -lowest\n else\n highest + epsilon\n // val m = (upLimit * BigDecimal(2.0).pow(fw)).setScale(0, BigDecimal.RoundingMode.HALF_UP).toBigInt\n val m = FixPoint.round(upLimit * BigDecimal(2.0).pow(fw))\n val width = log2Up(m) + 1\n new FixPoint(SInt(width.W), fw)\n }\n\n def zero(w: Int, fw: Int): FixPoint = {\n require(w >= 1 && fw >= 0)\n 0.S(w.W).asFixPoint(fw)\n }\n\n /**\n * @param w Total width\n * @param fw Fractional part width\n * @return Lowest (negative with max abs) FixPoint.\n */\n def lowest(w: Int, fw: Int): FixPoint = {\n require(w >= 1 && fw >= 0)\n (1.U(1.W) ## 0.U((w - 1).W)).asFixPoint(fw)\n }\n\n /**\n * @param w Total width\n * @param fw Fractional part width\n * @return Highest (positive with max abs) FixPoint.\n */\n def highest(w: Int, fw: Int): FixPoint = {\n require(w >= 1 && fw >= 0)\n (0.U(1.W) ## Fill(w - 1, 1.U(1.W))).asFixPoint(fw)\n }\n\n /**\n * @param w Total width\n * @param fw Fractional part width\n * @return Epsilon (positive with min abs) FixPoint.\n */\n def epsilon(w: Int, fw: Int): FixPoint = {\n require(w >= 1 && fw >= 0)\n (1.S(w.W)).asFixPoint(fw)\n }\n\n /**\n * @param w Total width\n * @param fw Fractional part width\n * @return Lowest (negative with max abs) FixPoint value in Double.\n */\n def lowestInDouble(w: Int, fw: Int): Double = {\n require(w >= 1 && fw >= 0)\n -math.pow(2.0, w - 1 - fw)\n }\n\n /**\n * @param w Total width\n * @param fw Fractional part width\n * @return Highest (positive with max abs) FixPoint value in Double.\n */\n def highestInDouble(w: Int, fw: Int): Double = {\n require(w >= 1 && fw >= 0)\n math.pow(2.0, w - 1 - fw) - math.pow(2.0, -fw)\n }\n\n /**\n * @param fw Fractional part width\n * @return psilon (positive with min abs) FixPoint value in Double.\n */\n def epsilonInDouble(fw: Int): Double = {\n require(fw >= 0)\n math.pow(2.0, -fw)\n }\n\n /**\n * @param w Total width\n * @param fw Fractional part width\n * @return Lowest (negative with max abs) FixPoint value in BigDecimal.\n */\n def lowestInBigDecimal(w: Int, fw: Int): BigDecimal = {\n -BigDecimal(2.0).pow(w - 1 - fw)\n }\n\n /**\n * @param w Total width\n * @param fw Fractional part width\n * @return Highest (positive with max abs) FixPoint value in BigDecimal.\n */\n def highestInBigDecimal(w: Int, fw: Int): BigDecimal = {\n BigDecimal(2.0).pow(w - 1 - fw) - BigDecimal(2.0).pow(-fw)\n }\n\n /**\n * @param fw Fractional part width\n * @return psilon (positive with min abs) FixPoint value in BigDecimal.\n */\n def epsilonInBigDecimal(fw: Int): BigDecimal = {\n BigDecimal(2.0).pow(-fw)\n }\n\n /**\n * @param w Total width\n * @param fw Fractional part width\n * @param value value to be tested\n * @return True if value can be fit into FixPoint\n */\n def inRange(w: Int, fw: Int, value: Double): Boolean = {\n lowestInDouble(w, fw) <= value && value <= highestInDouble(w, fw)\n }\n\n /**\n * @param w Total width\n * @param fw Fractional part width\n * @param value value to be tested\n * @return True if value can be fit into FixPoint after round to nearest quantitative steps.\n * @note The round mode is specified in FixPoint.roundMode.\n */\n def inRangeAfterRound(w: Int, fw: Int, value: Double): Boolean = {\n val rounded = FixPoint.round(value * math.pow(2.0, fw)) * math.pow(2.0, -fw)\n lowestInDouble(w, fw) <= rounded && rounded <= highestInDouble(w, fw)\n }\n\n /**\n * @param w Total width\n * @param fw Fractional part width\n * @param value value to be tested\n * @return True if value can be fit into FixPoint\n */\n def inRange(w: Int, fw: Int, value: BigDecimal): Boolean = {\n val low = lowestInBigDecimal(w, fw)\n val high = highestInBigDecimal(w, fw)\n low <= value && value <= high\n }\n\n /**\n * @param w Total width\n * @param fw Fractional part width\n * @param value value to be tested\n * @return True if value can be fit into FixPoint after round to nearest quantitative steps\n * @note The round mode is specified in FixPoint.roundMode.\n */\n def inRangeAfterRound(w: Int, fw: Int, value: BigDecimal): Boolean = {\n // val rounded = (value * BigDecimal(2.0).pow(fw)).setScale(0, BigDecimal.RoundingMode.HALF_UP) * BigDecimal(2.0).pow(-fw)\n val rounded = BigDecimal(FixPoint.round(value * BigDecimal(2.0).pow(fw))) * BigDecimal(2.0).pow(-fw)\n lowestInBigDecimal(w, fw) <= rounded && rounded <= highestInBigDecimal(w, fw)\n }\n }\n\n implicit class FromDoubleToFixPoint(private val x: Double) extends AnyVal {\n /**\n * Convert this double to FixPoint.\n * @param width total width\n * @param fw fractional part width\n * @return the FixPoint hardware represent the value of double.\n * @note\n * - Rntime requirement violation will occur if value can not be fitted in specified widths.\n * - Value will be quantified due to limited fractional part width (loss precision).\n * - The round mode is specified in FixPoint.roundMode.\n */\n def toFixPoint(width: Width, fw: Int): FixPoint = {\n val res = Wire(FixPoint(width, fw))\n res := x\n res\n }\n\n /**\n * Convert this double to FixPoint.\n * @param width total width\n * @param fw fractional part width\n * @return the FixPoint hardware represent the value of double.\n * @note\n * - Runtime requirement violation will occur if value can not be fitted in specified widths.\n * - Value will be quantified due to limited fractional part width (loss precision).\n * - The round mode is specified in FixPoint.roundMode.\n */\n def F(width: Width, fw: Int): FixPoint = {\n val res = Wire(FixPoint(width, fw))\n res := x\n res\n }\n\n /**\n * Get raw bit (as Long) of the FixPoint presenting this double.\n * @param width total width\n * @param fw fractional part width\n * @return Raw bit of the FixPoint represent the value of double.\n */\n def toFixPoint(width: Int, fw: Int): Long = {\n require(width <= 64 && fw < 64)\n require(FixPoint.inRange(width, fw, x))\n // (x * math.pow(2.0, fw)).round\n FixPoint.round(x * math.pow(2.0, fw))\n }\n }\n\n implicit class FromBigDecimalToFixPoint(private val x: BigDecimal) extends AnyVal {\n /**\n * Convert this BigDecimal to FixPoint.\n * @param width total width\n * @param fw fractional part width\n * @return the FixPoint hardware represent the value of BigDecimal.\n * @note\n * - Runtime requirement violation will occur if value can not be fitted in specified widths.\n * - Value will be quantified due to limited fractional part width (loss precision).\n * - The round mode is specified in FixPoint.roundMode.\n */\n def toFixPoint(width: Width, fw: Int): FixPoint = {\n val res = Wire(FixPoint(width, fw))\n res := x\n res\n }\n\n /**\n * Convert this BigDecimal to FixPoint.\n * @param width total width\n * @param fw fractional part width\n * @return the FixPoint hardware represent the value of BigDecimal.\n * @note\n * - Runtime requirement violation will occur if value can not be fitted in specified widths.\n * - Value will be quantified due to limited fractional part width (loss precision).\n * - The round mode is specified in FixPoint.roundMode.\n */\n def F(width: Width, fw: Int): FixPoint = {\n val res = Wire(FixPoint(width, fw))\n res := x\n res\n }\n\n /**\n * Get raw bit (as BigInt) of the FixPoint presenting this BigDecimal.\n * @param width total width\n * @param fw fractional part width\n * @return Raw bit of the FixPoint represent the value of BigDecimal.\n */\n def toFixPoint(width: Int, fw: Int): BigInt = {\n require(width <= 128 && fw < 128)\n require(FixPoint.inRange(width, fw, x))\n // (x * BigDecimal(2.0).pow(fw)).setScale(0, BigDecimal.RoundingMode.HALF_UP).toBigInt\n FixPoint.round(x * BigDecimal(2.0).pow(fw))\n }\n }\n\n implicit class DoubleUtils(private val x: Double) extends AnyVal {\n\n /**\n * Round half to +inf, alias of Double.round.\n * @return Round by half ceiling of this Double.\n */\n def halfCeil: Long = x.round\n\n /**\n * Round half to -inf\n * @return Round by half floor of this Double.\n */\n def halfFloor: Long = -(-x).round\n\n /**\n * Round half away from 0.\n * @return Round by half up of this Double.\n */\n def halfUp: Long = {\n if(x >= 0) x.round\n else -(-x).round\n }\n\n /**\n * Round half near to 0.\n * @return Round by half down of this Double.\n */\n def halfDown: Long = {\n if(x >= 0) -(-x).round\n else x.round\n }\n\n /**\n * Round half to even number.\n * @return Round by half even of this Double.\n */\n def halfEven: Long = {\n if(x.toLong % 2L == 0L)\n x.halfDown\n else\n x.halfUp\n }\n\n // template\n // constexpr T PhaseCycle (T x)\n // {\n // return std::floor((x + (T)M_PI) / (2 * (T)M_PI));\n // }\n\n /**\n * @return domain index of cycling [-pi, pi) domains.\n */\n def phaseCycle: Double = {\n math.floor((x + math.Pi) / (2.0 * math.Pi))\n }\n\n // template\n // constexpr T PhaseWrap(T x)\n // {\n // return x - 2 * (T)M_PI * PhaseCycle(x);\n // }\n\n /**\n * @return wrap phase into [-pi, pi) domains.\n */\n def phaseWrap: Double = {\n x - 2.0 * math.Pi * phaseCycle\n }\n\n // template\n // constexpr T PhaseUnwrap(T x, T a)\n // {\n // return x + 2 * (T)M_PI * PhaseCycle(a - x);\n // }\n\n /**\n * @param a reference phase.\n * @return unwrap phase to near the reference phase.\n */\n def phaseUnwrap(a: Double = 0.0): Double = {\n x + 2.0 * math.Pi * (a - x).phaseCycle\n }\n\n /**\n * @param y another phase.\n * @return phase diff in [-pi, pi) of two phases.\n */\n def phaseDiff(y: Double): Double = {\n (x - y).phaseUnwrap()\n }\n\n // template\n // constexpr T Clamp(T x, T l, T h)\n // {\n // return x > h ? h :\n // x < l ? l : x;\n // }\n\n /**\n * @param l low boundary\n * @param h high boundary\n * @return clamp this double into [l, h]\n * @note\n * - same as clip(l, h)\n */\n def clamp(l: Double, h: Double): Double = {\n if (x > h) h\n else if (x < l) l\n else x\n }\n\n /**\n * @param l low boundary\n * @param h high boundary\n * @return clip this double into [l, h]\n * @note\n * - same as clamp(l, h)\n */\n def clip(l: Double, h: Double): Double = {\n if (x > h) h\n else if (x < l) l\n else x\n }\n\n /**\n * @param l negative corrosion amount\n * @param h positive corrosion amount\n * @return corroded this double by specified amount\n * @note\n * - if x > h, return x - h\n * - if x < l, return x - l\n */\n def corrod(l: Double, h: Double): Double = {\n if (x > h) x - h\n else if (x < l) x - l\n else 0.0\n }\n\n // template \n // inline T Map2Unit(T x, T l, T h)\n // {\n // return (x - l) / (h - l);\n // }\n\n /**\n * @param l low boundary of range\n * @param h high boundary of range\n * @return map linearly this double in specified range into [0, 1]\n */\n def mapRange2Unit(l: Double, h: Double): Double = {\n (x - l) / (h - l)\n }\n\n // template \n // inline T Map2Range(T x, T l, T h)\n // {\n // return x * (h - l) + l;\n // }\n\n /**\n * @param l low boundary of range\n * @param h high boundary of range\n * @return map linearly this double in [0, 1] into [l, h]\n */\n def mapUnit2Range(l: Double, h: Double): Double = {\n x * (h - l) + l\n }\n\n /**\n * @param fromL low boundary of source range\n * @param fromH high boundary of source range\n * @param toL low boundary of destination range\n * @param toH high boundary of destination range\n * @return map linearly this double in [fromL, formH] into [toL, toH]\n */\n def mapFromTo(fromL: Double, fromH: Double, toL: Double, toH: Double): Double = {\n (x - fromL) / (fromH - fromL) * (toH - toL) + toL\n }\n\n // template \n // inline T Wrap(T x, T l, T h)\n // {\n // T d = h - l;\n // return x - std::floor((x - l) / d) * d;\n // }\n\n /**\n * @param l low boundary of domain\n * @param h high boundary of domain\n * @return domain index of cycling [l, h) domains.\n */\n def wrap(l: Double, h: Double): Double = {\n val d = h - l\n x - math.floor((x - l) / d) * d\n }\n\n // template \n // inline T Unwrp(T x, T l, T h, T a)\n // {\n // T d = (h - l) * (T)0.5;\n // return x - a > d ? x - (h - l) :\n // x - a < -d ? x + (h - l) : x;\n // }\n\n /**\n * @param l low boundary of domain\n * @param h high boundary of domain\n * @param a reference value\n * @return unwrap this double to near the reference value.\n */\n def unwrap(l: Double, h: Double, a: Double = 0.0): Double = {\n val d = (h - l) * 0.5\n if (x - a > d)\n x - (h - l)\n else if (x - a < -d)\n x + (h - l)\n else\n x\n }\n }\n\n implicit class BigDecimalUtils(private val x: BigDecimal) extends AnyVal {\n def halfUp: BigInt = {\n x.setScale(0, BigDecimal.RoundingMode.HALF_UP).toBigInt\n }\n def halfDown: BigInt = {\n x.setScale(0, BigDecimal.RoundingMode.HALF_DOWN).toBigInt\n }\n def halfEven: BigInt = {\n x.setScale(0, BigDecimal.RoundingMode.HALF_EVEN).toBigInt\n }\n def halfCeil: BigInt = {\n if(x >= BigDecimal(0.0))\n x.setScale(0, BigDecimal.RoundingMode.HALF_UP).toBigInt\n else\n x.setScale(0, BigDecimal.RoundingMode.HALF_DOWN).toBigInt\n }\n def halfFloor: BigInt = {\n if(x >= BigDecimal(0.0))\n x.setScale(0, BigDecimal.RoundingMode.HALF_DOWN).toBigInt\n else\n x.setScale(0, BigDecimal.RoundingMode.HALF_UP).toBigInt\n }\n }\n\n /**\n * Greatest common divisor of 2 integer\n *\n * @param u One integer\n * @param v Another integer\n * @tparam T Type of integers\n * @return GCD of `u` and `v`\n */\n def GCD[T: Integral](u: T, v: T): T = {\n val int = implicitly[Integral[T]]\n import int.mkNumericOps\n if (v == 0) u\n else GCD(v, u % v)\n }\n\n /**\n * Least common multiple of 2 integer\n *\n * @param u One integer\n * @param v Another integer\n * @tparam T Type of integer\n * @return LCM of `u` and `v`\n */\n def LCM[T: Integral](u: T, v: T): T = {\n val int = implicitly[Integral[T]]\n import int.mkNumericOps\n u * v / GCD(u, v)\n }\n\n def phaseDiff(x: Double, y: Double): Double = {\n (x - y).phaseUnwrap()\n }\n\n def asinh(x: Double): Double = {\n // import scala.math._\n log(x + sqrt(x * x + 1))\n }\n\n def acosh(x: Double): Double = {\n // import scala.math._\n if (x < 1) Double.NaN\n else log(x + sqrt(x * x - 1))\n }\n\n def atanh(x: Double): Double = {\n // import scala.math._\n if (x.abs >= 1) Double.NaN\n else 0.5 * log((1 + x) / (1 - x))\n }\n\n def elemWiseDiff[T: Numeric](x: Seq[T], y: Seq[T]): Seq[T] = {\n val num = implicitly[Numeric[T]]\n import num.mkNumericOps\n x.zip(y).map { case (x, y) => x - y }\n }\n\n def maxAndRms[T: Numeric](x: Seq[T]): (T, Int, Double) = {\n val num = implicitly[Numeric[T]]\n import num._\n val (max, mi, pwr) = x.zipWithIndex.foldLeft((zero, -1, 0.0)) {\n case ((max, mi, pwr), (x, i)) => {\n val abs = x.abs\n val sqr = x.toDouble * x.toDouble\n val (new_max, new_mi) = if (abs > max) (abs, i) else (max, mi)\n (new_max, new_mi, pwr + sqr)\n }\n }\n (max, mi, math.sqrt(pwr / x.length))\n }\n\n def minAndIndices[T: Numeric](x: Seq[T]): (T, Seq[Int]) = {\n val min = x.min\n val minIndices = x.zipWithIndex.collect{\n case (v, i) if v == min => i\n }\n (min, minIndices)\n }\n\n def maxAndIndices[T: Numeric](x: Seq[T]): (T, Seq[Int]) = {\n val max = x.max\n val maxIndices = x.zipWithIndex.collect{\n case (v, i) if v == max => i\n }\n (max, maxIndices)\n }\n\n def ReadCsvData(fileName: String, encoding: String = \"UTF-8\"): Array[Array[Double]] = {\n import java.nio.file.{Files, Paths}\n import scala.io.Source\n import scala.collection.mutable.ArrayBuffer\n\n val exist: Boolean = Files.exists(Paths.get(fileName))\n if(exist) {\n val colBuffer = ArrayBuffer[Array[Double]]()\n val source = Source.fromFile(fileName, encoding)\n val lines = source.getLines()\n lines.foreach(l => {\n val elems = l.split(',')\n val row = elems.map(e => {\n try { e.toDouble }\n catch { case _: Throwable => Double.NaN }\n })\n colBuffer += row\n })\n source.close()\n colBuffer.toArray\n }\n else {\n Array.empty[Array[Double]]\n }\n }\n\n}\n", "groundtruth": " final def <<<(n: UInt): FixPoint = shiftLeft(n)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "FPGA-Application-Development-and-Simulation", "path": "FPGA-Application-Development-and-Simulation/chisel/src/main/scala/temp.scala", "left_context": "import chisel3._\nimport loywong.util._\n\nclass abcd {\n val _a = Wire(Bool())\n val _b = Wire(Bool())\n val _c = _a ^ _b\n val _d = !(_a ^ _b)\n def con_ac(a: Bool, c: Bool) = {\n _a := a\n c := _c\n }\n def con_bd(b: Bool, d: Bool) = {\n _b := b\n d := _d\n }\n}\n\nclass test_abcd extends Module {\n //val io = FlatIO(new Bundle {\n val a = IO( Input(Bool()))\n", "right_context": " val c = IO(Output(Bool()))\n val d = IO(Output(Bool()))\n //})\n val the_abcd = new abcd\n the_abcd.con_ac(a, c)\n the_abcd.con_bd(b, d)\n}\n\nclass test_catbytewise extends Module {\n val io = IO(new Bundle {\n val a = Input(UInt(3.W))\n val b = Input(SInt(9.W))\n val c = Input(UInt(8.W))\n val d = Input(SInt(12.W))\n val o = Output(UInt(48.W))\n })\n io.o := CatByteWise(io.d, io.c, io.b, io.a)\n}\n\nclass test_slices extends Module {\n val io = IO(new Bundle {\n val x = Input(UInt(48.W))\n val a0 = Output(UInt(3.W))\n val b0 = Output(SInt(9.W))\n val c0 = Output(UInt(8.W))\n val d0 = Output(SInt(12.W))\n val a1 = Output(UInt(3.W))\n val b1 = Output(SInt(9.W))\n val c1 = Output(UInt(8.W))\n val d1 = Output(SInt(12.W))\n val a2 = Output(UInt(3.W))\n val b2 = Output(SInt(9.W))\n val c2 = Output(UInt(8.W))\n val d2 = Output(SInt(12.W))\n val a3 = Output(UInt(3.W))\n val b3 = Output(SInt(9.W))\n val c3 = Output(UInt(8.W))\n val d3 = Output(SInt(12.W))\n })\n io.x.sliceTo(io.d0, io.c0, io.b0, io.a0)\n io.x.sliceByteWiseTo(io.d1, io.c1, io.b1, io.a1)\n\n val sbits = io.x.slices(12, 8, 9, 3)\n io.d2 := sbits(0).asSInt\n io.c2 := sbits(1)\n io.b2 := sbits(2).asSInt\n io.a2 := sbits(3)\n\n val sbytes = io.x.slicesByteWise(12, 8, 9, 3)\n io.d3 := sbytes(0).asSInt\n io.c3 := sbytes(1)\n io.b3 := sbytes(2).asSInt\n io.a3 := sbytes(3)\n}\n\nclass test_fp extends Module {\n val io = IO(new Bundle {\n val a = Input(FixPoint(10.W, 8))\n val b = Input(FixPoint(16.W, 12))\n val c = Input(SInt(10.W))\n val i = Input(FixPoint(12.W, 11))\n val q = Input(FixPoint(8.W, 7))\n val add0 = Output(FixPoint(16.W, 12))\n val sub0 = Output(FixPoint(16.W, 12))\n val prod0 = Output(FixPoint(28.W, 16))\n val add1 = Output(FixPoint(12.W, 8))\n val sub1 = Output(FixPoint(12.W, 8))\n val prod1 = Output(FixPoint(15.W, 8))\n val add2 = Output(FixPoint(12.W, 8))\n val sub2 = Output(FixPoint(12.W, 8))\n val prod2 = Output(FixPoint(15.W, 8))\n val ca = Output(FixPoint(16.W, 12))\n val cb = Output(FixPoint(12.W, 8))\n val cc = Output(FixPoint(16.W, 6))\n val c0 = Output(FixPoint(16.W, 15))\n val c1 = Output(FixPoint(16.W, 8))\n val c2 = Output(FixPoint(16.W, 8))\n val c1zero = Output(FixPoint(16.W, 8))\n val c1negative = Output(FixPoint(17.W, 8))\n val c1int = Output(SInt(8.W))\n val c1frac = Output(FixPoint(9.W, 8))\n val c1floor = Output(FixPoint(8.W, 0))\n val c1ceil = Output(FixPoint(9.W, 0))\n val mag = Output(FixPoint(12.W, 11))\n val ff00 = Output(FixPoint(16.W, 3))\n val ff01 = Output(FixPoint(16.W, 3))\n val ff02 = Output(FixPoint(16.W, 3))\n val ff03 = Output(FixPoint(16.W, 3))\n val ff04 = Output(FixPoint(16.W, 3))\n val ff05 = Output(FixPoint(16.W, 3))\n val ff06 = Output(FixPoint(16.W, 3))\n val ff07 = Output(FixPoint(16.W, 3))\n val ff08 = Output(FixPoint(16.W, 3))\n })\n\n // println(s\"Q2.8 min: ${io.a.lowest}, max: ${io.a.highest}\")\n\n io.add0 := io.a + io.b\n io.sub0 := io.a - io.b\n io.prod0 := io.a * io.b\n io.add1 := (io.a + io.b).truncate(8)\n io.sub1 := (io.a - io.b).truncate(8)\n io.prod1 := (io.a * io.b).truncate(8)\n io.add2 := (io.a + io.b).round(8)\n io.sub2 := (io.a - io.b).round(8)\n io.prod2 := (io.a * io.b).round(8)\n io.ca := io.a\n io.cb := io.b\n io.cc := io.c\n io.c0 := 0.75\n io.c1 := -12.3\n io.c2 := 12.3.F(16.W, 8)\n // io.c1 := 128.0 // error\n io.c1zero := io.c1.zero\n io.c1negative := io.c1.negative\n io.c1int := io.c1.toSInt\n io.c1frac := io.c1.getPureFraction\n io.c1floor := io.c1.floor()\n io.c1ceil := io.c1.ceil()\n\n // val zzz = RegInit(new FixPoint(SInt(8.W), 7))\n\n val xxx = RegInit(FixPoint(0.S(8.W), 7))\n val sqi = RegInit(FixPoint(12.W, 11, 0.5))\n val sqq = RegInit(-0.5.F(8.W, 7))\n\n val mag = Reg(FixPoint(12.W, 11))\n\n val fp00 = Wire(FixPoint.byLowest(3, -3.3))\n fp00 := -3.3\n val fp01 = Wire(FixPoint.byHighest(3, 3.3))\n fp01 := 3.3\n val fp02 = Wire(FixPoint.byLowest(3, -2.0))\n fp02 := -2.0\n val fp03 = Wire(FixPoint.byHighest(3, 1.875))\n fp03 := 1.875\n val fp04 = Wire(FixPoint.byLowest(3, -2.0624))\n fp04 := -2.0624\n val fp05 = Wire(FixPoint.byLowest(3, -2.0625))\n fp05 := -2.0625\n val fp06 = Wire(FixPoint.byHighest(3, 1.9374))\n fp06 := 1.9374\n val fp07 = Wire(FixPoint.byHighest(3, 1.9375))\n fp07 := 1.9375\n val fp08 = Wire(FixPoint.byRange(3, -2.0624, 1.9374))\n fp08 := 0.1\n\n val halfs = (-4 until 4).map(_.toDouble + 0.5)\n val halfUps = halfs.map(_.halfUp)\n val halfDowns = halfs.map(_.halfDown)\n val halfEvens = halfs.map(_.halfEven)\n val halfCeils = halfs.map(_.halfCeil)\n val halfFloors = halfs.map(_.halfFloor)\n\n val bdHalfs = (-4 until 4).map(BigDecimal(_) + 0.5)\n val bdHalfCeils = bdHalfs.map(_.halfCeil)\n val bdHalfFloors = bdHalfs.map(_.halfFloor)\n\n io.ff00 := fp00\n io.ff01 := fp01\n io.ff02 := fp02\n io.ff03 := fp03\n io.ff04 := fp04\n io.ff05 := fp05\n io.ff06 := fp06\n io.ff07 := fp07\n io.ff08 := fp08\n\n sqi := (io.i * io.i).truncate(11)\n sqq := (io.q * io.q).truncate(7)\n mag := sqi + sqq\n io.mag := mag\n}", "groundtruth": " val b = IO( Input(Bool())).suggestName{\"bbb\"}\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.8, "category_reason": "Input or Output in Bundle/IO context"} {"task_id": "FPGA-Application-Development-and-Simulation", "path": "FPGA-Application-Development-and-Simulation/chisel/src/test/scala/loywongtest/axi4lite_test_common.scala", "left_context": "/*\n * MIT License\n *\n * Copyright (c) 2025 loykylewong (loywong@gmail.com)\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n */\n\npackage loywongtest\n\nimport chisel3._\nimport chisel3.util._\nimport chiseltest._\nimport chiseltest.internal.TesterThreadList\n\nimport loywong._\nimport loywong.util._\n\n/**\n * An AXI4-Lite Master for test-bench.\n * @param clk The clock associated with the AXI4-Lite IO\n * @param axi4l The AXI4-Lite Slave IO to be tested\n */\nclass Axi4LiteTestMaster(clk: Clock, axi4l: Axi4LiteIO) {\n\n // private val addrWidth = axi4l.ar.bits.addr.getWidth\n private val dataBytes = axi4l.r.bits.data.getWidth / 8\n private val dataMask = (BigInt(1) << (dataBytes * 8)) - 1\n private val strbMask = (BigInt(1) << dataBytes) - 1\n\n /**\n * Issue a write transaction\n *\n * @param addr Address of the write transaction\n * @param data Data to be written\n * @param strb Strb associated to the data\n * @return Slave response\n */\n def write(addr: BigInt, data: BigInt, strb: BigInt = strbMask): Int = {\n axi4l.aw.bits.addr.poke(addr)\n axi4l.aw.bits.prot.poke(0)\n axi4l.aw.valid.poke(true)\n axi4l.w.bits.data.poke(data & dataMask)\n axi4l.w.bits.strb.poke(strb & strbMask)\n axi4l.w.valid.poke(true)\n", "right_context": " clk.step() // aw handshake cycle\n axi4l.aw.valid.poke(false)\n }\n val wt = fork {\n while (!axi4l.w.ready.peekBoolean()) {\n clk.step()\n }\n clk.step() // w handshake cycle\n axi4l.w.valid.poke(false)\n }\n awt.join()\n wt.join()\n while (!axi4l.b.valid.peekBoolean()) {\n clk.step()\n }\n val resp = axi4l.b.bits.resp.peekInt()\n clk.step() // b handshake cycle\n resp.toInt\n }\n\n /**\n * Issue a read transaction\n *\n * @param addr Address of the read transaction\n * @return (data, resp)\n * - data: Data read\n * - resp: Slave response\n */\n def read(addr: BigInt): (BigInt, Int) = {\n axi4l.ar.bits.addr.poke(addr)\n axi4l.ar.bits.prot.poke(0)\n axi4l.ar.valid.poke(true)\n axi4l.r.ready.poke(true)\n while (!axi4l.ar.ready.peekBoolean()) {\n clk.step()\n }\n clk.step() // ar handshake cycle\n axi4l.ar.valid.poke(false)\n while (!axi4l.r.valid.peekBoolean()) {\n clk.step()\n }\n val data = axi4l.r.bits.data.peekInt()\n val resp = axi4l.r.bits.resp.peekInt().toInt\n clk.step() // r handshake cycle\n (data, resp)\n }\n}\n", "groundtruth": " axi4l.b.ready.poke(true)\n val awt = fork {\n while (!axi4l.aw.ready.peekBoolean()) {\n", "crossfile_context": "", "category": "Testbench Stimulus and Environment", "subcategory": "Stimulus Generation", "confidence": 0.85, "category_reason": "Chisel test harness (poke/peek/step)"} {"task_id": "FPGA-Application-Development-and-Simulation", "path": "FPGA-Application-Development-and-Simulation/chisel/src/test/scala/loywongtest/str_test_common.scala", "left_context": "/*\n * MIT License\n *\n * Copyright (c) 2025 loykylewong (loywong@gmail.com)\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n */\n\npackage loywongtest\n\nimport chisel3._\nimport chisel3.util._\nimport chiseltest._\nimport chiseltest.internal.TesterThreadList\n\nimport scala.util.Random\nimport scala.collection.Searching._\nimport scala.collection.mutable.ArrayBuffer\n// import scala.reflect.{ClassTag, classTag}\nimport org.apache.commons.math3.distribution.PoissonDistribution\nimport loywong._\nimport loywong.util._\n\n/**\n * A class collects stream signals\n * @param str the stream io (IrrevocableIO) to be monitored\n * @tparam T type of `str.bits`, must be inherited from StrBits\n */\nabstract class StrMonitorSignals[T <: StrBits](str: IrrevocableIO[T]) {\n private val gapsArray: ArrayBuffer[Int] = ArrayBuffer[Int]()\n private val clksArray: ArrayBuffer[Long] = ArrayBuffer[Long]()\n private var lastClkCnt: Long = 0\n /**\n * Append gap to gapsArray, calculate and append element to clksArray.\n * @param clkCnt clockStepCount after current beat\n */\n protected def appendGaps(clkCnt: Long): Unit = {\n gapsArray += {\n if(clksArray.isEmpty) clkCnt - lastClkCnt\n else clkCnt - clksArray.last\n }.toInt\n clksArray += clkCnt\n lastClkCnt = clkCnt\n }\n \n private val dataArray: ArrayBuffer[BigInt] = ArrayBuffer[BigInt]()\n private val strbArray: ArrayBuffer[BigInt] = ArrayBuffer[BigInt]()\n private val keepArray: ArrayBuffer[BigInt] = ArrayBuffer[BigInt]()\n private val lastArray: ArrayBuffer[Boolean] = ArrayBuffer[Boolean]()\n private val idArray: ArrayBuffer[Long] = ArrayBuffer[Long]()\n private val destArray: ArrayBuffer[Long] = ArrayBuffer[Long]()\n private val userArray: ArrayBuffer[BigInt] = ArrayBuffer[BigInt]()\n \n // non-removable bytes\n private val byteArray: ArrayBuffer[Byte] = ArrayBuffer[Byte]()\n // strb associated with each non-removable bytes\n private val bStrbArray: ArrayBuffer[Boolean] = ArrayBuffer[Boolean]()\n // id associated to each non-removable bytes\n private val bIdArray: ArrayBuffer[Long] = ArrayBuffer[Long]()\n // dest associated to each non-removable bytes\n private val bDestArray: ArrayBuffer[Long] = ArrayBuffer[Long]()\n // user associated with each non-removable bytes, if applicable\n private val bUserArray: ArrayBuffer[BigInt] = ArrayBuffer[BigInt]()\n \n private val nUserUnitBits = str.bits.userBitsPerDataByte\n private val userUnitMask = (BigInt(1) << nUserUnitBits) - 1\n \n protected def appendSignalsByPeek(): (\n Option[BigInt], // data\n Option[BigInt], // strb\n Option[BigInt], // keep\n Option[Boolean], // last\n Option[Long], // id\n Option[Long], // dest\n Option[BigInt] // user\n ) = {\n val data = str.bits.peekDataIfExist\n val strb = str.bits.peekStrbIfExist\n val keep = str.bits.peekKeepIfExist\n val last = str.bits.peekLastIfExist\n val id = str.bits.peekIdIfExist\n val dest = str.bits.peekDestIfExist\n val user = str.bits.peekUserIfExist\n appendSignalsManually(data, strb, keep, last, id, dest, user)\n (data, strb, keep, last, id, dest, user)\n }\n \n protected def appendSignalsManually(data: Option[BigInt],\n strb: Option[BigInt],\n keep: Option[BigInt],\n last: Option[Boolean],\n id : Option[Long],\n dest: Option[Long],\n user: Option[BigInt]): Unit = {\n data.foreach(d => dataArray += d)\n strb.foreach(s => strbArray += s)\n keep.foreach(k => keepArray += k)\n last.foreach(l => lastArray += l)\n id.foreach(i => idArray += i.toLong)\n dest.foreach(d => destArray += d.toLong)\n user.foreach(u => userArray += u)\n val s = strb.getOrElse(str.bits.strbMask)\n val k = keep.getOrElse(str.bits.keepMask)\n val d = data.getOrElse(BigInt(0))\n val i = id.getOrElse(0L)\n val t = dest.getOrElse(0L)\n val u = user.getOrElse(BigInt(0))\n for (b <- 0 until k.bitLength) {\n if (k.testBit(b)) {\n if (str.bits.hasData) {\n byteArray += ((d >> (8 * b)) & 0xFF).toByte\n if (str.bits.hasStrb) {\n bStrbArray += s.testBit(b)\n }\n }\n if (str.bits.hasId) {\n bIdArray += i\n }\n if (str.bits.hasDest) {\n bDestArray += t\n }\n if (str.bits.hasUser) {\n if (str.bits.asInstanceOf[StrHasUser].userAssociation == StrUserAssociation.SpreadInBytes)\n bUserArray += (u >> (nUserUnitBits * b)) & userUnitMask\n else\n bUserArray += u\n }\n }\n }\n }\n \n def gapsSeq: Seq[Int] = gapsArray.toSeq\n def clksSeq: Seq[Long] = clksArray.toSeq\n def dataSeq: Seq[BigInt] = dataArray.toSeq\n def strbSeq: Seq[BigInt] = strbArray.toSeq\n def keepSeq: Seq[BigInt] = keepArray.toSeq\n def lastSeq: Seq[Boolean] = lastArray.toSeq\n def idSeq: Seq[Long] = idArray.toSeq\n def destSeq: Seq[Long] = destArray.toSeq\n def userSeq: Seq[BigInt] = userArray.toSeq\n \n def byteSeq: Seq[Byte] = byteArray.toSeq\n def bStrbSeq: Seq[Boolean] = bStrbArray.toSeq\n def bIdSeq: Seq[Long] = bIdArray.toSeq\n def bDestSeq: Seq[Long] = bDestArray.toSeq\n def bUserSeq: Seq[BigInt] = bUserArray.toSeq\n \n def clearAllGapsAndSignals(): Unit = {\n gapsArray.clear()\n clksArray.clear()\n dataArray.clear()\n strbArray.clear()\n keepArray.clear()\n lastArray.clear()\n idArray.clear()\n destArray.clear()\n userArray.clear()\n byteArray.clear()\n bStrbArray.clear()\n bIdArray.clear()\n bDestArray.clear()\n bUserArray.clear()\n }\n \n private def checkSeqWithRef[T](ref: Seq[T], arr: ArrayBuffer[T]): Int = {\n var errCnt = math.abs(ref.length - arr.length)\n (0 until math.min(ref.length, arr.length)).foreach(i => {\n if(ref(i) != arr(i))\n errCnt = errCnt + 1\n })\n errCnt\n }\n \n def checkDataSeq(refData: Seq[BigInt]): Int = checkSeqWithRef(refData, dataArray)\n def checkStrbSeq(refStrb: Seq[BigInt]): Int = checkSeqWithRef(refStrb, strbArray)\n def checkKeepSeq(refKeep: Seq[BigInt]): Int = checkSeqWithRef(refKeep, keepArray)\n def checkIdSeq(refId: Seq[Long]): Int = checkSeqWithRef(refId, idArray)\n def checkDestSeq(refDest: Seq[Long]): Int = checkSeqWithRef(refDest, destArray)\n def checkUserSeq(refUser: Seq[BigInt]): Int = checkSeqWithRef(refUser, userArray)\n\n def checkByteSeq(refBytes: Seq[Byte]): Int = checkSeqWithRef(refBytes, byteArray)\n def checkBStrbSeq(refBStrbs: Seq[Boolean]): Int = checkSeqWithRef(refBStrbs, bStrbArray)\n def checkBIdSeq(refBIds: Seq[Long]): Int = checkSeqWithRef(refBIds, bIdArray)\n def checkBDestSeq(refBDests: Seq[Long]): Int = checkSeqWithRef(refBDests, bDestArray)\n def checkBUserSeq(refBUsers: Seq[BigInt]): Int = checkSeqWithRef(refBUsers, bUserArray)\n \n", "right_context": " \n private val dataHexWidth = str.bits.dataBytesCeil * 2\n private val dataFormat = s\"d:%0${dataHexWidth}X\"\n // private val strbHexWidth = math.ceil(str.bits.strStrbWidth / 4.0).toInt\n // private val strbFormat = s\" s:%0${strbHexWidth}X\"\n // private val keepHexWidth = math.ceil(str.bits.strKeepWidth / 4.0).toInt\n // private val keepFormat = s\" k:%0${keepHexWidth}X\"\n private val idHexWidth = math.ceil(str.bits.idWidth / 4.0).toInt\n private val idFormat = s\" \\u001b[38;2;128;128;128mi:\\u001b[0m%0${idHexWidth}X\"\n private val destHexWidth = math.ceil(str.bits.destWidth / 4.0).toInt\n private val destFormat = s\" \\u001b[38;2;128;128;128md:\\u001b[0m%0${destHexWidth}X\"\n private val userHexWidth = math.ceil(str.bits.userWidth / 4.0).toInt\n private val userFormat = s\" \\u001b[38;2;128;128;128mu:\\u001b[0m%0${userHexWidth}X\"\n private val emptyStringLen = /*2 +*/ dataHexWidth +\n // { if(str.bits.hasStrb) 3 + strbHexWidth else 0 } +\n // { if(str.bits.hasKeep) 3 + keepHexWidth else 0 } +\n // { if(str.bits.hasLast) 2 else 0 } +\n { if(str.bits.hasId) 3 + idHexWidth else 0 } +\n { if(str.bits.hasDest) 3 + destHexWidth else 0 } +\n { if(str.bits.hasUser) 3 + userHexWidth else 0 }\n private val emptyFormat = s\"%${emptyStringLen}s\"\n \n private def appendDataString(sigStr: StringBuilder, data: BigInt, strb: BigInt, keep: BigInt, last: Boolean): Unit = {\n if(last) {\n sigStr.append(\"\\u001b[7m\")\n }\n for(i <- str.bits.dataBytesCeil - 1 to 0 by -1) {\n if(!keep.testBit(i)) {\n // gray\n sigStr.append(\"\\u001b[38;2;128;128;128m%02X\\u001b[0m\".format((data >> (i * 8)) & 0xFF))\n }\n else if(!strb.testBit(i)) {\n // normal\n sigStr.append(\"%02X\\u001b[0m\".format((data >> (i * 8)) & 0xFF))\n }\n else {\n // bold\n sigStr.append(\"\\u001b[1m%02X\\u001b[0m\".format((data >> (i * 8)) & 0xFF))\n }\n }\n }\n\n /**\n * convert signals in the `nClock`-th clock cycle to human-readable string,\n * in which:\n *\n * - data is printed in hex, byte:\n *\n * is gray if associated keep is low;\n *\n * is normal if associated keep is high and strb is low;\n *\n * is bold if associated keep and strb are both high.\n *\n * - id, dest and user are printed in hex with prefix `i:`, `d:` and `u:`.\n *\n * @param nClock signals in which cycle to be converted\n * @return human-readable string\n */\n def signalStringOfClock(nClock: Long): String = {\n val sigStr = new StringBuilder()\n clksArray.search(nClock) match {\n case Found(i) => {\n val strb = if(str.bits.hasStrb) strbArray(i) else str.bits.strbMask\n val keep = if(str.bits.hasKeep) keepArray(i) else str.bits.keepMask\n val last = if(str.bits.hasLast) lastArray(i) else false\n appendDataString(sigStr, dataArray(i), strb, keep, last)\n sigStr.append(\n if (str.bits.hasId) {\n idFormat.format(idArray(i))\n } else \"\"\n )\n sigStr.append(\n if (str.bits.hasDest) {\n destFormat.format(destArray(i))\n } else \"\"\n )\n sigStr.append(\n if (str.bits.hasUser) {\n userFormat.format(userArray(i))\n } else \"\"\n )\n sigStr.toString()\n }\n case _ => {\n emptyFormat.format(\"\")\n }\n }\n }\n}\n\n/**\n * A stream source for test-bench.\n * @param clk Clock associated with stream IO (IrrevocableIO)\n * @param ds Down-stream IO to be tested\n * @tparam T Type of bits in IrrevocableIO\n */\nclass StrTestSource[T <: StrHasData](clk: Clock, ds: IrrevocableIO[T])\nextends StrMonitorSignals[T](ds) {\n \n ds.valid.poke(false)\n\n private val bytesPerBeat = ds.bits.dataBytesCeil\n private val strbMask = (BigInt(1) << bytesPerBeat) - 1\n private val keepMask = (BigInt(1) << bytesPerBeat) - 1\n private val userUnitWidth = ds.bits.userBitsPerDataByte\n private val userUnitMask = (BigInt(1) << userUnitWidth) - 1\n\n private var poisson = new PoissonDistribution(1.0)\n private var fixedInterval = 0\n private var isRandomInterval = false\n\n def setThrottle(isRandomThrottle: Boolean, throttleRatio: Double): Unit = {\n poisson = new PoissonDistribution(if (throttleRatio <= 0.0) Double.MinPositiveValue else throttleRatio)\n fixedInterval = math.round(throttleRatio).toInt\n isRandomInterval = isRandomThrottle\n }\n\n private var genRandomKeep = false\n private var randomKeepDensity = 0.5\n \n /**\n * Enable random keep generation in `sendBeatsByBytes`\n * @param desireDensity desire keep bit density (duty of non-removable\n * bytes)\n * - if `strbSeq`, `keepSeq`, `idSeq` and `destSeq`\n * are empty in `sendBeatsByBytes`, `desireDensity`\n * take effects;\n * - otherwise, actual density will be overridden by\n * `byteSeq.length / (totalBeats * nBytesOfData)`, in\n * which totalBeats = length of `strbSeq`, `keepSeq`,\n * `idSeq` or `destSeq`\n * @note if random keep generation enabled and `keepSeq` is not empty in\n * `sendBeatsByBytes`, elements in `keepSeq` will be overridden by\n * generated random keep.\n * @note OBSOLETE, use:\n * 1. randomBytes(), randomBStrbs(), randomBUsers() and.\n * 1. convertBytesToBeats() and,\n * 1. sendBeats() instead.\n */\n def enableRandomKeep(desireDensity: Double = 0.5): Unit = {\n require(1.0/256.0 <= desireDensity && desireDensity <= 255.0/256.0)\n require(ds.bits.hasKeep)\n genRandomKeep = true\n randomKeepDensity = desireDensity\n }\n \n /**\n * Disable random keep generation in `sendBeatsByBytes`\n * @note if random keep generation disabled and `keepSeq` is empty in\n * `sendBeatsByBytes`, `keep` in all beats will be all ones.\n * @note OBSOLETE, use:\n * 1. randomBytes(), randomBStrbs(), randomBUsers() and.\n * 1. convertBytesToBeats() and,\n * 1. sendBeats() instead.\n */\n def disableRandomKeep(): Unit = {\n genRandomKeep = false\n }\n\n /**\n * Wait a number of clock cycles specified by arg `isRandomThrottle` and\n * arg `throttleRatio` in method `setThrottle`.\n * @return Actual cycles of clock waited\n */\n private def waitGap(): Int = {\n val interval =\n if (isRandomInterval) poisson.sample()\n else fixedInterval\n if (interval > 0) {\n clk.step(interval)\n }\n interval\n }\n\n /**\n * Send a transaction beat.\n *\n * @param data Data to be sent\n * @param last Whether send a high on last signal if the bits in\n * IrrevocableIO contains last signal (inherit StrWithLast)\n * @param keep Keep signal to be sent, default all ones, if the bits in\n * IrrevocableIO contains keep signal (inherit StrWithKeep)\n * @return Clock cycles spent on waiting ready signal\n */\n private def sendBeat(data: BigInt,\n strb: BigInt = strbMask,\n keep: BigInt = keepMask,\n last: Boolean = false,\n id : Long = 0L,\n dest: Long = 0L,\n user: BigInt = BigInt(0)\n ): Int = {\n \n val d = ds.bits.pokeDataIfExist(data)\n val l = ds.bits.pokeLastIfExist(last)\n val s = ds.bits.pokeStrbIfExist(strb)\n val k = ds.bits.pokeKeepIfExist(keep)\n val i = ds.bits.pokeIdIfExist(id)\n val t = ds.bits.pokeDestIfExist(dest)\n val u = ds.bits.pokeUserIfExist(user)\n \n appendSignalsManually(d, s, k, l, i, t, u)\n \n ds.valid.poke(true)\n var gap = 0\n while (!ds.ready.peekBoolean()) {\n clk.step(1)\n gap = gap + 1\n }\n clk.step(1)\n ds.valid.poke(false)\n \n appendGaps(clk.getStepCount)\n \n gap\n }\n \n private def prepareDataByKeep(bytes: Seq[Byte], currIdx: Int, keep: BigInt): (BigInt, Int) = {\n var idx = currIdx\n var data: BigInt = 0\n for (b <- 0 until bytesPerBeat) {\n if(keep.testBit(b)) {\n data = data | (BigInt(bytes(idx) & 0xFF) << (b * 8))\n idx = idx + 1\n }\n }\n (data, idx)\n }\n \n private def prepareUserByKeep(users: Seq[BigInt], currIdx: Int, keep: BigInt): (BigInt, Int) = {\n var idx = currIdx\n var user: BigInt = 0\n for (b <- 0 until bytesPerBeat) {\n if(keep.testBit(b)) {\n user = user | (users(idx) << (b * userUnitWidth))\n idx = idx + 1\n }\n }\n (user, idx)\n }\n \n private def randBigInt(nBits: Int): BigInt = {\n val r = (0 until nBits by 32).foldLeft(BigInt(0))(\n (acc, i) => acc | (BigInt(Random.nextInt() & 0xFFFFFFFFL) << i)\n )\n r & ((BigInt(1) << nBits) - 1)\n }\n def randomBytes(nBytes: Int): Seq[Byte] = {\n Random.nextBytes(nBytes).toSeq\n }\n def randomBStrbs(nBytes: Int, density: Double = 1.0): Seq[Boolean] = {\n val thr = math.round(nBytes * density).toInt\n Random.shuffle((0 until nBytes).toList).map(i => i < thr)\n }\n def randomBUsers(nBytes: Int, unitWidth: Int = userUnitWidth): Seq[BigInt] = {\n require(unitWidth > 0)\n Seq.fill(nBytes)(randBigInt(unitWidth))\n }\n def randomData(nBeats: Int): Seq[BigInt] = {\n Seq.fill(nBeats)(randBigInt(ds.bits.dataWidth))\n }\n def randomStrbs(nBeats: Int, bytesPerBeat: Int = bytesPerBeat, density: Double = 1.0): Seq[BigInt] = {\n require(bytesPerBeat > 0)\n val nBytes = nBeats * bytesPerBeat\n val strbMask = (BigInt(1) << bytesPerBeat) - 1\n val strb = Array.fill(nBeats)(strbMask)\n randomBStrbs(nBytes, density).zipWithIndex.foreach { case(b, i) =>\n val beatIdx = i / bytesPerBeat\n val bitPos = i % bytesPerBeat\n if(!b)\n strb(beatIdx) = strb(beatIdx) & ~(BigInt(1) << bitPos)\n }\n strb.toSeq\n }\n def randomIds(nBeats: Int, width: Int = ds.bits.idWidth, immutablePeriod: Int = 1): Seq[Long] = {\n require(width > 0)\n require(immutablePeriod > 0)\n require(nBeats % immutablePeriod == 0)\n var lastRand = 0L\n Seq.tabulate(nBeats)( i => {\n if (i % immutablePeriod == 0) {\n lastRand = Random.nextLong() & ((1L << width) - 1)\n lastRand\n }\n else lastRand\n })\n }\n def randomDests(nBeats: Int, width: Int = ds.bits.destWidth, immutablePeriod: Int = 1): Seq[Long] = {\n require(width > 0)\n require(immutablePeriod > 0)\n require(nBeats % immutablePeriod == 0)\n var lastRand = 0L\n Seq.tabulate(nBeats)( i => {\n if (i % immutablePeriod == 0) {\n lastRand = Random.nextLong() & ((1L << width) - 1)\n lastRand\n }\n else lastRand\n })\n }\n def randomUsers(nBeats: Int, width: Int = ds.bits.userWidth, immutablePeriod: Int = 1): Seq[BigInt] = {\n require(width > 0)\n require(immutablePeriod > 0)\n require(nBeats % immutablePeriod == 0)\n var lastRand = BigInt(0)\n Seq.tabulate(nBeats)(i => {\n if (i % immutablePeriod == 0) {\n lastRand = randBigInt(width)\n lastRand\n }\n else lastRand\n })\n }\n \n /**\n * Convert non-removable bytes, associated strb and user to beats.\n * @param nBeats Number of desired beats, if `bytes.length < nDataBytes\n * * nBeats`, random keep will be generated, otherwise,\n * keep will be all ones.\n * @param bytes Non-removable bytes\n * @param strb Strb(s) associated with each byte in `bytes`\n * @param user User(s) associated with each byte in `bytes`\n * @return\n */\n def convertBytesToBeats(nBeats: Int,\n bytes: Seq[Byte],\n strb: Seq[Boolean] = Seq.empty[Boolean],\n user: Seq[BigInt] = Seq.empty[BigInt]\n ): (Seq[BigInt], Seq[BigInt], Seq[BigInt], Seq[BigInt]) = {\n \n require(bytes.nonEmpty)\n require(strb.isEmpty || strb.length == bytes.length)\n require(user.isEmpty || user.length == bytes.length)\n \n val minBeats = (bytes.length - 1) / bytesPerBeat + 1\n val totalBeats = math.max(nBeats, minBeats)\n val totalRawBytes = totalBeats * bytesPerBeat\n val totalKeepBytes = bytes.length\n \n val dataArray = Array.fill(totalBeats)(BigInt(0))\n val strbArray = Array.fill(totalBeats)(strbMask)\n val keepArray = Array.fill(totalBeats)(keepMask)\n val userArray = Array.fill(totalBeats)(BigInt(0))\n \n val kbits = Random.shuffle((0 until totalRawBytes).toList).map(i => i < totalKeepBytes)\n kbits.zipWithIndex.foreach {\n case (k, i) => if(!k) {\n val beatIdx = i / bytesPerBeat\n val byteIdx = i % bytesPerBeat\n keepArray(beatIdx) = keepArray(beatIdx) & ~(BigInt(1) << byteIdx)\n }\n }\n // val nrbytes = keepArray.foldLeft(0)((acc, k) => acc + k.popCount)\n // require(nrbytes == totalKeepBytes)\n \n var byteIdx = 0\n keepArray.zipWithIndex.foreach { case(keep, beatIdx) =>\n for (i <- 0 until bytesPerBeat) {\n if (keep.testBit(i)) {\n dataArray(beatIdx) = dataArray(beatIdx) | (BigInt(bytes(byteIdx) & 0xFF) << (i * 8))\n if(strb.nonEmpty && !strb(byteIdx))\n strbArray(beatIdx) &= ~(BigInt(1) << i)\n if(user.nonEmpty)\n userArray(beatIdx) = userArray(beatIdx) | ((user(byteIdx) & userUnitMask) << (i * userUnitWidth))\n byteIdx += 1\n }\n }\n }\n // require(byteIdx == bytes.length)\n (dataArray.toSeq, strbArray.toSeq, keepArray.toSeq, userArray.toSeq)\n }\n\n /**\n * Send beats by given signals of each beat.\n *\n * @param genLastAtLastBeat Whether generating last at the last beat,\n * this requires io.bits has last.\n * @param dataSeq Contains data to be sent in each beat.\n * @param strbSeq Contains strb to be sent in each beat,\n * default empty and all ones will be sent.\n * @param keepSeq Contains keep to be sent in each beat,\n * default empty and all ones will be sent.\n * @param idSeq Contains id to be sent in each beat,\n * default empty and all zeros will be sent.\n * @param destSeq Contains dest to be sent in each beat,\n * default empty and all zeros will be sent.\n * @param userSeq Contains user to be sent in each beat\n * default empty and all zeros will be sent.\n * @note\n * 1. When ds.bits contains no strb, keep, id, dest or user,\n * corresponding Seq(s) will be ignored.\n * 1. If a Seq is not empty, its length must be equal to dataSeq.\n * 1. Total number of beats is equal to length of dataSeq.\n * 1. If random data needed, use:\n * I. randomData(), randomStrbs(), randomIds(), randomDests()\n * and/or randomUsers(), if keep is not needed;\n * I. randomBytes(), randomBStrbs() and/or randomBUsers() with\n * convertBytesToBeats(), if keep is needed.\n */\n def sendBeats(genLastAtLastBeat: Boolean,\n dataSeq: Seq[BigInt] = Seq.empty[BigInt],\n strbSeq: Seq[BigInt] = Seq.empty[BigInt],\n keepSeq: Seq[BigInt] = Seq.empty[BigInt],\n idSeq: Seq[Long] = Seq.empty[Long],\n destSeq: Seq[Long] = Seq.empty[Long],\n userSeq: Seq[BigInt] = Seq.empty[BigInt]): TesterThreadList = {\n\n if (genLastAtLastBeat) require(ds.bits.hasLast)\n require(strbSeq.isEmpty || strbSeq.length == dataSeq.length)\n require(keepSeq.isEmpty || keepSeq.length == dataSeq.length)\n require(idSeq.isEmpty || idSeq.length == dataSeq.length)\n require(destSeq.isEmpty || destSeq.length == dataSeq.length)\n require(userSeq.isEmpty || userSeq.length == dataSeq.length)\n\n clearAllGapsAndSignals()\n\n val thread = fork {\n dataSeq.zipWithIndex.foreach {\n case (d, i) => {\n val last = (i == dataSeq.length - 1) && genLastAtLastBeat\n val strb = if (strbSeq.isEmpty) strbMask else strbSeq(i)\n val keep = if (keepSeq.isEmpty) keepMask else keepSeq(i)\n val id = if (idSeq.isEmpty) 0L else idSeq(i)\n val dest = if (destSeq.isEmpty) 0L else destSeq(i)\n val user = if (userSeq.isEmpty) BigInt(0) else userSeq(i)\n waitGap()\n sendBeat(d, strb, keep, last, id, dest, user)\n }\n }\n }\n thread\n }\n\n /**\n * Send beats by given non-removable bytes.\n *\n * @param genLastAtLastBeat Whether generating last at the last beat,\n * this requires io.bits has last\n * @param byteSeq Contains valid data bytes to be sent\n * @param strbSeq Contains strb to be sent in each beat,\n * default empty, all ones will be sent\n * @param keepSeq Contains keep to be sent in each beat,\n * default empty, all ones will be sent\n * @param idSeq Contains id to be sent in each beat,\n * default empty, all zeros will be sent\n * @param destSeq Contains dest to be sent in each beat,\n * default empty, all zeros will be sent\n * @param userSeq Contains user to be sent associated with data\n * bytes, length must be equal to length of\n * byteSeq, default empty, all zeros will be sent\n * @note\n * - When ds.bits contains no strb, keep, id, dest or user, Seq(s)\n * will be ignored.\n * - {{{\n * total_num_of_beats =\n * if (strbSeq.nonEmpty) strbSeq.length\n * else if (keepSeq.nonEmpty) keepSeq.length\n * else if (idSeq.nonEmpty) idSeq.length\n * else if (destSeq.nonEmpty) destSeq.length\n * else if(!genRandomKeep)\n * byteSeq.length / bytesPerBeat\n * else\n * ceil( byteSeq.length\n * / randomKeepDensity\n * / bytesPerBeat)\n * }}}\n * - When keepSeq is not empty, total count of high bit in keepSeq\n * must be equal to length of dataSeq\n * - When random keep enabled, elements in keepSeq is ignored\n *\n * @note OBSOLETE, since it's too difficult to use, use:\n * 1. convertBytesToBeats() and,\n * 1. sendBeats() instead.\n *\n * if random data needed, user randomBytes(), randomBStrbs() and/or\n * randomBUsers() first.\n */\n def sendBeatsByBytes(genLastAtLastBeat: Boolean,\n byteSeq: Seq[Byte] = Seq.empty[Byte],\n strbSeq: Seq[BigInt] = Seq.empty[BigInt],\n keepSeq: Seq[BigInt] = Seq.empty[BigInt],\n idSeq: Seq[Long] = Seq.empty[Long],\n destSeq: Seq[Long] = Seq.empty[Long],\n userSeq: Seq[BigInt] = Seq.empty[BigInt]): TesterThreadList = {\n\n require(ds.bits.userWidth % bytesPerBeat == 0)\n\n if (genLastAtLastBeat) require(ds.bits.hasLast)\n val (totalBeats, totalRawBytes) = {\n if (strbSeq.nonEmpty)\n (strbSeq.length, strbSeq.length * bytesPerBeat)\n else if (keepSeq.nonEmpty)\n (keepSeq.length, keepSeq.length * bytesPerBeat)\n else if (idSeq.nonEmpty)\n (idSeq.length, idSeq.length * bytesPerBeat)\n else if (destSeq.nonEmpty)\n (destSeq.length, destSeq.length * bytesPerBeat)\n else if(!genRandomKeep) {\n val beats = (byteSeq.length - 1) / bytesPerBeat + 1\n val rawBytes = beats * bytesPerBeat\n (beats, rawBytes)\n }\n else {\n val beats = math.ceil(byteSeq.length / randomKeepDensity / bytesPerBeat).toInt\n val rawBytes = beats * bytesPerBeat\n (beats, rawBytes)\n }\n }\n val totalKeepBytes = {\n if (genRandomKeep)\n byteSeq.length\n else if (keepSeq.nonEmpty)\n keepSeq.foldLeft(0)((acc, k) => acc + k.popCount)\n else\n totalRawBytes\n }\n\n require(totalKeepBytes <= totalRawBytes)\n require(byteSeq.length == totalKeepBytes)\n require(strbSeq.isEmpty || strbSeq.length == totalBeats)\n require(keepSeq.isEmpty || keepSeq.length == totalBeats)\n require(idSeq.isEmpty || idSeq.length == totalBeats)\n require(destSeq.isEmpty || destSeq.length == totalBeats)\n require(userSeq.isEmpty || userSeq.length == totalKeepBytes)\n\n clearAllGapsAndSignals()\n\n val actKeepSeq =\n if(!genRandomKeep) keepSeq\n else {\n val ks: Array[BigInt] = Array.fill[BigInt](totalBeats)(BigInt(0))\n val ki = scala.util.Random.shuffle((0 until totalRawBytes).toList).take(totalKeepBytes)\n ki.foreach {\n i => {\n ks(i / bytesPerBeat) = ks(i / bytesPerBeat).setBit(i % bytesPerBeat)\n }\n }\n ks.toSeq\n }\n\n val thread = fork {\n var byteIdx = 0\n var userIdx = 0\n (0 until totalBeats).foreach {\n i => {\n val last = (i == totalBeats - 1) && genLastAtLastBeat\n val strb = if (strbSeq.isEmpty) strbMask else strbSeq(i)\n val keep = if (actKeepSeq.isEmpty) keepMask else actKeepSeq(i)\n val id = if (idSeq.isEmpty) 0L else idSeq(i)\n val dest = if (destSeq.isEmpty) 0L else destSeq(i)\n val (data, bIdx) = prepareDataByKeep(byteSeq, byteIdx, keep)\n val (user, uIdx) = {\n if (userSeq.isEmpty) (BigInt(0), 0)\n else prepareUserByKeep(userSeq, userIdx, keep)\n }\n waitGap()\n sendBeat(data, strb, keep, last, id, dest, user)\n \n byteIdx = bIdx\n userIdx = uIdx\n }\n }\n }\n thread\n }\n}\n\n/**\n * A stream sink for test-bench.\n * @param clk Clock associated with stream IO (IrrevocableIO)\n * @param us Up-stream IO to be tested\n * @tparam T Type of bits in IrrevocableIO\n */\nclass StrTestSink[T <: StrHasData](clk: Clock, us: IrrevocableIO[T])\nextends StrMonitorSignals[T](us) {\n\n require(us.bits.data.getWidth % 8 == 0)\n \n us.ready.poke(false)\n\n private var poisson = new PoissonDistribution(1.0)\n private var fixedInterval = 0\n private var isRandomInterval = false\n\n def setThrottle(isRandomThrottle: Boolean, throttleRatio: Double): Unit = {\n poisson = new PoissonDistribution(if (throttleRatio <= 0.0) Double.MinPositiveValue else throttleRatio)\n fixedInterval = math.round(throttleRatio).toInt\n isRandomInterval = isRandomThrottle\n }\n\n // private var dealKeep = true\n\n /**\n * Wait a number of clock cycles specified by arg `isRandomThrottle` and\n * arg `throttleRatio` in method `setThrottle`\n *\n * @return Actual cycles of clock waited\n */\n private def waitGap(): Int = {\n val interval =\n if (isRandomInterval) poisson.sample()\n else fixedInterval\n if (interval > 0) {\n clk.step(interval)\n }\n interval\n }\n\n /**\n * Receive a transaction beat.\n *\n * @return (last, gap):\n * - last: if it's the last beat\n * - gap: Clock cycles spent on waiting valid signal\n */\n private def recvBeat(): (Boolean, Int) = {\n us.ready.poke(true)\n \n var gap = 0\n while (!us.valid.peekBoolean()) {\n clk.step(1)\n gap = gap + 1\n }\n \n val (_, _, _, last, _, _, _) = appendSignalsByPeek()\n\n clk.step(1)\n us.ready.poke(false)\n \n appendGaps(clk.getStepCount)\n \n (last.getOrElse(false), gap)\n }\n\n /**\n * Receive a package by specified beats\n *\n * @param rxBeats Number of beats to be received.\n * @return The TestThread forked, user should use its `join()` method to\n * wait the received operation finish before using any result\n */\n def recvBeats(rxBeats: Int): TesterThreadList = {\n \n clearAllGapsAndSignals()\n\n val thread = fork {\n for (i <- 0 until rxBeats) {\n waitGap()\n recvBeat()\n }\n }\n thread\n }\n\n /**\n * Receive a package to its end specified by the last signal in stream IO\n *\n * @return The TestThread forked, user should use its `join()` method to\n * wait the received operation finish before using any result\n * @note The type of bits in IrrevocableIO must be inherited from trait\n * `StrWithLast`\n */\n def recvBeatsToLast(): TesterThreadList = {\n\n require(us.bits.isInstanceOf[StrHasLast], s\"In StrTestSink.recvPkgToLast(), type of bits ${us.bits.typeName} does NOT has last signal, you may prefer to use StrTestSink.recvPkgByNumBeats().\")\n\n clearAllGapsAndSignals()\n\n val thread = fork {\n var last = false\n while (!last) {\n waitGap()\n val (lastBeat, _) = recvBeat()\n last = lastBeat\n }\n }\n thread\n }\n}\n", "groundtruth": " def totalClocks: Long = clksArray.last + 1\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "FPGA-Application-Development-and-Simulation", "path": "FPGA-Application-Development-and-Simulation/chisel/src/test/scala/test_accumulator.scala", "left_context": "/*\n * MIT License\n *\n * Copyright (c) 2025 loykylewong (loywong@gmail.com)\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n */\n\nimport chisel3._\nimport chisel3.util._\nimport chiseltest._\nimport org.scalatest.flatspec.AnyFlatSpec\nimport org.scalatest.matchers.should.Matchers._\nimport loywong._\n\nclass test_accumulator extends AnyFlatSpec with ChiselScalatestTester {\n println()\n println(\"====================\")\n println(\"Test Accumulator...\")\n println(\"--------------------\")\n\n \"DUT\" should \"pass\" in {\n val modu = 100\n test(new Accumulator(modu)).withAnnotations(Seq(WriteVcdAnnotation)) {\n dut => {\n dut.clock.step()\n dut.reset.poke(true.B)\n dut.clock.step()\n dut.reset.poke(false.B)\n \n var x = 0\n // ---- step 15 x 20 ----\n var step = 15\n dut.io.step.poke(step.S)\n dut.io.en.poke(true)\n for(i <- 0 until 20) {\n dut.clock.step()\n x += step\n val y = math.floorMod(x, modu)\n", "right_context": " dut.clock.step(20)\n dut.io.accu.expect(math.floorMod(x, modu).U)\n // ---- step -20 x 20 ----\n step = -20\n dut.io.step.poke(step.S)\n dut.io.en.poke(true)\n for(i <- 0 until 20) {\n dut.clock.step()\n x += step\n val y = math.floorMod(x, modu)\n if(y + step < 0)\n dut.io.wrapDown.expect(true)\n else\n dut.io.wrapDown.expect(false)\n dut.io.wrapUp.expect(false)\n dut.io.accu.expect(y.U)\n }\n println(\"-----------------------------\")\n println(s\"\\u001b[1mAccumulator test Pass.\\u001b[0m\")\n println(\"=============================\")\n Thread.sleep(1000)\n }\n }\n }\n}", "groundtruth": " if(y + step >= modu)\n dut.io.wrapUp.expect(true)\n else\n dut.io.wrapUp.expect(false)\n dut.io.wrapDown.expect(false)\n", "crossfile_context": "", "category": "Monitoring and Checking Logic", "subcategory": "Error Reporting and Logging", "confidence": 0.85, "category_reason": "Chisel expect (golden check)"} {"task_id": "FPGA-Application-Development-and-Simulation", "path": "FPGA-Application-Development-and-Simulation/chisel/src/test/scala/test_str_cordic_1.scala", "left_context": "/*\n * MIT License\n *\n * Copyright (c) 2025 loykylewong (loywong@gmail.com)\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n */\n\npackage test_str_cordic_1\n\nimport chisel3._\nimport chisel3.util._\nimport chiseltest._\nimport org.scalatest.flatspec.AnyFlatSpec\nimport org.scalatest.matchers.should.Matchers._\nimport loywong._\nimport loywong.util._\nimport loywongtest._\nimport org.apache.commons.math3.distribution.{UniformRealDistribution, UniformIntegerDistribution}\n\nobject SimSettings {\n val nBeats = 500\n val verbose: Boolean = nBeats <= 1000\n\n val randomValid = true\n val validInterval = 1.0 // if random, it's the poisson lambda\n val randomReady = true\n val readyInterval = 1.0 // if random, it's the poisson lambda\n\n val xyWidth = 12\n val zWidth = 12\n\n val userWidth = 8\n}\n\nimport SimSettings._\n\nclass CordicIOBitsWithUser extends CordicIOStrBits(xyWidth, zWidth) with StrHasLast with StrHasUser {\n override val last = Bool()\n override val user = UInt(userWidth.W)\n}\n\nclass CordicWrapperIOBits extends StrHasData with StrHasLast with StrHasUser {\n override val data = UInt((xyWidth.up8 * 2 + zWidth.up8).W)\n override val last = Bool()\n override val user = UInt(userWidth.up8.W)\n}\n\nclass CordicWrapper(xyFW: Int, zFW: Int, coor: CordicCoordinates.Value, mode: CordicMode.Value, linStgStart: Int = 0) extends Module {\n val io = IO(new Bundle {\n val us = Flipped(Irrevocable(new CordicWrapperIOBits))\n val ds = Irrevocable(new CordicWrapperIOBits)\n })\n\n val dut = Module(new Cordic(new CordicIOBitsWithUser, zWidth - 1, xyFW, zFW, coor, mode, linStgStart))\n\n io.us.bits.data.sliceByteWiseTo(dut.io.us.bits.z, dut.io.us.bits.y, dut.io.us.bits.x)\n io.us.bits.last <> dut.io.us.bits.last\n io.us.bits.user.sliceByteWiseTo(dut.io.us.bits.user)\n io.us.valid <> dut.io.us.valid\n io.us.ready <> dut.io.us.ready\n\n /**\n * birs for eliminate ready comb which may cause\n * \"Unordered poke after peek\" runtime error.\n */\n val brs = Module(new StrBirs(new CordicWrapperIOBits))\n\n brs.io.us.bits.data.catByteWiseFrom(dut.io.ds.bits.z, dut.io.ds.bits.y, dut.io.ds.bits.x)\n brs.io.us.bits.last <> dut.io.ds.bits.last\n brs.io.us.bits.user.catByteWiseFrom(dut.io.ds.bits.user)\n brs.io.us.valid <> dut.io.ds.valid\n brs.io.us.ready <> dut.io.ds.ready\n\n io.ds <> brs.io.ds\n}\n\nclass test extends AnyFlatSpec with ChiselScalatestTester {\n\n val shouldUseVerilator =\n if (System.getProperty(\"os.name\").toLowerCase.contains(\"win\"))\n Seq.empty[firrtl2.annotations.Annotation]\n else\n Seq(VerilatorBackendAnnotation)\n\n \"DUT Cordic Linear Rotation\" should \"Pass\" in {\n /**\n * Functions for this test:\n * - x := x\n * - y := y + x * z\n * - z := 0\n *\n * Domains of this test:\n * - x_i: (-1, 1)\n * - y_i: (-2, 2)\n * - z_i: (-2, 2)\n * - x_o: (-1, 1)\n * - y_o: (-4, 4)\n * - z_o: = 0\n */\n val xyFracWidth = xyWidth - 3\n val zFracWidth = zWidth - 2\n val xyLsb = math.pow(2.0, -xyFracWidth)\n val zLsb = math.pow(2.0, -zFracWidth)\n\n test(\n new CordicWrapper(xyFracWidth, zFracWidth, CordicCoordinates.Linear, CordicMode.Rotation)\n ).withAnnotations(\n shouldUseVerilator/* ++ Seq(WriteVcdAnnotation)*/\n ) {\n dut => {\n\n println(\n s\"\"\"\n |========================================================\n | Test CORDIC Linear Rotation with ${nBeats} data ...\"\"\".stripMargin)\n \n val src = new StrTestSource(dut.clock, dut.io.us)\n src.setThrottle(randomValid, validInterval)\n\n val snk = new StrTestSink(dut.clock, dut.io.ds)\n snk.setThrottle(randomReady, readyInterval)\n\n val xRand = new UniformRealDistribution(\n -1.0 + 16 * xyLsb, 1.0 - 16 * xyLsb\n )\n\n val yRand = new UniformRealDistribution(\n -2.0 + 16 * xyLsb, 2.0 - 16 * xyLsb\n )\n\n val zRand = new UniformRealDistribution(\n -2.0 + 16 * zLsb, 2.0 - 16 * zLsb\n )\n\n val xinSeq = Seq.fill(nBeats)(xRand.sample())\n val yinSeq = Seq.fill(nBeats)(yRand.sample())\n val zinSeq = Seq.fill(nBeats)(zRand.sample())\n\n val xoutRefSeq = xinSeq\n val youtRefSeq = (0 until nBeats).map(i => {\n yinSeq(i) + xinSeq(i) * zinSeq(i)\n })\n val zoutRefSeq = Seq.fill(nBeats)(0.0)\n \n val txDataSeq = (0 until nBeats).map(i => {\n CatByteWise(Seq.fill(3)(true), Seq(zWidth, xyWidth, xyWidth),\n zinSeq(i).toFixPoint(zWidth, zFracWidth).toBigInt,\n yinSeq(i).toFixPoint(xyWidth, xyFracWidth).toBigInt,\n xinSeq(i).toFixPoint(xyWidth, xyFracWidth).toBigInt,\n )\n })\n \n val txUserSeq = src.randomUsers(nBeats)\n\n val txThr = src.sendBeats(genLastAtLastBeat = true, dataSeq = txDataSeq, userSeq = txUserSeq)\n val rxThr = snk.recvBeatsToLast()\n\n txThr.join()\n rxThr.join()\n\n val outSeq = snk.dataSeq.map(d => d.bitSlicesByteWise(zWidth, xyWidth, xyWidth))\n val xoutSeq = outSeq.map(o => o(2).valueAsFixPoint(xyWidth, xyFracWidth))\n val youtSeq = outSeq.map(o => o(1).valueAsFixPoint(xyWidth, xyFracWidth))\n val zoutSeq = outSeq.map(o => o(0).valueAsFixPoint(zWidth, zFracWidth))\n\n if(verbose) {\n println(\"--------------------------------------------------------\")\n var lastClock = 0L\n for (i <- 0L until math.max(src.totalClocks, snk.totalClocks)) {\n val srcStr = src.signalStringOfClock(i)\n val snkStr = snk.signalStringOfClock(i)\n if (srcStr(0) != ' ' || snkStr(0) != ' ') {\n val clkInc = i - lastClock\n println(f\"clk+${clkInc}%02d=${i}%04d: ${srcStr} --> ${snkStr}\")\n lastClock = i\n }\n }\n println(\"--------------------------------------------------------\")\n for (i <- 0 until nBeats) {\n print(f\"beat_${i}%04d: \")\n print(f\"(${xinSeq(i)}%6.3f, ${yinSeq(i)}%6.3f, ${zinSeq(i)}%6.3f) --> \")\n println(f\"(${xoutRefSeq(i)}%6.3f, ${youtRefSeq(i)}%6.3f, ${zoutRefSeq(i)}%6.3f)\")\n print(\" \")\n println(f\"got (${xoutSeq(i)}%6.3f, ${youtSeq(i)}%6.3f, ${zoutSeq(i)}%6.3f)\")\n println()\n }\n }\n\n println(\"--------------------------------------------------------\")\n val xerr = elemWiseDiff(xoutSeq, xoutRefSeq)\n val yerr = elemWiseDiff(youtSeq, youtRefSeq)\n val zerr = elemWiseDiff(zoutSeq, zoutRefSeq)\n val (xm, xmi, xr) = maxAndRms(xerr)\n val (ym, ymi, yr) = maxAndRms(yerr)\n val (zm, zmi, zr) = maxAndRms(zerr)\n val (xmLsb, xrLsb) = (xm / xyLsb, xr / xyLsb)\n val (ymLsb, yrLsb) = (ym / xyLsb, yr / xyLsb)\n val (zmLsb, zrLsb) = (zm / zLsb, zr / zLsb)\n\n println(f\"Error of x: Max Abs = ${xm}%8.6f(${xmLsb}%4.2fLSB, @${xmi}%03d), Std Dev = ${xr}%8.6f(${xrLsb}%4.2fLSB)\")\n println(f\"Error of y: Max Abs = ${ym}%8.6f(${ymLsb}%4.2fLSB, @${ymi}%03d), Std Dev = ${yr}%8.6f(${yrLsb}%4.2fLSB)\")\n println(f\"Error of z: Max Abs = ${zm}%8.6f(${zmLsb}%4.2fLSB, @${zmi}%03d), Std Dev = ${zr}%8.6f(${zrLsb}%4.2fLSB)\")\n\n val inMaxAbsLimit = (xmLsb < 2 && ymLsb < 20 && zmLsb < 10)\n inMaxAbsLimit should be (true)\n val inStdDevLimit = (xrLsb < 1 && yrLsb < 4 && zrLsb < 2)\n inStdDevLimit should be (true)\n\n println(\"--------------------------------------------------------\")\n println(s\"\\u001b[1mErrors Meets Spec: ${if (inMaxAbsLimit && inStdDevLimit) \"YES\" else \"NO\"}\\u001b[0m\")\n println(\"========================================================\")\n Thread.sleep(1000)\n }\n }\n }\n \n \"DUT Cordic Linear Vectoring\" should \"PASS\" in {\n /**\n * Functions for this test:\n * - x := x\n * - y := 0\n * - z := z + y / x\n *\n * Domains of this test:\n * - x_i: (-1, 1), except [-1/8, 1/8]\n * - y_i: (-1, 1)\n * - z_i: (-8, 8)\n * - x_o: (-1, 1)\n * - y_o = 0\n * - z_o: (-16, 16)\n */\n val xyFracWidth = xyWidth - 3\n val zFracWidth = zWidth - 5\n val xyLsb = math.pow(2.0, -xyFracWidth)\n val zLsb = math.pow(2.0, -zFracWidth)\n \n test(\n // stage Idx start from -2, for extend z range from abs(y/x) < 2 to abs(y/x) < 8,\n // meanwhile, x & y width must cover max{x_in, y_in} * 2^2, x_out, y_out}\n new CordicWrapper(xyFracWidth, zFracWidth, CordicCoordinates.Linear, CordicMode.Vectoring, -2)\n ).withAnnotations(\n shouldUseVerilator/* ++ Seq(WriteVcdAnnotation)*/\n ) {\n dut => {\n \n println(\n s\"\"\"\n |========================================================\n | Test CORDIC Linear Vectoring with ${nBeats} data ...\"\"\".stripMargin)\n \n val src = new StrTestSource(dut.clock, dut.io.us)\n src.setThrottle(randomValid, validInterval)\n \n val snk = new StrTestSink(dut.clock, dut.io.ds)\n snk.setThrottle(randomReady, readyInterval)\n\n val xAbsRand = new UniformRealDistribution(\n 1.0 / 8, 1.0 - 16 * xyLsb\n )\n val xSignRand = new UniformIntegerDistribution(0, 1)\n\n val yRand = new UniformRealDistribution(\n -1.0 + 16 * xyLsb, 1.0 - 16 * xyLsb\n )\n\n val zRand = new UniformRealDistribution(\n -8.0 + 16 * zLsb, 8.0 - 16 * zLsb\n )\n\n val xinSeq = Seq.fill(nBeats)(xAbsRand.sample() * (if (xSignRand.sample() == 1) 1.0 else -1.0))\n val yinSeq = Seq.fill(nBeats)(yRand.sample())\n val zinSeq = Seq.fill(nBeats)(zRand.sample())\n \n val xoutRefSeq = xinSeq.map(_.abs)\n val youtRefSeq = Seq.fill(nBeats)(0.0)\n val zoutRefSeq = (0 until nBeats).map(i => {\n zinSeq(i) + yinSeq(i) / xinSeq(i)\n })\n \n val txDataSeq = (0 until nBeats).map(i => {\n CatByteWise(Seq.fill(3)(true), Seq(zWidth, xyWidth, xyWidth),\n zinSeq(i).toFixPoint(zWidth, zFracWidth).toBigInt,\n yinSeq(i).toFixPoint(xyWidth, xyFracWidth).toBigInt,\n xinSeq(i).toFixPoint(xyWidth, xyFracWidth).toBigInt,\n )\n })\n \n val txUserSeq = src.randomUsers(nBeats)\n \n val txThr = src.sendBeats(genLastAtLastBeat = true, dataSeq = txDataSeq, userSeq = txUserSeq)\n val rxThr = snk.recvBeatsToLast()\n \n txThr.join()\n rxThr.join()\n \n val outSeq = snk.dataSeq.map(d => d.bitSlicesByteWise(zWidth, xyWidth, xyWidth))\n val xoutSeq = outSeq.map(o => o(2).valueAsFixPoint(xyWidth, xyFracWidth))\n val youtSeq = outSeq.map(o => o(1).valueAsFixPoint(xyWidth, xyFracWidth))\n val zoutSeq = outSeq.map(o => o(0).valueAsFixPoint(zWidth, zFracWidth))\n\n if(verbose) {\n println(\"--------------------------------------------------------\")\n var lastClock = 0L\n for (i <- 0L until math.max(src.totalClocks, snk.totalClocks)) {\n val srcStr = src.signalStringOfClock(i)\n val snkStr = snk.signalStringOfClock(i)\n if (srcStr(0) != ' ' || snkStr(0) != ' ') {\n val clkInc = i - lastClock\n println(f\"clk+${clkInc}%02d=${i}%04d: ${srcStr} --> ${snkStr}\")\n lastClock = i\n }\n }\n println(\"--------------------------------------------------------\")\n for (i <- 0 until nBeats) {\n", "right_context": " print(f\"(${xinSeq(i)}%6.3f, ${yinSeq(i)}%6.3f, ${zinSeq(i)}%6.3f) --> \")\n println(f\"(${xoutRefSeq(i)}%6.3f, ${youtRefSeq(i)}%6.3f, ${zoutRefSeq(i)}%7.3f)\")\n print(\" \")\n println(f\"got (${xoutSeq(i)}%6.3f, ${youtSeq(i)}%6.3f, ${zoutSeq(i)}%7.3f)\")\n println()\n }\n }\n\n println(\"--------------------------------------------------------\")\n val xerr = elemWiseDiff(xoutSeq, xoutRefSeq)\n val yerr = elemWiseDiff(youtSeq, youtRefSeq)\n val zerr = elemWiseDiff(zoutSeq, zoutRefSeq)\n val (xm, xmi, xr) = maxAndRms(xerr)\n val (ym, ymi, yr) = maxAndRms(yerr)\n val (zm, zmi, zr) = maxAndRms(zerr)\n val (xmLsb, xrLsb) = (xm / xyLsb, xr / xyLsb)\n val (ymLsb, yrLsb) = (ym / xyLsb, yr / xyLsb)\n val (zmLsb, zrLsb) = (zm / zLsb, zr / zLsb)\n \n println(f\"Error of x: Max Abs = ${xm}%8.6f(${xmLsb}%4.2fLSB, @${xmi}%03d), Std Dev = ${xr}%8.6f(${xrLsb}%4.2fLSB)\")\n println(f\"Error of y: Max Abs = ${ym}%8.6f(${ymLsb}%4.2fLSB, @${ymi}%03d), Std Dev = ${yr}%8.6f(${yrLsb}%4.2fLSB)\")\n println(f\"Error of z: Max Abs = ${zm}%8.6f(${zmLsb}%4.2fLSB, @${zmi}%03d), Std Dev = ${zr}%8.6f(${zrLsb}%4.2fLSB)\")\n\n val inMaxAbsLimit = (xmLsb < 2 && ymLsb < 10 && zmLsb < 20)\n inMaxAbsLimit should be (true)\n val inStdDevLimit = (xrLsb < 1 && yrLsb < 2 && zrLsb < 4)\n inStdDevLimit should be (true)\n\n println(\"--------------------------------------------------------\")\n println(s\"\\u001b[1mErrors Meets Spec: ${if (inMaxAbsLimit && inStdDevLimit) \"YES\" else \"NO\"}\\u001b[0m\")\n println(\"========================================================\")\n Thread.sleep(1000)\n }\n }\n }\n}", "groundtruth": " print(f\"beat_${i}%04d: \")\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "FPGA-Application-Development-and-Simulation", "path": "FPGA-Application-Development-and-Simulation/chisel/src/test/scala/test_str_cordic_2.scala", "left_context": "/*\n * MIT License\n *\n * Copyright (c) 2025 loykylewong (loywong@gmail.com)\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n */\n\npackage test_str_cordic_2\n\nimport chisel3._\nimport chisel3.util._\nimport chiseltest._\nimport org.scalatest.flatspec.AnyFlatSpec\nimport org.scalatest.matchers.should.Matchers._\nimport loywong._\nimport loywong.util._\nimport loywongtest._\nimport org.apache.commons.math3.distribution.{UniformRealDistribution, UniformIntegerDistribution}\n\nobject SimSettings {\n val nBeats = 500\n val verbose: Boolean = nBeats <= 1000\n\n val randomValid = false\n val validInterval = 0.0 // if random, it's the poisson lambda\n val randomReady = false\n val readyInterval = 0.0 // if random, it's the poisson lambda\n\n val xyWidth = 12\n val zWidth = 12\n\n val userWidth = 8\n}\n\nimport SimSettings._\n\nclass CordicIOBitsWithUser extends CordicIOStrBits(xyWidth, zWidth) with StrHasLast with StrHasUser {\n override val last = Bool()\n override val user = UInt(userWidth.W)\n}\n\nclass CordicWrapperIOBits extends StrHasData with StrHasLast with StrHasUser {\n override val data = UInt((xyWidth.up8 * 2 + zWidth.up8).W)\n override val last = Bool()\n override val user = UInt(userWidth.up8.W)\n}\n\nclass CordicWrapper(xyFW: Int, zFW: Int, coor: CordicCoordinates.Value, mode: CordicMode.Value, linStgStart: Int = 0) extends Module {\n val io = IO(new Bundle {\n val us = Flipped(Irrevocable(new CordicWrapperIOBits))\n val ds = Irrevocable(new CordicWrapperIOBits)\n })\n\n val dut = Module(new Cordic(new CordicIOBitsWithUser, zWidth - 1, xyFW, zFW, coor, mode, linStgStart))\n\n io.us.bits.data.sliceByteWiseTo(dut.io.us.bits.z, dut.io.us.bits.y, dut.io.us.bits.x)\n io.us.bits.last <> dut.io.us.bits.last\n io.us.bits.user.sliceByteWiseTo(dut.io.us.bits.user)\n io.us.valid <> dut.io.us.valid\n io.us.ready <> dut.io.us.ready\n\n /**\n * birs for eliminate ready comb which may cause\n * \"Unordered poke after peek\" runtime error.\n */\n val brs = Module(new StrBirs(new CordicWrapperIOBits))\n\n brs.io.us.bits.data.catByteWiseFrom(dut.io.ds.bits.z, dut.io.ds.bits.y, dut.io.ds.bits.x)\n brs.io.us.bits.last <> dut.io.ds.bits.last\n brs.io.us.bits.user.catByteWiseFrom(dut.io.ds.bits.user)\n brs.io.us.valid <> dut.io.ds.valid\n brs.io.us.ready <> dut.io.ds.ready\n\n io.ds <> brs.io.ds\n}\n\nclass test extends AnyFlatSpec with ChiselScalatestTester {\n\n val shouldUseVerilator =\n if (System.getProperty(\"os.name\").toLowerCase.contains(\"win\"))\n Seq.empty[firrtl2.annotations.Annotation]\n else\n Seq(VerilatorBackendAnnotation)\n\n \"DUT Cordic Hyperbolic Rotation\" should \"Pass\" in {\n /**\n * Functions for this test:\n * - x := x cosh(z) + y sinh(z) = 0.5 * (x + y) exp(z) + 0.5 * (x - y) exp(z)\n * - y := x sinh(z) + y cosh(z) = 0.5 * (y + x) exp(z) + 0.5 * (y - x) exp(z)\n * - z := 0\n *\n * Domains of this test:\n * - x_i: (-4/e, 4/e)\n * - y_i: (-4/e, 4/e)\n * - z_i: (-1, 1)\n * - x_o: (-4, 4)\n * - y_o: (-4, 4)\n * - z_o: = 0\n */\n val xyFracWidth = xyWidth - 3\n val zFracWidth = zWidth - 1\n val xyLsb = math.pow(2.0, -xyFracWidth)\n val zLsb = math.pow(2.0, -zFracWidth)\n\n test(\n new CordicWrapper(xyFracWidth, zFracWidth, CordicCoordinates.Hyperbolic, CordicMode.Rotation)\n ).withAnnotations(\n shouldUseVerilator/* ++ Seq(WriteVcdAnnotation)*/\n ) {\n dut => {\n\n println(\n s\"\"\"\n |========================================================\n | Test CORDIC Hyperbolic Rotation with ${nBeats} data ...\"\"\".stripMargin)\n \n val src = new StrTestSource(dut.clock, dut.io.us)\n src.setThrottle(randomValid, validInterval)\n\n val snk = new StrTestSink(dut.clock, dut.io.ds)\n snk.setThrottle(randomReady, readyInterval)\n\n val xyRand = new UniformRealDistribution(\n -4.0 / math.E + 16 * xyLsb, 4.0 / math.E - 16 * xyLsb\n )\n\n val zRand = new UniformRealDistribution(\n -1.0 + 16 * zLsb, 1.0 - 16 * zLsb\n )\n\n val xinSeq = Seq.fill(nBeats)(xyRand.sample())\n val yinSeq = Seq.fill(nBeats)(xyRand.sample())\n val zinSeq = Seq.fill(nBeats)(zRand.sample())\n\n val xoutRefSeq = (0 until nBeats).map(i => {\n xinSeq(i) * math.cosh(zinSeq(i)) + yinSeq(i) * math.sinh(zinSeq(i))\n })\n val youtRefSeq = (0 until nBeats).map(i => {\n xinSeq(i) * math.sinh(zinSeq(i)) + yinSeq(i) * math.cosh(zinSeq(i))\n })\n val zoutRefSeq = Seq.fill(nBeats)(0.0)\n \n val txDataSeq = (0 until nBeats).map(i => {\n CatByteWise(Seq.fill(3)(true), Seq(zWidth, xyWidth, xyWidth),\n zinSeq(i).toFixPoint(zWidth, zFracWidth).toBigInt,\n yinSeq(i).toFixPoint(xyWidth, xyFracWidth).toBigInt,\n xinSeq(i).toFixPoint(xyWidth, xyFracWidth).toBigInt,\n )\n })\n \n val txUserSeq = src.randomUsers(nBeats)\n\n val txThr = src.sendBeats(genLastAtLastBeat = true, dataSeq = txDataSeq, userSeq = txUserSeq)\n val rxThr = snk.recvBeatsToLast()\n\n txThr.join()\n rxThr.join()\n\n val outSeq = snk.dataSeq.map(d => d.bitSlicesByteWise(zWidth, xyWidth, xyWidth))\n val xoutSeq = outSeq.map(o => o(2).valueAsFixPoint(xyWidth, xyFracWidth))\n val youtSeq = outSeq.map(o => o(1).valueAsFixPoint(xyWidth, xyFracWidth))\n val zoutSeq = outSeq.map(o => o(0).valueAsFixPoint(zWidth, zFracWidth))\n\n if(verbose) {\n println(\"--------------------------------------------------------\")\n var lastClock = 0L\n for (i <- 0L until math.max(src.totalClocks, snk.totalClocks)) {\n val srcStr = src.signalStringOfClock(i)\n val snkStr = snk.signalStringOfClock(i)\n if (srcStr(0) != ' ' || snkStr(0) != ' ') {\n val clkInc = i - lastClock\n println(f\"clk+${clkInc}%02d=${i}%04d: ${srcStr} --> ${snkStr}\")\n lastClock = i\n }\n }\n println(\"--------------------------------------------------------\")\n for (i <- 0 until nBeats) {\n", "right_context": " print(f\"(${xinSeq(i)}%6.3f, ${yinSeq(i)}%6.3f, ${zinSeq(i)}%6.3f) --> \")\n println(f\"(${xoutRefSeq(i)}%6.3f, ${youtRefSeq(i)}%6.3f, ${zoutRefSeq(i)}%6.3f)\")\n print(\" \")\n println(f\"got (${xoutSeq(i)}%6.3f, ${youtSeq(i)}%6.3f, ${zoutSeq(i)}%6.3f)\")\n println()\n }\n }\n\n println(\"--------------------------------------------------------\")\n val xerr = elemWiseDiff(xoutSeq, xoutRefSeq)\n val yerr = elemWiseDiff(youtSeq, youtRefSeq)\n val zerr = elemWiseDiff(zoutSeq, zoutRefSeq)\n val (xm, xmi, xr) = maxAndRms(xerr)\n val (ym, ymi, yr) = maxAndRms(yerr)\n val (zm, zmi, zr) = maxAndRms(zerr)\n val (xmLsb, xrLsb) = (xm / xyLsb, xr / xyLsb)\n val (ymLsb, yrLsb) = (ym / xyLsb, yr / xyLsb)\n val (zmLsb, zrLsb) = (zm / zLsb, zr / zLsb)\n\n println(f\"Error of x: Max Abs = ${xm}%8.6f(${xmLsb}%4.2fLSB, @${xmi}%03d), Std Dev = ${xr}%8.6f(${xrLsb}%4.2fLSB)\")\n println(f\"Error of y: Max Abs = ${ym}%8.6f(${ymLsb}%4.2fLSB, @${ymi}%03d), Std Dev = ${yr}%8.6f(${yrLsb}%4.2fLSB)\")\n println(f\"Error of z: Max Abs = ${zm}%8.6f(${zmLsb}%4.2fLSB, @${zmi}%03d), Std Dev = ${zr}%8.6f(${zrLsb}%4.2fLSB)\")\n\n val inMaxAbsLimit = (xmLsb < 20 && ymLsb < 20 && zmLsb < 10)\n inMaxAbsLimit should be (true)\n val inStdDevLimit = (xrLsb < 4 && yrLsb < 4 && zrLsb < 2)\n inStdDevLimit should be (true)\n\n println(\"--------------------------------------------------------\")\n println(s\"\\u001b[1mErrors Meets Spec: ${if (inMaxAbsLimit && inStdDevLimit) \"YES\" else \"NO\"}\\u001b[0m\")\n println(\"========================================================\")\n Thread.sleep(1000)\n }\n }\n }\n\n \"DUT Cordic Hyperbolic Vectoring\" should \"PASS\" in {\n /**\n * Functions for this test:\n * - x := \\sqrt{x^2 - y^2}\n * - y := 0\n * - z := z + arctanh(y / x) = z + 0.5 * ln((x + y) / (x - y))\n *\n * Domains of this test:\n * - x_i: (-1, 1)\n * - y_i: (-1, 1) and abs(y) < abs(x) * 0.761594 (make abs(arctanh(y/x) < 1)\n * - z_i: (-1, 1)\n * - x_o: (0, 1)\n * - y_o = 0\n * - z_o: (-2, 2)\n */\n val xyFracWidth = xyWidth - 1\n val zFracWidth = zWidth - 2\n val xyLsb = math.pow(2.0, -xyFracWidth)\n val zLsb = math.pow(2.0, -zFracWidth)\n \n test(\n new CordicWrapper(xyFracWidth, zFracWidth, CordicCoordinates.Hyperbolic, CordicMode.Vectoring)\n ).withAnnotations(\n shouldUseVerilator/* ++ Seq(WriteVcdAnnotation)*/\n ) {\n dut => {\n \n println(\n s\"\"\"\n |========================================================\n | Test CORDIC Hyperbolic Vectoring with ${nBeats} data ...\"\"\".stripMargin)\n \n val src = new StrTestSource(dut.clock, dut.io.us)\n src.setThrottle(randomValid, validInterval)\n \n val snk = new StrTestSink(dut.clock, dut.io.ds)\n snk.setThrottle(randomReady, readyInterval)\n\n val xyAbsRand = new UniformRealDistribution(\n 0.25 + 16 * xyLsb, 1.0 - 16 * xyLsb\n )\n val xySignRand = new UniformIntegerDistribution(0, 1)\n\n val zRand = new UniformRealDistribution(\n -1.0 + 16 * zLsb, 1.0 - 16 * zLsb\n )\n\n val xinSeq = Seq.fill(nBeats)(xyAbsRand.sample() * (if (xySignRand.sample() == 1) 1.0 else -1.0))\n val yinSeq = xinSeq.map(x =>\n xyAbsRand.sample().mapFromTo(0, 1, 0.25 * 0.761594, x * 0.761594) * (if (xySignRand.sample() == 1) 1.0 else -1.0))\n val zinSeq = Seq.fill(nBeats)(zRand.sample())\n \n val xoutRefSeq = (0 until nBeats).map(i =>\n math.sqrt(xinSeq(i) * xinSeq(i) - yinSeq(i) * yinSeq(i))\n )\n val youtRefSeq = Seq.fill(nBeats)(0.0)\n val zoutRefSeq = (0 until nBeats).map(i => {\n zinSeq(i) + atanh(yinSeq(i) / xinSeq(i))\n })\n \n val txDataSeq = (0 until nBeats).map(i => {\n CatByteWise(Seq.fill(3)(true), Seq(zWidth, xyWidth, xyWidth),\n zinSeq(i).toFixPoint(zWidth, zFracWidth).toBigInt,\n yinSeq(i).toFixPoint(xyWidth, xyFracWidth).toBigInt,\n xinSeq(i).toFixPoint(xyWidth, xyFracWidth).toBigInt,\n )\n })\n \n val txUserSeq = src.randomUsers(nBeats)\n \n val txThr = src.sendBeats(genLastAtLastBeat = true, dataSeq = txDataSeq, userSeq = txUserSeq)\n val rxThr = snk.recvBeatsToLast()\n \n txThr.join()\n rxThr.join()\n \n val outSeq = snk.dataSeq.map(d => d.bitSlicesByteWise(zWidth, xyWidth, xyWidth))\n val xoutSeq = outSeq.map(o => o(2).valueAsFixPoint(xyWidth, xyFracWidth))\n val youtSeq = outSeq.map(o => o(1).valueAsFixPoint(xyWidth, xyFracWidth))\n val zoutSeq = outSeq.map(o => o(0).valueAsFixPoint(zWidth, zFracWidth))\n\n if(verbose) {\n println(\"--------------------------------------------------------\")\n var lastClock = 0L\n for (i <- 0L until math.max(src.totalClocks, snk.totalClocks)) {\n val srcStr = src.signalStringOfClock(i)\n val snkStr = snk.signalStringOfClock(i)\n if (srcStr(0) != ' ' || snkStr(0) != ' ') {\n val clkInc = i - lastClock\n println(f\"clk+${clkInc}%02d=${i}%04d: ${srcStr} --> ${snkStr}\")\n lastClock = i\n }\n }\n println(\"--------------------------------------------------------\")\n for (i <- 0 until nBeats) {\n print(f\"beat_${i}%04d: \")\n print(f\"(${xinSeq(i)}%6.3f, ${yinSeq(i)}%6.3f, ${zinSeq(i)}%6.3f) --> \")\n println(f\"(${xoutRefSeq(i)}%6.3f, ${youtRefSeq(i)}%6.3f, ${zoutRefSeq(i)}%7.3f)\")\n print(\" \")\n println(f\"got (${xoutSeq(i)}%6.3f, ${youtSeq(i)}%6.3f, ${zoutSeq(i)}%7.3f)\")\n println()\n }\n }\n\n println(\"--------------------------------------------------------\")\n val xerr = elemWiseDiff(xoutSeq, xoutRefSeq)\n val yerr = elemWiseDiff(youtSeq, youtRefSeq)\n val zerr = elemWiseDiff(zoutSeq, zoutRefSeq)\n val (xm, xmi, xr) = maxAndRms(xerr)\n val (ym, ymi, yr) = maxAndRms(yerr)\n val (zm, zmi, zr) = maxAndRms(zerr)\n val (xmLsb, xrLsb) = (xm / xyLsb, xr / xyLsb)\n val (ymLsb, yrLsb) = (ym / xyLsb, yr / xyLsb)\n val (zmLsb, zrLsb) = (zm / zLsb, zr / zLsb)\n \n println(f\"Error of x: Max Abs = ${xm}%8.6f(${xmLsb}%4.2fLSB, @${xmi}%03d), Std Dev = ${xr}%8.6f(${xrLsb}%4.2fLSB)\")\n println(f\"Er ror of y: Max Abs = ${ym}%8.6f(${ymLsb}%4.2fLSB, @${ymi}%03d), Std Dev = ${yr}%8.6f(${yrLsb}%4.2fLSB)\")\n println(f\"Error of z: Max Abs = ${zm}%8.6f(${zmLsb}%4.2fLSB, @${zmi}%03d), Std Dev = ${zr}%8.6f(${zrLsb}%4.2fLSB)\")\n\n val inMaxAbsLimit = (xmLsb < 20 && ymLsb < 10 && zmLsb < 20)\n inMaxAbsLimit should be (true)\n val inStdDevLimit = (xrLsb < 4 && yrLsb < 2 && zrLsb < 4)\n inStdDevLimit should be (true)\n\n println(\"--------------------------------------------------------\")\n println(s\"\\u001b[1mErrors Meets Spec: ${if (inMaxAbsLimit && inStdDevLimit) \"YES\" else \"NO\"}\\u001b[0m\")\n println(\"========================================================\")\n Thread.sleep(1000)\n }\n }\n }\n}\n", "groundtruth": " print(f\"beat_${i}%04d: \")\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "riscv-self", "path": "riscv-self/src/main/scala/ALU.scala", "left_context": "package rself\n\nimport chisel3._\nimport chisel3.util._\n\nimport ALU_MODE._\n\nclass ALUIO extends Bundle {\n", "right_context": " val B = Input(UInt(32.W))\n val alu_op = Input(UInt(4.W))\n val out = Output(UInt(32.W))\n}\n\nclass ALU extends Module {\n val io = IO(new ALUIO)\n val shamt = io.B(4,0).asUInt\n\n io.out := MuxLookup(io.alu_op, io.B, Seq(\n ALU_ADD -> (io.A + io.B),\n ALU_SUB -> (io.A - io.B),\n ALU_SRA -> (io.A.asSInt >> shamt).asUInt,\n ALU_SRL -> (io.A >> shamt),\n ALU_SLL -> (io.A << shamt),\n ALU_SLT -> (io.A.asSInt < io.B.asSInt),\n ALU_SLTU -> (io.A < io.B),\n ALU_AND -> (io.A & io.B),\n ALU_OR -> (io.A | io.B),\n ALU_XOR -> (io.A ^ io.B)))\n}\n", "groundtruth": " val A = Input(UInt(32.W))\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.8, "category_reason": "Input or Output in Bundle/IO context"} {"task_id": "riscv-self", "path": "riscv-self/src/main/scala/BranchCond.scala", "left_context": "package rself\n\nimport chisel3._\nimport chisel3.util._\n\nimport BR_TYPE._\n\nclass BrCondIO extends Bundle {\n val rs1 = Input(UInt(32.W))\n val rs2 = Input(UInt(32.W))\n val br_type = Input(UInt(3.W))\n}\n\n", "right_context": " val cond = new BrCondIO\n val isJmp = Output(Bool())\n })\n val xlen = 32\n val diff = io.cond.rs1 - io.cond.rs2\n val neq = diff.orR\n val eq = !neq\n val isSameSign = io.cond.rs1(xlen-1) === io.cond.rs2(xlen-1)\n val lt = Mux(isSameSign, diff(xlen-1), io.cond.rs1(xlen-1))\n val ltu = Mux(isSameSign, diff(xlen-1), io.cond.rs2(xlen-1))\n val ge = !lt\n val geu = !ltu\n\n io.isJmp := MuxLookup(io.cond.br_type, false.B, Seq(\n BR_EQ -> eq,\n BR_NE -> neq,\n BR_LT -> lt,\n BR_GE -> ge,\n BR_LTU -> ltu,\n BR_GEU -> geu))\n}\n\nclass BrJump extends Module {\n val io = IO(new Bundle {\n val jmpAddr = Output(UInt(32.W))\n val jmp = new BrJumpIO\n })\n io.jmpAddr := io.jmp.PC + Utility.extendSign(io.jmp.disp, 32)\n}\n\nclass Branch extends Module {\n val io = IO(new Bundle {\n val cond = new BrCondIO\n val jump = new BrJumpIO\n val jmpAddr = Output(UInt(32.W))\n val isJmp = Output(Bool())\n })\n val modCond = Module(new BrCond)\n val modJump = Module(new BrJump)\n modCond.io.cond := io.cond\n modJump.io.jmp := io.jump\n\n io.isJmp := modCond.io.isJmp\n io.jmpAddr := modJump.io.jmpAddr\n}\n", "groundtruth": "class BrJumpIO extends Bundle {\n val disp = Input(UInt(13.W))\n val PC = Input(UInt(32.W))\n}\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.9, "category_reason": "Bundle class definition"} {"task_id": "riscv-self", "path": "riscv-self/src/main/scala/Compile.scala", "left_context": "package rself\n\nimport java.io.{File, FileWriter}\n\nobject Compile {\n val modules:Map[String, () => chisel3.Module] = Map(\n \"RegFile\" -> (() => new RegFile),\n \"ALU\" -> (() => new ALU),\n \"Control\" -> (() => new Control),\n \"ImmGen\" -> (() => new ImmGen),\n \"Branch\" -> (() => new Branch),\n \"LoadStore\" -> (() => new LoadStore),\n \"Execute\" -> (() => new Execute),\n \"Datapath\" -> (() => new Datapath)\n )\n\n def dump(dir:File, mod: () => chisel3.Module) = {\n val chirrtl = firrtl.Parser.parse(chisel3.Driver.emit(mod))\n val writer = new FileWriter(new File(dir, s\"${chirrtl.main}.fir\"))\n writer write chirrtl.serialize\n writer.close\n\n", "right_context": " new firrtl.VerilogCompiler compile (\n firrtl.CircuitState(chirrtl, firrtl.ChirrtlForm), verilog)\n verilog.close\n }\n\n def main(args: Array[String]): Unit = {\n val dir = new File(args(0)) ; dir.mkdirs\n if (args.length >= 2) {\n modules.get(args(1)) match {\n case Some(mod) =>\n dump(dir, mod)\n case _ =>\n println(s\"no module names ${args(1)}\")\n }\n }\n else {\n modules.foreach {\n case (key, value) => dump(dir, value)\n }\n }\n }\n}\n", "groundtruth": " val verilog = new FileWriter(new File(dir, s\"${chirrtl.main}.v\"))\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.6, "category_reason": "val binding"} {"task_id": "riscv-self", "path": "riscv-self/src/main/scala/Constants.scala", "left_context": "// auto generate by python scripts\n\npackage rself\n\nimport chisel3._\n\nobject ALU_MODE {\n val ALU_ADD = 0.U(4.W)\n val ALU_SUB = 8.U(4.W)\n val ALU_SLL = 1.U(4.W)\n val ALU_SLT = 2.U(4.W)\n val ALU_SLTU = 3.U(4.W)\n val ALU_XOR = 4.U(4.W)\n val ALU_SRL = 5.U(4.W)\n", "right_context": "}\n\nobject IMM_MODE {\n val IMM_R = 0.U(3.W)\n val IMM_I = 1.U(3.W)\n val IMM_S = 2.U(3.W)\n val IMM_U = 3.U(3.W)\n val IMM_J = 4.U(3.W)\n val IMM_B = 5.U(3.W)\n val IMM_Z = 6.U(3.W)\n}\n\nobject SL_TYPE {\n val SL_B = 0.U(2.W)\n val SL_H = 1.U(2.W)\n val SL_W = 2.U(2.W)\n val SL_D = 3.U(2.W)\n}\n\nobject BR_TYPE {\n val BR_EQ = 0.U(3.W)\n val BR_NE = 1.U(3.W)\n val BR_LT = 4.U(3.W)\n val BR_GE = 5.U(3.W)\n val BR_LTU = 6.U(3.W)\n val BR_GEU = 7.U(3.W)\n}\n\n", "groundtruth": " val ALU_SRA = 13.U(4.W)\n val ALU_OR = 6.U(4.W)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.7, "category_reason": "Literal value binding"} {"task_id": "riscv-self", "path": "riscv-self/src/main/scala/Control.scala", "left_context": "package rself\n\nimport chisel3._\nimport chisel3.util._\n\nobject ACT {\n val ALU = 0.U(3.W) // ALU\n val BRC = 1.U(3.W) // BranchCondition\n val LDS = 2.U(3.W) // Load and Store\n val FEN = 3.U(3.W) // Fence\n val SYS = 4.U(3.W) // System call\n val LUI = 5.U(3.W) // Load Upper Immediate\n val AUI = 6.U(3.W) // Add Upper Immediate to PC\n val JMP = 7.U(3.W) // Jump Directly\n}\n\nimport IMM_MODE._\n\nobject Control {\n val opdefault = List(IMM_Z, ACT.SYS)\n val opsel = Array(\n BitPat(\"b01100\") -> List(IMM_R, ACT.ALU),\n BitPat(\"b00100\") -> List(IMM_I, ACT.ALU),\n BitPat(\"b01000\") -> List(IMM_S, ACT.LDS),\n BitPat(\"b00000\") -> List(IMM_I, ACT.LDS),\n BitPat(\"b11000\") -> List(IMM_B, ACT.BRC),\n BitPat(\"b11100\") -> List(IMM_Z, ACT.SYS),\n BitPat(\"b00011\") -> List(IMM_Z, ACT.FEN),\n BitPat(\"b11011\") -> List(IMM_J, ACT.JMP),\n BitPat(\"b11001\") -> List(IMM_I, ACT.JMP),\n BitPat(\"b00101\") -> List(IMM_U, ACT.AUI),\n BitPat(\"b01101\") -> List(IMM_U, ACT.LUI))\n}\n\nclass Control extends Module {\n val io = IO(new Bundle {\n", "right_context": " io.sel := ctrlSignals(1)\n io.mode := MuxLookup(ctrlSignals(1), 0.U(4.W), Seq(\n ACT.ALU -> Mux(io.inst(5) === 1.U,\n Cat(io.inst(30), io.inst(14, 12)),\n Mux(io.inst(13, 12) === 1.U(2.W),\n Cat(io.inst(30), io.inst(14, 12)),\n Cat(0.U(1.W), io.inst(14, 12)))),\n ACT.LDS -> Cat(io.inst(5), io.inst(14, 12)),\n ACT.BRC -> Cat(0.U(1.W), io.inst(14, 12)),\n ACT.JMP -> Cat(0.U(3.W), io.inst(3))))\n}\n", "groundtruth": " val inst = Input(UInt(32.W))\n val mode = Output(UInt(4.W))\n val sel = Output(UInt(3.W))\n val imm = Output(UInt(3.W))\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.85, "category_reason": "Input/Output port declarations"} {"task_id": "riscv-self", "path": "riscv-self/src/main/scala/Datapath.scala", "left_context": "package rself\n\nimport chisel3._\nimport chisel3.util._\n\nobject Const {\n val PC_START = 0x200\n val PC_EVEC = 0x100\n}\n\nobject Instruction {\n def NOP = BitPat.bitPatToUInt(BitPat(\"b00000000000000000000000000010011\"))\n}\n\nclass InstructionReader extends Module {\n val io = IO(new Bundle {\n val en = Input(Bool())\n val ready = Output(Bool())\n\n val isJmp = Input(Bool())\n val jaddr = Input(UInt(32.W))\n\n val inst = Output(UInt(32.W))\n val pc = Output(UInt(32.W))\n\n val mem = Flipped(new MemoryReaderIO)\n })\n val pc = RegInit(Const.PC_START.U(32.W))\n val npc = RegInit(Const.PC_START.U(32.W))\n val inst = RegInit(Instruction.NOP)\n\n val vaild = RegInit(false.B)\n\n val posedgeState = RegInit(false.B)\n io.mem.ren := io.en | posedgeState\n posedgeState := (io.en | posedgeState) & ~io.mem.vaild\n\n when (reset.toBool) {\n pc := Const.PC_START.U(32.W)\n } .elsewhen (io.en) {\n pc := Mux(io.isJmp, io.jaddr, npc)\n vaild := false.B\n }\n\n when (io.mem.vaild & ~vaild) {\n inst := io.mem.data\n io.ready := true.B\n npc := pc + 4.U\n vaild := true.B\n } .otherwise {\n io.ready := false.B\n }\n\n io.mem.addr := pc\n io.inst := inst\n io.pc := pc\n}\n\nclass WriteBack extends Module {\n val io = IO(new Bundle {\n val en = Input(Bool())\n val ready = Output(Bool())\n\n val rd = Input(UInt(5.W))\n val data = Input(UInt(32.W))\n\n val reg = Flipped(new RegFileWriterIO)\n })\n\n io.reg.waddr := io.rd\n io.reg.wdata := io.data\n io.reg.wen := io.en\n\n when (io.en) {\n io.ready := true.B\n }.otherwise {\n io.ready := false.B\n }\n}\n\nclass DatapathIO extends Bundle {\n val dmem = Flipped(new MemoryIO)\n val imem = Flipped(new MemoryReaderIO)\n val sys = Output(Bool())\n}\n\nclass Datapath extends Module {\n val io = IO(new DatapathIO)\n val reg = Module(new RegFile)\n val exe = Module(new Execute)\n val inr = Module(new InstructionReader)\n val wrb = Module(new WriteBack)\n\n exe.io.inst := inr.io.inst\n exe.io.pc := inr.io.pc\n\n inr.io.isJmp := exe.io.jmp\n inr.io.jaddr := exe.io.npc\n\n wrb.io.rd := exe.io.rd\n wrb.io.data := exe.io.data\n\n exe.io.mem <> io.dmem\n inr.io.mem <> io.imem\n exe.io.reg <> reg.io.reader\n wrb.io.reg <> reg.io.writer\n\n io.sys := exe.io.sys\n\n val inrEnable = RegInit(true.B)\n val exeEnable = RegInit(false.B)\n val wrbEnable = RegInit(false.B)\n\n val mods = Array(\n inr.io.en -> inr.io.ready,\n exe.io.en -> exe.io.ready,\n wrb.io.en -> wrb.io.ready\n )\n\n val enReg = mods.indices map { i => RegInit((i == 0).B) }\n", "right_context": "\n val modsize = mods.size\n\n mods.zipWithIndex foreach { module =>\n val ((en, ready), index) = module\n en := enReg(index)\n rdReg(index) := ready\n enReg((index+1) % modsize) := ready & ~rdReg(index)\n }\n}\n", "groundtruth": " val rdReg = mods.indices map { i => RegInit(false.B) }\n", "crossfile_context": "", "category": "Storage Block", "subcategory": "Register-based Storage", "confidence": 0.85, "category_reason": "RegInit register"} {"task_id": "riscv-self", "path": "riscv-self/src/main/scala/Execute.scala", "left_context": "package rself\n\nimport chisel3._\nimport chisel3.util._\n\nclass ExecuteIO extends Bundle {\n val en = Input(Bool())\n val pc = Input(UInt(32.W))\n val ready = Output(Bool())\n\n val inst = Input(UInt(32.W))\n\n val jmp = Output(Bool())\n val npc = Output(UInt(32.W))\n val rd = Output(UInt(5.W))\n val data = Output(UInt(32.W))\n val sys = Output(Bool())\n\n val mem = Flipped(new MemoryIO)\n", "right_context": "}\n\nclass Execute extends Module {\n val io = IO(new ExecuteIO)\n\n val ctrl = Module(new Control)\n val immg = Module(new ImmGen)\n\n // Components\n val alu = Module(new ALU)\n val brc = Module(new Branch)\n val jmp = Module(new Jump)\n val lds = Module(new LoadStore)\n val aui = Module(new AddUpperImmPC)\n val lui = Module(new LoadUpperImm)\n val fen = Module(new MemoryOperation)\n val sys = Module(new SystemOperation)\n\n ctrl.io.inst := io.inst\n\n io.reg.raddr1 := io.inst(19, 15)\n io.reg.raddr2 := io.inst(24, 20)\n\n immg.io.inst := io.inst\n immg.io.mode := ctrl.io.imm\n\n val rs1 = io.reg.rdata1\n val rs2 = io.reg.rdata2\n val imm = immg.io.value\n val mode = ctrl.io.mode\n\n alu.io.A := rs1\n alu.io.B := Mux(ctrl.io.imm === IMM_MODE.IMM_R,\n rs2,\n Utility.extendSign(imm(11, 0)))\n alu.io.alu_op := mode\n\n brc.io.cond.rs1 := rs1\n brc.io.cond.rs2 := rs2\n brc.io.cond.br_type := mode(2, 0)\n brc.io.jump.disp := imm(12, 0)\n brc.io.jump.PC := io.pc\n\n jmp.io.mode := mode(0)\n jmp.io.pc := io.pc\n jmp.io.base := rs1\n jmp.io.imm := imm\n\n lds.io.inst := io.inst\n lds.io.mode := mode\n lds.io.en := io.en & (ctrl.io.sel === ACT.LDS)\n lds.io.rs3 := imm\n lds.io.rs2 := rs2\n lds.io.rs1 := rs1\n lds.io.mem <> io.mem\n\n aui.io.pc := io.pc\n aui.io.imm := imm\n\n lui.io.imm := imm\n\n fen.io.inst := io.inst\n\n sys.io.inst := io.inst\n\n io.data := MuxLookup(ctrl.io.sel, 0.U(32.W), Seq(\n ACT.ALU -> alu.io.out,\n ACT.LDS -> lds.io.ret,\n ACT.LUI -> lui.io.ret,\n ACT.AUI -> aui.io.ret,\n ACT.JMP -> jmp.io.ret))\n\n io.rd := MuxLookup(ctrl.io.sel, io.inst(11, 7), Seq(\n ACT.BRC -> 0.U(5.W),\n ACT.LDS -> lds.io.rd))\n\n io.npc := MuxLookup(ctrl.io.sel, 0.U(32.W), Seq(\n ACT.BRC -> brc.io.jmpAddr,\n ACT.JMP -> jmp.io.jaddr,\n ACT.AUI -> aui.io.ret))\n\n io.jmp := MuxLookup(ctrl.io.sel, false.B, Seq(\n ACT.BRC -> brc.io.isJmp,\n ACT.JMP -> true.B,\n ACT.AUI -> true.B))\n\n io.sys := ctrl.io.sel === ACT.SYS\n\n io.ready := MuxLookup(ctrl.io.sel, io.en, Seq(\n ACT.LDS -> lds.io.ready))\n\n}\n", "groundtruth": " val reg = Flipped(new RegFileReaderIO)\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.75, "category_reason": "Flipped port"} {"task_id": "riscv-self", "path": "riscv-self/src/main/scala/ImmGen.scala", "left_context": "package rself\n\nimport chisel3._\nimport chisel3.util._\n\nimport IMM_MODE._\n\nclass ImmGenIO extends Bundle {\n val inst = Input(UInt(32.W))\n val mode = Input(UInt(3.W))\n val value = Output(UInt(32.W))\n}\n\nclass ImmGen extends Module {\n", "right_context": " io.value := MuxLookup(io.mode, 0.U(32.W), Seq(\n IMM_R -> 0.U(32.W),\n IMM_I -> Cat(0.U(20.W), io.inst(31, 20)),\n IMM_S -> Cat(0.U(20.W), io.inst(31, 25), io.inst(11, 7)),\n IMM_B -> Cat(0.U(19.W), io.inst(31), io.inst(7), io.inst(30, 25), io.inst(11, 8), 0.U(1.W)),\n IMM_J -> Cat(0.U(11.W), io.inst(31), io.inst(19, 12), io.inst(20), io.inst(30, 21), 0.U(1.W)),\n IMM_U -> Cat(io.inst(31, 12), 0.U(12.W))))\n}\n", "groundtruth": " val io = IO(new ImmGenIO)\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.9, "category_reason": "IO bundle definition"} {"task_id": "riscv-self", "path": "riscv-self/src/main/scala/Interface.scala", "left_context": "package rself\n\nimport chisel3._\nimport chisel3.util._\n\nclass MemoryReaderIO extends Bundle {\n\n val ren = Input(Bool())\n val data = Output(UInt(32.W))\n val vaild = Output(Bool())\n}\n\nclass MemoryWriterIO extends Bundle {\n", "right_context": " val mode = Input(UInt(2.W))\n val wen = Input(Bool())\n val data = Input(UInt(32.W))\n val vaild = Output(Bool())\n}\n\nclass MemoryIO extends Bundle {\n val writer = new MemoryWriterIO\n val reader = new MemoryReaderIO\n}\n", "groundtruth": " val addr = Input(UInt(32.W))\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.8, "category_reason": "Input or Output in Bundle/IO context"} {"task_id": "riscv-self", "path": "riscv-self/src/main/scala/Jump.scala", "left_context": "package rself\n\nimport chisel3._\nimport chisel3.util._\n\nclass Jump extends Module {\n val io = IO(new Bundle {\n val mode = Input(Bool())\n val pc = Input(UInt(32.W))\n val imm = Input(UInt(32.W))\n val base = Input(UInt(32.W))\n val ret = Output(UInt(32.W))\n val jaddr = Output(UInt(32.W))\n })\n", "right_context": " io.ret := io.pc + 4.U(32.W)\n io.jaddr := Mux(io.mode, s(20), s(11)) + Mux(io.mode, io.pc, io.base)\n}\n\nclass AddUpperImmPC extends Module {\n val io = IO(new Bundle {\n val pc = Input(UInt(32.W))\n val imm = Input(UInt(32.W))\n val ret = Output(UInt(32.W))\n })\n io.ret := io.imm + io.pc\n}\n\nclass LoadUpperImm extends Module {\n val io = IO(new Bundle {\n val imm = Input(UInt(32.W))\n val ret = Output(UInt(32.W))\n })\n io.ret := io.imm\n}\n", "groundtruth": " def s(i: Int): UInt = Utility.extendSign(io.imm(i, 0), 32)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "riscv-self", "path": "riscv-self/src/main/scala/LoadStore.scala", "left_context": "package rself\n\nimport chisel3._\nimport chisel3.util._\n\nclass LoadIO extends Bundle {\n val mode = Input(UInt(3.W))\n val imm = Input(UInt(12.W))\n val rs1 = Input(UInt(32.W))\n val en = Input(Bool())\n val ready = Output(Bool())\n val data = Output(UInt(32.W))\n val mem = Flipped(new MemoryReaderIO)\n}\n\nclass StoreIO extends Bundle {\n val mode = Input(UInt(3.W))\n val imm = Input(UInt(12.W))\n val rs2 = Input(UInt(32.W))\n val rs1 = Input(UInt(32.W))\n val en = Input(Bool())\n val ready = Output(Bool())\n val mem = Flipped(new MemoryWriterIO)\n}\n\nclass Load extends Module {\n val io = IO(new LoadIO)\n val enable = Module(new Posedge)\n enable.io.in := io.en\n enable.io.re := ~io.mem.vaild\n io.mem.addr := io.rs1 + Utility.extendSign(io.imm)\n io.mem.ren := enable.io.out\n io.ready := io.mem.vaild\n\n", "right_context": "\n io.data := MuxLookup(io.mode(1, 0), 0.U(32.W), Seq(\n 0.U(2.W) -> UNS(8),\n 1.U(2.W) -> UNS(16),\n 2.U(2.W) -> UNS(32),\n 3.U(2.W) -> UNS(32))) // 32bits core treat 64bits insts as 32bits\n}\n\nclass Store extends Module {\n val io = IO(new StoreIO)\n val enable = Module(new Posedge)\n enable.io.in := io.en\n enable.io.re := ~io.mem.vaild\n io.mem.addr := io.rs1 + Utility.extendSign(io.imm)\n io.mem.wen := enable.io.out\n io.mem.data := io.rs2\n io.mem.mode := io.mode\n io.ready := io.mem.vaild\n}\n\nclass LoadStore extends Module {\n val io = IO(new Bundle {\n val inst = Input(UInt(32.W))\n val mode = Input(UInt(4.W))\n val en = Input(Bool())\n val rs3 = Input(UInt(32.W))\n val rs2 = Input(UInt(32.W))\n val rs1 = Input(UInt(32.W))\n val ret = Output(UInt(32.W))\n val rd = Output(UInt(5.W))\n val ready = Output(Bool())\n\n val mem = Flipped(new MemoryIO)\n })\n val load = Module(new Load)\n val store = Module(new Store)\n io.rd := Mux(io.mode(3), 0.U(5.W), io.inst(11, 7))\n\n load.io.imm := io.rs3(11, 0)\n load.io.rs1 := io.rs1\n\n store.io.imm := io.rs3(11, 0)\n store.io.rs2 := io.rs2\n store.io.rs1 := io.rs1\n\n load.io.en := (~io.mode(3)) & io.en\n store.io.en := ( io.mode(3)) & io.en\n\n load.io.mode := io.mode(2, 0)\n store.io.mode := io.mode(2, 0)\n\n io.mem.reader <> load.io.mem\n io.mem.writer <> store.io.mem\n\n io.ret := load.io.data\n io.ready := Mux(io.mode(3), store.io.ready, load.io.ready)\n}\n", "groundtruth": " def UNS(i: Int):UInt = Mux(~io.mode(2), Utility.extendSign(io.mem.data(i-1, 0), 32), io.mem.data(i-1, 0))\n", "crossfile_context": "", "category": "Computation Block", "subcategory": "Mux and Selection Logic", "confidence": 0.85, "category_reason": "Mux selection"} {"task_id": "riscv-self", "path": "riscv-self/src/main/scala/RegFile.scala", "left_context": "package rself\n\nimport chisel3._\n\nclass RegFileReaderIO extends Bundle {\n val raddr1 = Input(UInt(5.W))\n val raddr2 = Input(UInt(5.W))\n val rdata1 = Output(UInt(32.W))\n val rdata2 = Output(UInt(32.W))\n}\n\nclass RegFileWriterIO extends Bundle {\n val wen = Input(Bool())\n val waddr = Input(UInt(5.W))\n val wdata = Input(UInt(32.W))\n}\n\nclass RegFileIO extends Bundle {\n val reader = new RegFileReaderIO\n val writer = new RegFileWriterIO\n}\n\nclass RegFile extends Module {\n val io = IO(new RegFileIO)\n val regs = Mem(32, UInt(32.W))\n io.reader.rdata1 := Mux(io.reader.raddr1.orR, regs(io.reader.raddr1), 0.U)\n io.reader.rdata2 := Mux(io.reader.raddr2.orR, regs(io.reader.raddr2), 0.U)\n", "right_context": "", "groundtruth": " when(io.writer.wen & io.writer.waddr.orR) {\n regs(io.writer.waddr) := io.writer.wdata\n }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "riscv-self", "path": "riscv-self/src/main/scala/SystemOperation.scala", "left_context": "package rself\n\nimport chisel3._\nimport chisel3.util._\n\nclass MemoryOperation extends Module {\n val io = IO(new Bundle {\n", "right_context": "\nclass SystemOperation extends Module {\n val io = IO(new Bundle {\n\n", "groundtruth": " val inst = Input(UInt(32.W))\n })\n // Execute no Operation\n}\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.8, "category_reason": "Input or Output in Bundle/IO context"} {"task_id": "riscv-self", "path": "riscv-self/src/main/scala/Utils.scala", "left_context": "package rself\n\nimport chisel3._\nimport chisel3.util._\n\nobject Utility {\n def extendSign(m: UInt, b: Int = 32): UInt = {\n val extendWire = Wire(SInt(b.W))\n extendWire := m.asSInt\n extendWire.asUInt\n }\n}\n\nclass Posedge extends Module {\n val io = IO(new Bundle {\n", "right_context": "}\n", "groundtruth": " val in = Input(Bool())\n val re = Input(Bool())\n val out = Output(Bool())\n })\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.85, "category_reason": "Input/Output port declarations"} {"task_id": "riscv-self", "path": "riscv-self/src/test/scala/ALUTests.scala", "left_context": "package rself\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.testers._\nimport org.scalatest.FlatSpec\n\nclass ALUTester(alu: => ALU) extends BasicTester with TestUtils {\n val tester = Module(alu)\n val alu_A = TestList()\n val alu_B = TestList()\n val alu_op = TestList()\n val alu_out = TestList()\n for (op <- Constants.ALU; i <- 0 until 10) {\n val (_, opcode) = op\n val (a, b) = (random32(), random32())\n alu_op += opcode; alu_A += a; alu_B += b\n alu_out += calculate(a, b, opcode) // TestUtils::calculate\n }\n alu_A += 0L; alu_B += 0xfece1234L; alu_op += 15; alu_out += 0xfece1234L // test invaild operator\n shuffle(alu_A, alu_B, alu_op, alu_out)\n alu_A += 0L; alu_B += 0xfece1234L; alu_op += 15; alu_out += 0xfece1234L // can not reach last data\n\n val a = interface(alu_A)\n val b = interface(alu_B)\n val p = interface(alu_op, 4)\n val o = interface(alu_out)\n val (cntr, done) = Counter(true.B, o.size)\n tester.io.A := a(cntr)\n tester.io.B := b(cntr)\n tester.io.alu_op := p(cntr)\n\n", "right_context": " printf(\"Counter: %d, Op: %d, A: 0x%x, B: 0x%x, Out: %x ?= %x\\n\",\n cntr, tester.io.alu_op, tester.io.A, tester.io.B, tester.io.out, o(cntr))\n assert(tester.io.out === o(cntr))\n}\n\nclass ALUTests extends FlatSpec {\n \"ALU\" should \"pass\" in {\n assert(TesterDriver execute (() => new ALUTester(new ALU)))\n }\n}\n", "groundtruth": " when(done) { stop(); stop() }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "riscv-self", "path": "riscv-self/src/test/scala/BranchTests.scala", "left_context": "package rself\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.testers._\nimport org.scalatest.FlatSpec\n\nclass BranchTester(brc: => Branch) extends BasicTester with TestUtils {\n val tester = Module(brc)\n val rs1 = TestList()\n val rs2 = TestList()\n val jmty = TestList()\n val disp = TestList()\n val pc = TestList()\n val isJm = TestList()\n val addr = TestList()\n\n for (func <- Constants.BranchCodes; i <- 0 until 10) {\n val (fn, fid) = func\n jmty += fid\n val rrs = (fn match {\n case \"BEQ\" | \"BNE\" => {\n val a = random32()\n if (rnd.nextBoolean()) {\n (a, a)\n } else {\n (a, random32())\n }\n }\n case _ => (random32(), random32())\n })\n rs1 += rrs._1; rs2 += rrs._2\n\n val rdisp = randombits(13)\n disp += rdisp\n\n val cpc = random32()\n val jpc = (cpc + rdisp.toSigned(13)).toUnsigned()\n pc += cpc; addr += jpc\n\n isJm += branchCond(fn, rrs) // TestUtils::branchCond\n }\n shuffle(rs1, rs2, jmty, disp, pc, isJm, addr)\n rs1 += 0; rs2 += 0; jmty += BR_TYPE.BR_EQ.litValue().toLong; disp += 0; pc += 0; isJm += 1; addr += 0 // unreachable test\n\n val brc_cond_rs1 = interface(rs1)\n val brc_cond_rs2 = interface(rs2)\n val brc_cond_type = interface(jmty, 3)\n val brc_jump_disp = interface(disp, 13)\n val brc_jump_pc = interface(pc)\n val brc_out_isJmp = interface(isJm, 1)\n val brc_out_jAddr = interface(addr)\n\n val (cntr, done) = Counter(true.B, brc_jump_pc.size)\n\n tester.io.cond.rs1 := brc_cond_rs1(cntr)\n tester.io.cond.rs2 := brc_cond_rs2(cntr)\n tester.io.cond.br_type := brc_cond_type(cntr)\n tester.io.jump.disp := brc_jump_disp(cntr)\n tester.io.jump.PC := brc_jump_pc(cntr)\n\n", "right_context": " printf(\"Counter: %d, Br: %d, A: %x, B: %x, isJump: %b ?= %b, PC: %x, disp: %x, jumpAddr: %x ?= %x\\n\",\n cntr, tester.io.cond.br_type, tester.io.cond.rs1, tester.io.cond.rs2,\n tester.io.isJmp, brc_out_isJmp(cntr),\n tester.io.jump.PC, tester.io.jump.disp,\n tester.io.jmpAddr, brc_out_jAddr(cntr))\n assert(tester.io.isJmp === brc_out_isJmp(cntr))\n assert(tester.io.jmpAddr === brc_out_jAddr(cntr))\n}\n\nclass BranchTests extends FlatSpec {\n \"Branch\" should \"pass\" in {\n assert(TesterDriver execute (() => new BranchTester(new Branch)))\n }\n}\n", "groundtruth": " when(done) { stop(); stop() }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "riscv-self", "path": "riscv-self/src/test/scala/Constants.scala", "left_context": "// auto generate by python scripts\n\npackage rself\n\nimport chisel3._\n\n", "right_context": " \"SRA\" -> 13L,\n \"OR\" -> 6L,\n \"AND\" -> 7L)\n val Opcode = Map(\n \"LUI\" -> 55L,\n \"AUIPC\" -> 23L,\n \"JAL\" -> 111L,\n \"JALR\" -> 103L,\n \"BRANCH\" -> 99L,\n \"LOAD\" -> 3L,\n \"STORE\" -> 35L,\n \"ITYPE\" -> 19L,\n \"RTYPE\" -> 51L,\n \"MEMORY\" -> 15L,\n \"SYSTEM\" -> 115L)\n val BranchCodes = Map(\n \"BEQ\" -> 0L,\n \"BNE\" -> 1L,\n \"BLT\" -> 4L,\n \"BGE\" -> 5L,\n \"BLTU\" -> 6L,\n \"BGEU\" -> 7L)\n val LoadCodes = Map(\n \"LB\" -> 0L,\n \"LH\" -> 1L,\n \"LW\" -> 2L,\n \"LD\" -> 3L,\n \"LBU\" -> 4L,\n \"LHU\" -> 5L,\n \"LWU\" -> 6L)\n val StoreCodes = Map(\n \"SB\" -> 0L,\n \"SH\" -> 1L,\n \"SW\" -> 2L,\n \"SD\" -> 3L)\n val ControlActs = Map(\n \"ALU\" -> 0L,\n \"BRC\" -> 1L,\n \"LDS\" -> 2L,\n \"FEN\" -> 3L,\n \"SYS\" -> 4L,\n \"LUI\" -> 5L,\n \"AUI\" -> 6L,\n \"JMP\" -> 7L)\n val ImmModes = Map(\n \"R\" -> 0L,\n \"I\" -> 1L,\n \"S\" -> 2L,\n \"U\" -> 3L,\n \"J\" -> 4L,\n \"B\" -> 5L,\n \"Z\" -> 6L)\n}\n\n", "groundtruth": "object Constants {\n val ALU = Map(\n \"ADD\" -> 0L,\n \"SUB\" -> 8L,\n \"SLL\" -> 1L,\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.6, "category_reason": "val binding"} {"task_id": "riscv-self", "path": "riscv-self/src/test/scala/ControlTests.scala", "left_context": "package rself\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.testers._\nimport org.scalatest.FlatSpec\n\nclass ControlTester(ctl: => Control) extends BasicTester with TestUtils {\n val tester = Module(ctl)\n val (ctl_inst, ctl_mode, ctl_sel, ctl_imm) = randomInsts() // TestUtils::randomInsts\n ctl_inst += 127; ctl_mode += 0; ctl_sel += 4; ctl_imm += 6 // invaild instruction\n\n shuffle(ctl_inst, ctl_mode, ctl_sel, ctl_imm)\n ctl_inst += 127; ctl_mode += 0; ctl_sel += 4; ctl_imm += 6 // unreachable test\n\n val inst = interface(ctl_inst)\n val mod = interface(ctl_mode, 4)\n val sel = interface(ctl_sel, 3)\n val imm = interface(ctl_imm, 3)\n val (cntr, done) = Counter(true.B, inst.size)\n tester.io.inst := inst(cntr)\n\n", "right_context": " printf(\"Counter: %d, Inst: %b, mod: %x ?= %x, sel: %x ?= %x, imm: %x ?= %x\\n\",\n cntr, tester.io.inst, tester.io.mode, mod(cntr), tester.io.sel, sel(cntr), tester.io.imm, imm(cntr))\n assert(tester.io.mode === mod(cntr))\n assert(tester.io.sel === sel(cntr))\n assert(tester.io.imm === imm(cntr))\n}\n\nclass ControlTests extends FlatSpec {\n \"Control\" should \"pass\" in {\n assert(TesterDriver execute (() => new ControlTester(new Control)))\n }\n}\n", "groundtruth": " when(done) { stop(); stop() }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "riscv-self", "path": "riscv-self/src/test/scala/DatapathTests.scala", "left_context": "package rself\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.testers._\nimport org.scalatest.FlatSpec\n\nimport scala.io.Source\nimport scala.collection.mutable.ListBuffer\n\nobject PesudoAssemblyTools {\n import Constants._\n def LOAD(c: String, rd: Long, imm: Long, rs1: Long) = IMMTYPE(\"I\", \"LOAD\", rd, rs1, 0, imm, LoadCodes(c), 0)\n def STORE(c: String, rs2: Long, imm: Long, rs1: Long) = IMMTYPE(\"S\", \"STORE\", 0, rs1, rs2, imm, StoreCodes(c), 0)\n def IMMTYPE(immtype: String, op: String = \"Z\", rd: Long = 0, rs1: Long = 0, rs2: Long = 0, rawimm: Long = 0, funct3: Long = 0, funct7: Long = 0) = {\n // reassemble imm number to inst\n // mask = lambda a, b=-1: (1<>').replace('<<0','')\n // makeimm = lambda args: ' ^ '.join([bitreplace(*a) for a in args])\n val imm_length = Map(\n \"R\" -> 0,\n \"I\" -> 12,\n \"S\" -> 12,\n \"U\" -> 32,\n \"J\" -> 21,\n \"B\" -> 13,\n \"Z\" -> 0)\n val imm = rawimm & ((1L< Opcode(op) ^ rd<<7 ^ (funct3&0x7)<<12 ^ rs1<<15 ^ rs2<<20 ^ funct7<<25 ^ (funct3&0x8)<<27\n case \"I\" => Opcode(op) ^ rd<<7 ^ (funct3&0x7)<<12 ^ rs1<<15 ^ (funct3&0x8)<<27 ^ imm<<20\n case \"S\" => Opcode(op) ^ (imm&0x1f)<<7 ^ (funct3&0x7)<<12 ^ rs1<<15 ^ rs2<<20 ^ (imm&0xfe0)<<20\n case \"B\" => Opcode(op) ^ (funct3&0x7)<<12 ^ rs1<<15 ^ rs2<<20 ^ (imm&0x800)>>4 ^ (imm&0x1e)<<7 ^ (imm&0x7e0)<<20 ^ (imm&0x1000)<<19\n case \"U\" => Opcode(op) ^ rd<<7 ^ (imm&0xfffff000)\n case \"J\" => Opcode(op) ^ rd<<7 ^ (imm&0xff000) ^ (imm&0x800)<<9 ^ (imm&0x7fe)<<20 ^ (imm&0x100000)<<11\n case _ => Opcode(op)\n }\n }\n def ITYPE(op: String, rd: Long, rs1: Long, imm: Long) = IMMTYPE(\"I\", \"ITYPE\", rd, rs1, 0, imm, ALU(op), 0)\n def RTYPE(op: String, rd: Long, rs1: Long, rs2: Long) = IMMTYPE(\"R\", \"RTYPE\", rd, rs1, rs2, 0, ALU(op), 0)\n def BRC(op: String, rs1: Long, rs2: Long, imm: Long) = IMMTYPE(\"B\", \"BRANCH\", 0, rs1, rs2, imm, BranchCodes(op), 0)\n def sys = Opcode(\"SYSTEM\")\n}\n\nobject TestBinary {\n def apply(name: String, bin: scala.collection.Iterable[Long], result: Long) = new TestBinary(name, bin.to[Seq], result)\n def apply(name: String, bin: scala.collection.Iterable[Long]) = {\n import PesudoAssemblyTools._\n val newbin = bin.to[Seq] ++ Seq(\n RTYPE(\"XOR\", 1, 0, 0))\n new TestBinary(name, newbin, 0L)\n }\n}\n\nclass TestBinary(name: String, bin: Seq[Long], result: Long) {\n def name(): String = name\n def binary(): Seq[Long] = bin\n def vec() = {\n import PesudoAssemblyTools._\n val newbin = bin ++ Seq(\n STORE(\"SW\", 1, 0, 0),\n Constants.Opcode(\"SYSTEM\"))\n VecInit(newbin.map(_.U(32.W)))\n }\n def res() = result.U(32.W)\n def size() = bin.size + 2\n}\n\nclass DatapathTester(dp: => Datapath, bin: TestBinary) extends BasicTester with TestUtils {\n val tester = Module(dp)\n val mem = Mem(1 << 24, UInt(8.W))\n val runState = RegInit(false.B)\n\n val writeVaild = RegInit(false.B)\n tester.io.dmem.writer.vaild := writeVaild\n val readVaild = RegInit(false.B)\n val daddr = tester.io.dmem.reader.addr\n tester.io.dmem.reader.data := Cat(mem(daddr+3.U), mem(daddr+2.U), mem(daddr+1.U), mem(daddr))\n tester.io.dmem.reader.vaild := readVaild\n val iaddr = tester.io.imem.addr\n tester.io.imem.data := Cat(mem(iaddr+3.U), mem(iaddr+2.U), mem(iaddr+1.U), mem(iaddr))\n tester.io.imem.vaild := runState\n\n val insts = bin.vec()\n val result = bin.res()\n val (cntr, done) = Counter(~runState, bin.size)\n\n val stopper = RegInit(0.U(16.W))\n stopper := stopper + 1.U\n when (stopper > 0x8000.U) {\n printf(\"time too long.\\n\")\n assert(false.B)\n stop(); stop()\n }\n\n when (~runState) {\n // memory ready\n val data = insts(cntr)\n val wiaddr = (cntr << 2.U) + Const.PC_START.U(32.W)\n mem(wiaddr ) := data(7, 0)\n mem(wiaddr + 1.U) := data(15, 8)\n mem(wiaddr + 2.U) := data(23, 16)\n mem(wiaddr + 3.U) := data(31, 24)\n when(done) { runState := true.B }\n } .otherwise {\n when (tester.io.imem.ren & tester.io.imem.vaild) {\n printf(\"INS[%x] ==> %x, iaddr: %x\\n\", iaddr, Cat(mem(iaddr+3.U), mem(iaddr+2.U), mem(iaddr+1.U), mem(iaddr)), iaddr)\n }\n when (tester.io.dmem.writer.wen) {\n // memory write\n val waddr = tester.io.dmem.writer.addr\n val wdata = tester.io.dmem.writer.data\n switch(tester.io.dmem.writer.mode) {\n is (0.U) {\n mem(waddr) := wdata(7, 0)\n printf(\"MEM[%x] <== BYTE %x\\n\", waddr, wdata(7,0))\n }\n is (1.U) {\n mem(waddr ) := wdata(7, 0)\n mem(waddr + 1.U) := wdata(15, 8)\n printf(\"MEM[%x] <== HALF %x\\n\", waddr, wdata(15,0))\n }\n is (2.U) {\n mem(waddr ) := wdata(7, 0)\n mem(waddr + 1.U) := wdata(15, 8)\n mem(waddr + 2.U) := wdata(23, 16)\n mem(waddr + 3.U) := wdata(31, 24)\n printf(\"MEM[%x] <== WORD %x\\n\", waddr, wdata)\n }\n is (3.U) {\n mem(waddr ) := wdata(7, 0)\n mem(waddr + 1.U) := wdata(15, 8)\n mem(waddr + 2.U) := wdata(23, 16)\n mem(waddr + 3.U) := wdata(31, 24)\n printf(\"MEM[%x] <== WORD %x\\n\", waddr, wdata)\n }\n }\n writeVaild := true.B\n } .otherwise {\n writeVaild := false.B\n }\n when (tester.io.dmem.reader.ren) {\n printf(\"MEM[%x] ==> %x\\n\", daddr, Cat(mem(daddr+3.U), mem(daddr+2.U), mem(daddr+1.U), mem(daddr)))\n readVaild := true.B\n } .otherwise {\n readVaild := false.B\n }\n when(tester.io.sys) {\n printf(\"RESULT %x ?= %x\\n\", Cat(mem(3), mem(2), mem(1), mem(0)), result)\n assert(Cat(mem(3), mem(2), mem(1), mem(0)) === result)\n stop(); stop()\n }\n }\n}\n\nobject TestBinaryBundles {\n import PesudoAssemblyTools._\n\n val first = TestBinary(\"Hello\", Seq(\n ITYPE(\"XOR\", 2, 0, 0x2f), // r2 = 0x2f\n ITYPE(\"XOR\", 3, 0, 0x1c), // r3 = 0x1c\n RTYPE(\"ADD\", 2, 2, 3), // r2 = r2 + r3\n ITYPE(\"XOR\", 1, 2, 0x14b) // r1(ret) = r2 ^ 0x14b ; == 0x100\n ), 0x100)\n\n val hundredsum = TestBinary(\"Hundred-Sum\", Seq(\n RTYPE(\"XOR\", 2, 0, 0), // r2(add) = 0\n RTYPE(\"XOR\", 3, 0, 0), // r3(sum) = 0\n ITYPE(\"XOR\", 4, 0, 100), // r4 = 100\n ITYPE(\"ADD\", 2, 2, 1), // r2 = r2 + 1 ; label\n RTYPE(\"ADD\", 3, 3, 2), // r3 = r3 + r2\n BRC(\"BLT\", 2, 4, -(2L<<2)), // jump to label if r2 < r4\n RTYPE(\"XOR\", 1, 3, 0) // r1(ret) = r3\n ), 5050)\n\n val writeback = TestBinary(\"Write-Back\", Seq(\n RTYPE(\"XOR\", 2, 0, 0),\n ITYPE(\"ADD\", 2, 2, 1),\n ITYPE(\"ADD\", 2, 2, 2),\n ITYPE(\"ADD\", 2, 2, 3),\n ITYPE(\"ADD\", 2, 2, 4),\n RTYPE(\"XOR\", 1, 2, 0)\n ), 10)\n\n val collection = Array(\n first, writeback,\n TestBinary(\"Load-Store\", Seq(\n RTYPE(\"XOR\", 4, 0, 0), // r4 = 0\n ITYPE(\"XOR\", 2, 0, -1), // r2 = 0xffffffff\n STORE(\"SW\", 2, 0, 0), // SW x2, 0(0)\n LOAD( \"LBU\", 3, 0, 0), // LB x3, 0(0)\n ITYPE(\"SLL\", 4, 4, 1), // r4 <<= 1\n ITYPE(\"XOR\", 5, 0, 0xff), // r5 = 0xff\n BRC( \"BEQ\", 3, 5, (2L<<2)), // jump next code if r3 == r5\n ITYPE(\"ADD\", 4, 4, 1) // r4 += 1\n ), 0),\n hundredsum\n )\n}\n\nclass DatapathTests extends FlatSpec {\n TestBinaryBundles.collection foreach { test =>\n", "right_context": " // Console.print(s\"${test.name}:\\n\")\n // test.binary foreach { e =>\n // Console.printf (\" %08x\\n\", e)\n // }\n assert(TesterDriver execute (() => new DatapathTester(new Datapath, test)))\n }\n }\n}\n", "groundtruth": " \"DataPath\" should s\"pass ${test.name}\" in {\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "riscv-self", "path": "riscv-self/src/test/scala/ExecuteTests.scala", "left_context": "package rself\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.testers._\nimport org.scalatest.FlatSpec\n\ntrait ExecuteUtils extends TestUtils {\n val regData = (0 until 32).map((i) => if (i != 0) random32() else 0L)\n def instResults(cs: List4): List4 = {\n val (inst, mode, sel, imm) = cs\n val (data, rd, npc, jmp) = TestList.List4()\n val size = inst.size\n import Constants._\n val Act = ControlActs.map(_.swap)\n val Imm = ImmModes.map(_.swap)\n for (i <- 0 until size) {\n def B(hi: Int, lo: Int = -1) = {\n val low = if (lo == -1) {hi} else {lo}\n (inst(i) & ((1<<(hi+1)) - (1<> low\n }\n val rs3 = immData(inst(i), Imm(imm(i)))\n val rs2 = regData(B(24, 20).toInt)\n val rs1 = regData(B(19, 15).toInt)\n val rd0 = B(11, 7)\n // TODO: make assertion results\n }\n return (data, rd, npc, jmp)\n }\n}\n\nclass ExecuteTester(exe: => Execute) extends BasicTester with ExecuteUtils {\n val tester = Module(exe)\n val (ctl_inst, ctl_mode, ctl_sel, ctl_imm) = randomInsts() // TestUtils::randomInsts\n ctl_inst += 127; ctl_mode += 0; ctl_sel += 4; ctl_imm += 6 // invaild instruction\n\n val inst = interface(ctl_inst)\n val regs = interface(regData)\n val pcReg = RegInit(Const.PC_START.U(32.W))\n pcReg := pcReg + 1.U\n val (cntr, done) = Counter(true.B, inst.size)\n tester.io.en := true.B\n tester.io.pc := pcReg\n tester.io.inst := inst(cntr)\n tester.io.reg.rdata1 := regs(tester.io.reg.raddr1)\n tester.io.reg.rdata2 := regs(tester.io.reg.raddr2)\n tester.io.mem.writer.vaild := true.B\n tester.io.mem.reader.vaild := true.B\n tester.io.mem.reader.data := 0.U\n\n", "right_context": " printf(\"Counter: %d, Inst: %b, isJump: %b, nextPC: %x, rd: %d, data: %x, sys:%b\\n\",\n cntr, tester.io.inst, tester.io.jmp, tester.io.npc, tester.io.rd, tester.io.data, tester.io.sys)\n // TODO: no assertion\n}\n\nclass ExecuteTests extends FlatSpec {\n \"Execute\" should \"pass\" in {\n assert(TesterDriver execute (() => new ExecuteTester(new Execute)))\n }\n}\n", "groundtruth": " when(done) { stop(); stop() }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "riscv-self", "path": "riscv-self/src/test/scala/ImmGenTests.scala", "left_context": "package rself\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.testers._\nimport org.scalatest.FlatSpec\n\nimport IMM_MODE._\n\nclass ImmGenTester(img: => ImmGen) extends BasicTester with TestUtils {\n val tester = Module(img)\n import scala.collection.mutable.ListBuffer\n val img_inst = TestList()\n val img_mode = TestList()\n val img_val = TestList()\n for (mod <- Constants.ImmModes; i <- 0 until 15) {\n val (modstr, modop) = mod\n val inst = random32()\n img_inst += inst\n img_mode += modop\n img_val += immData(inst, modstr) // TestUtils::immData\n }\n\n shuffle(img_inst, img_mode, img_val)\n img_inst += 0; img_mode += IMM_Z.litValue().toLong; img_val += 0 // unreachable test\n\n val inst = interface(img_inst)\n val mode = interface(img_mode, 3)\n val value = interface(img_val)\n val (cntr, done) = Counter(true.B, inst.size)\n tester.io.inst := inst(cntr)\n tester.io.mode := mode(cntr)\n\n", "right_context": " printf(\"Counter: %d, Inst: %b, mod: %x, value: %x ?= %x\\n\",\n cntr, tester.io.inst, tester.io.mode, tester.io.value, value(cntr))\n assert(tester.io.value === value(cntr))\n}\n\nclass ImmGenTests extends FlatSpec {\n \"ImmGen\" should \"pass\" in {\n assert(TesterDriver execute (() => new ImmGenTester(new ImmGen)))\n }\n}\n", "groundtruth": " when(done) { stop(); stop() }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "riscv-self", "path": "riscv-self/src/test/scala/JumpTests.scala", "left_context": "package rself\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.testers._\nimport org.scalatest.FlatSpec\n\n// This test file is for src/main/scala/Jump.scala\n// with modules `Jump' `AddUpperImmPC' and `LoadUpperImm'\n\nclass JumpOnlyTester(jmp: => Jump) extends BasicTester with TestUtils {\n val tester = Module(jmp)\n val mode = TestList()\n val pc = TestList()\n val imm = TestList()\n val base = TestList()\n val ret = TestList()\n val addr = TestList()\n for (m <- Array(0, 1); i <- 0 until 10) {\n mode += m\n val (r_pc, r_base) = (random32(), random32())\n val bits = (m match {\n case 0 => 12\n case 1 => 21\n })\n val vaild_imm = randombits(bits).toSigned(bits)\n val redundancy_imm = randombits(32-bits)\n imm += (vaild_imm.toUnsigned(bits) + (redundancy_imm< AddUpperImmPC) extends BasicTester with TestUtils {\n val tester = Module(aui)\n val pc = TestList()\n val imm = TestList()\n val ret = TestList()\n for (i <- 0 until 10) {\n val r = (random32(), random32())\n pc += r._1; imm += r._2; ret += (r._1 + r._2).toUnsigned()\n }\n shuffle(pc, imm, ret)\n pc += 0; imm += 0; ret += 0 // unreachable test\n\n val p = interface(pc)\n val i = interface(imm)\n val r = interface(ret)\n val (cntr, done) = Counter(true.B, r.size)\n tester.io.pc := p(cntr)\n tester.io.imm := i(cntr)\n\n when(done) { stop(); stop() }\n printf(\"Counter: %d, PC: %x, IMM: %x, ret: %x ?= %x\\n\",\n cntr, tester.io.pc, tester.io.imm, tester.io.ret, r(cntr))\n assert(tester.io.ret === r(cntr))\n}\n\nclass LUITester(lui: => LoadUpperImm) extends BasicTester with TestUtils {\n val tester = Module(lui)\n val pc = TestList()\n val imm = TestList()\n val ret = TestList()\n for (i <- 0 until 10) {\n val r = random32()\n imm += r; ret += r\n }\n shuffle(imm, ret)\n imm += 0; ret += 0 // unreachable test\n\n val i = interface(imm)\n val r = interface(ret)\n val (cntr, done) = Counter(true.B, r.size)\n tester.io.imm := i(cntr)\n\n", "right_context": " printf(\"Counter: %d, IMM: %x, ret: %x ?= %x\\n\",\n cntr, tester.io.imm, tester.io.ret, r(cntr))\n assert(tester.io.ret === r(cntr))\n}\n\nclass JumpTests extends FlatSpec {\n \"Jump\" should \"pass\" in {\n assert(TesterDriver execute (() => new JumpOnlyTester(new Jump)))\n }\n \"AUIPC\" should \"pass\" in {\n assert(TesterDriver execute (() => new AUIPCTester(new AddUpperImmPC)))\n }\n \"LUI\" should \"pass\" in {\n assert(TesterDriver execute (() => new LUITester(new LoadUpperImm)))\n }\n}\n", "groundtruth": " when(done) { stop(); stop() }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "riscv-self", "path": "riscv-self/src/test/scala/LoadStoreTests.scala", "left_context": "package rself\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.testers._\nimport org.scalatest.FlatSpec\n\n// simple implementation for Memory, only for test\nclass Memory extends Module {\n val io = IO(new MemoryIO)\n}\n\nclass PosedgeTester(p: => Posedge) extends BasicTester with TestUtils {\n val tester = Module(p)\n\n val ser = TestList()\n val res = TestList()\n val out = TestList()\n for (i <- 0 until 100) {\n ser += 1; res += 1; out += 1\n for (j <- 0L until randombits(3)) {\n ser += 0; res += 1; out += 1\n }\n res += 0; ser += 0; out += 0\n for (j <- 0L until randombits(2)) {\n ser += 0; res += 1; out += 0\n }\n }\n\n val o = interface(ser, 1)\n val e = interface(res, 1)\n val t = interface(out, 1)\n val (cntr, done) = Counter(true.B, o.size)\n", "right_context": " tester.io.in := o(cntr)\n tester.io.re := e(cntr)\n assert(tester.io.out === t(cntr))\n // printf(\"%d \", tester.io.out)\n}\n\nobject LoadStoreTesterProperty {\n type LoadStoreTesterProperty = Int\n val LoadTest = 0\n val StoreTest = 1\n}\nimport LoadStoreTesterProperty._\n\nabstract class LoadStoreTester(ls: => LoadStore)(implicit property: LoadStoreTesterProperty) extends BasicTester with TestUtils {\n val tester = Module(ls)\n\n val _time = TestList()\n val _mode = TestList()\n val _imm = TestList()\n val _rs1 = TestList()\n val _rs2 = TestList()\n val _rd = TestList()\n val _cal = TestList()\n val _mem = TestList()\n val _ret = TestList()\n\n for (i <- 0 until 100) {\n val r = (random32(), randombits(12))\n _time += randombits(3)\n _rs1 += r._1\n _imm += r._2\n _cal += (r._1 + r._2.toSigned(12)).toUnsigned()\n val rmem = random32()\n _mem += rmem\n val mod = rnd.nextInt(3)\n property match {\n case LoadTest => {\n val signed = randombits(1)\n _mode += (0 << 3) + (signed << 2) + mod\n _rd += randombits(5)\n _rs2 += 0\n _ret += (if (signed == 0) rmem.toSigned(1 << (3+mod)) else rmem.toUnsigned(1 << (3+mod))).toUnsigned()\n }\n case StoreTest => {\n _mode += (1 << 3) + mod\n _rd += 0\n _rs2 += random32()\n _ret += 0\n }\n }\n }\n\n val time = interface(_time, 8)\n val mode = interface(_mode, 4)\n val rs3 = interface(_imm)\n val rs2 = interface(_rs2)\n val rs1 = interface(_rs1)\n val rd = interface(_rd, 5)\n val inst = interface(_rd map (x => x<<7))\n\n val mem = interface(_mem)\n val ret = interface(_ret)\n val pos = interface(_cal)\n\n val counter = RegInit(0.U(16.W))\n val timecounter = RegInit(0.U(8.W))\n\n // tester.io.mem.reader.addr := DontCare\n // tester.io.mem.reader.ren := DontCare\n // tester.io.mem.writer.addr := DontCare\n // tester.io.mem.writer.mode := DontCare\n // tester.io.mem.writer.wen := DontCare\n // tester.io.mem.writer.data := DontCare\n\n tester.io.mode := mode(counter)\n tester.io.inst := inst(counter)\n tester.io.rs3 := rs3(counter)\n tester.io.rs2 := rs2(counter)\n tester.io.rs1 := rs1(counter)\n\n val vaild = WireInit(false.B)\n val rdata = WireInit(0.U(32.W))\n val enabl = WireInit(false.B)\n\n val retmem = Wire(UInt(32.W))\n val nowmem = Wire(UInt(32.W))\n retmem := ret(counter)\n nowmem := mem(counter)\n\n property match {\n case LoadTest => {\n tester.io.mem.writer.vaild := false.B\n tester.io.mem.reader.vaild := vaild\n tester.io.mem.reader.data := rdata\n }\n case StoreTest => {\n tester.io.mem.reader.vaild := false.B\n tester.io.mem.writer.vaild := vaild\n tester.io.mem.reader.data := 0.U\n }\n }\n tester.io.en := enabl\n\n val stopper = RegInit(0.U(16.W))\n stopper := stopper + 1.U\n when (stopper > 0x8000.U) { stop(); stop() }\n\n when (counter >= time.size.U) { stop(); stop() }\n\n when (timecounter >= time(counter)) {\n vaild := true.B\n rdata := mem(counter)\n printf(\"Counter: %d, TimeReturn, Wait: %d ?= %d\\n\",\n counter, timecounter, time(counter))\n } .otherwise {\n vaild := false.B\n }\n\n when ((timecounter === 0.U) && (time(counter) =/= 0.U)) {\n printf(\"Counter: %d, Enable, Wait: %d, rs3: %x, rs2: %x, rs1: %x => rd: %d\\n\",\n counter, time(counter), rs3(counter), rs2(counter), rs1(counter), rd(counter))\n enabl := true.B\n } .elsewhen (time(counter) === 0.U) {\n printf(\"Counter: %d, Disable\\n\", counter)\n enabl := false.B\n counter := counter + 1.U\n } .otherwise {\n enabl := false.B\n }\n\n when (tester.io.mem.reader.ren || tester.io.mem.writer.wen) {\n timecounter := timecounter + 1.U\n when (tester.io.mem.reader.ren) {\n printf(\"Counter: %d, TimeCounter: %d, Addr: %x ?= %x\\n\", counter, timecounter, tester.io.mem.reader.addr, pos(counter))\n assert(tester.io.mem.reader.addr === pos(counter))\n } .elsewhen (tester.io.mem.writer.wen) {\n printf(\"Counter: %d, TimeCounter: %d, Addr: %x ?= %x, Data: %x ?= %x\\n\",\n counter, timecounter, tester.io.mem.writer.addr, pos(counter), tester.io.mem.writer.data, rs2(counter))\n assert(tester.io.mem.writer.addr === pos(counter))\n assert(tester.io.mem.writer.data === rs2(counter))\n }\n } .otherwise {\n timecounter := 0.U\n }\n\n when (tester.io.ready) {\n when (~tester.io.mode(3)) {\n // Load Ready\n printf(\"Counter: %d, Load Ready, Mod: %d %d, Data: %x ?= %x(%x)\\n\",\n counter, tester.io.mode(2), tester.io.mode(1, 0), tester.io.ret, retmem, nowmem)\n assert(timecounter === time(counter))\n assert(retmem === tester.io.ret)\n assert(tester.io.rd === rd(counter))\n } .otherwise {\n printf(\"Counter: %d, StoreReady, Mod: %d\\n\",\n counter, tester.io.mode(2, 0))\n assert(timecounter === time(counter))\n assert(tester.io.mem.writer.mode === tester.io.mode(1, 0))\n assert(tester.io.rd === 0.U)\n }\n counter := counter + 1.U\n }\n}\n\nclass LoadTester (ls: => LoadStore) extends LoadStoreTester(ls)(LoadTest)\n\nclass StoreTester(ls: => LoadStore) extends LoadStoreTester(ls)(StoreTest)\n\nclass LoadStoreTests extends FlatSpec {\n \"Posedge\" should \"pass\" in {\n assert(TesterDriver execute (() => new PosedgeTester(new Posedge)))\n }\n \"Load\" should \"pass\" in {\n assert(TesterDriver execute (() => new LoadTester(new LoadStore)))\n }\n \"Store\" should \"pass\" in {\n assert(TesterDriver execute (() => new StoreTester(new LoadStore)))\n }\n}\n", "groundtruth": " when(done) { printf(\"\\n\"); stop(); stop() }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "riscv-self", "path": "riscv-self/src/test/scala/TestUtils.scala", "left_context": "package rself\n\nimport chisel3._\n\ntrait TestUtils {\n val rnd = new scala.util.Random(System.currentTimeMillis)\n\n type TestList = scala.collection.mutable.ListBuffer[Long]\n object TestList {\n import scala.collection.mutable.ListBuffer\n def apply(): ListBuffer[Long] = {\n val ref: ListBuffer[Long] = ListBuffer()\n ref\n }\n def List4() = (TestList(), TestList(), TestList(), TestList())\n }\n import scala.collection.mutable.ListBuffer\n\n def randombits(bl: Int) = {rnd.nextLong() & ((1L<\n appendEle((opcode ^ randombits(5)<<7 ^ randombits(20)<<12), 0, ACT.LUI, IMM_U)\n case \"AUIPC\" =>\n appendEle((opcode ^ randombits(5)<<7 ^ randombits(20)<<12), 0, ACT.AUI, IMM_U)\n case \"JAL\" =>\n appendEle((opcode ^ randombits(5)<<7 ^ randombits(20)<<12), 1, ACT.JMP, IMM_J)\n case \"JALR\" =>\n appendEle((opcode ^ randombits(5)<<7 ^ randombits(5)<<15 ^ randombits(12)<<20),\n 0, ACT.JMP, IMM_I)\n case \"BRANCH\" => {\n for (bfunc <- Constants.BranchCodes) {\n val (bfs, bfmode) = bfunc\n appendEle((opcode ^ randombits(5)<<7 ^ bfmode<<12 ^ randombits(5)<<15 ^ randombits(5)<<20 ^ randombits(7)<<25),\n bfmode, ACT.BRC, IMM_B)\n }\n }\n case \"LOAD\" => {\n for (lfunc <- Constants.LoadCodes) {\n val (lfs, lfmode) = lfunc\n appendEle((opcode ^ randombits(5)<<7 ^ lfmode<<12 ^ randombits(5)<<15 ^ randombits(12)<<20),\n lfmode, ACT.LDS, IMM_I)\n }\n }\n case \"STORE\" => {\n for (sfunc <- Constants.LoadCodes) {\n val (sfs, sfmode) = sfunc\n appendEle((opcode ^ randombits(5)<<7 ^ sfmode<<12 ^ randombits(5)<<15 ^ randombits(5)<<20 ^ randombits(7)<<25),\n 8 ^ sfmode, ACT.LDS, IMM_S)\n }\n }\n case \"ITYPE\" => {\n for (alufunc <- Constants.ALU) {\n var (alstr, alumode) = alufunc\n if (alstr == \"SUB\") {\n alstr = \"ADD\"\n alumode = alumode & 7\n }\n val alcode = alumode & 7\n val hicode = alumode >> 3\n val imm = if ((alcode & 3) == 1) {\n hicode<<10 ^ randombits(5)\n } else {\n randombits(12)\n }\n appendEle((opcode ^ randombits(5)<<7 ^ alcode<<12 ^ randombits(5)<<15 ^ imm<<20),\n alumode, ACT.ALU, IMM_I)\n }\n }\n case \"RTYPE\" => {\n for (alufunc <- Constants.ALU) {\n val (alstr, alumode) = alufunc\n val alcode = alumode & 7\n val hicode = alumode >> 3\n appendEle((opcode ^ randombits(5)<<7 ^ alcode<<12 ^ randombits(5)<<15 ^ randombits(5)<<20 ^ hicode<<30),\n alumode, ACT.ALU, IMM_R)\n }\n }\n case \"MEMORY\" => {\n for (i <- 0 until 2) {\n appendEle((opcode ^ i<<12), 0, ACT.FEN, IMM_Z)\n }\n }\n case \"SYSTEM\" => {\n for (i <- 0 until 2) {\n appendEle((opcode ^ i<<20), 0, ACT.SYS, IMM_Z)\n }\n }\n case _ =>\n }\n }\n return (ctl_inst, ctl_mode, ctl_sel, ctl_imm)\n }\n\n def immData(inst: Long, mode: String): Long = {\n def B(hi: Int, lo: Int = -1) = {\n", "right_context": " (inst & ((1<<(hi+1)) - (1<> low\n }\n return (mode match {\n // operator `<<' higher than `^'\n case \"R\" => 0\n case \"I\" => B(31, 20)\n case \"S\" => B(31, 25)<<5 ^ B(11, 7)\n case \"B\" => B(31)<<12 ^ B(7)<<11 ^ B(30, 25)<<5 ^ B(11, 8)<<1\n case \"J\" => B(31)<<20 ^ B(19, 12)<<12 ^ B(20)<<11 ^ B(30, 21)<<1\n case \"U\" => B(31, 12)<<12\n case \"Z\" => 0\n case _ => 0\n })\n }\n\n def calculate(a: Long, b: Long, mod: Long): Long = {\n val shamt = b % (1<<5)\n val opstr = Constants.ALU.toMap.map(_.swap).get(mod).get\n return (opstr match {\n case \"ADD\" => a + b\n case \"SUB\" => a - b\n case \"XOR\" => a ^ b\n case \"AND\" => a & b\n case \"OR\" => a | b\n case \"SLT\" => if (a.toInt < b.toInt) {1L} else {0L}\n case \"SLTU\"=> if (a < b) {1L} else {0L}\n case \"SLL\" => a << shamt\n case \"SRL\" => a >> shamt\n case \"SRA\" => (a.toInt >> shamt).toLong\n case _ => 0xffffffffL\n }).toUnsigned()\n }\n\n def branchCond(fn: String, rrs: Tuple2[Long, Long]): Long = (if (fn match {\n case \"BEQ\" => rrs._1 == rrs._2\n case \"BNE\" => rrs._1 != rrs._2\n case \"BLT\" => rrs._1.toInt < rrs._2.toInt\n case \"BGE\" => rrs._1.toInt >= rrs._2.toInt\n case \"BLTU\" => rrs._1 < rrs._2\n case \"BGEU\" => rrs._1 >= rrs._2\n }) {1L} else {0L})\n}\n", "groundtruth": " val low = if (lo == -1) {hi} else {lo}\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.6, "category_reason": "val binding"} {"task_id": "Bossa", "path": "Bossa/generators/chipyard/src/main/scala/ChipTop.scala", "left_context": "package chipyard\n\nimport chisel3._\n\nimport scala.collection.mutable.{ArrayBuffer}\n\nimport freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockSinkParameters, ClockSinkNode, ClockGroup}\nimport freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey}\nimport freechips.rocketchip.config.{Parameters, Field}\nimport freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike, BindingScope}\nimport freechips.rocketchip.util.{ResetCatchAndSync}\nimport chipyard.iobinders._\n\nimport barstools.iocell.chisel._\n\n", "right_context": "\ntrait HasReferenceClockFreq {\n def refClockFreqMHz: Double\n}\n\n/**\n * The base class used for building chips. This constructor instantiates a module specified by the BuildSystem parameter,\n * named \"system\", which is an instance of DigitalTop by default. The diplomatic clocks of System, as well as its implicit clock,\n * is aggregated into the clockGroupNode. The parameterized functions controlled by ClockingSchemeKey and GlobalResetSchemeKey\n * drive clock and reset generation\n */\n\nclass ChipTop(implicit p: Parameters) extends LazyModule with BindingScope\n with HasTestHarnessFunctions with HasReferenceClockFreq with HasIOBinders {\n // The system module specified by BuildSystem\n lazy val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName(\"system\")\n\n // The implicitClockSinkNode provides the implicit clock and reset for the system (connected by clocking scheme)\n val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some(\"implicit_clock\"))))\n\n // Generate Clocks and Reset\n val mvRefClkFreq = p(ClockingSchemeKey)(this)\n def refClockFreqMHz: Double = mvRefClkFreq.getWrappedValue\n\n // NOTE: Making this a LazyRawModule is moderately dangerous, as anonymous children\n // of ChipTop (ex: ClockGroup) do not receive clock or reset.\n // However. anonymous children of ChipTop should not need an implicit Clock or Reset\n // anyways, they probably need to be explicitly clocked.\n lazy val module: LazyModuleImpLike = new LazyRawModuleImp(this) {\n // These become the implicit clock and reset to the System\n val implicit_clock = implicitClockSinkNode.in.head._1.clock\n val implicit_reset = implicitClockSinkNode.in.head._1.reset\n\n // Connect the implicit clock/reset, if present\n lazySystem.module match { case l: LazyModuleImp => {\n l.clock := implicit_clock\n l.reset := implicit_reset\n }}\n }\n}\n\n", "groundtruth": "case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) => new DigitalTop()(p))\n", "crossfile_context": "", "category": "Design Structure", "subcategory": "Parameterization and Configuration", "confidence": 0.7, "category_reason": "Config Field definition"} {"task_id": "Bossa", "path": "Bossa/generators/chipyard/src/main/scala/Clocks.scala", "left_context": "package chipyard\n\nimport chisel3._\n\nimport scala.collection.mutable.{ArrayBuffer}\n\nimport freechips.rocketchip.prci._\nimport freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey, InstantiatesTiles}\nimport freechips.rocketchip.config.{Parameters, Field, Config}\nimport freechips.rocketchip.diplomacy.{ModuleValue, OutwardNodeHandle, InModuleBody, LazyModule}\nimport freechips.rocketchip.util.{ResetCatchAndSync}\n\nimport barstools.iocell.chisel._\nimport testchipip.{TLTileResetCtrl}\n\nimport chipyard.clocking._\nimport chipyard.iobinders._\n\n/**\n * A simple reset implementation that punches out reset ports\n * for standard Module classes. The ChipTop reset pin is Async.\n * Synchronization is performed in the ClockGroupResetSynchronizer\n */\nobject GenerateReset {\n def apply(chiptop: ChipTop, clock: Clock): Reset = {\n implicit val p = chiptop.p\n // this needs directionality so generateIOFromSignal works\n val async_reset_wire = Wire(Input(AsyncReset()))\n val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(async_reset_wire, \"reset\", p(IOCellKey),\n abstractResetAsAsync = true)\n\n chiptop.iocells ++= resetIOCell\n chiptop.harnessFunctions += ((th: HasHarnessSignalReferences) => {\n reset_io := th.dutReset\n Nil\n })\n async_reset_wire\n }\n}\n\n\ncase object ClockingSchemeKey extends Field[ChipTop => ModuleValue[Double]](ClockingSchemeGenerators.dividerOnlyClockGenerator)\n/*\n * This is a Seq of assignment functions, that accept a clock name and return an optional frequency.\n * Functions that appear later in this seq have higher precedence that earlier ones.\n * If no function returns a non-empty value, the value specified in\n * [[DefaultClockFrequencyKey]] will be used.\n */\ncase object ClockFrequencyAssignersKey extends Field[Seq[(String) => Option[Double]]](Seq.empty)\ncase object DefaultClockFrequencyKey extends Field[Double]()\n\nclass ClockNameMatchesAssignment(name: String, fMHz: Double) extends Config((site, here, up) => {\n case ClockFrequencyAssignersKey => up(ClockFrequencyAssignersKey, site) ++\n Seq((cName: String) => if (cName == name) Some(fMHz) else None)\n})\n\nclass ClockNameContainsAssignment(name: String, fMHz: Double) extends Config((site, here, up) => {\n case ClockFrequencyAssignersKey => up(ClockFrequencyAssignersKey, site) ++\n", "right_context": "})\n\nobject ClockingSchemeGenerators {\n val dividerOnlyClockGenerator: ChipTop => ModuleValue[Double] = { chiptop =>\n implicit val p = chiptop.p\n\n // Requires existence of undriven asyncClockGroups in subsystem\n val systemAsyncClockGroup = chiptop.lazySystem match {\n case l: BaseSubsystem if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) =>\n l.asyncClockGroupsNode\n }\n\n // Add a control register for each tile's reset\n val resetSetter = chiptop.lazySystem match {\n case sys: BaseSubsystem with InstantiatesTiles => Some(TLTileResetCtrl(sys))\n case _ => None\n }\n val resetSetterResetProvider = resetSetter.map(_.tileResetProviderNode).getOrElse(ClockGroupEphemeralNode())\n\n val aggregator = LazyModule(new ClockGroupAggregator(\"allClocks\")).node\n // provides the implicit clock to the system\n (chiptop.implicitClockSinkNode\n := ClockGroup()\n := aggregator)\n // provides the system clock (ex. the bus clocks)\n (systemAsyncClockGroup\n :*= ClockGroupNamePrefixer()\n :*= aggregator)\n\n val referenceClockSource = ClockSourceNode(Seq(ClockSourceParameters()))\n val dividerOnlyClkGenerator = LazyModule(new DividerOnlyClockGenerator(\"buildTopClockGenerator\"))\n // provides all the divided clocks (from the top-level clock)\n (aggregator\n := ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey), p(DefaultClockFrequencyKey))\n := ClockGroupResetSynchronizer()\n := resetSetterResetProvider\n := dividerOnlyClkGenerator.node\n := referenceClockSource)\n\n val asyncResetBroadcast = FixedClockBroadcast(None)\n resetSetter.foreach(_.asyncResetSinkNode := asyncResetBroadcast)\n val asyncResetSource = ClockSourceNode(Seq(ClockSourceParameters()))\n asyncResetBroadcast := asyncResetSource\n\n InModuleBody {\n val clock_wire = Wire(Input(Clock()))\n val reset_wire = GenerateReset(chiptop, clock_wire)\n val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, \"clock\", p(IOCellKey))\n chiptop.iocells ++= clockIOCell\n\n referenceClockSource.out.unzip._1.map { o =>\n o.clock := clock_wire\n o.reset := reset_wire\n }\n\n asyncResetSource.out.unzip._1.map { o =>\n o.clock := false.B.asClock // async reset broadcast network does not provide a clock\n o.reset := reset_wire\n }\n\n chiptop.harnessFunctions += ((th: HasHarnessSignalReferences) => {\n clock_io := th.buildtopClock\n Nil })\n\n // return the reference frequency\n dividerOnlyClkGenerator.module.referenceFreq\n }\n }\n}\n", "groundtruth": " Seq((cName: String) => if (cName.contains(name)) Some(fMHz) else None)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "Bossa", "path": "Bossa/generators/chipyard/src/main/scala/ConfigFragments.scala", "left_context": "package chipyard.config\n\nimport scala.util.matching.Regex\nimport chisel3._\nimport chisel3.util.{log2Up}\n\nimport freechips.rocketchip.config.{Field, Parameters, Config}\nimport freechips.rocketchip.subsystem._\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.devices.tilelink.{BootROMLocated}\nimport freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI}\nimport freechips.rocketchip.groundtest.{GroundTestSubsystem}\nimport freechips.rocketchip.tile._\nimport freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams}\nimport freechips.rocketchip.tilelink.{HasTLBusParams}\nimport freechips.rocketchip.util.{AsyncResetReg, Symmetric}\nimport freechips.rocketchip.prci._\nimport freechips.rocketchip.stage.phases.TargetDirKey\n\nimport testchipip._\n\nimport boom.common.{BoomTileAttachParams}\n\nimport sifive.blocks.devices.gpio._\nimport sifive.blocks.devices.uart._\nimport sifive.blocks.devices.spi._\n\nimport chipyard._\n\n// -----------------------\n// Common Config Fragments\n// -----------------------\n\nclass WithBootROM extends Config((site, here, up) => {\n", "right_context": "})\n\n// DOC include start: gpio config fragment\nclass WithGPIO extends Config((site, here, up) => {\n case PeripheryGPIOKey => Seq(\n GPIOParams(address = 0x10012000, width = 4, includeIOF = false))\n})\n// DOC include end: gpio config fragment\n\nclass WithUART(baudrate: BigInt = 115200) extends Config((site, here, up) => {\n case PeripheryUARTKey => Seq(\n UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate))\n})\n\nclass WithSPIFlash(size: BigInt = 0x10000000) extends Config((site, here, up) => {\n // Note: the default size matches freedom with the addresses below\n case PeripherySPIFlashKey => Seq(\n SPIFlashParams(rAddress = 0x10040000, fAddress = 0x20000000, fSize = size))\n})\n\nclass WithL2TLBs(entries: Int) extends Config((site, here, up) => {\n case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {\n case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(\n core = tp.tileParams.core.copy(nL2TLBEntries = entries)))\n case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(\n core = tp.tileParams.core.copy(nL2TLBEntries = entries)))\n case other => other\n }\n})\n\n/**\n * Map from a hartId to a particular RoCC accelerator\n */\ncase object MultiRoCCKey extends Field[Map[Int, Seq[Parameters => LazyRoCC]]](Map.empty[Int, Seq[Parameters => LazyRoCC]])\n\n/**\n * Config fragment to enable different RoCCs based on the hartId\n */\nclass WithMultiRoCC extends Config((site, here, up) => {\n case BuildRoCC => site(MultiRoCCKey).getOrElse(site(TileKey).hartId, Nil)\n})\n\n/**\n * Assigns what was previously in the BuildRoCC key to specific harts with MultiRoCCKey\n * Must be paired with WithMultiRoCC\n */\nclass WithMultiRoCCFromBuildRoCC(harts: Int*) extends Config((site, here, up) => {\n case BuildRoCC => Nil\n case MultiRoCCKey => up(MultiRoCCKey, site) ++ harts.distinct.map { i =>\n (i -> up(BuildRoCC, site))\n }\n})\n\nclass WithTraceIO extends Config((site, here, up) => {\n case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {\n case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(\n trace = true))\n case other => other\n }\n case TracePortKey => Some(TracePortParams())\n})\n\nclass WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => {\n case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {\n case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(\n core = tp.tileParams.core.copy(nPerfCounters = n)))\n case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(\n core = tp.tileParams.core.copy(nPerfCounters = n)))\n case other => other\n }\n})\n\nclass WithNPMPs(n: Int = 8) extends Config((site, here, up) => {\n case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {\n case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(\n core = tp.tileParams.core.copy(nPMPs = n)))\n case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(\n core = tp.tileParams.core.copy(nPMPs = n)))\n case other => other\n }\n})\n\nclass WithRocketICacheScratchpad extends Config((site, here, up) => {\n case RocketTilesKey => up(RocketTilesKey, site) map { r =>\n r.copy(icache = r.icache.map(_.copy(itimAddr = Some(0x300000 + r.hartId * 0x10000))))\n }\n})\n\nclass WithRocketDCacheScratchpad extends Config((site, here, up) => {\n case RocketTilesKey => up(RocketTilesKey, site) map { r =>\n r.copy(dcache = r.dcache.map(_.copy(nSets = 32, nWays = 1, scratch = Some(0x200000 + r.hartId * 0x10000))))\n }\n})\n\n// Replaces the L2 with a broadcast manager for maintaining coherence\nclass WithBroadcastManager extends Config((site, here, up) => {\n case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = CoherenceManagerWrapper.broadcastManager)\n})\n\n// The default RocketChip BaseSubsystem drives its diplomatic clock graph\n// with the implicit clocks of Subsystem. Don't do that, instead we extend\n// the diplomacy graph upwards into the ChipTop, where we connect it to\n// our clock drivers\nclass WithNoSubsystemDrivenClocks extends Config((site, here, up) => {\n case SubsystemDriveAsyncClockGroupsKey => None\n})\n\nclass WithDMIDTM extends Config((site, here, up) => {\n case ExportDebug => up(ExportDebug, site).copy(protocols = Set(DMI))\n})\n\nclass WithNoDebug extends Config((site, here, up) => {\n case DebugModuleKey => None\n})\n\nclass WithTLSerialLocation(masterWhere: TLBusWrapperLocation, slaveWhere: TLBusWrapperLocation) extends Config((site, here, up) => {\n case SerialTLAttachKey => up(SerialTLAttachKey, site).copy(masterWhere = masterWhere, slaveWhere = slaveWhere)\n})\n\nclass WithTLBackingMemory extends Config((site, here, up) => {\n case ExtMem => None // disable AXI backing memory\n case ExtTLMem => up(ExtMem, site) // enable TL backing memory\n})\n\nclass WithSerialTLBackingMemory extends Config((site, here, up) => {\n case ExtMem => None\n case SerialTLKey => up(SerialTLKey, site).map { k => k.copy(\n memParams = {\n val memPortParams = up(ExtMem, site).get\n require(memPortParams.nMemoryChannels == 1)\n memPortParams.master\n },\n isMemoryDevice = true\n )}\n})\n\n/**\n * Mixins to define either a specific tile frequency for a single hart or all harts\n *\n * @param fMHz Frequency in MHz of the tile or all tiles\n * @param hartId Optional hartid to assign the frequency to (if unspecified default to all harts)\n */\nclass WithTileFrequency(fMHz: Double, hartId: Option[Int] = None) extends ClockNameContainsAssignment({\n hartId match {\n case Some(id) => s\"tile_$id\"\n case None => \"tile\"\n }\n },\n fMHz)\n\nclass WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => {\n case DefaultClockFrequencyKey => (site(PeripheryBusKey).dtsFrequency.get / (1000 * 1000)).toDouble\n})\n\nclass WithSystemBusFrequencyAsDefault extends Config((site, here, up) => {\n case DefaultClockFrequencyKey => (site(SystemBusKey).dtsFrequency.get / (1000 * 1000)).toDouble\n})\n\nclass BusFrequencyAssignment[T <: HasTLBusParams](re: Regex, key: Field[T]) extends Config((site, here, up) => {\n case ClockFrequencyAssignersKey => up(ClockFrequencyAssignersKey, site) ++\n Seq((cName: String) => site(key).dtsFrequency.flatMap { f =>\n re.findFirstIn(cName).map {_ => (f / (1000 * 1000)).toDouble }\n })\n})\n\n/**\n * Provides a diplomatic frequency for all clock sinks with an unspecified\n * frequency bound to each bus.\n *\n * For example, the L2 cache, when bound to the sbus, receives a separate\n * clock that appears as \"subsystem_sbus_\". This fragment ensures that\n * clock requests the same frequency as the sbus itself.\n */\n\nclass WithInheritBusFrequencyAssignments extends Config(\n new BusFrequencyAssignment(\"subsystem_sbus_\\\\d+\".r, SystemBusKey) ++\n new BusFrequencyAssignment(\"subsystem_pbus_\\\\d+\".r, PeripheryBusKey) ++\n new BusFrequencyAssignment(\"subsystem_cbus_\\\\d+\".r, ControlBusKey) ++\n new BusFrequencyAssignment(\"subsystem_fbus_\\\\d+\".r, FrontBusKey) ++\n new BusFrequencyAssignment(\"subsystem_mbus_\\\\d+\".r, MemoryBusKey)\n)\n\n/**\n * Mixins to specify crossing types between the 5 traditional TL buses\n *\n * Note: these presuppose the legacy connections between buses and set\n * parameters in SubsystemCrossingParams; they may not be resuable in custom\n * topologies (but you can specify the desired crossings in your topology).\n *\n * @param xType The clock crossing type\n *\n */\n\nclass WithSbusToMbusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => {\n case SbusToMbusXTypeKey => xType\n})\nclass WithSbusToCbusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => {\n case SbusToCbusXTypeKey => xType\n})\nclass WithCbusToPbusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => {\n case CbusToPbusXTypeKey => xType\n})\nclass WithFbusToSbusCrossingType(xType: ClockCrossingType) extends Config((site, here, up) => {\n case FbusToSbusXTypeKey => xType\n})\n\n/**\n * Mixins to set the dtsFrequency field of BusParams -- these will percolate its way\n * up the diplomatic graph to the clock sources.\n */\nclass WithPeripheryBusFrequency(freqMHz: Double) extends Config((site, here, up) => {\n case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))\n})\nclass WithMemoryBusFrequency(freqMHz: Double) extends Config((site, here, up) => {\n case MemoryBusKey => up(MemoryBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))\n})\nclass WithSystemBusFrequency(freqMHz: Double) extends Config((site, here, up) => {\n case SystemBusKey => up(SystemBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))\n})\nclass WithFrontBusFrequency(freqMHz: Double) extends Config((site, here, up) => {\n case FrontBusKey => up(FrontBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))\n})\nclass WithControlBusFrequency(freqMHz: Double) extends Config((site, here, up) => {\n case ControlBusKey => up(ControlBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))\n})\n\nclass WithRationalMemoryBusCrossing extends WithSbusToMbusCrossingType(RationalCrossing(Symmetric))\nclass WithAsynchrousMemoryBusCrossing extends WithSbusToMbusCrossingType(AsynchronousCrossing())\n\nclass WithTestChipBusFreqs extends Config(\n // Frequency specifications\n new chipyard.config.WithTileFrequency(1600.0) ++ // Matches the maximum frequency of U540\n new chipyard.config.WithSystemBusFrequency(800.0) ++ // Put the system bus at a lower freq, representative of ncore working at a lower frequency than the tiles. Same freq as U540\n new chipyard.config.WithMemoryBusFrequency(1000.0) ++ // 2x the U540 freq (appropriate for a 128b Mbus)\n new chipyard.config.WithPeripheryBusFrequency(800.0) ++ // Match the sbus and pbus frequency\n new chipyard.config.WithSystemBusFrequencyAsDefault ++ // All unspecified clock frequencies, notably the implicit clock, will use the sbus freq (800 MHz)\n // Crossing specifications\n new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS\n new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS\n new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore\n new boom.common.WithRationalBoomTiles ++ // Add rational crossings between BoomTile and uncore\n new testchipip.WithAsynchronousSerialSlaveCrossing // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS\n)\n", "groundtruth": " case BootROMLocated(x) => up(BootROMLocated(x), site).map(_.copy(contentFileName = s\"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img\"))\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Loop-based Control", "confidence": 0.75, "category_reason": "Functional iteration"} {"task_id": "Bossa", "path": "Bossa/generators/chipyard/src/main/scala/CustomBusTopologies.scala", "left_context": "\npackage chipyard\n\nimport freechips.rocketchip.config.{Field, Config, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\nimport freechips.rocketchip.util.{Location, Symmetric}\nimport freechips.rocketchip.subsystem._\n\n// I'm putting this code here temporarily as I think it should be a candidate\n// for upstreaming based on input from Henry Cook, but don't wnat to deal with\n// an RC branch just yet.\n\n// For subsystem/BusTopology.scala\n\n// Biancolin: This, modified from Henry's email\n/** Parameterization of a topology containing a banked coherence manager and a bus for attaching memory devices. */\ncase class CoherentMulticlockBusTopologyParams(\n sbus: SystemBusParams, // TODO remove this after better width propagation\n mbus: MemoryBusParams,\n l2: BankedL2Params,\n sbusToMbusXType: ClockCrossingType = NoCrossing\n) extends TLBusWrapperTopology(\n instantiations = (if (l2.nBanks == 0) Nil else List(\n (MBUS, mbus),\n (L2, CoherenceManagerWrapperParams(mbus.blockBytes, mbus.beatBytes, l2.nBanks, L2.name)(l2.coherenceManager)))),\n connections = if (l2.nBanks == 0) Nil else List(\n", "right_context": "\n// This differs from upstream only in that it does not use the legacy crossTo\n// and crossFrom functions, and it ensures driveClockFromMaster = None\ncase class HierarchicalMulticlockBusTopologyParams(\n pbus: PeripheryBusParams,\n fbus: FrontBusParams,\n cbus: PeripheryBusParams,\n xTypes: SubsystemCrossingParams\n) extends TLBusWrapperTopology(\n instantiations = List(\n (PBUS, pbus),\n (FBUS, fbus),\n (CBUS, cbus)),\n connections = List(\n (SBUS, CBUS, TLBusWrapperConnection. crossTo(xType = xTypes.sbusToCbusXType, driveClockFromMaster = None)),\n (CBUS, PBUS, TLBusWrapperConnection. crossTo(xType = xTypes.cbusToPbusXType, driveClockFromMaster = None)),\n (FBUS, SBUS, TLBusWrapperConnection.crossFrom(xType = xTypes.fbusToSbusXType, driveClockFromMaster = None)))\n)\n\n// For subsystem/Configs.scala\n\nclass WithMulticlockCoherentBusTopology extends Config((site, here, up) => {\n case TLNetworkTopologyLocated(InSubsystem) => List(\n JustOneBusTopologyParams(sbus = site(SystemBusKey)),\n HierarchicalMulticlockBusTopologyParams(\n pbus = site(PeripheryBusKey),\n fbus = site(FrontBusKey),\n cbus = site(ControlBusKey),\n xTypes = SubsystemCrossingParams(\n sbusToCbusXType = site(SbusToCbusXTypeKey),\n cbusToPbusXType = site(CbusToPbusXTypeKey),\n fbusToSbusXType = site(FbusToSbusXTypeKey))),\n CoherentMulticlockBusTopologyParams(\n sbus = site(SystemBusKey),\n mbus = site(MemoryBusKey),\n l2 = site(BankedL2Key),\n sbusToMbusXType = site(SbusToMbusXTypeKey)))\n})\n\nclass WithMulticlockIncoherentBusTopology extends Config((site, here, up) => {\n case TLNetworkTopologyLocated(InSubsystem) => List(\n JustOneBusTopologyParams(sbus = site(SystemBusKey)),\n HierarchicalMulticlockBusTopologyParams(\n pbus = site(PeripheryBusKey),\n fbus = site(FrontBusKey),\n cbus = site(ControlBusKey),\n xTypes = SubsystemCrossingParams()))\n})\n", "groundtruth": " (SBUS, L2, TLBusWrapperConnection(xType = NoCrossing, driveClockFromMaster = Some(true), nodeBinding = BIND_STAR)()),\n (L2, MBUS, TLBusWrapperConnection.crossTo(\n xType = sbusToMbusXType,\n driveClockFromMaster = None,\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "Bossa", "path": "Bossa/generators/chipyard/src/main/scala/DigitalTop.scala", "left_context": "package chipyard\n\nimport chisel3._\n\nimport freechips.rocketchip.subsystem._\nimport freechips.rocketchip.system._\nimport freechips.rocketchip.config.Parameters\nimport freechips.rocketchip.devices.tilelink._\n\n// ------------------------------------\n// BOOM and/or Rocket Top Level Systems\n// ------------------------------------\n\n// DOC include start: DigitalTop\nclass DigitalTop(implicit p: Parameters) extends ChipyardSystem\n with testchipip.CanHavePeripheryCustomBootPin // Enables optional custom boot pin\n with testchipip.HasPeripheryBootAddrReg // Use programmable boot address register\n with testchipip.CanHaveTraceIO // Enables optionally adding trace IO\n with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad\n with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device\n with testchipip.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter\n with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C\n with sifive.blocks.devices.pwm.HasPeripheryPWM // Enables optionally adding the sifive PWM\n with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART\n with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs\n with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller\n with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI port\n{\n override lazy val module = new DigitalTopModule(this)\n}\n\nclass DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l)\n with testchipip.CanHaveTraceIOModuleImp\n with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp\n with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp\n with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp\n with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp\n with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp\n", "right_context": "", "groundtruth": " with sifive.blocks.devices.spi.HasPeripherySPIModuleImp\n with freechips.rocketchip.util.DontTouch\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "Bossa", "path": "Bossa/generators/chipyard/src/main/scala/Generator.scala", "left_context": "package chipyard\n\nimport firrtl.options.{StageMain}\nimport chipyard.stage.ChipyardStage\n\n", "right_context": "", "groundtruth": "object Generator extends StageMain(new ChipyardStage)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "Bossa", "path": "Bossa/generators/chipyard/src/main/scala/HarnessBinders.scala", "left_context": "package chipyard.harness\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.{Analog, BaseModule, DataMirror, Direction}\n\nimport freechips.rocketchip.config.{Field, Config, Parameters}\nimport freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike}\nimport freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters}\nimport freechips.rocketchip.devices.debug._\nimport freechips.rocketchip.jtag.{JTAGIO}\nimport freechips.rocketchip.system.{SimAXIMem}\nimport freechips.rocketchip.subsystem._\nimport freechips.rocketchip.util._\n\nimport sifive.blocks.devices.gpio._\nimport sifive.blocks.devices.uart._\nimport sifive.blocks.devices.spi._\n\nimport barstools.iocell.chisel._\n\nimport testchipip._\n\nimport chipyard.{HasHarnessSignalReferences, HarnessClockInstantiatorKey}\nimport chipyard.iobinders.{GetSystemParameters, JTAGChipIO}\n\nimport scala.reflect.{ClassTag}\n\ncase object HarnessBinders extends Field[Map[String, (Any, HasHarnessSignalReferences, Seq[Data]) => Unit]](\n Map[String, (Any, HasHarnessSignalReferences, Seq[Data]) => Unit]().withDefaultValue((t: Any, th: HasHarnessSignalReferences, d: Seq[Data]) => ())\n)\n\nobject ApplyHarnessBinders {\n def apply(th: HasHarnessSignalReferences, sys: LazyModule, portMap: Map[String, Seq[Data]])(implicit p: Parameters): Unit = {\n val pm = portMap.withDefaultValue(Nil)\n p(HarnessBinders).foreach { case (s, f) =>\n f(sys, th, pm(s))\n f(sys.module, th, pm(s))\n }\n }\n}\n\n// The ClassTags here are necessary to overcome issues arising from type erasure\nclass HarnessBinder[T, S <: HasHarnessSignalReferences, U <: Data](composer: ((T, S, Seq[U]) => Unit) => (T, S, Seq[U]) => Unit)(implicit systemTag: ClassTag[T], harnessTag: ClassTag[S], portTag: ClassTag[U]) extends Config((site, here, up) => {\n case HarnessBinders => up(HarnessBinders, site) + (systemTag.runtimeClass.toString ->\n ((t: Any, th: HasHarnessSignalReferences, ports: Seq[Data]) => {\n val pts = ports.collect({case p: U => p})\n require (pts.length == ports.length, s\"Port type mismatch between IOBinder and HarnessBinder: ${portTag}\")\n val upfn = up(HarnessBinders, site)(systemTag.runtimeClass.toString)\n th match {\n case th: S =>\n t match {\n case system: T => composer(upfn)(system, th, pts)\n case _ =>\n }\n case _ =>\n }\n })\n )\n})\n\nclass OverrideHarnessBinder[T, S <: HasHarnessSignalReferences, U <: Data](fn: => (T, S, Seq[U]) => Unit)\n (implicit tag: ClassTag[T], thtag: ClassTag[S], ptag: ClassTag[U])\n extends HarnessBinder[T, S, U]((upfn: (T, S, Seq[U]) => Unit) => fn)\n\nclass ComposeHarnessBinder[T, S <: HasHarnessSignalReferences, U <: Data](fn: => (T, S, Seq[U]) => Unit)\n (implicit tag: ClassTag[T], thtag: ClassTag[S], ptag: ClassTag[U])\n extends HarnessBinder[T, S, U]((upfn: (T, S, Seq[U]) => Unit) => (t, th, p) => {\n upfn(t, th, p)\n fn(t, th, p)\n })\n\n\nclass WithGPIOTiedOff extends OverrideHarnessBinder({\n (system: HasPeripheryGPIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[Analog]) => {\n ports.foreach { _ <> AnalogConst(0) }\n }\n})\n\n// DOC include start: WithUARTAdapter\nclass WithUARTAdapter extends OverrideHarnessBinder({\n (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => {\n UARTAdapter.connect(ports)(system.p)\n }\n})\n// DOC include end: WithUARTAdapter\n\nclass WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideHarnessBinder({\n (system: HasPeripherySPIFlashModuleImp, th: HasHarnessSignalReferences, ports: Seq[SPIChipIO]) => {\n SimSPIFlashModel.connect(ports, th.buildtopReset, rdOnly)(system.p)\n }\n})\n\nclass WithSimBlockDevice extends OverrideHarnessBinder({\n (system: CanHavePeripheryBlockDevice, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => {\n implicit val p: Parameters = GetSystemParameters(system)\n ports.map { b => SimBlockDevice.connect(b.clock, th.buildtopReset.asBool, Some(b.bits)) }\n }\n})\n\nclass WithBlockDeviceModel extends OverrideHarnessBinder({\n (system: CanHavePeripheryBlockDevice, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => {\n implicit val p: Parameters = GetSystemParameters(system)\n ports.map { b => withClockAndReset(b.clock, th.buildtopReset) { BlockDeviceModel.connect(Some(b.bits)) } }\n }\n})\n\nclass WithSimAXIMem extends OverrideHarnessBinder({\n (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedAndResetIO[AXI4Bundle]]) => {\n val p: Parameters = chipyard.iobinders.GetSystemParameters(system)\n (ports zip system.memAXI4Node.edges.in).map { case (port, edge) =>\n val mem = LazyModule(new SimAXIMem(edge, size=p(ExtMem).get.master.size)(p))\n withClockAndReset(port.clock, port.reset) {\n Module(mem.module).suggestName(\"mem\")\n }\n mem.io_axi4.head <> port.bits\n }\n }\n})\n\nclass WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({\n (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {\n implicit val p = chipyard.iobinders.GetSystemParameters(system)\n\n p(SerialTLKey).map({ sVal =>\n require(sVal.axiMemOverSerialTLParams.isDefined)\n val axiDomainParams = sVal.axiMemOverSerialTLParams.get\n require(sVal.isMemoryDevice)\n\n val memFreq = axiDomainParams.getMemFrequency(system.asInstanceOf[HasTileLinkLocations])\n\n ports.map({ port =>\n// DOC include start: HarnessClockInstantiatorEx\n withClockAndReset(th.buildtopClock, th.buildtopReset) {\n val memOverSerialTLClockBundle = p(HarnessClockInstantiatorKey).requestClockBundle(\"mem_over_serial_tl_clock\", memFreq)\n val serial_bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset)\n val harnessMultiClockAXIRAM = SerialAdapter.connectHarnessMultiClockAXIRAM(\n system.serdesser.get,\n serial_bits,\n memOverSerialTLClockBundle,\n th.buildtopReset)\n// DOC include end: HarnessClockInstantiatorEx\n val success = SerialAdapter.connectSimSerial(harnessMultiClockAXIRAM.module.io.tsi_ser, th.buildtopClock, th.buildtopReset.asBool)\n when (success) { th.success := true.B }\n\n // connect SimDRAM from the AXI port coming from the harness multi clock axi ram\n (harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi_port, edge) =>\n val memSize = sVal.memParams.size\n val lineSize = p(CacheBlockBytes)\n val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), edge.bundle)).suggestName(\"simdram\")\n mem.io.axi <> axi_port.bits\n mem.io.clock := axi_port.clock\n mem.io.reset := axi_port.reset\n }\n }\n })\n })\n }\n})\n\nclass WithBlackBoxSimMem(additionalLatency: Int = 0) extends OverrideHarnessBinder({\n (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedAndResetIO[AXI4Bundle]]) => {\n val p: Parameters = chipyard.iobinders.GetSystemParameters(system)\n (ports zip system.memAXI4Node.edges.in).map { case (port, edge) =>\n val memSize = p(ExtMem).get.master.size\n val lineSize = p(CacheBlockBytes)\n val clockFreq = p(MemoryBusKey).dtsFrequency.get\n val mem = Module(new SimDRAM(memSize, lineSize, clockFreq, edge.bundle)).suggestName(\"simdram\")\n mem.io.axi <> port.bits\n // Bug in Chisel implementation. See https://github.com/chipsalliance/chisel3/pull/1781\n def Decoupled[T <: Data](irr: IrrevocableIO[T]): DecoupledIO[T] = {\n require(DataMirror.directionOf(irr.bits) == Direction.Output, \"Only safe to cast produced Irrevocable bits to Decoupled.\")\n val d = Wire(new DecoupledIO(chiselTypeOf(irr.bits)))\n d.bits := irr.bits\n d.valid := irr.valid\n irr.ready := d.ready\n d\n }\n if (additionalLatency > 0) {\n withClockAndReset (port.clock, port.reset) {\n mem.io.axi.aw <> (0 until additionalLatency).foldLeft(Decoupled(port.bits.aw))((t, _) => Queue(t, 1, pipe=true))\n mem.io.axi.w <> (0 until additionalLatency).foldLeft(Decoupled(port.bits.w ))((t, _) => Queue(t, 1, pipe=true))\n port.bits.b <> (0 until additionalLatency).foldLeft(Decoupled(mem.io.axi.b))((t, _) => Queue(t, 1, pipe=true))\n mem.io.axi.ar <> (0 until additionalLatency).foldLeft(Decoupled(port.bits.ar))((t, _) => Queue(t, 1, pipe=true))\n port.bits.r <> (0 until additionalLatency).foldLeft(Decoupled(mem.io.axi.r))((t, _) => Queue(t, 1, pipe=true))\n }\n }\n mem.io.clock := port.clock\n mem.io.reset := port.reset\n }\n }\n})\n\nclass WithSimAXIMMIO extends OverrideHarnessBinder({\n (system: CanHaveMasterAXI4MMIOPort, th: HasHarnessSignalReferences, ports: Seq[ClockedAndResetIO[AXI4Bundle]]) => {\n val p: Parameters = chipyard.iobinders.GetSystemParameters(system)\n (ports zip system.mmioAXI4Node.edges.in).map { case (port, edge) =>\n val mmio_mem = LazyModule(new SimAXIMem(edge, size = p(ExtBus).get.size)(p))\n withClockAndReset(port.clock, port.reset) {\n Module(mmio_mem.module).suggestName(\"mmio_mem\")\n }\n mmio_mem.io_axi4.head <> port.bits\n }\n }\n})\n\nclass WithTieOffInterrupts extends OverrideHarnessBinder({\n (system: HasExtInterruptsModuleImp, th: HasHarnessSignalReferences, ports: Seq[UInt]) => {\n ports.foreach { _ := 0.U }\n }\n})\n\nclass WithTieOffL2FBusAXI extends OverrideHarnessBinder({\n (system: CanHaveSlaveAXI4Port, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => {\n", "right_context": " }\n})\n\nclass WithSimDebug extends OverrideHarnessBinder({\n (system: HasPeripheryDebug, th: HasHarnessSignalReferences, ports: Seq[Data]) => {\n implicit val p: Parameters = GetSystemParameters(system)\n ports.map {\n case d: ClockedDMIIO =>\n val dtm_success = WireInit(false.B)\n when (dtm_success) { th.success := true.B }\n val dtm = Module(new SimDTM).connect(th.buildtopClock, th.buildtopReset.asBool, d, dtm_success)\n case j: JTAGChipIO =>\n val dtm_success = WireInit(false.B)\n when (dtm_success) { th.success := true.B }\n val jtag_wire = Wire(new JTAGIO)\n jtag_wire.TDO.data := j.TDO\n jtag_wire.TDO.driven := true.B\n j.TCK := jtag_wire.TCK\n j.TMS := jtag_wire.TMS\n j.TDI := jtag_wire.TDI\n val jtag = Module(new SimJTAG(tickDelay=3)).connect(jtag_wire, th.buildtopClock, th.buildtopReset.asBool, ~(th.buildtopReset.asBool), dtm_success)\n }\n }\n})\n\nclass WithTiedOffDebug extends OverrideHarnessBinder({\n (system: HasPeripheryDebug, th: HasHarnessSignalReferences, ports: Seq[Data]) => {\n ports.map {\n case j: JTAGChipIO =>\n j.TCK := true.B.asClock\n j.TMS := true.B\n j.TDI := true.B\n case d: ClockedDMIIO =>\n d.dmi.req.valid := false.B\n d.dmi.req.bits := DontCare\n d.dmi.resp.ready := true.B\n d.dmiClock := false.B.asClock\n d.dmiReset := true.B\n case a: ClockedAPBBundle =>\n a.tieoff()\n a.clock := false.B.asClock\n a.reset := true.B.asAsyncReset\n a.psel := false.B\n a.penable := false.B\n }\n }\n})\n\n\nclass WithSerialAdapterTiedOff extends OverrideHarnessBinder({\n (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {\n implicit val p = chipyard.iobinders.GetSystemParameters(system)\n ports.map({ port =>\n val bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset)\n withClockAndReset(th.buildtopClock, th.buildtopReset) {\n val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset)\n SerialAdapter.tieoff(ram.module.io.tsi_ser)\n }\n })\n }\n})\n\nclass WithSimSerial extends OverrideHarnessBinder({\n (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {\n implicit val p = chipyard.iobinders.GetSystemParameters(system)\n ports.map({ port =>\n val bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset)\n withClockAndReset(th.buildtopClock, th.buildtopReset) {\n val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset)\n val success = SerialAdapter.connectSimSerial(ram.module.io.tsi_ser, th.buildtopClock, th.buildtopReset.asBool)\n when (success) { th.success := true.B }\n }\n })\n }\n})\n\nclass WithTieOffCustomBootPin extends OverrideHarnessBinder({\n (system: CanHavePeripheryCustomBootPin, th: HasHarnessSignalReferences, ports: Seq[Bool]) => {\n ports.foreach(_ := false.B)\n }\n})\n", "groundtruth": " ports.foreach({ p => p := DontCare; p.bits.tieoff() })\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Loop-based Control", "confidence": 0.75, "category_reason": "Functional iteration"} {"task_id": "Bossa", "path": "Bossa/generators/chipyard/src/main/scala/IOBinders.scala", "left_context": "package chipyard.iobinders\n\nimport chisel3._\nimport chisel3.experimental.{Analog, IO, DataMirror}\n\nimport freechips.rocketchip.config._\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.devices.debug._\nimport freechips.rocketchip.jtag.{JTAGIO}\nimport freechips.rocketchip.subsystem._\nimport freechips.rocketchip.system.{SimAXIMem}\nimport freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters}\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.prci.{ClockSinkNode, ClockSinkParameters}\nimport freechips.rocketchip.groundtest.{GroundTestSubsystemModuleImp, GroundTestSubsystem}\n\nimport sifive.blocks.devices.gpio._\nimport sifive.blocks.devices.uart._\nimport sifive.blocks.devices.spi._\n\nimport barstools.iocell.chisel._\n\nimport testchipip._\n\nimport scala.reflect.{ClassTag}\n\nobject IOBinderTypes {\n type IOBinderTuple = (Seq[Data], Seq[IOCell])\n type IOBinderFunction = (Boolean, => Any) => ModuleValue[IOBinderTuple]\n}\nimport IOBinderTypes._\n\n// System for instantiating binders based\n// on the scala type of the Target (_not_ its IO). This avoids needing to\n// duplicate harnesses (essentially test harnesses) for each target.\n\n// IOBinders is map between string representations of traits to the desired\n// IO connection behavior for tops matching that trait. We use strings to enable\n// composition and overriding of IOBinders, much like how normal Keys in the config\n// system are used/ At elaboration, the testharness traverses this set of functions,\n// and functions which match the type of the DigitalTop are evaluated.\n\n// You can add your own binder by adding a new (key, fn) pair, typically by using\n// the OverrideIOBinder or ComposeIOBinder macros\ncase object IOBinders extends Field[Map[String, Seq[IOBinderFunction]]](\n Map[String, Seq[IOBinderFunction]]().withDefaultValue(Nil)\n)\n\nabstract trait HasIOBinders { this: LazyModule =>\n val lazySystem: LazyModule\n private val iobinders = p(IOBinders)\n // Note: IOBinders cannot rely on the implicit clock/reset, as they may be called from the\n // context of a LazyRawModuleImp\n private val lzy = iobinders.map({ case (s,fns) => s -> fns.map(f => f(true, lazySystem)) })\n private val imp = iobinders.map({ case (s,fns) => s -> fns.map(f => f(false, lazySystem.module)) })\n\n private lazy val lzyFlattened: Map[String, IOBinderTuple] = lzy.map({\n case (s,ms) => s -> (ms.map(_._1).flatten, ms.map(_._2).flatten)\n })\n private lazy val impFlattened: Map[String, IOBinderTuple] = imp.map({\n case (s,ms) => s -> (ms.map(_._1).flatten, ms.map(_._2).flatten)\n })\n\n // A publicly accessible list of IO cells (useful for a floorplanning tool, for example)\n lazy val iocells = (lzyFlattened.values ++ impFlattened.values).unzip._2.flatten.toBuffer\n\n // A mapping between stringified DigitalSystem traits and their corresponding ChipTop ports\n lazy val portMap = iobinders.keys.map(k => k -> (lzyFlattened(k)._1 ++ impFlattened(k)._1)).toMap\n}\n\n// Note: The parameters instance is accessible only through LazyModule\n// or LazyModuleImpLike. The self-type requirement in traits like\n// CanHaveMasterAXI4MemPort is insufficient to make it accessible to the IOBinder\n// As a result, IOBinders only work on Modules which inherit LazyModule or\n// or LazyModuleImpLike\nobject GetSystemParameters {\n def apply(s: Any): Parameters = {\n s match {\n case s: LazyModule => s.p\n case s: LazyModuleImpLike => s.p\n case _ => throw new Exception(s\"Trying to get Parameters from a system that is not LazyModule or LazyModuleImpLike\")\n }\n }\n}\n\nclass IOBinder[T](composer: Seq[IOBinderFunction] => Seq[IOBinderFunction])(implicit tag: ClassTag[T]) extends Config((site, here, up) => {\n case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> composer(up(IOBinders, site)(tag.runtimeClass.toString)))\n})\n\nclass ConcreteIOBinder[T](composes: Boolean, fn: T => IOBinderTuple)(implicit tag: ClassTag[T]) extends IOBinder[T](\n up => (if (composes) up else Nil) ++ Seq(((_, t) => { InModuleBody {\n t match {\n case system: T => fn(system)\n case _ => (Nil, Nil)\n }\n }}): IOBinderFunction)\n)\n\nclass LazyIOBinder[T](composes: Boolean, fn: T => ModuleValue[IOBinderTuple])(implicit tag: ClassTag[T]) extends IOBinder[T](\n up => (if (composes) up else Nil) ++ Seq(((isLazy, t) => {\n val empty = new ModuleValue[IOBinderTuple] {\n def getWrappedValue: IOBinderTuple = (Nil, Nil)\n }\n if (isLazy) {\n t match {\n case system: T => fn(system)\n case _ => empty\n }\n } else {\n empty\n }\n }): IOBinderFunction)\n)\n\n// The \"Override\" binders override any previous IOBinders (lazy or concrete) defined on the same trait.\n// The \"Compose\" binders do not override previously defined IOBinders on the same trait\n// The default IOBinders evaluate only in the concrete \"ModuleImp\" phase of elaboration\n// The \"Lazy\" IOBinders evaluate in the LazyModule phase, but can also generate hardware through InModuleBody\n\nclass OverrideIOBinder[T](fn: T => IOBinderTuple)(implicit tag: ClassTag[T]) extends ConcreteIOBinder[T](false, fn)\nclass ComposeIOBinder[T](fn: T => IOBinderTuple)(implicit tag: ClassTag[T]) extends ConcreteIOBinder[T](true, fn)\n\nclass OverrideLazyIOBinder[T](fn: T => ModuleValue[IOBinderTuple])(implicit tag: ClassTag[T]) extends LazyIOBinder[T](false, fn)\nclass ComposeLazyIOBinder[T](fn: T => ModuleValue[IOBinderTuple])(implicit tag: ClassTag[T]) extends LazyIOBinder[T](true, fn)\n\n\ncase object IOCellKey extends Field[IOCellTypeParams](GenericIOCellParams())\n\n\nclass WithGPIOCells extends OverrideIOBinder({\n (system: HasPeripheryGPIOModuleImp) => {\n val (ports2d, cells2d) = system.gpio.zipWithIndex.map({ case (gpio, i) =>\n gpio.pins.zipWithIndex.map({ case (pin, j) =>\n val g = IO(Analog(1.W)).suggestName(s\"gpio_${i}_${j}\")\n val iocell = system.p(IOCellKey).gpio().suggestName(s\"iocell_gpio_${i}_${j}\")\n iocell.io.o := pin.o.oval\n iocell.io.oe := pin.o.oe\n iocell.io.ie := pin.o.ie\n pin.i.ival := iocell.io.i\n iocell.io.pad <> g\n (g, iocell)\n }).unzip\n }).unzip\n val ports: Seq[Analog] = ports2d.flatten\n (ports, cells2d.flatten)\n }\n})\n\n// DOC include start: WithUARTIOCells\nclass WithUARTIOCells extends OverrideIOBinder({\n (system: HasPeripheryUARTModuleImp) => {\n val (ports: Seq[UARTPortIO], cells2d) = system.uart.zipWithIndex.map({ case (u, i) =>\n val (port, ios) = IOCell.generateIOFromSignal(u, s\"uart_${i}\", system.p(IOCellKey), abstractResetAsAsync = true)\n (port, ios)\n }).unzip\n (ports, cells2d.flatten)\n }\n})\n// DOC include end: WithUARTIOCells\n\nclass WithSPIIOCells extends OverrideIOBinder({\n (system: HasPeripherySPIFlashModuleImp) => {\n val (ports: Seq[SPIChipIO], cells2d) = system.qspi.zipWithIndex.map({ case (s, i) =>\n val name = s\"spi_${i}\"\n val port = IO(new SPIChipIO(s.c.csWidth)).suggestName(name)\n val iocellBase = s\"iocell_${name}\"\n\n // SCK and CS are unidirectional outputs\n val sckIOs = IOCell.generateFromSignal(s.sck, port.sck, Some(s\"${iocellBase}_sck\"), system.p(IOCellKey), IOCell.toAsyncReset)\n val csIOs = IOCell.generateFromSignal(s.cs, port.cs, Some(s\"${iocellBase}_cs\"), system.p(IOCellKey), IOCell.toAsyncReset)\n\n // DQ are bidirectional, so then need special treatment\n val dqIOs = s.dq.zip(port.dq).zipWithIndex.map { case ((pin, ana), j) =>\n val iocell = system.p(IOCellKey).gpio().suggestName(s\"${iocellBase}_dq_${j}\")\n iocell.io.o := pin.o\n iocell.io.oe := pin.oe\n iocell.io.ie := true.B\n pin.i := iocell.io.i\n iocell.io.pad <> ana\n iocell\n }\n\n (port, dqIOs ++ csIOs ++ sckIOs)\n }).unzip\n (ports, cells2d.flatten)\n }\n})\n\nclass WithExtInterruptIOCells extends OverrideIOBinder({\n (system: HasExtInterruptsModuleImp) => {\n if (system.outer.nExtInterrupts > 0) {\n val (port: UInt, cells) = IOCell.generateIOFromSignal(system.interrupts, \"ext_interrupts\", system.p(IOCellKey), abstractResetAsAsync = true)\n (Seq(port), cells)\n } else {\n (Nil, Nil)\n }\n }\n})\n\n// Rocketchip's JTAGIO exposes the oe signal, which doesn't go off-chip\nclass JTAGChipIO extends Bundle {\n val TCK = Input(Clock())\n val TMS = Input(Bool())\n val TDI = Input(Bool())\n val TDO = Output(Bool())\n}\n\nclass WithDebugIOCells extends OverrideLazyIOBinder({\n (system: HasPeripheryDebug) => {\n implicit val p = GetSystemParameters(system)\n val tlbus = system.asInstanceOf[BaseSubsystem].locateTLBusWrapper(p(ExportDebug).slaveWhere)\n val clockSinkNode = system.debugOpt.map(_ => ClockSinkNode(Seq(ClockSinkParameters())))\n clockSinkNode.map(_ := tlbus.fixedClockNode)\n def clockBundle = clockSinkNode.get.in.head._1\n\n\n InModuleBody { system.asInstanceOf[BaseSubsystem].module match { case system: HasPeripheryDebugModuleImp => {\n system.debug.map({ debug =>\n // We never use the PSDIO, so tie it off on-chip\n system.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) }\n system.resetctrl.map { rcio => rcio.hartIsInReset.map { _ := clockBundle.reset.asBool } }\n system.debug.map { d =>\n // Tie off extTrigger\n d.extTrigger.foreach { t =>\n t.in.req := false.B\n t.out.ack := t.out.req\n }\n // Tie off disableDebug\n d.disableDebug.foreach { d => d := false.B }\n // Drive JTAG on-chip IOs\n d.systemjtag.map { j =>\n j.reset := ResetCatchAndSync(j.jtag.TCK, clockBundle.reset.asBool)\n j.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)\n j.part_number := p(JtagDTMKey).idcodePartNum.U(16.W)\n j.version := p(JtagDTMKey).idcodeVersion.U(4.W)\n }\n }\n Debug.connectDebugClockAndReset(Some(debug), clockBundle.clock)\n\n // Add IOCells for the DMI/JTAG/APB ports\n val dmiTuple = debug.clockeddmi.map { d =>\n IOCell.generateIOFromSignal(d, \"dmi\", p(IOCellKey), abstractResetAsAsync = true)\n }\n\n val jtagTuple = debug.systemjtag.map { j =>\n val jtag_wire = Wire(new JTAGChipIO)\n j.jtag.TCK := jtag_wire.TCK\n j.jtag.TMS := jtag_wire.TMS\n j.jtag.TDI := jtag_wire.TDI\n jtag_wire.TDO := j.jtag.TDO.data\n IOCell.generateIOFromSignal(jtag_wire, \"jtag\", p(IOCellKey), abstractResetAsAsync = true)\n }\n\n val apbTuple = debug.apb.map { a =>\n IOCell.generateIOFromSignal(a, \"apb\", p(IOCellKey), abstractResetAsAsync = true)\n }\n\n val allTuples = (dmiTuple ++ jtagTuple ++ apbTuple).toSeq\n (allTuples.map(_._1).toSeq, allTuples.flatMap(_._2).toSeq)\n }).getOrElse((Nil, Nil))\n }}}\n }\n})\n\nclass WithSerialTLIOCells extends OverrideIOBinder({\n (system: CanHavePeripheryTLSerial) => system.serial_tl.map({ s =>\n val sys = system.asInstanceOf[BaseSubsystem]\n val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, \"serial_tl\", sys.p(IOCellKey), abstractResetAsAsync = true)\n (Seq(port), cells)\n }).getOrElse((Nil, Nil))\n})\n\nclass WithAXI4MemPunchthrough extends OverrideLazyIOBinder({\n (system: CanHaveMasterAXI4MemPort) => {\n implicit val p: Parameters = GetSystemParameters(system)\n val clockSinkNode = p(ExtMem).map(_ => ClockSinkNode(Seq(ClockSinkParameters())))\n clockSinkNode.map(_ := system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(MBUS).fixedClockNode)\n def clockBundle = clockSinkNode.get.in.head._1\n\n InModuleBody {\n val ports: Seq[ClockedAndResetIO[AXI4Bundle]] = system.mem_axi4.zipWithIndex.map({ case (m, i) =>\n", "right_context": " p.bits <> m\n p.clock := clockBundle.clock\n p.reset := clockBundle.reset\n p\n })\n (ports, Nil)\n }\n }\n})\n\nclass WithAXI4MMIOPunchthrough extends OverrideLazyIOBinder({\n (system: CanHaveMasterAXI4MMIOPort) => {\n implicit val p: Parameters = GetSystemParameters(system)\n val clockSinkNode = p(ExtBus).map(_ => ClockSinkNode(Seq(ClockSinkParameters())))\n clockSinkNode.map(_ := system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(MBUS).fixedClockNode)\n def clockBundle = clockSinkNode.get.in.head._1\n\n InModuleBody {\n val ports: Seq[ClockedAndResetIO[AXI4Bundle]] = system.mmio_axi4.zipWithIndex.map({ case (m, i) =>\n val p = IO(new ClockedAndResetIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s\"axi4_mmio_${i}\")\n p.bits <> m\n p.clock := clockBundle.clock\n p.reset := clockBundle.reset\n p\n })\n (ports, Nil)\n }\n }\n})\n\nclass WithL2FBusAXI4Punchthrough extends OverrideLazyIOBinder({\n (system: CanHaveSlaveAXI4Port) => {\n implicit val p: Parameters = GetSystemParameters(system)\n val clockSinkNode = p(ExtIn).map(_ => ClockSinkNode(Seq(ClockSinkParameters())))\n clockSinkNode.map(_ := system.asInstanceOf[BaseSubsystem].fbus.fixedClockNode)\n def clockBundle = clockSinkNode.get.in.head._1\n\n InModuleBody {\n val ports: Seq[ClockedIO[AXI4Bundle]] = system.l2_frontend_bus_axi4.zipWithIndex.map({ case (m, i) =>\n val p = IO(new ClockedIO(Flipped(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)))).suggestName(s\"axi4_fbus_${i}\")\n m <> p.bits\n p.clock := clockBundle.clock\n p\n })\n (ports, Nil)\n }\n }\n})\n\nclass WithBlockDeviceIOPunchthrough extends OverrideIOBinder({\n (system: CanHavePeripheryBlockDevice) => {\n val ports: Seq[ClockedIO[BlockDeviceIO]] = system.bdev.map({ bdev =>\n val p = IO(new ClockedIO(new BlockDeviceIO()(GetSystemParameters(system)))).suggestName(\"blockdev\")\n p <> bdev\n p\n }).toSeq\n (ports, Nil)\n }\n})\n\nclass WithTraceIOPunchthrough extends OverrideIOBinder({\n (system: CanHaveTraceIOModuleImp) => {\n val ports: Option[TraceOutputTop] = system.traceIO.map { t =>\n val trace = IO(DataMirror.internal.chiselTypeClone[TraceOutputTop](t)).suggestName(\"trace\")\n trace <> t\n trace\n }\n (ports.toSeq, Nil)\n }\n})\n\nclass WithCustomBootPin extends OverrideIOBinder({\n (system: CanHavePeripheryCustomBootPin) => system.custom_boot_pin.map({ p =>\n val sys = system.asInstanceOf[BaseSubsystem]\n val (port, cells) = IOCell.generateIOFromSignal(p.getWrappedValue, \"custom_boot\", sys.p(IOCellKey), abstractResetAsAsync = true)\n (Seq(port), cells)\n }).getOrElse((Nil, Nil))\n})\n\nclass WithDontTouchPorts extends OverrideIOBinder({\n (system: DontTouch) => system.dontTouchPorts(); (Nil, Nil)\n})\n\n", "groundtruth": " val p = IO(new ClockedAndResetIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s\"axi4_mem_${i}\")\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.6, "category_reason": "val binding"} {"task_id": "Bossa", "path": "Bossa/generators/chipyard/src/main/scala/Subsystem.scala", "left_context": "//******************************************************************************\n// Copyright (c) 2019 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\npackage chipyard\n\nimport chisel3._\nimport chisel3.internal.sourceinfo.{SourceInfo}\n\nimport freechips.rocketchip.prci._\nimport freechips.rocketchip.config.{Field, Parameters}\nimport freechips.rocketchip.devices.tilelink._\nimport freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug, DebugModuleKey}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.diplomaticobjectmodel.model.{OMInterrupt}\nimport freechips.rocketchip.diplomaticobjectmodel.logicaltree.{RocketTileLogicalTreeNode, LogicalModuleTree}\nimport freechips.rocketchip.tile._\nimport freechips.rocketchip.tilelink._\nimport freechips.rocketchip.interrupts._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.subsystem._\nimport freechips.rocketchip.amba.axi4._\n\nimport boom.common.{BoomTile}\n\n\nimport testchipip.{CanHavePeripheryTLSerial, SerialTLKey}\n\ntrait CanHaveHTIF { this: BaseSubsystem =>\n // Advertise HTIF if system can communicate with fesvr\n if (this match {\n case _: CanHavePeripheryTLSerial if p(SerialTLKey).nonEmpty => true\n case _: HasPeripheryDebug if (!p(DebugModuleKey).isEmpty && p(ExportDebug).dmi) => true\n case _ => false\n }) {\n ResourceBinding {\n val htif = new Device {\n def describe(resources: ResourceBindings): Description = {\n val compat = resources(\"compat\").map(_.value)\n Description(\"htif\", Map(\n \"compatible\" -> compat))\n }\n }\n Resource(htif, \"compat\").bind(ResourceString(\"ucb,htif0\"))\n }\n }\n}\n\nclass ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem\n with HasTiles\n with CanHaveHTIF\n{\n def coreMonitorBundles = tiles.map {\n case r: RocketTile => r.module.core.rocketImpl.coreMonitorBundle\n case b: BoomTile => b.module.core.coreMonitorBundle\n }.toList\n\n\n // Relying on [[TLBusWrapperConnection]].driveClockFromMaster for\n // bus-couplings that are not asynchronous strips the bus name from the sink\n // ClockGroup. This makes it impossible to determine which clocks are driven\n // by which bus based on the member names, which is problematic when there is\n // a rational crossing between two buses. Instead, provide all bus clocks\n // directly from the asyncClockGroupsNode in the subsystem to ensure bus\n // names are always preserved in the top-level clock names.\n //\n // For example, using a RationalCrossing between the Sbus and Cbus, and\n // driveClockFromMaster = Some(true) results in all cbus-attached device and\n // bus clocks to be given names of the form \"subsystem_sbus_[0-9]*\".\n // Conversly, if an async crossing is used, they instead receive names of the\n // form \"subsystem_cbus_[0-9]*\". The assignment below provides the latter names in all cases.\n Seq(PBUS, FBUS, MBUS, CBUS).foreach { loc =>\n", "right_context": " }\n override lazy val module = new ChipyardSubsystemModuleImp(this)\n}\n\nclass ChipyardSubsystemModuleImp[+L <: ChipyardSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)\n with HasTilesModuleImp\n{\n // create file with core params\n ElaborationArtefacts.add(\"\"\"core.config\"\"\", outer.tiles.map(x => x.module.toString).mkString(\"\\n\"))\n}\n\n", "groundtruth": " tlBusWrapperLocationMap.lift(loc).foreach { _.clockGroupNode := asyncClockGroupsNode }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Loop-based Control", "confidence": 0.75, "category_reason": "Functional iteration"} {"task_id": "Bossa", "path": "Bossa/generators/chipyard/src/main/scala/System.scala", "left_context": "//******************************************************************************\n// Copyright (c) 2019 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\npackage chipyard\n\nimport chisel3._\n\nimport freechips.rocketchip.config.{Parameters, Field}\nimport freechips.rocketchip.subsystem._\nimport freechips.rocketchip.tilelink._\nimport freechips.rocketchip.devices.tilelink._\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.util.{DontTouch}\n\n// ---------------------------------------------------------------------\n// Base system that uses the debug test module (dtm) to bringup the core\n// ---------------------------------------------------------------------\n\n/**\n * Base top with periphery devices and ports, and a BOOM + Rocket subsystem\n */\nclass ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem\n with HasAsyncExtInterrupts\n with CanHaveMasterTLMemPort // export TL port for outer memory\n with CanHaveMasterAXI4MemPort // expose AXI port for outer mem\n with CanHaveMasterAXI4MMIOPort\n with CanHaveSlaveAXI4Port\n{\n\n val bootROM = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) }\n", "right_context": " override lazy val module = new ChipyardSystemModule(this)\n}\n\n/**\n * Base top module implementation with periphery devices and ports, and a BOOM + Rocket subsystem\n */\nclass ChipyardSystemModule[+L <: ChipyardSystem](_outer: L) extends ChipyardSubsystemModuleImp(_outer)\n with HasRTCModuleImp\n with HasExtInterruptsModuleImp\n with DontTouch\n\n// ------------------------------------\n// TL Mem Port Mixin\n// ------------------------------------\n\n// Similar to ExtMem but instantiates a TL mem port\ncase object ExtTLMem extends Field[Option[MemoryPortParams]](None)\n\n/** Adds a port to the system intended to master an TL DRAM controller. */\ntrait CanHaveMasterTLMemPort { this: BaseSubsystem =>\n\n require(!(p(ExtTLMem).nonEmpty && p(ExtMem).nonEmpty),\n \"Can only have 1 backing memory port. Use ExtTLMem for a TL memory port or ExtMem for an AXI memory port.\")\n\n private val memPortParamsOpt = p(ExtTLMem)\n private val portName = \"tl_mem\"\n private val device = new MemoryDevice\n private val idBits = memPortParamsOpt.map(_.master.idBits).getOrElse(1)\n\n val memTLNode = TLManagerNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels) =>\n Seq.tabulate(nMemoryChannels) { channel =>\n val base = AddressSet.misaligned(memPortParams.base, memPortParams.size)\n val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes))\n\n TLSlavePortParameters.v1(\n managers = Seq(TLSlaveParameters.v1(\n address = base.flatMap(_.intersect(filter)),\n resources = device.reg,\n regionType = RegionType.UNCACHED, // cacheable\n executable = true,\n supportsGet = TransferSizes(1, mbus.blockBytes),\n supportsPutFull = TransferSizes(1, mbus.blockBytes),\n supportsPutPartial = TransferSizes(1, mbus.blockBytes))),\n beatBytes = memPortParams.beatBytes)\n }\n }).toList.flatten)\n\n mbus.coupleTo(s\"memory_controller_port_named_$portName\") {\n (memTLNode\n :*= TLBuffer()\n :*= TLSourceShrinker(1 << idBits)\n :*= TLWidthWidget(mbus.beatBytes)\n :*= _)\n }\n\n val mem_tl = InModuleBody { memTLNode.makeIOs() }\n}\n", "groundtruth": " val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Loop-based Control", "confidence": 0.75, "category_reason": "Functional iteration"} {"task_id": "Bossa", "path": "Bossa/generators/chipyard/src/main/scala/TestHarness.scala", "left_context": "package chipyard\n\nimport chisel3._\n\nimport scala.collection.mutable.{ArrayBuffer, LinkedHashMap}\nimport freechips.rocketchip.diplomacy.{LazyModule}\nimport freechips.rocketchip.config.{Field, Parameters}\nimport freechips.rocketchip.util.{ResetCatchAndSync}\nimport freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters, ClockSinkParameters, ClockParameters}\n\nimport chipyard.harness.{ApplyHarnessBinders, HarnessBinders}\nimport chipyard.iobinders.HasIOBinders\nimport chipyard.clocking.{SimplePllConfiguration, ClockDividerN}\n\n// -------------------------------\n// Chipyard Test Harness\n// -------------------------------\n\n", "right_context": "\ntrait HasTestHarnessFunctions {\n val harnessFunctions = ArrayBuffer.empty[HasHarnessSignalReferences => Seq[Any]]\n}\n\ntrait HasHarnessSignalReferences {\n // clock/reset of the chiptop reference clock (can be different than the implicit harness clock/reset)\n def buildtopClock: Clock\n def buildtopReset: Reset\n def dutReset: Reset\n def success: Bool\n}\n\nclass HarnessClockInstantiator {\n private val _clockMap: LinkedHashMap[String, (Double, ClockBundle)] = LinkedHashMap.empty\n\n // request a clock bundle at a particular frequency\n def requestClockBundle(name: String, freqRequested: Double): ClockBundle = {\n val clockBundle = Wire(new ClockBundle(ClockBundleParameters()))\n _clockMap(name) = (freqRequested, clockBundle)\n clockBundle\n }\n\n // connect all clock wires specified to a divider only PLL\n def instantiateHarnessDividerPLL(refClock: ClockBundle): Unit = {\n val sinks = _clockMap.map({ case (name, (freq, bundle)) =>\n ClockSinkParameters(take=Some(ClockParameters(freqMHz=freq / (1000 * 1000))), name=Some(name))\n }).toSeq\n\n val pllConfig = new SimplePllConfiguration(\"harnessDividerOnlyClockGenerator\", sinks)\n pllConfig.emitSummaries()\n\n val dividedClocks = LinkedHashMap[Int, Clock]()\n def instantiateDivider(div: Int): Clock = {\n val divider = Module(new ClockDividerN(div))\n divider.suggestName(s\"ClockDivideBy${div}\")\n divider.io.clk_in := refClock.clock\n dividedClocks(div) = divider.io.clk_out\n divider.io.clk_out\n }\n\n // connect wires to clock source\n for (sinkParams <- sinks) {\n // bypass the reference freq. (don't create a divider + reset sync)\n val (divClock, divReset) = if (sinkParams.take.get.freqMHz != pllConfig.referenceFreqMHz) {\n val div = pllConfig.sinkDividerMap(sinkParams)\n val divClock = dividedClocks.getOrElse(div, instantiateDivider(div))\n (divClock, ResetCatchAndSync(divClock, refClock.reset.asBool))\n } else {\n (refClock.clock, refClock.reset)\n }\n\n _clockMap(sinkParams.name.get)._2.clock := divClock\n _clockMap(sinkParams.name.get)._2.reset := divReset\n }\n }\n}\n\ncase object HarnessClockInstantiatorKey extends Field[HarnessClockInstantiator](new HarnessClockInstantiator)\n\nclass TestHarness(implicit val p: Parameters) extends Module with HasHarnessSignalReferences {\n val io = IO(new Bundle {\n val success = Output(Bool())\n })\n\n val buildtopClock = Wire(Clock())\n val buildtopReset = Wire(Reset())\n\n val lazyDut = LazyModule(p(BuildTop)(p)).suggestName(\"chiptop\")\n val dut = Module(lazyDut.module)\n\n io.success := false.B\n\n val freqMHz = lazyDut match {\n case d: HasReferenceClockFreq => d.refClockFreqMHz\n case _ => p(DefaultClockFrequencyKey)\n }\n val refClkBundle = p(HarnessClockInstantiatorKey).requestClockBundle(\"buildtop_reference_clock\", freqMHz * (1000 * 1000))\n\n buildtopClock := refClkBundle.clock\n buildtopReset := WireInit(refClkBundle.reset)\n val dutReset = refClkBundle.reset.asAsyncReset\n\n val success = io.success\n\n lazyDut match { case d: HasTestHarnessFunctions =>\n d.harnessFunctions.foreach(_(this))\n }\n lazyDut match { case d: HasIOBinders =>\n ApplyHarnessBinders(this, d.lazySystem, d.portMap)\n }\n\n val implicitHarnessClockBundle = Wire(new ClockBundle(ClockBundleParameters()))\n implicitHarnessClockBundle.clock := clock\n implicitHarnessClockBundle.reset := reset\n p(HarnessClockInstantiatorKey).instantiateHarnessDividerPLL(implicitHarnessClockBundle)\n}\n\n", "groundtruth": "case object BuildTop extends Field[Parameters => LazyModule]((p: Parameters) => new ChipTop()(p))\n", "crossfile_context": "", "category": "Design Structure", "subcategory": "Parameterization and Configuration", "confidence": 0.7, "category_reason": "Config Field definition"} {"task_id": "Bossa", "path": "Bossa/generators/chipyard/src/main/scala/TestSuites.scala", "left_context": "package chipyard\n\nimport scala.collection.mutable.{LinkedHashSet}\n\nimport freechips.rocketchip.subsystem._\nimport freechips.rocketchip.tile.{XLen, TileParams}\nimport freechips.rocketchip.config.{Parameters, Field, Config}\nimport freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite}\n\n/**\n * A set of pre-chosen regression tests\n */\nobject RegressionTestSuites\n{\n val rv64RegrTestNames = LinkedHashSet(\n \"rv64ud-v-fcvt\",\n \"rv64ud-p-fdiv\",\n \"rv64ud-v-fadd\",\n \"rv64uf-v-fadd\",\n \"rv64um-v-mul\",\n \"rv64mi-p-breakpoint\",\n \"rv64uc-v-rvc\",\n \"rv64ud-v-structural\",\n \"rv64si-p-wfi\",\n \"rv64um-v-divw\",\n \"rv64ua-v-lrsc\",\n \"rv64ui-v-fence_i\",\n \"rv64ud-v-fcvt_w\",\n \"rv64uf-v-fmin\",\n \"rv64ui-v-sb\",\n \"rv64ua-v-amomax_d\",\n \"rv64ud-v-move\",\n \"rv64ud-v-fclass\",\n \"rv64ua-v-amoand_d\",\n \"rv64ua-v-amoxor_d\",\n \"rv64si-p-sbreak\",\n \"rv64ud-v-fmadd\",\n \"rv64uf-v-ldst\",\n \"rv64um-v-mulh\",\n \"rv64si-p-dirty\")\n\n val rv32RegrTestNames = LinkedHashSet(\n \"rv32mi-p-ma_addr\",\n \"rv32mi-p-csr\",\n \"rv32ui-p-sh\",\n \"rv32ui-p-lh\",\n \"rv32uc-p-rvc\",\n \"rv32mi-p-sbreak\",\n \"rv32ui-p-sll\")\n}\n\n/**\n * Helper functions to add BOOM or Rocket tests\n */\nclass TestSuiteHelper\n{\n import freechips.rocketchip.system.DefaultTestSuites._\n import RegressionTestSuites._\n val suites = collection.mutable.ListMap[String, RocketTestSuite]()\n", "right_context": " def addSuites(s: Seq[RocketTestSuite]) { s.foreach(addSuite) }\n\n /**\n * Add generic tests (asm, bmark, regression) for all cores.\n */\n def addGenericTestSuites(tiles: Seq[TileParams])(implicit p: Parameters) = {\n val xlen = p(XLen)\n tiles.find(_.hartId == 0).map { tileParams =>\n val coreParams = tileParams.core\n val vm = coreParams.useVM\n val env = if (vm) List(\"p\",\"v\") else List(\"p\")\n coreParams.fpu foreach { case cfg =>\n if (xlen == 32) {\n addSuites(env.map(rv32uf))\n if (cfg.fLen >= 64)\n addSuites(env.map(rv32ud))\n } else {\n addSuite(rv32udBenchmarks)\n addSuites(env.map(rv64uf))\n if (cfg.fLen >= 64)\n addSuites(env.map(rv64ud))\n }\n }\n if (coreParams.useAtomics) {\n if (tileParams.dcache.flatMap(_.scratch).isEmpty)\n addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))\n else\n addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))\n }\n if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))\n val (rvi, rvu) =\n if (xlen == 64) ((if (vm) rv64i else rv64pi), (if (coreParams.mulDiv.isDefined) rv64u else List(rv64ui)))\n else ((if (vm) rv32i else rv32pi), (if (coreParams.mulDiv.isDefined) rv32u else List(rv32ui)))\n\n addSuites(rvi.map(_(\"p\")))\n addSuites(rvu.map(_(\"p\")))\n addSuites((if (vm) List(\"v\") else List()).flatMap(env => rvu.map(_(env))))\n addSuite(benchmarks)\n addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))\n }\n }\n}\n\n/**\n * Config key of custom test suite.\n */\ncase object TestSuitesKey extends Field[(Seq[TileParams], TestSuiteHelper, Parameters) => String]((tiles, helper, p) => {\n helper.addGenericTestSuites(tiles)(p)\n // Return an empty string as makefile additional snippets\n \"\"\n})\n", "groundtruth": " def addSuite(s: RocketTestSuite) { suites += (s.makeTargetName -> s) }\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "Bossa", "path": "Bossa/generators/chipyard/src/main/scala/clocking/ClockDividerN.scala", "left_context": "// See LICENSE for license details.\n\npackage chipyard.clocking\n\nimport chisel3._\nimport chisel3.util._\n\nclass ClockDividerN(div: Int) extends BlackBox(Map(\"DIV\" -> div)) with HasBlackBoxResource {\n require(div > 0);\n val io = IO(new Bundle {\n val clk_out = Output(Clock())\n val clk_in = Input(Clock())\n })\n addResource(\"/vsrc/ClockDividerN.sv\")\n}\n\nobject ClockDivideByN {\n", "right_context": "", "groundtruth": " def apply(clockIn: Clock, div: Int): Clock = {\n val clockDivider = Module(new ClockDividerN(div))\n clockDivider.io.clk_in := clockIn\n clockDivider.io.clk_out\n }\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "Bossa", "path": "Bossa/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala", "left_context": "package chipyard.clocking\n\nimport chisel3._\n\nimport freechips.rocketchip.config.{Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.prci._\n\n/**\n * This sort of node can be used when it is a connectivity passthrough, but modifies\n * the flow of parameters (which may result in changing the names of the underlying signals).\n */\nclass ClockGroupParameterModifier(\n sourceFn: ClockGroupSourceParameters => ClockGroupSourceParameters = { m => m },\n sinkFn: ClockGroupSinkParameters => ClockGroupSinkParameters = { s => s })(\n implicit p: Parameters, v: ValName) extends LazyModule {\n val node = ClockGroupAdapterNode(sourceFn, sinkFn)\n lazy val module = new LazyRawModuleImp(this) {\n (node.out zip node.in).map { case ((o, _), (i, _)) =>\n (o.member.data zip i.member.data).foreach { case (oD, iD) => oD := iD }\n }\n }\n}\n\n/**\n * Pushes the ClockGroup's name into each member's name field as a prefix. This is\n * intended to be used before a ClockGroupAggregator so that sources from\n * different aggregated ClockGroups can be disambiguated by their names.\n */\nobject ClockGroupNamePrefixer {\n def apply()(implicit p: Parameters, valName: ValName): ClockGroupAdapterNode =\n LazyModule(new ClockGroupParameterModifier(sinkFn = { s => s.copy(members = s.members.zipWithIndex.map { case (m, idx) =>\n m.copy(name = m.name match {\n // This matches what the chisel would do if the names were not modified\n case Some(clockName) => Some(s\"${s.name}_${clockName}\")\n", "right_context": " })\n })})).node\n}\n\n/**\n * [Word from on high is that Strings are in...]\n * Overrides the take field of all clocks in a group, by attempting to apply a\n * series of assignment functions:\n * (name: String) => freq-in-MHz: Option[Double]\n * to each sink. Later functions that return non-empty values take priority.\n * The default if all functions return None.\n */\nobject ClockGroupFrequencySpecifier {\n def apply(\n assigners: Seq[(String) => Option[Double]],\n defaultFreq: Double)(\n implicit p: Parameters, valName: ValName): ClockGroupAdapterNode = {\n\n def lookupFrequencyForName(clock: ClockSinkParameters): ClockSinkParameters = {\n require(clock.name.nonEmpty, \"All clocks in clock group must have an assigned name\")\n val clockFreq = assigners.foldLeft(defaultFreq)(\n (currentFreq, candidateFunc) => candidateFunc(clock.name.get).getOrElse(currentFreq))\n\n clock.copy(take = clock.take match {\n case Some(cp) =>\n println(s\"Clock ${clock.name.get}: using diplomatically specified frequency of ${cp.freqMHz}.\")\n Some(cp)\n case None => Some(ClockParameters(clockFreq))\n })\n }\n\n LazyModule(new ClockGroupParameterModifier(sinkFn = { s => s.copy(members = s.members.map(lookupFrequencyForName)) })).node\n }\n}\n", "groundtruth": " case None => Some(s\"${s.name}_${idx}\")\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.7, "category_reason": "Scala case/match expression"} {"task_id": "Bossa", "path": "Bossa/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala", "left_context": "package chipyard.clocking\n\nimport chisel3._\n\nimport freechips.rocketchip.config.{Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.prci._\nimport freechips.rocketchip.util.ElaborationArtefacts\n\nimport scala.collection.mutable\nimport scala.collection.immutable.ListMap\n\n/**\n * TODO: figure out how much division is acceptable in our simulators and redefine this.\n */\nobject FrequencyUtils {\n /**\n * Adds up the squared error between the generated clocks (refClock / [integer] divider)\n * and the requested frequencies.\n *\n * @param refMHz The candidate reference clock\n * @param desiredFreqMHz A list of the requested output frequencies\n */\n def squaredError(refMHz: Double, desiredFreqMHz: List[Double], sum: Double = 0.0): Double = desiredFreqMHz match {\n case Nil => sum\n case desired :: xs =>\n val divider = Math.round(refMHz / desired)\n val termError = ((refMHz / divider) - desired) / desired\n squaredError(refMHz, xs, sum + termError * termError)\n }\n\n /**\n * Picks a candidate reference frequency by doing a brute-force search over\n * multiples of the fastest requested clock. Choose the smallest multiple that\n * has an RMS error (across all output frequencies) that is:\n * 1) zero or failing that,\n * 2) is within the relativeThreshold of the best or is less than the absoluteThreshold\n *\n * @param requestedOutputs The desired output frequencies in MHz\n * @param maximumAllowableFreqMHz The maximum allowable reference in MHz\n * @param relativeThreshold See above\n * @param absoluteThreshold See above\n */\n def computeReferenceAsMultipleOfFastestClock(\n requestedOutputs: Seq[ClockParameters],\n maximumAllowableFreqMHz: Double,\n relativeThreshold: Double = 1.10,\n absoluteThreshold: Double = 0.01): ClockParameters = {\n\n require(requestedOutputs.nonEmpty)\n require(!requestedOutputs.contains(0.0))\n val requestedFreqs = requestedOutputs.map(_.freqMHz)\n val fastestFreq = requestedFreqs.max\n require(fastestFreq <= maximumAllowableFreqMHz)\n\n val candidateFreqs =\n Seq.tabulate(Math.ceil(maximumAllowableFreqMHz / fastestFreq).toInt)(i => (i + 1) * fastestFreq)\n val errorTuples = candidateFreqs.map { f =>\n f -> Math.sqrt(squaredError(f, requestedFreqs.toList) / requestedFreqs.size)\n }\n val minError = errorTuples.map(_._2).min\n val viableFreqs = errorTuples.collect {\n case (f, error) if (error <= minError * relativeThreshold) || (minError > 0 && error < absoluteThreshold) => f\n }\n ClockParameters(viableFreqs.min)\n }\n}\n\nclass SimplePllConfiguration(\n name: String,\n val sinks: Seq[ClockSinkParameters],\n maximumAllowableFreqMHz: Double = 16000.0 ) {\n val referenceFreqMHz = FrequencyUtils.computeReferenceAsMultipleOfFastestClock(\n sinks.flatMap(_.take),\n maximumAllowableFreqMHz).freqMHz\n val sinkDividerMap = ListMap((sinks.map({s => (s, Math.round(referenceFreqMHz / s.take.get.freqMHz).toInt) })):_*)\n\n private val preamble = s\"\"\"\n |${name} Frequency Summary\n | Input Reference Frequency: ${referenceFreqMHz} MHz\\n\"\"\".stripMargin\n private val outputSummaries = sinkDividerMap.map { case (sink, division) =>\n val requested = sink.take.get.freqMHz\n val actual = referenceFreqMHz / division.toDouble\n", "right_context": " }\n\n val summaryString = preamble + outputSummaries.mkString(\"\\n\")\n def emitSummaries(): Unit = {\n ElaborationArtefacts.add(s\"${name}.freq-summary\", summaryString)\n println(summaryString)\n }\n def referenceSinkParams(): ClockSinkParameters = sinkDividerMap.find(_._2 == 1).get._1\n}\n\ncase class DividerOnlyClockGeneratorNode(pllName: String)(implicit valName: ValName)\n extends MixedNexusNode(ClockImp, ClockGroupImp)(\n dFn = { _ => ClockGroupSourceParameters() },\n uFn = { u =>\n require(u.size == 1)\n require(!u.head.members.contains(None),\n \"All output clocks in group must set their take parameters. Use a ClockGroupDealiaser\")\n ClockSinkParameters(\n name = Some(s\"${pllName}_reference_input\"),\n take = Some(ClockParameters(new SimplePllConfiguration(pllName, u.head.members).referenceFreqMHz))) }\n )\n\n/**\n * Generates a digital-divider-only PLL model that verilator can simulate.\n * Inspects all take-specified frequencies in the output ClockGroup, calculates a\n * fast reference clock (roughly LCM(requested frequencies)) which is passed up the\n * diplomatic graph, and then generates dividers for each unique requested\n * frequency.\n *\n * Output resets are not synchronized to generated clocks and should be\n * synchronized by the user in a manner they see fit.\n *\n */\n\nclass DividerOnlyClockGenerator(pllName: String)(implicit p: Parameters, valName: ValName) extends LazyModule {\n val node = DividerOnlyClockGeneratorNode(pllName)\n\n lazy val module = new LazyRawModuleImp(this) {\n require(node.out.size == 1, \"Idealized PLL expects to generate a single output clock group. Use a ClockGroupAggregator\")\n val (refClock, ClockEdgeParameters(_, refSinkParam, _, _)) = node.in.head\n val (outClocks, ClockGroupEdgeParameters(_, outSinkParams, _, _)) = node.out.head\n\n val referenceFreq = refSinkParam.take.get.freqMHz\n val pllConfig = new SimplePllConfiguration(pllName, outSinkParams.members)\n pllConfig.emitSummaries()\n\n val dividedClocks = mutable.HashMap[Int, Clock]()\n def instantiateDivider(div: Int): Clock = {\n val divider = Module(new ClockDividerN(div))\n divider.suggestName(s\"ClockDivideBy${div}\")\n divider.io.clk_in := refClock.clock\n dividedClocks(div) = divider.io.clk_out\n divider.io.clk_out\n }\n\n for (((sinkBName, sinkB), sinkP) <- outClocks.member.elements.zip(outSinkParams.members)) {\n val div = pllConfig.sinkDividerMap(sinkP)\n sinkB.clock := dividedClocks.getOrElse(div, instantiateDivider(div))\n // Reset handling and synchronization is expected to be handled by a downstream node\n sinkB.reset := refClock.reset\n }\n }\n}\n", "groundtruth": " s\" Output clock ${sink.name.get}, requested: ${requested} MHz, actual: ${actual} MHz (division of ${division})\"\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "Bossa", "path": "Bossa/generators/chipyard/src/main/scala/config/AbstractConfig.scala", "left_context": "package chipyard.config\n\nimport freechips.rocketchip.config.{Config}\n\n// --------------\n// Chipyard abstract (\"base\") configuration\n// NOTE: This configuration is NOT INSTANTIABLE, as it defines a empty system with no tiles\n//\n// The default set of IOBinders instantiate IOcells and ChipTop IOs for digital IO bundles.\n// The default set of HarnessBinders instantiate TestHarness hardware for interacting with ChipTop IOs\n// --------------\n\nclass AbstractConfig extends Config(\n // The HarnessBinders control generation of hardware in the TestHarness\n new chipyard.harness.WithUARTAdapter ++ // add UART adapter to display UART on stdout, if uart is present\n", "right_context": " new chipyard.harness.WithTieOffL2FBusAXI ++ // tie-off external AXI4 master, if present\n new chipyard.harness.WithTieOffCustomBootPin ++\n\n // The IOBinders instantiate ChipTop IOs to match desired digital IOs\n // IOCells are generated for \"Chip-like\" IOs, while simulation-only IOs are directly punched through\n new chipyard.iobinders.WithAXI4MemPunchthrough ++\n new chipyard.iobinders.WithAXI4MMIOPunchthrough ++\n new chipyard.iobinders.WithL2FBusAXI4Punchthrough ++\n new chipyard.iobinders.WithBlockDeviceIOPunchthrough ++\n new chipyard.iobinders.WithSerialTLIOCells ++\n new chipyard.iobinders.WithDebugIOCells ++\n new chipyard.iobinders.WithUARTIOCells ++\n new chipyard.iobinders.WithGPIOCells ++\n new chipyard.iobinders.WithUARTIOCells ++\n new chipyard.iobinders.WithSPIIOCells ++\n new chipyard.iobinders.WithTraceIOPunchthrough ++\n new chipyard.iobinders.WithExtInterruptIOCells ++\n new chipyard.iobinders.WithCustomBootPin ++\n\n new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM\n new chipyard.config.WithBootROM ++ // use default bootrom\n new chipyard.config.WithUART ++ // add a UART\n new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs\n new chipyard.config.WithNoSubsystemDrivenClocks ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks\n new chipyard.config.WithInheritBusFrequencyAssignments ++ // Unspecified clocks within a bus will receive the bus frequency if set\n new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // Unspecified frequencies with match the pbus frequency (which is always set)\n new chipyard.config.WithMemoryBusFrequency(100.0) ++ // Default 100 MHz mbus\n new chipyard.config.WithPeripheryBusFrequency(100.0) ++ // Default 100 MHz pbus\n new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port\n new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip)\n new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)\n new freechips.rocketchip.subsystem.WithBufferlessBroadcastHub ++ // bufferless (without L2 cache)\n new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts\n new chipyard.WithMulticlockCoherentBusTopology ++ // hierarchical buses including mbus+l2\n new freechips.rocketchip.system.BaseConfig) // \"base\" rocketchip system\n", "groundtruth": " new chipyard.harness.WithBlackBoxSimMem ++ // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled\n new chipyard.harness.WithSimSerial ++ // add external serial-adapter and RAM\n new chipyard.harness.WithSimDebug ++ // add SimJTAG or SimDTM adapters if debug module is enabled\n new chipyard.harness.WithGPIOTiedOff ++ // tie-off chiptop GPIOs, if GPIOs are present\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "Bossa", "path": "Bossa/generators/chipyard/src/main/scala/config/BoomConfigs.scala", "left_context": "package chipyard\n\nimport freechips.rocketchip.config.{Config}\n\n// ---------------------\n// BOOM Configs\n// ---------------------\n\n", "right_context": " new boom.common.WithNMediumBooms(1) ++ // medium boom config\n new chipyard.config.AbstractConfig)\n\nclass LargeBoomConfig extends Config(\n new boom.common.WithNLargeBooms(1) ++ // large boom config\n new chipyard.config.AbstractConfig)\n\nclass MegaBoomConfig extends Config(\n new boom.common.WithNMegaBooms(1) ++ // mega boom config\n new chipyard.config.AbstractConfig)\n\nclass DualSmallBoomConfig extends Config(\n new boom.common.WithNSmallBooms(2) ++ // 2 boom cores\n new chipyard.config.AbstractConfig)\n\n", "groundtruth": "class SmallBoomConfig extends Config(\n new boom.common.WithNSmallBooms(1) ++ // small boom config\n new chipyard.config.AbstractConfig)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "Bossa", "path": "Bossa/generators/chipyard/src/main/scala/config/RocketConfigs.scala", "left_context": "package chipyard\n\nimport freechips.rocketchip.config.{Config}\nimport freechips.rocketchip.diplomacy.{AsynchronousCrossing}\n\n// --------------\n// Rocket Configs\n// --------------\n\nclass RocketConfig extends Config(\n new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core\n new chipyard.config.AbstractConfig)\n\nclass TinyRocketConfig extends Config(\n new chipyard.config.WithTLSerialLocation(\n freechips.rocketchip.subsystem.FBUS,\n freechips.rocketchip.subsystem.PBUS) ++ // attach TL serial adapter to f/p busses\n new chipyard.WithMulticlockIncoherentBusTopology ++ // use incoherent bus topology\n", "right_context": "class dmiRocketConfig extends Config(\n new chipyard.harness.WithSerialAdapterTiedOff ++ // don't attach an external SimSerial\n new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port\n new freechips.rocketchip.subsystem.WithNBigCores(1) ++\n new chipyard.config.AbstractConfig)\n// DOC include end: DmiRocket\n\nclass LargeSPIFlashROMRocketConfig extends Config(\n new chipyard.harness.WithSimSPIFlashModel(true) ++ // add the SPI flash model in the harness (read-only)\n new chipyard.config.WithSPIFlash ++ // add the SPI flash controller\n new freechips.rocketchip.subsystem.WithNBigCores(1) ++\n new chipyard.config.AbstractConfig)\n\nclass SmallSPIFlashRocketConfig extends Config(\n new chipyard.harness.WithSimSPIFlashModel(false) ++ // add the SPI flash model in the harness (writeable)\n new chipyard.config.WithSPIFlash(0x100000) ++ // add the SPI flash controller (1 MiB)\n new freechips.rocketchip.subsystem.WithNBigCores(1) ++\n new chipyard.config.AbstractConfig)\n\nclass SimAXIRocketConfig extends Config(\n new chipyard.harness.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory, instead of default SimDRAM\n new freechips.rocketchip.subsystem.WithNBigCores(1) ++\n new chipyard.config.AbstractConfig)\n\nclass SimBlockDeviceRocketConfig extends Config(\n new chipyard.harness.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice\n new testchipip.WithBlockDevice ++ // add block-device module to peripherybus\n new freechips.rocketchip.subsystem.WithNBigCores(1) ++\n new chipyard.config.AbstractConfig)\n\nclass BlockDeviceModelRocketConfig extends Config(\n new chipyard.harness.WithBlockDeviceModel ++ // drive block-device IOs with a BlockDeviceModel\n new testchipip.WithBlockDevice ++ // add block-device module to periphery bus\n new freechips.rocketchip.subsystem.WithNBigCores(1) ++\n new chipyard.config.AbstractConfig)\n\n// DOC include start: GPIORocketConfig\nclass GPIORocketConfig extends Config(\n new chipyard.config.WithGPIO ++ // add GPIOs to the peripherybus\n new freechips.rocketchip.subsystem.WithNBigCores(1) ++\n new chipyard.config.AbstractConfig)\n// DOC include end: GPIORocketConfig\n\nclass QuadRocketConfig extends Config(\n new freechips.rocketchip.subsystem.WithNBigCores(4) ++ // quad-core (4 RocketTiles)\n new chipyard.config.AbstractConfig)\n\nclass RV32RocketConfig extends Config(\n new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit\n new freechips.rocketchip.subsystem.WithNBigCores(1) ++\n new chipyard.config.AbstractConfig)\n\nclass GB1MemoryRocketConfig extends Config(\n new freechips.rocketchip.subsystem.WithExtMemSize((1<<30) * 1L) ++ // use 1GB simulated external memory\n new freechips.rocketchip.subsystem.WithNBigCores(1) ++\n new chipyard.config.AbstractConfig)\n\n// DOC include start: l1scratchpadrocket\nclass ScratchpadOnlyRocketConfig extends Config(\n new testchipip.WithSerialPBusMem ++\n new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port\n new freechips.rocketchip.subsystem.WithNBanks(0) ++\n new freechips.rocketchip.subsystem.WithNoMemPort ++\n new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 DCache scratchpad as base phys mem\n new freechips.rocketchip.subsystem.WithNBigCores(1) ++\n new chipyard.config.AbstractConfig)\n// DOC include end: l1scratchpadrocket\n\nclass L1ScratchpadRocketConfig extends Config(\n new chipyard.config.WithRocketICacheScratchpad ++ // use rocket ICache scratchpad\n new chipyard.config.WithRocketDCacheScratchpad ++ // use rocket DCache scratchpad\n new freechips.rocketchip.subsystem.WithNBigCores(1) ++\n new chipyard.config.AbstractConfig)\n\n// DOC include start: mbusscratchpadrocket\nclass MbusScratchpadRocketConfig extends Config(\n new testchipip.WithBackingScratchpad ++ // add mbus backing scratchpad\n new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port\n new freechips.rocketchip.subsystem.WithNBigCores(1) ++\n new chipyard.config.AbstractConfig)\n// DOC include end: mbusscratchpadrocket\n\n// DOC include start: RingSystemBusRocket\nclass RingSystemBusRocketConfig extends Config(\n new testchipip.WithRingSystemBus ++ // Ring-topology system bus\n new freechips.rocketchip.subsystem.WithNBigCores(1) ++\n new chipyard.config.AbstractConfig)\n// DOC include end: RingSystemBusRocket\n\nclass MMIORocketConfig extends Config(\n new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++ // add default external master port\n new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port\n new freechips.rocketchip.subsystem.WithNBigCores(1) ++\n new chipyard.config.AbstractConfig)\n\nclass MulticlockRocketConfig extends Config(\n new freechips.rocketchip.subsystem.WithNBigCores(1) ++\n // Frequency specifications\n new chipyard.config.WithTileFrequency(1600.0) ++ // Matches the maximum frequency of U540\n new chipyard.config.WithSystemBusFrequency(800.0) ++ // Ditto\n new chipyard.config.WithMemoryBusFrequency(1000.0) ++ // 2x the U540 freq (appropriate for a 128b Mbus)\n new chipyard.config.WithPeripheryBusFrequency(100) ++ // Retains the default pbus frequency\n new chipyard.config.WithSystemBusFrequencyAsDefault ++ // All unspecified clock frequencies, notably the implicit clock, will use the sbus freq (800 MHz)\n // Crossing specifications\n new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS\n new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS\n new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore\n new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS\n new chipyard.config.AbstractConfig)\n\nclass TestChipMulticlockRocketConfig extends Config(\n new freechips.rocketchip.subsystem.WithNBigCores(1) ++\n new chipyard.config.WithTestChipBusFreqs ++\n new chipyard.config.AbstractConfig)\n\nclass LBWIFRocketConfig extends Config(\n new testchipip.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory\n new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory\n new freechips.rocketchip.subsystem.WithNBigCores(1) ++\n new chipyard.config.AbstractConfig)\n\n// DOC include start: MulticlockAXIOverSerialConfig\nclass MulticlockAXIOverSerialConfig extends Config(\n new chipyard.config.WithSystemBusFrequencyAsDefault ++\n new chipyard.config.WithSystemBusFrequency(250) ++\n new chipyard.config.WithPeripheryBusFrequency(250) ++\n new chipyard.config.WithMemoryBusFrequency(250) ++\n new chipyard.config.WithFrontBusFrequency(50) ++\n new chipyard.config.WithTileFrequency(500, Some(1)) ++\n new chipyard.config.WithTileFrequency(250, Some(0)) ++\n\n new chipyard.config.WithFbusToSbusCrossingType(AsynchronousCrossing()) ++\n new testchipip.WithAsynchronousSerialSlaveCrossing ++\n new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(\n AsynchronousCrossing().depth,\n AsynchronousCrossing().sourceSync) ++\n\n new chipyard.harness.WithSimAXIMemOverSerialTL ++ // add SimDRAM DRAM model for axi4 backing memory over the SerDes link, if axi4 mem is enabled\n new chipyard.config.WithSerialTLBackingMemory ++ // remove axi4 mem port in favor of SerialTL memory\n\n new freechips.rocketchip.subsystem.WithNBigCores(2) ++\n new chipyard.config.AbstractConfig)\n// DOC include end: MulticlockAXIOverSerialConfig\n", "groundtruth": " new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$\n new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory\n new freechips.rocketchip.subsystem.With1TinyCore ++ // single tiny rocket-core\n new chipyard.config.AbstractConfig)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "Bossa", "path": "Bossa/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala", "left_context": "// See LICENSE for license details.\n// Based on Rocket Chip's stage implementation\n\npackage chipyard.stage\n\nimport freechips.rocketchip.stage.ConfigsAnnotation\nimport firrtl.options.{HasShellOptions, ShellOption}\n\n/** This hijacks the existing ConfigAnnotation to accept the legacy _-delimited format */\nprivate[stage] object UnderscoreDelimitedConfigsAnnotation extends HasShellOptions {\n override val options = Seq(\n new ShellOption[String](\n longOption = \"legacy-configs\",\n toAnnotationSeq = a => {\n val split = a.split(':')\n assert(split.length == 2)\n val packageName = split.head\n val configs = split.last.split(\"_\")\n", "right_context": " },\n helpText = \"A string of underscore-delimited configs (configs have decreasing precendence from left to right).\",\n shortOption = Some(\"LC\")\n )\n )\n}\n\n", "groundtruth": " Seq(new ConfigsAnnotation(configs map { config => if (config contains \".\") s\"${config}\" else s\"${packageName}.${config}\" } ))\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "Bossa", "path": "Bossa/generators/chipyard/src/main/scala/stage/ChipyardCli.scala", "left_context": "// See LICENSE for license details.\n// Based on Rocket Chip's stage implementation\n\npackage chipyard.stage\n\nimport firrtl.options.Shell\n\n", "right_context": "\n parser.note(\"Chipyard Generator Options\")\n Seq(\n UnderscoreDelimitedConfigsAnnotation\n )\n .foreach(_.addOptions(parser))\n}\n", "groundtruth": "trait ChipyardCli { this: Shell =>\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "Bossa", "path": "Bossa/generators/chipyard/src/main/scala/stage/ChipyardStage.scala", "left_context": "// See LICENSE for license details.\n// Based on Rocket Chip's stage implementation\n\npackage chipyard.stage\n\nimport chisel3.stage.{ChiselCli, ChiselStage}\nimport firrtl.options.PhaseManager.PhaseDependency\nimport firrtl.options.{Phase, PreservesAll, Shell}\nimport firrtl.stage.FirrtlCli\nimport freechips.rocketchip.stage.RocketChipCli\nimport freechips.rocketchip.system.RocketChipStage\n\nimport firrtl.options.{Phase, PhaseManager, PreservesAll, Shell, Stage, StageError, StageMain, Dependency}\nimport firrtl.options.phases.DeletedWrapper\n\nclass ChipyardStage extends ChiselStage with PreservesAll[Phase] {\n override val shell = new Shell(\"chipyard\") with ChipyardCli with RocketChipCli with ChiselCli with FirrtlCli\n override val targets: Seq[PhaseDependency] = Seq(\n Dependency[freechips.rocketchip.stage.phases.Checks],\n Dependency[freechips.rocketchip.stage.phases.TransformAnnotations],\n Dependency[freechips.rocketchip.stage.phases.PreElaboration],\n Dependency[chisel3.stage.phases.Checks],\n Dependency[chisel3.stage.phases.Elaborate],\n Dependency[freechips.rocketchip.stage.phases.GenerateROMs],\n Dependency[chisel3.stage.phases.AddImplicitOutputFile],\n Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile],\n Dependency[chisel3.stage.phases.MaybeAspectPhase],\n Dependency[chisel3.stage.phases.Emitter],\n Dependency[chisel3.stage.phases.Convert],\n Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos],\n Dependency[freechips.rocketchip.stage.phases.AddDefaultTests],\n Dependency[chipyard.stage.phases.AddDefaultTests],\n", "right_context": "}\n", "groundtruth": " Dependency[chipyard.stage.phases.GenerateTestSuiteMakefrags],\n Dependency[freechips.rocketchip.stage.phases.GenerateArtefacts],\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "Bossa", "path": "Bossa/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala", "left_context": "// See LICENSE for license details.\n// Based on Rocket Chip's stage implementation\n\npackage chipyard.stage.phases\n\nimport scala.util.Try\nimport scala.collection.mutable\n\nimport chipsalliance.rocketchip.config.Parameters\nimport chisel3.stage.phases.Elaborate\nimport firrtl.AnnotationSeq\nimport firrtl.annotations.{Annotation, NoTargetAnnotation}\nimport firrtl.options.{Phase, PreservesAll, Dependency}\nimport firrtl.options.Viewer.view\nimport freechips.rocketchip.stage.RocketChipOptions\nimport freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation}\nimport freechips.rocketchip.system.{RocketTestSuite, TestGeneration}\nimport freechips.rocketchip.subsystem.{TilesLocated, InSubsystem}\nimport freechips.rocketchip.util.HasRocketChipStageUtils\nimport freechips.rocketchip.tile.XLen\n\nimport chipyard.TestSuiteHelper\nimport chipyard.TestSuitesKey\n\nclass AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils {\n // Make sure we run both after RocketChip's version of this phase, and Rocket Chip's annotation emission phase\n // because the RocketTestSuiteAnnotation is not serializable (but is not marked as such).\n override val prerequisites = Seq(\n Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos],\n Dependency[freechips.rocketchip.stage.phases.AddDefaultTests])\n override val dependents = Seq(Dependency[freechips.rocketchip.stage.phases.GenerateTestSuiteMakefrags])\n\n private def addTestSuiteAnnotations(implicit p: Parameters): Seq[Annotation] = {\n val annotations = mutable.ArrayBuffer[Annotation]()\n val suiteHelper = new TestSuiteHelper\n // Use Xlen as a proxy for detecting if we are a processor-like target\n // The underlying test suites expect this field to be defined\n val tileParams = p(TilesLocated(InSubsystem)) map (tp => tp.tileParams)\n", "right_context": " val (testSuiteAnnos, oAnnos) = annotations.partition {\n case RocketTestSuiteAnnotation(_) => true\n case o => false\n }\n implicit val p = getConfig(view[RocketChipOptions](annotations).configNames.get).toInstance\n addTestSuiteAnnotations ++ oAnnos\n }\n}\n", "groundtruth": " if (p.lift(XLen).nonEmpty)\n // If a custom test suite is set up, use the custom test suite\n annotations += CustomMakefragSnippet(p(TestSuitesKey).apply(tileParams, suiteHelper, p))\n\n RocketTestSuiteAnnotation(suiteHelper.suites.values.toSeq) +: annotations\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "Bossa", "path": "Bossa/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala", "left_context": "// See LICENSE for license details.\n// Based on Rocket Chip's stage implementation\n\npackage chipyard.stage.phases\n\nimport scala.collection.mutable\n\nimport firrtl.AnnotationSeq\nimport firrtl.annotations.{Annotation, NoTargetAnnotation}\nimport firrtl.options.{Phase, PreservesAll, StageOptions, Unserializable, Dependency}\nimport firrtl.options.Viewer.view\nimport freechips.rocketchip.stage.RocketChipOptions\nimport freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation}\nimport freechips.rocketchip.system.TestGeneration\nimport freechips.rocketchip.util.HasRocketChipStageUtils\n\ntrait MakefragSnippet { self: Annotation =>\n def toMakefrag: String\n}\n\n", "right_context": "\n/** Generates a make script to run tests in [[RocketTestSuiteAnnotation]]. */\nclass GenerateTestSuiteMakefrags extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils {\n\n // Our annotations tend not to be serializable, but are not marked as such.\n override val prerequisites = Seq(Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos],\n Dependency[chipyard.stage.phases.AddDefaultTests])\n\n override def transform(annotations: AnnotationSeq): AnnotationSeq = {\n val targetDir = view[StageOptions](annotations).targetDir\n val fileName = s\"${view[RocketChipOptions](annotations).longName.get}.d\"\n\n val makefragBuilder = new mutable.StringBuilder()\n val outputAnnotations = annotations.flatMap {\n case RocketTestSuiteAnnotation(tests) =>\n // Unfortunately the gen method of TestGeneration is rocketchip package\n // private, so we either have to copy code in or use the stateful form\n TestGeneration.addSuites(tests)\n None\n case a: MakefragSnippet =>\n makefragBuilder :+ (\"\\n\" + a.toMakefrag)\n None\n case a => Some(a)\n }\n writeOutputFile(targetDir, fileName, TestGeneration.generateMakeFrag ++ makefragBuilder.toString)\n outputAnnotations\n }\n}\n", "groundtruth": "case class CustomMakefragSnippet(val toMakefrag: String) extends NoTargetAnnotation with MakefragSnippet with Unserializable\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Type Definition", "confidence": 0.7, "category_reason": "Case class definition"} {"task_id": "Bossa", "path": "Bossa/generators/chipyard/src/main/scala/unittest/TestHarness.scala", "left_context": "package chipyard.unittest\n\nimport chisel3._\nimport freechips.rocketchip.config.Parameters\n\n", "right_context": "", "groundtruth": "class TestHarness(implicit val p: Parameters) extends Module {\n val io = IO(new Bundle { val success = Output(Bool()) })\n io.success := Module(new UnitTestSuite).io.finished\n}\n", "crossfile_context": "", "category": "Design Structure", "subcategory": "Top-level Structure", "confidence": 0.85, "category_reason": "Module class definition"} {"task_id": "Bossa", "path": "Bossa/generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala", "left_context": "package chipyard.unittest\n\nimport freechips.rocketchip.config.Parameters\nimport freechips.rocketchip.util.{ElaborationArtefacts, PlusArgArtefacts}\n\n", "right_context": "", "groundtruth": "class UnitTestSuite(implicit p: Parameters) extends freechips.rocketchip.unittest.UnitTestSuite {\n ElaborationArtefacts.add(\"plusArgs\", PlusArgArtefacts.serialize_cHeader)\n}\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "Bossa", "path": "Bossa/generators/chipyard/src/test/scala/clocking/SimplePllConfigurationSpec.scala", "left_context": "//See LICENSE for license details.\npackage chipyard.clocking\n\nimport freechips.rocketchip.prci._\n\nclass SimplePllConfigurationSpec extends org.scalatest.flatspec.AnyFlatSpec {\n\n def genConf(freqMHz: Iterable[Double]): SimplePllConfiguration = new SimplePllConfiguration(\n \"testPLL\",\n freqMHz.map({ f => ClockSinkParameters(\n name = Some(s\"desiredFreq_$f\"),\n take = Some(ClockParameters(f))) }).toSeq,\n maximumAllowableFreqMHz = 16000.0)\n\n def trySuccessfulConf(requestedFreqs: Seq[Double], expected: Double): Unit = {\n val freqStr = requestedFreqs.mkString(\", \")\n", "right_context": " val conf = genConf(requestedFreqs)\n conf.emitSummaries\n assert(expected == conf.referenceFreqMHz)\n }\n }\n\n trySuccessfulConf(Seq(3200.0, 1600.0, 1000.0, 100.0), 16000.0)\n trySuccessfulConf(Seq(3200.0, 1600.0), 3200.0)\n trySuccessfulConf(Seq(3200.0, 1066.7), 3200.0)\n trySuccessfulConf(Seq(100, 50, 6.67), 100)\n trySuccessfulConf(Seq(1, 2, 3, 5, 7, 11, 13).map(_ * 10.0), 1560.0)\n}\n", "groundtruth": " it should s\"select a reference of ${expected} MHz for ${freqStr} MHz\" in { \n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "riscv-mini", "path": "riscv-mini/src/main/scala/junctions/nasti.scala", "left_context": "// See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage junctions\nimport chisel3._\nimport chisel3.util._\n\nobject NastiConstants {\n // These are all fixed by the standard:\n val LenBits = 8\n val SizeBits = 3\n val BurstBits = 2\n val LockBits = 1\n val CacheBits = 4\n val ProtBits = 3\n val QosBits = 4\n val RespBits = 2\n\n def CacheReadAllocate = 8.U(CacheBits.W)\n def CacheWriteAllocate = 4.U(CacheBits.W)\n def CacheModifiable = 2.U(CacheBits.W)\n def CacheBufferable = 1.U(CacheBits.W)\n\n def ProtPrivileged = 1.U(ProtBits.W)\n def ProtInsecure = 2.U(ProtBits.W)\n def ProtInstruction = 4.U(ProtBits.W)\n\n def BurstFixed = 0.U(BurstBits.W)\n def BurstIncr = 1.U(BurstBits.W)\n def BurstWrap = 2.U(BurstBits.W)\n\n", "right_context": " def RespExOkay = 1.U(RespBits.W)\n def RespSlvErr = 2.U(RespBits.W)\n def RespDevErr = 3.U(RespBits.W)\n}\n\ncase class NastiBundleParameters(\n addrBits: Int,\n dataBits: Int,\n idBits: Int) {\n require(dataBits >= 8, s\"AXI4 data bits must be >= 8 (got $dataBits)\")\n require(addrBits >= 1, s\"AXI4 addr bits must be >= 1 (got $addrBits)\")\n require(idBits >= 1, s\"AXI4 id bits must be >= 1 (got $idBits)\")\n require(isPow2(dataBits), s\"AXI4 data bits must be pow2 (got $dataBits)\")\n}\n\n/** aka the AW/AR channel */\nclass NastiAddressBundle(params: NastiBundleParameters) extends Bundle {\n val id = UInt(params.idBits.W)\n val addr = UInt(params.addrBits.W)\n val len = UInt(NastiConstants.LenBits.W) // number of beats - 1\n val size = UInt(NastiConstants.SizeBits.W) // bytes in beat = 2^size\n val burst = UInt(NastiConstants.BurstBits.W)\n val lock = UInt(NastiConstants.LockBits.W)\n val cache = UInt(NastiConstants.CacheBits.W)\n val prot = UInt(NastiConstants.ProtBits.W)\n val qos = UInt(NastiConstants.QosBits.W) // 0=no QoS, bigger = higher priority\n}\n\nobject NastiAddressBundle {\n def apply(params: NastiBundleParameters)(id: UInt, addr: UInt, size: UInt, len: UInt = 0.U): NastiAddressBundle = {\n val aw = Wire(new NastiAddressBundle(params))\n aw.id := id\n aw.addr := addr\n aw.len := len\n aw.size := size\n aw.burst := NastiConstants.BurstIncr\n aw.lock := false.B\n aw.cache := 0.U\n aw.prot := 0.U\n aw.qos := 0.U\n aw\n }\n}\n\n/** aka the W-channel */\nclass NastiWriteDataBundle(params: NastiBundleParameters) extends Bundle {\n // id removed\n val data = UInt(params.dataBits.W)\n val strb = UInt((params.dataBits / 8).W)\n val last = Bool()\n}\n\nobject NastiWriteDataBundle {\n def apply(\n params: NastiBundleParameters\n )(data: UInt,\n strb: Option[UInt] = None,\n last: Bool = true.B\n ): NastiWriteDataBundle = {\n val w = Wire(new NastiWriteDataBundle(params))\n w.strb := strb.getOrElse(Fill(params.dataBits / 8, 1.U))\n w.data := data\n w.last := last\n w\n }\n}\n\n/** aka the R-channel */\nclass NastiReadDataBundle(params: NastiBundleParameters) extends Bundle {\n val id = UInt(params.idBits.W)\n val data = UInt(params.dataBits.W)\n val resp = UInt(NastiConstants.RespBits.W)\n val last = Bool()\n}\n\nobject NastiReadDataBundle {\n def apply(\n params: NastiBundleParameters\n )(id: UInt,\n data: UInt,\n last: Bool = true.B,\n resp: UInt = 0.U\n ): NastiReadDataBundle = {\n val r = Wire(new NastiReadDataBundle(params))\n r.id := id\n r.data := data\n r.last := last\n r.resp := resp\n r\n }\n}\n\n/** aka the B-channel */\nclass NastiWriteResponseBundle(params: NastiBundleParameters) extends Bundle {\n val id = UInt(params.idBits.W)\n val resp = UInt(NastiConstants.RespBits.W)\n}\n\nobject NastiWriteResponseBundle {\n def apply(params: NastiBundleParameters)(id: UInt, resp: UInt = 0.U): NastiWriteResponseBundle = {\n val b = Wire(new NastiWriteResponseBundle(params))\n b.id := id\n b.resp := resp\n b\n }\n}\n\nclass NastiBundle(params: NastiBundleParameters) extends Bundle {\n val aw = Decoupled(new NastiAddressBundle(params))\n val w = Decoupled(new NastiWriteDataBundle(params))\n val b = Flipped(Decoupled(new NastiWriteResponseBundle(params)))\n val ar = Decoupled(new NastiAddressBundle(params))\n val r = Flipped(Decoupled(new NastiReadDataBundle(params)))\n}\n\nclass NastiArbiterIO(params: NastiBundleParameters, arbN: Int) extends Bundle {\n val master = Flipped(Vec(arbN, new NastiBundle(params)))\n val slave = new NastiBundle(params)\n}\n\n/** Arbitrate among arbN masters requesting to a single slave */\nclass NastiArbiter(params: NastiBundleParameters, val arbN: Int) extends Module {\n val io = new NastiArbiterIO(params, arbN)\n\n if (arbN > 1) {\n val arbIdBits = log2Up(arbN)\n\n val ar_arb = Module(new RRArbiter(new NastiAddressBundle(params), arbN))\n val aw_arb = Module(new RRArbiter(new NastiAddressBundle(params), arbN))\n\n val slave_r_arb_id = io.slave.r.bits.id(arbIdBits - 1, 0)\n val slave_b_arb_id = io.slave.b.bits.id(arbIdBits - 1, 0)\n\n val w_chosen = Reg(UInt(arbIdBits.W))\n val w_done = RegInit(true.B)\n\n when(aw_arb.io.out.fire) {\n w_chosen := aw_arb.io.chosen\n w_done := false.B\n }\n\n when(io.slave.w.fire && io.slave.w.bits.last) {\n w_done := true.B\n }\n\n for (i <- 0 until arbN) {\n val m_ar = io.master(i).ar\n val m_aw = io.master(i).aw\n val m_r = io.master(i).r\n val m_b = io.master(i).b\n val a_ar = ar_arb.io.in(i)\n val a_aw = aw_arb.io.in(i)\n val m_w = io.master(i).w\n\n a_ar <> m_ar\n a_aw <> m_aw\n\n m_r.valid := io.slave.r.valid && slave_r_arb_id === i.U\n m_r.bits := io.slave.r.bits\n m_r.bits.id := io.slave.r.bits.id >> arbIdBits.U\n\n m_b.valid := io.slave.b.valid && slave_b_arb_id === i.U\n m_b.bits := io.slave.b.bits\n m_b.bits.id := io.slave.b.bits.id >> arbIdBits.U\n\n m_w.ready := io.slave.w.ready && w_chosen === i.U && !w_done\n }\n\n io.slave.r.ready := io.master(slave_r_arb_id).r.ready\n io.slave.b.ready := io.master(slave_b_arb_id).b.ready\n\n io.slave.w.bits := io.master(w_chosen).w.bits\n io.slave.w.valid := io.master(w_chosen).w.valid && !w_done\n\n io.slave.ar <> ar_arb.io.out\n\n io.slave.aw.bits <> aw_arb.io.out.bits\n io.slave.aw.valid := aw_arb.io.out.valid && w_done\n aw_arb.io.out.ready := io.slave.aw.ready && w_done\n\n } else { io.slave <> io.master.head }\n}\n", "groundtruth": " def RespOkay = 0.U(RespBits.W)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "riscv-mini", "path": "riscv-mini/src/main/scala/mini/Alu.scala", "left_context": "// See LICENSE for license details.\n\npackage mini\n\nimport chisel3._\nimport chisel3.util._\n\nobject Alu {\n val ALU_ADD = 0.U(4.W)\n val ALU_SUB = 1.U(4.W)\n val ALU_AND = 2.U(4.W)\n val ALU_OR = 3.U(4.W)\n val ALU_XOR = 4.U(4.W)\n val ALU_SLT = 5.U(4.W)\n val ALU_SLL = 6.U(4.W)\n val ALU_SLTU = 7.U(4.W)\n val ALU_SRL = 8.U(4.W)\n val ALU_SRA = 9.U(4.W)\n val ALU_COPY_A = 10.U(4.W)\n val ALU_COPY_B = 11.U(4.W)\n val ALU_XXX = 15.U(4.W)\n}\n\nclass AluIO(width: Int) extends Bundle {\n val A = Input(UInt(width.W))\n val B = Input(UInt(width.W))\n val alu_op = Input(UInt(4.W))\n val out = Output(UInt(width.W))\n val sum = Output(UInt(width.W))\n}\n\nimport mini.Alu._\n\ntrait Alu extends Module {\n def width: Int\n val io: AluIO\n}\n\nclass AluSimple(val width: Int) extends Alu {\n", "right_context": "\n io.out := MuxLookup(io.alu_op, io.B)(\n Seq(\n ALU_ADD -> (io.A + io.B),\n ALU_SUB -> (io.A - io.B),\n ALU_SRA -> (io.A.asSInt >> shamt).asUInt,\n ALU_SRL -> (io.A >> shamt),\n ALU_SLL -> (io.A << shamt),\n ALU_SLT -> (io.A.asSInt < io.B.asSInt),\n ALU_SLTU -> (io.A < io.B),\n ALU_AND -> (io.A & io.B),\n ALU_OR -> (io.A | io.B),\n ALU_XOR -> (io.A ^ io.B),\n ALU_COPY_A -> io.A\n )\n )\n\n io.sum := io.A + Mux(io.alu_op(0), -io.B, io.B)\n}\n\nclass AluArea(val width: Int) extends Alu {\n val io = IO(new AluIO(width))\n val sum = io.A + Mux(io.alu_op(0), -io.B, io.B)\n val cmp =\n Mux(io.A(width - 1) === io.B(width - 1), sum(width - 1), Mux(io.alu_op(1), io.B(width - 1), io.A(width - 1)))\n val shamt = io.B(4, 0).asUInt\n val shin = Mux(io.alu_op(3), io.A, Reverse(io.A))\n val shiftr = (Cat(io.alu_op(0) && shin(width - 1), shin).asSInt >> shamt)(width - 1, 0)\n val shiftl = Reverse(shiftr)\n\n val out =\n Mux(\n io.alu_op === ALU_ADD || io.alu_op === ALU_SUB,\n sum,\n Mux(\n io.alu_op === ALU_SLT || io.alu_op === ALU_SLTU,\n cmp,\n Mux(\n io.alu_op === ALU_SRA || io.alu_op === ALU_SRL,\n shiftr,\n Mux(\n io.alu_op === ALU_SLL,\n shiftl,\n Mux(\n io.alu_op === ALU_AND,\n io.A & io.B,\n Mux(\n io.alu_op === ALU_OR,\n io.A | io.B,\n Mux(io.alu_op === ALU_XOR, io.A ^ io.B, Mux(io.alu_op === ALU_COPY_A, io.A, io.B))\n )\n )\n )\n )\n )\n )\n\n io.out := out\n io.sum := sum\n}\n", "groundtruth": " val io = IO(new AluIO(width))\n\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.9, "category_reason": "IO bundle definition"} {"task_id": "riscv-mini", "path": "riscv-mini/src/main/scala/mini/BrCond.scala", "left_context": "// See LICENSE for license details.\n\npackage mini\n\nimport chisel3._\nimport mini.Control._\n\nclass BrCondIO(xlen: Int) extends Bundle {\n val rs1 = Input(UInt(xlen.W))\n val rs2 = Input(UInt(xlen.W))\n val br_type = Input(UInt(3.W))\n val taken = Output(Bool())\n}\n\ntrait BrCond extends Module {\n def xlen: Int\n val io: BrCondIO\n}\n\nclass BrCondSimple(val xlen: Int) extends BrCond {\n val io = IO(new BrCondIO(xlen))\n val eq = io.rs1 === io.rs2\n val neq = !eq\n val lt = io.rs1.asSInt < io.rs2.asSInt\n val ge = !lt\n val ltu = io.rs1 < io.rs2\n val geu = !ltu\n io.taken :=\n ((io.br_type === BR_EQ) && eq) ||\n ((io.br_type === BR_NE) && neq) ||\n ((io.br_type === BR_LT) && lt) ||\n ((io.br_type === BR_GE) && ge) ||\n ((io.br_type === BR_LTU) && ltu) ||\n ((io.br_type === BR_GEU) && geu)\n}\n\nclass BrCondArea(val xlen: Int) extends BrCond {\n val io = IO(new BrCondIO(xlen))\n val diff = io.rs1 - io.rs2\n val neq = diff.orR\n val eq = !neq\n val isSameSign = io.rs1(xlen - 1) === io.rs2(xlen - 1)\n", "right_context": " ((io.br_type === BR_EQ) && eq) ||\n ((io.br_type === BR_NE) && neq) ||\n ((io.br_type === BR_LT) && lt) ||\n ((io.br_type === BR_GE) && ge) ||\n ((io.br_type === BR_LTU) && ltu) ||\n ((io.br_type === BR_GEU) && geu)\n}\n", "groundtruth": " val lt = Mux(isSameSign, diff(xlen - 1), io.rs1(xlen - 1))\n val ltu = Mux(isSameSign, diff(xlen - 1), io.rs2(xlen - 1))\n val ge = !lt\n", "crossfile_context": "", "category": "Computation Block", "subcategory": "Mux and Selection Logic", "confidence": 0.85, "category_reason": "Mux selection"} {"task_id": "riscv-mini", "path": "riscv-mini/src/main/scala/mini/CSR.scala", "left_context": "// See LICENSE for license details.\n\npackage mini\n\nimport chisel3._\nimport chisel3.util._\n\nobject CSR {\n val N = 0.U(3.W)\n val W = 1.U(3.W)\n val S = 2.U(3.W)\n val C = 3.U(3.W)\n val P = 4.U(3.W)\n\n // Supports machine & user modes\n val PRV_U = 0x0.U(2.W)\n val PRV_M = 0x3.U(2.W)\n\n // User-level CSR addrs\n val cycle = 0xc00.U(12.W)\n val time = 0xc01.U(12.W)\n val instret = 0xc02.U(12.W)\n val cycleh = 0xc80.U(12.W)\n val timeh = 0xc81.U(12.W)\n val instreth = 0xc82.U(12.W)\n\n // Supervisor-level CSR addrs\n val cyclew = 0x900.U(12.W)\n val timew = 0x901.U(12.W)\n val instretw = 0x902.U(12.W)\n val cyclehw = 0x980.U(12.W)\n val timehw = 0x981.U(12.W)\n val instrethw = 0x982.U(12.W)\n\n // Machine-level CSR addrs\n // Machine Information Registers\n val mcpuid = 0xf00.U(12.W)\n val mimpid = 0xf01.U(12.W)\n val mhartid = 0xf10.U(12.W)\n // Machine Trap Setup\n val mstatus = 0x300.U(12.W)\n val mtvec = 0x301.U(12.W)\n val mtdeleg = 0x302.U(12.W)\n val mie = 0x304.U(12.W)\n val mtimecmp = 0x321.U(12.W)\n // Machine Timers and Counters\n val mtime = 0x701.U(12.W)\n val mtimeh = 0x741.U(12.W)\n // Machine Trap Handling\n val mscratch = 0x340.U(12.W)\n val mepc = 0x341.U(12.W)\n val mcause = 0x342.U(12.W)\n val mbadaddr = 0x343.U(12.W)\n val mip = 0x344.U(12.W)\n // Machine HITF\n val mtohost = 0x780.U(12.W)\n val mfromhost = 0x781.U(12.W)\n\n val regs = List(\n cycle,\n time,\n instret,\n cycleh,\n timeh,\n instreth,\n cyclew,\n timew,\n instretw,\n cyclehw,\n timehw,\n instrethw,\n mcpuid,\n mimpid,\n mhartid,\n mtvec,\n mtdeleg,\n mie,\n mtimecmp,\n mtime,\n mtimeh,\n mscratch,\n mepc,\n mcause,\n mbadaddr,\n mip,\n mtohost,\n mfromhost,\n mstatus\n )\n}\n\nobject Cause {\n val InstAddrMisaligned = 0x0.U\n val IllegalInst = 0x2.U\n val Breakpoint = 0x3.U\n val LoadAddrMisaligned = 0x4.U\n val StoreAddrMisaligned = 0x6.U\n val Ecall = 0x8.U\n}\n\nclass CSRIO(xlen: Int) extends Bundle {\n val stall = Input(Bool())\n val cmd = Input(UInt(3.W))\n val in = Input(UInt(xlen.W))\n val out = Output(UInt(xlen.W))\n // Excpetion\n val pc = Input(UInt(xlen.W))\n val addr = Input(UInt(xlen.W))\n val inst = Input(UInt(xlen.W))\n val illegal = Input(Bool())\n val st_type = Input(UInt(2.W))\n val ld_type = Input(UInt(3.W))\n val pc_check = Input(Bool())\n val expt = Output(Bool())\n val evec = Output(UInt(xlen.W))\n val epc = Output(UInt(xlen.W))\n // HTIF\n val host = new HostIO(xlen)\n}\n\nclass CSR(val xlen: Int) extends Module {\n val io = IO(new CSRIO(xlen))\n\n val csr_addr = io.inst(31, 20)\n val rs1_addr = io.inst(19, 15)\n\n // user counters\n val time = RegInit(0.U(xlen.W))\n val timeh = RegInit(0.U(xlen.W))\n val cycle = RegInit(0.U(xlen.W))\n val cycleh = RegInit(0.U(xlen.W))\n val instret = RegInit(0.U(xlen.W))\n val instreth = RegInit(0.U(xlen.W))\n\n val mcpuid = Cat(\n 0.U(2.W) /* RV32I */,\n 0.U((xlen - 28).W),\n (1 << ('I' - 'A') /* Base ISA */ |\n 1 << ('U' - 'A') /* User Mode */ ).U(26.W)\n )\n val mimpid = 0.U(xlen.W) // not implemented\n val mhartid = 0.U(xlen.W) // only one hart\n\n // interrupt enable stack\n val PRV = RegInit(CSR.PRV_M)\n val PRV1 = RegInit(CSR.PRV_M)\n val PRV2 = 0.U(2.W)\n val PRV3 = 0.U(2.W)\n val IE = RegInit(false.B)\n val IE1 = RegInit(false.B)\n val IE2 = false.B\n val IE3 = false.B\n // virtualization management field\n val VM = 0.U(5.W)\n // memory privilege\n val MPRV = false.B\n // extention context status\n val XS = 0.U(2.W)\n val FS = 0.U(2.W)\n val SD = 0.U(1.W)\n val mstatus = Cat(SD, 0.U((xlen - 23).W), VM, MPRV, XS, FS, PRV3, IE3, PRV2, IE2, PRV1, IE1, PRV, IE)\n val mtvec = Consts.PC_EVEC.U(xlen.W)\n val mtdeleg = 0x0.U(xlen.W)\n\n // interrupt registers\n val MTIP = RegInit(false.B)\n val HTIP = false.B\n val STIP = false.B\n val MTIE = RegInit(false.B)\n val HTIE = false.B\n val STIE = false.B\n val MSIP = RegInit(false.B)\n val HSIP = false.B\n val SSIP = false.B\n val MSIE = RegInit(false.B)\n val HSIE = false.B\n val SSIE = false.B\n val mip = Cat(0.U((xlen - 8).W), MTIP, HTIP, STIP, false.B, MSIP, HSIP, SSIP, false.B)\n val mie = Cat(0.U((xlen - 8).W), MTIE, HTIE, STIE, false.B, MSIE, HSIE, SSIE, false.B)\n\n val mtimecmp = Reg(UInt(xlen.W))\n\n val mscratch = Reg(UInt(xlen.W))\n\n val mepc = Reg(UInt(xlen.W))\n val mcause = Reg(UInt(xlen.W))\n val mbadaddr = Reg(UInt(xlen.W))\n\n val mtohost = RegInit(0.U(xlen.W))\n val mfromhost = Reg(UInt(xlen.W))\n io.host.tohost := mtohost\n when(io.host.fromhost.valid) {\n mfromhost := io.host.fromhost.bits\n }\n\n val csrFile = Seq(\n BitPat(CSR.cycle) -> cycle,\n BitPat(CSR.time) -> time,\n BitPat(CSR.instret) -> instret,\n BitPat(CSR.cycleh) -> cycleh,\n BitPat(CSR.timeh) -> timeh,\n BitPat(CSR.instreth) -> instreth,\n BitPat(CSR.cyclew) -> cycle,\n BitPat(CSR.timew) -> time,\n BitPat(CSR.instretw) -> instret,\n BitPat(CSR.cyclehw) -> cycleh,\n BitPat(CSR.timehw) -> timeh,\n BitPat(CSR.instrethw) -> instreth,\n BitPat(CSR.mcpuid) -> mcpuid,\n BitPat(CSR.mimpid) -> mimpid,\n BitPat(CSR.mhartid) -> mhartid,\n BitPat(CSR.mtvec) -> mtvec,\n BitPat(CSR.mtdeleg) -> mtdeleg,\n BitPat(CSR.mie) -> mie,\n BitPat(CSR.mtimecmp) -> mtimecmp,\n BitPat(CSR.mtime) -> time,\n BitPat(CSR.mtimeh) -> timeh,\n BitPat(CSR.mscratch) -> mscratch,\n BitPat(CSR.mepc) -> mepc,\n BitPat(CSR.mcause) -> mcause,\n BitPat(CSR.mbadaddr) -> mbadaddr,\n BitPat(CSR.mip) -> mip,\n BitPat(CSR.mtohost) -> mtohost,\n BitPat(CSR.mfromhost) -> mfromhost,\n BitPat(CSR.mstatus) -> mstatus\n )\n\n io.out := Lookup(csr_addr, 0.U, csrFile).asUInt\n\n val privValid = csr_addr(9, 8) <= PRV\n val privInst = io.cmd === CSR.P\n val isEcall = privInst && !csr_addr(0) && !csr_addr(8)\n val isEbreak = privInst && csr_addr(0) && !csr_addr(8)\n val isEret = privInst && !csr_addr(0) && csr_addr(8)\n val csrValid = csrFile.map(_._1 === csr_addr).reduce(_ || _)\n val csrRO = csr_addr(11, 10).andR || csr_addr === CSR.mtvec || csr_addr === CSR.mtdeleg\n val wen = io.cmd === CSR.W || io.cmd(1) && rs1_addr.orR\n val wdata = MuxLookup(io.cmd, 0.U)(\n Seq(\n CSR.W -> io.in,\n CSR.S -> (io.out | io.in),\n CSR.C -> (io.out & ~io.in)\n )\n )\n val iaddrInvalid = io.pc_check && io.addr(1)\n val laddrInvalid = MuxLookup(io.ld_type, false.B)(\n Seq(Control.LD_LW -> io.addr(1, 0).orR, Control.LD_LH -> io.addr(0), Control.LD_LHU -> io.addr(0))\n )\n val saddrInvalid =\n MuxLookup(io.st_type, false.B)(Seq(Control.ST_SW -> io.addr(1, 0).orR, Control.ST_SH -> io.addr(0)))\n io.expt := io.illegal || iaddrInvalid || laddrInvalid || saddrInvalid ||\n io.cmd(1, 0).orR && (!csrValid || !privValid) || wen && csrRO ||\n (privInst && !privValid) || isEcall || isEbreak\n io.evec := mtvec + (PRV << 6)\n io.epc := mepc\n\n // Counters\n time := time + 1.U\n when(time.andR) { timeh := timeh + 1.U }\n cycle := cycle + 1.U\n when(cycle.andR) { cycleh := cycleh + 1.U }\n val isInstRet = io.inst =/= Instructions.NOP && (!io.expt || isEcall || isEbreak) && !io.stall\n when(isInstRet) { instret := instret + 1.U }\n when(isInstRet && instret.andR) { instreth := instreth + 1.U }\n\n when(!io.stall) {\n when(io.expt) {\n mepc := io.pc >> 2 << 2\n mcause := Mux(\n iaddrInvalid,\n Cause.InstAddrMisaligned,\n Mux(\n laddrInvalid,\n Cause.LoadAddrMisaligned,\n Mux(\n saddrInvalid,\n Cause.StoreAddrMisaligned,\n Mux(isEcall, Cause.Ecall + PRV, Mux(isEbreak, Cause.Breakpoint, Cause.IllegalInst))\n )\n )\n )\n PRV := CSR.PRV_M\n IE := false.B\n PRV1 := PRV\n IE1 := IE\n when(iaddrInvalid || laddrInvalid || saddrInvalid) { mbadaddr := io.addr }\n }.elsewhen(isEret) {\n PRV := PRV1\n IE := IE1\n PRV1 := CSR.PRV_U\n IE1 := true.B\n }.elsewhen(wen) {\n when(csr_addr === CSR.mstatus) {\n PRV1 := wdata(5, 4)\n IE1 := wdata(3)\n PRV := wdata(2, 1)\n IE := wdata(0)\n }\n .elsewhen(csr_addr === CSR.mip) {\n MTIP := wdata(7)\n MSIP := wdata(3)\n }\n .elsewhen(csr_addr === CSR.mie) {\n MTIE := wdata(7)\n MSIE := wdata(3)\n }\n .elsewhen(csr_addr === CSR.mtime) { time := wdata }\n .elsewhen(csr_addr === CSR.mtimeh) { timeh := wdata }\n .elsewhen(csr_addr === CSR.mtimecmp) { mtimecmp := wdata }\n .elsewhen(csr_addr === CSR.mscratch) { mscratch := wdata }\n .elsewhen(csr_addr === CSR.mepc) { mepc := wdata >> 2.U << 2.U }\n .elsewhen(csr_addr === CSR.mcause) { mcause := wdata & (BigInt(1) << (xlen - 1) | 0xf).U }\n .elsewhen(csr_addr === CSR.mbadaddr) { mbadaddr := wdata }\n .elsewhen(csr_addr === CSR.mtohost) { mtohost := wdata }\n .elsewhen(csr_addr === CSR.mfromhost) { mfromhost := wdata }\n .elsewhen(csr_addr === CSR.cyclew) { cycle := wdata }\n .elsewhen(csr_addr === CSR.timew) { time := wdata }\n .elsewhen(csr_addr === CSR.instretw) { instret := wdata }\n", "right_context": " .elsewhen(csr_addr === CSR.timehw) { timeh := wdata }\n .elsewhen(csr_addr === CSR.instrethw) { instreth := wdata }\n }\n }\n}\n", "groundtruth": " .elsewhen(csr_addr === CSR.cyclehw) { cycleh := wdata }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": ".elsewhen conditional"} {"task_id": "riscv-mini", "path": "riscv-mini/src/main/scala/mini/Cache.scala", "left_context": "// See LICENSE for license details.\n\npackage mini\n\nimport chisel3._\nimport chisel3.util._\nimport junctions._\n\nclass CacheReq(addrWidth: Int, dataWidth: Int) extends Bundle {\n val addr = UInt(addrWidth.W)\n val data = UInt(dataWidth.W)\n val mask = UInt((dataWidth / 8).W)\n}\n\nclass CacheResp(dataWidth: Int) extends Bundle {\n val data = UInt(dataWidth.W)\n}\n\nclass CacheIO(addrWidth: Int, dataWidth: Int) extends Bundle {\n val abort = Input(Bool())\n val req = Flipped(Valid(new CacheReq(addrWidth, dataWidth)))\n val resp = Valid(new CacheResp(dataWidth))\n}\n\nclass CacheModuleIO(nastiParams: NastiBundleParameters, addrWidth: Int, dataWidth: Int) extends Bundle {\n val cpu = new CacheIO(addrWidth, dataWidth)\n val nasti = new NastiBundle(nastiParams)\n}\n\n", "right_context": "\nclass MetaData(tagLength: Int) extends Bundle {\n val tag = UInt(tagLength.W)\n}\n\nobject CacheState extends ChiselEnum {\n val sIdle, sReadCache, sWriteCache, sWriteBack, sWriteAck, sRefillReady, sRefill = Value\n}\n\nclass Cache(val p: CacheConfig, val nasti: NastiBundleParameters, val xlen: Int) extends Module {\n // local parameters\n val nSets = p.nSets\n val bBytes = p.blockBytes\n val bBits = bBytes << 3\n val blen = log2Ceil(bBytes)\n val slen = log2Ceil(nSets)\n val tlen = xlen - (slen + blen)\n val nWords = bBits / xlen\n val wBytes = xlen / 8\n val byteOffsetBits = log2Ceil(wBytes)\n val dataBeats = bBits / nasti.dataBits\n\n val io = IO(new CacheModuleIO(nasti, addrWidth = xlen, dataWidth = xlen))\n\n // cache states\n import CacheState._\n val state = RegInit(sIdle)\n // memory\n val v = RegInit(0.U(nSets.W))\n val d = RegInit(0.U(nSets.W))\n val metaMem = SyncReadMem(nSets, new MetaData(tlen))\n val dataMem = Seq.fill(nWords)(SyncReadMem(nSets, Vec(wBytes, UInt(8.W))))\n\n val addr_reg = Reg(chiselTypeOf(io.cpu.req.bits.addr))\n val cpu_data = Reg(chiselTypeOf(io.cpu.req.bits.data))\n val cpu_mask = Reg(chiselTypeOf(io.cpu.req.bits.mask))\n\n // Counters\n require(dataBeats > 0)\n val (read_count, read_wrap_out) = Counter(io.nasti.r.fire, dataBeats)\n val (write_count, write_wrap_out) = Counter(io.nasti.w.fire, dataBeats)\n\n val is_idle = state === sIdle\n val is_read = state === sReadCache\n val is_write = state === sWriteCache\n val is_alloc = state === sRefill && read_wrap_out\n val is_alloc_reg = RegNext(is_alloc)\n\n val hit = Wire(Bool())\n val wen = is_write && (hit || is_alloc_reg) && !io.cpu.abort || is_alloc\n val ren = !wen && (is_idle || is_read) && io.cpu.req.valid\n val ren_reg = RegNext(ren)\n\n val addr = io.cpu.req.bits.addr\n val idx = addr(slen + blen - 1, blen)\n val tag_reg = addr_reg(xlen - 1, slen + blen)\n val idx_reg = addr_reg(slen + blen - 1, blen)\n val off_reg = addr_reg(blen - 1, byteOffsetBits)\n\n val rmeta = metaMem.read(idx, ren)\n val rdata = Cat((dataMem.map(_.read(idx, ren).asUInt)).reverse)\n val rdata_buf = RegEnable(rdata, ren_reg)\n val refill_buf = Reg(Vec(dataBeats, UInt(nasti.dataBits.W)))\n val read = Mux(is_alloc_reg, refill_buf.asUInt, Mux(ren_reg, rdata, rdata_buf))\n\n hit := v(idx_reg) && rmeta.tag === tag_reg\n\n // Read Mux\n io.cpu.resp.bits.data := VecInit.tabulate(nWords)(i => read((i + 1) * xlen - 1, i * xlen))(off_reg)\n io.cpu.resp.valid := is_idle || is_read && hit || is_alloc_reg && !cpu_mask.orR\n\n when(io.cpu.resp.valid) {\n addr_reg := addr\n cpu_data := io.cpu.req.bits.data\n cpu_mask := io.cpu.req.bits.mask\n }\n\n val wmeta = Wire(new MetaData(tlen))\n wmeta.tag := tag_reg\n\n val wmask = Mux(!is_alloc, (cpu_mask << Cat(off_reg, 0.U(byteOffsetBits.W))).zext, (-1).S)\n val wdata = Mux(\n !is_alloc,\n Fill(nWords, cpu_data),\n if (refill_buf.size == 1) io.nasti.r.bits.data\n else Cat(io.nasti.r.bits.data, Cat(refill_buf.init.reverse))\n )\n when(wen) {\n v := v.bitSet(idx_reg, true.B)\n d := d.bitSet(idx_reg, !is_alloc)\n when(is_alloc) {\n metaMem.write(idx_reg, wmeta)\n }\n dataMem.zipWithIndex.foreach {\n case (mem, i) =>\n val data = VecInit.tabulate(wBytes)(k => wdata(i * xlen + (k + 1) * 8 - 1, i * xlen + k * 8))\n mem.write(idx_reg, data, wmask((i + 1) * wBytes - 1, i * wBytes).asBools)\n mem.suggestName(s\"dataMem_${i}\")\n }\n }\n\n io.nasti.ar.bits := NastiAddressBundle(nasti)(\n 0.U,\n (Cat(tag_reg, idx_reg) << blen.U).asUInt,\n log2Up(nasti.dataBits / 8).U,\n (dataBeats - 1).U\n )\n io.nasti.ar.valid := false.B\n // read data\n io.nasti.r.ready := state === sRefill\n when(io.nasti.r.fire) {\n refill_buf(read_count) := io.nasti.r.bits.data\n }\n\n // write addr\n io.nasti.aw.bits := NastiAddressBundle(nasti)(\n 0.U,\n (Cat(rmeta.tag, idx_reg) << blen.U).asUInt,\n log2Up(nasti.dataBits / 8).U,\n (dataBeats - 1).U\n )\n io.nasti.aw.valid := false.B\n // write data\n io.nasti.w.bits := NastiWriteDataBundle(nasti)(\n VecInit.tabulate(dataBeats)(i => read((i + 1) * nasti.dataBits - 1, i * nasti.dataBits))(write_count),\n None,\n write_wrap_out\n )\n io.nasti.w.valid := false.B\n // write resp\n io.nasti.b.ready := false.B\n\n // Cache FSM\n val is_dirty = v(idx_reg) && d(idx_reg)\n switch(state) {\n is(sIdle) {\n when(io.cpu.req.valid) {\n state := Mux(io.cpu.req.bits.mask.orR, sWriteCache, sReadCache)\n }\n }\n is(sReadCache) {\n when(hit) {\n when(io.cpu.req.valid) {\n state := Mux(io.cpu.req.bits.mask.orR, sWriteCache, sReadCache)\n }.otherwise {\n state := sIdle\n }\n }.otherwise {\n io.nasti.aw.valid := is_dirty\n io.nasti.ar.valid := !is_dirty\n when(io.nasti.aw.fire) {\n state := sWriteBack\n }.elsewhen(io.nasti.ar.fire) {\n state := sRefill\n }\n }\n }\n is(sWriteCache) {\n when(hit || is_alloc_reg || io.cpu.abort) {\n state := sIdle\n }.otherwise {\n io.nasti.aw.valid := is_dirty\n io.nasti.ar.valid := !is_dirty\n when(io.nasti.aw.fire) {\n state := sWriteBack\n }.elsewhen(io.nasti.ar.fire) {\n state := sRefill\n }\n }\n }\n is(sWriteBack) {\n io.nasti.w.valid := true.B\n when(write_wrap_out) {\n state := sWriteAck\n }\n }\n is(sWriteAck) {\n io.nasti.b.ready := true.B\n when(io.nasti.b.fire) {\n state := sRefillReady\n }\n }\n is(sRefillReady) {\n io.nasti.ar.valid := true.B\n when(io.nasti.ar.fire) {\n state := sRefill\n }\n }\n is(sRefill) {\n when(read_wrap_out) {\n state := Mux(cpu_mask.orR, sWriteCache, sIdle)\n }\n }\n }\n}\n", "groundtruth": "case class CacheConfig(nWays: Int, nSets: Int, blockBytes: Int)\n", "crossfile_context": "", "category": "Design Structure", "subcategory": "Parameterization and Configuration", "confidence": 0.85, "category_reason": "Params/Config case class"} {"task_id": "riscv-mini", "path": "riscv-mini/src/main/scala/mini/Config.scala", "left_context": "// See LICENSE for license details.\n\npackage mini\n\nimport junctions.NastiBundleParameters\n\n", "right_context": "\nobject MiniConfig {\n def apply(): Config = {\n val xlen = 32\n Config(\n core = CoreConfig(\n xlen = xlen,\n makeAlu = new AluArea(_),\n makeBrCond = new BrCondArea(_),\n makeImmGen = new ImmGenWire(_)\n ),\n cache = CacheConfig(\n nWays = 1,\n nSets = 256,\n blockBytes = 4 * (xlen / 8) // 4 * 32 bits = 16B\n ),\n nasti = NastiBundleParameters(\n addrBits = 32,\n dataBits = 64,\n idBits = 5\n )\n )\n }\n}\n", "groundtruth": "case class Config(core: CoreConfig, cache: CacheConfig, nasti: NastiBundleParameters)\n", "crossfile_context": "", "category": "Design Structure", "subcategory": "Parameterization and Configuration", "confidence": 0.85, "category_reason": "Params/Config case class"} {"task_id": "riscv-mini", "path": "riscv-mini/src/main/scala/mini/Control.scala", "left_context": "// See LICENSE for license details.\n\npackage mini\n\nimport chisel3._\nimport chisel3.util._\n\nobject Control {\n val Y = true.B\n val N = false.B\n\n // pc_sel\n val PC_4 = 0.U(2.W)\n val PC_ALU = 1.U(2.W)\n val PC_0 = 2.U(2.W)\n val PC_EPC = 3.U(2.W)\n\n // A_sel\n val A_XXX = 0.U(1.W)\n val A_PC = 0.U(1.W)\n val A_RS1 = 1.U(1.W)\n\n // B_sel\n val B_XXX = 0.U(1.W)\n val B_IMM = 0.U(1.W)\n val B_RS2 = 1.U(1.W)\n\n // imm_sel\n val IMM_X = 0.U(3.W)\n val IMM_I = 1.U(3.W)\n val IMM_S = 2.U(3.W)\n val IMM_U = 3.U(3.W)\n val IMM_J = 4.U(3.W)\n val IMM_B = 5.U(3.W)\n val IMM_Z = 6.U(3.W)\n\n // br_type\n val BR_XXX = 0.U(3.W)\n val BR_LTU = 1.U(3.W)\n val BR_LT = 2.U(3.W)\n val BR_EQ = 3.U(3.W)\n val BR_GEU = 4.U(3.W)\n val BR_GE = 5.U(3.W)\n val BR_NE = 6.U(3.W)\n\n // st_type\n val ST_XXX = 0.U(2.W)\n val ST_SW = 1.U(2.W)\n val ST_SH = 2.U(2.W)\n val ST_SB = 3.U(2.W)\n\n // ld_type\n val LD_XXX = 0.U(3.W)\n val LD_LW = 1.U(3.W)\n val LD_LH = 2.U(3.W)\n val LD_LB = 3.U(3.W)\n val LD_LHU = 4.U(3.W)\n val LD_LBU = 5.U(3.W)\n\n // wb_sel\n val WB_ALU = 0.U(2.W)\n val WB_MEM = 1.U(2.W)\n val WB_PC4 = 2.U(2.W)\n val WB_CSR = 3.U(2.W)\n\n import Alu._\n import Instructions._\n\n // format: off\n val default =\n // kill wb_en illegal?\n // pc_sel A_sel B_sel imm_sel alu_op br_type | st_type ld_type wb_sel | csr_cmd |\n // | | | | | | | | | | | | |\n List(PC_4 , A_XXX, B_XXX, IMM_X, ALU_XXX , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, N, CSR.N, Y)\n val map = Array(\n LUI -> List(PC_4 , A_PC, B_IMM, IMM_U, ALU_COPY_B, BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),\n AUIPC -> List(PC_4 , A_PC, B_IMM, IMM_U, ALU_ADD , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),\n JAL -> List(PC_ALU, A_PC, B_IMM, IMM_J, ALU_ADD , BR_XXX, Y, ST_XXX, LD_XXX, WB_PC4, Y, CSR.N, N),\n JALR -> List(PC_ALU, A_RS1, B_IMM, IMM_I, ALU_ADD , BR_XXX, Y, ST_XXX, LD_XXX, WB_PC4, Y, CSR.N, N),\n BEQ -> List(PC_4 , A_PC, B_IMM, IMM_B, ALU_ADD , BR_EQ , N, ST_XXX, LD_XXX, WB_ALU, N, CSR.N, N),\n BNE -> List(PC_4 , A_PC, B_IMM, IMM_B, ALU_ADD , BR_NE , N, ST_XXX, LD_XXX, WB_ALU, N, CSR.N, N),\n BLT -> List(PC_4 , A_PC, B_IMM, IMM_B, ALU_ADD , BR_LT , N, ST_XXX, LD_XXX, WB_ALU, N, CSR.N, N),\n BGE -> List(PC_4 , A_PC, B_IMM, IMM_B, ALU_ADD , BR_GE , N, ST_XXX, LD_XXX, WB_ALU, N, CSR.N, N),\n BLTU -> List(PC_4 , A_PC, B_IMM, IMM_B, ALU_ADD , BR_LTU, N, ST_XXX, LD_XXX, WB_ALU, N, CSR.N, N),\n BGEU -> List(PC_4 , A_PC, B_IMM, IMM_B, ALU_ADD , BR_GEU, N, ST_XXX, LD_XXX, WB_ALU, N, CSR.N, N),\n LB -> List(PC_0 , A_RS1, B_IMM, IMM_I, ALU_ADD , BR_XXX, Y, ST_XXX, LD_LB , WB_MEM, Y, CSR.N, N),\n LH -> List(PC_0 , A_RS1, B_IMM, IMM_I, ALU_ADD , BR_XXX, Y, ST_XXX, LD_LH , WB_MEM, Y, CSR.N, N),\n LW -> List(PC_0 , A_RS1, B_IMM, IMM_I, ALU_ADD , BR_XXX, Y, ST_XXX, LD_LW , WB_MEM, Y, CSR.N, N),\n LBU -> List(PC_0 , A_RS1, B_IMM, IMM_I, ALU_ADD , BR_XXX, Y, ST_XXX, LD_LBU, WB_MEM, Y, CSR.N, N),\n LHU -> List(PC_0 , A_RS1, B_IMM, IMM_I, ALU_ADD , BR_XXX, Y, ST_XXX, LD_LHU, WB_MEM, Y, CSR.N, N),\n SB -> List(PC_4 , A_RS1, B_IMM, IMM_S, ALU_ADD , BR_XXX, N, ST_SB , LD_XXX, WB_ALU, N, CSR.N, N),\n SH -> List(PC_4 , A_RS1, B_IMM, IMM_S, ALU_ADD , BR_XXX, N, ST_SH , LD_XXX, WB_ALU, N, CSR.N, N),\n SW -> List(PC_4 , A_RS1, B_IMM, IMM_S, ALU_ADD , BR_XXX, N, ST_SW , LD_XXX, WB_ALU, N, CSR.N, N),\n ADDI -> List(PC_4 , A_RS1, B_IMM, IMM_I, ALU_ADD , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),\n SLTI -> List(PC_4 , A_RS1, B_IMM, IMM_I, ALU_SLT , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),\n SLTIU -> List(PC_4 , A_RS1, B_IMM, IMM_I, ALU_SLTU , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),\n XORI -> List(PC_4 , A_RS1, B_IMM, IMM_I, ALU_XOR , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),\n ORI -> List(PC_4 , A_RS1, B_IMM, IMM_I, ALU_OR , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),\n ANDI -> List(PC_4 , A_RS1, B_IMM, IMM_I, ALU_AND , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),\n SLLI -> List(PC_4 , A_RS1, B_IMM, IMM_I, ALU_SLL , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),\n SRLI -> List(PC_4 , A_RS1, B_IMM, IMM_I, ALU_SRL , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),\n SRAI -> List(PC_4 , A_RS1, B_IMM, IMM_I, ALU_SRA , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),\n ADD -> List(PC_4 , A_RS1, B_RS2, IMM_X, ALU_ADD , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),\n SUB -> List(PC_4 , A_RS1, B_RS2, IMM_X, ALU_SUB , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),\n SLL -> List(PC_4 , A_RS1, B_RS2, IMM_X, ALU_SLL , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),\n SLT -> List(PC_4 , A_RS1, B_RS2, IMM_X, ALU_SLT , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),\n SLTU -> List(PC_4 , A_RS1, B_RS2, IMM_X, ALU_SLTU , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),\n XOR -> List(PC_4 , A_RS1, B_RS2, IMM_X, ALU_XOR , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),\n SRL -> List(PC_4 , A_RS1, B_RS2, IMM_X, ALU_SRL , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),\n SRA -> List(PC_4 , A_RS1, B_RS2, IMM_X, ALU_SRA , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),\n OR -> List(PC_4 , A_RS1, B_RS2, IMM_X, ALU_OR , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),\n AND -> List(PC_4 , A_RS1, B_RS2, IMM_X, ALU_AND , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N),\n FENCE -> List(PC_4 , A_XXX, B_XXX, IMM_X, ALU_XXX , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, N, CSR.N, N),\n FENCEI-> List(PC_0 , A_XXX, B_XXX, IMM_X, ALU_XXX , BR_XXX, Y, ST_XXX, LD_XXX, WB_ALU, N, CSR.N, N),\n CSRRW -> List(PC_0 , A_RS1, B_XXX, IMM_X, ALU_COPY_A, BR_XXX, Y, ST_XXX, LD_XXX, WB_CSR, Y, CSR.W, N),\n CSRRS -> List(PC_0 , A_RS1, B_XXX, IMM_X, ALU_COPY_A, BR_XXX, Y, ST_XXX, LD_XXX, WB_CSR, Y, CSR.S, N),\n CSRRC -> List(PC_0 , A_RS1, B_XXX, IMM_X, ALU_COPY_A, BR_XXX, Y, ST_XXX, LD_XXX, WB_CSR, Y, CSR.C, N),\n CSRRWI-> List(PC_0 , A_XXX, B_XXX, IMM_Z, ALU_XXX , BR_XXX, Y, ST_XXX, LD_XXX, WB_CSR, Y, CSR.W, N),\n CSRRSI-> List(PC_0 , A_XXX, B_XXX, IMM_Z, ALU_XXX , BR_XXX, Y, ST_XXX, LD_XXX, WB_CSR, Y, CSR.S, N),\n CSRRCI-> List(PC_0 , A_XXX, B_XXX, IMM_Z, ALU_XXX , BR_XXX, Y, ST_XXX, LD_XXX, WB_CSR, Y, CSR.C, N),\n ECALL -> List(PC_4 , A_XXX, B_XXX, IMM_X, ALU_XXX , BR_XXX, N, ST_XXX, LD_XXX, WB_CSR, N, CSR.P, N),\n EBREAK-> List(PC_4 , A_XXX, B_XXX, IMM_X, ALU_XXX , BR_XXX, N, ST_XXX, LD_XXX, WB_CSR, N, CSR.P, N),\n ERET -> List(PC_EPC, A_XXX, B_XXX, IMM_X, ALU_XXX , BR_XXX, Y, ST_XXX, LD_XXX, WB_CSR, N, CSR.P, N),\n WFI -> List(PC_4 , A_XXX, B_XXX, IMM_X, ALU_XXX , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, N, CSR.N, N))\n // format: on\n}\n\nclass ControlSignals extends Bundle {\n val inst = Input(UInt(32.W))\n val pc_sel = Output(UInt(2.W))\n val inst_kill = Output(Bool())\n val A_sel = Output(UInt(1.W))\n val B_sel = Output(UInt(1.W))\n val imm_sel = Output(UInt(3.W))\n", "right_context": " val br_type = Output(UInt(3.W))\n val st_type = Output(UInt(2.W))\n val ld_type = Output(UInt(3.W))\n val wb_sel = Output(UInt(2.W))\n val wb_en = Output(Bool())\n val csr_cmd = Output(UInt(3.W))\n val illegal = Output(Bool())\n}\n\nclass Control extends Module {\n val io = IO(new ControlSignals)\n val ctrlSignals = ListLookup(io.inst, Control.default, Control.map)\n\n // Control signals for Fetch\n io.pc_sel := ctrlSignals(0)\n io.inst_kill := ctrlSignals(6).asBool\n\n // Control signals for Execute\n io.A_sel := ctrlSignals(1)\n io.B_sel := ctrlSignals(2)\n io.imm_sel := ctrlSignals(3)\n io.alu_op := ctrlSignals(4)\n io.br_type := ctrlSignals(5)\n io.st_type := ctrlSignals(7)\n\n // Control signals for Write Back\n io.ld_type := ctrlSignals(8)\n io.wb_sel := ctrlSignals(9)\n io.wb_en := ctrlSignals(10).asBool\n io.csr_cmd := ctrlSignals(11)\n io.illegal := ctrlSignals(12)\n}\n", "groundtruth": " val alu_op = Output(UInt(4.W))\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.8, "category_reason": "Input or Output in Bundle/IO context"} {"task_id": "riscv-mini", "path": "riscv-mini/src/main/scala/mini/Core.scala", "left_context": "// See LICENSE for license details.\n\npackage mini\n\nimport chisel3._\nimport chisel3.util.Valid\n\ncase class CoreConfig(\n xlen: Int,\n makeAlu: Int => Alu = new AluSimple(_),\n makeBrCond: Int => BrCond = new BrCondSimple(_),\n makeImmGen: Int => ImmGen = new ImmGenWire(_))\n\nclass HostIO(xlen: Int) extends Bundle {\n val fromhost = Flipped(Valid(UInt(xlen.W)))\n val tohost = Output(UInt(xlen.W))\n}\n\nclass CoreIO(xlen: Int) extends Bundle {\n val host = new HostIO(xlen)\n val icache = Flipped(new CacheIO(xlen, xlen))\n val dcache = Flipped(new CacheIO(xlen, xlen))\n}\n\nclass Core(val conf: CoreConfig) extends Module {\n val io = IO(new CoreIO(conf.xlen))\n val dpath = Module(new Datapath(conf))\n val ctrl = Module(new Control)\n\n io.host <> dpath.io.host\n dpath.io.icache <> io.icache\n dpath.io.dcache <> io.dcache\n", "right_context": "", "groundtruth": " dpath.io.ctrl <> ctrl.io\n}\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.55, "category_reason": "Code near IO/Bundle"} {"task_id": "riscv-mini", "path": "riscv-mini/src/main/scala/mini/Datapath.scala", "left_context": "// See LICENSE for license details.\n\npackage mini\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.BundleLiterals._\n\nobject Consts {\n val PC_START = 0x200\n val PC_EVEC = 0x100\n}\n\nclass DatapathIO(xlen: Int) extends Bundle {\n val host = new HostIO(xlen)\n val icache = Flipped(new CacheIO(xlen, xlen))\n val dcache = Flipped(new CacheIO(xlen, xlen))\n val ctrl = Flipped(new ControlSignals)\n}\n\nclass FetchExecutePipelineRegister(xlen: Int) extends Bundle {\n val inst = chiselTypeOf(Instructions.NOP)\n val pc = UInt(xlen.W)\n}\n\nclass ExecuteWritebackPipelineRegister(xlen: Int) extends Bundle {\n val inst = chiselTypeOf(Instructions.NOP)\n val pc = UInt(xlen.W)\n val alu = UInt(xlen.W)\n val csr_in = UInt(xlen.W)\n}\n\nclass Datapath(val conf: CoreConfig) extends Module {\n val io = IO(new DatapathIO(conf.xlen))\n val csr = Module(new CSR(conf.xlen))\n val regFile = Module(new RegFile(conf.xlen))\n val alu = Module(conf.makeAlu(conf.xlen))\n val immGen = Module(conf.makeImmGen(conf.xlen))\n val brCond = Module(conf.makeBrCond(conf.xlen))\n\n import Control._\n\n /** Pipeline State Registers * */\n\n /** *** Fetch / Execute Registers ****\n */\n val fe_reg = RegInit(\n (new FetchExecutePipelineRegister(conf.xlen)).Lit(\n _.inst -> Instructions.NOP,\n _.pc -> 0.U\n )\n )\n\n /** *** Execute / Write Back Registers ****\n */\n val ew_reg = RegInit(\n (new ExecuteWritebackPipelineRegister(conf.xlen)).Lit(\n _.inst -> Instructions.NOP,\n _.pc -> 0.U,\n _.alu -> 0.U,\n _.csr_in -> 0.U\n )\n )\n\n /** **** Control signals ****\n */\n val st_type = Reg(io.ctrl.st_type.cloneType)\n val ld_type = Reg(io.ctrl.ld_type.cloneType)\n val wb_sel = Reg(io.ctrl.wb_sel.cloneType)\n val wb_en = Reg(Bool())\n val csr_cmd = Reg(io.ctrl.csr_cmd.cloneType)\n val illegal = Reg(Bool())\n val pc_check = Reg(Bool())\n\n /** **** Fetch ****\n */\n val started = RegNext(reset.asBool)\n val stall = !io.icache.resp.valid || !io.dcache.resp.valid\n val pc = RegInit(Consts.PC_START.U(conf.xlen.W) - 4.U(conf.xlen.W))\n // Next Program Counter\n val next_pc = MuxCase(\n pc + 4.U,\n IndexedSeq(\n stall -> pc,\n csr.io.expt -> csr.io.evec,\n (io.ctrl.pc_sel === PC_EPC) -> csr.io.epc,\n ((io.ctrl.pc_sel === PC_ALU) || (brCond.io.taken)) -> (alu.io.sum >> 1.U << 1.U),\n (io.ctrl.pc_sel === PC_0) -> pc\n )\n )\n val inst =\n Mux(started || io.ctrl.inst_kill || brCond.io.taken || csr.io.expt, Instructions.NOP, io.icache.resp.bits.data)\n pc := next_pc\n io.icache.req.bits.addr := next_pc\n io.icache.req.bits.data := 0.U\n io.icache.req.bits.mask := 0.U\n io.icache.req.valid := !stall\n io.icache.abort := false.B\n\n // Pipelining\n when(!stall) {\n fe_reg.pc := pc\n fe_reg.inst := inst\n }\n\n /** **** Execute ****\n */\n io.ctrl.inst := fe_reg.inst\n\n // regFile read\n val rd_addr = fe_reg.inst(11, 7)\n val rs1_addr = fe_reg.inst(19, 15)\n val rs2_addr = fe_reg.inst(24, 20)\n regFile.io.raddr1 := rs1_addr\n regFile.io.raddr2 := rs2_addr\n\n // gen immdeates\n immGen.io.inst := fe_reg.inst\n immGen.io.sel := io.ctrl.imm_sel\n\n // bypass\n val wb_rd_addr = ew_reg.inst(11, 7)\n val rs1hazard = wb_en && rs1_addr.orR && (rs1_addr === wb_rd_addr)\n val rs2hazard = wb_en && rs2_addr.orR && (rs2_addr === wb_rd_addr)\n val rs1 = Mux(wb_sel === WB_ALU && rs1hazard, ew_reg.alu, regFile.io.rdata1)\n val rs2 = Mux(wb_sel === WB_ALU && rs2hazard, ew_reg.alu, regFile.io.rdata2)\n\n // ALU operations\n alu.io.A := Mux(io.ctrl.A_sel === A_RS1, rs1, fe_reg.pc)\n", "right_context": " alu.io.alu_op := io.ctrl.alu_op\n\n // Branch condition calc\n brCond.io.rs1 := rs1\n brCond.io.rs2 := rs2\n brCond.io.br_type := io.ctrl.br_type\n\n // D$ access\n val daddr = Mux(stall, ew_reg.alu, alu.io.sum) >> 2.U << 2.U\n val woffset = (alu.io.sum(1) << 4.U).asUInt | (alu.io.sum(0) << 3.U).asUInt\n io.dcache.req.valid := !stall && (io.ctrl.st_type.orR || io.ctrl.ld_type.orR)\n io.dcache.req.bits.addr := daddr\n io.dcache.req.bits.data := rs2 << woffset\n io.dcache.req.bits.mask := MuxLookup(Mux(stall, st_type, io.ctrl.st_type), \"b0000\".U)(\n Seq(ST_SW -> \"b1111\".U, ST_SH -> (\"b11\".U << alu.io.sum(1, 0)), ST_SB -> (\"b1\".U << alu.io.sum(1, 0)))\n )\n\n // Pipelining\n when(reset.asBool || !stall && csr.io.expt) {\n st_type := 0.U\n ld_type := 0.U\n wb_en := false.B\n csr_cmd := 0.U\n illegal := false.B\n pc_check := false.B\n }.elsewhen(!stall && !csr.io.expt) {\n ew_reg.pc := fe_reg.pc\n ew_reg.inst := fe_reg.inst\n ew_reg.alu := alu.io.out\n ew_reg.csr_in := Mux(io.ctrl.imm_sel === IMM_Z, immGen.io.out, rs1)\n st_type := io.ctrl.st_type\n ld_type := io.ctrl.ld_type\n wb_sel := io.ctrl.wb_sel\n wb_en := io.ctrl.wb_en\n csr_cmd := io.ctrl.csr_cmd\n illegal := io.ctrl.illegal\n pc_check := io.ctrl.pc_sel === PC_ALU\n }\n\n // Load\n val loffset = (ew_reg.alu(1) << 4.U).asUInt | (ew_reg.alu(0) << 3.U).asUInt\n val lshift = io.dcache.resp.bits.data >> loffset\n val load = MuxLookup(ld_type, io.dcache.resp.bits.data.zext)(\n Seq(\n LD_LH -> lshift(15, 0).asSInt,\n LD_LB -> lshift(7, 0).asSInt,\n LD_LHU -> lshift(15, 0).zext,\n LD_LBU -> lshift(7, 0).zext\n )\n )\n\n // CSR access\n csr.io.stall := stall\n csr.io.in := ew_reg.csr_in\n csr.io.cmd := csr_cmd\n csr.io.inst := ew_reg.inst\n csr.io.pc := ew_reg.pc\n csr.io.addr := ew_reg.alu\n csr.io.illegal := illegal\n csr.io.pc_check := pc_check\n csr.io.ld_type := ld_type\n csr.io.st_type := st_type\n io.host <> csr.io.host\n\n // Regfile Write\n val regWrite =\n MuxLookup(wb_sel, ew_reg.alu.zext)(\n Seq(WB_MEM -> load, WB_PC4 -> (ew_reg.pc + 4.U).zext, WB_CSR -> csr.io.out.zext)\n ).asUInt\n\n regFile.io.wen := wb_en && !stall && !csr.io.expt\n regFile.io.waddr := wb_rd_addr\n regFile.io.wdata := regWrite\n\n // Abort store when there's an excpetion\n io.dcache.abort := csr.io.expt\n\n // TODO: re-enable through AOP\n// if (p(Trace)) {\n// printf(\n// \"PC: %x, INST: %x, REG[%d] <- %x\\n\",\n// ew_reg.pc,\n// ew_reg.inst,\n// Mux(regFile.io.wen, wb_rd_addr, 0.U),\n// Mux(regFile.io.wen, regFile.io.wdata, 0.U)\n// )\n// }\n}\n", "groundtruth": " alu.io.B := Mux(io.ctrl.B_sel === B_RS2, rs2, immGen.io.out)\n", "crossfile_context": "", "category": "Computation Block", "subcategory": "Mux and Selection Logic", "confidence": 0.85, "category_reason": "Mux selection"} {"task_id": "riscv-mini", "path": "riscv-mini/src/main/scala/mini/ImmGen.scala", "left_context": "// See LICENSE for license details.\n\npackage mini\n\nimport chisel3._\nimport chisel3.util._\nimport mini.Control._\n\nclass ImmGenIO(xlen: Int) extends Bundle {\n val inst = Input(UInt(xlen.W))\n val sel = Input(UInt(3.W))\n val out = Output(UInt(xlen.W))\n}\n\ntrait ImmGen extends Module {\n def xlen: Int\n val io: ImmGenIO\n}\n\nclass ImmGenWire(val xlen: Int) extends ImmGen {\n val io = IO(new ImmGenIO(xlen))\n val Iimm = io.inst(31, 20).asSInt\n val Simm = Cat(io.inst(31, 25), io.inst(11, 7)).asSInt\n val Bimm = Cat(io.inst(31), io.inst(7), io.inst(30, 25), io.inst(11, 8), 0.U(1.W)).asSInt\n", "right_context": "}\n\nclass ImmGenMux(val xlen: Int) extends ImmGen {\n val io = IO(new ImmGenIO(xlen))\n val sign = Mux(io.sel === IMM_Z, 0.S, io.inst(31).asSInt)\n val b30_20 = Mux(io.sel === IMM_U, io.inst(30, 20).asSInt, sign)\n val b19_12 = Mux(io.sel =/= IMM_U && io.sel =/= IMM_J, sign, io.inst(19, 12).asSInt)\n val b11 = Mux(\n io.sel === IMM_U || io.sel === IMM_Z,\n 0.S,\n Mux(io.sel === IMM_J, io.inst(20).asSInt, Mux(io.sel === IMM_B, io.inst(7).asSInt, sign))\n )\n val b10_5 = Mux(io.sel === IMM_U || io.sel === IMM_Z, 0.U, io.inst(30, 25))\n val b4_1 = Mux(\n io.sel === IMM_U,\n 0.U,\n Mux(io.sel === IMM_S || io.sel === IMM_B, io.inst(11, 8), Mux(io.sel === IMM_Z, io.inst(19, 16), io.inst(24, 21)))\n )\n val b0 =\n Mux(io.sel === IMM_S, io.inst(7), Mux(io.sel === IMM_I, io.inst(20), Mux(io.sel === IMM_Z, io.inst(15), 0.U)))\n\n io.out := Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0).asSInt.asUInt\n}\n", "groundtruth": " val Uimm = Cat(io.inst(31, 12), 0.U(12.W)).asSInt\n val Jimm = Cat(io.inst(31), io.inst(19, 12), io.inst(20), io.inst(30, 25), io.inst(24, 21), 0.U(1.W)).asSInt\n val Zimm = io.inst(19, 15).zext\n\n", "crossfile_context": "", "category": "Computation Block", "subcategory": "Type Casting and Conversion", "confidence": 0.8, "category_reason": "Type casting"} {"task_id": "riscv-mini", "path": "riscv-mini/src/main/scala/mini/Instructions.scala", "left_context": "// See LICENSE for license details.\n\npackage mini\n\nimport chisel3.util.BitPat\n\nobject Instructions {\n // Loads\n def LB = BitPat(\"b?????????????????000?????0000011\")\n def LH = BitPat(\"b?????????????????001?????0000011\")\n def LW = BitPat(\"b?????????????????010?????0000011\")\n def LBU = BitPat(\"b?????????????????100?????0000011\")\n def LHU = BitPat(\"b?????????????????101?????0000011\")\n // Stores\n def SB = BitPat(\"b?????????????????000?????0100011\")\n def SH = BitPat(\"b?????????????????001?????0100011\")\n def SW = BitPat(\"b?????????????????010?????0100011\")\n // Shifts\n def SLL = BitPat(\"b0000000??????????001?????0110011\")\n def SLLI = BitPat(\"b0000000??????????001?????0010011\")\n def SRL = BitPat(\"b0000000??????????101?????0110011\")\n def SRLI = BitPat(\"b0000000??????????101?????0010011\")\n def SRA = BitPat(\"b0100000??????????101?????0110011\")\n def SRAI = BitPat(\"b0100000??????????101?????0010011\")\n // Arithmetic\n def ADD = BitPat(\"b0000000??????????000?????0110011\")\n def ADDI = BitPat(\"b?????????????????000?????0010011\")\n def SUB = BitPat(\"b0100000??????????000?????0110011\")\n def LUI = BitPat(\"b?????????????????????????0110111\")\n def AUIPC = BitPat(\"b?????????????????????????0010111\")\n // Logical\n def XOR = BitPat(\"b0000000??????????100?????0110011\")\n def XORI = BitPat(\"b?????????????????100?????0010011\")\n def OR = BitPat(\"b0000000??????????110?????0110011\")\n def ORI = BitPat(\"b?????????????????110?????0010011\")\n def AND = BitPat(\"b0000000??????????111?????0110011\")\n def ANDI = BitPat(\"b?????????????????111?????0010011\")\n // Compare\n def SLT = BitPat(\"b0000000??????????010?????0110011\")\n def SLTI = BitPat(\"b?????????????????010?????0010011\")\n def SLTU = BitPat(\"b0000000??????????011?????0110011\")\n def SLTIU = BitPat(\"b?????????????????011?????0010011\")\n // Branches\n def BEQ = BitPat(\"b?????????????????000?????1100011\")\n def BNE = BitPat(\"b?????????????????001?????1100011\")\n def BLT = BitPat(\"b?????????????????100?????1100011\")\n def BGE = BitPat(\"b?????????????????101?????1100011\")\n def BLTU = BitPat(\"b?????????????????110?????1100011\")\n def BGEU = BitPat(\"b?????????????????111?????1100011\")\n // Jump & Link\n", "right_context": " def JALR = BitPat(\"b?????????????????000?????1100111\")\n // Synch\n def FENCE = BitPat(\"b0000????????00000000000000001111\")\n def FENCEI = BitPat(\"b00000000000000000001000000001111\")\n // CSR Access\n def CSRRW = BitPat(\"b?????????????????001?????1110011\")\n def CSRRS = BitPat(\"b?????????????????010?????1110011\")\n def CSRRC = BitPat(\"b?????????????????011?????1110011\")\n def CSRRWI = BitPat(\"b?????????????????101?????1110011\")\n def CSRRSI = BitPat(\"b?????????????????110?????1110011\")\n def CSRRCI = BitPat(\"b?????????????????111?????1110011\")\n // Change Level\n def ECALL = BitPat(\"b00000000000000000000000001110011\")\n def EBREAK = BitPat(\"b00000000000100000000000001110011\")\n def ERET = BitPat(\"b00010000000000000000000001110011\")\n def WFI = BitPat(\"b00010000001000000000000001110011\")\n\n def NOP = BitPat.bitPatToUInt(BitPat(\"b00000000000000000000000000010011\"))\n}\n", "groundtruth": " def JAL = BitPat(\"b?????????????????????????1101111\")\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "riscv-mini", "path": "riscv-mini/src/main/scala/mini/Main.scala", "left_context": "// See LICENSE for license details.\n\npackage mini\n\nimport circt.stage.ChiselStage\nobject Main extends App {\n val config = MiniConfig()\n ChiselStage.emitSystemVerilogFile(\n new Tile(\n", "right_context": " nastiParams = config.nasti,\n cacheParams = config.cache\n ),\n args\n )\n}\n", "groundtruth": " coreParams = config.core,\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "riscv-mini", "path": "riscv-mini/src/main/scala/mini/RegFile.scala", "left_context": "// See LICENSE for license details.\n\npackage mini\n\nimport chisel3._\n\nclass RegFileIO(xlen: Int) extends Bundle {\n val raddr1 = Input(UInt(5.W))\n val raddr2 = Input(UInt(5.W))\n", "right_context": " val regs = Mem(32, UInt(xlen.W))\n io.rdata1 := Mux(io.raddr1.orR, regs(io.raddr1), 0.U)\n io.rdata2 := Mux(io.raddr2.orR, regs(io.raddr2), 0.U)\n when(io.wen & io.waddr.orR) {\n regs(io.waddr) := io.wdata\n }\n}\n", "groundtruth": " val rdata1 = Output(UInt(xlen.W))\n val rdata2 = Output(UInt(xlen.W))\n val wen = Input(Bool())\n val waddr = Input(UInt(5.W))\n val wdata = Input(UInt(xlen.W))\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.85, "category_reason": "Input/Output port declarations"} {"task_id": "riscv-mini", "path": "riscv-mini/src/main/scala/mini/Tile.scala", "left_context": "// See LICENSE for license details.\n\npackage mini\n\nimport chisel3._\nimport chisel3.util._\nimport junctions._\n\nclass MemArbiterIO(params: NastiBundleParameters) extends Bundle {\n val icache = Flipped(new NastiBundle(params))\n val dcache = Flipped(new NastiBundle(params))\n val nasti = new NastiBundle(params)\n}\n\nobject MemArbiterState extends ChiselEnum {\n val sIdle, sICacheRead, sDCacheRead, sDCacheWrite, sDCacheAck = Value\n}\n\nclass MemArbiter(params: NastiBundleParameters) extends Module {\n val io = IO(new MemArbiterIO(params))\n\n import MemArbiterState._\n val state = RegInit(sIdle)\n\n // Write Address\n io.nasti.aw.bits := io.dcache.aw.bits\n io.nasti.aw.valid := io.dcache.aw.valid && state === sIdle\n io.dcache.aw.ready := io.nasti.aw.ready && state === sIdle\n io.icache.aw := DontCare\n\n // Write Data\n io.nasti.w.bits := io.dcache.w.bits\n io.nasti.w.valid := io.dcache.w.valid && state === sDCacheWrite\n io.dcache.w.ready := io.nasti.w.ready && state === sDCacheWrite\n io.icache.w := DontCare\n\n // Write Ack\n io.dcache.b.bits := io.nasti.b.bits\n io.dcache.b.valid := io.nasti.b.valid && state === sDCacheAck\n io.nasti.b.ready := io.dcache.b.ready && state === sDCacheAck\n io.icache.b := DontCare\n\n // Read Address\n io.nasti.ar.bits := NastiAddressBundle(params)(\n Mux(io.dcache.ar.valid, io.dcache.ar.bits.id, io.icache.ar.bits.id),\n Mux(io.dcache.ar.valid, io.dcache.ar.bits.addr, io.icache.ar.bits.addr),\n Mux(io.dcache.ar.valid, io.dcache.ar.bits.size, io.icache.ar.bits.size),\n Mux(io.dcache.ar.valid, io.dcache.ar.bits.len, io.icache.ar.bits.len)\n )\n io.nasti.ar.valid := (io.icache.ar.valid || io.dcache.ar.valid) &&\n !io.nasti.aw.valid && state === sIdle\n io.dcache.ar.ready := io.nasti.ar.ready && !io.nasti.aw.valid && state === sIdle\n io.icache.ar.ready := io.dcache.ar.ready && !io.dcache.ar.valid\n\n // Read Data\n io.icache.r.bits := io.nasti.r.bits\n io.dcache.r.bits := io.nasti.r.bits\n io.icache.r.valid := io.nasti.r.valid && state === sICacheRead\n io.dcache.r.valid := io.nasti.r.valid && state === sDCacheRead\n io.nasti.r.ready := io.icache.r.ready && state === sICacheRead ||\n io.dcache.r.ready && state === sDCacheRead\n\n switch(state) {\n is(sIdle) {\n when(io.dcache.aw.fire) {\n state := sDCacheWrite\n }.elsewhen(io.dcache.ar.fire) {\n state := sDCacheRead\n }.elsewhen(io.icache.ar.fire) {\n state := sICacheRead\n }\n }\n is(sICacheRead) {\n when(io.nasti.r.fire && io.nasti.r.bits.last) {\n state := sIdle\n }\n }\n is(sDCacheRead) {\n when(io.nasti.r.fire && io.nasti.r.bits.last) {\n state := sIdle\n }\n }\n is(sDCacheWrite) {\n when(io.dcache.w.fire && io.dcache.w.bits.last) {\n state := sDCacheAck\n }\n }\n is(sDCacheAck) {\n when(io.nasti.b.fire) {\n state := sIdle\n }\n }\n }\n}\n\nclass TileIO(xlen: Int, nastiParams: NastiBundleParameters) extends Bundle {\n val host = new HostIO(xlen)\n val nasti = new NastiBundle(nastiParams)\n}\n\nobject Tile {\n", "right_context": "}\n\nclass Tile(val coreParams: CoreConfig, val nastiParams: NastiBundleParameters, val cacheParams: CacheConfig)\n extends Module {\n val io = IO(new TileIO(coreParams.xlen, nastiParams))\n val core = Module(new Core(coreParams))\n val icache = Module(new Cache(cacheParams, nastiParams, coreParams.xlen))\n val dcache = Module(new Cache(cacheParams, nastiParams, coreParams.xlen))\n val arb = Module(new MemArbiter(nastiParams))\n\n io.host <> core.io.host\n core.io.icache <> icache.io.cpu\n core.io.dcache <> dcache.io.cpu\n arb.io.icache <> icache.io.nasti\n arb.io.dcache <> dcache.io.nasti\n io.nasti <> arb.io.nasti\n}\n", "groundtruth": " def apply(config: Config): Tile = new Tile(config.core, config.nasti, config.cache)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "riscv-mini", "path": "riscv-mini/src/test/scala/mini/ALUTests.scala", "left_context": "// See LICENSE for license details.\n\npackage mini\n\nimport chisel3._\nimport chisel3.testers._\nimport chisel3.util._\nimport chiseltest._\nimport chiseltest.formal._\nimport org.scalatest.flatspec.AnyFlatSpec\n\nclass AluTester(alu: => Alu) extends BasicTester with TestUtils {\n import Alu._\n val dut = Module(alu)\n val ctrl = Module(new Control)\n val xlen = dut.width\n\n val (cntr, done) = Counter(true.B, insts.size)\n val rs1 = Seq.fill(insts.size)(rnd.nextInt()).map(toBigInt)\n val rs2 = Seq.fill(insts.size)(rnd.nextInt()).map(toBigInt)\n val sum = VecInit(rs1.zip(rs2).map { case (a, b) => toBigInt(a.toInt + b.toInt).U(xlen.W) })\n val diff = VecInit(rs1.zip(rs2).map { case (a, b) => toBigInt(a.toInt - b.toInt).U(xlen.W) })\n val and = VecInit(rs1.zip(rs2).map { case (a, b) => (a & b).U(xlen.W) })\n val or = VecInit(rs1.zip(rs2).map { case (a, b) => (a | b).U(xlen.W) })\n val xor = VecInit(rs1.zip(rs2).map { case (a, b) => (a ^ b).U(xlen.W) })\n val slt = VecInit(rs1.zip(rs2).map { case (a, b) => (if (a.toInt < b.toInt) 1 else 0).U(xlen.W) })\n val sltu = VecInit(rs1.zip(rs2).map { case (a, b) => (if (a < b) 1 else 0).U(xlen.W) })\n val sll = VecInit(rs1.zip(rs2).map { case (a, b) => toBigInt(a.toInt << (b.toInt & 0x1f)).U(xlen.W) })\n val srl = VecInit(rs1.zip(rs2).map { case (a, b) => toBigInt(a.toInt >>> (b.toInt & 0x1f)).U(xlen.W) })\n val sra = VecInit(rs1.zip(rs2).map { case (a, b) => toBigInt(a.toInt >> (b.toInt & 0x1f)).U(xlen.W) })\n val out = (\n Mux(\n dut.io.alu_op === ALU_ADD,\n sum(cntr),\n Mux(\n dut.io.alu_op === ALU_SUB,\n diff(cntr),\n Mux(\n dut.io.alu_op === ALU_AND,\n and(cntr),\n Mux(\n dut.io.alu_op === ALU_OR,\n or(cntr),\n Mux(\n dut.io.alu_op === ALU_XOR,\n xor(cntr),\n Mux(\n dut.io.alu_op === ALU_SLT,\n slt(cntr),\n Mux(\n dut.io.alu_op === ALU_SLTU,\n sltu(cntr),\n Mux(\n dut.io.alu_op === ALU_SLL,\n sll(cntr),\n Mux(\n dut.io.alu_op === ALU_SRL,\n srl(cntr),\n Mux(dut.io.alu_op === ALU_SRA, sra(cntr), Mux(dut.io.alu_op === ALU_COPY_A, dut.io.A, dut.io.B))\n )\n )\n )\n )\n )\n )\n )\n )\n ),\n Mux(dut.io.alu_op(0), diff(cntr), sum(cntr))\n )\n\n ctrl.io.inst := VecInit(insts)(cntr)\n dut.io.alu_op := ctrl.io.alu_op\n dut.io.A := VecInit(rs1.map(_.U))(cntr)\n dut.io.B := VecInit(rs2.map(_.U))(cntr)\n\n", "right_context": " assert(dut.io.out === out._1)\n assert(dut.io.sum === out._2)\n printf(\n \"Counter: %d, OP: 0x%x, A: 0x%x, B: 0x%x, OUT: 0x%x ?= 0x%x, SUM: 0x%x ?= 0x%x\\n\",\n cntr,\n dut.io.alu_op,\n dut.io.A,\n dut.io.B,\n dut.io.out,\n out._1,\n dut.io.sum,\n out._2\n )\n}\n\nclass ALUTests extends AnyFlatSpec with ChiselScalatestTester with Formal {\n \"ALUSimple\" should \"pass\" in {\n test(new AluTester(new AluSimple(32))).runUntilStop()\n }\n \"AluArea\" should \"pass\" in {\n test(new AluTester(new AluArea(32))).runUntilStop()\n }\n \"AluArea\" should \"be equivalent to AluSimple\" in {\n // since there is no state (registers/memory) in the ALU, a single cycle check is enough to prove equivalence\n verify(new AluEquivalenceCheck(new AluArea(32)), Seq(BoundedCheck(1)))\n }\n}\n\nclass AluEquivalenceCheck(other: => Alu) extends Module {\n val dut = Module(other)\n val ref = Module(new AluSimple(dut.width))\n\n // arbitrary inputs\n val io = IO(chiselTypeOf(dut.io))\n\n // connect the same inputs to both modules (the outputs will be overwritten to always connect to the reference)\n dut.io <> io; ref.io <> io\n\n // check to ensure that outputs are the same\n assert(ref.io.out === dut.io.out, \"out: expected: %d, actual: %d\", ref.io.out, dut.io.out)\n assert(ref.io.sum === dut.io.sum, \"sum: %d, actual: %d\", ref.io.sum, dut.io.sum)\n}\n", "groundtruth": " when(done) { stop() }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "riscv-mini", "path": "riscv-mini/src/test/scala/mini/BrCondTests.scala", "left_context": "// See LICENSE for license details.\n\npackage mini\n\nimport chisel3._\nimport chisel3.testers._\nimport chisel3.util._\nimport chiseltest._\nimport chiseltest.formal._\nimport org.scalatest.flatspec.AnyFlatSpec\n\nclass BrCondTester(br: => BrCond) extends BasicTester with TestUtils {\n import Control._\n val dut = Module(br)\n val ctrl = Module(new Control)\n\n override val insts = Seq\n .fill(10)(\n Seq(\n B(Funct3.BEQ, 0, 0, 0),\n B(Funct3.BNE, 0, 0, 0),\n B(Funct3.BLT, 0, 0, 0),\n B(Funct3.BGE, 0, 0, 0),\n B(Funct3.BLTU, 0, 0, 0),\n B(Funct3.BGEU, 0, 0, 0)\n )\n )\n .flatten\n\n val (cntr, done) = Counter(true.B, insts.size)\n val rs1 = Seq.fill(insts.size)(rnd.nextInt()).map(toBigInt)\n val rs2 = Seq.fill(insts.size)(rnd.nextInt()).map(toBigInt)\n val eq = VecInit(rs1.zip(rs2).map { case (a, b) => (a == b).B })\n val ne = VecInit(rs1.zip(rs2).map { case (a, b) => (a != b).B })\n val lt = VecInit(rs1.zip(rs2).map { case (a, b) => (a.toInt < b.toInt).B })\n val ge = VecInit(rs1.zip(rs2).map { case (a, b) => (a.toInt >= b.toInt).B })\n val ltu = VecInit(rs1.zip(rs2).map { case (a, b) => (a < b).B })\n val geu = VecInit(rs1.zip(rs2).map { case (a, b) => (a >= b).B })\n val out = Mux(\n dut.io.br_type === BR_EQ,\n eq(cntr),\n Mux(\n dut.io.br_type === BR_NE,\n ne(cntr),\n Mux(\n dut.io.br_type === BR_LT,\n lt(cntr),\n Mux(\n dut.io.br_type === BR_GE,\n ge(cntr),\n Mux(dut.io.br_type === BR_LTU, ltu(cntr), Mux(dut.io.br_type === BR_GEU, geu(cntr), false.B))\n )\n )\n )\n )\n\n ctrl.io.inst := VecInit(insts)(cntr)\n dut.io.br_type := ctrl.io.br_type\n dut.io.rs1 := VecInit(rs1.map(_.U))(cntr)\n dut.io.rs2 := VecInit(rs2.map(_.U))(cntr)\n\n", "right_context": " assert(dut.io.taken === out)\n printf(\n \"Counter: %d, BrType: 0x%x, rs1: 0x%x, rs2: 0x%x, Taken: %d ?= %d\\n\",\n cntr,\n dut.io.br_type,\n dut.io.rs1,\n dut.io.rs2,\n dut.io.taken,\n out\n )\n}\n\nclass BrCondTests extends AnyFlatSpec with ChiselScalatestTester with Formal {\n \"BrCondSimple\" should \"pass\" in {\n test(new BrCondTester(new BrCondSimple(32))).runUntilStop()\n }\n \"BrCondArea\" should \"pass\" in {\n test(new BrCondTester(new BrCondArea(32))).runUntilStop()\n }\n \"BrCondArea\" should \"be equivalent to BrCondSimple\" in {\n // since there is no state (registers/memory) in the BrCond, a single cycle check is enough to prove equivalence\n verify(new BrCondEquivalenceCheck(new BrCondArea(32)), Seq(BoundedCheck(1)))\n }\n}\n\nclass BrCondEquivalenceCheck(other: => BrCond) extends Module {\n val dut = Module(other)\n val ref = Module(new BrCondSimple(dut.xlen))\n\n // arbitrary inputs\n val io = IO(chiselTypeOf(dut.io))\n\n // connect the same inputs to both modules (the outputs will be overwritten to always connect to the reference)\n dut.io <> io; ref.io <> io\n\n // check to ensure that outputs are the same\n assert(ref.io.taken === dut.io.taken, \"taken: expected: %d, actual: %d\", ref.io.taken, dut.io.taken)\n}\n", "groundtruth": " when(done) { stop() }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "riscv-mini", "path": "riscv-mini/src/test/scala/mini/CSRTests.scala", "left_context": "// See LICENSE for license details.\n\npackage mini\n\nimport chisel3._\nimport chisel3.testers._\nimport chisel3.util._\nimport chiseltest._\nimport org.scalatest.flatspec.AnyFlatSpec\n\nclass CSRTester(c: => CSR, trace: Boolean = false) extends BasicTester with TestUtils {\n import Control._\n val dut = Module(c)\n val ctrl = Module(new Control)\n val xlen = dut.xlen\n\n override val insts =\n CSR.regs.map(csr => I(rand_fn3, 0, rand_rs1.litValue, csr.litValue)) ++\n CSR.regs.map(csr => SYS(Funct3.CSRRW, 0, csr, rand_rs1.litValue)) ++\n CSR.regs.map(csr => SYS(Funct3.CSRRS, 0, csr, rand_rs1.litValue)) ++\n CSR.regs.map(csr => SYS(Funct3.CSRRC, 0, csr, rand_rs1.litValue)) ++\n CSR.regs.map(csr => SYS(Funct3.CSRRWI, 0, csr, rand_rs1.litValue)) ++\n CSR.regs.map(csr => SYS(Funct3.CSRRSI, 0, csr, rand_rs1.litValue)) ++\n CSR.regs.map(csr => SYS(Funct3.CSRRCI, 0, csr, rand_rs1.litValue)) ++\n CSR.regs.map(csr => I(rand_fn3, 0, rand_rs1.litValue, csr.litValue)) ++ List[UInt](\n // system insts\n Instructions.ECALL,\n SYS(Funct3.CSRRC, 0, CSR.mcause, 0),\n Instructions.EBREAK,\n SYS(Funct3.CSRRC, 0, CSR.mcause, 0),\n Instructions.ERET,\n SYS(Funct3.CSRRC, 0, CSR.mcause, 0),\n // illegal addr\n J(rand_rd.litValue, rnd.nextInt()),\n SYS(Funct3.CSRRC, 0, CSR.mcause, 0),\n JR(rand_rd.litValue, rand_rs1.litValue, rnd.nextInt()),\n SYS(Funct3.CSRRC, 0, CSR.mcause, 0),\n L(Funct3.LW, rand_rd.litValue, rand_rs1.litValue, rand_rs2.litValue),\n SYS(Funct3.CSRRC, 0, CSR.mcause, 0),\n L(Funct3.LH, rand_rd.litValue, rand_rs1.litValue, rand_rs2.litValue),\n SYS(Funct3.CSRRC, 0, CSR.mcause, 0),\n L(Funct3.LHU, rand_rd.litValue, rand_rs1.litValue, rand_rs2.litValue),\n SYS(Funct3.CSRRC, 0, CSR.mcause, 0),\n S(Funct3.SW, rand_rd.litValue, rand_rs1.litValue, rand_rs2.litValue),\n SYS(Funct3.CSRRC, 0, CSR.mcause, 0),\n S(Funct3.SH, rand_rd.litValue, rand_rs1.litValue, rand_rs2.litValue),\n SYS(Funct3.CSRRC, 0, CSR.mcause, 0),\n // illegal inst\n rand_inst,\n SYS(Funct3.CSRRC, 0, CSR.mcause, 0),\n // Check counters\n SYS(Funct3.CSRRC, 0, CSR.time, 0),\n SYS(Funct3.CSRRC, 0, CSR.cycle, 0),\n SYS(Funct3.CSRRC, 0, CSR.instret, 0),\n SYS(Funct3.CSRRC, 0, CSR.mfromhost, 0)\n )\n\n val (cntr, done) = Counter(true.B, insts.size)\n val pc = Seq.fill(insts.size)(rnd.nextInt()).map(toBigInt)\n val addr = Seq.fill(insts.size)(rnd.nextInt()).map(toBigInt)\n val data = Seq.fill(insts.size)(rnd.nextInt()).map(toBigInt)\n val regs = CSR.regs\n .map(_.litValue)\n .map { addr =>\n addr -> RegInit(\n if (addr == CSR.mcpuid.litValue) (BigInt(1) << ('I' - 'A') | BigInt(1) << ('U' - 'A')).U(xlen.W)\n else if (addr == CSR.mstatus.litValue) (CSR.PRV_M.litValue << 4 | CSR.PRV_M.litValue << 1).U(xlen.W)\n else if (addr == CSR.mtvec.litValue) Consts.PC_EVEC.U(xlen.W)\n else 0.U(xlen.W)\n )\n }\n .toMap\n\n ctrl.io.inst := VecInit(insts)(cntr)\n dut.io.inst := ctrl.io.inst\n dut.io.cmd := ctrl.io.csr_cmd\n dut.io.illegal := ctrl.io.illegal\n dut.io.st_type := ctrl.io.st_type\n dut.io.ld_type := ctrl.io.ld_type\n dut.io.pc_check := ctrl.io.pc_sel === PC_ALU\n dut.io.pc := VecInit(pc.map(_.U))(cntr)\n dut.io.addr := VecInit(addr.map(_.U))(cntr)\n dut.io.in := VecInit(data.map(_.U))(cntr)\n\n dut.io.stall := false.B\n dut.io.host.fromhost.valid := false.B\n dut.io.host.fromhost.bits := 0.U\n\n // values known statically\n val _csr_addr = insts.map(csr)\n val _rs1_addr = insts.map(rs1)\n val _csr_ro = _csr_addr.map(x =>\n ((((x >> 11) & 0x1) > 0x0) && (((x >> 10) & 0x1) > 0x0)) ||\n x == CSR.mtvec.litValue || x == CSR.mtdeleg.litValue\n )\n val _csr_valid = _csr_addr.map(x => CSR.regs.exists(_.litValue == x))\n // should be <= prv in runtime\n val _prv_level = _csr_addr.map(x => (x >> 8) & 0x3)\n // should consider prv in runtime\n val _is_ecall = _csr_addr.map(x => ((x & 0x1) == 0x0) && (((x >> 8) & 0x1) == 0x0))\n val _is_ebreak = _csr_addr.map(x => ((x & 0x1) > 0x0) && (((x >> 8) & 0x1) == 0x0))\n val _is_eret = _csr_addr.map(x => ((x & 0x1) == 0x0) && (((x >> 8) & 0x1) > 0x0))\n // should consider pc_check in runtime\n val _iaddr_invalid = addr.map(x => ((x >> 1) & 0x1) > 0)\n // should consider ld_type & st_type\n val _waddr_invalid = addr.map(x => ((x >> 1) & 0x1) > 0 || (x & 0x1) > 0)\n val _haddr_invalid = addr.map(x => (x & 0x1) > 0)\n\n // values known in runtime\n val csr_addr = Wire(UInt())\n val rs1_addr = Wire(UInt())\n val csr_ro = Wire(Bool())\n val csr_valid = Wire(Bool())\n csr_addr := VecInit(_csr_addr.map(_.U))(cntr)\n rs1_addr := VecInit(_rs1_addr.map(_.U))(cntr)\n csr_ro := VecInit(_csr_ro.map(_.B))(cntr)\n csr_valid := VecInit(_csr_valid.map(_.B))(cntr)\n val wen = dut.io.cmd === CSR.W || dut.io.cmd(1) && rs1_addr =/= 0.U\n val prv1 = (regs(CSR.mstatus.litValue) >> 4.U).asUInt & 0x3.U\n val ie1 = (regs(CSR.mstatus.litValue) >> 3.U).asUInt & 0x1.U\n val prv = (regs(CSR.mstatus.litValue) >> 1.U).asUInt & 0x3.U\n val ie = regs(CSR.mstatus.litValue) & 0x1.U\n val prv_inst = dut.io.cmd === CSR.P\n val prv_valid = VecInit(_prv_level.map(_.U))(cntr) <= prv\n val iaddr_invalid = VecInit(_iaddr_invalid.map(_.B))(cntr) && dut.io.pc_check\n val laddr_invalid =\n VecInit(_haddr_invalid.map(_.B))(cntr) && (dut.io.ld_type === LD_LH || dut.io.ld_type === LD_LHU) ||\n VecInit(_waddr_invalid.map(_.B))(cntr) && (dut.io.ld_type === LD_LW)\n val saddr_invalid =\n VecInit(_haddr_invalid.map(_.B))(cntr) && dut.io.st_type === ST_SH ||\n VecInit(_waddr_invalid.map(_.B))(cntr) && dut.io.st_type === ST_SW\n val is_ecall = prv_inst && VecInit(_is_ecall.map(_.B))(cntr)\n val is_ebreak = prv_inst && VecInit(_is_ebreak.map(_.B))(cntr)\n val is_eret = prv_inst && VecInit(_is_eret.map(_.B))(cntr)\n val exception = dut.io.illegal || iaddr_invalid || laddr_invalid || saddr_invalid ||\n (((dut.io.cmd & 0x3.U) > 0.U) && (!csr_valid || !prv_valid)) ||\n (csr_ro && wen) || (prv_inst && !prv_valid) || is_ecall || is_ebreak\n val instret = dut.io.inst =/= nop && (!exception || is_ecall || is_ebreak)\n\n val rdata = Lookup(\n csr_addr,\n 0.U,\n regs.toSeq.map {\n case (addr, reg) => BitPat(addr.U(12.W)) -> reg\n }\n )\n val wdata = Lookup(\n dut.io.cmd,\n 0.U,\n Seq(\n BitPat(CSR.W) -> dut.io.in,\n BitPat(CSR.S) -> (dut.io.in | rdata),\n BitPat(CSR.C) -> ((~dut.io.in).asUInt & rdata)\n )\n )\n\n // compute state\n regs(CSR.time.litValue) := regs(CSR.time.litValue) + 1.U\n regs(CSR.timew.litValue) := regs(CSR.timew.litValue) + 1.U\n regs(CSR.mtime.litValue) := regs(CSR.mtime.litValue) + 1.U\n regs(CSR.cycle.litValue) := regs(CSR.cycle.litValue) + 1.U\n regs(CSR.cyclew.litValue) := regs(CSR.cyclew.litValue) + 1.U\n when(regs(CSR.time.litValue).andR) {\n regs(CSR.mtime.litValue) := regs(CSR.mtime.litValue) + 1.U\n regs(CSR.timeh.litValue) := regs(CSR.timeh.litValue) + 1.U\n regs(CSR.timehw.litValue) := regs(CSR.timehw.litValue) + 1.U\n }\n when(regs(CSR.cycle.litValue).andR) {\n regs(CSR.cycleh.litValue) := regs(CSR.cycleh.litValue) + 1.U\n regs(CSR.cyclehw.litValue) := regs(CSR.cyclehw.litValue) + 1.U\n }\n when(instret) {\n regs(CSR.instret.litValue) := regs(CSR.instret.litValue) + 1.U\n regs(CSR.instretw.litValue) := regs(CSR.instret.litValue) + 1.U\n when(regs(CSR.instret.litValue).andR) {\n regs(CSR.instreth.litValue) := regs(CSR.instreth.litValue) + 1.U\n regs(CSR.instrethw.litValue) := regs(CSR.instrethw.litValue) + 1.U\n }\n }\n\n when(exception) {\n regs(CSR.mepc.litValue) := (dut.io.pc >> 2.U) << 2.U\n regs(CSR.mcause.litValue) :=\n Mux(\n iaddr_invalid,\n Cause.InstAddrMisaligned,\n Mux(\n laddr_invalid,\n Cause.LoadAddrMisaligned,\n Mux(\n saddr_invalid,\n Cause.StoreAddrMisaligned,\n Mux(\n prv_inst && VecInit(is_ecall)(cntr),\n Cause.Ecall + prv,\n Mux(prv_inst && VecInit(is_ebreak)(cntr), Cause.Breakpoint, Cause.IllegalInst)\n )\n )\n )\n )\n regs(CSR.mstatus.litValue) := (prv << 4.U).asUInt | (ie << 3.U).asUInt | (CSR.PRV_M << 1.U).asUInt | 0.U\n when(iaddr_invalid || laddr_invalid || saddr_invalid) {\n regs(CSR.mbadaddr.litValue) := dut.io.addr\n }\n }.elsewhen(is_eret) {\n regs(CSR.mstatus.litValue) := (CSR.PRV_U << 4.U).asUInt | (1.U << 3.U).asUInt | (prv1 << 1.U).asUInt | ie1\n }.elsewhen(wen) {\n when(csr_addr === CSR.mstatus) {\n regs(CSR.mstatus.litValue) := wdata(5, 0)\n }.elsewhen(csr_addr === CSR.mip) {\n regs(CSR.mip.litValue) := (wdata(7) << 7.U).asUInt | (wdata(3) << 3.U).asUInt\n }.elsewhen(csr_addr === CSR.mie) {\n regs(CSR.mie.litValue) := (wdata(7) << 7.U).asUInt | (wdata(3) << 3.U).asUInt\n }.elsewhen(csr_addr === CSR.mepc) {\n regs(CSR.mepc.litValue) := (wdata >> 2.U) << 2.U\n }.elsewhen(csr_addr === CSR.mcause) {\n regs(CSR.mcause.litValue) := wdata & ((BigInt(1) << 31) | 0xf).U\n }.elsewhen(csr_addr === CSR.timew || csr_addr === CSR.mtime) {\n regs(CSR.time.litValue) := wdata\n regs(CSR.timew.litValue) := wdata\n regs(CSR.mtime.litValue) := wdata\n }.elsewhen(csr_addr === CSR.timehw || csr_addr === CSR.mtimeh) {\n regs(CSR.timeh.litValue) := wdata\n regs(CSR.timehw.litValue) := wdata\n regs(CSR.mtimeh.litValue) := wdata\n }.elsewhen(csr_addr === CSR.cyclew) {\n regs(CSR.cycle.litValue) := wdata\n regs(CSR.cyclew.litValue) := wdata\n }.elsewhen(csr_addr === CSR.cyclehw) {\n regs(CSR.cycleh.litValue) := wdata\n regs(CSR.cyclehw.litValue) := wdata\n }.elsewhen(csr_addr === CSR.instretw) {\n regs(CSR.instret.litValue) := wdata\n regs(CSR.instretw.litValue) := wdata\n }.elsewhen(csr_addr === CSR.instrethw) {\n regs(CSR.instreth.litValue) := wdata\n regs(CSR.instrethw.litValue) := wdata\n }.elsewhen(csr_addr === CSR.mtimecmp) {\n regs(CSR.mtimecmp.litValue) := wdata\n }.elsewhen(csr_addr === CSR.mscratch) {\n regs(CSR.mscratch.litValue) := wdata\n }.elsewhen(csr_addr === CSR.mbadaddr) {\n regs(CSR.mbadaddr.litValue) := wdata\n }.elsewhen(csr_addr === CSR.mtohost) {\n regs(CSR.mtohost.litValue) := wdata\n }.elsewhen(csr_addr === CSR.mfromhost) {\n regs(CSR.mfromhost.litValue) := wdata\n }\n }\n\n val epc = Wire(UInt())\n val evec = Wire(UInt())\n epc := regs(CSR.mepc.litValue)\n evec := regs(CSR.mtvec.litValue) + (prv << 6.U).asUInt\n\n", "right_context": " when(cntr.orR) {\n assert(dut.io.out === rdata)\n assert(dut.io.epc === epc)\n assert(dut.io.evec === evec)\n assert(dut.io.expt === exception)\n }\n\n if (trace) {\n printf(\"*** Counter: %d ***\\n\", cntr)\n printf(\"[in] inst: 0x%x, pc: 0x%x, daddr: 0x%x, in: 0x%x\\n\", dut.io.inst, dut.io.pc, dut.io.addr, dut.io.in)\n printf(\n \" cmd: 0x%x, st_type: 0x%x, ld_type: 0x%x, illegal: %d, pc_check: %d\\n\",\n dut.io.cmd,\n dut.io.st_type,\n dut.io.ld_type,\n dut.io.illegal,\n dut.io.pc_check\n )\n printf(\"[state] csr addr: %x\\n\", csr_addr)\n regs.toSeq.sortWith(_._1 < _._1).foreach {\n case (addr, reg) => printf(s\" ${addr.toString(16)} -> 0x%x\\n\", reg)\n }\n printf(\n \"[out] read: 0x%x =? 0x%x, epc: 0x%x =? 0x%x, evec: 0x%x ?= 0x%x, expt: %d ?= %d\\n\",\n dut.io.out,\n rdata,\n dut.io.epc,\n epc,\n dut.io.evec,\n evec,\n dut.io.expt,\n exception\n )\n }\n}\n\nclass CSRTests extends AnyFlatSpec with ChiselScalatestTester {\n \"CSR\" should \"pass\" in {\n test(new CSRTester(new CSR(xlen = 32))).runUntilStop()\n }\n}\n", "groundtruth": " when(done) { stop() }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "riscv-mini", "path": "riscv-mini/src/test/scala/mini/CacheTests.scala", "left_context": "// See LICENSE for license details.\n\npackage mini\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.testers._\nimport junctions._\nimport chiseltest._\nimport org.scalatest.flatspec.AnyFlatSpec\n\nclass GoldCacheIO(p: CacheConfig, nastiParams: NastiBundleParameters, xlen: Int) extends Bundle {\n val req = Flipped(Decoupled(new CacheReq(xlen, xlen)))\n val resp = Decoupled(new CacheResp(xlen))\n val nasti = new NastiBundle(nastiParams)\n}\n\nobject GoldCacheState extends ChiselEnum {\n val sIdle, sWrite, sWriteAck, sRead = Value\n}\n\nclass GoldCache(p: CacheConfig, nasti: NastiBundleParameters, xlen: Int) extends Module {\n // local parameters\n val nSets = p.nSets\n val bBytes = p.blockBytes\n val bBits = bBytes << 3\n val blen = log2Ceil(bBytes)\n val slen = log2Ceil(nSets)\n val tlen = xlen - (slen + blen)\n val nWords = bBits / xlen\n val wBytes = xlen / 8\n val byteOffsetBits = log2Ceil(wBytes)\n val dataBeats = bBits / nasti.dataBits\n\n val io = IO(new GoldCacheIO(p, nasti, xlen))\n val size = log2Ceil(nasti.dataBits / 8).U\n val len = (dataBeats - 1).U\n\n val dataMemory = Mem(nSets, UInt(bBits.W))\n val tags = Mem(nSets, UInt(tlen.W))\n val v = Mem(nSets, Bool())\n val d = Mem(nSets, Bool())\n\n val req = io.req.bits\n val tag = (req.addr >> (blen + slen).U).asUInt\n val idx = req.addr(blen + slen - 1, blen)\n val off = req.addr(blen - 1, 0)\n\n val readData = dataMemory(idx)\n val writeData = (0 until bBytes).foldLeft(0.U) { (write, i) =>\n write | {\n val condition = ((off / 4.U) === (i / 4).U) && (req.mask >> (i & 0x3).U)(0)\n val trueClause = (((req.data >> (8 * (i & 0x3)).U).asUInt & 0xff.U).asUInt << (8 * BigInt(i)).U).asUInt\n val falseClause = readData & (BigInt(0xff) << (8 * i)).U\n Mux(condition, trueClause, falseClause)\n }\n }(bBits - 1, 0)\n\n import GoldCacheState._\n val state = RegInit(sIdle)\n val (wCnt, wDone) = Counter(state === sWrite, dataBeats)\n val (rCnt, rDone) = Counter(state === sRead && io.nasti.r.valid, dataBeats)\n\n io.resp.bits.data := readData >> ((off / 4.U) * xlen.U)\n io.resp.valid := false.B\n io.req.ready := false.B\n io.nasti.ar.bits := NastiAddressBundle(nasti)(0.U, ((req.addr >> blen.U).asUInt << blen.U).asUInt, size, len)\n io.nasti.ar.valid := false.B\n io.nasti.aw.bits := NastiAddressBundle(nasti)(0.U, (Cat(tags(idx), idx) << blen.U).asUInt, size, len)\n io.nasti.aw.valid := false.B\n io.nasti.w.bits := NastiWriteDataBundle(nasti)((readData >> (wCnt * nasti.dataBits.U)).asUInt, None, wDone)\n io.nasti.w.valid := state === sWrite\n io.nasti.b.ready := state === sWriteAck\n io.nasti.r.ready := state === sRead\n\n switch(state) {\n is(sIdle) {\n when(io.req.valid && io.resp.ready) {\n when(v(idx) && (tags(idx) === tag)) {\n when(req.mask.orR) {\n d(idx) := true.B\n dataMemory(idx) := writeData\n printf(\n \"[cache] data[%x] <= writeData %x, readData %x, off: %x, req: %x, mask: %b\\n\",\n idx,\n writeData,\n readData,\n off,\n io.req.bits.data,\n io.req.bits.mask\n )\n }.otherwise {\n printf(\"[cache] data[%x] => %x, off: %x, resp: %x\\n\", idx, readData, off, io.resp.bits.data)\n }\n io.req.ready := true.B\n io.resp.valid := true.B\n }.otherwise {\n when(d(idx)) {\n io.nasti.aw.valid := true.B\n state := sWrite\n }.otherwise {\n dataMemory(idx) := 0.U\n io.nasti.ar.valid := true.B\n state := sRead\n }\n }\n }\n }\n is(sWrite) {\n when(wDone) {\n state := sWriteAck\n }\n }\n is(sWriteAck) {\n when(io.nasti.b.valid) {\n dataMemory(idx) := 0.U\n io.nasti.ar.valid := true.B\n state := sRead\n }\n }\n is(sRead) {\n when(io.nasti.r.valid) {\n dataMemory(idx) := readData | (io.nasti.r.bits.data << (rCnt * nasti.dataBits.U)).asUInt\n }\n when(rDone) {\n assert(io.nasti.r.bits.last)\n tags(idx) := tag\n v(idx) := true.B\n state := sIdle\n }\n }\n }\n}\n\nobject CacheTesterState extends ChiselEnum {\n val sInit, sStart, sWait, sDone = Value\n}\n\nobject CacheTesterMemState extends ChiselEnum {\n val sMemIdle, sMemWrite, sMemWrAck, sMemRead = Value\n}\n\nclass CacheTester(cache: => Cache) extends BasicTester {\n /* Target Design */\n val dut = Module(cache)\n // extract parameters from dut\n val p = dut.p\n val xlen = dut.xlen\n val nasti = dut.nasti\n val nSets = p.nSets\n val bBytes = p.blockBytes\n val bBits = bBytes << 3\n val blen = log2Ceil(bBytes)\n val slen = log2Ceil(nSets)\n val tlen = xlen - (slen + blen)\n val nWords = bBits / xlen\n val wBytes = xlen / 8\n val byteOffsetBits = log2Ceil(wBytes)\n val dataBeats = bBits / nasti.dataBits\n val dut_mem = Wire(new NastiBundle(nasti))\n dut_mem.ar <> Queue(dut.io.nasti.ar, 32)\n dut_mem.aw <> Queue(dut.io.nasti.aw, 32)\n dut_mem.w <> Queue(dut.io.nasti.w, 32)\n dut.io.nasti.b <> Queue(dut_mem.b, 32)\n dut.io.nasti.r <> Queue(dut_mem.r, 32)\n\n /* Gold Model */\n val gold = Module(new GoldCache(p, nasti, xlen))\n val gold_req = WireInit(gold.io.req)\n val gold_resp = WireInit(gold.io.resp)\n val gold_mem = Wire(new NastiBundle(nasti))\n gold.io.req <> Queue(gold_req, 32)\n gold_resp <> Queue(gold.io.resp, 32)\n gold_mem.ar <> Queue(gold.io.nasti.ar, 32)\n gold_mem.aw <> Queue(gold.io.nasti.aw, 32)\n gold_mem.w <> Queue(gold.io.nasti.w, 32)\n gold.io.nasti.b <> Queue(gold_mem.b, 32)\n gold.io.nasti.r <> Queue(gold_mem.r, 32)\n\n val size = log2Ceil(nasti.dataBits / 8).U\n val len = (dataBeats - 1).U\n\n /* Main Memory */\n val mem = Mem(1 << 20, UInt(nasti.dataBits.W))\n import CacheTesterMemState._\n val memState = RegInit(sMemIdle)\n val (wCnt, wDone) = Counter(memState === sMemWrite && dut_mem.w.valid && gold_mem.w.valid, dataBeats)\n val (rCnt, rDone) = Counter(memState === sMemRead && dut_mem.r.ready && gold_mem.r.ready, dataBeats)\n\n dut_mem.ar.ready := false.B\n dut_mem.aw.ready := false.B\n dut_mem.w.ready := false.B\n dut_mem.b.valid := memState === sMemWrAck\n dut_mem.b.bits := NastiWriteResponseBundle(nasti)(0.U)\n dut_mem.r.valid := memState === sMemRead\n dut_mem.r.bits := NastiReadDataBundle(nasti)(0.U, mem((gold_mem.ar.bits.addr >> size).asUInt + rCnt), rDone)\n gold_mem.ar.ready := dut_mem.ar.ready\n gold_mem.aw.ready := dut_mem.aw.ready\n gold_mem.w.ready := dut_mem.w.ready\n gold_mem.b.valid := dut_mem.b.valid\n gold_mem.b.bits := dut_mem.b.bits\n gold_mem.r.valid := dut_mem.r.valid\n gold_mem.r.bits := dut_mem.r.bits\n\n switch(memState) {\n is(sMemIdle) {\n when(gold_mem.aw.valid && dut_mem.aw.valid) {\n assert(\n dut_mem.aw.bits.id === gold_mem.aw.bits.id,\n \"* dut.io.nasti.aw.bits.id => %x != %x *\\n\",\n dut_mem.aw.bits.id,\n gold_mem.aw.bits.id\n )\n assert(\n gold_mem.aw.bits.addr === dut_mem.aw.bits.addr,\n \"* dut.io.nasti.aw.bits.addr => %x != %x *\\n\",\n dut_mem.aw.bits.addr,\n gold_mem.aw.bits.addr\n )\n assert(\n gold_mem.aw.bits.size === dut_mem.aw.bits.size,\n \"* dut.io.nasti.aw.bits.size => %x != %x *\\n\",\n dut_mem.aw.bits.size,\n gold_mem.aw.bits.size\n )\n assert(\n gold_mem.aw.bits.len === dut_mem.aw.bits.len,\n \"* dut.io.nasti.aw.bits.len => %x != %x *\\n\",\n dut_mem.aw.bits.len,\n gold_mem.aw.bits.len\n )\n memState := sMemWrite\n }.elsewhen(gold_mem.ar.valid && dut_mem.ar.valid) {\n assert(\n dut_mem.ar.bits.id === gold_mem.ar.bits.id,\n \"* dut.io.nasti.ar.bits.id => %x != %x *\\n\",\n dut_mem.ar.bits.id,\n gold_mem.ar.bits.id\n )\n assert(\n gold_mem.ar.bits.addr === dut_mem.ar.bits.addr,\n \"* dut.io.nasti.ar.bits.addr => %x != %x *\\n\",\n dut_mem.ar.bits.addr,\n gold_mem.ar.bits.addr\n )\n assert(\n gold_mem.ar.bits.size === dut_mem.ar.bits.size,\n \"* dut.io.nasti.ar.bits.size => %x != %x *\\n\",\n dut_mem.ar.bits.size,\n gold_mem.ar.bits.size\n )\n assert(\n gold_mem.ar.bits.len === dut_mem.ar.bits.len,\n \"* dut.io.nasti.ar.bits.len => %x != %x *\\nn\",\n dut_mem.ar.bits.len,\n gold_mem.ar.bits.len\n )\n memState := sMemRead\n }\n }\n is(sMemWrite) {\n assert(dut_mem.aw.bits.size === size)\n assert(dut_mem.aw.bits.len === len)\n when(gold_mem.w.valid && dut_mem.w.valid) {\n assert(\n dut_mem.w.bits.data === gold_mem.w.bits.data,\n \"* dut.io.nasti.w.bits.data => %x != %x *\\n\",\n dut_mem.w.bits.data,\n gold_mem.w.bits.data\n )\n assert(\n dut_mem.w.bits.strb === gold_mem.w.bits.strb,\n \"* dut.io.nasti.w.bits.strb => %x != %x *\\n\",\n dut_mem.w.bits.strb,\n gold_mem.w.bits.strb\n )\n assert(\n dut_mem.w.bits.last === gold_mem.w.bits.last,\n \"* dut.io.nasti.w.bits.last => %x != %x *\\n\",\n dut_mem.w.bits.last,\n gold_mem.w.bits.last\n )\n assert(dut_mem.w.bits.strb === ((1 << (nasti.dataBits / 8)) - 1).U) // TODO: release it?\n mem((dut_mem.aw.bits.addr >> size).asUInt + wCnt) := dut_mem.w.bits.data\n printf(\"[write] mem[%x] <= %x\\n\", (dut_mem.aw.bits.addr >> size).asUInt + wCnt, dut_mem.w.bits.data)\n dut_mem.w.ready := true.B\n }\n when(wDone) {\n dut_mem.aw.ready := true.B\n memState := sMemWrAck\n }\n }\n is(sMemWrAck) {\n when(gold_mem.b.ready && dut_mem.b.ready) {\n memState := sMemIdle\n }\n }\n is(sMemRead) {\n when(dut_mem.r.ready && gold_mem.r.ready) {\n printf(\"[read] mem[%x] => %x\\n\", (dut_mem.ar.bits.addr >> size).asUInt + rCnt, dut_mem.r.bits.data)\n }\n when(rDone) {\n dut_mem.ar.ready := true.B\n memState := sMemIdle\n }\n }\n }\n\n /* Tests */\n val seed = System.currentTimeMillis()\n val rnd = new scala.util.Random(seed)\n println(s\"CacheTester using seed $seed\")\n\n def rand_tag = rnd.nextInt(1 << tlen).U(tlen.W)\n", "right_context": " def rand_off = (rnd.nextInt(1 << blen) & -4).U(blen.W)\n def rand_data = (0 until (nasti.dataBits / 8))\n .foldLeft(BigInt(0))((r, i) => r | (BigInt(rnd.nextInt(0xff + 1)) << (8 * i)))\n .U(nasti.dataBits.W)\n def rand_mask = (rnd.nextInt((1 << (xlen / 8)) - 1) + 1).U((xlen / 8).W)\n def test(tag: UInt, idx: UInt, off: UInt, mask: UInt = 0.U((xlen / 8).W)) =\n Cat(mask, Cat(Seq.fill(bBits / nasti.dataBits)(rand_data)), tag, idx, off)\n\n val tags = Vector.fill(3)(rand_tag)\n val idxs = Vector.fill(2)(rand_idx)\n val offs = Vector.fill(6)(rand_off)\n\n val initAddr = for {\n tag <- tags\n idx <- idxs\n off <- 0 until dataBeats\n } yield Cat(tag, idx, off.U)\n val initData = Seq.fill(initAddr.size)(rand_data)\n val testVec = Seq(\n test(tags(0), idxs(0), offs(0)), // #0: read miss\n test(tags(0), idxs(0), offs(1)), // #1: read hit\n test(tags(1), idxs(0), offs(0)), // #2: read miss\n test(tags(1), idxs(0), offs(2)), // #3: read hit\n test(tags(1), idxs(0), offs(3)), // #4: read hit\n test(tags(1), idxs(0), offs(4), rand_mask), // #5: write hit\n test(tags(1), idxs(0), offs(4)), // #6: read hit\n test(tags(2), idxs(0), offs(5)), // #7: read miss & write back\n test(tags(0), idxs(1), offs(0), rand_mask), // #8: write miss\n test(tags(0), idxs(1), offs(0)), // #9: read hit\n test(tags(0), idxs(1), offs(1)), // #10: read hit\n test(tags(1), idxs(1), offs(2), rand_mask), // #11: write miss & write back\n test(tags(1), idxs(1), offs(3)), // #12: read hit\n test(tags(2), idxs(1), offs(4)), // #13: read write back\n test(tags(2), idxs(1), offs(5)) // #14: read hit\n )\n\n import CacheTesterState._\n val state = RegInit(sInit)\n val timeout = Reg(UInt(32.W))\n val (initCnt, initDone) = Counter(state === sInit, initAddr.size)\n val (testCnt, testDone) = Counter(state === sDone, testVec.size)\n val mask = (VecInit(testVec)(testCnt) >> (blen + slen + tlen + bBits)).asUInt\n val data = (VecInit(testVec)(testCnt) >> (blen + slen + tlen))(bBits - 1, 0)\n val tag = (VecInit(testVec)(testCnt) >> (blen + slen).U)(tlen - 1, 0)\n val idx = (VecInit(testVec)(testCnt) >> blen.U)(slen - 1, 0)\n val off = VecInit(testVec)(testCnt)(blen - 1, 0)\n dut.io.cpu.req.bits.addr := Cat(tag, idx, off)\n dut.io.cpu.req.bits.data := data\n dut.io.cpu.req.bits.mask := mask\n dut.io.cpu.req.valid := state === sWait\n dut.io.cpu.abort := DontCare\n gold_req.bits := dut.io.cpu.req.bits\n gold_req.valid := state === sStart\n gold_resp.ready := state === sDone\n\n switch(state) {\n is(sInit) {\n mem(VecInit(initAddr)(initCnt)) := VecInit(initData)(initCnt)\n printf(\"[init] mem[%x] <= %x\\n\", VecInit(initAddr)(initCnt), VecInit(initData)(initCnt))\n when(initDone) {\n state := sStart\n }\n }\n is(sStart) {\n when(gold_req.ready) {\n timeout := 0.U\n state := sWait\n }\n }\n is(sWait) {\n timeout := timeout + 1.U\n assert(timeout < 100.U)\n when(dut.io.cpu.resp.valid && gold_resp.valid) {\n when(!mask.orR) {\n assert(\n dut.io.cpu.resp.bits.data === gold_resp.bits.data,\n \"* dut.io.cpu.resp.bits.data => %x ?= %x *\\n\",\n dut.io.cpu.resp.bits.data,\n gold_resp.bits.data\n )\n }\n state := sDone\n }\n }\n is(sDone) {\n state := sStart\n }\n }\n\n when(testDone) { stop() }\n}\n\nclass CacheTests extends AnyFlatSpec with ChiselScalatestTester {\n val p = MiniConfig()\n\n \"Cache\" should \"pass with verilator\" in {\n test(new CacheTester(new Cache(p.cache, p.nasti, p.core.xlen)))\n .withAnnotations(Seq(VerilatorBackendAnnotation))\n .runUntilStop()\n }\n\n \"Cache\" should \"pass with treadle\" in {\n test(new CacheTester(new Cache(p.cache, p.nasti, p.core.xlen))).runUntilStop()\n }\n}\n", "groundtruth": " def rand_idx = rnd.nextInt(1 << slen).U(slen.W)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "riscv-mini", "path": "riscv-mini/src/test/scala/mini/CoreTests.scala", "left_context": "// See LICENSE for license details.\n\npackage mini\n\nimport chisel3._\nimport chisel3.testers._\nimport chisel3.util.experimental.loadMemoryFromFileInline\nimport chiseltest._\nimport org.scalatest.flatspec.AnyFlatSpec\n\nclass CoreTester(core: => Core, benchmark: String, trace: Boolean = false) extends BasicTester {\n val originalHexFile = os.rel / \"tests\" / f\"$benchmark.hex\"\n val resizedHexFile = os.rel / \"tests\" / \"32\" / f\"$benchmark.hex\"\n TestUtils.resizeHexFile(os.pwd / originalHexFile, os.pwd / resizedHexFile, 32) // we have 32 bits per memory entry\n\n val dut = Module(core)\n val xlen = dut.conf.xlen\n dut.io.host.fromhost.bits := DontCare\n dut.io.host.fromhost.valid := false.B\n\n val imem = Mem(1 << 20, UInt(xlen.W))\n loadMemoryFromFileInline(imem, resizedHexFile.toString())\n val dmem = Mem(1 << 20, UInt(xlen.W))\n loadMemoryFromFileInline(dmem, resizedHexFile.toString())\n\n val cycle = RegInit(0.U(32.W))\n val iaddr = dut.io.icache.req.bits.addr / (xlen / 8).U\n val daddr = dut.io.dcache.req.bits.addr / (xlen / 8).U\n val write = (0 until (xlen / 8)).foldLeft(0.U(xlen.W)) { (write, i) =>\n write |\n (Mux(\n (dut.io.dcache.req.valid && dut.io.dcache.req.bits.mask(i)).asBool,\n dut.io.dcache.req.bits.data,\n dmem(daddr)\n )(8 * (i + 1) - 1, 8 * i) << (8 * i).U).asUInt\n }\n dut.io.icache.resp.valid := !reset.asBool\n dut.io.dcache.resp.valid := !reset.asBool\n dut.io.icache.resp.bits.data := RegNext(imem(iaddr))\n dut.io.dcache.resp.bits.data := RegNext(dmem(daddr))\n\n when(dut.io.icache.req.valid) {\n if (trace) printf(\"INST[%x] => %x\\n\", iaddr * (xlen / 8).U, imem(iaddr))\n }\n when(dut.io.dcache.req.valid) {\n when(dut.io.dcache.req.bits.mask.orR) {\n dmem(daddr) := write\n if (trace) printf(\"MEM[%x] <= %x\\n\", daddr * (xlen / 8).U, write)\n }.otherwise {\n", "right_context": " }\n }\n cycle := cycle + 1.U\n when(dut.io.host.tohost =/= 0.U) {\n printf(\"cycles: %d\\n\", cycle)\n assert((dut.io.host.tohost >> 1.U).asUInt === 0.U, \"* tohost: %d *\\n\", dut.io.host.tohost)\n stop()\n }\n}\n\nobject DefaultCoreConfig {\n def apply() = MiniConfig().core\n}\n\nclass CoreSimpleTests extends AnyFlatSpec with ChiselScalatestTester {\n behavior.of(\"Core\")\n it should \"execute a simple test\" in {\n test(new CoreTester(new Core(DefaultCoreConfig()), \"rv32ui-p-simple\")).runUntilStop(100)\n }\n}\n\nabstract class CoreTests(cfg: TestConfig, useVerilator: Boolean = false)\n extends AnyFlatSpec\n with ChiselScalatestTester {\n behavior.of(\"Core\")\n val opts = if (useVerilator) Seq(VerilatorBackendAnnotation) else Seq()\n cfg.tests.foreach { name =>\n it should s\"execute $name\" taggedAs IntegrationTest in {\n test(new CoreTester(new Core(DefaultCoreConfig()), name)).withAnnotations(opts).runUntilStop(cfg.maxcycles)\n }\n }\n}\n\nclass CoreISATests extends CoreTests(ISATests)\nclass CoreBmarkTests extends CoreTests(BmarkTests, true)\n", "groundtruth": " if (trace) printf(\"MEM[%x] => %x\\n\", daddr * (xlen / 8).U, dmem(daddr))\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.55, "category_reason": "Code near when block"} {"task_id": "riscv-mini", "path": "riscv-mini/src/test/scala/mini/DatapathTests.scala", "left_context": "// See LICENSE for license details.\n\npackage mini\n\nimport chisel3._\nimport chisel3.testers._\nimport chisel3.util._\nimport chiseltest._\nimport org.scalatest.flatspec.AnyFlatSpec\n\nobject DatapathTesterState extends ChiselEnum {\n val sInit, sRun = Value\n}\n\nclass DatapathTester(datapath: => Datapath, testType: DatapathTest) extends BasicTester with TestUtils {\n val dut = Module(datapath)\n val ctrl = Module(new Control)\n val xlen = dut.conf.xlen\n\n dut.io.ctrl <> ctrl.io\n dut.io.host.fromhost.bits := DontCare\n dut.io.host.fromhost.valid := false.B\n\n override val insts = tests(testType)\n\n import DatapathTesterState._\n val state = RegInit(sInit)\n val (cntr, done) = Counter(state === sInit, insts.size)\n val timeout = RegInit(0.U(32.W))\n val mem = Mem(1 << 20, UInt(xlen.W))\n val iaddr = dut.io.icache.req.bits.addr / (xlen / 8).U\n val daddr = dut.io.dcache.req.bits.addr / (xlen / 8).U\n val write = (0 until (xlen / 8)).foldLeft(0.U) { (data, i) =>\n data |\n (Mux(dut.io.dcache.req.bits.mask(i), dut.io.dcache.req.bits.data, mem(daddr)) & (BigInt(0xff) << (8 * i)).U)\n }\n dut.reset := state === sInit\n dut.io.icache.resp.bits.data := RegNext(mem(iaddr))\n dut.io.icache.resp.valid := state === sRun\n dut.io.dcache.resp.bits.data := RegNext(mem(daddr))\n dut.io.dcache.resp.valid := state === sRun\n\n switch(state) {\n is(sInit) {\n (0 until Consts.PC_START by 4).foreach { addr =>\n mem((addr / 4).U) := (if (addr == Consts.PC_EVEC + (3 << 6)) fin else nop)\n }\n mem((Consts.PC_START / (xlen / 8)).U + cntr) := VecInit(insts)(cntr)\n", "right_context": " }\n is(sRun) {\n when(dut.io.icache.req.valid) {\n printf(s\"INST[%x] => %x, iaddr: %x\\n\", dut.io.icache.req.bits.addr, mem(iaddr), iaddr)\n }\n when(dut.io.dcache.req.valid) {\n when(dut.io.dcache.req.bits.mask.orR) {\n mem(daddr) := write\n printf(\"MEM[%x] <= %x\\n\", dut.io.dcache.req.bits.addr, write)\n }.otherwise {\n printf(\"MEM[%x] => %x\\n\", dut.io.dcache.req.bits.addr, mem(daddr))\n }\n }\n timeout := timeout + 1.U\n assert(timeout < 100.U)\n when(dut.io.host.tohost =/= 0.U) {\n assert(\n dut.io.host.tohost === testResults(testType).U,\n s\"* tohost: %d != ${testResults(testType)} *\",\n dut.io.host.tohost\n )\n stop()\n }\n }\n }\n}\n\nclass DatapathTests extends AnyFlatSpec with ChiselScalatestTester {\n val p = MiniConfig()\n Seq(BypassTest, ExceptionTest).foreach { tst =>\n \"Datapath\" should s\"pass $tst\" in {\n test(new DatapathTester(new Datapath(p.core), tst)).runUntilStop()\n }\n }\n}\n", "groundtruth": " when(done) { state := sRun }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "riscv-mini", "path": "riscv-mini/src/test/scala/mini/ImmGenTests.scala", "left_context": "// See LICENSE for license details.\n\npackage mini\n\nimport chisel3._\nimport chisel3.testers._\nimport chisel3.util._\nimport chiseltest._\nimport chiseltest.formal._\nimport org.scalatest.flatspec.AnyFlatSpec\n\nclass ImmGenTester(imm: => ImmGen) extends BasicTester with TestUtils {\n import Control._\n val dut = Module(imm)\n val ctrl = Module(new Control)\n\n val (cntr, done) = Counter(true.B, insts.size)\n val i = VecInit(insts.map(iimm))\n val s = VecInit(insts.map(simm))\n val b = VecInit(insts.map(bimm))\n val u = VecInit(insts.map(uimm))\n val j = VecInit(insts.map(jimm))\n val z = VecInit(insts.map(zimm))\n val x = VecInit(insts.map(iimm).map(x => (x.litValue & -2).U))\n val out = Mux(\n dut.io.sel === IMM_I,\n i(cntr),\n Mux(\n dut.io.sel === IMM_S,\n s(cntr),\n Mux(\n dut.io.sel === IMM_B,\n b(cntr),\n Mux(\n dut.io.sel === IMM_U,\n u(cntr),\n Mux(dut.io.sel === IMM_J, j(cntr), Mux(dut.io.sel === IMM_Z, z(cntr), x(cntr)))\n )\n )\n )\n )\n\n ctrl.io.inst := VecInit(insts)(cntr)\n dut.io.inst := ctrl.io.inst\n dut.io.sel := ctrl.io.imm_sel\n\n", "right_context": " assert(dut.io.out === out)\n printf(\"Counter: %d, Type: 0x%x, Out: %x ?= %x\\n\", cntr, dut.io.sel, dut.io.out, out)\n}\n\nclass ImmGenTests extends AnyFlatSpec with ChiselScalatestTester with Formal {\n \"ImmGenWire\" should \"pass\" in {\n test(new ImmGenTester(new ImmGenWire(32))).runUntilStop()\n }\n \"ImmGenMux\" should \"pass\" in {\n test(new ImmGenTester(new ImmGenMux(32))).runUntilStop()\n }\n \"ImmGenMux\" should \"be equivalent to ImmGenWire\" in {\n // since there is no state (registers/memory) in the ImmGen, a single cycle check is enough to prove equivalence\n verify(new ImmGenEquivalenceCheck(new ImmGenMux(32)), Seq(BoundedCheck(1)))\n }\n}\n\nclass ImmGenEquivalenceCheck(other: => ImmGen) extends Module {\n val dut = Module(other)\n val ref = Module(new ImmGenWire(dut.xlen))\n\n // arbitrary inputs\n val io = IO(chiselTypeOf(dut.io))\n\n // connect the same inputs to both modules (the outputs will be overwritten to always connect to the reference)\n dut.io <> io; ref.io <> io\n\n // check to ensure that outputs are the same\n assert(ref.io.out === dut.io.out, \"out: expected: %d, actual: %d\", ref.io.out, dut.io.out)\n}\n", "groundtruth": " when(done) { stop() }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "riscv-mini", "path": "riscv-mini/src/test/scala/mini/IntegrationTest.scala", "left_context": "// See LICENSE for license details.\npackage mini\n\nimport org.scalatest.Tag\n\n", "right_context": "", "groundtruth": "object IntegrationTest extends Tag(\"IntegrationTest\")\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "riscv-mini", "path": "riscv-mini/src/test/scala/mini/Opcode.scala", "left_context": "// See LICENSE for license details.\n\npackage mini\n\nimport chisel3._\n\nobject Opcode {\n // Special immediate instructions\n val LUI = BigInt(\"0110111\", 2).U(7.W)\n val AUIPC = BigInt(\"0010111\", 2).U(7.W)\n\n // Jump instructions\n val JAL = BigInt(\"1101111\", 2).U(7.W)\n val JALR = BigInt(\"1100111\", 2).U(7.W)\n\n // Branch instructions\n val BRANCH = BigInt(\"1100011\", 2).U(7.W)\n\n // Load and store instrucdtions\n val STORE = BigInt(\"0100011\", 2).U(7.W)\n val LOAD = BigInt(\"0000011\", 2).U(7.W)\n\n // Arithmetic instructions\n val RTYPE = BigInt(\"0110011\", 2).U(7.W)\n val ITYPE = BigInt(\"0010011\", 2).U(7.W)\n\n val MEMORY = BigInt(\"0001111\", 2).U(7.W)\n val SYSTEM = BigInt(\"1110011\", 2).U(7.W)\n}\n\nobject Funct3 {\n // Branch function codes\n val BEQ = BigInt(\"000\", 2).U(3.W)\n val BNE = BigInt(\"001\", 2).U(3.W)\n val BLT = BigInt(\"100\", 2).U(3.W)\n val BGE = BigInt(\"101\", 2).U(3.W)\n val BLTU = BigInt(\"110\", 2).U(3.W)\n val BGEU = BigInt(\"111\", 2).U(3.W)\n\n // Load and store function codes\n val LB = BigInt(\"000\", 2).U(3.W)\n val LH = BigInt(\"001\", 2).U(3.W)\n val LW = BigInt(\"010\", 2).U(3.W)\n val LBU = BigInt(\"100\", 2).U(3.W)\n val LHU = BigInt(\"101\", 2).U(3.W)\n val SB = BigInt(\"000\", 2).U(3.W)\n val SH = BigInt(\"001\", 2).U(3.W)\n val SW = BigInt(\"010\", 2).U(3.W)\n\n // Arithmetic R-type and I-type functions codes\n val ADD = BigInt(\"000\", 2).U(3.W)\n val SLL = BigInt(\"001\", 2).U(3.W)\n val SLT = BigInt(\"010\", 2).U(3.W)\n val SLTU = BigInt(\"011\", 2).U(3.W)\n val XOR = BigInt(\"100\", 2).U(3.W)\n val OR = BigInt(\"110\", 2).U(3.W)\n val AND = BigInt(\"111\", 2).U(3.W)\n val SR = BigInt(\"101\", 2).U(3.W)\n\n val CSRRW = BigInt(\"001\", 2).U(3.W)\n val CSRRS = BigInt(\"010\", 2).U(3.W)\n val CSRRC = BigInt(\"011\", 2).U(3.W)\n", "right_context": "}\n\nobject Funct7 {\n val U = BigInt(\"0000000\", 2).U(7.W)\n val S = BigInt(\"0100000\", 2).U(7.W)\n}\n\nobject Funct12 {\n val ECALL = BigInt(\"000000000000\", 2).U(12.W)\n val EBREAK = BigInt(\"000000000001\", 2).U(12.W)\n val ERET = BigInt(\"000100000000\", 2).U(12.W)\n}\n", "groundtruth": " val CSRRWI = BigInt(\"101\", 2).U(3.W)\n val CSRRSI = BigInt(\"110\", 2).U(3.W)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.6, "category_reason": "val binding"} {"task_id": "riscv-mini", "path": "riscv-mini/src/test/scala/mini/TestConfig.scala", "left_context": "// See LICENSE for license details.\n\npackage mini\n\ntrait TestConfig {\n def tests: List[String]\n def maxcycles: Int\n def namePrefix: String\n}\n\ncase object ISATests extends TestConfig {\n val tests = List(\n \"simple\",\n \"add\",\n \"addi\",\n \"auipc\",\n \"and\",\n \"andi\", // TODO: \"fence_i\",\n \"sb\",\n \"sh\",\n \"sw\",\n \"lb\",\n \"lbu\",\n \"lh\",\n \"lhu\",\n \"lui\",\n \"lw\",\n \"beq\",\n \"bge\",\n \"bgeu\",\n \"blt\",\n \"bltu\",\n \"bne\",\n \"j\",\n \"jal\",\n \"jalr\",\n \"or\",\n \"ori\",\n \"sll\",\n \"slli\",\n \"slt\",\n \"slti\",\n \"sra\",\n \"srai\",\n \"sub\",\n \"xor\",\n \"xori\"\n", "right_context": " List(\n \"sbreak\",\n \"scall\",\n \"illegal\",\n \"ma_fetch\",\n \"ma_addr\",\n \"csr\" //, TODO: \"timer\"\n ).map(t => s\"rv32mi-p-$t\")\n val maxcycles = 15000\n val namePrefix = \"ISATests\"\n}\n\ncase object BmarkTests extends TestConfig {\n val tests = List(\n \"median.riscv\",\n \"multiply.riscv\",\n \"qsort.riscv\",\n \"towers.riscv\",\n \"vvadd.riscv\"\n )\n val maxcycles = 1500000\n val namePrefix = \"BmarkTests\"\n}\n\ncase object LargeBmarkTests extends TestConfig {\n val tests = List(\n \"median.riscv-large\",\n \"multiply.riscv-large\",\n \"qsort.riscv-large\",\n \"towers.riscv-large\",\n \"vvadd.riscv-large\"\n )\n val maxcycles = 5000000\n val namePrefix = \"LargeBmarkTests\"\n}\n", "groundtruth": " ).map(t => s\"rv32ui-p-${t}\") ++\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Loop-based Control", "confidence": 0.75, "category_reason": "Functional iteration"} {"task_id": "riscv-mini", "path": "riscv-mini/src/test/scala/mini/TestUtils.scala", "left_context": "// See LICENSE for license details.\n\npackage mini\n\nimport chisel3._\nimport chisel3.util._\nimport Instructions._\nimport junctions.NastiBundleParameters\nimport org.scalatest.flatspec.AnyFlatSpec\n\nimport scala.language.implicitConversions\n\ntrait DatapathTest\nobject BypassTest extends DatapathTest {\n override def toString: String = \"bypass test\"\n}\nobject ExceptionTest extends DatapathTest {\n override def toString: String = \"exception test\"\n}\n// Define your own test\n\ntrait TestUtils {\n implicit def boolToBoolean(x: Bool): Boolean = x.litValue == 1\n implicit def bitPatToUInt(b: BitPat): UInt = BitPat.bitPatToUInt(b)\n implicit def uintToBitPat(u: UInt): BitPat = BitPat(u)\n implicit def bigIntToInt(x: BigInt): Int = x.toInt\n implicit def bigIntToBoolean(x: BigInt): Boolean = x != 0\n def toBigInt(x: Int): BigInt = (BigInt(x >>> 1) << 1) | (x & 0x1)\n\n def rs1(inst: UInt) = ((inst.litValue >> 15) & 0x1f).toInt\n def rs2(inst: UInt) = ((inst.litValue >> 20) & 0x1f).toInt\n def rd(inst: UInt) = ((inst.litValue >> 7) & 0x1f).toInt\n def csr(inst: UInt) = inst.litValue >> 20\n def reg(x: Int) = (x & ((1 << 5) - 1)).U(5.W)\n def imm(x: Int) = (x & ((1 << 20) - 1)).S(21.W)\n def Cat(l: Seq[Bits]): UInt = l.tail.foldLeft(l.head.asUInt) { (x, y) =>\n assert(x.isLit && y.isLit)\n (x.litValue << y.getWidth | y.litValue).U((x.getWidth + y.getWidth).W)\n }\n def Cat(x: Bits, l: Bits*): UInt = Cat(x :: l.toList)\n val fence = Cat(0.U(4.W), 0xf.U(4.W), 0xf.U(4.W), 0.U(13.W), Opcode.MEMORY)\n val nop = Cat(0.U(12.W), reg(0), Funct3.ADD, reg(0), Opcode.ITYPE)\n val csrRegs = CSR.regs.map(_.litValue)\n private val csrMap = csrRegs\n .zip(\n List(\n \"cycle\",\n \"time\",\n \"instret\",\n \"cycleh\",\n \"timeh\",\n \"instreth\",\n \"cyclew\",\n \"timew\",\n \"instretw\",\n \"cyclehw\",\n \"timehw\",\n \"instrethw\",\n \"mcpuid\",\n \"mimpid\",\n \"mhartid\",\n \"mtvec\",\n \"mtdeleg\",\n \"mie\",\n \"mtimecmp\",\n \"mtime\",\n \"mtimeh\",\n \"mscratch\",\n \"mepc\",\n \"mcause\",\n \"mbadaddr\",\n \"mip\",\n \"mtohost\",\n \"mfromhost\",\n \"mstatus\"\n )\n )\n .toMap\n def csrName(csr: BigInt) = csrMap.getOrElse(csr, csr.toString(16))\n\n private def inst_31(inst: UInt) = ((inst.litValue >> 31) & 0x1).U(1.W)\n private def inst_30_25(inst: UInt) = ((inst.litValue >> 25) & 0x3f).U(6.W)\n private def inst_24_21(inst: UInt) = ((inst.litValue >> 21) & 0xf).U(4.W)\n private def inst_20(inst: UInt) = ((inst.litValue >> 20) & 0x1).U(1.W)\n private def inst_19_12(inst: UInt) = ((inst.litValue >> 12) & 0xff).U(8.W)\n private def inst_11_8(inst: UInt) = ((inst.litValue >> 8) & 0xf).U(4.W)\n private def inst_7(inst: UInt) = ((inst.litValue >> 7) & 0x1).U(1.W)\n\n", "right_context": " def simm(inst: UInt) = Cat(Cat(Seq.fill(21) { inst_31(inst) }), inst_30_25(inst), inst_11_8(inst), inst_7(inst))\n def bimm(inst: UInt) =\n Cat(Cat(Seq.fill(20) { inst_31(inst) }), inst_7(inst), inst_30_25(inst), inst_11_8(inst), 0.U(1.W))\n def uimm(inst: UInt) =\n Cat(inst_31(inst), inst_30_25(inst), inst_24_21(inst), inst_20(inst), inst_19_12(inst), 0.U(12.W))\n def jimm(inst: UInt) = Cat(\n Cat(Seq.fill(12) { inst_31(inst) }),\n inst_19_12(inst),\n inst_20(inst),\n inst_30_25(inst),\n inst_24_21(inst),\n 0.U(1.W)\n )\n def zimm(inst: UInt) = ((inst.litValue >> 15) & 0x1f).U\n\n /* Define tests */\n val rnd = new scala.util.Random\n def rand_fn7 = rnd.nextInt(1 << 7).U(7.W)\n def rand_rs2 = (rnd.nextInt((1 << 5) - 1) + 1).U(5.W)\n def rand_rs1 = (rnd.nextInt((1 << 5) - 1) + 1).U(5.W)\n def rand_fn3 = rnd.nextInt(1 << 3).U(3.W)\n def rand_rd = (rnd.nextInt((1 << 5) - 1) + 1).U(5.W)\n def rand_csr = csrRegs(rnd.nextInt(csrRegs.size - 1)).U\n def rand_inst = toBigInt(rnd.nextInt()).U\n def rand_addr = toBigInt(rnd.nextInt()).U\n def rand_data = toBigInt(rnd.nextInt()).U\n\n val insts: Seq[UInt] = Seq(\n Cat(rand_fn7, rand_rs2, rand_rs1, rand_fn3, rand_rd, Opcode.LUI),\n Cat(rand_fn7, rand_rs2, rand_rs1, rand_fn3, rand_rd, Opcode.AUIPC),\n Cat(rand_fn7, rand_rs2, rand_rs1, rand_fn3, rand_rd, Opcode.JAL),\n Cat(rand_fn7, rand_rs2, rand_rs1, 0.U(3.W), rand_rd, Opcode.JALR),\n Cat(rand_fn7, rand_rs2, rand_rs1, Funct3.BEQ, rand_rd, Opcode.BRANCH),\n Cat(rand_fn7, rand_rs2, rand_rs1, Funct3.BNE, rand_rd, Opcode.BRANCH),\n Cat(rand_fn7, rand_rs2, rand_rs1, Funct3.BLT, rand_rd, Opcode.BRANCH),\n Cat(rand_fn7, rand_rs2, rand_rs1, Funct3.BGE, rand_rd, Opcode.BRANCH),\n Cat(rand_fn7, rand_rs2, rand_rs1, Funct3.BLTU, rand_rd, Opcode.BRANCH),\n Cat(rand_fn7, rand_rs2, rand_rs1, Funct3.BGEU, rand_rd, Opcode.BRANCH),\n Cat(rand_fn7, rand_rs2, rand_rs1, Funct3.LB, rand_rd, Opcode.LOAD),\n Cat(rand_fn7, rand_rs2, rand_rs1, Funct3.LH, rand_rd, Opcode.LOAD),\n Cat(rand_fn7, rand_rs2, rand_rs1, Funct3.LW, rand_rd, Opcode.LOAD),\n Cat(rand_fn7, rand_rs2, rand_rs1, Funct3.LBU, rand_rd, Opcode.LOAD),\n Cat(rand_fn7, rand_rs2, rand_rs1, Funct3.LHU, rand_rd, Opcode.LOAD),\n Cat(rand_fn7, rand_rs2, rand_rs1, Funct3.SB, rand_rd, Opcode.STORE),\n Cat(rand_fn7, rand_rs2, rand_rs1, Funct3.SH, rand_rd, Opcode.STORE),\n Cat(rand_fn7, rand_rs2, rand_rs1, Funct3.SW, rand_rd, Opcode.STORE),\n Cat(rand_fn7, rand_rs2, rand_rs1, Funct3.ADD, rand_rd, Opcode.ITYPE),\n Cat(rand_fn7, rand_rs2, rand_rs1, Funct3.SLT, rand_rd, Opcode.ITYPE),\n Cat(rand_fn7, rand_rs2, rand_rs1, Funct3.SLTU, rand_rd, Opcode.ITYPE),\n Cat(rand_fn7, rand_rs2, rand_rs1, Funct3.XOR, rand_rd, Opcode.ITYPE),\n Cat(rand_fn7, rand_rs2, rand_rs1, Funct3.OR, rand_rd, Opcode.ITYPE),\n Cat(rand_fn7, rand_rs2, rand_rs1, Funct3.AND, rand_rd, Opcode.ITYPE),\n Cat(Funct7.U, rand_rs2, rand_rs1, Funct3.SLL, rand_rd, Opcode.ITYPE),\n Cat(Funct7.U, rand_rs2, rand_rs1, Funct3.SR, rand_rd, Opcode.ITYPE),\n Cat(Funct7.S, rand_rs2, rand_rs1, Funct3.SR, rand_rd, Opcode.ITYPE),\n Cat(Funct7.U, rand_rs2, rand_rs1, Funct3.ADD, rand_rd, Opcode.RTYPE),\n Cat(Funct7.S, rand_rs2, rand_rs1, Funct3.ADD, rand_rd, Opcode.RTYPE),\n Cat(Funct7.U, rand_rs2, rand_rs1, Funct3.SLL, rand_rd, Opcode.RTYPE),\n Cat(Funct7.U, rand_rs2, rand_rs1, Funct3.SLT, rand_rd, Opcode.RTYPE),\n Cat(Funct7.U, rand_rs2, rand_rs1, Funct3.SLTU, rand_rd, Opcode.RTYPE),\n Cat(Funct7.U, rand_rs2, rand_rs1, Funct3.XOR, rand_rd, Opcode.RTYPE),\n Cat(Funct7.U, rand_rs2, rand_rs1, Funct3.SR, rand_rd, Opcode.RTYPE),\n Cat(Funct7.S, rand_rs2, rand_rs1, Funct3.SR, rand_rd, Opcode.RTYPE),\n Cat(Funct7.U, rand_rs2, rand_rs1, Funct3.OR, rand_rd, Opcode.RTYPE),\n Cat(Funct7.U, rand_rs2, rand_rs1, Funct3.AND, rand_rd, Opcode.RTYPE),\n fence,\n FENCEI,\n Cat(rand_csr, rand_rs1, Funct3.CSRRW, rand_rd, Opcode.SYSTEM),\n Cat(rand_csr, rand_rs1, Funct3.CSRRS, rand_rd, Opcode.SYSTEM),\n Cat(rand_csr, rand_rs1, Funct3.CSRRC, rand_rd, Opcode.SYSTEM),\n Cat(rand_csr, rand_rs1, Funct3.CSRRWI, rand_rd, Opcode.SYSTEM),\n Cat(rand_csr, rand_rs1, Funct3.CSRRSI, rand_rd, Opcode.SYSTEM),\n Cat(rand_csr, rand_rs1, Funct3.CSRRCI, rand_rd, Opcode.SYSTEM),\n ECALL,\n EBREAK,\n ERET,\n nop,\n rand_inst\n )\n\n def RU(funct3: UInt, rd: Int, rs1: Int, rs2: Int) =\n Cat(Funct7.U, reg(rs2), reg(rs1), funct3, reg(rd), Opcode.RTYPE)\n def RS(funct3: UInt, rd: Int, rs1: Int, rs2: Int) =\n Cat(Funct7.S, reg(rs2), reg(rs1), funct3, reg(rd), Opcode.RTYPE)\n def I(funct3: UInt, rd: Int, rs1: Int, i: Int) =\n Cat(imm(i)(11, 0), reg(rs1), funct3, reg(rd), Opcode.ITYPE)\n def L(funct3: UInt, rd: Int, rs1: Int, i: Int) =\n Cat(imm(i)(11, 0), reg(rs1), funct3, reg(rd), Opcode.LOAD)\n def S(funct3: UInt, rs2: Int, rs1: Int, i: Int) =\n Cat(imm(i)(11, 5), reg(rs2), reg(rs1), funct3, imm(i)(4, 0), Opcode.STORE)\n def B(funct3: UInt, rs1: Int, rs2: Int, i: Int) =\n Cat(imm(i)(12), imm(i)(10, 5), reg(rs2), reg(rs1), funct3, imm(i)(4, 1), imm(i)(11), Opcode.BRANCH)\n def U(op: UInt, rd: Int, i: Int) =\n Cat(imm(i), reg(rd), op)\n def J(rd: Int, i: Int) =\n Cat(imm(i)(20), imm(i)(10, 1), imm(i)(11), imm(i)(19, 12), reg(rd), Opcode.JAL)\n def JR(rd: Int, rs1: Int, i: Int) =\n Cat(imm(i)(11, 0), reg(rs1), 0.U(3.W), reg(rd), Opcode.JALR)\n def SYS(funct3: UInt, rd: Int, csr: UInt, rs1: Int) =\n Cat(csr, reg(rs1), funct3, reg(rd), Opcode.SYSTEM)\n\n val fin = Cat(CSR.mtohost, reg(31), Funct3.CSRRW, reg(0), Opcode.SYSTEM)\n val bypassTest = List(\n I(Funct3.ADD, 1, 0, 1), // ADDI x1, x0, 1 # x1 <- 1\n S(Funct3.SW, 1, 0, 12), // SW x1, x0, 12 # Mem[12] <- 1\n L(Funct3.LW, 2, 0, 12), // LW x2, x0, 12 # x2 <- 1\n RU(Funct3.ADD, 3, 2, 2), // ADD x3, x2, x2 # x3 <- 2\n RS(Funct3.ADD, 4, 3, 2), // SUB x4, x2, x3 # x4 <- 1\n RU(Funct3.SLL, 5, 3, 4), // SLL x5, x2, x4 # x5 <- 4\n RU(Funct3.SLT, 6, 4, 5), // SLT x6, x4, x5 # x6 <- 1\n B(Funct3.BEQ, 1, 6, 8), // BEQ x1, x6, 8 # go to the BGE branch\n J(0, 12), // JAL x0, 12 # skip nop\n B(Funct3.BGE, 4, 1, -4), // BGE x4, x1, -4 # go to the jump\n nop,\n nop,\n RU(Funct3.ADD, 26, 0, 1), // ADD x26, x0, x1 # x26 <- 1\n RU(Funct3.ADD, 27, 26, 2), // ADD x27, x26, x2 # x27 <- 2\n RU(Funct3.ADD, 28, 27, 3), // ADD x28, x27, x3 # x28 <- 4\n RU(Funct3.ADD, 29, 28, 4), // ADD x29, x28, x4 # x29 <- 5\n RU(Funct3.ADD, 30, 29, 5), // ADD x30, x29, x5 # x30 <- 9\n RU(Funct3.ADD, 31, 30, 6), // ADD x31, x31, x6 # x31 <- 10\n fin\n )\n val exceptionTest = List(\n fence,\n I(Funct3.ADD, 31, 0, 2), // ADDI x31, x0, 1 # x31 <- 2\n I(Funct3.ADD, 31, 31, 1), // ADDI x31, x31, 1 # x31 <- 3\n I(Funct3.ADD, 31, 31, 1), // ADDI x31, x32, 1 # x31 <- 4\n 0.U, // exception\n I(Funct3.ADD, 31, 31, 1), // ADDI x31, x31, 1 # x31 <- 5\n I(Funct3.ADD, 31, 31, 1), // ADDI x31, x31, 1 # x31 <- 6\n I(Funct3.ADD, 31, 31, 1), // ADDI x31, x31, 1 # x31 <- 7\n fin\n )\n val tests = Map(BypassTest -> bypassTest, ExceptionTest -> exceptionTest)\n val testResults = Map(\n BypassTest -> 10,\n ExceptionTest -> 4\n )\n}\n\nobject TestUtils {\n def resizeHexFile(originalHexFile: os.Path, resizedHexFile: os.Path, resizedWidth: Int): Unit = {\n val hexFileLines = os.read.lines(originalHexFile)\n val resizedLines = resizeHexFileInner(hexFileLines, resizedWidth)\n os.write.over(resizedHexFile, resizedLines.mkString(\"\\n\"), createFolders = true)\n }\n\n def resizeHexFileInner(hexFileLines: Seq[String], resizedWidth: Int): Seq[String] = {\n val hexFileLineLengths = hexFileLines.filter(_.nonEmpty).map(_.length)\n assert(hexFileLineLengths.forall(_ == hexFileLineLengths.head), \"hex file has lines of differing lengths\")\n val originalWidth = hexFileLineLengths.head * 4 // 4 bits / nibble\n\n if (originalWidth > resizedWidth) {\n assert(\n originalWidth % resizedWidth == 0,\n f\"The original width of the hex file ($originalWidth) is not evenly divisible by the desired resized width ($resizedWidth)\"\n )\n\n hexFileLines.flatMap(_.grouped(resizedWidth / 4).toSeq.reverse)\n } else if (originalWidth < resizedWidth) {\n ???\n } else { // no resizing\n hexFileLines\n }\n }\n}\n\nclass TestUtilsTests extends AnyFlatSpec {\n \"resizeHexFile\" should \"resize to a smaller word size\" in {\n val in = Seq(\"12345678deadbeef1010101066666666\", \"11112222333344445555666677778888\")\n val out = TestUtils.resizeHexFileInner(in, 32)\n assert(out == Seq(\"66666666\", \"10101010\", \"deadbeef\", \"12345678\", \"77778888\", \"55556666\", \"33334444\", \"11112222\"))\n\n val out2 = TestUtils.resizeHexFileInner(in, 64)\n assert(out2 == Seq(\"1010101066666666\", \"12345678deadbeef\", \"5555666677778888\", \"1111222233334444\"))\n }\n}\n\nobject TestParams {\n val Nasti = NastiBundleParameters(addrBits = 32, dataBits = 64, idBits = 5)\n}\n", "groundtruth": " def iimm(inst: UInt) = Cat(Cat(Seq.fill(21) { inst_31(inst) }), inst_30_25(inst), inst_24_21(inst), inst_20(inst))\n", "crossfile_context": "", "category": "Computation Block", "subcategory": "Type Casting and Conversion", "confidence": 0.75, "category_reason": "Cat/Fill operation"} {"task_id": "riscv-mini", "path": "riscv-mini/src/test/scala/mini/TileTester.scala", "left_context": "// See LICENSE for license details.\n\npackage mini\n\nimport chisel3._\nimport chisel3.testers._\nimport chisel3.util._\nimport chisel3.util.experimental.loadMemoryFromFileInline\nimport chiseltest._\nimport junctions._\nimport org.scalatest.flatspec.AnyFlatSpec\n\nobject TileTesterState extends ChiselEnum {\n val sIdle, sWrite, sWrAck, sRead = Value\n}\n\nclass TileTester(tile: => Tile, benchmark: String, latency: Int = 8, trace: Boolean = false) extends BasicTester {\n val originalHexFile = os.rel / \"tests\" / f\"$benchmark.hex\"\n val resizedHexFile = os.rel / \"tests\" / \"64\" / f\"$benchmark.hex\"\n TestUtils.resizeHexFile(os.pwd / originalHexFile, os.pwd / resizedHexFile, 64) // we have 64 bits per memory entry\n\n val dut = Module(tile)\n // extract parameters from design under test\n val nasti = dut.nastiParams\n\n dut.io.host.fromhost.bits := 0.U\n dut.io.host.fromhost.valid := false.B\n\n val _mem = Mem(1 << 20, UInt(nasti.dataBits.W))\n loadMemoryFromFileInline(_mem, resizedHexFile.toString())\n import TileTesterState._\n val state = RegInit(sIdle)\n val cycle = RegInit(0.U(32.W))\n\n val id = Reg(UInt(nasti.idBits.W))\n val addr = Reg(UInt(nasti.addrBits.W))\n val len = Reg(UInt(NastiConstants.LenBits.W))\n val off = Reg(UInt(NastiConstants.LenBits.W))\n val write = (0 until (nasti.dataBits / 8)).foldLeft(0.U(nasti.dataBits.W)) { (write, i) =>\n write |\n (Mux(dut.io.nasti.w.bits.strb(i), dut.io.nasti.w.bits.data, _mem(addr))(\n 8 * (i + 1) - 1,\n 8 * i\n ) << (8 * i).U).asUInt\n }\n val bpipe = WireInit(dut.io.nasti.b)\n val rpipe = WireInit(dut.io.nasti.r)\n\n dut.reset := reset.asBool\n dut.io.nasti.aw.ready := state === sIdle\n dut.io.nasti.ar.ready := state === sIdle\n dut.io.nasti.w.ready := state === sWrite\n dut.io.nasti.b <> LatencyPipe(bpipe, latency)\n dut.io.nasti.r <> LatencyPipe(rpipe, latency)\n bpipe.bits := NastiWriteResponseBundle(nasti)(id)\n bpipe.valid := state === sWrAck\n rpipe.bits := NastiReadDataBundle(nasti)(id, _mem(addr + off), off === len)\n rpipe.valid := state === sRead\n\n val isDone = WireInit(false.B)\n val setDone = WireInit(false.B)\n\n cycle := cycle + 1.U\n when(dut.io.host.tohost =/= 0.U) {\n isDone := true.B\n }\n\n setDone := isDone\n when(setDone) {\n printf(\"cycles: %d\\n\", cycle)\n assert((dut.io.host.tohost >> 1.U) === 0.U, \"* tohost: %d *\\n\", dut.io.host.tohost)\n stop()\n }\n\n /**\n * Master(Tile) --------- Slaver(Memory)\n *\n * Address Write > == AW == >\n * Data Write > == W == >\n * Response < == B == <\n *\n * Address Read > == AR == >\n * Data Read < == R == <\n */\n\n switch(state) {\n is(sIdle) {\n when(dut.io.nasti.aw.valid) {\n assert((1.U << dut.io.nasti.aw.bits.size).asUInt === (nasti.dataBits / 8).U)\n addr := dut.io.nasti.aw.bits.addr / (nasti.dataBits / 8).U\n id := dut.io.nasti.aw.bits.id\n len := dut.io.nasti.aw.bits.len\n off := 0.U\n state := sWrite\n }.elsewhen(dut.io.nasti.ar.valid) {\n assert((1.U << dut.io.nasti.ar.bits.size).asUInt === (nasti.dataBits / 8).U)\n addr := dut.io.nasti.ar.bits.addr / (nasti.dataBits / 8).U\n id := dut.io.nasti.ar.bits.id\n len := dut.io.nasti.ar.bits.len\n off := 0.U\n state := sRead\n }\n }\n is(sWrite) {\n when(dut.io.nasti.w.valid) {\n _mem(addr + off) := write\n", "right_context": " when(off === len) {\n assert(dut.io.nasti.w.bits.last)\n state := sWrAck\n }.otherwise {\n off := off + 1.U\n }\n }\n }\n is(sWrAck) {\n when(bpipe.ready) {\n state := sIdle\n }\n }\n is(sRead) {\n when(rpipe.ready) {\n when(off === len) {\n state := sIdle\n }.otherwise {\n off := off + 1.U\n }\n }\n }\n }\n}\n\nclass LatencyPipeIO[T <: Data](val gen: T) extends Bundle {\n val in = Flipped(Decoupled(gen))\n val out = Decoupled(gen)\n}\n\nclass LatencyPipe[T <: Data](gen: T, latency: Int) extends Module {\n val io = IO(new LatencyPipeIO(chiselTypeOf(gen)))\n io := DontCare\n io.out <> (0 until latency).foldLeft(io.in)((in, i) => Queue(in, 1, pipe = true))\n}\n\nobject LatencyPipe {\n def apply[T <: Data](in: DecoupledIO[T], latency: Int) = {\n val pipe = Module(new LatencyPipe(in.bits, latency))\n pipe.io.in <> in\n pipe.io.out\n }\n}\n\nclass TileSimpleTests extends AnyFlatSpec with ChiselScalatestTester {\n behavior.of(\"Tile\")\n val p = MiniConfig()\n it should \"execute a simple test\" in {\n test(new TileTester(Tile(p), \"rv32ui-p-simple\")).runUntilStop(15000)\n }\n}\n\nabstract class TileTests(cfg: TestConfig, useVerilator: Boolean = false)\n extends AnyFlatSpec\n with ChiselScalatestTester {\n behavior.of(\"Tile\")\n val opts = if (useVerilator) Seq(VerilatorBackendAnnotation) else Seq()\n val p = MiniConfig()\n cfg.tests.foreach { name =>\n it should s\"execute $name\" taggedAs IntegrationTest in {\n test(new TileTester(Tile(p), name)).withAnnotations(opts).runUntilStop(cfg.maxcycles)\n }\n }\n}\n\nclass TileISATests extends TileTests(ISATests, true)\nclass TileBmarkTests extends TileTests(BmarkTests, true)\nclass TileLargeBmarkTests extends TileTests(LargeBmarkTests, true)\n", "groundtruth": " if (trace) printf(\"MEM[%x] <= %x\\n\", (addr + off) * (nasti.dataBits / 8).U, write)\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.55, "category_reason": "Code near when block"} {"task_id": "fpga_final_project", "path": "fpga_final_project/src/main/scala/bram/bram.scala", "left_context": "package final_project\n\nimport chisel3._\nimport chisel3.util._\n\nclass TrueDualPortWire(w: Int, addr_w: Int) extends Bundle{\n val addra = Input(UInt(addr_w.W))\n val dina = Input(UInt(w.W))\n val douta = Output(UInt(w.W))\n val wea = Input(Bool())\n val addrb = Input(UInt(addr_w.W))\n val dinb = Input(UInt(w.W))\n val doutb = Output(UInt(w.W))\n val web = Input(Bool())\n}\n\n\nclass TrueDualPort(w: Int, addr_w: Int) extends Bundle{\n val clka = Input(Clock())\n val clkb = Input(Clock())\n \n val addra = Input(UInt(addr_w.W))\n val dina = Input(UInt(w.W))\n val douta = Output(UInt(w.W))\n val wea = Input(Bool())\n val addrb = Input(UInt(addr_w.W))\n val dinb = Input(UInt(w.W))\n val doutb = Output(UInt(w.W))\n val web = Input(Bool())\n}\n\nobject TrueDualPortWire{\n def apply(x: TrueDualPort, w: Int, addr_w: Int): TrueDualPortWire = {\n val ret = Wire(new TrueDualPortWire(w, addr_w))\n x.addra := ret.addra\n x.dina := ret.dina\n ret.douta := x.douta\n x.wea := ret.wea\n x.addrb := ret.addrb\n x.dinb := ret.dinb\n ret.doutb := x.doutb\n x.web := ret.web\n ret.addra := 0.U\n ret.dina := 0.U\n ret.wea := false.B\n ret.addrb := 0.U\n ret.dinb := 0.U\n ret.web := false.B\n return ret\n }\n}\n\nclass SinglePortROM(w: Int, addr_w: Int) extends Bundle{\n val addra = Input(UInt(addr_w.W))\n val clka = Input(Clock())\n val douta = Output(UInt(w.W))\n}\n\nclass big_bank0(w: Int, addr_w: Int) extends BlackBox{\n val io = IO(new TrueDualPort(w, addr_w))\n}\n\n", "right_context": " val io = IO(new TrueDualPort(w, addr_w))\n}\nclass small_bank1(w: Int, addr_w: Int) extends BlackBox{\n val io = IO(new TrueDualPort(w, addr_w))\n}\n\nclass small_bank2(w: Int, addr_w: Int) extends BlackBox{\n val io = IO(new TrueDualPort(w, addr_w))\n}\n\nclass small_bank3(w: Int, addr_w: Int) extends BlackBox{\n val io = IO(new TrueDualPort(w, addr_w))\n}\n\nclass small_bank4(w: Int, addr_w: Int) extends BlackBox{\n val io = IO(new TrueDualPort(w, addr_w))\n}\n\nclass small_bank5(w: Int, addr_w: Int) extends BlackBox{\n val io = IO(new TrueDualPort(w, addr_w))\n}\n\nclass small_bank6(w: Int, addr_w: Int) extends BlackBox{\n val io = IO(new TrueDualPort(w, addr_w))\n}\n\nclass small_bank7(w: Int, addr_w: Int) extends BlackBox{\n val io = IO(new TrueDualPort(w, addr_w))\n}\nclass weight0(w: Int, addr_w: Int) extends BlackBox{\n val io = IO(new SinglePortROM(w, addr_w))\n}\n\nclass bias0(w: Int, addr_w: Int) extends BlackBox{\n val io = IO(new SinglePortROM(w, addr_w))\n}\nclass weight0_2(w: Int, addr_w: Int) extends BlackBox{\n val io = IO(new SinglePortROM(w, addr_w))\n}\n\nclass bias0_2(w: Int, addr_w: Int) extends BlackBox{\n val io = IO(new SinglePortROM(w, addr_w))\n}\n\nclass RAMGroupBundle(w: Int, addr_w: Int, id_w: Int) extends Bundle{\n val rd_valid_in = Input(Bool())\n val rd_valid_out = Output(Bool())\n val rd_addr1 = Input(new AddressReadGroup(addr_w, id_w))\n val rd_addr2 = Input(new AddressReadGroup(addr_w, id_w))\n val rd_big = Output(Vec(2, new BigBankReadData(w)))\n val rd_small = Output(Vec(2, Vec(4, new SmallBankReadData(w))))\n val wr_addr = Input(new AddressWriteGroup(addr_w, id_w))\n val wr_valid_in = Input(Bool())\n val to_bigbank = Input(new BigBankWriteData(w))\n val to_smallbank = Input(Vec(2, new SmallBankWriteData(w)))\n}\n\nclass RAMGroup(w: Int, addr_w: Int, id_w: Int) extends Module{\n val io = IO(new RAMGroupBundle(w, addr_w, id_w))\n\n val reg_valid = RegNext(RegNext(io.rd_valid_in, 0.U), 0.U)\n io.rd_valid_out := reg_valid\n io.rd_big := 0.U.asTypeOf(io.rd_big)\n io.rd_small := 0.U.asTypeOf(io.rd_small)\n\n\n\n val a_big_bank0 = Module(new big_bank0(StdPara.big_bank_w, StdPara.big_bank_addr_w))\n val a_big_bank1 = Module(new big_bank1(StdPara.big_bank_w, StdPara.big_bank_addr_w))\n\n a_big_bank0.io.clka := clock\n a_big_bank0.io.clkb := clock\n a_big_bank1.io.clka := clock\n a_big_bank1.io.clkb := clock\n\n\n\n val a_small_bank0 = Module(new small_bank0(StdPara.small_bank_w, StdPara.small_bank_addr_w))\n val a_small_bank1 = Module(new small_bank1(StdPara.small_bank_w, StdPara.small_bank_addr_w))\n val a_small_bank2 = Module(new small_bank2(StdPara.small_bank_w, StdPara.small_bank_addr_w))\n val a_small_bank3 = Module(new small_bank3(StdPara.small_bank_w, StdPara.small_bank_addr_w))\n val a_small_bank4 = Module(new small_bank4(StdPara.small_bank_w, StdPara.small_bank_addr_w))\n val a_small_bank5 = Module(new small_bank5(StdPara.small_bank_w, StdPara.small_bank_addr_w))\n val a_small_bank6 = Module(new small_bank6(StdPara.small_bank_w, StdPara.small_bank_addr_w))\n val a_small_bank7 = Module(new small_bank7(StdPara.small_bank_w, StdPara.small_bank_addr_w))\n\n a_small_bank0.io.clka := clock\n a_small_bank0.io.clkb := clock\n a_small_bank1.io.clka := clock\n a_small_bank1.io.clkb := clock\n a_small_bank2.io.clka := clock\n a_small_bank2.io.clkb := clock\n a_small_bank3.io.clka := clock\n a_small_bank3.io.clkb := clock\n a_small_bank4.io.clka := clock\n a_small_bank4.io.clkb := clock\n a_small_bank5.io.clka := clock\n a_small_bank5.io.clkb := clock\n a_small_bank6.io.clka := clock\n a_small_bank6.io.clkb := clock\n a_small_bank7.io.clka := clock\n a_small_bank7.io.clkb := clock\n\n\n val big_banks = Array.fill(2)(new TrueDualPortWire(StdPara.big_bank_w, StdPara.big_bank_addr_w))\n val small_banks = Array.fill(8)(new TrueDualPortWire(StdPara.small_bank_w, StdPara.small_bank_addr_w))\n\n big_banks(0) = TrueDualPortWire(a_big_bank0.io, StdPara.big_bank_w, StdPara.big_bank_addr_w)\n big_banks(1) = TrueDualPortWire(a_big_bank1.io, StdPara.big_bank_w, StdPara.big_bank_addr_w)\n\n small_banks(0) = TrueDualPortWire(a_small_bank0.io, StdPara.small_bank_w, StdPara.small_bank_addr_w)\n small_banks(1) = TrueDualPortWire(a_small_bank1.io, StdPara.small_bank_w, StdPara.small_bank_addr_w)\n small_banks(2) = TrueDualPortWire(a_small_bank2.io, StdPara.small_bank_w, StdPara.small_bank_addr_w)\n small_banks(3) = TrueDualPortWire(a_small_bank3.io, StdPara.small_bank_w, StdPara.small_bank_addr_w)\n small_banks(4) = TrueDualPortWire(a_small_bank4.io, StdPara.small_bank_w, StdPara.small_bank_addr_w)\n small_banks(5) = TrueDualPortWire(a_small_bank5.io, StdPara.small_bank_w, StdPara.small_bank_addr_w)\n small_banks(6) = TrueDualPortWire(a_small_bank6.io, StdPara.small_bank_w, StdPara.small_bank_addr_w)\n small_banks(7) = TrueDualPortWire(a_small_bank7.io, StdPara.small_bank_w, StdPara.small_bank_addr_w)\n\n big_banks(0).addra := io.rd_addr1.addrs(0).addr\n big_banks(1).addra := io.rd_addr2.addrs(0).addr\n\n io.rd_big(0) := RegNext(big_banks(0).douta.asTypeOf(new BigBankReadData(w)), 0.U.asTypeOf(new BigBankReadData(w)))\n io.rd_big(1) := RegNext(big_banks(1).douta.asTypeOf(new BigBankReadData(w)), 0.U.asTypeOf(new BigBankReadData(w)))\n\n // magic\n val typ = RegInit(VecInit(Seq.fill(2)(0.U(id_w.W))))\n typ(0) := io.rd_addr1.addrs(2).bank_id\n typ(1) := io.rd_addr2.addrs(2).bank_id\n\n val magic_mat = Array(Array(0, 2, 3, 1), Array(1, 3, 0, 2), Array(2, 0, 1, 3), Array(3, 1, 2, 0))\n def get_which(bank: Int, addr1: Int): Int = {\n for(i <- 0 to 3) if(addr1==magic_mat(1)(i)){\n for(j <- 0 to 3) if(bank==magic_mat(j)(i))\n return j+1\n }\n return -1\n }\n\n def get_which_res(rd: Int, addr1: Int): Int = {\n for(i <- 0 to 3) if(addr1==magic_mat(1)(i)){\n return magic_mat(rd)(i)\n }\n return -1\n }\n\n\n for(i <- 0 to 3){\n small_banks(i).addra := MuxCase(0.U.asTypeOf(small_banks(i).addra), Seq.tabulate(4){\n j => ((io.rd_addr1.addrs(2).bank_id(j)) -> io.rd_addr1.addrs(get_which(i, j)).addr)\n })\n small_banks(i+4).addra := MuxCase(0.U.asTypeOf(small_banks(i+4).addra), Seq.tabulate(4){\n j => ((io.rd_addr2.addrs(2).bank_id(j+4)) -> io.rd_addr2.addrs(get_which(i, j)).addr)\n }) \n }\n for(i <- 0 to 3){\n val x0 = Wire(new SmallBankReadData(w))\n val x1 = Wire(new SmallBankReadData(w))\n x0 := MuxCase(0.U.asTypeOf(new SmallBankReadData(w)), Seq.tabulate(4){\n j => ((typ(0)(j)) -> small_banks(get_which_res(i, j)).douta.asTypeOf(new SmallBankReadData(w)))\n })\n x1 := MuxCase(0.U.asTypeOf(new SmallBankReadData(w)), Seq.tabulate(4){\n j => ((typ(1)(j+4)) -> small_banks(get_which_res(i, j)+4).douta.asTypeOf(new SmallBankReadData(w)))\n })\n io.rd_small(0)(i) := RegNext(x0, 0.U.asTypeOf(new SmallBankReadData(w)))\n io.rd_small(1)(i) := RegNext(x1, 0.U.asTypeOf(new SmallBankReadData(w)))\n }\n\n\n big_banks(1).addrb := io.wr_addr.addrs(0).addr\n big_banks(1).dinb := io.to_bigbank.asUInt\n big_banks(0).addrb := io.wr_addr.addrs(0).addr\n big_banks(0).dinb := io.to_bigbank.asUInt\n when(io.wr_addr.addrs(0).bank_id(0)){\n big_banks(0).web := io.wr_valid_in\n }.otherwise{\n big_banks(1).web := io.wr_valid_in\n }\n for(i <- 0 to 3){\n small_banks(i*2).addrb := io.wr_addr.addrs(1).addr\n small_banks(i*2).dinb := io.to_smallbank(0).asUInt\n small_banks(i*2+1).addrb := io.wr_addr.addrs(2).addr\n small_banks(i*2+1).dinb := io.to_smallbank(1).asUInt\n when(io.wr_addr.addrs(1).bank_id(i*2)){\n small_banks(i*2).web := io.wr_valid_in\n small_banks(i*2+1).web := io.wr_valid_in\n } \n }\n \n}\n\nclass ROMBiasBundle(para_num: Int) extends Bundle{\n val addr = Input(UInt(StdPara.bias_addr_w.W))\n val out = Output(Vec(para_num, SInt(StdPara.bias_w.W)))\n}\n\nclass ROMBias(para_num: Int) extends Module{\n val io = IO(new ROMBiasBundle(para_num))\n val rom = Module(new bias0(para_num*StdPara.bias_w, StdPara.bias_addr_w)).io\n rom.clka := clock\n rom.addra := io.addr\n io.out := rom.douta.asTypeOf(Vec(para_num, SInt(StdPara.bias_w.W)))\n}\n\nclass ROMWeightBundle(para_num: Int) extends Bundle{\n val addr = Input(UInt(StdPara.weight_addr_w.W))\n val out = Output(Vec(para_num, Vec(9, SInt(16.W))))\n}\n\nclass ROMWeight(para_num: Int) extends Module{\n val io = IO(new ROMWeightBundle(para_num))\n val rom = Module(new weight0(para_num*StdPara.weight_w, StdPara.weight_addr_w)).io\n rom.clka := clock\n rom.addra := RegNext(io.addr, 0.U)\n io.out := rom.douta.asTypeOf(Vec(para_num, Vec(9, SInt(16.W))))\n}\n\n\nclass ROMHalfBias(para_num: Int) extends Module{\n val io = IO(new ROMBiasBundle(para_num))\n val rom = Module(new bias0_2(para_num*StdPara.bias_w, StdPara.bias_addr_w)).io\n rom.clka := clock\n rom.addra := io.addr\n io.out := rom.douta.asTypeOf(Vec(para_num, SInt(StdPara.bias_w.W)))\n\n}\n\nclass ROMHalfWeight(para_num: Int) extends Module{\n val io = IO(new ROMWeightBundle(para_num))\n val rom = Module(new weight0_2(para_num*StdPara.weight_w, StdPara.weight_addr_w)).io\n rom.clka := clock\n rom.addra := RegNext(io.addr, 0.U)\n io.out := rom.douta.asTypeOf(Vec(para_num, Vec(9, SInt(16.W))))\n}", "groundtruth": "class big_bank1(w: Int, addr_w: Int) extends BlackBox{\n val io = IO(new TrueDualPort(w, addr_w))\n}\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.9, "category_reason": "IO bundle definition"} {"task_id": "fpga_final_project", "path": "fpga_final_project/src/main/scala/calc8x8/accumu.scala", "left_context": "package final_project\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.util.HasBlackBoxInline\n\nclass AccumuRawData(val w: Int) extends Bundle{\n val mat = Vec(64, SInt((w*2+10).W))\n}\n\nclass AccumuBundle(w: Int, addr_w: Int, bias_w: Int, para_num: Int) extends Bundle{\n val in_from_calc8x8 = Input(Vec(para_num, new RawData(w)))\n val result = Output(Vec(para_num, new AccumuRawData(w)))\n val csum = Input(UInt(addr_w.W))\n val bias_begin_addr = Input(UInt(addr_w.W))\n val bias_end_addr = Input(UInt(addr_w.W))\n val bias_addr = Output(UInt(addr_w.W))\n val bias_in = Input(Vec(para_num, SInt(bias_w.W)))\n val is_in_use = Input(Bool())\n val valid_in = Input(UInt(para_num.W))\n val valid_out = Output(UInt(para_num.W))\n val flag_job = Input(Bool())\n}\n\n// for x.. for y.. for ic.. for oc..\n// get the sum of a 8x8 block\n\nclass Accumu(w: Int, addr_w: Int, bias_w: Int, para_num: Int) extends Module{\n val io = IO(new AccumuBundle(w, addr_w, bias_w, para_num))\n\n val counter = RegInit(0.U.asTypeOf(ACounter(addr_w)))\n val now_addr = RegInit(0.U.asTypeOf(RCounter(addr_w)))\n val enable = RegInit(false.B)\n val valid_out_reg = RegInit(0.U(para_num.W))\n\n io.result := 0.U.asTypeOf(Vec(para_num, new AccumuRawData(w)))\n io.valid_out := 0.U\n io.bias_addr := now_addr.ccnt\n\n val r64 = RegInit(0.U.asTypeOf(Vec(para_num, new AccumuRawData(w))))\n \n for(t <- 0 to para_num-1)\n for(i <- 0 to 63){\n val adder = Module(new DSP48Adder).io\n adder.a := io.in_from_calc8x8(t).mat(i)\n adder.b := r64(t).mat(i)\n adder.t := io.bias_in(t)\n adder.flag := counter.ccnt===counter.cend\n when(io.valid_in(0)){\n r64(t).mat(i) := adder.c\n }\n }\n io.result := r64\n when(io.flag_job){\n counter.set(io.csum, io.csum)\n now_addr.set(io.bias_begin_addr, io.bias_end_addr)\n r64 := 0.U.asTypeOf(r64)\n enable := io.is_in_use\n valid_out_reg := 0.U\n }.elsewhen(enable){\n when(io.valid_in(0)){\n", "right_context": " valid_out_reg := 0.U\n counter.ccnt := counter.ccnt-1.U\n }\n when(counter.ccnt===1.U){\n now_addr.inc()\n }\n }.otherwise{\n valid_out_reg := 0.U\n }\n io.valid_out := valid_out_reg\n }.otherwise{\n io.result(0) := io.in_from_calc8x8(0)\n io.valid_out := io.valid_in\n }\n\n}\n\nclass DSP48Adder extends BlackBox with HasBlackBoxInline{\n val io = IO(new Bundle{\n val a = Input(SInt(36.W))\n val t = Input(SInt(36.W))\n val flag = Input(Bool())\n val b = Input(SInt(42.W))\n val c = Output(SInt(42.W))\n })\n setInline(\n \"BlackBoxAdder3642.v\",\n \"\"\"(*use_dsp=\"yes\"*)\n |module DSP48Adder(\n | input[35:0] a,\n | input[35:0] t,\n | input flag,\n | input[41:0] b,\n | output[41:0] c\n |);\n |wire[41:0] x;\n |assign x = flag? {{6{t[35]}}, t}: b;\n |assign c = x + $signed({{6{a[35]}}, a});\n |endmodule\n \"\"\".stripMargin)\n}", "groundtruth": " when(counter.ccnt===counter.cend){\n valid_out_reg := 0.U\n counter.ccnt := counter.ccnt-1.U\n }.elsewhen(counter.ccnt===0.U){\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "fpga_final_project", "path": "fpga_final_project/src/main/scala/calc8x8/calc6x6.scala", "left_context": "package final_project\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.ChiselEnum\n\nclass FirstTransInput(val w: Int) extends Bundle{\n val mat_real = Vec(36, SInt(w.W))\n val mat_comp = Vec(12, SInt(w.W))\n}\n\nclass FinalTransInput(val w: Int) extends Bundle{\n val mat_real = Vec(36, SInt(w.W))\n val mat_comp = Vec(10, SInt(w.W))\n}\n\nclass TransOutput(val w: Int) extends Bundle{\n val mat_real = Vec(36, SInt(w.W))\n val mat_comp = Vec(36, SInt(w.W))\n}\n\nclass FirstTransOutput(val w: Int) extends Bundle{\n val mat_real = Vec(24, SInt(w.W))\n val mat_comp = Vec(24, SInt(w.W))\n}\n\nclass CalcWeightData extends Bundle{\n val real = Vec(16, SInt(16.W))\n}\n\nclass WeightData extends Bundle{\n val real = Vec(16, SInt(StdPara.dsp_w.W))\n val sbx = Vec(10, SInt(StdPara.dsp_w.W))\n val rbx = Vec(10, Bool())\n val bx = Vec(10, SInt(StdPara.dsp_w.W))\n val by = Vec(10, SInt(StdPara.dsp_w.W))\n}\n\nclass InputData(w: Int) extends Bundle {\n val mat = Vec(36, SInt(w.W))\n}\n\nclass OutputData(val w: Int) extends Bundle {\n val mat = Vec(16, SInt((w*2+6).W))\n}\n\n\nobject CalcType extends ChiselEnum {\n val empty = Value(0.U)\n val leakyReLU = Value(1.U)\n val calcMult = Value(2.U)\n val calcConv = Value(3.U)\n}\n\nclass Calc6x6(val w: Int, val para_num: Int) extends Module{\n val io = IO(new Bundle{\n val input = Input(new InputData(w))\n val flag = Input(CalcType())\n val weight = Input(Vec(para_num, new WeightData()))\n val output = Output(Vec(para_num, new OutputData(w)))\n val valid_in = Input(Bool())\n val valid_out = Output(Bool())\n })\n \n io.output := 0.U.asTypeOf(io.output)\n io.valid_out := false.B\n \n val real = Array.fill(para_num, 16)(Module(new Core()).io)\n \n for(t <- 0 to para_num-1)\n for(i <- 0 to 15){\n real(t)(i).w_a := 0.U.asTypeOf(real(t)(i).w_a)\n real(t)(i).in_b := 0.U.asTypeOf(real(t)(i).in_b)\n }\n\n val comp = Array.fill(para_num, 10)(Module(new ComplexCore()).io)\n \n for(t <- 0 to para_num-1)\n for(i <- 0 to 9){\n comp(t)(i).sbx := 0.S\n comp(t)(i).rbx := false.B\n comp(t)(i).bx := 0.S\n comp(t)(i).by := 0.S\n comp(t)(i).ax := 0.S\n comp(t)(i).ay := 0.S\n }\n \n \n val reg1 = RegInit(0.U.asTypeOf(new FirstTransInput(w+2)))\n val reg2 = RegInit(0.U.asTypeOf(new FinalTransInput(w+4)))\n val w3 = RegInit(VecInit(Seq.fill(para_num)(0.U.asTypeOf(new TransOutput(w+StdPara.dsp_w+4)))))\n val reg3 = RegInit(VecInit(Seq.fill(para_num)(0.U.asTypeOf(new FirstTransOutput(w+StdPara.dsp_w+5)))))\n \n \n def g6(x: Int, y: Int): Int = {\n return x*6+y\n }\n def g4(x: Int, y: Int): Int = {\n return x*4+y\n }\n\n \n def carry_save(A: SInt, B: SInt, C: SInt): SInt = {\n val _A = Wire(SInt((A.getWidth+1).W))\n val _B = Wire(SInt((A.getWidth+1).W))\n val _C = Wire(SInt((A.getWidth+1).W))\n _A := A\n _B := B\n _C := C\n val r_and = Wire(SInt((A.getWidth+1).W))\n val r_xor = Wire(SInt((A.getWidth+1).W))\n r_and := (_A&(_B|_C))|(_B&_C)\n r_xor := _A^_B^_C\n return (r_and<<1.U)+&r_xor\n }\n\n\n def first_trans_input(in: InputData): Unit = {\n for(i <- 0 to 5){\n\n \n val w2m4 = RegInit(0.S((in.mat(g6(2, i)).getWidth+1).W))\n val w2a4 = RegInit(0.S((in.mat(g6(2, i)).getWidth+1).W))\n val w1a3 = RegInit(0.S((in.mat(g6(1, i)).getWidth+1).W))\n\n w2m4 := in.mat(g6(4, i))-&in.mat(g6(2, i))\n w2a4 := in.mat(g6(2, i))+&in.mat(g6(4, i))\n\n w1a3 := in.mat(g6(1, i))+&in.mat(g6(3, i))\n\n reg1.mat_real(g6(0, i)) := RegNext(in.mat(g6(0, i))-&in.mat(g6(4, i)), 0.S)\n reg1.mat_real(g6(1, i)) := w1a3+&w2a4\n reg1.mat_real(g6(2, i)) := w2a4-&w1a3\n reg1.mat_real(g6(3, i)) := w2m4\n reg1.mat_real(g6(4, i)) := w2m4\n reg1.mat_real(g6(5, i)) := RegNext(in.mat(g6(5, i))-&in.mat(g6(1, i)), 0.S)\n\n val w1m3 = RegInit(0.S((in.mat(g6(1, i)).getWidth+1).W))\n w1m3 := in.mat(g6(1, i))-&in.mat(g6(3, i))\n\n\n reg1.mat_comp(g6(0, i)) := -w1m3 // g(3, i, 6)\n reg1.mat_comp(g6(1, i)) := w1m3 // g(4, i, 6)\n }\n }\n\n\n def final_trans_input(in: FirstTransInput): Unit = {\n for(i <- 0 to 5){\n\n val w13 = RegInit(0.S((in.mat_real(g6(i, 1)).getWidth+1).W))\n val w24 = RegInit(0.S((in.mat_real(g6(i, 2)).getWidth+1).W))\n val w2m4 = RegInit(0.S((in.mat_real(g6(i, 2)).getWidth+1).W))\n\n w13 := in.mat_real(g6(i, 1))+&in.mat_real(g6(i, 3))\n w24 := in.mat_real(g6(i, 2))+&in.mat_real(g6(i, 4))\n w2m4 := in.mat_real(g6(i, 4))-&in.mat_real(g6(i, 2))\n if(i>=3&&i<=4){\n val c13 = RegInit(0.S((in.mat_comp(g6(1, 3)).getWidth+1).W))\n if(i==3){\n c13 := in.mat_comp(g6(1, 1))-&in.mat_comp(g6(1, 3))\n } else {\n c13 := in.mat_comp(g6(1, 3))-&in.mat_comp(g6(1, 1))\n }\n \n reg2.mat_real(g6(i, 3)) := w2m4-&c13\n reg2.mat_real(g6(i, 4)) := w2m4+&c13\n } else {\n reg2.mat_real(g6(i, 3)) := w2m4\n reg2.mat_real(g6(i, 4)) := w2m4\n }\n \n\n reg2.mat_real(g6(i, 0)) := RegNext(in.mat_real(g6(i, 0))-&in.mat_real(g6(i, 4)), 0.S)\n reg2.mat_real(g6(i, 1)) := w13+&w24\n reg2.mat_real(g6(i, 2)) := w24-&w13\n reg2.mat_real(g6(i, 5)) := RegNext(in.mat_real(g6(i, 5))-&in.mat_real(g6(i, 1)), 0.S)\n }\n val w13 = RegInit(0.S((in.mat_real(g6(0, 1)).getWidth+1).W))\n val w33 = RegInit(0.S((in.mat_real(g6(0, 1)).getWidth+1).W))\n val w24 = RegInit(0.S((in.mat_real(g6(0, 2)).getWidth+1).W))\n val w2m4 = RegInit(0.S((in.mat_real(g6(0, 2)).getWidth+1).W))\n\n w13 := in.mat_comp(g6(0, 1))+&in.mat_comp(g6(0, 3))\n w24 := in.mat_comp(g6(0, 2))+&in.mat_comp(g6(0, 4))\n w2m4 := in.mat_comp(g6(0, 4))-&in.mat_comp(g6(0, 2))\n w33 := in.mat_real(g6(3, 1))-&in.mat_real(g6(3, 3))\n\n //(3, 0...5)\n reg2.mat_comp(0) := RegNext(in.mat_comp(g6(0, 0))-&in.mat_comp(g6(0, 4)), 0.S)\n reg2.mat_comp(1) := w13+&w24\n reg2.mat_comp(2) := w24-&w13\n reg2.mat_comp(3) := w2m4-&w33\n reg2.mat_comp(4) := w2m4+&w33\n reg2.mat_comp(5) := RegNext(in.mat_comp(g6(0, 5))-&in.mat_comp(g6(0, 1)), 0.S)\n\n // (0, 3) (1, 3) (2, 3) (5, 3)\n reg2.mat_comp(6) := RegNext(in.mat_real(g6(0, 3))-&in.mat_real(g6(0, 1)), 0.S)\n reg2.mat_comp(7) := RegNext(in.mat_real(g6(1, 3))-&in.mat_real(g6(1, 1)), 0.S)\n reg2.mat_comp(8) := RegNext(in.mat_real(g6(2, 3))-&in.mat_real(g6(2, 1)), 0.S)\n reg2.mat_comp(9) := RegNext(in.mat_real(g6(5, 3))-&in.mat_real(g6(5, 1)), 0.S)\n }\n\n def first_trans_output(out: FirstTransOutput, in: TransOutput): Unit = {\n for(i <- 0 to 5)if(i!=4){\n \n val w1a2 = RegInit(0.S((in.mat_real(g6(1, i)).getWidth+1).W))\n val w1m2 = RegInit(0.S((in.mat_real(g6(1, i)).getWidth+1).W))\n\n\n w1a2 := in.mat_real(g6(1, i))+&in.mat_real(g6(2, i))\n w1m2 := in.mat_real(g6(1, i))-&in.mat_real(g6(2, i))\n\n\n val r34 = RegInit(0.S((in.mat_real(g6(3, i)).getWidth+1).W))\n val c34 = RegInit(0.S((in.mat_comp(g6(3, i)).getWidth+1).W))\n \n if(i==3){\n r34 := in.mat_real(g6(3, 3))+&in.mat_real(g6(3, 4))\n c34 := in.mat_comp(g6(3, 3))+&in.mat_comp(g6(3, 4)) \n } else {\n r34 := in.mat_real(g6(3, i))<<1.U\n c34 := in.mat_comp(g6(3, i))<<1.U\n }\n val r_mat_0_i = RegInit(0.S((in.mat_real(g6(0, i)).getWidth+2).W))\n val r_mat_5_i = RegInit(0.S((in.mat_comp(g6(5, i)).getWidth+2).W))\n \n r_mat_0_i := in.mat_real(g6(0, i))<<(2.U)\n r_mat_5_i := in.mat_real(g6(5, i))<<(2.U)\n\n out.mat_real(g6(0, i)) := carry_save(w1a2, r34, r_mat_0_i)>>2.U\n out.mat_real(g6(1, i)) := (w1m2-&c34)>>2.U\n out.mat_real(g6(2, i)) := (w1a2-&r34)>>2.U\n out.mat_real(g6(3, i)) := carry_save(w1m2, c34, r_mat_5_i)>>2.U\n \n }\n\n val _w1a2 = RegInit(0.S((in.mat_real(g6(1, 3)).getWidth+1).W))\n val _w1m2 = RegInit(0.S((in.mat_real(g6(1, 3)).getWidth+1).W))\n\n\n _w1a2 := in.mat_comp(g6(1, 3))+&in.mat_comp(g6(2, 3))\n _w1m2 := in.mat_comp(g6(1, 3))-&in.mat_comp(g6(2, 3))\n\n val _r34 = RegInit(0.S((in.mat_real(g6(3, 3)).getWidth+1).W))\n val _c34 = RegInit(0.S((in.mat_comp(g6(3, 3)).getWidth+1).W))\n\n _r34 := in.mat_real(g6(3, 4))-&in.mat_real(g6(3, 3))\n _c34 := in.mat_comp(g6(3, 3))-&in.mat_comp(g6(3, 4))\n \n val c_mat_0_3 = RegInit(0.S((in.mat_real(g6(0, 3)).getWidth+2).W))\n val c_mat_5_3 = RegInit(0.S((in.mat_comp(g6(5, 3)).getWidth+2).W))\n\n c_mat_0_3 := in.mat_comp(g6(0, 3))<<(2.U)\n c_mat_5_3 := in.mat_comp(g6(5, 3))<<(2.U)\n\n out.mat_comp(g6(0, 3)) := carry_save(_w1a2, _c34, c_mat_0_3)>>2.U\n out.mat_comp(g6(1, 3)) := (_w1m2-&_r34)>>2.U\n out.mat_comp(g6(2, 3)) := (_w1a2-&_c34)>>2.U\n out.mat_comp(g6(3, 3)) := carry_save(_w1m2, _r34, c_mat_5_3)>>2.U\n \n }\n\n def final_trans_output(output: OutputData, in: FirstTransOutput): Unit = {\n for(i <- 0 to 3){\n val w1a2 = RegInit(0.S((in.mat_real(g6(i, 1)).getWidth).W))\n val w1m2 = RegInit(0.S((in.mat_real(g6(i, 1)).getWidth).W))\n\n w1a2 := (in.mat_real(g6(i, 1))+&in.mat_real(g6(i, 2)))>>1.U\n w1m2 := (in.mat_real(g6(i, 1))-&in.mat_real(g6(i, 2)))>>1.U\n\n val r34 = RegInit(0.S((in.mat_real(g6(i, 3)).getWidth).W))\n val c34 = RegInit(0.S((in.mat_comp(g6(i, 3)).getWidth).W))\n\n r34 := in.mat_real(g6(i, 3))\n c34 := in.mat_comp(g6(i, 3))\n \n val r_mat_0_i = RegInit(0.S((in.mat_real(g6(i, 0)).getWidth+1).W))\n val r_mat_5_i = RegInit(0.S((in.mat_real(g6(i, 5)).getWidth+1).W))\n\n r_mat_0_i := in.mat_real(g6(i, 0))<<(1.U)\n r_mat_5_i := in.mat_real(g6(i, 5))<<(1.U)\n\n output.mat(g4(i, 0)) := RegNext(carry_save(w1a2, r34, r_mat_0_i)>>1.U, 0.S)\n output.mat(g4(i, 1)) := RegNext(((w1m2-&c34)>>1.U), 0.S)\n output.mat(g4(i, 2)) := RegNext(((w1a2-&r34)>>1.U), 0.S)\n output.mat(g4(i, 3)) := RegNext(carry_save(w1m2, c34, r_mat_5_i)>>1.U, 0.S)\n }\n }\n\n val valid_reg = RegInit(VecInit(Seq.fill(13)(false.B)))\n \n // first_trans_input(io.input)\n first_trans_input(RegNext(RegNext(io.input, 0.U.asTypeOf(io.input)), 0.U.asTypeOf(io.input)))\n final_trans_input(reg1)\n for(t <- 0 to para_num-1)\n first_trans_output(reg3(t), w3(t))\n valid_reg(1) := valid_reg(0)\n valid_reg(2) := valid_reg(1)\n valid_reg(3) := valid_reg(2)\n valid_reg(4) := valid_reg(3)\n valid_reg(5) := valid_reg(4)\n valid_reg(6) := valid_reg(5)\n valid_reg(7) := valid_reg(6)\n valid_reg(8) := valid_reg(7)\n valid_reg(9) := valid_reg(8)\n valid_reg(10) := valid_reg(9)\n valid_reg(11) := valid_reg(10)\n valid_reg(12) := valid_reg(11)\n \n for(t <- 0 to para_num-1){\n var y = 0\n for(i <- 0 to 5){\n for(j <- 0 to 5){\n if(i==3){\n comp(t)(y).sbx := io.weight(t).sbx(y)\n comp(t)(y).rbx := io.weight(t).rbx(y)\n comp(t)(y).bx := io.weight(t).bx(y)\n comp(t)(y).by := io.weight(t).by(y)\n comp(t)(y).ax := reg2.mat_real(g6(i, j))\n comp(t)(y).ay := reg2.mat_comp(j)\n\n w3(t).mat_real(g6(i, j)) := comp(t)(y).x\n w3(t).mat_comp(g6(i, j)) := comp(t)(y).y\n \n y = y+1\n } else if(i!=4&&j==3){\n", "right_context": " comp(t)(y).sbx := io.weight(t).sbx(y)\n comp(t)(y).rbx := io.weight(t).rbx(y)\n comp(t)(y).bx := io.weight(t).bx(y)\n comp(t)(y).by := io.weight(t).by(y)\n comp(t)(y).ax := reg2.mat_real(g6(i, j))\n comp(t)(y).ay := reg2.mat_comp(real_i)\n\n w3(t).mat_real(g6(i, j)) := comp(t)(y).x\n w3(t).mat_comp(g6(i, j)) := comp(t)(y).y\n\n y = y+1\n }\n }\n }\n }\n switch(io.flag){\n is(CalcType.leakyReLU){\n for(i <- 0 to 15){\n real(0)(i).w_a := Mux(io.input.mat((i/4)*6+(i%4))(w-1), 6554.S, 32768.S)\n real(0)(i).in_b := io.input.mat((i/4)*6+(i%4))\n io.output(0).mat(i) := real(0)(i).result\n }\n io.valid_out := RegNext(RegNext(io.valid_in, false.B), false.B)\n }\n\n is(CalcType.calcMult){\n for(i <- 0 to 15){\n real(0)(i).in_b := io.input.mat((i/4)*6+(i%4))\n real(0)(i).w_a := io.weight(0).real(i)\n io.output(0).mat(i) := real(0)(i).result\n }\n \n io.valid_out := RegNext(RegNext(io.valid_in, false.B), false.B)\n }\n \n is(CalcType.calcConv){\n valid_reg(0) := io.valid_in\n for(t <- 0 to para_num-1)\n final_trans_output(io.output(t), reg3(t))\n\t\t\t\n \n for(t <- 0 to para_num-1){\n var x = 0\n var y = 0\n for(i <- 0 to 5){\n for(j <- 0 to 5){\n if(i!=3&&i!=4&&j!=3&&j!=4){\n real(t)(x).in_b := reg2.mat_real(g6(i, j))\n real(t)(x).w_a := io.weight(t).real(x)\n w3(t).mat_real(g6(i, j)) := real(t)(x).result\n x = x+1\n }\n }\n }\n }\n io.valid_out := valid_reg(12)\n // io.valid_out := valid_reg(10)\n \n }\n }\n}\n", "groundtruth": " val real_i = if(i>=5) 9 else i+6\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.6, "category_reason": "val binding"} {"task_id": "fpga_final_project", "path": "fpga_final_project/src/main/scala/calc8x8/calc8x8.scala", "left_context": "package final_project\n\nimport chisel3._\nimport chisel3.util._\n\n\nclass PackedData(val w: Int) extends Bundle {\n val mat = Vec(64, SInt(w.W))\n val up = Vec(10, SInt(w.W))\n val down = Vec(10, SInt(w.W))\n val left = Vec(8, SInt(w.W))\n val right = Vec(8, SInt(w.W))\n}\n\nclass RawData(val w: Int) extends Bundle {\n val mat = Vec(64, SInt((w*2+4).W))\n}\n\nclass Calc8x8(val w: Int, val para_num: Int) extends Module{\n val io = IO(new Bundle{\n val input = Input(new PackedData(w))\n val flag = Input(CalcType())\n val mask = Input(UInt(para_num.W))\n val weight = Input(Vec(para_num, new CalcWeightData()))\n val multmap = Input(Vec(4, new CalcWeightData()))\n val output = Output(Vec(para_num, new RawData(w)))\n val valid_in = Input(Bool())\n val valid_out = Output(UInt(para_num.W))\n })\n def get_one(a: PackedData, x: Int, y: Int): Data = {\n if(x==0) return a.up(y)\n if(x==9) return a.down(y)\n if(y==0) return a.left(x-1)\n if(y==9) return a.right(x-1)\n return a.mat((x-1)*8+(y-1))\n }\n def get_area(a: PackedData, lx: Int, ly: Int, rx: Int, ry: Int): Data = {\n val ret = Wire(new InputData(w))\n for(i <- 0 to 5)\n for(j <- 0 to 5)\n ret.mat(i*6+j) := (if(i=r, r, Mux(x<=l, l, x))\n //return Mux((~x(18))&&x(17), ((1<<17)-1).S(18.W), Mux(x(18)&&(~x(17)), (-(1<<17)).S(18.W), x))\n }\n\n for(t <- 0 to para_num-1){\n var x = 0\n var y = 0\n for(i <- 0 to 5){\n for(j <- 0 to 5){\n if(i!=3&&i!=4&&j!=3&&j!=4){\n conv_weight(t).real(x) := RegNext(clamp_18(__B(t)(i)(j)), 0.S(StdPara.dsp_w.W))\n // conv_weight(t).real(x) := clamp_18(__B(t)(i)(j))\n x = x+1\n } else if(i==3||(i!=4&&j==3)){\n val __Bx = RegInit(0.S(StdPara.dsp_w.W))\n val __Bix = RegInit(0.S(StdPara.dsp_w.W))\n // val __Bx = Wire(SInt(StdPara.dsp_w.W))\n // val __Bix = Wire(SInt(StdPara.dsp_w.W))\n __Bx := clamp_18(__B(t)(i)(j))\n __Bix := clamp_18(__Bi(t)(i)(j))\n conv_weight(t).sbx(y) := ((__Bx+&__Bix)>>1.U)\n conv_weight(t).rbx(y) := __Bx(0)^__Bix(0)\n conv_weight(t).bx(y) := __Bx\n conv_weight(t).by(y) := __Bix\n y = y+1\n }\n }\n }\n }\n \n\n\n switch(io.flag){\n is(CalcType.leakyReLU){\n A(0).input := get_area(io.input, 1, 1, 4, 4)\n A(1).input := get_area(io.input, 1, 5, 4, 8)\n A(2).input := get_area(io.input, 5, 1, 8, 4)\n A(3).input := get_area(io.input, 5, 5, 8, 8)\n for(i <- 0 to 3){\n A(i).flag := CalcType.leakyReLU\n A(i).valid_in := io.valid_in\n }\n io.output(0) := set_output(A(0).output(0), A(1).output(0), A(2).output(0), A(3).output(0))\n io.valid_out := (if(para_num==1) A(0).valid_out else Cat(0.U((para_num-1).W), A(0).valid_out))\n }\n is(CalcType.calcMult){\n A(0).input := get_area(io.input, 1, 1, 4, 4)\n A(1).input := get_area(io.input, 1, 5, 4, 8)\n A(2).input := get_area(io.input, 5, 1, 8, 4)\n A(3).input := get_area(io.input, 5, 5, 8, 8)\n for(i <- 0 to 3){\n A(i).weight(0).real := io.multmap(i).real\n A(i).flag := CalcType.calcMult\n A(i).valid_in := io.valid_in\n }\n io.output(0) := set_output(A(0).output(0), A(1).output(0), A(2).output(0), A(3).output(0))\n", "right_context": " }\n is(CalcType.calcConv){\n A(0).input := get_area(io.input, 0, 0, 5, 5)\n A(1).input := get_area(io.input, 0, 4, 5, 9)\n A(2).input := get_area(io.input, 4, 0, 9, 5)\n A(3).input := get_area(io.input, 4, 4, 9, 9)\n for(i <- 0 to 3){\n A(i).weight := conv_weight\n A(i).flag := CalcType.calcConv\n A(i).valid_in := io.valid_in\n }\n for(t <- 0 to para_num-1)\n io.output(t) := set_output(A(0).output(t), A(1).output(t), A(2).output(t), A(3).output(t))\n io.valid_out := Cat(Seq.tabulate(para_num){\n i => A(0).valid_out&io.mask(para_num-1-i)\n }) \n }\n \n is(CalcType.empty){\n io.valid_out := io.valid_in\n for(i <- 0 to 63)\n io.output(0).mat(i) := io.input.mat(i)\n }\n }\n}\n", "groundtruth": " io.valid_out := (if(para_num==1) A(0).valid_out else Cat(0.U((para_num-1).W), A(0).valid_out))\n", "crossfile_context": "", "category": "Computation Block", "subcategory": "Type Casting and Conversion", "confidence": 0.75, "category_reason": "Cat/Fill operation"} {"task_id": "fpga_final_project", "path": "fpga_final_project/src/main/scala/calc8x8/core.scala", "left_context": "package final_project\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.ChiselEnum\n\nclass Core extends Module{\n val io = IO(new Bundle{\n val w_a = Input(SInt(StdPara.dsp_w.W))\n val in_b = Input(SInt(20.W))\n", "right_context": "}\n\n\nclass DSP48 extends Module{\n val io = IO(new Bundle{\n val in_a = Input(SInt(StdPara.dsp_w.W))\n val in_b = Input(SInt(20.W))\n val out = Output(SInt(40.W))\n })\n /*\n val M = Module(new ip_dsp48).io\n M.A := io.in_b\n M.B := io.in_a\n io.out := M.P*/\n io.out := io.in_a*io.in_b\n}\n\n\nclass ComplexCore extends Module{\n val io = IO(new Bundle{\n val sbx = Input(SInt(StdPara.dsp_w.W))\n val rbx = Input(Bool())\n val bx = Input(SInt(StdPara.dsp_w.W))\n val by = Input(SInt(StdPara.dsp_w.W))\n val ax = Input(SInt(20.W))\n val ay = Input(SInt(20.W))\n val x = Output(SInt(40.W))\n val y = Output(SInt(40.W))\n })\n val _ax = RegNext(io.ax, 0.S(20.W))\n val _ay = RegNext(io.ay, 0.S(20.W))\n val _bx = RegNext(io.bx, 0.S(StdPara.dsp_w.W))\n val _by = RegNext(io.by, 0.S(StdPara.dsp_w.W))\n val w = RegNext((io.ay<<(1.U))*io.sbx+&Mux(io.rbx, io.ay, 0.S), 0.S)\n io.x := RegNext((_ax+&_ay)*_bx-&w, 0.S)\n io.y := RegNext((_ax-&_ay)*_by+&w, 0.S)\n}", "groundtruth": " val result = Output(SInt(40.W))\n })\n \n val dsp48 = Module(new DSP48())\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.8, "category_reason": "Input or Output in Bundle/IO context"} {"task_id": "fpga_final_project", "path": "fpga_final_project/src/main/scala/calc8x8/quant.scala", "left_context": "package final_project\n\nimport chisel3._\nimport chisel3.util._\n\nclass QuantedData(val w: Int) extends Bundle{\n val mat = Vec(64, SInt(w.W))\n}\n\nclass QuantBundle(val w: Int) extends TransBundle{\n val in_from_accumu = Input(new AccumuRawData(w))\n val result = Output(new QuantedData(w))\n val quant_in = Input(UInt(5.W))\n}\n\nclass Quant(val w: Int) extends Module{\n val io = IO(new QuantBundle(w))\n\n\n val r_q = RegInit(0.U(5.W))\n\n io.valid_out := false.B\n io.result := 0.U.asTypeOf(new QuantedData(w))\n\n", "right_context": " return Mux(ret1<=ret3, ret3, Mux(ret1>=ret2, ret2, ret1))\n }\n\n val mat = RegInit(0.U.asTypeOf(new AccumuRawData(w)))\n mat := io.in_from_accumu\n for(i <- 0 to 63)\n io.result.mat(i) := clamp_rs(mat.mat(i), r_q)\n \n when(io.flag_job){\n r_q := io.quant_in\n }.otherwise{\n io.valid_out := RegNext(io.valid_in, false.B)\n }\n\n}", "groundtruth": " def clamp_rs(x: SInt, a: UInt): Data = {\n val ret2 = ((1<<(w-1))-1).S(32.W)\n val ret3 = (-(1<<(w-1))).S(32.W)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "fpga_final_project", "path": "fpga_final_project/src/main/scala/control/switch.scala", "left_context": "package final_project\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.ChiselEnum\n\nobject ReadSwitchType extends ChiselEnum{\n val idle = Value(0.U)\n val toConv = Value(1.U)\n val toMult2 = Value(2.U)\n val toMaxp = Value(3.U)\n val toCopy = Value(4.U)\n val toUps = Value(5.U)\n}\n\nclass ReadSwitchBundle(val w: Int, val h_w: Int, val c_w: Int, val para_num: Int) extends Bundle{\n val flag_job = Input(Bool())\n val job = Input(ReadSwitchType())\n val in_h = Input(UInt(h_w.W))\n val in_chan = Input(UInt(c_w.W))\n val valid_in = Input(Bool())\n val valid_out_calc8x8 = Output(Bool())\n val valid_out_copy = Output(Bool())\n val valid_out_maxp = Output(Bool())\n val from = Input(new PackedData(w))\n val from_weight = Input(Vec(para_num, Vec(9, SInt(16.W))))\n val to_calc8x8 = Output(new PackedData(w))\n val to_copy = Output(new QuantedData(w))\n val to_weight = Output(Vec(para_num, new CalcWeightData()))\n val to_multmap = Output(Vec(4, new CalcWeightData()))\n\n val valid_in_from_user = Input(Bool())\n val data_from_user = Input(new QuantedData(w))\n}\n\nclass ReadSwitch(val w: Int, val h_w: Int, val c_w: Int, val para_num: Int) extends Module{\n val io = IO(new ReadSwitchBundle(w, h_w, c_w, para_num))\n val job_type = RegInit(0.U.asTypeOf(ReadSwitchType()))\n\n", "right_context": " val state = RegInit(false.B)\n\n val cnt_h = RegInit(0.U.asTypeOf(ACounter(h_w.W)))\n val cnt_ic = RegInit(0.U.asTypeOf(ACounter(c_w.W)))\n val ups_state = RegInit(false.B)\n\n io.valid_out_calc8x8 := false.B\n io.valid_out_copy := false.B\n io.valid_out_maxp := false.B\n io.to_calc8x8 := 0.U.asTypeOf(io.to_calc8x8)\n io.to_weight := 0.U.asTypeOf(io.to_weight)\n io.to_copy := 0.U.asTypeOf(io.to_copy)\n io.to_multmap := 0.U.asTypeOf(io.to_multmap)\n \n io.to_calc8x8 := io.from\n cache := io.from.mat \n for(ii <- 0 to 1)\n for(jj <- 0 to 1)\n for(i <- 0 to 3)\n for(j <- 0 to 3)\n io.to_multmap(ii*2+jj).real(i*4+j) := cache((i+ii*4)*8+(j+jj*4))\n \n for(t <- 0 to para_num-1)\n for(i <- 0 to 8)\n io.to_weight(t).real(i) := io.from_weight(t)(i) \n when(io.flag_job){\n job_type := io.job\n ups_state := false.B\n cnt_h.set(io.in_h)\n cnt_ic.set(io.in_chan)\n state := false.B\n }.otherwise{\n switch(job_type){\n is(ReadSwitchType.toConv){\n io.valid_out_calc8x8 := io.valid_in\n }\n is(ReadSwitchType.toCopy){\n io.valid_out_copy := io.valid_in\n io.to_copy.mat := io.from.mat\n }\n is(ReadSwitchType.toMult2){\n when(io.valid_in){\n when(state){ \n io.valid_out_calc8x8 := true.B\n }\n state := ~state \n }\n }\n is(ReadSwitchType.toMaxp){\n io.valid_out_maxp := io.valid_in\n }\n is(ReadSwitchType.idle){\n io.valid_out_copy := io.valid_in_from_user\n io.to_copy := io.data_from_user\n }\n is(ReadSwitchType.toUps){\n when(io.valid_in){\n io.valid_out_copy := true.B\n when(cnt_ic.inc()){\n state := ~state\n when(cnt_h.inc()){\n ups_state := ~ups_state\n }\n } \n }\n \n when(ups_state){\n when(state){\n for(i <- 0 to 7)\n for(j <- 0 to 7)\n io.to_copy.mat(i*8+j) := io.from.mat((i/2+4)*8+(j/2+4))\n }.otherwise{\n for(i <- 0 to 7)\n for(j <- 0 to 7)\n io.to_copy.mat(i*8+j) := io.from.mat((i/2)*8+(j/2+4))\n }\n }.otherwise{\n when(state){\n for(i <- 0 to 7)\n for(j <- 0 to 7)\n io.to_copy.mat(i*8+j) := io.from.mat((i/2+4)*8+(j/2))\n }.otherwise{\n for(i <- 0 to 7)\n for(j <- 0 to 7)\n io.to_copy.mat(i*8+j) := io.from.mat((i/2)*8+(j/2))\n }\n }\n }\n }\n }\n}\n\nclass WriteSwitch(val w: Int, val num: Int) extends Module{\n val io = IO(new Bundle{\n val valid_in = Input(Vec(num, new Bool()))\n val valid_out = Output(Bool())\n val input = Input(Vec(num, new QuantedData(w)))\n val output = Output(new QuantedData(w))\n })\n io.output := MuxCase(0.U.asTypeOf(io.output), Seq.tabulate(num){\n i => (io.valid_in(i) -> io.input(i))\n })\n io.valid_out := io.valid_in.reduce(_ | _)\n}", "groundtruth": " val cache = RegInit(VecInit(Seq.fill(64){0.S(w.W)}))\n", "crossfile_context": "", "category": "Storage Block", "subcategory": "Register-based Storage", "confidence": 0.85, "category_reason": "RegInit register"} {"task_id": "fpga_final_project", "path": "fpga_final_project/src/main/scala/some/maxpool.scala", "left_context": "package final_project\n\nimport chisel3._\nimport chisel3.util._\n\nclass Maxpool(val w: Int) extends Module{\n val io = IO(new Bundle{\n val from_big = Input(Vec(2, new BigBankReadData(w)))\n val from_small = Input(Vec(2, Vec(2, new SmallBankReadData(w))))\n val valid_in = Input(Bool())\n val valid_out = Output(Bool())\n val result = Output(new QuantedData(w))\n })\n val state = RegInit(0.U(1.W))\n val output = RegInit(VecInit(Seq.fill(32)(0.S(w.W))))\n val cache = Wire(Vec(32, SInt(w.W)))\n\n cache := 0.U.asTypeOf(cache)\n \n io.valid_out := false.B\n io.result := 0.U.asTypeOf(io.result)\n \n for(t <- 0 to 1){\n for(ii <- 0 to 3){\n for(jj <- 0 to 3){\n val w4 = Wire(Vec(4, SInt(w.W)))\n val a2 = Wire(SInt(w.W))\n val b2 = Wire(SInt(w.W))\n for(i <- 0 to 1){\n for(j <- 0 to 1){\n val x = ii*2+i\n val y = jj*2+j\n if(y==0){\n w4(i*2+j) := io.from_small(t)(0).data(x)\n } else if(y==7){\n w4(i*2+j) := io.from_small(t)(1).data(x)\n } else {\n w4(i*2+j) := io.from_big(t).data(x*6+y-1)\n }\n }\n }\n a2 := Mux(w4(0)>quant.U\n state(i+1) := input_reg(i)=ret2, ret2, x).asUInt\n }\n\n ans_reg := clamp(ans(len)) >> last_quant.U\n}", "groundtruth": " 1058213120,\n 1069382976,\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "fpga_final_project", "path": "fpga_final_project/src/main/scala/top/emit.scala", "left_context": "package final_project\n\nimport chisel3._\nimport chisel3.util._\n\nimport chisel3.experimental.BundleLiterals._\n\nimport chisel3.stage.ChiselStage\n\n// test\n\nclass Fuck extends Module{\n val io = IO(new Bundle{\n val sbx = Input(SInt(18.W))\n val rbx = Input(SInt(40.W))\n val bx = Input(SInt(18.W))\n val by = Input(SInt(18.W))\n val ax = Input(SInt(20.W))\n val ay = Input(SInt(20.W))\n val x = Output(SInt(40.W))\n val y = Output(SInt(40.W))\n })\n val _ax = RegNext(io.ax, 0.S(18.W))\n val _ay = RegNext(io.ay, 0.S(18.W))\n val _bx = RegNext(io.bx, 0.S(18.W))\n val _by = RegNext(io.by, 0.S(18.W))\n val w = RegInit(0.S(40.W))\n w := (io.ay<<(1.U))*io.sbx+&io.rbx\n io.x := (_ax+&_ay)*_bx-&w\n io.y := (_ax-&_ay)*_by+&w\n}\n/*\nclass FuckAdd extends Module{\n val io = IO(new Bundle{\n val t = Input(SInt(48.W))\n val tx = Input(SInt(48.W))\n val tg = Input(Bool())\n val hi_y = Input(SInt(24.W))\n val lo_y = Input(SInt(24.W))\n val hi_out = Output(SInt(24.W))\n val lo_out = Output(SInt(24.W))\n })\n val state = RegInit(0.U(1.W))\n val hi_and = RegInit(0.S(24.W))\n val lo_and = RegInit(0.S(24.W))\n val hi_xor = RegInit(0.S(24.W))\n val lo_xor = RegInit(0.S(24.W))\n val lst_hi = RegInit(VecInit(Seq.fill(2)(0.S(24.W))))\n val lst_lo = RegInit(VecInit(Seq.fill(2)(0.S(24.W))))\n when(tg){\n lo_and := t(23, 0)&tx(23, 0)\n lo_xor := t(23, 0)^tx(23, 0)\n hi_xor := t(47, 24)^tx(47, 24)\n hi_and := t(47, 24)&tx(47, 24)\n lst_hi(0) := t(23, 0)\n lst_lo(0) := t(47, 24)\n lst_hi(1) := tx(23, 0)\n lst_lo(1) := tx(47, 24)\n state := 0.U\n }.otherwise{\n hi_and := \n }\n \n}\n*/\nclass Accumu2(w: Int, addr_w: Int, bias_w: Int, para_num: Int) extends Module{\n val io = IO(new AccumuBundle(w, addr_w, bias_w, para_num))\n\n io.result := 0.U.asTypeOf(Vec(para_num, new AccumuRawData(w)))\n io.bias_addr := 0.U\n io.valid_out := io.valid_in\n", "right_context": " }\n io.result := r64\n}\nobject FafaDriver extends App {\n (new ChiselStage).emitVerilog(\n new Top,\n //new ROMBias,\n //new RAMGroup(StdPara.w, StdPara.addr_w, StdPara.id_w), \n Array(\"--target-dir\", \"C:\\\\Users\\\\yfz\\\\Desktop\\\\data\\\\Plan\\\\homework\\\\AI_fpga\\\\final_project\\\\project_1\\\\\")\n )\n}\n\nobject ShowDriver extends App {\n (new ChiselStage).emitVerilog(\n new Show,\n //new ROMBias,\n //new RAMGroup(StdPara.w, StdPara.addr_w, StdPara.id_w), \n Array(\"--target-dir\", \"C:\\\\Users\\\\yfz\\\\Desktop\\\\data\\\\Plan\\\\homework\\\\AI_fpga\\\\final_project\\\\project_1\\\\\")\n )\n}\n\nobject FuckDriver extends App {\n (new ChiselStage).emitVerilog(\n new Accumu2(16, 10, 36, 4),\n //new ROMBias,\n //new RAMGroup(StdPara.w, StdPara.addr_w, StdPara.id_w), \n Array(\"--target-dir\", \"C:\\\\Users\\\\yfz\\\\Desktop\\\\data\\\\Plan\\\\homework\\\\AI_fpga\\\\final_project\\\\project_test\\\\\")\n )\n}\n\nobject XDriver extends App {\n (new ChiselStage).emitVerilog(\n new Wrapper,\n Array(\"--target-dir\", \"C:\\\\Users\\\\yfz\\\\Desktop\\\\data\\\\Plan\\\\homework\\\\AI_fpga\\\\final_project\\\\project_1\\\\\")\n )\n}", "groundtruth": "\n val r64 = RegInit(0.U.asTypeOf(Vec(para_num, new AccumuRawData(w))))\n for(t <- 0 to para_num-1)\n", "crossfile_context": "", "category": "Storage Block", "subcategory": "Register-based Storage", "confidence": 0.85, "category_reason": "RegInit register"} {"task_id": "fpga_final_project", "path": "fpga_final_project/src/main/scala/top/final_top.scala", "left_context": "// Copy from top.scala\n\n// And change the interface\n\npackage final_project\n\nimport chisel3._\nimport chisel3.util._\n\nimport chisel3.experimental.BundleLiterals._\n\nclass FinalTop extends Module{\n val io = IO(new Bundle{\n val start = Input(Bool())\n val input = Input(SInt(16.W))\n val valid_in = Input(Bool())\n val complete = Output(Bool())\n val complete_output = Output(Bool())\n val valid = Output(Bool())\n val output = Output(SInt(16.W))\n })\n\n val reader1 = Module(new GraphReader(StdPara.addr_w, StdPara.h_w, StdPara.c_w, StdPara.id_w, StdPara.big_w)).io\n val reader2 = Module(new GraphReader(StdPara.addr_w, StdPara.h_w, StdPara.c_w, StdPara.id_w, StdPara.big_w)).io\n val read_pack = Module(new PackReadData(StdPara.w, StdPara.h_w, StdPara.c_w, StdPara.big_w)).io\n val read_switch = Module(new ReadSwitch(StdPara.w, StdPara.h_w, StdPara.c_w, StdPara.para_num)).io\n val read_weight = Module(new WeightReader(StdPara.w, StdPara.weight_addr_w)).io\n val calc8x8 = Module(new Calc8x8(StdPara.w, StdPara.para_num)).io\n val accu = Module(new Accumu(StdPara.w, StdPara.bias_addr_w, StdPara.bias_w, StdPara.para_num)).io\n\n val cache_writer = Module(new CacheWriter(StdPara.w, StdPara.para_num)).io\n val quant = Module(new Quant(StdPara.w)).io\n val write_switch = Module(new WriteSwitch(StdPara.w, 3)).io\n val writer = Module(new RealWriter(StdPara.w, StdPara.addr_w, StdPara.h_w, StdPara.c_w, StdPara.id_w)).io\n val maxpool = Module(new Maxpool(StdPara.w)).io\n\n", "right_context": " val rom_bias = if(StdPara.para_num==4) Module(new ROMBias(StdPara.para_num)).io else Module(new ROMHalfBias(StdPara.para_num)).io\n // val rom_weight = Module(new ROMWeight(StdPara.para_num)).io\n // val rom_bias = Module(new ROMBias(StdPara.para_num)).io\n val bram = Module(new RAMGroup(StdPara.w, StdPara.addr_w, StdPara.id_w)).io\n\n io.complete := false.B\n io.valid := false.B\n io.output := 0.S\n bram.rd_addr1 := reader1.to_banks\n reader1.flag_job := false.B\n reader1.valid_in := false.B\n reader1.job := 0.U.asTypeOf(reader1.job)\n reader1.job_type := 0.U.asTypeOf(reader1.job_type)\n reader1.job2 := 0.U.asTypeOf(reader1.job2)\n reader1.signal := false.B\n\n bram.rd_valid_in := reader2.valid_out\n bram.rd_addr2 := reader2.to_banks\n reader2.flag_job := false.B\n reader2.valid_in := false.B\n reader2.job := 0.U.asTypeOf(reader2.job)\n reader2.job_type := 0.U.asTypeOf(reader2.job_type)\n reader2.job2 := 0.U.asTypeOf(reader2.job2)\n reader2.signal := false.B\n\n read_weight.valid_in := false.B\n read_weight.addr_end := 0.U\n read_weight.begin_addr := 0.U\n rom_weight.addr := read_weight.addr\n read_weight.flag_job := false.B\n \n\n read_pack.valid_in := bram.rd_valid_out\n read_pack.flag_job := false.B\n read_pack.job := 0.U.asTypeOf(read_pack.job)\n read_pack.from_big := bram.rd_big\n read_pack.from_small := bram.rd_small\n \n read_switch.flag_job := false.B\n read_switch.job := 0.U.asTypeOf(read_switch.job)\n read_switch.valid_in := read_pack.valid_out\n read_switch.from := read_pack.output\n read_switch.from_weight := rom_weight.out\n read_switch.in_h := 0.U\n read_switch.in_chan := 0.U\n read_switch.valid_in_from_user := false.B\n read_switch.data_from_user := 0.U.asTypeOf(read_switch.data_from_user)\n\n calc8x8.input := read_switch.to_calc8x8\n calc8x8.flag := 0.U.asTypeOf(calc8x8.flag)\n calc8x8.weight := read_switch.to_weight\n calc8x8.valid_in := read_switch.valid_out_calc8x8\n calc8x8.mask := 0.U\n calc8x8.multmap := read_switch.to_multmap\n \n \n accu.in_from_calc8x8 := calc8x8.output\n accu.valid_in := calc8x8.valid_out\n accu.flag_job := false.B\n accu.csum := 0.U\n accu.bias_begin_addr := 0.U\n accu.bias_end_addr := 0.U\n rom_bias.addr := accu.bias_addr\n accu.bias_in := rom_bias.out\n accu.is_in_use := false.B\n\n cache_writer.in_from_accumu := accu.result\n cache_writer.valid_in := accu.valid_out\n\n\n quant.in_from_accumu := cache_writer.out\n quant.valid_in := cache_writer.valid_out\n quant.flag_job := false.B\n quant.quant_in := 0.U.asTypeOf(quant.quant_in)\n\n \n maxpool.from_big := bram.rd_big\n for(t <- 0 to 1){\n maxpool.from_small(t)(0) := bram.rd_small(t)(0)\n maxpool.from_small(t)(1) := bram.rd_small(t)(1)\n }\n \n maxpool.valid_in := read_switch.valid_out_maxp\n\n //write_switch.valid_in(1) := false.B\n //write_switch.input(1) := 0.U.asTypeOf(write_switch.input(1))\n\n write_switch.valid_in(0) := quant.valid_out // conv\n write_switch.valid_in(1) := maxpool.valid_out // maxpool\n write_switch.valid_in(2) := read_switch.valid_out_copy // go through\n\n write_switch.input(0) := quant.result\n write_switch.input(1) := maxpool.result\n write_switch.input(2) := read_switch.to_copy\n\n writer.in_from_quant := write_switch.output\n writer.valid_in := write_switch.valid_out\n writer.flag_job := false.B\n writer.job := 0.U.asTypeOf(writer.job)\n\n // io.output_ls := quant.result.mat(0)\n\n\n /*dontTouch(writer.to_banks)\n dontTouch(writer.to_bigbank)\n dontTouch(writer.to_smallbank)\n dontTouch(writer.valid_out)*/\n bram.wr_addr := writer.to_banks\n bram.to_bigbank := writer.to_bigbank\n bram.to_smallbank := writer.to_smallbank\n bram.wr_valid_in := writer.valid_out\n\n def nxt_big(x: Int): Int = {\n val L = StdPara.big_min_addr\n val R = StdPara.big_max_addr\n return (x-L)%(R-L+1)+L\n }\n def nxt_small(x: Int): Int = {\n val L = StdPara.small_min_addr\n val R = StdPara.small_max_addr\n return (x-L)%(R-L+1)+L\n }\n\n var big_addr = StdPara.big_min_addr\n var small_addr = StdPara.small_min_addr\n var weight_addr = 0\n var bias_addr = 0\n \n\n \n \n val counter = RegInit(0.U.asTypeOf(ACounter(16.W)))\n val state = RegInit(0.U(6.W))\n\n\n var num_stages = 0\n\n io.complete_output := false.B\n\n WAIT_START()\n CONV(4, 4, 4, 16, 30, 15)\n // LAST_PRINT(8, 8, 4)\n // NEXT_LOOP()\n // LAST_PRINT(8, 8, 4)\n // END()\n // WRITEHALF_CONV1(8, 8, 17, 8)\n // LAST_PRINT(4, 4, 32)\n \n // RELU(4, 4, 16, 15+15, 17)\n // CONV(4, 4, 16, 32, 32, 16)\n // LAST_PRINT(4, 4, 16)\n RELU0(4, 4, 16, 15+15, 17)\n // weight_addr = 0\n // bias_addr = 0\n // big_addr = 0\n // small_addr = 0\n // CONV(4, 4, 4, 16, 30, 15)\n // RELU(4, 4, 16, 15+15, 17)\n // LAST_PRINT(4, 4, 16)\n\n CONV1(4, 4, 16, 32, 32, 16)\n RELU1(4, 4, 32, 16+15, 17)\n MAXPOOL(4, 4, 32)\n //conv_2\n CONV(2, 2, 32, 64, 32, 14)\n RELU(2, 2, 64, 14+15, 14)\n\n // conv_6\n CONV(2, 2, 64, 64, 29, 11) \n RELU(2, 2, 64, 11+15, 11)\n\n\n // conv_u1\n UPS(2, 2, 64)\n\n CONV(4, 4, 64, 32, 26, 8)\n RELU(4, 4, 32, 8+15, 8)\n // LAST_PRINT(4, 4, 32)\n println(num_stages)\n CONVMULT()\n println(num_stages)\n\n // conv_u4\n UPS(4, 4, 16)\n CONV(8, 8, 16, 16, 27, 12)\n RELU(8, 8, 16, 12+15, 12)\n\n // conv_10\n CONV(8, 8, 16, 4, 29, 13)\n LAST_PRINT(8, 8, 4)\n NEXT_LOOP()\n\n // val checksum = RegInit(0.U(16.W))\n // CHECK_PRINT()\n // LAST_CHECK(8, 8, 4)\n // LAST_PRINT(2, 2, 32)\n\n\n def WAIT_START(){\n when(state===(num_stages).U){\n when(io.start){\n state := (num_stages+1).U \n } \n }\n num_stages += 1\n }\n def CONVMULT(){\n WRITEHALF_CONV1(8, 8, 17, 8)\n println(num_stages)\n CONV(4, 4, 64, 16, 22, 6)\n println(num_stages)\n RELU(4, 4, 16, 6+15, 6)\n println(num_stages)\n MULT(6+17, 11) \n // LAST_PRINT(4, 4, 16)\n }\n\n def MULT(q_in: Int, q_out: Int){\n val paras = GenAllPara(addr_w=StdPara.addr_w, h_w=StdPara.h_w, c_w=StdPara.c_w, id_w=StdPara.id_w, big_w=StdPara.big_w, \n width=4, \n height=4, \n wr_width=4, \n wr_height=4,\n in_chan=16, \n out_chan=16,\n para_num=StdPara.para_num, \n mask=StdPara.mask,\n big_begin_addr=big_addr, \n big_max_addr=StdPara.big_max_addr, \n big_min_addr=StdPara.big_min_addr, \n wr_big_begin_addr=nxt_big(big_addr+16*4*4/2), \n wr_big_max_addr=StdPara.big_max_addr, \n wr_big_min_addr=StdPara.big_min_addr, \n small_begin_addr=small_addr, \n small_max_addr=StdPara.small_max_addr, \n small_min_addr=StdPara.small_min_addr, \n wr_small_begin_addr=nxt_small(small_addr+16*4*4/4), \n wr_small_max_addr=StdPara.small_max_addr, \n wr_small_min_addr=StdPara.small_min_addr, \n weight_begin_addr=0, \n bias_begin_addr=0, \n quant_q_in=q_in, \n quant_q_out=q_out \n )\n\n val paras2 = GenAllPara(addr_w=StdPara.addr_w, h_w=StdPara.h_w, c_w=StdPara.c_w, id_w=StdPara.id_w, big_w=StdPara.big_w, \n width=4, \n height=4, \n wr_width=4, \n wr_height=4,\n in_chan=16, \n out_chan=16,\n para_num=StdPara.para_num, \n mask=StdPara.mask,\n big_begin_addr=StdPara.big_conv0_addr, \n big_max_addr=StdPara.big_global_addr, \n big_min_addr=0, \n wr_big_begin_addr=0, \n wr_big_max_addr=0, \n wr_big_min_addr=0, \n small_begin_addr=StdPara.small_conv0_addr, \n small_max_addr=StdPara.small_global_addr, \n small_min_addr=0, \n wr_small_begin_addr=0, \n wr_small_max_addr=0, \n wr_small_min_addr=0, \n weight_begin_addr=0, \n bias_begin_addr=0, \n quant_q_in=0, \n quant_q_out=0 \n )\n\n big_addr = nxt_big(big_addr+16*4*4/2)\n small_addr = nxt_small(small_addr+16*4*4/4)\n when(state===(num_stages).U){\n paras.set_copy_reader1(reader1, 1)\n paras.set_copy_reader2(reader2, 1)\n paras2.set_copy_reader1_job2(reader1, 1)\n paras2.set_copy_reader2_job2(reader2, 1)\n paras.set_ups_read_pack(read_pack)\n paras.set_mult_switch(read_switch)\n paras.set_unuse_accu(accu)\n paras.set_quant(quant)\n paras.set_write(writer)\n counter.set((16*4*4-1).U)\n state := (num_stages+1).U\n }\n num_stages += 1\n when(state===(num_stages).U){\n when(writer.valid_out){\n when(counter.inc()){\n state := (num_stages+1).U\n }\n }\n reader1.valid_in := true.B\n reader2.valid_in := true.B\n reader1.signal := true.B\n reader2.signal := true.B\n calc8x8.flag := CalcType.calcMult\n }\n num_stages += 1\n\n }\n\n def WRITEHALF_CONV1(q_in: Int, q_out: Int, q_in2: Int, q_out2: Int){\n val in_chan = 32\n val paras = GenAllPara(addr_w=StdPara.addr_w, h_w=StdPara.h_w, c_w=StdPara.c_w, id_w=StdPara.id_w, big_w=StdPara.big_w, \n width=4, \n height=4, \n wr_width=4, \n wr_height=4,\n in_chan=in_chan, \n out_chan=in_chan*2,\n para_num=StdPara.para_num, \n mask=StdPara.mask,\n big_begin_addr=big_addr, \n big_max_addr=StdPara.big_max_addr, \n big_min_addr=StdPara.big_min_addr, \n wr_big_begin_addr=nxt_big(big_addr+in_chan*4*4/2+0), \n wr_big_max_addr=StdPara.big_max_addr, \n wr_big_min_addr=StdPara.big_min_addr, \n small_begin_addr=small_addr, \n small_max_addr=StdPara.small_max_addr, \n small_min_addr=StdPara.small_min_addr, \n wr_small_begin_addr=nxt_small(small_addr+in_chan*4*4/4+0), \n wr_small_max_addr=StdPara.small_max_addr, \n wr_small_min_addr=StdPara.small_min_addr, \n weight_begin_addr=0, \n bias_begin_addr=0, \n quant_q_in=q_in, \n quant_q_out=q_out \n )\n\n val paras2 = GenAllPara(addr_w=StdPara.addr_w, h_w=StdPara.h_w, c_w=StdPara.c_w, id_w=StdPara.id_w, big_w=StdPara.big_w, \n width=4, \n height=4, \n wr_width=4, \n wr_height=4,\n in_chan=in_chan, \n out_chan=in_chan*2,\n para_num=StdPara.para_num, \n mask=StdPara.mask,\n big_begin_addr=StdPara.big_conv1_addr, \n big_max_addr=StdPara.big_global_addr, \n big_min_addr=0, \n wr_big_begin_addr=nxt_big(big_addr+in_chan*4*4/2+in_chan), \n wr_big_max_addr=StdPara.big_max_addr, \n wr_big_min_addr=StdPara.big_min_addr, \n small_begin_addr=StdPara.small_conv1_addr, \n small_max_addr=StdPara.small_global_addr, \n small_min_addr=0, \n wr_small_begin_addr=nxt_small(small_addr+in_chan*4*4/4+in_chan), \n wr_small_max_addr=StdPara.small_max_addr, \n wr_small_min_addr=StdPara.small_min_addr, \n weight_begin_addr=0, \n bias_begin_addr=0, \n quant_q_in=q_in2, \n quant_q_out=q_out2 \n )\n\n big_addr = nxt_big(big_addr+in_chan*4*4/2)\n small_addr = nxt_small(small_addr+in_chan*4*4/4)\n when(state===(num_stages).U){\n paras.set_copy_reader1(reader1, 1)\n paras.set_copy_reader2(reader2, 1)\n paras.set_copy_read_pack(read_pack)\n paras.set_copy_switch(read_switch)\n paras.set_unuse_accu(accu)\n paras.set_quant(quant)\n paras.set_write_alar(writer, 0, in_chan-1)\n counter.set((in_chan*4*4-1).U)\n state := (num_stages+1).U\n }\n num_stages += 1\n when(state===(num_stages).U){\n when(writer.valid_out){\n when(counter.inc()){\n state := (num_stages+1).U\n }\n }\n reader1.valid_in := true.B\n reader2.valid_in := true.B\n }\n num_stages += 1\n when(state===(num_stages).U){\n paras2.set_copy_reader1(reader1, 1)\n paras2.set_copy_reader2(reader2, 1)\n paras2.set_copy_read_pack(read_pack)\n paras2.set_conv_read_switch(read_switch)\n paras2.set_unuse_accu(accu)\n paras2.set_quant(quant)\n paras2.set_write_alar(writer, in_chan, 2*in_chan-1)\n counter.set((in_chan*4*4-1).U)\n state := (num_stages+1).U\n }\n num_stages += 1\n when(state===(num_stages).U){\n when(writer.valid_out){\n when(counter.inc()){\n state := (num_stages+1).U\n }\n }\n reader1.valid_in := true.B\n reader2.valid_in := true.B\n calc8x8.flag := CalcType.empty\n }\n num_stages += 1\n }\n\n\n def CONV(w: Int, h: Int, in_chan: Int, out_chan: Int, conv_q_in: Int, \n conv_q_out: Int): Unit = {\n val paras = GenAllPara(addr_w=StdPara.addr_w, h_w=StdPara.h_w, c_w=StdPara.c_w, id_w=StdPara.id_w, big_w=StdPara.big_w, \n width=w, \n height=h, \n wr_width=w, \n wr_height=h,\n in_chan=in_chan, \n out_chan=out_chan,\n para_num=StdPara.para_num, \n mask=StdPara.mask,\n big_begin_addr=big_addr, \n big_max_addr=StdPara.big_max_addr, \n big_min_addr=StdPara.big_min_addr, \n wr_big_begin_addr=nxt_big(big_addr+in_chan*w*h/2), \n wr_big_max_addr=StdPara.big_max_addr, \n wr_big_min_addr=StdPara.big_min_addr, \n small_begin_addr=small_addr, \n small_max_addr=StdPara.small_max_addr, \n small_min_addr=StdPara.small_min_addr, \n wr_small_begin_addr=nxt_small(small_addr+in_chan*w*h/4), \n wr_small_max_addr=StdPara.small_max_addr, \n wr_small_min_addr=StdPara.small_min_addr, \n weight_begin_addr=weight_addr, \n bias_begin_addr=bias_addr, \n quant_q_in=conv_q_in, \n quant_q_out=conv_q_out \n )\n big_addr = nxt_big(big_addr+in_chan*w*h/2)\n small_addr = nxt_small(small_addr+in_chan*w*h/4)\n weight_addr += in_chan*out_chan/StdPara.para_num\n bias_addr += out_chan/StdPara.para_num\n\n when(state===(num_stages).U){\n paras.set_conv_reader1(reader1)\n paras.set_conv_reader2(reader2)\n paras.set_read_weight(read_weight)\n paras.set_conv_read_pack(read_pack)\n paras.set_conv_accu(accu)\n paras.set_quant(quant)\n paras.set_write(writer)\n paras.set_conv_read_switch(read_switch)\n\n counter.set((out_chan*w*h-1).U)\n state := (num_stages+1).U\n }\n num_stages += 1\n when(state===(num_stages).U){\n when(writer.valid_out){\n when(counter.inc()){\n state := (num_stages+1).U\n }\n }\n reader1.valid_in := true.B\n reader2.valid_in := true.B\n read_weight.valid_in := true.B\n calc8x8.flag := CalcType.calcConv\n calc8x8.mask := paras.mask.U\n }\n num_stages += 1\n }\n\n def CONV1(w: Int, h: Int, in_chan: Int, out_chan: Int, conv_q_in: Int, \n conv_q_out: Int): Unit = {\n val paras = GenAllPara(addr_w=StdPara.addr_w, h_w=StdPara.h_w, c_w=StdPara.c_w, id_w=StdPara.id_w, big_w=StdPara.big_w, \n width=w, \n height=h, \n wr_width=w, \n wr_height=h,\n in_chan=in_chan, \n out_chan=out_chan,\n para_num=StdPara.para_num, \n mask=StdPara.mask,\n big_begin_addr=StdPara.big_conv0_addr, \n big_max_addr=StdPara.big_global_addr, \n big_min_addr=0, \n wr_big_begin_addr=big_addr, \n wr_big_max_addr=StdPara.big_max_addr, \n wr_big_min_addr=StdPara.big_min_addr, \n small_begin_addr=StdPara.small_conv0_addr, \n small_max_addr=StdPara.small_global_addr, \n small_min_addr=0, \n wr_small_begin_addr=small_addr, \n wr_small_max_addr=StdPara.small_max_addr, \n wr_small_min_addr=StdPara.small_min_addr, \n weight_begin_addr=weight_addr, \n bias_begin_addr=bias_addr, \n quant_q_in=conv_q_in, \n quant_q_out=conv_q_out \n )\n weight_addr += in_chan*out_chan/StdPara.para_num\n bias_addr += out_chan/StdPara.para_num\n\n when(state===(num_stages).U){\n paras.set_conv_reader1(reader1)\n paras.set_conv_reader2(reader2)\n paras.set_read_weight(read_weight)\n paras.set_conv_read_pack(read_pack)\n paras.set_conv_accu(accu)\n paras.set_quant(quant)\n paras.set_write(writer)\n paras.set_conv_read_switch(read_switch)\n\n calc8x8.mask := paras.mask.U\n counter.set((out_chan*w*h-1).U)\n state := (num_stages+1).U\n }\n num_stages += 1\n when(state===(num_stages).U){\n when(writer.valid_out){\n when(counter.inc()){\n state := (num_stages+1).U\n }\n }\n reader1.valid_in := true.B\n reader2.valid_in := true.B\n read_weight.valid_in := true.B\n calc8x8.flag := CalcType.calcConv\n calc8x8.mask := paras.mask.U\n }\n num_stages += 1\n }\n\n def RELU0(w: Int, h: Int, in_chan: Int, relu_q_in: Int, relu_q_out: Int): Unit = {\n val paras = GenAllPara(addr_w=StdPara.addr_w, h_w=StdPara.h_w, c_w=StdPara.c_w, id_w=StdPara.id_w, big_w=StdPara.big_w, \n width=w, \n height=h, \n wr_width=w, \n wr_height=h,\n in_chan=in_chan, \n out_chan=in_chan,\n para_num=1, \n mask=1,\n big_begin_addr=big_addr, \n big_max_addr=StdPara.big_max_addr, \n big_min_addr=StdPara.big_min_addr, \n wr_big_begin_addr=StdPara.big_conv0_addr, \n wr_big_max_addr=StdPara.big_global_addr, \n wr_big_min_addr=0, \n small_begin_addr=small_addr, \n small_max_addr=StdPara.small_max_addr, \n small_min_addr=StdPara.small_min_addr, \n wr_small_begin_addr=StdPara.small_conv0_addr,\n wr_small_max_addr=StdPara.small_global_addr,\n wr_small_min_addr=0,\n weight_begin_addr=0, \n bias_begin_addr=0, \n quant_q_in=relu_q_in, \n quant_q_out=relu_q_out \n )\n\n when(state===(num_stages).U){\n paras.set_copy_reader1(reader1, 1)\n paras.set_copy_reader2(reader2, 1)\n paras.set_copy_read_pack(read_pack)\n paras.set_conv_read_switch(read_switch)\n paras.set_unuse_accu(accu)\n paras.set_quant(quant)\n paras.set_write(writer)\n counter.set((in_chan*w*h-1).U)\n state := (num_stages+1).U\n }\n num_stages += 1\n when(state===(num_stages).U){\n when(writer.valid_out){\n when(counter.inc()){\n state := (num_stages+1).U\n }\n }\n reader1.valid_in := true.B\n reader2.valid_in := true.B\n calc8x8.flag := CalcType.leakyReLU\n }\n num_stages += 1\n }\n\n def RELU1(w: Int, h: Int, in_chan: Int, relu_q_in: Int, relu_q_out: Int): Unit = {\n val paras = GenAllPara(addr_w=StdPara.addr_w, h_w=StdPara.h_w, c_w=StdPara.c_w, id_w=StdPara.id_w, big_w=StdPara.big_w, \n width=w, \n height=h, \n wr_width=w, \n wr_height=h,\n in_chan=in_chan, \n out_chan=in_chan,\n para_num=1, \n mask=1,\n big_begin_addr=big_addr, \n big_max_addr=StdPara.big_max_addr, \n big_min_addr=StdPara.big_min_addr, \n wr_big_begin_addr=StdPara.big_conv1_addr, \n wr_big_max_addr=StdPara.big_global_addr, \n wr_big_min_addr=0, \n small_begin_addr=small_addr, \n small_max_addr=StdPara.small_max_addr, \n small_min_addr=StdPara.small_min_addr, \n wr_small_begin_addr=StdPara.small_conv1_addr,\n wr_small_max_addr=StdPara.small_global_addr,\n wr_small_min_addr=0,\n weight_begin_addr=0, \n bias_begin_addr=0, \n quant_q_in=relu_q_in, \n quant_q_out=relu_q_out \n )\n\n when(state===(num_stages).U){\n paras.set_copy_reader1(reader1, 1)\n paras.set_copy_reader2(reader2, 1)\n paras.set_copy_read_pack(read_pack)\n paras.set_conv_read_switch(read_switch)\n paras.set_unuse_accu(accu)\n paras.set_quant(quant)\n paras.set_write(writer)\n counter.set((in_chan*w*h-1).U)\n state := (num_stages+1).U\n }\n num_stages += 1\n when(state===(num_stages).U){\n when(writer.valid_out){\n when(counter.inc()){\n state := (num_stages+1).U\n }\n }\n reader1.valid_in := true.B\n reader2.valid_in := true.B\n calc8x8.flag := CalcType.leakyReLU\n }\n num_stages += 1\n }\n\n def RELU(w: Int, h: Int, in_chan: Int, relu_q_in: Int, relu_q_out: Int): Unit = {\n val paras = GenAllPara(addr_w=StdPara.addr_w, h_w=StdPara.h_w, c_w=StdPara.c_w, id_w=StdPara.id_w, big_w=StdPara.big_w, \n width=w, \n height=h, \n wr_width=w, \n wr_height=h,\n in_chan=in_chan, \n out_chan=in_chan,\n para_num=StdPara.para_num, \n mask=StdPara.mask,\n big_begin_addr=big_addr, \n big_max_addr=StdPara.big_max_addr, \n big_min_addr=StdPara.big_min_addr, \n wr_big_begin_addr=nxt_big(big_addr+in_chan*w*h/2), \n wr_big_max_addr=StdPara.big_max_addr, \n wr_big_min_addr=StdPara.big_min_addr, \n small_begin_addr=small_addr, \n small_max_addr=StdPara.small_max_addr, \n small_min_addr=StdPara.small_min_addr, \n wr_small_begin_addr=nxt_small(small_addr+in_chan*w*h/4), \n wr_small_max_addr=StdPara.small_max_addr, \n wr_small_min_addr=StdPara.small_min_addr, \n weight_begin_addr=0, \n bias_begin_addr=0, \n quant_q_in=relu_q_in, \n quant_q_out=relu_q_out \n )\n\n big_addr = nxt_big(big_addr+in_chan*w*h/2)\n small_addr = nxt_small(small_addr+in_chan*w*h/4)\n when(state===(num_stages).U){\n paras.set_copy_reader1(reader1, 1)\n paras.set_copy_reader2(reader2, 1)\n paras.set_copy_read_pack(read_pack)\n paras.set_conv_read_switch(read_switch)\n paras.set_unuse_accu(accu)\n paras.set_quant(quant)\n paras.set_write(writer)\n counter.set((in_chan*w*h-1).U)\n state := (num_stages+1).U\n }\n num_stages += 1\n when(state===(num_stages).U){\n when(writer.valid_out){\n when(counter.inc()){\n state := (num_stages+1).U\n }\n }\n reader1.valid_in := true.B\n reader2.valid_in := true.B\n calc8x8.flag := CalcType.leakyReLU\n }\n num_stages += 1\n }\n\n def MAXPOOL(w: Int, h: Int, in_chan: Int): Unit = {\n val paras = GenAllPara(addr_w=StdPara.addr_w, h_w=StdPara.h_w, c_w=StdPara.c_w, id_w=StdPara.id_w, big_w=StdPara.big_w, \n width=w, \n height=h, \n wr_width=w/2, \n wr_height=h/2,\n in_chan=in_chan, \n out_chan=in_chan,\n para_num=1, \n mask=0,\n big_begin_addr=StdPara.big_conv1_addr, \n big_max_addr=StdPara.big_global_addr, \n big_min_addr=0, \n wr_big_begin_addr=big_addr, \n wr_big_max_addr=StdPara.big_max_addr, \n wr_big_min_addr=StdPara.big_min_addr, \n small_begin_addr=StdPara.small_conv1_addr, \n small_max_addr=StdPara.small_global_addr, \n small_min_addr=0, \n wr_small_begin_addr=small_addr, \n wr_small_max_addr=StdPara.small_max_addr, \n wr_small_min_addr=StdPara.small_min_addr, \n weight_begin_addr=0, \n bias_begin_addr=0, \n quant_q_in=0, \n quant_q_out=0 \n )\n\n when(state===(num_stages).U){\n paras.set_maxp_reader1(reader1)\n paras.set_maxp_reader2(reader2)\n paras.set_write(writer)\n paras.set_maxpool_switch(read_switch)\n counter.set((in_chan*w*h/4-1).U)\n\n state := (num_stages+1).U\n }\n num_stages += 1\n when(state===(num_stages).U){\n when(writer.valid_out){\n when(counter.inc()){\n state := (num_stages+1).U\n }\n }\n reader1.valid_in := true.B\n reader2.valid_in := true.B\n }\n num_stages += 1\n }\n\n def UPS(w: Int, h: Int, in_chan: Int): Unit = {\n val paras = GenAllPara(addr_w=StdPara.addr_w, h_w=StdPara.h_w, c_w=StdPara.c_w, id_w=StdPara.id_w, big_w=StdPara.big_w, \n width=w, \n height=h, \n wr_width=w*2, \n wr_height=h*2,\n in_chan=in_chan, \n out_chan=in_chan,\n para_num=StdPara.para_num, \n mask=StdPara.mask,\n big_begin_addr=big_addr, \n big_max_addr=StdPara.big_max_addr, \n big_min_addr=StdPara.big_min_addr, \n wr_big_begin_addr=nxt_big(big_addr+in_chan*w*h/2), \n wr_big_max_addr=StdPara.big_max_addr, \n wr_big_min_addr=StdPara.big_min_addr, \n small_begin_addr=small_addr, \n small_max_addr=StdPara.small_max_addr, \n small_min_addr=StdPara.small_min_addr, \n wr_small_begin_addr=nxt_small(small_addr+in_chan*w*h/4), \n wr_small_max_addr=StdPara.small_max_addr, \n wr_small_min_addr=StdPara.small_min_addr, \n weight_begin_addr=0, \n bias_begin_addr=0, \n quant_q_in=0, \n quant_q_out=0 \n )\n\n big_addr = nxt_big(big_addr+in_chan*w*h/2)\n small_addr = nxt_small(small_addr+in_chan*w*h/4)\n\n when(state===(num_stages).U){\n paras.set_ups_reader1(reader1)\n paras.set_ups_reader2(reader2)\n paras.set_ups_read_pack(read_pack)\n paras.set_write(writer)\n paras.set_ups_switch(read_switch)\n counter.set((in_chan*w*h*4-1).U)\n\n state := (num_stages+1).U\n }\n num_stages += 1\n when(state===(num_stages).U){\n when(writer.valid_out){\n when(counter.inc()){\n state := (num_stages+1).U\n }\n }\n reader1.valid_in := true.B\n reader2.valid_in := true.B\n }\n num_stages += 1\n }\n\n def LAST_PRINT(w: Int, h: Int, in_chan: Int): Unit = {\n val output_cache = RegInit(VecInit(Seq.fill(64)(0.S(16.W))))\n val write_cache = RegInit(VecInit(Seq.fill(64)(0.S(16.W))))\n val lst_counter = RegInit(0.U.asTypeOf(ACounter(16.W)))\n val lst_64_counter = RegInit(0.U.asTypeOf(ACounter(16.W)))\n println(big_addr)\n println(small_addr)\n val paras_print = GenAllPara(StdPara.addr_w, StdPara.h_w, StdPara.c_w, StdPara.id_w, big_w=StdPara.big_w, \n 8, 8, 4, 4, \n 4, 1,\n 1, 0,\n big_addr, StdPara.big_max_addr, StdPara.big_min_addr,\n 0, 0, 0,\n small_addr, StdPara.small_max_addr, StdPara.small_min_addr,\n 0, 0, 0,\n 0, 0, 0, 0\n )\n val paras_new_input = GenAllPara(StdPara.addr_w, StdPara.h_w, StdPara.c_w, StdPara.id_w, big_w=StdPara.big_w, \n 8, 8, 4, 4, \n 4, 4,\n 1, 0,\n 0, 0, 0,\n StdPara.big_min_addr, StdPara.big_max_addr, StdPara.big_min_addr,\n 0, 0, 0,\n StdPara.small_min_addr, StdPara.small_max_addr, StdPara.small_min_addr,\n 0, 0, 0, 0\n )\n when(state===(num_stages).U){\n state := (num_stages+1).U\n paras_print.set_conv_reader1(reader1)\n paras_print.set_conv_reader2(reader2)\n paras_print.set_conv_read_pack(read_pack)\n read_switch.flag_job := true.B\n read_switch.job := ReadSwitchType.idle\n paras_new_input.set_write(writer)\n lst_64_counter.set(63.U)\n lst_counter.set((w*h*in_chan-1).U)\n }\n when(state===(num_stages+1).U){\n reader1.valid_in := true.B\n reader2.valid_in := true.B\n state := (num_stages+2).U\n }\n when(state===(num_stages+2).U){\n state := (num_stages+3).U\n io.complete := true.B\n }\n for(i <- 0 to 62)\n write_cache(i) := write_cache(i+1)\n val rs_reg = RegInit(false.B)\n when(state===(num_stages+3).U){\n read_switch.data_from_user.mat := write_cache\n rs_reg := false.B\n when(lst_64_counter.inc()){\n when(lst_counter.inc()){\n state := (num_stages+4).U\n }\n rs_reg := true.B\n }.elsewhen(lst_64_counter.ccnt===62.U){\n reader1.valid_in := true.B\n reader2.valid_in := true.B \n }\n read_switch.valid_in_from_user := rs_reg\n when(read_pack.valid_out){\n io.valid := true.B\n io.output := read_pack.output.mat(0)\n for(i <- 0 to 62)\n output_cache(i) := read_pack.output.mat(i+1)\n }.otherwise{\n io.valid := true.B\n io.output := output_cache(0)\n for(i <- 0 to 62)\n output_cache(i) := output_cache(i+1)\n }\n write_cache(63) := io.input\n }\n when(state===(num_stages+4).U){\n rs_reg := false.B\n state := (num_stages+5).U\n io.complete_output := true.B\n }\n num_stages += 5\n }\n\n /*def CHECK_PRINT(): Unit = {\n when(io.valid){\n checksum := checksum^io.output.asUInt\n }\n io.checksum := checksum\n }*/\n\n def NEXT_LOOP(): Unit = {\n println(\"next_loop: \", num_stages)\n when(state===(num_stages).U){\n state := 0.U\n }\n num_stages += 1\n }\n def END(): Unit = {\n num_stages += 1\n }\n\n println(\"all state: \", num_stages)\n}", "groundtruth": " val rom_weight = if(StdPara.para_num==4) Module(new ROMWeight(StdPara.para_num)).io else Module(new ROMHalfWeight(StdPara.para_num)).io\n", "crossfile_context": "", "category": "Design Structure", "subcategory": "Hierarchical Composition", "confidence": 0.7, "category_reason": "Module instantiation"} {"task_id": "fpga_final_project", "path": "fpga_final_project/src/main/scala/top/show_on_board.scala", "left_context": "package final_project\n\nimport chisel3._\nimport chisel3.util._\n\nimport chisel3.experimental.BundleLiterals._\n\nclass Show extends Module{\n val io = IO(new Bundle{\n val start = Input(Bool())\n val ok = Output(Bool())\n })\n val fuck = Module(new Top).io\n fuck.start := io.start\n fuck.input := 0.S\n io.ok := false.B\n", "right_context": "", "groundtruth": " when(fuck.complete_output){\n io.ok := fuck.checksum===26782.U\n }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "fpga_final_project", "path": "fpga_final_project/src/main/scala/top/top.scala", "left_context": "package final_project\n\nimport chisel3._\nimport chisel3.util._\n\nimport chisel3.experimental.BundleLiterals._\n\nclass Top extends Module{\n //val io = IO(new)\n val io = IO(new Bundle{\n val start = Input(Bool())\n val input = Input(SInt(16.W))\n val complete = Output(Bool())\n val valid = Output(Bool())\n val complete_output = Output(Bool())\n // val output = Output(UInt(1.W))\n val output = Output(SInt(16.W))\n val checksum = Output(UInt(16.W))\n })\n\n val reader1 = Module(new GraphReader(StdPara.addr_w, StdPara.h_w, StdPara.c_w, StdPara.id_w, StdPara.big_w)).io\n val reader2 = Module(new GraphReader(StdPara.addr_w, StdPara.h_w, StdPara.c_w, StdPara.id_w, StdPara.big_w)).io\n val read_pack = Module(new PackReadData(StdPara.w, StdPara.h_w, StdPara.c_w, StdPara.big_w)).io\n val read_switch = Module(new ReadSwitch(StdPara.w, StdPara.h_w, StdPara.c_w, StdPara.para_num)).io\n val read_weight = Module(new WeightReader(StdPara.w, StdPara.weight_addr_w)).io\n val calc8x8 = Module(new Calc8x8(StdPara.w, StdPara.para_num)).io\n val accu = Module(new Accumu(StdPara.w, StdPara.bias_addr_w, StdPara.bias_w, StdPara.para_num)).io\n\n val cache_writer = Module(new CacheWriter(StdPara.w, StdPara.para_num)).io\n val quant = Module(new Quant(StdPara.w)).io\n val write_switch = Module(new WriteSwitch(StdPara.w, 3)).io\n val writer = Module(new RealWriter(StdPara.w, StdPara.addr_w, StdPara.h_w, StdPara.c_w, StdPara.id_w)).io\n val maxpool = Module(new Maxpool(StdPara.w)).io\n\n val rom_weight = if(StdPara.para_num==4) Module(new ROMWeight(StdPara.para_num)).io else Module(new ROMHalfWeight(StdPara.para_num)).io\n", "right_context": " // val rom_weight = Module(new ROMWeight(StdPara.para_num)).io\n // val rom_bias = Module(new ROMBias(StdPara.para_num)).io\n val bram = Module(new RAMGroup(StdPara.w, StdPara.addr_w, StdPara.id_w)).io\n\n io.complete := false.B\n io.valid := false.B\n io.output := 0.S\n bram.rd_addr1 := reader1.to_banks\n reader1.flag_job := false.B\n reader1.valid_in := false.B\n reader1.job := 0.U.asTypeOf(reader1.job)\n reader1.job_type := 0.U.asTypeOf(reader1.job_type)\n reader1.job2 := 0.U.asTypeOf(reader1.job2)\n reader1.signal := false.B\n\n bram.rd_valid_in := reader2.valid_out\n bram.rd_addr2 := reader2.to_banks\n reader2.flag_job := false.B\n reader2.valid_in := false.B\n reader2.job := 0.U.asTypeOf(reader2.job)\n reader2.job_type := 0.U.asTypeOf(reader2.job_type)\n reader2.job2 := 0.U.asTypeOf(reader2.job2)\n reader2.signal := false.B\n\n read_weight.valid_in := false.B\n read_weight.addr_end := 0.U\n read_weight.begin_addr := 0.U\n rom_weight.addr := read_weight.addr\n read_weight.flag_job := false.B\n \n\n read_pack.valid_in := bram.rd_valid_out\n read_pack.flag_job := false.B\n read_pack.job := 0.U.asTypeOf(read_pack.job)\n read_pack.from_big := bram.rd_big\n read_pack.from_small := bram.rd_small\n \n read_switch.flag_job := false.B\n read_switch.job := 0.U.asTypeOf(read_switch.job)\n read_switch.valid_in := read_pack.valid_out\n read_switch.from := read_pack.output\n read_switch.from_weight := rom_weight.out\n read_switch.in_h := 0.U\n read_switch.in_chan := 0.U\n read_switch.valid_in_from_user := false.B\n read_switch.data_from_user := 0.U.asTypeOf(read_switch.data_from_user)\n\n calc8x8.input := read_switch.to_calc8x8\n calc8x8.flag := 0.U.asTypeOf(calc8x8.flag)\n calc8x8.weight := read_switch.to_weight\n calc8x8.valid_in := read_switch.valid_out_calc8x8\n calc8x8.mask := 0.U\n calc8x8.multmap := read_switch.to_multmap\n \n \n accu.in_from_calc8x8 := calc8x8.output\n accu.valid_in := calc8x8.valid_out\n accu.flag_job := false.B\n accu.csum := 0.U\n accu.bias_begin_addr := 0.U\n accu.bias_end_addr := 0.U\n rom_bias.addr := accu.bias_addr\n accu.bias_in := rom_bias.out\n accu.is_in_use := false.B\n\n cache_writer.in_from_accumu := accu.result\n cache_writer.valid_in := accu.valid_out\n\n\n quant.in_from_accumu := cache_writer.out\n quant.valid_in := cache_writer.valid_out\n quant.flag_job := false.B\n quant.quant_in := 0.U.asTypeOf(quant.quant_in)\n\n \n maxpool.from_big := bram.rd_big\n for(t <- 0 to 1){\n maxpool.from_small(t)(0) := bram.rd_small(t)(0)\n maxpool.from_small(t)(1) := bram.rd_small(t)(1)\n }\n \n maxpool.valid_in := read_switch.valid_out_maxp\n\n //write_switch.valid_in(1) := false.B\n //write_switch.input(1) := 0.U.asTypeOf(write_switch.input(1))\n\n write_switch.valid_in(0) := quant.valid_out // conv\n write_switch.valid_in(1) := maxpool.valid_out // maxpool\n write_switch.valid_in(2) := read_switch.valid_out_copy // go through\n\n write_switch.input(0) := quant.result\n write_switch.input(1) := maxpool.result\n write_switch.input(2) := read_switch.to_copy\n\n writer.in_from_quant := write_switch.output\n writer.valid_in := write_switch.valid_out\n writer.flag_job := false.B\n writer.job := 0.U.asTypeOf(writer.job)\n\n // io.output_ls := quant.result.mat(0)\n\n\n /*dontTouch(writer.to_banks)\n dontTouch(writer.to_bigbank)\n dontTouch(writer.to_smallbank)\n dontTouch(writer.valid_out)*/\n bram.wr_addr := writer.to_banks\n bram.to_bigbank := writer.to_bigbank\n bram.to_smallbank := writer.to_smallbank\n bram.wr_valid_in := writer.valid_out\n\n def nxt_big(x: Int): Int = {\n val L = StdPara.big_min_addr\n val R = StdPara.big_max_addr\n return (x-L)%(R-L+1)+L\n }\n def nxt_small(x: Int): Int = {\n val L = StdPara.small_min_addr\n val R = StdPara.small_max_addr\n return (x-L)%(R-L+1)+L\n }\n\n var big_addr = 0\n var small_addr = 0\n var weight_addr = 0\n var bias_addr = 0\n \n\n \n \n val counter = RegInit(0.U.asTypeOf(ACounter(16.W)))\n val state = RegInit(0.U(8.W))\n\n\n val output_cache = RegInit(VecInit(Seq.fill(64)(0.S(16.W))))\n\n var num_stages = 0\n\n io.complete_output := false.B\n\n WAIT_START()\n CONV(4, 4, 4, 16, 30, 15)\n // WRITEHALF_CONV1(8, 8, 17, 8)\n // LAST_PRINT(4, 4, 32)\n \n // CONV(4, 4, 16, 32, 32, 16)\n // RELU(4, 4, 16, 15+15, 17)\n // LAST_PRINT(4, 4, 16)\n RELU0(4, 4, 16, 15+15, 17)\n // weight_addr = 0\n // bias_addr = 0\n // big_addr = 0\n // small_addr = 0\n // CONV(4, 4, 4, 16, 30, 15)\n // RELU(4, 4, 16, 15+15, 17)\n // LAST_PRINT(4, 4, 16)\n\n CONV1(4, 4, 16, 32, 32, 16)\n RELU1(4, 4, 32, 16+15, 17)\n MAXPOOL(4, 4, 32)\n //conv_2\n CONV(2, 2, 32, 64, 32, 14)\n RELU(2, 2, 64, 14+15, 14)\n\n // conv_6\n CONV(2, 2, 64, 64, 29, 11) \n RELU(2, 2, 64, 11+15, 11)\n\n\n // conv_u1\n UPS(2, 2, 64)\n\n CONV(4, 4, 64, 32, 26, 8)\n RELU(4, 4, 32, 8+15, 8)\n // LAST_PRINT(4, 4, 32)\n println(num_stages)\n CONVMULT()\n println(num_stages)\n\n // conv_u4\n UPS(4, 4, 16)\n CONV(8, 8, 16, 16, 27, 12)\n RELU(8, 8, 16, 12+15, 12)\n\n // conv_10\n CONV(8, 8, 16, 4, 29, 13)\n LAST_PRINT(8, 8, 4)\n\n val checksum = RegInit(0.U(16.W))\n CHECK_PRINT()\n // LAST_CHECK(8, 8, 4)\n // LAST_PRINT(2, 2, 32)\n\n\n def WAIT_START(){\n when(state===(num_stages).U){\n when(io.start){\n state := (num_stages+1).U \n } \n }\n num_stages += 1\n }\n def CONVMULT(){\n WRITEHALF_CONV1(8, 8, 17, 8)\n println(num_stages)\n CONV(4, 4, 64, 16, 22, 6)\n println(num_stages)\n RELU(4, 4, 16, 6+15, 6)\n println(num_stages)\n MULT(6+17, 11) \n // LAST_PRINT(4, 4, 16)\n }\n\n def MULT(q_in: Int, q_out: Int){\n val paras = GenAllPara(addr_w=StdPara.addr_w, h_w=StdPara.h_w, c_w=StdPara.c_w, id_w=StdPara.id_w, big_w=StdPara.big_w, \n width=4, \n height=4, \n wr_width=4, \n wr_height=4,\n in_chan=16, \n out_chan=16,\n para_num=StdPara.para_num, \n mask=StdPara.mask,\n big_begin_addr=big_addr, \n big_max_addr=StdPara.big_max_addr, \n big_min_addr=StdPara.big_min_addr, \n wr_big_begin_addr=nxt_big(big_addr+16*4*4/2), \n wr_big_max_addr=StdPara.big_max_addr, \n wr_big_min_addr=StdPara.big_min_addr, \n small_begin_addr=small_addr, \n small_max_addr=StdPara.small_max_addr, \n small_min_addr=StdPara.small_min_addr, \n wr_small_begin_addr=nxt_small(small_addr+16*4*4/4), \n wr_small_max_addr=StdPara.small_max_addr, \n wr_small_min_addr=StdPara.small_min_addr, \n weight_begin_addr=0, \n bias_begin_addr=0, \n quant_q_in=q_in, \n quant_q_out=q_out \n )\n\n val paras2 = GenAllPara(addr_w=StdPara.addr_w, h_w=StdPara.h_w, c_w=StdPara.c_w, id_w=StdPara.id_w, big_w=StdPara.big_w, \n width=4, \n height=4, \n wr_width=4, \n wr_height=4,\n in_chan=16, \n out_chan=16,\n para_num=StdPara.para_num, \n mask=StdPara.mask,\n big_begin_addr=StdPara.big_conv0_addr, \n big_max_addr=StdPara.big_global_addr, \n big_min_addr=0, \n wr_big_begin_addr=0, \n wr_big_max_addr=0, \n wr_big_min_addr=0, \n small_begin_addr=StdPara.small_conv0_addr, \n small_max_addr=StdPara.small_global_addr, \n small_min_addr=0, \n wr_small_begin_addr=0, \n wr_small_max_addr=0, \n wr_small_min_addr=0, \n weight_begin_addr=0, \n bias_begin_addr=0, \n quant_q_in=0, \n quant_q_out=0 \n )\n\n big_addr = nxt_big(big_addr+16*4*4/2)\n small_addr = nxt_small(small_addr+16*4*4/4)\n when(state===(num_stages).U){\n paras.set_copy_reader1(reader1, 1)\n paras.set_copy_reader2(reader2, 1)\n paras2.set_copy_reader1_job2(reader1, 1)\n paras2.set_copy_reader2_job2(reader2, 1)\n paras.set_ups_read_pack(read_pack)\n paras.set_mult_switch(read_switch)\n paras.set_unuse_accu(accu)\n paras.set_quant(quant)\n paras.set_write(writer)\n counter.set((16*4*4-1).U)\n state := (num_stages+1).U\n }\n num_stages += 1\n when(state===(num_stages).U){\n when(writer.valid_out){\n when(counter.inc()){\n state := (num_stages+1).U\n }\n }\n reader1.valid_in := true.B\n reader2.valid_in := true.B\n reader1.signal := true.B\n reader2.signal := true.B\n calc8x8.flag := CalcType.calcMult\n }\n num_stages += 1\n\n }\n\n def WRITEHALF_CONV1(q_in: Int, q_out: Int, q_in2: Int, q_out2: Int){\n val in_chan = 32\n val paras = GenAllPara(addr_w=StdPara.addr_w, h_w=StdPara.h_w, c_w=StdPara.c_w, id_w=StdPara.id_w, big_w=StdPara.big_w, \n width=4, \n height=4, \n wr_width=4, \n wr_height=4,\n in_chan=in_chan, \n out_chan=in_chan*2,\n para_num=StdPara.para_num, \n mask=StdPara.mask,\n big_begin_addr=big_addr, \n big_max_addr=StdPara.big_max_addr, \n big_min_addr=StdPara.big_min_addr, \n wr_big_begin_addr=nxt_big(big_addr+in_chan*4*4/2+0), \n wr_big_max_addr=StdPara.big_max_addr, \n wr_big_min_addr=StdPara.big_min_addr, \n small_begin_addr=small_addr, \n small_max_addr=StdPara.small_max_addr, \n small_min_addr=StdPara.small_min_addr, \n wr_small_begin_addr=nxt_small(small_addr+in_chan*4*4/4+0), \n wr_small_max_addr=StdPara.small_max_addr, \n wr_small_min_addr=StdPara.small_min_addr, \n weight_begin_addr=0, \n bias_begin_addr=0, \n quant_q_in=q_in, \n quant_q_out=q_out \n )\n\n val paras2 = GenAllPara(addr_w=StdPara.addr_w, h_w=StdPara.h_w, c_w=StdPara.c_w, id_w=StdPara.id_w, big_w=StdPara.big_w, \n width=4, \n height=4, \n wr_width=4, \n wr_height=4,\n in_chan=in_chan, \n out_chan=in_chan*2,\n para_num=StdPara.para_num, \n mask=StdPara.mask,\n big_begin_addr=StdPara.big_conv1_addr, \n big_max_addr=StdPara.big_global_addr, \n big_min_addr=0, \n wr_big_begin_addr=nxt_big(big_addr+in_chan*4*4/2+in_chan), \n wr_big_max_addr=StdPara.big_max_addr, \n wr_big_min_addr=StdPara.big_min_addr, \n small_begin_addr=StdPara.small_conv1_addr, \n small_max_addr=StdPara.small_global_addr, \n small_min_addr=0, \n wr_small_begin_addr=nxt_small(small_addr+in_chan*4*4/4+in_chan), \n wr_small_max_addr=StdPara.small_max_addr, \n wr_small_min_addr=StdPara.small_min_addr, \n weight_begin_addr=0, \n bias_begin_addr=0, \n quant_q_in=q_in2, \n quant_q_out=q_out2 \n )\n\n big_addr = nxt_big(big_addr+in_chan*4*4/2)\n small_addr = nxt_small(small_addr+in_chan*4*4/4)\n when(state===(num_stages).U){\n paras.set_copy_reader1(reader1, 1)\n paras.set_copy_reader2(reader2, 1)\n paras.set_copy_read_pack(read_pack)\n paras.set_copy_switch(read_switch)\n paras.set_unuse_accu(accu)\n paras.set_quant(quant)\n paras.set_write_alar(writer, 0, in_chan-1)\n counter.set((in_chan*4*4-1).U)\n state := (num_stages+1).U\n }\n num_stages += 1\n when(state===(num_stages).U){\n when(writer.valid_out){\n when(counter.inc()){\n state := (num_stages+1).U\n }\n }\n reader1.valid_in := true.B\n reader2.valid_in := true.B\n }\n num_stages += 1\n when(state===(num_stages).U){\n paras2.set_copy_reader1(reader1, 1)\n paras2.set_copy_reader2(reader2, 1)\n paras2.set_copy_read_pack(read_pack)\n paras2.set_conv_read_switch(read_switch)\n paras2.set_unuse_accu(accu)\n paras2.set_quant(quant)\n paras2.set_write_alar(writer, in_chan, 2*in_chan-1)\n counter.set((in_chan*4*4-1).U)\n state := (num_stages+1).U\n }\n num_stages += 1\n when(state===(num_stages).U){\n when(writer.valid_out){\n when(counter.inc()){\n state := (num_stages+1).U\n }\n }\n reader1.valid_in := true.B\n reader2.valid_in := true.B\n calc8x8.flag := CalcType.empty\n }\n num_stages += 1\n }\n\n\n def CONV(w: Int, h: Int, in_chan: Int, out_chan: Int, conv_q_in: Int, \n conv_q_out: Int): Unit = {\n val paras = GenAllPara(addr_w=StdPara.addr_w, h_w=StdPara.h_w, c_w=StdPara.c_w, id_w=StdPara.id_w, big_w=StdPara.big_w, \n width=w, \n height=h, \n wr_width=w, \n wr_height=h,\n in_chan=in_chan, \n out_chan=out_chan,\n para_num=StdPara.para_num, \n mask=StdPara.mask,\n big_begin_addr=big_addr, \n big_max_addr=StdPara.big_max_addr, \n big_min_addr=StdPara.big_min_addr, \n wr_big_begin_addr=nxt_big(big_addr+in_chan*w*h/2), \n wr_big_max_addr=StdPara.big_max_addr, \n wr_big_min_addr=StdPara.big_min_addr, \n small_begin_addr=small_addr, \n small_max_addr=StdPara.small_max_addr, \n small_min_addr=StdPara.small_min_addr, \n wr_small_begin_addr=nxt_small(small_addr+in_chan*w*h/4), \n wr_small_max_addr=StdPara.small_max_addr, \n wr_small_min_addr=StdPara.small_min_addr, \n weight_begin_addr=weight_addr, \n bias_begin_addr=bias_addr, \n quant_q_in=conv_q_in, \n quant_q_out=conv_q_out \n )\n big_addr = nxt_big(big_addr+in_chan*w*h/2)\n small_addr = nxt_small(small_addr+in_chan*w*h/4)\n weight_addr += in_chan*out_chan/StdPara.para_num\n bias_addr += out_chan/StdPara.para_num\n\n when(state===(num_stages).U){\n paras.set_conv_reader1(reader1)\n paras.set_conv_reader2(reader2)\n paras.set_read_weight(read_weight)\n paras.set_conv_read_pack(read_pack)\n paras.set_conv_accu(accu)\n paras.set_quant(quant)\n paras.set_write(writer)\n paras.set_conv_read_switch(read_switch)\n\n counter.set((out_chan*w*h-1).U)\n state := (num_stages+1).U\n }\n num_stages += 1\n when(state===(num_stages).U){\n when(writer.valid_out){\n when(counter.inc()){\n state := (num_stages+1).U\n }\n }\n reader1.valid_in := true.B\n reader2.valid_in := true.B\n read_weight.valid_in := true.B\n calc8x8.flag := CalcType.calcConv\n calc8x8.mask := paras.mask.U\n }\n num_stages += 1\n }\n\n def CONV1(w: Int, h: Int, in_chan: Int, out_chan: Int, conv_q_in: Int, \n conv_q_out: Int): Unit = {\n val paras = GenAllPara(addr_w=StdPara.addr_w, h_w=StdPara.h_w, c_w=StdPara.c_w, id_w=StdPara.id_w, big_w=StdPara.big_w, \n width=w, \n height=h, \n wr_width=w, \n wr_height=h,\n in_chan=in_chan, \n out_chan=out_chan,\n para_num=StdPara.para_num, \n mask=StdPara.mask,\n big_begin_addr=StdPara.big_conv0_addr, \n big_max_addr=StdPara.big_global_addr, \n big_min_addr=0, \n wr_big_begin_addr=big_addr, \n wr_big_max_addr=StdPara.big_max_addr, \n wr_big_min_addr=StdPara.big_min_addr, \n small_begin_addr=StdPara.small_conv0_addr, \n small_max_addr=StdPara.small_global_addr, \n small_min_addr=0, \n wr_small_begin_addr=small_addr, \n wr_small_max_addr=StdPara.small_max_addr, \n wr_small_min_addr=StdPara.small_min_addr, \n weight_begin_addr=weight_addr, \n bias_begin_addr=bias_addr, \n quant_q_in=conv_q_in, \n quant_q_out=conv_q_out \n )\n weight_addr += in_chan*out_chan/StdPara.para_num\n bias_addr += out_chan/StdPara.para_num\n\n when(state===(num_stages).U){\n paras.set_conv_reader1(reader1)\n paras.set_conv_reader2(reader2)\n paras.set_read_weight(read_weight)\n paras.set_conv_read_pack(read_pack)\n paras.set_conv_accu(accu)\n paras.set_quant(quant)\n paras.set_write(writer)\n paras.set_conv_read_switch(read_switch)\n\n calc8x8.mask := paras.mask.U\n counter.set((out_chan*w*h-1).U)\n state := (num_stages+1).U\n }\n num_stages += 1\n when(state===(num_stages).U){\n when(writer.valid_out){\n when(counter.inc()){\n state := (num_stages+1).U\n }\n }\n reader1.valid_in := true.B\n reader2.valid_in := true.B\n read_weight.valid_in := true.B\n calc8x8.flag := CalcType.calcConv\n calc8x8.mask := paras.mask.U\n }\n num_stages += 1\n }\n\n def RELU0(w: Int, h: Int, in_chan: Int, relu_q_in: Int, relu_q_out: Int): Unit = {\n val paras = GenAllPara(addr_w=StdPara.addr_w, h_w=StdPara.h_w, c_w=StdPara.c_w, id_w=StdPara.id_w, big_w=StdPara.big_w, \n width=w, \n height=h, \n wr_width=w, \n wr_height=h,\n in_chan=in_chan, \n out_chan=in_chan,\n para_num=1, \n mask=1,\n big_begin_addr=big_addr, \n big_max_addr=StdPara.big_max_addr, \n big_min_addr=StdPara.big_min_addr, \n wr_big_begin_addr=StdPara.big_conv0_addr, \n wr_big_max_addr=StdPara.big_global_addr, \n wr_big_min_addr=0, \n small_begin_addr=small_addr, \n small_max_addr=StdPara.small_max_addr, \n small_min_addr=StdPara.small_min_addr, \n wr_small_begin_addr=StdPara.small_conv0_addr,\n wr_small_max_addr=StdPara.small_global_addr,\n wr_small_min_addr=0,\n weight_begin_addr=0, \n bias_begin_addr=0, \n quant_q_in=relu_q_in, \n quant_q_out=relu_q_out \n )\n\n when(state===(num_stages).U){\n paras.set_copy_reader1(reader1, 1)\n paras.set_copy_reader2(reader2, 1)\n paras.set_copy_read_pack(read_pack)\n paras.set_conv_read_switch(read_switch)\n paras.set_unuse_accu(accu)\n paras.set_quant(quant)\n paras.set_write(writer)\n counter.set((in_chan*w*h-1).U)\n state := (num_stages+1).U\n }\n num_stages += 1\n when(state===(num_stages).U){\n when(writer.valid_out){\n when(counter.inc()){\n state := (num_stages+1).U\n }\n }\n reader1.valid_in := true.B\n reader2.valid_in := true.B\n calc8x8.flag := CalcType.leakyReLU\n }\n num_stages += 1\n }\n\n def RELU1(w: Int, h: Int, in_chan: Int, relu_q_in: Int, relu_q_out: Int): Unit = {\n val paras = GenAllPara(addr_w=StdPara.addr_w, h_w=StdPara.h_w, c_w=StdPara.c_w, id_w=StdPara.id_w, big_w=StdPara.big_w, \n width=w, \n height=h, \n wr_width=w, \n wr_height=h,\n in_chan=in_chan, \n out_chan=in_chan,\n para_num=1, \n mask=1,\n big_begin_addr=big_addr, \n big_max_addr=StdPara.big_max_addr, \n big_min_addr=StdPara.big_min_addr, \n wr_big_begin_addr=StdPara.big_conv1_addr, \n wr_big_max_addr=StdPara.big_global_addr, \n wr_big_min_addr=0, \n small_begin_addr=small_addr, \n small_max_addr=StdPara.small_max_addr, \n small_min_addr=StdPara.small_min_addr, \n wr_small_begin_addr=StdPara.small_conv1_addr,\n wr_small_max_addr=StdPara.small_global_addr,\n wr_small_min_addr=0,\n weight_begin_addr=0, \n bias_begin_addr=0, \n quant_q_in=relu_q_in, \n quant_q_out=relu_q_out \n )\n\n when(state===(num_stages).U){\n paras.set_copy_reader1(reader1, 1)\n paras.set_copy_reader2(reader2, 1)\n paras.set_copy_read_pack(read_pack)\n paras.set_conv_read_switch(read_switch)\n paras.set_unuse_accu(accu)\n paras.set_quant(quant)\n paras.set_write(writer)\n counter.set((in_chan*w*h-1).U)\n state := (num_stages+1).U\n }\n num_stages += 1\n when(state===(num_stages).U){\n when(writer.valid_out){\n when(counter.inc()){\n state := (num_stages+1).U\n }\n }\n reader1.valid_in := true.B\n reader2.valid_in := true.B\n calc8x8.flag := CalcType.leakyReLU\n }\n num_stages += 1\n }\n\n def RELU(w: Int, h: Int, in_chan: Int, relu_q_in: Int, relu_q_out: Int): Unit = {\n val paras = GenAllPara(addr_w=StdPara.addr_w, h_w=StdPara.h_w, c_w=StdPara.c_w, id_w=StdPara.id_w, big_w=StdPara.big_w, \n width=w, \n height=h, \n wr_width=w, \n wr_height=h,\n in_chan=in_chan, \n out_chan=in_chan,\n para_num=StdPara.para_num, \n mask=StdPara.mask,\n big_begin_addr=big_addr, \n big_max_addr=StdPara.big_max_addr, \n big_min_addr=StdPara.big_min_addr, \n wr_big_begin_addr=nxt_big(big_addr+in_chan*w*h/2), \n wr_big_max_addr=StdPara.big_max_addr, \n wr_big_min_addr=StdPara.big_min_addr, \n small_begin_addr=small_addr, \n small_max_addr=StdPara.small_max_addr, \n small_min_addr=StdPara.small_min_addr, \n wr_small_begin_addr=nxt_small(small_addr+in_chan*w*h/4), \n wr_small_max_addr=StdPara.small_max_addr, \n wr_small_min_addr=StdPara.small_min_addr, \n weight_begin_addr=0, \n bias_begin_addr=0, \n quant_q_in=relu_q_in, \n quant_q_out=relu_q_out \n )\n\n big_addr = nxt_big(big_addr+in_chan*w*h/2)\n small_addr = nxt_small(small_addr+in_chan*w*h/4)\n when(state===(num_stages).U){\n paras.set_copy_reader1(reader1, 1)\n paras.set_copy_reader2(reader2, 1)\n paras.set_copy_read_pack(read_pack)\n paras.set_conv_read_switch(read_switch)\n paras.set_unuse_accu(accu)\n paras.set_quant(quant)\n paras.set_write(writer)\n counter.set((in_chan*w*h-1).U)\n state := (num_stages+1).U\n }\n num_stages += 1\n when(state===(num_stages).U){\n when(writer.valid_out){\n when(counter.inc()){\n state := (num_stages+1).U\n }\n }\n reader1.valid_in := true.B\n reader2.valid_in := true.B\n calc8x8.flag := CalcType.leakyReLU\n }\n num_stages += 1\n }\n\n def MAXPOOL(w: Int, h: Int, in_chan: Int): Unit = {\n val paras = GenAllPara(addr_w=StdPara.addr_w, h_w=StdPara.h_w, c_w=StdPara.c_w, id_w=StdPara.id_w, big_w=StdPara.big_w, \n width=w, \n height=h, \n wr_width=w/2, \n wr_height=h/2,\n in_chan=in_chan, \n out_chan=in_chan,\n para_num=1, \n mask=0,\n big_begin_addr=StdPara.big_conv1_addr, \n big_max_addr=StdPara.big_global_addr, \n big_min_addr=0, \n wr_big_begin_addr=big_addr, \n wr_big_max_addr=StdPara.big_max_addr, \n wr_big_min_addr=StdPara.big_min_addr, \n small_begin_addr=StdPara.small_conv1_addr, \n small_max_addr=StdPara.small_global_addr, \n small_min_addr=0, \n wr_small_begin_addr=small_addr, \n wr_small_max_addr=StdPara.small_max_addr, \n wr_small_min_addr=StdPara.small_min_addr, \n weight_begin_addr=0, \n bias_begin_addr=0, \n quant_q_in=0, \n quant_q_out=0 \n )\n\n when(state===(num_stages).U){\n paras.set_maxp_reader1(reader1)\n paras.set_maxp_reader2(reader2)\n paras.set_write(writer)\n paras.set_maxpool_switch(read_switch)\n counter.set((in_chan*w*h/4-1).U)\n\n state := (num_stages+1).U\n }\n num_stages += 1\n when(state===(num_stages).U){\n when(writer.valid_out){\n when(counter.inc()){\n state := (num_stages+1).U\n }\n }\n reader1.valid_in := true.B\n reader2.valid_in := true.B\n }\n num_stages += 1\n }\n\n def UPS(w: Int, h: Int, in_chan: Int): Unit = {\n val paras = GenAllPara(addr_w=StdPara.addr_w, h_w=StdPara.h_w, c_w=StdPara.c_w, id_w=StdPara.id_w, big_w=StdPara.big_w, \n width=w, \n height=h, \n wr_width=w*2, \n wr_height=h*2,\n in_chan=in_chan, \n out_chan=in_chan,\n para_num=StdPara.para_num, \n mask=StdPara.mask,\n big_begin_addr=big_addr, \n big_max_addr=StdPara.big_max_addr, \n big_min_addr=StdPara.big_min_addr, \n wr_big_begin_addr=nxt_big(big_addr+in_chan*w*h/2), \n wr_big_max_addr=StdPara.big_max_addr, \n wr_big_min_addr=StdPara.big_min_addr, \n small_begin_addr=small_addr, \n small_max_addr=StdPara.small_max_addr, \n small_min_addr=StdPara.small_min_addr, \n wr_small_begin_addr=nxt_small(small_addr+in_chan*w*h/4), \n wr_small_max_addr=StdPara.small_max_addr, \n wr_small_min_addr=StdPara.small_min_addr, \n weight_begin_addr=0, \n bias_begin_addr=0, \n quant_q_in=0, \n quant_q_out=0 \n )\n\n big_addr = nxt_big(big_addr+in_chan*w*h/2)\n small_addr = nxt_small(small_addr+in_chan*w*h/4)\n\n when(state===(num_stages).U){\n paras.set_ups_reader1(reader1)\n paras.set_ups_reader2(reader2)\n paras.set_ups_read_pack(read_pack)\n paras.set_write(writer)\n paras.set_ups_switch(read_switch)\n counter.set((in_chan*w*h*4-1).U)\n\n state := (num_stages+1).U\n }\n num_stages += 1\n when(state===(num_stages).U){\n when(writer.valid_out){\n when(counter.inc()){\n state := (num_stages+1).U\n }\n }\n reader1.valid_in := true.B\n reader2.valid_in := true.B\n }\n num_stages += 1\n }\n\n def LAST_PRINT(w: Int, h: Int, in_chan: Int): Unit = {\n val lst_counter = RegInit(0.U.asTypeOf(ACounter(16.W)))\n val lst_64_counter = RegInit(0.U.asTypeOf(ACounter(16.W)))\n val paras_print = GenAllPara(StdPara.addr_w, StdPara.h_w, StdPara.c_w, StdPara.id_w, big_w=StdPara.big_w, \n w, h, w, h, \n in_chan, 1,\n 1, 0,\n big_addr, StdPara.big_max_addr, StdPara.big_min_addr,\n // StdPara.big_conv1_addr, 899, 0,\n 0, 0, 0,\n small_addr, StdPara.small_max_addr, StdPara.small_min_addr,\n // StdPara.small_conv1_addr, 449, 0,\n 0, 0, 0,\n 0, 0, 0, 0\n )\n when(state===(num_stages).U){\n state := (num_stages+1).U\n paras_print.set_conv_reader1(reader1)\n paras_print.set_conv_reader2(reader2)\n paras_print.set_conv_read_pack(read_pack)\n read_switch.flag_job := true.B\n read_switch.job := ReadSwitchType.idle\n lst_64_counter.set(63.U)\n lst_counter.set((w*h*in_chan-1).U)\n }\n when(state===(num_stages+1).U){\n reader1.valid_in := true.B\n reader2.valid_in := true.B\n state := (num_stages+2).U\n }\n when(state===(num_stages+2).U){\n state := (num_stages+3).U\n }\n when(state===(num_stages+3).U){\n when(lst_64_counter.inc()){\n when(lst_counter.inc()){\n state := (num_stages+4).U\n }\n }.elsewhen(lst_64_counter.ccnt===62.U){\n reader1.valid_in := true.B\n reader2.valid_in := true.B \n }\n when(read_pack.valid_out){\n io.complete := true.B\n io.valid := true.B\n io.output := read_pack.output.mat(0)\n for(i <- 0 to 62)\n output_cache(i) := read_pack.output.mat(i+1)\n }.otherwise{\n io.valid := true.B\n io.output := output_cache(0)\n for(i <- 0 to 62)\n output_cache(i) := output_cache(i+1)\n }\n }\n when(state===(num_stages+4).U){\n state := (num_stages+4).U\n io.complete_output := true.B\n }\n num_stages += 5\n }\n\n def CHECK_PRINT(): Unit = {\n when(io.valid){\n checksum := checksum^io.output.asUInt\n }\n io.checksum := checksum\n }\n}", "groundtruth": " val rom_bias = if(StdPara.para_num==4) Module(new ROMBias(StdPara.para_num)).io else Module(new ROMHalfBias(StdPara.para_num)).io\n", "crossfile_context": "", "category": "Design Structure", "subcategory": "Hierarchical Composition", "confidence": 0.7, "category_reason": "Module instantiation"} {"task_id": "fpga_final_project", "path": "fpga_final_project/src/main/scala/top/wrapper.scala", "left_context": "package final_project\n\nimport chisel3._\nimport chisel3.util._\n\nimport chisel3.experimental.BundleLiterals._\n\nclass Wrapper extends Module{\n val io = IO(new Bundle{\n val raw_bram_addr = Output(UInt(32.W))\n val rgb_bram_wr_en = Output(Bool())\n val rgb_bram_addr = Output(UInt(12.W))\n val rgb_bram_data = Output(UInt(24.W))\n val raw_bram_data = Input(UInt(32.W))\n })\n\n val quant_in = 4\n\n val top = Module(new FinalTop).io\n val sigmoid = Module(new Sigmoid).io\n sigmoid.valid_in := top.valid\n sigmoid.input := top.output\n\n top.input := 0.S\n top.valid_in := false.B\n top.start := true.B\n\n io.raw_bram_addr := 0.U\n io.rgb_bram_wr_en := false.B\n io.rgb_bram_addr := 0.U\n io.rgb_bram_data := 0.U\n\n val in_state = RegInit(0.U(2.W))\n val raw_addr = RegInit(0.U(20.W))\n val raw_addr_0 = RegInit(false.B)\n val in_w = RegInit(0.U.asTypeOf(ACounter(2.W)))\n val in_h = RegInit(0.U.asTypeOf(ACounter(2.W)))\n val in_chan = RegInit(0.U.asTypeOf(ACounter(2.W)))\n val x = RegInit(0.U.asTypeOf(ACounter(3.W)))\n val y = RegInit(0.U.asTypeOf(ACounter(3.W)))\n \n switch(in_state){\n is(0.U){\n when(top.complete){\n in_state := 1.U\n }\n io.raw_bram_addr := 0.U\n in_w.set(3.U)\n in_h.set(3.U)\n in_chan.set(3.U)\n x.set(7.U)\n y.set(2.U, 7.U)\n // raw_addr := Cat(in_chan.ccnt, y.ccnt, in_h.ccnt, x.ccnt, in_w.ccnt)\n raw_addr := 4.U\n raw_addr_0 := false.B\n }\n is(1.U){\n when(y.inc()){\n when(x.inc()){\n when(in_chan.inc()){\n when(in_w.inc()){\n when(in_h.inc()){\n in_state := 2.U\n }\n }\n }\n }\n }\n // raw_addr := ((in_w.ccnt*8+x.ccnt)*32+(in_h.ccnt*8+y.ccnt))*2+(in_chan.ccnt>>1.U)\n // raw_addr := Cat(in_chan.ccnt, y.ccnt, in_h.ccnt, x.ccnt, in_w.ccnt)\n raw_addr := Cat(in_w.ccnt, x.ccnt, in_h.ccnt, y.ccnt, in_chan.ccnt)\n raw_addr_0 := raw_addr(0)\n io.raw_bram_addr := (raw_addr >> 1.U) << 2.U // (AXI32)\n top.input := Cat(0.U(1.W), Mux(raw_addr_0, io.raw_bram_data(7, 0).asUInt, io.raw_bram_data(15, 8).asUInt) << quant_in.U).asSInt\n top.valid_in := true.B\n }\n is(2.U){\n io.raw_bram_addr := (raw_addr >> 1.U) << 2.U\n top.input := Cat(0.U(1.W), Mux(raw_addr_0, io.raw_bram_data(7, 0).asUInt, io.raw_bram_data(15, 8).asUInt) << quant_in.U).asSInt\n top.valid_in := true.B\n when(top.complete_output){\n in_state := 0.U\n }.otherwise{\n in_state := 3.U\n }\n }\n is(3.U){\n when(top.complete_output){\n in_state := 0.U\n }\n }\n }\n\n val out_state = RegInit(0.U(3.W))\n val out_reg = RegInit(VecInit(Seq.fill(64)(0.U(24.W))))\n val out_64_counter = RegInit(0.U.asTypeOf(ACounter(6.W)))\n \n val out_w = RegInit(0.U.asTypeOf(ACounter(3.W)))\n val out_h = RegInit(0.U.asTypeOf(ACounter(3.W)))\n val out_x = RegInit(0.U.asTypeOf(ACounter(3.W)))\n val out_y = RegInit(0.U.asTypeOf(ACounter(3.W)))\n for(i <- 0 to 62)\n out_reg(i) := out_reg(i+1)\n \n switch(out_state){\n is(0.U){\n when(sigmoid.valid_out){\n out_state := 1.U\n }\n out_reg(63) := Cat(sigmoid.output, 0.U(16.W))\n out_w.set(7.U)\n out_h.set(7.U)\n out_x.set(7.U)\n out_y.set(7.U)\n out_64_counter.set(1.U, 63.U)\n }\n is(6.U){\n when(sigmoid.valid_out){\n out_state := 1.U\n }.otherwise{\n out_state := 0.U\n }\n out_reg(63) := Cat(sigmoid.output, 0.U(16.W))\n out_64_counter.set(1.U, 63.U)\n }\n is(1.U){\n when(out_64_counter.inc()){\n out_state := 2.U\n }\n out_reg(63) := Cat(sigmoid.output, 0.U(16.W))\n }\n is(2.U){\n when(out_64_counter.inc()){\n out_state := 3.U\n }\n out_reg(63) := Cat(out_reg(0)(23, 16), sigmoid.output, 0.U(8.W))\n }\n is(3.U){\n", "right_context": " is(5.U){\n when(out_y.inc()){\n when(out_x.inc()){\n out_state := 6.U\n when(out_h.inc()){\n out_w.inc()\n }\n }\n }\n // io.rgb_bram_addr := Cat(out_y.ccnt, out_h.ccnt, out_x.ccnt, out_w.ccnt)\n io.rgb_bram_addr := Cat(out_h.ccnt, out_x.ccnt, out_w.ccnt, out_y.ccnt)\n io.rgb_bram_data := out_reg(0)\n io.rgb_bram_wr_en := true.B\n }\n }\n \n} ", "groundtruth": " when(out_64_counter.inc()){\n out_state := 5.U\n }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "fpga_final_project", "path": "fpga_final_project/src/main/scala/utils/para.scala", "left_context": "package final_project\n\nimport chisel3._\nimport chisel3.experimental.ChiselEnum\n\n\nclass GenAllPara(val addr_w: Int, val h_w: Int, val c_w: Int, val id_w: Int, big_w: Int){\n var width = 0\n var height = 0\n var wr_width = 0\n var wr_height = 0\n var in_chan = 0\n var out_chan = 0\n var bank_id_big = Array[Int]()\n var bank_id_small = Array[Array[Int]]()\n var para_num = 0\n var mask = 0\n var big_begin_addr = 0\n var big_max_addr = 0\n var big_min_addr = 0\n var wr_big_begin_addr = 0\n var wr_big_max_addr = 0\n var wr_big_min_addr = 0\n var small_begin_addr = 0\n var small_max_addr = 0\n var small_min_addr = 0\n var wr_small_begin_addr = 0\n var wr_small_max_addr = 0\n var wr_small_min_addr = 0\n var weight_begin_addr = 0\n var bias_begin_addr = 0\n var quant_q_in = 0\n var quant_q_out = 0\n def set_conv_reader1(reader1: GraphReaderBundle): Bundle = {\n val (loop_num, loop_h) = (2*out_chan/para_num, 1)\n val begin_loop_num1 = out_chan/para_num\n reader1.flag_job := true.B\n reader1.job_type := ReadType.toConvOrCopy\n \n reader1.job := GenConvReadJob.gen(\n addr_w, h_w, c_w, id_w, big_w, \n loop_num, begin_loop_num1, loop_h,\n height/2, width, in_chan, \n big_begin_addr, big_min_addr, big_max_addr,\n small_begin_addr, small_min_addr, small_max_addr,\n bank_id_big(0), bank_id_small(0)\n )\n\n return reader1\n }\n\n def set_conv_reader2(reader2: GraphReaderBundle): Bundle = {\n val (loop_num, loop_h) = (2*out_chan/para_num, 1)\n val begin_loop_num2 = 0\n\n reader2.flag_job := true.B\n reader2.job_type := ReadType.toConvOrCopy\n\n reader2.job := GenConvReadJob.gen(\n addr_w, h_w, c_w, id_w, big_w, \n loop_num, begin_loop_num2, loop_h,\n height/2, width, in_chan, \n big_begin_addr, big_min_addr, big_max_addr,\n small_begin_addr, small_min_addr, small_max_addr,\n bank_id_big(1), bank_id_small(1)\n )\n\n return reader2\n }\n\n def set_copy_reader1(reader1: GraphReaderBundle, copy_cnt: Int): Bundle = {\n val (loop_num, loop_h) = (2, copy_cnt)\n val begin_loop_num1 = 1\n reader1.flag_job := true.B\n reader1.job_type := ReadType.toConvOrCopy\n \n reader1.job := GenConvReadJob.gen(\n addr_w, h_w, c_w, id_w, big_w, \n loop_num, begin_loop_num1, loop_h,\n height/2, width, in_chan, \n big_begin_addr, big_min_addr, big_max_addr,\n small_begin_addr, small_min_addr, small_max_addr,\n bank_id_big(0), bank_id_small(0)\n )\n\n return reader1\n }\n\n def set_copy_reader2(reader2: GraphReaderBundle, copy_cnt: Int): Bundle = {\n val (loop_num, loop_h) = (2, copy_cnt)\n val begin_loop_num2 = 0\n\n reader2.flag_job := true.B\n reader2.job_type := ReadType.toConvOrCopy\n\n reader2.job := GenConvReadJob.gen(\n addr_w, h_w, c_w, id_w, big_w, \n loop_num, begin_loop_num2, loop_h,\n height/2, width, in_chan, \n big_begin_addr, big_min_addr, big_max_addr,\n small_begin_addr, small_min_addr, small_max_addr,\n bank_id_big(1), bank_id_small(1)\n )\n\n return reader2\n }\n\n def set_ups_reader1(reader1: GraphReaderBundle): Bundle = {\n val (loop_num, loop_h) = (4, 2)\n val begin_loop_num1 = 2\n reader1.flag_job := true.B\n reader1.job_type := ReadType.toConvOrCopy\n \n reader1.job := GenConvReadJob.gen(\n addr_w, h_w, c_w, id_w, big_w, \n loop_num, begin_loop_num1, loop_h,\n height/2, width, in_chan, \n big_begin_addr, big_min_addr, big_max_addr,\n small_begin_addr, small_min_addr, small_max_addr,\n bank_id_big(0), bank_id_small(0)\n )\n\n return reader1\n }\n\n def set_ups_reader2(reader2: GraphReaderBundle): Bundle = {\n val (loop_num, loop_h) = (4, 2)\n val begin_loop_num2 = 0\n\n reader2.flag_job := true.B\n reader2.job_type := ReadType.toConvOrCopy\n\n reader2.job := GenConvReadJob.gen(\n addr_w, h_w, c_w, id_w, big_w, \n loop_num, begin_loop_num2, loop_h,\n height/2, width, in_chan, \n big_begin_addr, big_min_addr, big_max_addr,\n small_begin_addr, small_min_addr, small_max_addr,\n bank_id_big(1), bank_id_small(1)\n )\n\n return reader2\n }\n\n def set_copy_reader1_job2(reader1: GraphReaderBundle, copy_cnt: Int): Bundle = {\n val (loop_num, loop_h) = (2, copy_cnt)\n val begin_loop_num1 = 1\n \n reader1.job2 := GenConvReadJob.gen(\n addr_w, h_w, c_w, id_w, big_w, \n loop_num, begin_loop_num1, loop_h,\n height/2, width, in_chan, \n big_begin_addr, big_min_addr, big_max_addr,\n small_begin_addr, small_min_addr, small_max_addr,\n bank_id_big(0), bank_id_small(0)\n )\n\n return reader1\n }\n\n def set_copy_reader2_job2(reader2: GraphReaderBundle, copy_cnt: Int): Bundle = {\n val (loop_num, loop_h) = (2, copy_cnt)\n val begin_loop_num2 = 0\n\n reader2.job2 := GenConvReadJob.gen(\n addr_w, h_w, c_w, id_w, big_w, \n loop_num, begin_loop_num2, loop_h,\n height/2, width, in_chan, \n big_begin_addr, big_min_addr, big_max_addr,\n small_begin_addr, small_min_addr, small_max_addr,\n bank_id_big(1), bank_id_small(1)\n )\n\n return reader2\n }\n\n def set_maxp_reader1(reader1: GraphReaderBundle): Bundle = {\n reader1.flag_job := true.B\n reader1.job_type := ReadType.toMaxp\n val bank_id_small0 = Array[Int](bank_id_small(0)(3), bank_id_small(0)(2), bank_id_small(0)(1), bank_id_small(0)(0))\n \n reader1.job := GenMaxpReadJob.gen(\n addr_w, h_w, c_w, id_w, big_w, \n 1, 1, 1,\n height/2, width, in_chan, \n big_begin_addr, big_min_addr, big_max_addr,\n small_begin_addr, small_min_addr, small_max_addr,\n bank_id_big(0), bank_id_small0\n )\n\n return reader1\n }\n\n def set_maxp_reader2(reader2: GraphReaderBundle): Bundle = {\n\n reader2.flag_job := true.B\n reader2.job_type := ReadType.toMaxp\n val bank_id_small1 = Array[Int](bank_id_small(1)(3), bank_id_small(1)(2), bank_id_small(1)(1), bank_id_small(1)(0))\n \n reader2.job := GenMaxpReadJob.gen(\n addr_w, h_w, c_w, id_w, big_w, \n 1, 1, 1,\n height/2, width, in_chan, \n big_begin_addr, big_min_addr, big_max_addr,\n small_begin_addr, small_min_addr, small_max_addr,\n bank_id_big(1), bank_id_small1\n )\n\n return reader2\n }\n\n def set_read_weight(rw: WeightReaderBundle): Bundle = {\n rw.flag_job := true.B\n val weight_end_addr = weight_begin_addr+in_chan*out_chan/para_num-1\n rw.begin_addr := weight_begin_addr.U\n rw.addr_end := weight_end_addr.U\n return rw\n }\n\n def set_conv_read_pack(rp: PackReadDataBundle): Bundle = {\n rp.flag_job := true.B\n rp.job := GenPackJob.gen(addr_w, h_w, c_w, big_w, width-1, height-1, in_chan*out_chan/para_num-1, in_chan-1)\n return rp\n }\n\n def set_copy_read_pack(rp: PackReadDataBundle): Bundle = {\n rp.flag_job := true.B\n rp.job := GenPackJob.gen(addr_w, h_w, c_w, big_w, width-1, height-1, in_chan-1, in_chan-1)\n return rp\n }\n\n def set_ups_read_pack(rp: PackReadDataBundle): Bundle = {\n rp.flag_job := true.B\n rp.job := GenPackJob.gen(addr_w, h_w, c_w, big_w, width-1, height-1, in_chan*2-1, in_chan-1)\n return rp\n }\n\n def set_conv_read_switch(rs: ReadSwitchBundle): Bundle = {\n rs.flag_job := true.B\n rs.job := ReadSwitchType.toConv\n return rs\n }\n\n def set_maxpool_switch(rs: ReadSwitchBundle): Bundle = {\n rs.flag_job := true.B\n rs.job := ReadSwitchType.toMaxp\n return rs\n }\n\n def set_copy_switch(rs: ReadSwitchBundle): Bundle = {\n rs.flag_job := true.B\n rs.job := ReadSwitchType.toCopy\n return rs\n }\n \n\n \n def set_mult_switch(rs: ReadSwitchBundle): Bundle = {\n rs.flag_job := true.B\n rs.job := ReadSwitchType.toMult2\n return rs\n }\n\n def set_ups_switch(rs: ReadSwitchBundle): Bundle = {\n rs.flag_job := true.B\n rs.job := ReadSwitchType.toUps\n rs.in_h := (height*2-1).U\n rs.in_chan := (in_chan-1).U\n return rs\n }\n\n def set_conv_accu(ac: AccumuBundle): Bundle = {\n ac.flag_job := true.B\n ac.csum := (in_chan-1).U\n ac.is_in_use := true.B\n val bias_end_addr = bias_begin_addr+out_chan/para_num-1\n ac.bias_begin_addr := bias_begin_addr.U\n ac.bias_end_addr := bias_end_addr.U\n return ac\n }\n\n def set_unuse_accu(ac: AccumuBundle): Bundle = {\n ac.flag_job := true.B\n ac.is_in_use := false.B\n return ac\n }\n\n def set_quant(q: QuantBundle): Bundle = {\n q.flag_job := true.B\n q.quant_in := (quant_q_in-quant_q_out).U\n return q\n }\n\n def set_write_alar(wr: RealWriterBundle, al: Int, ar: Int): Bundle = {\n wr.flag_job := true.B\n", "right_context": " val bank_id_small0 = Array[Int](bank_id_small(0)(1), bank_id_small(0)(2), bank_id_small(0)(3), bank_id_small(0)(0))\n val bank_id_small1 = Array[Int](bank_id_small(1)(1), bank_id_small(1)(2), bank_id_small(1)(3), bank_id_small(1)(0))\n wr.job.job(0) := GenWriteConvJob.gen(\n addr_w, h_w, c_w, id_w,\n wr_height/2, wr_width, out_chan, \n wr_big_begin_addr, wr_big_min_addr, wr_big_max_addr,\n wr_small_begin_addr, wr_small_min_addr, wr_small_max_addr,\n bank_id_big(0), bank_id_small0, al, ar\n )\n wr.job.job(1) := GenWriteConvJob.gen(\n addr_w, h_w, c_w, id_w,\n wr_height/2, wr_width, out_chan, \n wr_big_begin_addr, wr_big_min_addr, wr_big_max_addr,\n wr_small_begin_addr, wr_small_min_addr, wr_small_max_addr,\n bank_id_big(1), bank_id_small1, al, ar\n )\n wr.job.out_chan := (ar-al).U\n return wr\n }\n\n def set_write(wr: RealWriterBundle): Bundle = {\n return set_write_alar(wr, 0, out_chan-1)\n }\n}\n\nobject GenAllPara{\n def apply(\n addr_w: Int, \n h_w: Int, \n c_w: Int, \n id_w: Int,\n big_w: Int,\n width: Int,\n height: Int,\n wr_width: Int,\n wr_height: Int,\n in_chan: Int,\n out_chan: Int,\n para_num: Int,\n mask: Int,\n big_begin_addr: Int,\n big_max_addr: Int,\n big_min_addr: Int,\n wr_big_begin_addr: Int,\n wr_big_max_addr: Int,\n wr_big_min_addr: Int,\n small_begin_addr: Int,\n small_max_addr: Int,\n small_min_addr: Int,\n wr_small_begin_addr: Int,\n wr_small_max_addr: Int,\n wr_small_min_addr: Int,\n weight_begin_addr: Int,\n bias_begin_addr: Int,\n quant_q_in: Int,\n quant_q_out: Int\n ): GenAllPara = {\n val ret = new GenAllPara(addr_w, h_w, c_w, id_w, big_w)\n ret.width = width\n ret.height = height\n ret.wr_width = wr_width\n ret.wr_height = wr_height\n ret.in_chan = in_chan\n ret.out_chan = out_chan\n ret.bank_id_big = Array(1<<0, 1<<1)\n ret.bank_id_small = Array(Array(1<<3, 1<<0, 1<<1, 1<<2), Array(1<<7, 1<<4, 1<<5, 1<<6))\n ret.para_num = para_num\n ret.big_begin_addr = big_begin_addr\n ret.big_max_addr = big_max_addr\n ret.big_min_addr = big_min_addr\n ret.wr_big_begin_addr = wr_big_begin_addr\n ret.wr_big_max_addr = wr_big_max_addr\n ret.wr_big_min_addr = wr_big_min_addr\n ret.small_begin_addr = small_begin_addr\n ret.small_max_addr = small_max_addr\n ret.small_min_addr = small_min_addr\n ret.wr_small_begin_addr = wr_small_begin_addr\n ret.wr_small_max_addr = wr_small_max_addr\n ret.wr_small_min_addr = wr_small_min_addr\n ret.weight_begin_addr = weight_begin_addr\n ret.bias_begin_addr = bias_begin_addr\n ret.quant_q_in = quant_q_in\n ret.quant_q_out = quant_q_out\n ret.mask = mask\n return ret\n }\n}\n\nobject StdPara{\n val w = 16\n val big_bank_w = 768\n val big_bank_addr_w = 10\n val big_global_size = 1024\n val small_bank_w = 128\n val small_bank_addr_w = 9\n val small_global_size = 512\n val bias_w = 36\n val weight_w = 144\n val bias_addr_w = 8\n val weight_addr_w = 13\n val big_w = 16\n val h_w = 3\n val addr_w = 10\n val c_w = 6\n val id_w = 8\n val para_num = 2\n val mask = (1< (if(x>=y) y else x)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.6, "category_reason": "val binding"} {"task_id": "fpga_final_project", "path": "fpga_final_project/src/main/scala/utils/utils.scala", "left_context": "package final_project\n\nimport chisel3._\nimport chisel3.experimental.ChiselEnum\n\nclass TransBundle extends Bundle{\n val valid_in = Input(Bool())\n val valid_out = Output(Bool())\n val flag_job = Input(Bool())\n}\n\nclass ACounter(val w: chisel3.internal.firrtl.Width) extends Bundle{\n val ccnt = UInt(w)\n val cend = UInt(w)\n def inc(): Bool = {\n val nxt = Wire(Bool())\n nxt := ccnt===cend\n ccnt := Mux(nxt, 0.U, ccnt+1.U)\n return nxt\n }\n def set(csum: UInt): Unit = {\n cend := csum\n ccnt := 0.U\n }\n def set(begin: UInt, csum: UInt): Unit = {\n cend := csum\n ccnt := begin\n }\n def clr(): Unit = {\n ccnt := 0.U\n cend := 0.U\n }\n}\n\nobject ACounter{\n", "right_context": " def apply(w: chisel3.internal.firrtl.Width) = new ACounter(w)\n}\n\nclass RCounter(val w: chisel3.internal.firrtl.Width) extends Bundle{\n val ccnt = UInt(w)\n val cr = UInt(w)\n val cl = UInt(w)\n def inc(): Bool = {\n val nxt = Wire(Bool())\n nxt := ccnt===cr\n ccnt := Mux(nxt, cl, ccnt+1.U)\n return nxt\n }\n def set(r: UInt): Unit = {\n cr := r\n cl := 0.U\n ccnt := 0.U\n }\n def set(l: UInt, r: UInt): Unit = {\n cr := r\n cl := l\n ccnt := l\n }\n}\n\nobject RCounter{\n def apply(w: Int) = new RCounter(w.W)\n def apply(w: chisel3.internal.firrtl.Width) = new RCounter(w)\n}", "groundtruth": " def apply(w: Int) = new ACounter(w.W)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "fpga_final_project", "path": "fpga_final_project/src/main/scala/wr/gen_addr.scala", "left_context": "package final_project\n\nimport chisel3._\nimport chisel3.util._\n\nclass Address(val addr_w: Int, val id_w: Int) extends Bundle{\n val addr = UInt(addr_w.W)\n val bank_id = UInt(id_w.W)\n}\n\nobject Address{\n", "right_context": " def apply(addr: Data, id: Data): Data = {\n val ret = Wire(Address(addr.getWidth, id.getWidth))\n ret.addr := addr\n ret.bank_id := id\n return ret\n }\n}\n\nclass AddressReadGroup(val addr_w: Int, val id_w: Int) extends Bundle{\n val addrs = Vec(5, Address(addr_w, id_w))\n}\n\nclass AddressWriteGroup(val addr_w: Int, val id_w: Int) extends Bundle{\n val addrs = Vec(3, Address(addr_w, id_w))\n}\n\n\ntrait GenAddressInterface{\n def go(): Unit\n def output(): Data\n}\n\n// remember this is a register, not wire\nabstract class GenAddress(addr_w: Int, h_w: Int, c_w: Int, id_w: Int) extends Bundle with GenAddressInterface{\n val max_addr = UInt(addr_w.W) \n val min_addr = UInt(addr_w.W) \n val dta_addr = UInt(addr_w.W)\n val now_addr = UInt(addr_w.W)\n val cnt_ic = ACounter(c_w.W)\n val cnt_x = ACounter(h_w.W)\n val cnt_y = ACounter(h_w.W)\n val bank_id = UInt(id_w.W)\n val block_size = UInt(addr_w.W)\n val column_size = UInt(addr_w.W)\n def clamp(addr: UInt): UInt = {\n val nxt = Wire(UInt(addr.getWidth.W))\n when(addr>max_addr){\n nxt := addr+dta_addr\n }.otherwise{\n nxt := addr\n }\n return nxt\n }\n def set(x: WRJob): Unit = {\n max_addr := x.max_addr\n min_addr := x.min_addr\n now_addr := x.begin_addr\n block_size := x.block_size\n column_size := x.column_size\n cnt_ic.set(x.cnt_ic_end)\n cnt_x.set(x.cnt_x_end)\n cnt_y.set(x.cnt_y_end)\n bank_id := x.bank_id\n dta_addr := -x.max_addr-1.U+x.min_addr\n }\n override def output(): Data = {\n return Address(now_addr, bank_id)\n }\n}\n\nclass GenReadBigBankAddress(addr_w: Int, h_w: Int, c_w: Int, id_w: Int) extends GenAddress(addr_w, h_w, c_w, id_w){\n val cnt_loop = ACounter((2*c_w).W)\n val cnt_ups = ACounter(1.W)\n val cnt_maxp = ACounter(1.W)\n val y_begin_addr = UInt(addr_w.W)\n val ic_begin_addr = UInt(addr_w.W)\n val flag_end = Bool() \n override def go(): Unit = {\n val nxt_addr = Wire(UInt(addr_w.W))\n nxt_addr := 0.U\n when(cnt_ic.inc()){\n when(cnt_loop.inc()){\n when(cnt_y.inc()){\n when(cnt_ups.inc()){\n when(cnt_x.inc()){\n flag_end := true.B\n }.otherwise{\n nxt_addr := now_addr+1.U\n }\n y_begin_addr := clamp(nxt_addr)\n }.otherwise{\n nxt_addr := y_begin_addr\n }\n }.otherwise{\n nxt_addr := now_addr+1.U\n }\n ic_begin_addr := clamp(nxt_addr)\n }.otherwise{\n nxt_addr := ic_begin_addr\n }\n }.otherwise{\n nxt_addr := now_addr+1.U\n }\n now_addr := clamp(nxt_addr)\n }\n def go_maxp(): Unit = {\n val nxt_addr = Wire(UInt(addr_w.W))\n nxt_addr := 0.U\n when(cnt_maxp.inc()){\n when(cnt_ic.inc()){\n when(cnt_y.inc()){\n when(cnt_x.inc()){\n flag_end := true.B\n }.otherwise{\n nxt_addr := now_addr+1.U\n }\n }.otherwise{\n nxt_addr := y_begin_addr+1.U\n }\n }.otherwise{\n nxt_addr := y_begin_addr+1.U\n }\n y_begin_addr := clamp(nxt_addr)\n }.otherwise{\n nxt_addr := y_begin_addr+column_size\n }\n now_addr := clamp(nxt_addr)\n }\n def is_end(): Bool = {\n return flag_end\n }\n def set(x: ReadBigJob): Unit = {\n super.set(x)\n flag_end := false.B\n cnt_loop.set(x.begin_loop, x.cnt_loop_end)\n cnt_ups.set(x.cnt_ups_end)\n cnt_maxp.set(1.U)\n y_begin_addr := x.begin_addr\n ic_begin_addr := x.begin_addr\n }\n}\n\nclass GenReadSmallBankAddress(addr_w: Int, h_w: Int, c_w: Int, id_w: Int, big_w: Int) extends GenAddress(addr_w, h_w, c_w, id_w){\n val ano_bank_id = UInt(id_w.W) \n val cnt_invalid = ACounter(big_w.W)\n val cnt_maxp = ACounter(1.W)\n val cnt_ups = ACounter(1.W)\n val cnt_loop = ACounter((2*c_w).W)\n val cnt_swap = ACounter(1.W)\n val y_begin_addr = UInt(addr_w.W)\n val ic_begin_addr = UInt(addr_w.W)\n val start = Bool()\n override def go(): Unit = {\n val nxt_addr = Wire(UInt(addr_w.W))\n nxt_addr := 0.U\n when(cnt_invalid.inc()||start){\n start := true.B\n when(cnt_ic.inc()){\n when(cnt_loop.inc()){\n when(cnt_y.inc()){\n when(cnt_ups.inc()){\n when(cnt_swap.inc()){\n nxt_addr := now_addr+1.U\n y_begin_addr := clamp(nxt_addr)\n }.otherwise{\n nxt_addr := y_begin_addr\n }\n bank_id := ano_bank_id\n ano_bank_id := bank_id\n }.otherwise{\n nxt_addr := y_begin_addr\n }\n }.otherwise{\n nxt_addr := now_addr+1.U\n }\n ic_begin_addr := clamp(nxt_addr)\n }.otherwise{\n nxt_addr := ic_begin_addr\n }\n }.otherwise{\n nxt_addr := now_addr+1.U\n }\n now_addr := clamp(nxt_addr) \n }\n }\n def go_maxp(): Unit = {\n val nxt_addr = Wire(UInt(addr_w.W))\n nxt_addr := 0.U\n when(cnt_maxp.inc()){\n now_addr := clamp(now_addr+1.U)\n }\n bank_id := ano_bank_id\n ano_bank_id := bank_id\n }\n def set(x: ReadSmallJob): Unit = {\n super.set(x)\n ano_bank_id := x.ano_bank_id\n cnt_loop.set(x.begin_loop, x.cnt_loop_end)\n cnt_invalid.set(x.cnt_invalid_end)\n cnt_ups.set(x.cnt_ups_end)\n cnt_maxp.set(1.U)\n cnt_swap.set(x.begin_swap, 1.U)\n start := false.B\n y_begin_addr := x.begin_addr\n ic_begin_addr := x.begin_addr\n }\n}\n\n\nclass GenWriteSmallBankAddress(addr_w: Int, h_w: Int, c_w: Int, id_w: Int) extends GenAddress(addr_w, h_w, c_w, id_w){\n // a is the output_chan that it outputs,\n val a = UInt(c_w.W)\n val ano_bank_id = UInt(id_w.W) \n val cnt_swap = Bool()\n val y_begin_addr = UInt(addr_w.W)\n override def go(): Unit = {\n val nxt_addr = Wire(UInt((addr_w+1).W))\n nxt_addr := 0.U\n when(cnt_ic.inc()){\n when(cnt_y.inc()){\n cnt_swap := ~cnt_swap\n when(cnt_swap){\n nxt_addr := now_addr+a\n y_begin_addr := clamp(nxt_addr)\n }.otherwise{\n nxt_addr := y_begin_addr\n }\n bank_id := ano_bank_id\n ano_bank_id := bank_id\n }.otherwise{\n nxt_addr := now_addr+&a\n }\n }.otherwise{\n nxt_addr := now_addr+&1.U\n }\n now_addr := clamp(nxt_addr)\n }\n\n def set(x: WriteSmallJob): Unit = {\n super.set(x)\n a := x.a\n ano_bank_id := x.ano_bank_id\n y_begin_addr := x.begin_addr\n cnt_swap := false.B\n }\n}\n\nclass GenWriteBigBankAddress(addr_w: Int, h_w: Int, c_w: Int, id_w: Int) extends GenAddress(addr_w, h_w, c_w, id_w){\n val a = UInt(c_w.W) \n override def go(): Unit = {\n val nxt_addr = Wire(UInt((addr_w+1).W))\n when(cnt_ic.inc()){\n nxt_addr := now_addr+&a\n }.otherwise{\n nxt_addr := now_addr+&1.U\n }\n now_addr := clamp(nxt_addr)\n }\n \n def set(x: WriteBigJob): Unit = {\n super.set(x)\n a := x.a\n }\n\n}\n\nclass ReadGroup(addr_w: Int, h_w: Int, c_w: Int, id_w: Int, big_w: Int) extends Bundle{\n val big = new GenReadBigBankAddress(addr_w, h_w, c_w, id_w)\n val small = Vec(4, new GenReadSmallBankAddress(addr_w, h_w, c_w, id_w, big_w))\n def set(x: ReadJobs): Unit = {\n big.set(x.big)\n for(i <- 0 to 3)\n small(i).set(x.small(i))\n }\n def go(): Unit = {\n big.go()\n for(i <- 0 to 3)\n small(i).go()\n }\n def go_maxp(): Unit = {\n big.go_maxp()\n for(i <- 0 to 1)\n small(i).go_maxp()\n }\n def output(): Data = {\n val ret = Wire(new AddressReadGroup(addr_w, id_w))\n ret.addrs(0) := big.output()\n for(j <- 0 to 3)\n ret.addrs(j+1) := small(j).output()\n return ret\n }\n def is_end(): Bool = {\n return big.is_end()\n }\n}\n\n\nclass WriteGroup(addr_w: Int, h_w: Int, c_w: Int, id_w: Int) extends Bundle{\n val big = new GenWriteBigBankAddress(addr_w, h_w, c_w, id_w)\n val small = Vec(2, new GenWriteSmallBankAddress(addr_w, h_w, c_w, id_w))\n def set(x: WriteJobs): Unit = {\n big.set(x.big)\n for(j <- 0 to 1)\n small(j).set(x.small(j))\n }\n def go(): Unit = {\n big.go()\n for(j <- 0 to 1)\n small(j).go()\n }\n def output(): Data = {\n val ret = Wire(new AddressWriteGroup(addr_w, id_w))\n ret.addrs(0) := big.output()\n for(j <- 0 to 1)\n ret.addrs(j+1) := small(j).output()\n return ret\n }\n}", "groundtruth": " def apply(addr_w: Int, id_w: Int) = new Address(addr_w, id_w)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "fpga_final_project", "path": "fpga_final_project/src/main/scala/wr/read.scala", "left_context": "package final_project\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.ChiselEnum\n\nobject ReadType extends ChiselEnum{\n val toConvOrCopy = Value(0.U) // Sigmoid, conv, mult\n val toMaxp = Value(1.U) // Maxpool\n}\n\nclass GraphReaderBundle(val addr_w: Int, val h_w: Int, val c_w: Int, val id_w: Int, val big_w: Int) extends TransBundle{\n val job = Input(new ReadJobs(addr_w, h_w, c_w, id_w, big_w))\n val job2 = Input(new ReadJobs(addr_w, h_w, c_w, id_w, big_w))\n val signal = Input(Bool())\n val job_type = Input(ReadType())\n val to_banks = Output(new AddressReadGroup(addr_w, id_w))\n}\n\nclass GraphReader(val addr_w: Int, val h_w: Int, val c_w: Int, val id_w: Int, val big_w: Int) extends Module{\n val io = IO(new GraphReaderBundle(addr_w, h_w, c_w, id_w, big_w))\n\n io.valid_out := false.B\n io.to_banks := 0.U.asTypeOf(io.to_banks)\n \n val job_type = RegInit(ReadType.toConvOrCopy)\n\n val gen = RegInit(0.U.asTypeOf(Vec(2, new ReadGroup(addr_w, h_w, c_w, id_w, big_w))))\n\n val state = RegInit(0.U(1.W))\n\n when(io.flag_job){\n gen(0).set(io.job)\n gen(1).set(io.job2)\n state := 0.U\n job_type := io.job_type\n }.elsewhen(io.valid_in){\n state := state^io.signal.asUInt\n switch(job_type){\n is(ReadType.toConvOrCopy){\n gen(state).go()\n }\n", "right_context": " io.to_banks := gen(state).output() \n }\n \n \n}", "groundtruth": " is(ReadType.toMaxp){\n gen(state).go_maxp()\n }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.75, "category_reason": "is() in switch context"} {"task_id": "fpga_final_project", "path": "fpga_final_project/src/main/scala/wr/read_pack.scala", "left_context": "package final_project\n\nimport chisel3._\nimport chisel3.util._\n\nclass BigBankReadData(val w: Int) extends Bundle{\n val data = Vec(48, SInt(w.W))\n}\n\nclass SmallBankReadData(val w: Int) extends Bundle{\n val data = Vec(8, SInt(w.W))\n}\n\nclass PackReadDataBundle(val w: Int, val h_w: Int, val c_w: Int, val big_w: Int) extends TransBundle{\n val job = Input(new PackJob(w, h_w, c_w, big_w))\n val from_big = Input(Vec(2, new BigBankReadData(w)))\n val from_small = Input(Vec(2, Vec(4, new SmallBankReadData(w))))\n val output = Output(new PackedData(w))\n}\n\nclass PackReadData(val w: Int, val h_w: Int, val c_w: Int, val big_w: Int) extends Module{\n val io = IO(new PackReadDataBundle(w, h_w, c_w, big_w))\n val cache = RegInit(0.U.asTypeOf(Vec(2, Vec(64, Vec(10, SInt(w.W))))))\n\n val cnt_ic = RegInit(0.U.asTypeOf(ACounter(c_w.W)))\n val cnt_swap = RegInit(0.U.asTypeOf(ACounter(big_w.W)))\n val cnt_x = RegInit(0.U.asTypeOf(ACounter(h_w.W)))\n val cnt_y = RegInit(0.U.asTypeOf(ACounter(h_w.W)))\n\n val output_reg = Wire((new PackedData(w)))\n io.output := output_reg\n\n \n val state = RegInit(0.U(1.W))\n \n def copy64(): Unit = {\n for(i <- 0 to 7){\n for(j <- 1 to 6)\n output_reg.mat(i*8+j) := io.from_big(state).data(i*6+j-1)\n output_reg.mat(i*8+0) := io.from_small(state)(1).data(i)\n output_reg.mat(i*8+7) := io.from_small(state)(2).data(i)\n }\n }\n\n copy64()\n when(cnt_y.ccnt===0.U){\n for(i <- 2 to 7)\n output_reg.up(i) := io.from_big(state).data(6+i-2)\n output_reg.up(1) := io.from_small(state)(1).data(1)\n output_reg.up(8) := io.from_small(state)(2).data(1)\n when(cnt_x.ccnt===0.U){\n output_reg.up(0) := io.from_big(state).data(6)\n }.otherwise{\n output_reg.up(0) := io.from_small(state)(0).data(1)\n }\n when(cnt_x.ccnt===cnt_x.cend){\n output_reg.up(9) := io.from_big(state).data(6+5)\n }.otherwise{\n output_reg.up(9) := io.from_small(state)(3).data(1) \n }\n }.otherwise{\n output_reg.up := cache(~state)(0)\n }\n\n var x = 1\n for(i <- 0 to 63){\n if(i==(1<> 1.U)|io.valid_in\n\n val cache = RegInit(0.U.asTypeOf(Vec(para_num, new AccumuRawData(w))))\n for(i <- 0 to para_num-2)\n cache(i) := Mux(io.valid_in(i), io.in_from_accumu(i), cache(i+1))\n cache(para_num-1) := Mux(io.valid_in(para_num-1), io.in_from_accumu(para_num-1), 0.U.asTypeOf(cache(para_num-1)))\n \n io.out := cache(0)\n io.valid_out := cache_valid(0)\n\n}\n\n/*\nclass CacheWriter(val w: Int, val addr_w: Int, val num: Int, val h_w: Int, val c_w: Int, val id_w: Int) extends Module{\n val io = IO(new Bundle{\n val in_from_quant = Input(Vec(num, new QuantedData(w)))\n val valid_in = Input(Vec(num, Bool()))\n val valid_out = Output(Bool())\n val flag_job = Input(Bool())\n val jobs = Input(Vec(num, new WriteJobs(addr_w, h_w, c_w, id_w)))\n val to_bigbank = Output(new BigBankWriteData(w))\n val to_smallbank = Output(Vec(2, new SmallBankWriteData(w)))\n val to_banks = Output(new AddressWriteGroup(addr_w, id_w))\n })\n\n val writers = VecInit(Seq.fill(num)(Module(new Writer(w, addr_w, h_w, c_w, id_w)).io))\n val cache = RegInit(0.U.asTypeOf(VecInit(Seq.fill(num)(new QuantedData(w)))))\n val cache_valid = RegInit(0.U.asTypeOf(Vec(num, Bool())))\n val now = PriorityMux(Seq.tabulate(num){i => cache_valid(i)}, Seq.tabulate(num){i => i.U})\n\n io.to_bigbank := 0.U.asTypeOf(io.to_bigbank)\n io.to_smallbank := 0.U.asTypeOf(io.to_smallbank)\n io.to_banks := 0.U.asTypeOf(io.to_banks)\n io.valid_out := false.B\n for(i <- 0 to num-1)\n writers(i) := 0.U.asTypeOf(writers(i))\n\n when(io.flag_job){\n cache_valid := 0.U.asTypeOf(cache_valid)\n for(i <- 0 to num-1){\n writers(i).job := io.jobs(i)\n writers(i).flag_job := true.B\n }\n }.otherwise{\n for(i <- 0 to num-1)\n cache := io.in_from_quant(i)\n for(i <- 0 to num-1)\n cache_valid(i) := cache_valid(i)|io.valid_in(i)\n when(cache_valid(now)){\n writers(now).valid_in := true.B\n writers(now).in_from_quant := cache(now)\n io.to_bigbank := writers(now).to_bigbank\n io.to_smallbank := writers(now).to_smallbank\n io.to_banks := writers(now).to_banks\n cache_valid(now) := io.valid_in(now)\n }\n }\n\n}*/", "groundtruth": " for(j <- 0 to 5)\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Loop-based Control", "confidence": 0.8, "category_reason": "for loop"} {"task_id": "fpga_final_project", "path": "fpga_final_project/src/main/scala/wr/wrjob.scala", "left_context": "package final_project\n\nimport chisel3._\nimport chisel3.util._\n\nclass WRJob(addr_w: Int, h_w: Int, c_w: Int, id_w: Int) extends Bundle{\n val begin_addr = UInt(addr_w.W)\n val max_addr = UInt(addr_w.W)\n val min_addr = UInt(addr_w.W)\n val bank_id = UInt(id_w.W)\n val block_size = UInt(addr_w.W)\n val column_size = UInt(addr_w.W)\n val cnt_x_end = UInt(h_w.W)\n val cnt_y_end = UInt(h_w.W)\n val cnt_ic_end = UInt(c_w.W)\n}\n\nclass WriteBigJob(addr_w: Int, h_w: Int, c_w: Int, id_w: Int) extends WRJob(addr_w, h_w, c_w, id_w){\n val a = UInt(c_w.W)\n}\n\nclass WriteSmallJob(addr_w: Int, h_w: Int, c_w: Int, id_w: Int) extends WRJob(addr_w, h_w, c_w, id_w){\n val a = UInt(c_w.W)\n val ano_bank_id = UInt(id_w.W)\n}\n\nclass ReadBigJob(addr_w: Int, h_w: Int, c_w: Int, id_w: Int) extends WRJob(addr_w, h_w, c_w, id_w){\n val cnt_loop_end = UInt((2*c_w).W)\n val begin_loop = UInt((2*c_w).W)\n val cnt_ups_end = UInt(1.W)\n}\n\nclass ReadSmallJob(addr_w: Int, h_w: Int, c_w: Int, id_w: Int, big_w: Int) extends WRJob(addr_w, h_w, c_w, id_w){\n val ano_bank_id = UInt(id_w.W)\n val cnt_loop_end = UInt((2*c_w).W)\n val begin_loop = UInt((2*c_w).W)\n val cnt_invalid_end = UInt(big_w.W)\n val cnt_ups_end = UInt(1.W)\n val begin_swap = UInt(1.W)\n}\n\nclass ReadJobs(addr_w: Int, h_w: Int, c_w: Int, id_w: Int, big_w: Int) extends Bundle{\n val big = new ReadBigJob(addr_w, h_w, c_w, id_w)\n val small = Vec(4, new ReadSmallJob(addr_w, h_w, c_w, id_w, big_w))\n}\n\nclass WriteJobs(addr_w: Int, h_w: Int, c_w: Int, id_w: Int) extends Bundle{\n val big = new WriteBigJob(addr_w, h_w, c_w, id_w)\n val small = Vec(2, new WriteSmallJob(addr_w, h_w, c_w, id_w))\n}\n\nclass RealWriteJobs(addr_w: Int, h_w: Int, c_w: Int, id_w: Int) extends Bundle{\n val job = Vec(2, new WriteJobs(addr_w, h_w, c_w, id_w))\n val out_chan = UInt(c_w.W)\n}\n\nobject GenConvReadJob{\n def gen(addr_w: Int, h_w: Int, c_w: Int, id_w: Int, big_w: Int, loop_num: Int, begin_loop_num: Int, loop_h: Int, \n h: Int, w: Int, in_chan: Int, begin_addr: Int, min_addr: Int, max_addr: Int,\n small_begin_addr: Int, small_min_addr: Int, small_max_addr: Int, \n bank_id_big: Int, bank_id_small: Array[Int]): ReadJobs = {\n val ret = Wire(new ReadJobs(addr_w, h_w, c_w, id_w, big_w))\n ret.big.begin_addr := begin_addr.U\n ret.big.min_addr := min_addr.U\n ret.big.max_addr := max_addr.U\n ret.big.bank_id := bank_id_big.U\n ret.big.block_size := in_chan.U\n ret.big.column_size := (in_chan*h).U\n ret.big.cnt_x_end := (w-1).U\n ret.big.cnt_y_end := (h-1).U\n ret.big.cnt_ic_end := (in_chan-1).U\n ret.big.cnt_loop_end := (loop_num-1).U\n ret.big.cnt_ups_end := (loop_h-1).U\n ret.big.begin_loop := begin_loop_num.U\n for(i <- 0 to 3){\n ret.small(i).begin_addr := small_begin_addr.U\n ret.small(i).min_addr := small_min_addr.U\n ret.small(i).max_addr := small_max_addr.U\n ret.small(i).block_size := in_chan.U\n ret.small(i).column_size := (in_chan*h).U\n ret.small(i).cnt_x_end := (w/2-1).U\n ret.small(i).cnt_y_end := (h-1).U\n ret.small(i).cnt_ic_end := (in_chan-1).U\n ret.small(i).cnt_loop_end := (loop_num-1).U\n", "right_context": " ret.small(i).cnt_ups_end := (loop_h-1).U\n ret.small(i).begin_loop := begin_loop_num.U\n if(i==0){\n ret.small(i).bank_id := bank_id_small(2).U\n ret.small(i).ano_bank_id := bank_id_small(0).U \n } else {\n ret.small(i).bank_id := bank_id_small(i).U\n ret.small(i).ano_bank_id := bank_id_small(i^2).U \n }\n if(i==3){\n ret.small(i).begin_swap := (1).U\n } else {\n ret.small(i).begin_swap := 0.U\n }\n \n }\n return ret\n }\n}\n\nobject GenMaxpReadJob{\n def gen(addr_w: Int, h_w: Int, c_w: Int, id_w: Int, big_w: Int, loop_num: Int, begin_loop_num: Int, loop_h: Int, \n h: Int, w: Int, in_chan: Int, begin_addr: Int, min_addr: Int, max_addr: Int,\n small_begin_addr: Int, small_min_addr: Int, small_max_addr: Int, \n bank_id_big: Int, bank_id_small: Array[Int]): ReadJobs = {\n val ret = Wire(new ReadJobs(addr_w, h_w, c_w, id_w, big_w))\n ret := 0.U.asTypeOf(new ReadJobs(addr_w, h_w, c_w, id_w, big_w))\n ret.big.begin_addr := begin_addr.U\n ret.big.min_addr := min_addr.U\n ret.big.max_addr := max_addr.U\n ret.big.bank_id := bank_id_big.U\n ret.big.block_size := in_chan.U\n ret.big.column_size := (in_chan*h).U\n ret.big.cnt_x_end := (w/2-1).U\n ret.big.cnt_y_end := (h-1).U\n ret.big.cnt_ic_end := (in_chan-1).U\n for(i <- 0 to 1){\n ret.small(i).begin_addr := small_begin_addr.U\n ret.small(i).min_addr := small_min_addr.U\n ret.small(i).max_addr := small_max_addr.U\n if(i==0){\n ret.small(i).bank_id := bank_id_small(2).U\n ret.small(i).ano_bank_id := bank_id_small(0).U \n } else {\n ret.small(i).bank_id := bank_id_small(i).U\n ret.small(i).ano_bank_id := bank_id_small(i^2).U \n }\n \n }\n return ret\n }\n}\n\n\nobject GenWriteConvJob{\n def gen(addr_w: Int, h_w: Int, c_w: Int, id_w: Int, \n h: Int, w: Int, out_chan: Int, begin_addr: Int, min_addr: Int, max_addr: Int,\n small_begin_addr: Int, small_min_addr: Int, small_max_addr: Int, \n bank_id_big: Int, bank_id_small: Array[Int], al: Int, ar: Int): WriteJobs = {\n val ret = Wire(new WriteJobs(addr_w, h_w, c_w, id_w))\n ret.big.begin_addr := begin_addr.U\n ret.big.min_addr := min_addr.U\n ret.big.max_addr := max_addr.U\n ret.big.bank_id := bank_id_big.U\n ret.big.block_size := out_chan.U\n ret.big.column_size := (out_chan*h).U\n ret.big.cnt_x_end := (w-1).U\n ret.big.cnt_y_end := (h-1).U\n ret.big.cnt_ic_end := (ar-al).U\n ret.big.a := (out_chan-ar+al).U\n for(i <- 0 to 1){\n ret.small(i).begin_addr := small_begin_addr.U\n ret.small(i).min_addr := small_min_addr.U\n ret.small(i).max_addr := small_max_addr.U\n ret.small(i).block_size := out_chan.U\n ret.small(i).column_size := (out_chan*h).U\n ret.small(i).cnt_x_end := (w/2-1).U\n ret.small(i).cnt_y_end := (h-1).U\n ret.small(i).cnt_ic_end := (ar-al).U\n ret.small(i).a := (out_chan-ar+al).U\n ret.small(i).bank_id := bank_id_small(i).U\n ret.small(i).ano_bank_id := bank_id_small(i+2).U\n }\n return ret \n }\n}\n\n\nclass PackJob(addr_w: Int, h_w: Int, c_w: Int, big_w: Int) extends Bundle{\n val cnt_x_end = UInt(h_w.W)\n val cnt_y_end = UInt(h_w.W)\n val in_chan = UInt(c_w.W)\n val cnt_swap_end = UInt(big_w.W)\n}\n\nobject GenPackJob{\n def gen(addr_w: Int, h_w: Int, c_w: Int, big_w: Int, cnt_x_end: Int, cnt_y_end: Int, cnt_swap_end: Int, in_chan: Int): PackJob = {\n val ret = Wire(new PackJob(addr_w, h_w, c_w, big_w))\n ret.cnt_x_end := cnt_x_end.U\n ret.cnt_y_end := cnt_y_end.U\n ret.in_chan := in_chan.U\n ret.cnt_swap_end := cnt_swap_end.U\n return ret\n }\n}", "groundtruth": " ret.small(i).cnt_invalid_end := (if(i==0) (loop_num*in_chan*h*loop_h).U else 0.U)\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.55, "category_reason": ":= connection"} {"task_id": "fpga_final_project", "path": "fpga_final_project/src/test/scala/gcd/test_calc8x8.scala", "left_context": "// See README.md for license details.\n\npackage final_project\n\nimport chisel3._\nimport chisel3.tester._\nimport org.scalatest._\nimport chisel3.experimental.BundleLiterals._\nimport chisel3.iotesters._\n\nclass Calc8x8Tester(dut: Calc8x8) extends PeekPokeTester(dut) {\n\n //val rnd = new scala.util.Random\n val T = 10\n for(t <- 0 until T){\n var A = Array.tabulate(10, 10) {\n (i, j) => rnd.nextInt(5)-32768\n }\n for(i <- 0 to 63){\n poke(dut.io.input.mat(i), A(i/8+1)(i%8+1))\n }\n for(i <- 0 to 9) {\n poke(dut.io.input.up(i), A(0)(i))\n }\n for(i <- 0 to 7) {\n poke(dut.io.input.left(i), A(i+1)(0))\n }\n for(i <- 0 to 7) {\n poke(dut.io.input.right(i), A(i+1)(9))\n }\n for(i <- 0 to 9) {\n poke(dut.io.input.down(i), A(9)(i))\n }\n\n val B = Array.fill[Int](4, 3, 3)(0)\n for(t <- 0 to 3)\n for(i <- 0 to 8) B(t)(i/3)(i%3) = rnd.nextInt(32768)-16384\n //rnd.nextInt(5)-32768\n\n val std = Array.tabulate(4, 8, 8) {\n (t, i, j) => {\n var sum = BigInt(0)\n for(ii <- i to i+2)\n for(jj <- j to j+2){\n var a = A(ii)(jj)\n var b = B(t)(ii-i)(jj-j)\n sum = sum+BigInt(a)*b\n }\n \n sum\n }\n }\n for(t <- 0 to 3)\n for(i <- 0 to 8)\n poke(dut.io.weight(t).real(i), B(t)(i/3)(i%3))\n\n poke(dut.io.flag, 3)\n poke(dut.io.mask, 15)\n poke(dut.io.valid_in, true)\n var stop = false\n while(!stop){\n step(1)\n poke(dut.io.valid_in, false)\n if(peek(dut.io.valid_out)==15){\n println(\"[valid: \" + peek(dut.io.valid_out).toString + \"] Result:\")\n for(t <- 0 to 3)\n", "right_context": " var str = \"\"\n for(k <- 0 to 7){\n var x = peek(dut.io.output(t).mat(j*8+k)).toString()\n expect(dut.io.output(t).mat(j*8+k), std(t)(j)(k))\n str = str+x+\" \"\n } \n println(str)\n }\n\n stop = true\n }\n \n }\n }\n \n /*\n val _B = Array.fill[Int](6, 3)(0)\n val _Bi = Array.fill[Int](6, 3)(0)\n for(j <- 0 to 2){\n _B(0)(j) = B(0)(j)\n _B(1)(j) = B(0)(j)+B(1)(j)+B(2)(j)\n _B(2)(j) = B(0)(j)-B(1)(j)+B(2)(j)\n _B(3)(j) = B(0)(j)-B(2)(j)\n _B(4)(j) = B(0)(j)-B(2)(j)\n _B(5)(j) = B(2)(j)\n _Bi(3)(j) = B(1)(j)\n _Bi(4)(j) = -B(1)(j)\n }\n\n val __B = Array.fill[Int](6, 6)(0)\n val __Bi = Array.fill[Int](6, 6)(0)\n\n for(i <- 0 to 5){\n __B(i)(0) = _B(i)(0)\n __B(i)(1) = _B(i)(0)+_B(i)(1)+_B(i)(2)\n __B(i)(2) = _B(i)(0)-_B(i)(1)+_B(i)(2)\n __B(i)(3) = _B(i)(0)-_B(i)(2)-_Bi(i)(1)\n __B(i)(4) = _B(i)(0)-_B(i)(2)+_Bi(i)(1)\n __B(i)(5) = _B(i)(2)\n __Bi(i)(0) = _Bi(i)(0)\n __Bi(i)(1) = _Bi(i)(0)+_Bi(i)(1)+_Bi(i)(2)\n __Bi(i)(2) = _Bi(i)(0)-_Bi(i)(1)+_Bi(i)(2)\n __Bi(i)(3) = _Bi(i)(0)-_Bi(i)(2)+_B(i)(1)\n __Bi(i)(4) = _Bi(i)(0)-_Bi(i)(2)-_B(i)(1)\n __Bi(i)(5) = _Bi(i)(2)\n }\n \n for(t <- 0 to 3){\n var x = 0\n var y = 0\n for(i <- 0 to 5){\n for(j <- 0 to 5){\n if(i!=3&&i!=4&&j!=3&&j!=4){\n poke(dut.io.weight(t).real(x), __B(i)(j))\n x = x+1\n } else if(i==3){\n poke(dut.io.weight(t).comp1(y), __B(i)(j)+__Bi(i)(j))\n poke(dut.io.weight(t).comp2(y), __B(i)(j))\n poke(dut.io.weight(t).comp3(y), __Bi(i)(j))\n y = y+1\n } else if(i!=4&&j==3){\n poke(dut.io.weight(t).comp1(y), __B(i)(j)+__Bi(i)(j))\n poke(dut.io.weight(t).comp2(y), __B(i)(j))\n poke(dut.io.weight(t).comp3(y), __Bi(i)(j))\n y = y+1\n }\n }\n }\n }*/\n \n}\n\n\nclass Calc8x8Spec extends FlatSpec with Matchers {\n\n it should \"Calc8x8 should pass\" in {\n chisel3.iotesters.Driver(() => new Calc8x8(16, 4)) { c =>\n new Calc8x8Tester(c)\n } should be (true)\n }\n}\n", "groundtruth": " for(j <- 0 to 7){\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Loop-based Control", "confidence": 0.8, "category_reason": "for loop"} {"task_id": "fpga_final_project", "path": "fpga_final_project/src/test/scala/gcd/test_conv.scala", "left_context": "package final_project\n\nimport chisel3._\nimport chisel3.util._\n\nimport chisel3._\nimport chisel3.tester._\nimport org.scalatest._\nimport chisel3.experimental.BundleLiterals._\nimport chisel3.iotesters._\n\nclass Global1(_w: Int, h_w: Int, c_w: Int, id_w: Int, big_w: Int, addr_w: Int, bias_w: Int, num: Int) extends Module{\n val io = IO(new Bundle{\n val rd_addr1 = Output(new AddressReadGroup(addr_w, id_w))\n val rd_addr2 = Output(new AddressReadGroup(addr_w, id_w))\n val rd_big = Input(Vec(2, new BigBankReadData(_w)))\n val rd_small = Input(Vec(2, Vec(4, new SmallBankReadData(_w))))\n val rd_valid_in = Input(Bool())\n val rd_valid_out = Output(Bool())\n val weight_addr = Output(UInt(addr_w.W))\n val weight_in = Input(Vec(9, SInt(16.W)))\n val wr_addr = Output(new AddressWriteGroup(addr_w, id_w))\n val bias_in = Input(SInt(bias_w.W))\n val bias_addr = Output(UInt(addr_w.W))\n val packed = Output(new PackedData(_w))\n //val wr_small = Output(Vec(4, UInt((_w*8).W)))\n //val wr_big = Output(Vec(1, UInt((_w*48).W)))\n val quanted = Output(new QuantedData(_w))\n val wr_valid_out = Output(Bool())\n val test_valid_out = Output(Bool())\n val to_bigbank = Output(new BigBankWriteData(_w))\n val to_smallbank = Output(Vec(2, new SmallBankWriteData(_w)))\n })\n\n\n\n\n val reader1 = Module(new GraphReader(addr_w, h_w, c_w, id_w, big_w)).io\n val reader2 = Module(new GraphReader(addr_w, h_w, c_w, id_w, big_w)).io\n val read_pack = Module(new PackReadData(_w, h_w, c_w, big_w)).io\n val read_switch = Module(new ReadSwitch(_w, h_w, c_w, 1)).io\n val read_weight = Module(new WeightReader(_w, addr_w)).io\n val calc8x8 = Module(new Calc8x8(_w, 1)).io\n val accu = Module(new Accumu(_w, addr_w, bias_w, 1)).io\n val quant = Module(new Quant(_w)).io\n val write_switch = Module(new WriteSwitch(_w, 3)).io\n val writer = Module(new RealWriter(_w, addr_w, h_w, c_w, id_w)).io\n val maxpool = Module(new Maxpool(_w)).io\n \n io.rd_addr1 := 0.U.asTypeOf(io.rd_addr1)\n io.rd_addr2 := 0.U.asTypeOf(io.rd_addr2)\n io.rd_valid_out := false.B\n io.weight_addr := 0.U.asTypeOf(io.weight_addr)\n\n\n io.rd_addr1 := reader1.to_banks\n reader1.flag_job := false.B\n reader1.valid_in := false.B\n reader1.job := 0.U.asTypeOf(reader1.job)\n reader1.job2 := 0.U.asTypeOf(reader1.job2)\n reader1.signal := false.B\n reader1.job_type := 0.U.asTypeOf(reader1.job_type)\n\n io.rd_valid_out := reader2.valid_out\n io.rd_addr2 := reader2.to_banks\n reader2.flag_job := false.B\n reader2.valid_in := false.B\n reader2.job := 0.U.asTypeOf(reader2.job)\n reader2.job_type := 0.U.asTypeOf(reader2.job_type)\n reader2.job2 := 0.U.asTypeOf(reader1.job2)\n reader2.signal := false.B\n\n read_weight.valid_in := false.B\n read_weight.addr_end := 0.U\n read_weight.begin_addr := 0.U\n io.weight_addr := read_weight.addr\n read_weight.flag_job := false.B\n \n\n read_pack.valid_in := io.rd_valid_in\n read_pack.flag_job := false.B\n read_pack.job := 0.U.asTypeOf(read_pack.job)\n read_pack.from_big := io.rd_big\n read_pack.from_small := io.rd_small\n\n \n \n read_switch.flag_job := false.B\n read_switch.job := 0.U.asTypeOf(read_switch.job)\n read_switch.valid_in := read_pack.valid_out\n read_switch.from := read_pack.output\n read_switch.from_weight(0) := io.weight_in\n read_switch.in_h := 0.U\n read_switch.in_chan := 0.U\n\n calc8x8.input := read_switch.to_calc8x8\n calc8x8.flag := 0.U.asTypeOf(calc8x8.flag)\n calc8x8.weight := read_switch.to_weight\n calc8x8.valid_in := read_switch.valid_out_calc8x8\n calc8x8.mask := 0.U\n calc8x8.multmap := read_switch.to_multmap\n\n \n \n accu.in_from_calc8x8 := calc8x8.output\n accu.valid_in := calc8x8.valid_out\n accu.flag_job := false.B\n accu.csum := 0.U\n accu.bias_begin_addr := 0.U\n accu.bias_end_addr := 0.U\n io.bias_addr := accu.bias_addr\n accu.bias_in(0) := io.bias_in\n accu.is_in_use := false.B\n\n\n quant.in_from_accumu := accu.result(0)\n quant.valid_in := accu.valid_out(0)\n quant.flag_job := false.B\n quant.quant_in := 0.U.asTypeOf(quant.quant_in)\n\n \n maxpool.from_big := io.rd_big\n for(t <- 0 to 1){\n maxpool.from_small(t)(0) := io.rd_small(t)(1)\n maxpool.from_small(t)(1) := io.rd_small(t)(2)\n }\n \n maxpool.valid_in := read_switch.valid_out_maxp\n\n //write_switch.valid_in(1) := false.B\n //write_switch.input(1) := 0.U.asTypeOf(write_switch.input(1))\n\n write_switch.valid_in(0) := quant.valid_out // conv\n write_switch.valid_in(1) := maxpool.valid_out // maxpool\n write_switch.valid_in(2) := read_switch.valid_out_copy // go through\n\n write_switch.valid_in(1) := false.B\n write_switch.valid_in(2) := false.B\n\n write_switch.input(0) := quant.result\n write_switch.input(1) := maxpool.result\n write_switch.input(2) := read_switch.to_copy\n\n writer.in_from_quant := write_switch.output\n writer.valid_in := write_switch.valid_out\n writer.flag_job := false.B\n writer.job := 0.U.asTypeOf(writer.job)\n io.wr_addr := writer.to_banks\n io.to_bigbank := writer.to_bigbank\n io.to_smallbank := writer.to_smallbank\n io.wr_valid_out := writer.valid_out\n \n /*\n io.wr_addr := 0.U.asTypeOf(io.wr_addr)\n io.to_bigbank := 0.U.asTypeOf(io.to_bigbank)\n io.to_smallbank := 0.U.asTypeOf(io.to_smallbank)\n io.wr_valid_out := false.B\n io.bias_addr := 0.U*/\n\n \n io.quanted := quant.result\n io.test_valid_out := calc8x8.valid_out\n // io.quanted := read_pack.output\n\n io.packed := 0.U.asTypeOf(io.packed)\n io.packed.mat := calc8x8.output(0).mat\n /*\n // w, h, wr_w, wr_h\n // in out chan\n // para\n // big addr\n // wr big addr\n // small addr\n // wr small addr\n */\n val paras = GenAllPara(addr_w, h_w, c_w, id_w, big_w, \n 2, 2, 2, 2, \n 2, 2, \n 1, 1, \n 0, 1023, 0, \n 1020, 1023, 0, \n 0, 1023, 0, \n 1020, 1023, 0, \n 0, 0, 17, 16\n )\n \n \n val state = RegInit(0.U(3.W))\n switch(state){\n is(0.U){\n paras.set_conv_reader1(reader1)\n paras.set_conv_reader2(reader2)\n paras.set_read_weight(read_weight)\n paras.set_conv_read_pack(read_pack)\n paras.set_conv_accu(accu)\n paras.set_quant(quant)\n paras.set_write(writer)\n paras.set_conv_read_switch(read_switch)\n\n calc8x8.flag := CalcType.calcConv\n calc8x8.mask := paras.mask.U\n state := 1.U\n }\n is(1.U){\n reader1.valid_in := true.B\n reader2.valid_in := true.B\n read_weight.valid_in := true.B\n calc8x8.flag := CalcType.calcConv\n calc8x8.mask := paras.mask.U\n }\n }\n}\n\n\nclass ConvTester(dut: Global1, _w: Int, h_w: Int, c_w: Int, id_w: Int, big_w: Int, addr_w: Int, bias_w: Int, num: Int) extends PeekPokeTester(dut){\n \n var bank_id_big = Array(0, 1)\n var bank_id_small = Array(Array(3, 0, 1, 2), Array(7, 4, 5, 6))\n var (w, h) = (2, 2)\n var (in_chan, out_chan) = (2, 2)\n var A = Array.tabulate(8*8*w*h, in_chan){\n (i, ic) => i*in_chan+ic\n }\n var small_bank = Array.fill[Int](10, (h/2)*(w/2)*8*in_chan+64*in_chan)(0)\n var big_bank = Array.fill[Int](10, (h/2)*w*48*in_chan+64*in_chan)(0)\n for(i <- 0 to w-1)\n for(j <- 0 to h-1){\n var t1 = bank_id_small(j%2)(if(i%2==1) 3 else 1)\n", "right_context": " for(ic <- 0 to in_chan-1){\n for(k <- 0 to 7){\n small_bank(t1)((i/2)*(h/2)*8*in_chan+(j/2)*8*in_chan+ic*8+k) = A((i*h+j)*64+k*8)(ic)\n small_bank(t2)((i/2)*(h/2)*8*in_chan+(j/2)*8*in_chan+ic*8+k) = A((i*h+j)*64+k*8+7)(ic)\n }\n for(k <- 0 to 7)\n for(l <- 0 to 5){\n big_bank(bank_id_big(j%2))(i*(h/2)*48*in_chan+(j/2)*48*in_chan+ic*48+(k*6+l)) = A((i*h+j)*64+k*8+l+1)(ic)\n }\n }\n \n }\n var weight_bank = Array.fill[Int](9*in_chan*out_chan)(0)\n var bias_bank = Array.tabulate(out_chan){\n i => i\n }\n for(i <- 0 to out_chan-1)\n for(j <- 0 to in_chan-1){\n val B = Array.tabulate(3, 3) {\n (i, j) => i*3+j\n }\n for(k <- 0 to 8)\n weight_bank((i*in_chan+j)*9+k) = B(k/3)(k%3)\n }\n var read_reg = 0\n var T = 0\n var stop = 0\n while(T<20&&(stop==0)){\n T += 1\n val rd_bias = peek(dut.io.bias_addr).toInt\n poke(dut.io.bias_in, bias_bank(rd_bias))\n if(peek(dut.io.rd_valid_out)==1){\n poke(dut.io.rd_valid_in, true)\n val rd_w = (peek(dut.io.weight_addr)).toInt\n val vis = Array.fill[Int](10, 10)(0)\n val vis_id = Array.fill[Int](10, 10)(0)\n def get_addr(i: Int, j: Int): Int = {\n if(vis(i)(j)!=0) return vis(i)(j)\n //println(\"(\"+i+\",\"+j+\") addr: \"+(if(i==1) (peek(dut.io.rd_addr1.addrs(j).addr)).toInt else (peek(dut.io.rd_addr2.addrs(j).addr)).toInt))\n vis(i)(j) = (if(i==1) (peek(dut.io.rd_addr1.addrs(j).addr)).toInt else (peek(dut.io.rd_addr2.addrs(j).addr)).toInt)\n return vis(i)(j)\n }\n def get_id(i: Int, j: Int): Int = {\n if(vis_id(i)(j)!=0) return vis_id(i)(j)\n //return 0\n //println(\"(\"+i+\",\"+j+\") addr: \"+(if(i==1) (peek(dut.io.rd_addr1.addrs(j).bank_id)).toInt else (peek(dut.io.rd_addr2.addrs(j).bank_id)).toInt))\n vis_id(i)(j) = (if(i==1) (peek(dut.io.rd_addr1.addrs(j).bank_id)).toInt else (peek(dut.io.rd_addr2.addrs(j).bank_id)).toInt)\n return vis_id(i)(j)\n }\n for(i <- 1 to 4){\n for(j <- 0 to 7)\n poke(dut.io.rd_small(0)(i-1).data(j), small_bank(get_id(1, i))(get_addr(1, i)*8+j))\n }\n for(j <- 0 to 47) \n poke(dut.io.rd_big(0).data(j), big_bank(get_id(1, 0))(get_addr(1, 0)*48+j))\n for(i <- 1 to 4){\n for(j <- 0 to 7)\n poke(dut.io.rd_small(1)(i-1).data(j), small_bank(get_id(2, i))(get_addr(2, i)*8+j))\n }\n for(j <- 0 to 47) \n poke(dut.io.rd_big(1).data(j), big_bank(get_id(2, 0))(get_addr(2, 0)*48+j))\n for(i <- 0 to 8)\n poke(dut.io.weight_in(i), weight_bank(rd_w*9+i))\n \n var addr_str = \"\"\n\n for(i <- 0 to 4)\n addr_str += \"(\"+get_addr(1, i)+\", \"+get_id(1, i)+\"), \"\n println(\"rd_addr1: \"+addr_str)\n addr_str = \"\"\n for(i <- 0 to 4)\n addr_str += \"(\"+get_addr(2, i)+\", \"+get_id(2, i)+\"), \"\n println(\"rd_addr2: \"+addr_str)\n\n read_reg = 0\n } else {\n poke(dut.io.rd_valid_in, false)\n }\n if(peek(dut.io.wr_valid_out)==1){\n //stop = 1\n var addr_str = \"\"\n \n for(i <- 0 to 2)\n addr_str += \"(\"+peek(dut.io.wr_addr.addrs(i).addr)+\", \"+peek(dut.io.wr_addr.addrs(i).bank_id)+\"), \"\n println(\"wr_addr1: \"+addr_str)\n\n println(\"Written Result:\")\n for(j <- 0 to 7){\n var str = peek(dut.io.to_smallbank(0).data(j)).toString()+\" \"\n for(k <- 0 to 5){\n var x = peek(dut.io.to_bigbank.data(j*6+k)).toString()\n //expect(result.mat(j*8+k), std(j)(k))\n str = str+x+\" \"\n } \n str = str+peek(dut.io.to_smallbank(1).data(j)).toString()+\" \"\n println(str)\n }\n\n }\n if(peek(dut.io.test_valid_out)==1){\n println(\"Switch Result:\")\n for(j <- 0 to 9){\n var str = \"\"\n if(j==0){ \n for(k <- 0 to 9){\n var x = peek(dut.io.packed.up(k)).toString()\n //expect(result.mat(j*8+k), std(j)(k))\n str = str+x+\" \"\n }\n } else if(j>=1&&j<=8) {\n str = str+peek(dut.io.packed.left(j-1)).toString()+\" \"\n for(k <- 0 to 7){\n var x = peek(dut.io.packed.mat((j-1)*8+k)).toString()\n //expect(result.mat(j*8+k), std(j)(k))\n str = str+x+\" \"\n } \n str = str+peek(dut.io.packed.right(j-1)).toString()+\" \"\n } else {\n for(k <- 0 to 9){\n var x = peek(dut.io.packed.down(k)).toString()\n //expect(result.mat(j*8+k), std(j)(k))\n str = str+x+\" \"\n }\n }\n \n println(str)\n }\n\n }\n step(1)\n }\n}\n\n\n\nclass ConvSpec extends FlatSpec with Matchers {\n /*\n it should \"Conv should pass\" in {\n val w = 16\n val h_w = 16\n val c_w = 16\n val id_w = 16\n val addr_w = 16\n val bias_w = 36\n val big_w = 16\n val num = 1\n chisel3.iotesters.Driver(() => new Global1(w, h_w, c_w, id_w, big_w, addr_w, bias_w, num)) { c =>\n new ConvTester(c, w, h_w, c_w, id_w, big_w, addr_w, bias_w, num)\n } should be (true)\n }*/\n}\n", "groundtruth": " var t2 = bank_id_small(j%2)(if(i%2==1) 0 else 2)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "fpga_final_project", "path": "fpga_final_project/src/test/scala/gcd/test_leakyrelu.scala", "left_context": "// See README.md for license details.\n\npackage final_project\n\nimport chisel3._\nimport chisel3.tester._\nimport org.scalatest._\nimport chisel3.experimental.BundleLiterals._\nimport chisel3.iotesters._\n\nclass LeakyReLUTester(dut: Calc8x8) extends PeekPokeTester(dut) {\n\n //val rnd = new scala.util.Random\n var A = Array.tabulate(8, 8) {\n (i, j) => rnd.nextInt(65536)-32768\n }\n for(i <- 0 to 63){\n poke(dut.io.input.mat(i), A(i/8)(i%8))\n }\n\n\n val std = Array.tabulate(8, 8) {\n (i, j) => {\n", "right_context": " }\n }\n\n poke(dut.io.flag, 1)\n poke(dut.io.mask, 1)\n poke(dut.io.valid_in, true)\n var stop = false\n var fuck = 0\n while(!stop&&fuck<=20){\n step(1)\n fuck += 1\n println(\"[valid: \" + peek(dut.io.valid_out).toString + \"] Result:\")\n if(peek(dut.io.valid_out)==1){\n for(j <- 0 to 7){\n var str = \"\"\n for(k <- 0 to 7){\n var x = peek(dut.io.output(0).mat(j*8+k)).toString()\n expect(dut.io.output(0).mat(j*8+k), std(j)(k))\n str = str+x+\" \"\n } \n println(str)\n }\n\n stop = true\n }\n \n }\n \n}\n\n\nclass LeakyReLUSpec extends FlatSpec with Matchers {\n\n it should \"LeakyReLU should pass\" in {\n chisel3.iotesters.Driver(() => new Calc8x8(16, 4)) { c =>\n new LeakyReLUTester(c)\n } should be (true)\n }\n}\n", "groundtruth": " if(A(i)(j)<0) A(i)(j)*6554 else A(i)(j)*32768\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "fpga_final_project", "path": "fpga_final_project/src/test/scala/gcd/test_maxpool.scala", "left_context": "package final_project\n\nimport chisel3._\nimport chisel3.util._\n\nimport chisel3._\nimport chisel3.tester._\nimport org.scalatest._\nimport chisel3.experimental.BundleLiterals._\nimport chisel3.iotesters._\n\nclass Global2(_w: Int, h_w: Int, c_w: Int, id_w: Int, big_w: Int, addr_w: Int, bias_w: Int, num: Int) extends Module{\n val io = IO(new Bundle{\n val rd_addr1 = Output(new AddressReadGroup(addr_w, id_w))\n val rd_addr2 = Output(new AddressReadGroup(addr_w, id_w))\n val rd_big = Input(Vec(2, new BigBankReadData(_w)))\n val rd_small = Input(Vec(2, Vec(4, new SmallBankReadData(_w))))\n val rd_valid_in = Input(Bool())\n val rd_valid_out = Output(Bool())\n val weight_addr = Output(UInt(addr_w.W))\n val weight_in = Input(Vec(9, SInt(16.W)))\n val wr_addr = Output(new AddressWriteGroup(addr_w, id_w))\n val bias_in = Input(SInt(bias_w.W))\n val bias_addr = Output(UInt(addr_w.W))\n val packed = Output(new PackedData(_w))\n //val wr_small = Output(Vec(4, UInt((_w*8).W)))\n //val wr_big = Output(Vec(1, UInt((_w*48).W)))\n val quanted = Output(new QuantedData(_w))\n val wr_valid_out = Output(Bool())\n val test_valid_out = Output(Bool())\n val to_bigbank = Output(new BigBankWriteData(_w))\n val to_smallbank = Output(Vec(2, new SmallBankWriteData(_w)))\n })\n\n\n\n\n val reader1 = Module(new GraphReader(addr_w, h_w, c_w, id_w, big_w)).io\n val reader2 = Module(new GraphReader(addr_w, h_w, c_w, id_w, big_w)).io\n val read_pack = Module(new PackReadData(_w, h_w, c_w, big_w)).io\n val read_switch = Module(new ReadSwitch(_w, h_w, c_w, 1)).io\n val read_weight = Module(new WeightReader(_w, addr_w)).io\n val calc8x8 = Module(new Calc8x8(_w, 1)).io\n val accu = Module(new Accumu(_w, addr_w, bias_w, 1)).io\n val quant = Module(new Quant(_w)).io\n val write_switch = Module(new WriteSwitch(_w, 3)).io\n val writer = Module(new RealWriter(_w, addr_w, h_w, c_w, id_w)).io\n val maxpool = Module(new Maxpool(_w)).io\n \n io.rd_addr1 := 0.U.asTypeOf(io.rd_addr1)\n io.rd_addr2 := 0.U.asTypeOf(io.rd_addr2)\n io.rd_valid_out := false.B\n io.weight_addr := 0.U.asTypeOf(io.weight_addr)\n\n\n io.rd_addr1 := reader1.to_banks\n reader1.flag_job := false.B\n reader1.valid_in := false.B\n reader1.job := 0.U.asTypeOf(reader1.job)\n reader1.job_type := 0.U.asTypeOf(reader1.job_type)\n\n io.rd_valid_out := reader2.valid_out\n io.rd_addr2 := reader2.to_banks\n reader2.flag_job := false.B\n reader2.valid_in := false.B\n reader2.job := 0.U.asTypeOf(reader2.job)\n reader2.job_type := 0.U.asTypeOf(reader2.job_type)\n\n read_weight.valid_in := false.B\n read_weight.addr_end := 0.U\n read_weight.begin_addr := 0.U\n io.weight_addr := read_weight.addr\n read_weight.flag_job := false.B\n \n\n read_pack.valid_in := io.rd_valid_in\n read_pack.flag_job := false.B\n read_pack.job := 0.U.asTypeOf(read_pack.job)\n read_pack.from_big := io.rd_big\n read_pack.from_small := io.rd_small\n\n \n \n read_switch.flag_job := false.B\n read_switch.job := 0.U.asTypeOf(read_switch.job)\n read_switch.valid_in := read_pack.valid_out\n read_switch.from := read_pack.output\n read_switch.from_weight(0) := io.weight_in\n read_switch.in_h := 0.U\n read_switch.in_chan := 0.U\n\n calc8x8.input := read_switch.to_calc8x8\n calc8x8.flag := 0.U.asTypeOf(calc8x8.flag)\n calc8x8.weight := read_switch.to_weight\n calc8x8.valid_in := read_switch.valid_out_calc8x8\n calc8x8.mask := 0.U\n calc8x8.multmap := read_switch.to_multmap\n\n \n \n accu.in_from_calc8x8 := calc8x8.output\n accu.valid_in := calc8x8.valid_out\n accu.flag_job := false.B\n accu.csum := 0.U\n accu.bias_begin_addr := 0.U\n accu.bias_end_addr := 0.U\n io.bias_addr := accu.bias_addr\n accu.bias_in(0) := io.bias_in\n accu.is_in_use := false.B\n\n\n quant.in_from_accumu := accu.result(0)\n quant.valid_in := accu.valid_out(0)\n quant.flag_job := false.B\n quant.quant_in := 0.U.asTypeOf(quant.quant_in)\n\n \n maxpool.from_big := io.rd_big\n for(t <- 0 to 1){\n maxpool.from_small(t)(0) := io.rd_small(t)(0)\n maxpool.from_small(t)(1) := io.rd_small(t)(1)\n }\n \n maxpool.valid_in := read_switch.valid_out_maxp\n\n //write_switch.valid_in(1) := false.B\n //write_switch.input(1) := 0.U.asTypeOf(write_switch.input(1))\n\n write_switch.valid_in(0) := quant.valid_out // conv\n write_switch.valid_in(1) := maxpool.valid_out // maxpool\n write_switch.valid_in(2) := read_switch.valid_out_copy // go through\n\n write_switch.input(0) := quant.result\n write_switch.input(1) := maxpool.result\n write_switch.input(2) := read_switch.to_copy\n\n writer.in_from_quant := write_switch.output\n writer.valid_in := write_switch.valid_out\n writer.flag_job := false.B\n writer.job := 0.U.asTypeOf(writer.job)\n io.wr_addr := writer.to_banks\n io.to_bigbank := writer.to_bigbank\n io.to_smallbank := writer.to_smallbank\n io.wr_valid_out := writer.valid_out\n \n /*\n io.wr_addr := 0.U.asTypeOf(io.wr_addr)\n io.to_bigbank := 0.U.asTypeOf(io.to_bigbank)\n io.to_smallbank := 0.U.asTypeOf(io.to_smallbank)\n io.wr_valid_out := false.B\n io.bias_addr := 0.U*/\n\n \n io.quanted := quant.result\n io.test_valid_out := calc8x8.valid_out\n // io.quanted := read_pack.output\n\n io.packed := 0.U.asTypeOf(io.packed)\n io.packed.mat := calc8x8.output(0).mat\n /*\n // w, h, wr_w, wr_h\n // in out chan\n // para\n // big addr\n // wr big addr\n // small addr\n // wr small addr\n */\n val paras = GenAllPara(addr_w, h_w, c_w, id_w, big_w,\n 2, 2, 2, 2, \n 2, 2, \n 1, 1, \n 0, 1023, 0, \n 1020, 1023, 0, \n 0, 1023, 0, \n 1020, 1023, 0, \n 0, 0, 17, 16\n )\n \n \n val state = RegInit(0.U(3.W))\n switch(state){\n is(0.U){\n paras.set_maxp_reader1(reader1)\n paras.set_maxp_reader2(reader2)\n paras.set_write(writer)\n paras.set_maxpool_switch(read_switch)\n\n state := 1.U\n }\n is(1.U){\n reader1.valid_in := true.B\n reader2.valid_in := true.B\n\n }\n }\n}\n\n\nclass MaxpoolTester(dut: Global2, _w: Int, h_w: Int, c_w: Int, id_w: Int, addr_w: Int, bias_w: Int, num: Int) extends PeekPokeTester(dut){\n \n var bank_id_big = Array(0, 1)\n var bank_id_small = Array(Array(3, 0, 1, 2), Array(7, 4, 5, 6))\n var (w, h) = (2, 2)\n var (in_chan, out_chan) = (2, 2)\n var A = Array.tabulate(8*8*w*h, in_chan){\n (i, ic) => i*in_chan+ic\n }\n var small_bank = Array.fill[Int](10, (h/2)*(w/2)*8*in_chan+64*in_chan)(0)\n var big_bank = Array.fill[Int](10, (h/2)*w*48*in_chan+64*in_chan)(0)\n for(i <- 0 to w-1)\n for(j <- 0 to h-1){\n var t1 = bank_id_small(j%2)(if(i%2==1) 3 else 1)\n var t2 = bank_id_small(j%2)(if(i%2==1) 0 else 2)\n for(ic <- 0 to in_chan-1){\n for(k <- 0 to 7){\n small_bank(t1)((i/2)*(h/2)*8*in_chan+(j/2)*8*in_chan+ic*8+k) = A((i*h+j)*64+k*8)(ic)\n small_bank(t2)((i/2)*(h/2)*8*in_chan+(j/2)*8*in_chan+ic*8+k) = A((i*h+j)*64+k*8+7)(ic)\n }\n for(k <- 0 to 7)\n for(l <- 0 to 5){\n big_bank(bank_id_big(j%2))(i*(h/2)*48*in_chan+(j/2)*48*in_chan+ic*48+(k*6+l)) = A((i*h+j)*64+k*8+l+1)(ic)\n }\n }\n \n }\n var weight_bank = Array.fill[Int](9*in_chan*out_chan)(0)\n var bias_bank = Array.tabulate(out_chan){\n i => i\n }\n for(i <- 0 to out_chan-1)\n for(j <- 0 to in_chan-1){\n val B = Array.tabulate(3, 3) {\n (i, j) => i*3+j\n }\n for(k <- 0 to 8)\n weight_bank((i*in_chan+j)*9+k) = B(k/3)(k%3)\n }\n var read_reg = 0\n var T = 0\n var stop = 0\n\n val std = Array.tabulate(8, 8, 2){\n (i, j, t) => {\n var mx = 0\n for(x <- i*2 to i*2+1)\n for(y <- j*2 to j*2+1)\n if(mx < A(((y/8)*h+(x/8))*64+(x%8)*8+(y%8))(t))\n mx = A(((y/8)*h+(x/8))*64+(x%8)*8+(y%8))(t)\n mx\n }\n }\n\n var tt = 0\n while(T<20&&(stop==0)){\n T += 1\n val rd_bias = peek(dut.io.bias_addr).toInt\n poke(dut.io.bias_in, bias_bank(rd_bias))\n if(peek(dut.io.rd_valid_out)==1){\n poke(dut.io.rd_valid_in, true)\n val rd_w = (peek(dut.io.weight_addr)).toInt\n val vis = Array.fill[Int](10, 10)(0)\n val vis_id = Array.fill[Int](10, 10)(0)\n def get_addr(i: Int, j: Int): Int = {\n if(vis(i)(j)!=0) return vis(i)(j)\n //println(\"(\"+i+\",\"+j+\") addr: \"+(if(i==1) (peek(dut.io.rd_addr1.addrs(j).addr)).toInt else (peek(dut.io.rd_addr2.addrs(j).addr)).toInt))\n", "right_context": " return vis(i)(j)\n }\n def get_id(i: Int, j: Int): Int = {\n if(vis_id(i)(j)!=0) return vis_id(i)(j)\n //return 0\n //println(\"(\"+i+\",\"+j+\") addr: \"+(if(i==1) (peek(dut.io.rd_addr1.addrs(j).bank_id)).toInt else (peek(dut.io.rd_addr2.addrs(j).bank_id)).toInt))\n vis_id(i)(j) = (if(i==1) (peek(dut.io.rd_addr1.addrs(j).bank_id)).toInt else (peek(dut.io.rd_addr2.addrs(j).bank_id)).toInt)\n return vis_id(i)(j)\n }\n for(i <- 1 to 4){\n for(j <- 0 to 7)\n poke(dut.io.rd_small(0)(i-1).data(j), small_bank(get_id(1, i))(get_addr(1, i)*8+j))\n }\n for(j <- 0 to 47) \n poke(dut.io.rd_big(0).data(j), big_bank(get_id(1, 0))(get_addr(1, 0)*48+j))\n for(i <- 1 to 4){\n for(j <- 0 to 7)\n poke(dut.io.rd_small(1)(i-1).data(j), small_bank(get_id(2, i))(get_addr(2, i)*8+j))\n }\n for(j <- 0 to 47) \n poke(dut.io.rd_big(1).data(j), big_bank(get_id(2, 0))(get_addr(2, 0)*48+j))\n for(i <- 0 to 8)\n poke(dut.io.weight_in(i), weight_bank(rd_w*9+i))\n \n var addr_str = \"\"\n\n for(i <- 0 to 4)\n addr_str += \"(\"+get_addr(1, i)+\", \"+get_id(1, i)+\"), \"\n println(\"rd_addr1: \"+addr_str)\n addr_str = \"\"\n for(i <- 0 to 4)\n addr_str += \"(\"+get_addr(2, i)+\", \"+get_id(2, i)+\"), \"\n println(\"rd_addr2: \"+addr_str)\n\n read_reg = 0\n } else {\n poke(dut.io.rd_valid_in, false)\n }\n if(peek(dut.io.wr_valid_out)==1){\n //stop = 1\n var addr_str = \"\"\n \n for(i <- 0 to 2)\n addr_str += \"(\"+peek(dut.io.wr_addr.addrs(i).addr)+\", \"+peek(dut.io.wr_addr.addrs(i).bank_id)+\"), \"\n println(\"wr_addr1: \"+addr_str)\n\n println(\"Written Result:\")\n for(j <- 0 to 7){\n var str = peek(dut.io.to_smallbank(0).data(j)).toString()+\" \"\n expect(dut.io.to_smallbank(0).data(j), std(j)(0)(tt))\n for(k <- 0 to 5){\n var x = peek(dut.io.to_bigbank.data(j*6+k)).toString()\n expect(dut.io.to_bigbank.data(j*6+k), std(j)(k+1)(tt))\n str = str+x+\" \"\n } \n str = str+peek(dut.io.to_smallbank(1).data(j)).toString()+\" \"\n expect(dut.io.to_smallbank(1).data(j), std(j)(7)(tt))\n println(str)\n }\n\n tt = tt+1\n }\n step(1)\n }\n}\n\n\n\nclass MaxpoolSpec extends FlatSpec with Matchers {\n /*\n it should \"Maxpool should pass\" in {\n val w = 16\n val h_w = 16\n val c_w = 16\n val id_w = 16\n val addr_w = 16\n val bias_w = 36\n val big_w = 16\n val num = 1\n chisel3.iotesters.Driver(() => new Global2(w, h_w, c_w, id_w, big_w, addr_w, bias_w, num)) { c =>\n new MaxpoolTester(c, w, h_w, c_w, id_w, addr_w, bias_w, num)\n } should be (true)\n }*/\n}\n", "groundtruth": " vis(i)(j) = (if(i==1) (peek(dut.io.rd_addr1.addrs(j).addr)).toInt else (peek(dut.io.rd_addr2.addrs(j).addr)).toInt)\n", "crossfile_context": "", "category": "Testbench Stimulus and Environment", "subcategory": "Stimulus Generation", "confidence": 0.85, "category_reason": "Chisel test harness (poke/peek/step)"} {"task_id": "fpga_final_project", "path": "fpga_final_project/src/test/scala/gcd/test_read_conv.scala", "left_context": "// See README.md for license details.\n\npackage final_project\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.tester._\nimport org.scalatest._\nimport chisel3.experimental.BundleLiterals._\nimport chisel3.iotesters._\n\nclass ReadConvTestModule(addr_w: Int, h_w: Int, c_w: Int, id_w: Int, loop_num: Int, loop_h: Int, \n h: Int, w: Int, in_chan: Int, begin_addr: Int, min_addr: Int, max_addr: Int,\n small_begin_addr: Int, small_min_addr: Int, small_max_addr: Int, \n bank_id_big: Int, bank_id_small: Array[Int]) extends Module{\n val io = IO(new Bundle{\n val start = Input(Bool())\n val valid_out = Output(Bool())\n val to_banks = Output(new AddressReadGroup(addr_w, id_w))\n })\n val r = Module(new GraphReader(addr_w, h_w, c_w, id_w, 16))\n val state = RegInit(0.U(2.W))\n \n r.io.flag_job := false.B\n r.io.job := 0.U.asTypeOf(r.io.job)\n r.io.job2 := 0.U.asTypeOf(r.io.job2)\n r.io.signal := false.B\n r.io.job_type := 0.U.asTypeOf(r.io.job_type)\n r.io.valid_in := false.B\n io.to_banks := r.io.to_banks\n io.valid_out := r.io.valid_out\n when(io.start){\n state := 1.U\n }.otherwise{\n switch(state){\n is(1.U){\n r.io.flag_job := true.B\n r.io.job_type := ReadType.toConvOrCopy\n r.io.job := GenConvReadJob.gen(\n addr_w, h_w, c_w, id_w, 16, loop_num, 0, loop_h, \n h, w, in_chan, begin_addr, max_addr, min_addr, small_begin_addr, small_min_addr, small_max_addr,\n bank_id_big, bank_id_small\n )\n r.io.valid_in := true.B\n state := 2.U\n }\n is(2.U){\n r.io.flag_job := false.B\n r.io.valid_in := true.B\n r.io.job_type := ReadType.toConvOrCopy\n state := 2.U\n }\n }\n }\n}\n\nclass ReadConvTester(dut: ReadConvTestModule, std: Array[Array[Tuple2[Int, Int]]]) extends PeekPokeTester(dut) {\n poke(dut.io.start, true.B)\n step(1)\n poke(dut.io.start, false.B)\n step(1)\n for(i <- 0 to 10000){\n var str = \"\"\n str = str+\"[\"+peek(dut.io.valid_out)+\"]\"\n for(j <- 0 to 4){\n str = str+\"(\"+peek(dut.io.to_banks.addrs(j).bank_id)+\",\"+peek(dut.io.to_banks.addrs(j).addr)+\"), \"\n if(std(i)(j)._1!=(-1)&&peek(dut.io.valid_out)==1){\n expect(dut.io.to_banks.addrs(j).bank_id, std(i)(j)._1)\n expect(dut.io.to_banks.addrs(j).addr, std(i)(j)._2) \n }\n }\n if(i%100==0)\n println(str)\n step(1)\n }\n}\n\n\nclass ReadConvSpec extends FlatSpec with Matchers {\n\n\n it should \"ReadConv should pass\" in {\n var (h, w) = (4, 4)\n var in_chan = 16\n var (begin_addr, max_addr, min_addr) = (990, 1010, 12)\n var (small_begin_addr, small_max_addr, small_min_addr) = (540, 600, 29)\n var bank_id_big = 0\n var bank_id_small = Array(4, 1, 2, 3)\n var loop_num = 32\n var loop_h = 1\n\n var std = Array.tabulate(100000, 5){\n (i, j) => (0, 0)\n }\n\n def f(x: Int, L: Int, R: Int): Int = {\n return (x-L)%(R-L+1)+L\n }\n\n var x = 0\n for(i <- 0 to w-1)\n for(c <- 0 to loop_h-1)\n for(j <- 0 to h-1)\n for(t <- 0 to loop_num-1)\n for(k <- 0 to in_chan-1){\n std(x)(1) = (\n (if(i==0) -1 else bank_id_small(if(i%2==0) 0 else 2)),\n f((((i-1)/2)*h+j)*in_chan+k+small_begin_addr, small_min_addr, small_max_addr)\n )\n std(x)(2) = (\n", "right_context": " f(((i/2)*(h)+j)*in_chan+k+small_begin_addr, small_min_addr, small_max_addr)\n )\n std(x)(3) = (\n bank_id_small(if(i%2==0) 2 else 0),\n f(((i/2)*(h)+j)*in_chan+k+small_begin_addr, small_min_addr, small_max_addr)\n )\n std(x)(4) = (\n (if(i==w-1) -1 else bank_id_small(if(i%2==0) 3 else 1)),\n f((((i+1)/2)*(h)+j)*in_chan+k+small_begin_addr, small_min_addr, small_max_addr)\n )\n std(x)(0) = (\n bank_id_big,\n f((i*(h)+j)*in_chan+k+begin_addr, min_addr, max_addr)\n )\n x += 1\n }\n\n\n chisel3.iotesters.Driver(() => new ReadConvTestModule(10, 3, 6, 4, loop_num, loop_h, \n h, w, in_chan, begin_addr, max_addr, min_addr, small_begin_addr, small_min_addr, small_max_addr,\n bank_id_big, bank_id_small\n )) { c =>\n new ReadConvTester(c, std)\n } should be (true)\n }\n}\n", "groundtruth": " bank_id_small(if(i%2==0) 1 else 3),\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "fpga_final_project", "path": "fpga_final_project/src/test/scala/gcd/test_write_conv.scala", "left_context": "// See README.md for license details.\n\npackage final_project\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.tester._\nimport org.scalatest._\nimport chisel3.experimental.BundleLiterals._\nimport chisel3.iotesters._\n\nclass WriteConvTestModule(addr_w: Int, h_w: Int, c_w: Int, id_w: Int, \n h: Int, w: Int, in_chan: Int, begin_addr: Int, min_addr: Int, max_addr: Int,\n small_begin_addr: Int, small_min_addr: Int, small_max_addr: Int, \n bank_id_big: Int, bank_id_small: Array[Int], al: Int, ar: Int) extends Module{\n val io = IO(new Bundle{\n val start = Input(Bool())\n val valid_out = Output(Bool())\n val to_banks = Output(new AddressWriteGroup(addr_w, id_w))\n })\n val r = Module(new Writer(16, addr_w, h_w, c_w, id_w))\n val state = RegInit(0.U(2.W))\n \n r.io.flag_job := false.B\n r.io.job := 0.U.asTypeOf(r.io.job)\n r.io.valid_in := false.B\n r.io.in_from_quant := 0.U.asTypeOf(r.io.in_from_quant)\n io.to_banks := r.io.to_banks\n io.valid_out := r.io.valid_out\n when(io.start){\n state := 1.U\n }.otherwise{\n switch(state){\n is(1.U){\n r.io.flag_job := true.B\n r.io.job := GenWriteConvJob.gen(\n addr_w, h_w, c_w, id_w,\n h, w, in_chan, begin_addr, max_addr, min_addr, small_begin_addr, small_min_addr, small_max_addr,\n bank_id_big, bank_id_small, al, ar\n )\n r.io.valid_in := true.B\n state := 2.U\n }\n is(2.U){\n r.io.flag_job := false.B\n r.io.valid_in := true.B\n state := 2.U\n }\n }\n }\n}\n\nclass WriteConvTester(dut: WriteConvTestModule, std: Array[Array[Tuple2[Int, Int]]]) extends PeekPokeTester(dut) {\n poke(dut.io.start, true.B)\n step(1)\n poke(dut.io.start, false.B)\n step(1)\n for(i <- 0 to 3000){\n var str = \"\"\n str = str+\"[\"+peek(dut.io.valid_out)+\"]\"\n for(j <- 0 to 2){\n str = str+\"(\"+peek(dut.io.to_banks.addrs(j).bank_id)+\",\"+peek(dut.io.to_banks.addrs(j).addr)+\"), \"\n if(std(i)(j)._1!=(-1)&&peek(dut.io.valid_out)==1){\n expect(dut.io.to_banks.addrs(j).bank_id, std(i)(j)._1)\n expect(dut.io.to_banks.addrs(j).addr, std(i)(j)._2) \n }\n }\n //if(i%100==0)\n println(str)\n step(1)\n }\n}\n\n\nclass WriteConvSpec extends FlatSpec with Matchers {\n\n\n it should \"WriteConv should pass\" in {\n var (h, w) = (8, 8)\n var in_chan = 64\n var (begin_addr, max_addr, min_addr) = (990, 1010, 12)\n var (small_begin_addr, small_max_addr, small_min_addr) = (540, 600, 29)\n var bank_id_big = 0\n var bank_id_small = Array(1, 2, 3, 4)\n var al = 32\n var ar = 63\n\n var std = Array.tabulate(10000, 3){\n (i, j) => (-1, 0)\n }\n\n def f(x: Int, L: Int, R: Int): Int = {\n return (x-L)%(R-L+1)+L\n }\n\n var x = 0\n for(i <- 0 to w-1)\n for(j <- 0 to h-1)\n for(k <- al to ar){\n std(x)(1) = (\n", "right_context": " f((((i)/2)*h+j)*in_chan+k+small_begin_addr, small_min_addr, small_max_addr)\n )\n std(x)(2) = (\n bank_id_small(if(i%2==0) 1 else 3),\n f(((i/2)*(h)+j)*in_chan+k+small_begin_addr, small_min_addr, small_max_addr)\n )\n std(x)(0) = (\n bank_id_big,\n f((i*(h)+j)*in_chan+k+begin_addr, min_addr, max_addr)\n )\n x += 1\n }\n\n\n chisel3.iotesters.Driver(() => new WriteConvTestModule(10, 3, 6, 3, \n h, w, in_chan, f(begin_addr+al, min_addr, max_addr), max_addr, min_addr, f(small_begin_addr+al, small_min_addr, small_max_addr), small_min_addr, small_max_addr,\n bank_id_big, bank_id_small, al, ar\n )) { c =>\n new WriteConvTester(c, std)\n } should be (true)\n }\n}\n", "groundtruth": " bank_id_small(if(i%2==0) 0 else 2),\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "magma-si", "path": "magma-si/src/main/scala/components/AdderSwitch.scala", "left_context": "package magmasi.components\n\nimport chisel3._\nimport chisel3.util._\n\nclass AdderSwitch(DATA_TYPE: Int = 32, NUM_IN: Int = 2, SEL_IN: Int = 2,NUM_OUT: Int =2) extends Module {\n val io = IO(new Bundle {\n val i_valid = Input(Bool())\n val i_data_bus = Input(Vec(NUM_IN, UInt(DATA_TYPE.W)))\n val i_add_en = Input(UInt(3.W))\n val i_cmd = Input(UInt(3.W))\n val i_sel = Input(UInt(SEL_IN.W))\n val o_vn_valid = Output(UInt(NUM_OUT.W))\n val o_vn = Output(UInt((2 * DATA_TYPE).W))\n val o_adder = Output(Vec(NUM_OUT, UInt(DATA_TYPE.W)))\n })\n\n val clk = clock\n val rst = reset.asBool\n\n val reductionMux = Module(new ReductionMux(W = DATA_TYPE, NUM_IN = NUM_IN, SEL_IN = SEL_IN))\n reductionMux.io.i_data := io.i_data_bus\n reductionMux.io.i_sel := io.i_sel\n\n val adder32 = Module(new SimpleAdder)\n adder32.io.A := reductionMux.io.o_data(1)\n adder32.io.B := reductionMux.io.o_data(0)\n\n val r_adder = RegInit(0.U((2 * DATA_TYPE).W))\n val r_vn = RegInit(0.U((2 * DATA_TYPE).W))\n val r_vn_valid = RegInit(0.U(2.W))\n val r_add_en = RegNext(io.i_add_en, init = 0.U)\n\n when (rst) {\n r_adder := 0.U\n r_vn := 0.U\n r_vn_valid := 0.U\n } .elsewhen (io.i_valid) {\n switch (io.i_cmd) {\n is (\"b001\".U) {\n r_adder := Cat(reductionMux.io.o_data)\n r_vn_valid := 0.U\n }\n is (\"b011\".U) {\n r_adder := Cat(0.U((DATA_TYPE - 1).W), reductionMux.io.o_data(1))\n r_vn := io.i_data_bus(0)\n r_vn_valid := 1.U\n }\n is (\"b100\".U) {\n r_adder := Cat(reductionMux.io.o_data(0), 0.U((DATA_TYPE - 1).W))\n r_vn := io.i_data_bus(1)\n r_vn_valid := 2.U\n }\n", "right_context": " }\n }\n\n when (rst) {\n io.o_adder := VecInit(Seq.fill(2)(0.U(DATA_TYPE.W)))\n io.o_vn := 0.U\n io.o_vn_valid := 0.U\n } .otherwise {\n when (!r_add_en) {\n io.o_adder := VecInit(Seq(r_adder(DATA_TYPE - 1, 0), r_adder(2 * DATA_TYPE - 1, DATA_TYPE)))\n } .otherwise {\n io.o_adder := VecInit(Seq.fill(2)(adder32.io.O))\n }\n io.o_vn := r_vn\n io.o_vn_valid := r_vn_valid\n }\n}\n", "groundtruth": " is (\"b101\".U) {\n r_vn := Cat(reductionMux.io.o_data)\n r_vn_valid := 3.U\n }\n", "crossfile_context": "", "category": "Computation Block", "subcategory": "Type Casting and Conversion", "confidence": 0.75, "category_reason": "Cat/Fill operation"} {"task_id": "magma-si", "path": "magma-si/src/main/scala/components/Benes.scala", "left_context": "/* This Module is translated into CHISEL from https://github.com/georgia-tech-synergy-lab/SIGMA/blob/master/vmod/benes.v */\npackage magmasi.components\n\nimport chisel3._\nimport chisel3.util._\n\n/*\nSample Indexing Diagram with 4 PES example\n\nTable:\n O --> switch (regular)\n $\t --> input switch\n # --> output switch\n\n----------------------------------------------------------------------------------------------- \nData IO Diagram: \n\nr_data_bus_ff[Element 0] --> $ 0 0 0 0 0 # --> w_dist_bus[Element 0]\n\nr_data_bus_ff[Element 1] --> $ 0 0 0 0 0 # --> w_dist_bus[Element 1]\n\nr_data_bus_ff[Element 2] --> $ 0 0 0 0 0 # --> w_dist_bus[Element 2]\n\nr_data_bus_ff[Element 3] --> $ 0 0 0 0 0 # --> w_dist_bus[Element 3]\n\n----------------------------------------------------------------------------------------------- \nHorizontal Internal Wires Diagram: (between each switch) \n\n\n$ w_internal[0] O w_internal[2] O w_internal[4] O w_internal[6] # \n\n$ w_internal[8] O w_internal[10] O w_internal[12] O w_internal[14] # \n\n$ w_internal[16] O w_internal[18] O w_internal[20] O w_internal[22] # \n\n$ w_internal[24] O w_internal[26] O w_internal[28] O w_internal[30] # \n\n----------------------------------------------------------------------------------------------- \nDiagonal Internal Wires Diagram: (between each switch)\n\n$ w_internal[1] O w_internal[3] O w_internal[5] O w_internal[7] # \n\n$ w_internal[9] O w_internal[11] O w_internal[13] O w_internal[15] # \n\n$ w_internal[17] O w_internal[19] O w_internal[21] O w_internal[23] # \n\n$ w_internal[25] O w_internal[27] O w_internal[29] O w_internal[31] # \n\n----------------------------------------------------------------------------------------------- \nMux Select Signals Diagram (inputs to each switch)\n\t* input switch does not require any control signals --> value will go to both horizontal and diagonal\n\t* output switch only requires one control bit\n\nNA r_mux_bus_ff[0,1] r_mux_bus_ff[2,3] r_mux_bus_ff[4,5] r_mux_bus_ff[24] \nNA r_mux_bus_ff[6,7] r_mux_bus_ff[8,9] r_mux_bus_ff[10,11] r_mux_bus_ff[25]\nNA r_mux_bus_ff[12,13] r_mux_bus_ff[14,15] r_mux_bus_ff[16,17]\t r_mux_bus_ff[26]\nNA r_mux_bus_ff[18,19]\t r_mux_bus_ff[20,21]\t r_mux_bus_ff[22,23] r_mux_bus_ff[27]\n\n----------------------------------------------------------------------------------------------- \n*/\n\nclass Benes(implicit val config: MagmasiConfig) extends Module {\n val LEVELS : Int = (2 * (math.log(config.NUM_PES) / math.log(2))).toInt + 1\n val io = IO(new Bundle {\n\n val i_data_bus2 = Input(Vec(config.NUM_PES, UInt(config.DATA_TYPE.W)))\n val i_data_bus1 = Input(Vec(config.NUM_PES, UInt(config.DATA_TYPE.W)))\n val i_mux_bus = Input(Vec(2 * (LEVELS - 2) * config.NUM_PES + config.NUM_PES, Bool()))\n val o_dist_bus2 = Output(Vec(config.NUM_PES, UInt(config.DATA_TYPE.W)))\n val o_dist_bus1 = Output(Vec(config.NUM_PES, UInt(config.DATA_TYPE.W)))\n\n })\n io.o_dist_bus1 := io.i_data_bus1\n val clk = clock\n val rst = reset.asBool\n\n val r_data_bus_ff = RegInit(VecInit(Seq.fill(config.NUM_PES)(0.U(config.DATA_TYPE.W))))\n val r_mux_bus_ff = RegInit(VecInit(Seq.fill(2 * (LEVELS - 2) * config.NUM_PES + config.NUM_PES)(false.B)))\n val w_dist_bus = Wire(Vec(config.NUM_PES, UInt(config.DATA_TYPE.W)))\n val w_internal = Wire(Vec(2 * config.NUM_PES * (LEVELS - 1), UInt(config.DATA_TYPE.W))) // 8 x 2 = 16\n\n dontTouch(w_internal)\n\n r_data_bus_ff := Mux(rst, VecInit(Seq.fill(config.NUM_PES)(0.U(config.DATA_TYPE.W))), io.i_data_bus2)\n r_mux_bus_ff := Mux(rst, VecInit(Seq.fill(2 * (LEVELS - 2) * config.NUM_PES + config.NUM_PES)(false.B)), io.i_mux_bus)\n io.o_dist_bus2 := Mux(rst, VecInit(Seq.fill(config.NUM_PES)(0.U(config.DATA_TYPE.W))), w_dist_bus)\n\n for (i <- 0 until config.NUM_PES) {\n\n val in_switch = Module(new InputSwitch(config.DATA_TYPE))\n in_switch.io.in := r_data_bus_ff(i)\n w_internal(2 * i * (LEVELS - 1)) := in_switch.io.y\n w_internal(2 * i * (LEVELS - 1) + 1) := in_switch.io.z\n\n }\n\n for (i <- 0 until config.NUM_PES) { \n\n val out_switch = Module(new OutputSwitch(config.DATA_TYPE))\n out_switch.io.in0 := w_internal(2 * i * (LEVELS - 1) + (2 * (LEVELS - 2)))\n", "right_context": " out_switch.io.sel := r_mux_bus_ff(2 * config.NUM_PES * (LEVELS - 2) + i) \n w_dist_bus(i) := out_switch.io.y\n \n }\n\n for (i <- 0 until config.NUM_PES) {\n for (j <- 1 until (LEVELS - 1)) {\n val imm_switch = Module(new Switch(config.DATA_TYPE))\n imm_switch.io.in0 := w_internal(2 * i * (LEVELS - 1) + 2 * (j - 1))\n if (j <= (LEVELS - 1) / 2) {\n if (i % math.pow(2, j).toInt < math.pow(2, j - 1).toInt) {\n imm_switch.io.in1 := w_internal(2 * (i + math.pow(2, j - 1).toInt) * (LEVELS - 1) + 2 * (j - 1) + 1)\n } else {\n imm_switch.io.in1 := w_internal(2 * (i - math.pow(2, j - 1).toInt) * (LEVELS - 1) + 2 * (j - 1) + 1)\n }\n } else {\n if (i % math.pow(2, LEVELS - j).toInt < math.pow(2, LEVELS - j - 1).toInt) {\n imm_switch.io.in1 := w_internal(2 * (i + math.pow(2, LEVELS - j - 1).toInt) * (LEVELS - 1) + 2 * (j - 1) + 1)\n } else {\n imm_switch.io.in1 := w_internal(2 * (i - math.pow(2, LEVELS - j - 1).toInt) * (LEVELS - 1) + 2 * (j - 1) + 1)\n }\n }\n imm_switch.io.sel0 := r_mux_bus_ff(2 * (LEVELS - 2) * i + 2 * (j - 1))\n imm_switch.io.sel1 := r_mux_bus_ff(2 * (LEVELS - 2) * i + 2 * (j - 1) + 1)\n w_internal(2 * i * (LEVELS - 1) + 2 * j) := imm_switch.io.y \n w_internal(2 * i * (LEVELS - 1) + 2 * j + 1) := imm_switch.io.z \n }\n }\n}\n", "groundtruth": " out_switch.io.in1 := w_internal(2 * (if(i % 2 == 0) i + 1 else i - 1) * (LEVELS - 1) + (2 * (LEVELS - 2)) + 1)\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.5, "category_reason": ":= to io port"} {"task_id": "magma-si", "path": "magma-si/src/main/scala/components/Bitmap.scala", "left_context": "package magmasi.components\n\nimport chisel3._\nimport chisel3.util._\n\nclass Bitmap(implicit val config: MagmasiConfig) extends Module{\n val io = IO(new Bundle {\n val mat1 =Input(Vec(config.rowsA, Vec(config.colsA, UInt(config.DATA_TYPE.W))))\n val mat2 = Input(Vec(config.rowsB, Vec(config.colsB, UInt(config.DATA_TYPE.W))))\n val bitmap1 =Output(Vec(config.rowsA, Vec(config.colsA, UInt(config.DATA_TYPE.W))))\n val bitmap2 = Output(Vec(config.rowsB, Vec(config.colsB, UInt(config.DATA_TYPE.W))))\n })\n\n val matReg1 = RegInit(VecInit(Seq.fill(config.rowsA)(VecInit(Seq.fill(config.colsA)(0.U(config.DATA_TYPE.W))))))\n val matReg2 = RegInit(VecInit(Seq.fill(config.rowsB)(VecInit(Seq.fill(config.colsB)(0.U(config.DATA_TYPE.W))))))\n io.bitmap1 := matReg1\n io.bitmap2 := matReg2\n\n val i = RegInit(0.U(log2Ceil(config.rowsA).W))\n val j = RegInit(0.U(log2Ceil(config.colsB).W))\n\n when (j < config.colsB.U) {\n when (io.mat1(i)(j) =/= 0.U){\n matReg1(i)(j) := 1.U\n }.otherwise{\n matReg1(i)(j) := 0.U\n }\n", "right_context": " j := j + 1.U\n}\n when (j === (config.colsB-1).U){\n i := i + 1.U\n }\n\n\n}", "groundtruth": " when (io.mat2(i)(j) =/= 0.U){\n matReg2(i)(j) := 1.U\n }.otherwise{\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "magma-si", "path": "magma-si/src/main/scala/components/EdgeAdderSwitch.scala", "left_context": "package magmasi.components\nimport chisel3._\nimport chisel3.util._\nclass EdgeAdderSwitch(DATA_TYPE: Int = 32, NUM_IN: Int = 2, SEL_IN: Int = 2,NUM_OUT: Int = 2) extends Module {\n val io = IO(new Bundle {\n val i_valid = Input(Bool())\n val i_data_bus = Input(Vec(NUM_IN, UInt(64.W)))\n val i_add_en = Input(UInt(3.W))\n val i_cmd = Input(UInt(5.W))\n val i_sel = Input(UInt(SEL_IN.W))\n val o_vn = Output(UInt((2 * DATA_TYPE).W))\n val o_vn_valid = Output(UInt(2.W))\n val o_adder = Output(UInt(DATA_TYPE.W))\n })\n\n val clk = clock\n val rst = reset.asBool\n\n val reductionMux = Module(new ReductionMux(W = DATA_TYPE, NUM_IN = NUM_IN, SEL_IN = SEL_IN))\n reductionMux.io.i_data := io.i_data_bus\n reductionMux.io.i_sel := io.i_sel\n\n val adder32 = Module(new SimpleAdder)\n adder32.io.A := reductionMux.io.o_data(1)\n adder32.io.B := reductionMux.io.o_data(0)\n\n val r_valid = RegNext(io.i_valid, init = false.B)\n val r_adder = RegInit(0.U(DATA_TYPE.W))\n val r_vn = RegInit(0.U((2 * DATA_TYPE).W))\n val r_vn_valid = RegInit(0.U(2.W))\n val r_add_en = RegNext(io.i_add_en, init = 0.U)\n\n", "right_context": " r_vn_valid := 1.U\n }\n is (\"b100\".U) {\n r_adder := reductionMux.io.o_data(0)\n r_vn := Cat(0.U(DATA_TYPE.W), io.i_data_bus(NUM_IN - 1))\n r_vn_valid := 2.U\n }\n is (\"b101\".U) {\n r_vn := Cat(reductionMux.io.o_data)\n r_vn_valid := 3.U\n }\n is (0.U) {\n r_vn_valid := 0.U\n }\n }\n }\n\n when (rst) {\n io.o_adder := 0.U\n io.o_vn := 0.U\n io.o_vn_valid := 0.U\n } .otherwise {\n when (!r_add_en) {\n io.o_adder := r_adder\n } .otherwise {\n io.o_adder := adder32.io.O\n }\n io.o_vn := r_vn\n io.o_vn_valid := r_vn_valid\n }\n}\n", "groundtruth": " when (rst) {\n r_adder := 0.U\n r_vn := 0.U\n r_vn_valid := 0.U\n } .elsewhen (r_valid) {\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "magma-si", "path": "magma-si/src/main/scala/components/FanCtrl.scala", "left_context": "package magmasi.components\n\nimport chisel3._\nimport chisel3.util._\n\nclass fancontrol(DATA_TYPE: Int = 32, NUM_PES: Int = 32, LOG2_PES: Int = 5) extends Module {\n val io = IO(new Bundle {\n \n val i_vn = Input(Vec(NUM_PES, UInt(LOG2_PES.W)))\n val i_stationary = Input(Bool())\n val i_data_valid = Input(Bool())\n val o_reduction_add = Output(Vec(NUM_PES - 1, UInt()))\n val o_reduction_cmd = Output(Vec(NUM_PES - 1, UInt(3.W)))\n val o_reduction_sel = Output(Vec(20, UInt(2.W)))\n val o_reduction_valid = Output(UInt(1.W))\n })\n\n\n val r_reduction_add = RegInit(VecInit(Seq.fill(NUM_PES - 1)(0.U)))\n val r_reduction_cmd = RegInit(VecInit(Seq.fill(NUM_PES - 1)(0.U(3.W))))\n val r_reduction_sel = RegInit(VecInit(Seq.fill(20)(0.U(2.W))))\n\n val r_add_lvl_0Reg = RegInit(VecInit(Seq.fill(16)(0.U)))\n val r_add_lvl_1Reg = RegInit(VecInit(Seq.fill(16)(0.U)))\n val r_add_lvl_2Reg = RegInit(VecInit(Seq.fill(12)(0.U)))\n val r_add_lvl_3Reg = RegInit(VecInit(Seq.fill(8)(0.U))) \n val r_add_lvl_4Reg = RegInit(VecInit(Seq.fill(5)(0.U)))\n\n val r_cmd_lvl_0Reg = RegInit(VecInit(Seq.fill(16)(0.U(3.W))))\n val r_cmd_lvl_1Reg = RegInit(VecInit(Seq.fill(16)(0.U(3.W))))\n val r_cmd_lvl_2Reg = RegInit(VecInit(Seq.fill(12)(0.U(3.W))))\n val r_cmd_lvl_3Reg = RegInit(VecInit(Seq.fill(8)(0.U(3.W))))\n val r_cmd_lvl_4Reg = RegInit(VecInit(Seq.fill(5)(0.U(3.W))))\n\n val r_sel_lvl_2Reg = RegInit(VecInit(Seq.fill(24)(0.U(2.W))))\n val r_sel_lvl_3Reg = RegInit(VecInit(Seq.fill(32)(0.U(2.W))))\n val r_sel_lvl_4Reg = RegInit(VecInit(Seq.fill(20)(0.U(2.W)))) \n\n\n val w_vn = RegInit(VecInit(Seq.fill(NUM_PES)(0.U(LOG2_PES.W))))\n val r_valid = RegInit(VecInit(Seq.fill(5)(0.U)))\n \n w_vn := io.i_vn\n\n for (x <- 0 until 16) {\n when(x.U === 0.U) {\n when(r_valid(1) === 1.U) {\n when(w_vn(2.U * x.U + 0.U) === w_vn(2.U * x.U + 1.U)) {\n r_reduction_add(0.U+x.U) := 1.U\n }.otherwise {\n r_reduction_add(0.U+x.U) := 0.U\n }\n\n when((w_vn(2.U * x.U + 1.U) =/=\n w_vn(2.U * x.U + 2.U)) &&\n (w_vn(2.U * x.U + 0.U) =/=\n w_vn(2.U * x.U + 1.U) )) {\n\n r_reduction_cmd(0 ) := \"b101\".U // both vn done\n\n }.elsewhen((w_vn(2.U * x.U + 1.U) ===\n w_vn(2.U * x.U + 2.U)) &&\n (w_vn(2.U * x.U + 0.U) =/=\n w_vn(2.U * x.U + 1.U) )) {\n\n r_reduction_cmd(0) := \"b011\".U // left vn done\n\n }.otherwise {\n r_reduction_cmd( 0 ) := \"b000\".U // nothing\n\n }\n }.otherwise {\n r_reduction_add(0.U+x.U) := 0.U\n r_reduction_cmd(0 ) := \"b000\".U // nothing\n \n }\n \n\n\n }.elsewhen(x.U === 15.U) {\n \n \n r_reduction_add(0.U + x.U) := 0.U\n r_reduction_cmd(x.U ) := 0.U\n \n \n when(r_valid(1) === 1.U) {\n when(w_vn(2.U * x.U + 0.U) === w_vn(2.U * x.U + 1.U)) {\n r_reduction_add(0.U + x.U) := 1.U\n }.otherwise {\n r_reduction_add(0.U + x.U) := 0.U\n }\n\n when((w_vn(2.U * x.U + 0.U) =/= w_vn(2.U * x.U - 1.U) ) &&\n (w_vn(2.U * x.U + 0.U) =/= w_vn(2.U * x.U + 1.U) )) {\n\n r_reduction_cmd(x.U ) := \"b101\".U // both vn done\n\n }.elsewhen((w_vn(2.U * x.U + 0.U) === w_vn(2.U * x.U - 1.U) )&&\n (w_vn(2.U * x.U + 0.U) =/= w_vn(2.U * x.U + 1.U) )) {\n\n r_reduction_cmd(x.U ) := \"b100\".U // bypass\n\n }.otherwise {\n r_reduction_cmd(x.U ) := \"b000\".U\n }\n }.otherwise {\n r_reduction_add(0.U + x.U) := 0.U\n r_reduction_cmd(x.U ) := \"b000\".U\n \n }\n \n }.otherwise {\n r_reduction_add(0.U + x.U) := 0.U\n r_reduction_cmd(x.U ) := 0.U\n\n when(r_valid(1) === 1.U) {\n when(w_vn(2.U * x.U + 0.U) === w_vn(2.U * x.U + 1.U)) {\n\n r_reduction_add(0.U + x.U) := 1.U\n }.otherwise {\n r_reduction_add(0.U + x.U) := 0.U\n }\n\n when((w_vn(2.U * x.U + 0.U) =/= w_vn(2.U * x.U - 1.U)) &&\n (w_vn(2.U * x.U + 1.U) =/= w_vn(2.U * x.U + 2.U) )&&\n (w_vn(2.U * x.U + 0.U) =/= w_vn(2.U * x.U + 1.U)) ) {\n\n r_reduction_cmd(x.U ) := \"b101\".U // both vn done\n\n }.elsewhen((w_vn(2.U * x.U + 0.U) === w_vn(2.U * x.U - 1.U)) &&\n (w_vn(2.U * x.U + 1.U) =/= w_vn(2.U * x.U + 2.U)) &&\n (w_vn(2.U * x.U + 0.U) =/= w_vn(2.U * x.U + 1.U) )) {\n\n r_reduction_cmd( x.U ) := \"b100\".U // right vn done\n\n }.elsewhen((w_vn(2.U * x.U + 0.U) =/= w_vn(2.U * x.U - 1.U)) &&\n (w_vn(2.U * x.U + 1.U) === w_vn(2.U * x.U + 2.U)) &&\n (w_vn(2.U * x.U + 0.U) =/= w_vn(2.U * x.U + 1.U) )) {\n\n r_reduction_cmd(x.U ) := \"b011\".U // left vn done\n\n }.otherwise {\n r_reduction_cmd( x.U ) := \"b001\".U // bypass\n }\n }.otherwise {\n r_reduction_add(0.U + x.U) := 0.U\n r_reduction_cmd(x.U ) := \"b000\".U // nothing\n }\n }\n\n } \n\n for (x <- 0 until 8) {\n when(x.U === 0.U) {\n r_reduction_add(16.U + x.U) := 0.U\n r_reduction_cmd( 16.U + x.U) := 0.U\n\n when(r_valid(1) === 1.U) {\n when(w_vn(4.U * x.U + 1.U) === w_vn(4.U * x.U + 2.U) ) {\n r_reduction_add(16.U + x.U) := 1.U\n }.otherwise {\n r_reduction_add(16.U + x.U) := 0.U\n }\n\n when((w_vn(4.U * x.U + 0.U) === w_vn(4.U * x.U + 1.U)) &&\n (w_vn(4.U * x.U + 2.U) === w_vn(4.U * x.U + 3.U)) &&\n (w_vn(4.U * x.U + 4.U) =/= w_vn(4.U * x.U + 3.U)) &&\n (w_vn(4.U * x.U + 1.U) =/= w_vn(4.U * x.U + 2.U))) {\n\n r_reduction_cmd(16.U + x.U) := \"b101\".U // both vn done\n\n }.elsewhen((w_vn(4.U * x.U + 2.U) === w_vn(4.U * x.U + 3.U)) &&\n (w_vn(4.U * x.U + 4.U) =/= w_vn(4.U * x.U + 3.U)) &&\n (w_vn(4.U * x.U + 1.U) =/= w_vn(4.U * x.U + 2.U))) {\n\n r_reduction_cmd(16.U + x.U) := \"b100\".U // right vn done\n\n }.elsewhen((w_vn(4.U * x.U + 0.U) === w_vn(4.U * x.U + 1.U) ) &&\n (w_vn(4.U * x.U + 1.U) =/= w_vn(4.U * x.U + 2.U))) {\n\n r_reduction_cmd(16.U + x.U) := \"b011\".U // left vn done\n }.otherwise {\n r_reduction_cmd(16.U+ x.U):= \"b000\".U // nothing\n }\n }.otherwise {\n r_reduction_add(16.U + x.U) := 0.U\n r_reduction_cmd( 16.U + x.U) := \"b000\".U // nothing\n }\n }.elsewhen(x.U === 7.U) {\n r_reduction_add(16.U + x.U) := 0.U\n r_reduction_cmd(16.U + x.U) := 0.U\n\n when(r_valid(1) === true.B) {\n when(w_vn(4.U * x.U + 1.U) === w_vn(4.U * x.U + 2.U)) {\n r_reduction_add(16.U + x.U) := 1.U\n }.otherwise {\n r_reduction_add(16.U + x.U) := 0.U\n }\n\n when((w_vn(4.U * x.U + 0.U) === w_vn(4.U * x.U + 1.U) ) &&\n (w_vn(4.U * x.U + 2.U) === w_vn(4.U * x.U + 3.U) ) &&\n (w_vn(4.U * x.U + 0.U) =/= w_vn(4.U * x.U - 1.U) ) &&\n (w_vn(4.U * x.U + 1.U) =/= w_vn(4.U * x.U + 2.U))) {\n\n r_reduction_cmd(16.U + x.U):= \"b101\".U // both vn done\n\n }.elsewhen((w_vn(4.U * x.U + 0.U) === w_vn(4.U * x.U + 1.U) ) &&\n (w_vn(4.U * x.U + 0.U) =/= w_vn(4.U * x.U - 1.U) ) &&\n (w_vn(4.U * x.U + 1.U) =/= w_vn(4.U * x.U + 2.U))) {\n\n r_reduction_cmd(16.U +x.U) := \"b011\".U // left vn done\n\n }.elsewhen((w_vn(4.U * x.U + 2.U) === w_vn(4.U * x.U + 3.U)) &&\n (w_vn(4.U * x.U + 1.U) =/= w_vn(4.U * x.U + 2.U) )) {\n\n r_reduction_cmd(16.U + x.U) := \"b100\".U // right vn done\n\n }.otherwise {\n r_reduction_cmd(16.U + x.U) := \"b000\".U // nothing\n }\n }.otherwise {\n r_reduction_add(16.U + x.U) := 0.U\n r_reduction_cmd(16.U + x.U) := \"b000\".U // nothing\n }\n }.otherwise{\n r_reduction_add(16.U + x.U) := 0.U\n r_reduction_cmd(16.U +x.U) := 0.U\n\n when(r_valid(1) === 1.U) {\n when(w_vn(4.U * x.U + 1.U) === w_vn(4.U * x.U + 2.U) ) {\n r_reduction_add(16.U + x.U) := 1.U\n }.otherwise {\n r_reduction_add(16.U + x.U) := 0.U\n }\n\n when((w_vn(4.U * x.U + 0.U) === w_vn(4.U * x.U + 1.U)) &&\n (w_vn(4.U * x.U + 2.U) === w_vn(4.U * x.U + 3.U)) &&\n (w_vn(4.U * x.U + 0.U) =/= w_vn(4.U * x.U - 1.U) ) &&\n (w_vn(4.U * x.U + 4.U)=/= w_vn(4.U * x.U + 3.U) ) &&\n (w_vn(4.U * x.U + 1.U) =/= w_vn(4.U * x.U + 2.U))) {\n\n r_reduction_cmd(16.U + x.U) := \"b101\".U // both vn done\n\n }.elsewhen((w_vn(4.U * x.U + 2.U) === w_vn(4.U * x.U + 3.U)) &&\n (w_vn(4.U * x.U + 4.U) =/= w_vn(4.U * x.U + 3.U) ) &&\n (w_vn(4.U * x.U + 1.U) =/= w_vn(4.U * x.U + 2.U) )) {\n\n r_reduction_cmd(16.U + x.U):= \"b100\".U // right vn done\n\n }.elsewhen((w_vn(4.U * x.U + 0.U) === w_vn(4.U * x.U + 1.U) ) &&\n (w_vn(4.U * x.U + 0.U) =/= w_vn(4.U * x.U - 1.U) ) &&\n (w_vn(4.U * x.U + 1.U) =/= w_vn(4.U * x.U + 2.U) )) {\n\n \n r_reduction_cmd( 16.U + x.U) := \"b011\".U // left vn done\n }.otherwise {\n r_reduction_cmd( 16.U + x.U) := \"b000\".U // nothing\n }\n }.otherwise {\n r_reduction_add(16.U + x.U) := 0.U\n r_reduction_cmd( 16.U + x.U) := \"b000\".U // nothing\n }\n }\n }\n\n\n for (x <- 0 until 4) {\n when(x.U === 0.U) {\n r_reduction_add(24.U + x.U) := 0.U\n r_reduction_cmd(24.U + x.U) := 0.U\n r_reduction_sel((x * 2).U + 0.U) := \"b00\".U\n\n when(r_valid(1) === 1.U) {\n\n when(w_vn(8.U * x.U + 3.U) === w_vn(8.U * x.U + 4.U)) {\n r_reduction_add(24.U + x.U) := 1.U\n }.otherwise {\n r_reduction_add(24.U + x.U) := 0.U\n }\n\n when((w_vn(8.U * x.U + 1.U) === w_vn(8.U * x.U + 2.U)) &&\n (w_vn(8.U * x.U + 5.U) === w_vn(8.U * x.U + 6.U)) &&\n (w_vn(8.U * x.U + 8.U) =/= w_vn(8.U * x.U + 6.U) ) &&\n (w_vn(8.U * x.U + 2.U) =/= w_vn(8.U * x.U + 4.U) ) &&\n (w_vn(8.U * x.U + 5.U) =/= w_vn(8.U * x.U + 3.U))) {\n\n r_reduction_cmd(24.U + x.U) := \"b101\".U // both vn done\n\n }.elsewhen((w_vn(8.U * x.U + 5.U) === w_vn(8.U * x.U + 6.U) ) &&\n (w_vn(8.U * x.U + 8.U) =/= w_vn(8.U * x.U + 6.U) ) &&\n (w_vn(8.U * x.U + 5.U) =/= w_vn(8.U * x.U + 3.U) )) {\n\n r_reduction_cmd(24.U + x.U):= \"b100\".U // right vn done\n\n }.elsewhen((w_vn(8.U * x.U + 1.U) === w_vn(8.U * x.U + 2.U) ) &&\n (w_vn(8.U * x.U + 2.U) =/= w_vn(8.U * x.U + 4.U) )) {\n\n r_reduction_cmd( 24.U + x.U):= \"b011\".U // left vn done\n\n }.otherwise {\n r_reduction_cmd(24.U + x.U):= \"b000\".U // nothing\n }\n\n // Left select logic\n }.otherwise {\n r_reduction_add(24.U + x.U) := 0.U\n r_reduction_cmd( 24.U + x.U) := \"b000\".U // nothing\n }\n\n // Left select logic\n when(r_valid(1) === 1.U) {\n when(w_vn(8.U * x.U + 3.U) === w_vn((8.U * x.U + 1.U) )) {\n r_reduction_sel((x * 2).U + 0.U) := \"b0\".U\n }.otherwise {\n r_reduction_sel((x * 2).U + 0.U) := \"b1\".U\n }\n }.otherwise {\n r_reduction_sel((x * 2).U + 0.U):= \"b00\".U\n \n }\n\n // Right select logic\n when(r_valid(1) === 1.U) {\n when(w_vn(8.U * x.U + 4.U) === w_vn(8.U * x.U + 6.U) ) {\n r_reduction_sel((x * 2).U + 1.U) := \"b1\".U\n }.otherwise {\n r_reduction_sel((x * 2).U + 1.U) := \"b0\".U\n }\n }.otherwise{\n r_reduction_sel((x * 2).U + 0.U) := \"b00\".U\n \n }\n \n }.elsewhen (x.U === 3.U) {\n r_reduction_add(24.U + x.U) := 0.U\n r_reduction_cmd( 24.U + x.U) := 0.U\n r_reduction_sel((x.U * 2.U) + 0.U) := \"b00\".U\n\n when (r_valid(1) === 1.U) {\n when (w_vn(8.U * x.U + 3.U) === w_vn(8.U * x.U + 4.U) ) {\n r_reduction_add(24.U + x.U) := 1.U\n }.otherwise {\n r_reduction_add(24.U + x.U) := 0.U\n }\n\n when ((w_vn(8.U * x.U + 1.U) === w_vn(8.U * x.U + 2.U) ) &&\n (w_vn(8.U * x.U + 5.U) === w_vn(8.U * x.U + 6.U) ) &&\n (w_vn(8.U * x.U + 1.U) =/= w_vn(8.U * x.U - 1.U) ) &&\n (w_vn(8.U * x.U + 2.U) =/= w_vn(8.U * x.U + 4.U) ) &&\n (w_vn(8.U * x.U + 5.U) =/= w_vn(8.U * x.U + 3.U) )) {\n\n r_reduction_cmd( 24.U + x.U):= \"b101\".U // both vn done\n\n }.elsewhen ((w_vn(8.U * x.U + 1.U) === w_vn(8.U * x.U + 2.U) ) &&\n (w_vn(8.U * x.U + 1.U) =/= w_vn(8.U * x.U - 1.U) ) &&\n (w_vn(8.U * x.U + 4.U) =/= w_vn(8.U * x.U + 2.U))) {\n\n r_reduction_cmd( 24.U + x.U) := \"b011\".U // left vn done\n \n }.elsewhen ((w_vn(8.U * x.U + 5.U) === w_vn(8.U * x.U + 6.U) ) &&\n (w_vn(8.U * x.U + 5.U) =/= w_vn(8.U * x.U + 3.U))) {\n\n r_reduction_cmd( 24.U * x.U) := \"b100\".U // right vn done\n\n }.otherwise {\n\n r_reduction_cmd( 24.U + x.U) := \"b000\".U // nothing\n }\n }.otherwise {\n r_reduction_add(24.U + x.U) := 0.U\n r_reduction_cmd(24.U +x.U):= \"b000\".U // nothing\n }\n\n // generate left select logic\n when (r_valid(1) === 1.U) {\n when (w_vn(8.U * x.U + 3.U) === w_vn(8.U * x.U + 1.U)) {\n\n r_reduction_sel((x.U * 2.U) + 0.U) := \"b0\".U\n\n }.otherwise {\n r_reduction_sel((x.U * 2.U) + 0.U) := \"b1\".U\n }\n }.otherwise {\n r_reduction_sel((x.U * 2.U) + 0.U) := \"b00\".U\n }\n\n // generate right select logic\n when (r_valid(1) === 1.U) {\n when (w_vn(8.U * x.U + 4.U) === w_vn(8.U * x.U + 6.U)) {\n\n r_reduction_sel((x.U * 2.U) + 1.U) := \"b1\".U\n\n }.otherwise {\n r_reduction_sel((x.U * 2.U) + 1.U) := \"b0\".U\n }\n }.otherwise {\n r_reduction_sel((x.U * 2.U) + 0.U) := \"b00\".U\n }\n\n\n }.otherwise{\n r_reduction_add(24.U + x.U) := 0.U\n r_reduction_cmd( 24.U + x.U) := \"b000\".U\n r_reduction_sel((x.U * 2.U) + 0.U) := \"b00\".U\n\n // generate cmd logic\n when (r_valid(1) === 1.U) {\n when (w_vn(8.U * x.U + 3.U) === w_vn(8.U * x.U + 4.U) ) {\n r_reduction_add(24.U + x.U) := 1.U // add enable\n }.otherwise {\n r_reduction_add(24.U + x.U) := 0.U\n }\n\n when ((w_vn(8.U * x.U + 1.U) === w_vn(8.U * x.U + 2.U) ) &&\n (w_vn(8.U * x.U + 5.U) === w_vn(8.U * x.U + 6.U) ) &&\n (w_vn(8.U * x.U + 1.U) =/= w_vn(8.U * x.U - 1.U) ) &&\n (w_vn(8.U * x.U + 8.U) =/= w_vn(8.U * x.U + 6.U) ) &&\n (w_vn(8.U * x.U + 2.U) =/= w_vn(8.U * x.U + 4.U) ) &&\n (w_vn(8.U * x.U + 5.U) =/= w_vn(8.U * x.U + 3.U) )) {\n\n r_reduction_cmd( 24.U + x.U) := \"b101\".U // both vn done\n\n }.elsewhen ((w_vn(8.U * x.U + 5.U) === w_vn(8.U * x.U + 6.U)) &&\n (w_vn(8.U * x.U + 8.U) =/= w_vn(8.U * x.U + 6.U) ) &&\n (w_vn(8.U * x.U + 5.U) =/= w_vn(8.U * x.U + 3.U) )) {\n\n r_reduction_cmd(24.U + x.U):= \"b100\".U // right vn done\n\n }.elsewhen ((w_vn(8.U * x.U + 1.U) === w_vn(8.U * x.U + 2.U) ) &&\n (w_vn(8.U * x.U + 1.U) =/= w_vn(8.U * x.U - 1.U) ) &&\n (w_vn(8.U * x.U + 4.U) =/= w_vn(8.U * x.U + 2.U) )) {\n\n r_reduction_cmd( 24.U + x.U):= \"b011\".U // left vn done\n\n }.otherwise {\n r_reduction_cmd( 24.U + x.U):= \"b000\".U // nothing\n }\n }.otherwise {\n r_reduction_add(24.U + x.U) := 0.U\n r_reduction_cmd( 24.U + x.U) := \"b000\".U // nothing\n }\n\n // generate left select logic\n when (r_valid(1) === 1.U) {\n when (w_vn(8.U * x.U + 3.U) === w_vn(8.U * x.U + 1.U) ) {\n\n r_reduction_sel((x.U * 2.U) + 0.U) := \"b0\".U\n\n }.otherwise {\n\n r_reduction_sel((x.U * 2.U) + 0.U) := \"b1\".U\n }\n }.otherwise {\n r_reduction_sel((x.U * 2.U) + 0.U) := \"b00\".U\n }\n\n // generate right select logic\n when (r_valid(1) === 1.U) {\n when (w_vn(8.U * x.U + 4.U) === w_vn(8.U * x.U + 6.U) ) {\n\n r_reduction_sel((x.U * 2.U) + 1.U) := \"b1\".U\n\n }.otherwise {\n\n r_reduction_sel((x.U * 2.U) + 1.U) := \"b0\".U\n }\n }.otherwise {\n\n r_reduction_sel((x.U * 2.U) + 1.U) := \"b00\".U\n }\n }\n }\n for (x <- 0 until 2) {\n when (x.U === 0.U) {\n \n r_reduction_add(28.U + x.U) := 0.U\n r_reduction_cmd( 28.U + x.U):= 0.U\n r_reduction_sel((x.U * 4.U) + 8.U) := \"b0000\".U\n \n // generate cmd logic\n when (r_valid(1) === 1.U) {\n when (w_vn(16.U * x.U + 7.U) === w_vn(16.U * x.U + 8.U)) {\n r_reduction_add(28.U + x.U) := 1.U // add enable\n }.otherwise {\n r_reduction_add(28.U + x.U) := 0.U\n }\n\n when (w_vn(16.U * x.U + 3.U) === w_vn((16.U * x.U + 4.U) ) &&\n (w_vn(16.U * x.U + 11.U) === w_vn(16.U * x.U + 12.U) ) &&\n (w_vn(16.U * x.U + 16.U) =/= w_vn(16.U * x.U + 12.U)) &&\n (w_vn(16.U * x.U + 4.U) =/= w_vn(16.U * x.U + 8.U) ) &&\n (w_vn(16.U * x.U + 11.U) =/= w_vn(16.U * x.U + 7.U))) {\n\n r_reduction_cmd( 28.U + x.U) := \"b101\".U // both vn done\n\n }.elsewhen ((w_vn(16.U * x.U + 11.U)=== w_vn(16.U * x.U + 12.U)) &&\n (w_vn(16.U * x.U + 16.U) =/= w_vn(16.U * x.U + 12.U)) &&\n (w_vn(16.U * x.U + 11.U) =/= w_vn(16.U * x.U + 7.U))) {\n\n r_reduction_cmd( 28.U + x.U) := \"b100\".U // right vn done\n\n }.elsewhen ((w_vn(16.U * x.U + 3.U) === w_vn(16.U * x.U + 4.U)) &&\n (w_vn(16.U * x.U + 4.U) =/= w_vn(16.U * x.U + 8.U))) {\n\n r_reduction_cmd( 28.U + x.U):= \"b011\".U // left vn done\n\n }.otherwise {\n r_reduction_cmd( 28.U +x.U) := \"b000\".U // nothing\n }\n }.otherwise {\n r_reduction_add(28.U + x.U) := 0.U\n r_reduction_cmd( 28.U + x.U):= \"b000\".U // nothing\n }\n\n // generate left select logic\n when (r_valid(1) === 1.U) {\n when (w_vn(16.U * x.U + 7.U) === w_vn(16.U * x.U + 3.U) ) {\n\n r_reduction_sel((x.U * 4.U) + 8.U) := \"b00\".U\n\n }.elsewhen (w_vn(16.U * x.U + 7.U) === w_vn(16.U * x.U + 5.U) ) {\n\n r_reduction_sel((x.U * 4.U) + 8.U):= \"b01\".U\n\n }.otherwise {\n\n r_reduction_sel((x.U * 4.U) + 8.U) := \"b10\".U\n }\n }.otherwise {\n r_reduction_sel((x.U * 4.U) + 8.U) := \"b0000\".U\n }\n\n // generate right select logic\n when (r_valid(1) === 1.U) {\n when (w_vn(16.U * x.U + 8.U) === w_vn(16.U * x.U + 12.U) ) {\n\n r_reduction_sel((x.U * 4.U) + 10.U) := \"b10\".U\n\n }.elsewhen (w_vn(16.U * x.U + 8.U) === w_vn(16.U * x.U + 10.U)) {\n\n r_reduction_sel((x.U * 4.U) + 10.U) := \"b01\".U\n\n }.otherwise {\n r_reduction_sel((x.U * 4.U) + 10.U) := \"b00\".U\n }\n }.otherwise {\n r_reduction_sel((x.U * 4.U) + 8.U) := \"b0000\".U\n }\n\n }.elsewhen (x.U === 1.U) {\n \n r_reduction_add(28.U + x.U) := 0.U\n r_reduction_cmd( 28.U + x.U) := 0.U\n r_reduction_sel((x.U * 4.U) + 8.U):= \"b0000\".U\n \n // generate cmd logic\n when (r_valid(1)===1.U) {\n when (w_vn(16.U * x.U + 7.U) === w_vn(16.U * x.U + 8.U) ) {\n r_reduction_add(28.U + x.U) := 1.U // add enable\n }.otherwise {\n r_reduction_add(28.U + x.U) := 0.U\n }\n\n when ((w_vn(16.U * x.U + 3.U) === w_vn(16.U * x.U + 4.U) ) &&\n (w_vn(16.U * x.U + 11.U) === w_vn(16.U * x.U + 12.U) ) &&\n (w_vn(16.U * x.U + 3.U) =/= w_vn(16.U * x.U - 1.U)) &&\n (w_vn(16.U * x.U + 4.U) =/= w_vn(16.U * x.U + 8.U) ) &&\n (w_vn(16.U * x.U + 11.U) =/= w_vn(16.U * x.U + 7.U) )) {\n\n r_reduction_cmd(28.U + x.U) := \"b101\".U // both vn done\n\n }.elsewhen ((w_vn(16.U * x.U + 3.U) === w_vn(16.U * x.U + 4.U) ) &&\n (w_vn(16.U * x.U + 3.U) =/= w_vn(16.U * x.U - 1.U) ) &&\n (w_vn(16.U * x.U + 8.U) =/= w_vn(16.U * x.U + 4.U) )) {\n\n r_reduction_cmd( 28.U + x.U):= \"b011\".U // left vn done\n\n }.elsewhen ((w_vn(16.U * x.U + 11.U) === w_vn(16.U * x.U + 12.U) ) &&\n (w_vn(16.U * x.U + 11.U) =/= w_vn(16.U * x.U + 7.U) )) {\n\n r_reduction_cmd( 28.U +x.U) := \"b100\".U // right vn done\n\n }.otherwise {\n r_reduction_cmd( 28.U + x.U) := \"b000\".U // nothing\n }\n }.otherwise {\n r_reduction_add(28.U + x.U) := 0.U\n r_reduction_cmd( 28.U + x.U) := \"b000\".U // nothing\n }\n\n // generate left select logic\n when (r_valid(1) === 1.U) {\n when (w_vn(16.U * x.U + 7.U) === w_vn(16.U * x.U + 3.U)) {\n r_reduction_sel((x.U * 4.U) + 8.U) := \"b00\".U\n }.elsewhen (w_vn(16.U * x.U + 7.U) === w_vn(16.U * x.U + 5.U) ) {\n r_reduction_sel((x.U * 4.U) + 8.U) := \"b01\".U\n }.otherwise {\n r_reduction_sel((x.U * 4.U) + 8.U) := \"b10\".U\n }\n }.otherwise {\n r_reduction_sel((x.U * 4.U) + 8.U) := \"b0000\".U\n }\n\n // generate right select logic\n when (r_valid(1)===1.U) {\n when (w_vn(16.U * x.U + 8.U) === w_vn(16.U * x.U + 12.U) ) {\n r_reduction_sel((x.U * 4.U) + 10.U) := \"b10\".U\n }.elsewhen (w_vn(16.U * x.U + 8.U) === w_vn(16.U * x.U + 10.U) ) {\n r_reduction_sel((x.U * 4.U) + 10.U) := \"b01\".U\n }.otherwise {\n r_reduction_sel((x.U * 4.U) + 10.U) := \"b00\".U\n }\n }.otherwise {\n r_reduction_sel((x.U * 4.U) + 8.U) := \"b0000\".U\n }\n\n\n }.otherwise{\n r_reduction_add(28.U + x.U) := 0.U\n r_reduction_cmd(28.U + x.U) := 0.U\n r_reduction_sel((x.U * 4.U) + 8.U) := \"b0000\".U\n // generate cmd logic\n when (r_valid(1)===1.U) {\n when (w_vn(16.U * x.U + 7.U) === w_vn(16.U * x.U + 8.U)) {\n r_reduction_add(28.U + x.U) := 1.U // add enable\n } .otherwise {\n r_reduction_add(28.U + x.U) := 0.U\n }\n\n when ((w_vn(16.U * x.U + 3.U) === w_vn(16.U * x.U + 4.U) ) &&\n (w_vn(16.U * x.U + 11.U) === w_vn(16.U * x.U + 12.U) ) &&\n (w_vn(16.U * x.U + 3.U) =/= w_vn(16.U * x.U - 1.U) ) &&\n (w_vn(16.U * x.U + 16.U) =/= w_vn(16.U * x.U + 12.U)) &&\n (w_vn(16.U * x.U + 4.U)=/= w_vn(16.U * x.U + 8.U)) &&\n (w_vn(16.U * x.U + 11.U) =/= w_vn(16.U * x.U + 7.U))) {\n\n r_reduction_cmd( 28.U + x.U) := \"b101\".U // both vn done\n\n } .elsewhen ((w_vn(16.U * x.U + 11.U) === w_vn(16.U * x.U + 12.U) ) &&\n (w_vn(16.U * x.U + 16.U) =/= w_vn(16.U * x.U + 12.U) ) &&\n (w_vn(16.U * x.U + 11.U) =/= w_vn(16.U * x.U + 7.U) )) {\n\n r_reduction_cmd( 28.U + x.U):= \"b100\".U // right vn done\n\n } .elsewhen ((w_vn(16.U * x.U + 3.U) === w_vn(16.U * x.U + 4.U) ) &&\n (w_vn(16.U * x.U + 3.U) =/= w_vn(16.U * x.U - 1.U) ) &&\n (w_vn(16.U * x.U + 8.U) =/= w_vn(16.U * x.U + 4.U) )) {\n\n r_reduction_cmd( 28.U + x.U) := \"b011\".U // left vn done\n\n } .otherwise {\n r_reduction_cmd( 28.U + x.U) := \"b000\".U // nothing\n }\n } .otherwise {\n r_reduction_add(28.U + x.U) := 0.U\n r_reduction_cmd( 28.U + x.U):= \"b000\".U // nothing\n }\n\n // generate left select logic\n when (r_valid(1)===1.U) {\n when (w_vn(16.U * x.U + 7.U) === w_vn(16.U * x.U + 3.U) ) {\n\n r_reduction_sel((x.U * 4.U) + 8.U) := \"b00\".U\n\n } .elsewhen (w_vn(16.U * x.U + 7.U) === w_vn(16.U * x.U + 5.U)) {\n\n r_reduction_sel((x.U * 4.U) + 8.U) := \"b01\".U\n\n } .otherwise {\n r_reduction_sel((x.U * 4.U) + 8.U):= \"b10\".U\n }\n } .otherwise {\n r_reduction_sel((x.U * 4.U) + 8.U):= \"b0000\".U\n }\n\n // generate right select logic\n when (r_valid(1) === 1.U) {\n when (w_vn(16.U * x.U + 8.U) === w_vn(16.U * x.U + 12.U) ) {\n r_reduction_sel((x.U * 4.U) + 10.U) := \"b10\".U\n } .elsewhen (w_vn(16.U * x.U + 8.U) === w_vn(16.U * x.U + 10.U)) {\n r_reduction_sel((x.U * 4.U) + 10.U) := \"b01\".U\n } .otherwise {\n r_reduction_sel((x.U * 4.U) + 10.U) := \"b00\".U\n }\n } .otherwise {\n r_reduction_sel((x.U * 4.U) + 8.U) := \"b0000\".U\n }\n }\n }\n\n\n for (x <- 0 until 1) {\n when (x.U === 0.U) {\n r_reduction_add(30.U + x.U) := 0.U\n r_reduction_cmd( 30.U + x.U):= 0.U\n r_reduction_sel((x.U * 4.U) + 16.U) := \"b0000\".U\n\n when (r_valid(1) === true.B) {\n when (w_vn(32.U * x.U + 15.U) === w_vn(32.U * x.U + 16.U) ) {\n r_reduction_add(30.U + x.U) := 1.U\n }.otherwise {\n r_reduction_add(30.U + x.U) := 0.U\n }\n\n when ((w_vn(32.U * x.U + 7.U) === w_vn(32.U * x.U + 8.U) ) &&\n (w_vn(32.U * x.U + 23.U) === w_vn(32.U * x.U + 24.U)) &&\n (w_vn(32.U * x.U + 8.U) =/= w_vn(32.U * x.U + 16.U) ) &&\n (w_vn(32.U * x.U + 23.U) =/= w_vn(32.U * x.U + 15.U))) {\n\n r_reduction_cmd( 30.U + x.U) := \"b101\".U\n\n }.elsewhen ((w_vn(32.U * x.U + 23.U) === w_vn(32.U * x.U + 24.U) ) &&\n (w_vn(32.U * x.U + 23.U) =/= w_vn(32.U * x.U + 15.U) )) {\n\n r_reduction_cmd( 30.U + x.U) := \"b100\".U\n\n }.elsewhen ((w_vn(32.U * x.U + 7.U) === w_vn(32.U * x.U + 8.U) ) &&\n (w_vn(32.U * x.U + 16.U) =/= w_vn(32.U * x.U + 8.U) )) {\n\n r_reduction_cmd( 30.U + x.U) := \"b011\".U\n\n }.otherwise {\n r_reduction_cmd( 30.U + x.U) := \"b000\".U\n }\n", "right_context": " r_reduction_sel((x.U * 4.U) + 16.U) := \"b00\".U\n } .elsewhen (w_vn(32.U * x.U + 15.U) === w_vn(32.U * x.U + 11.U)) {\n r_reduction_sel((x.U * 4.U) + 16.U) := \"b01\".U\n } .elsewhen (w_vn(32.U * x.U + 15.U) === w_vn(32.U * x.U + 13.U)) {\n r_reduction_sel((x.U * 4.U) + 16.U) := \"b10\".U\n } .otherwise {\n r_reduction_sel((x.U * 4.U) + 16.U) := \"b11\".U\n }\n } .otherwise {\n r_reduction_sel((x.U * 4.U) + 16.U):= \"b0000\".U\n }\n\n when (r_valid(1) === 1.U) {\n when (w_vn(32.U * x.U + 16.U) === w_vn(32.U * x.U + 24.U) ) {\n r_reduction_sel((x.U * 4.U) + 18.U):= \"b11\".U\n } .elsewhen (w_vn(32.U * x.U + 16.U) === w_vn(32.U * x.U + 20.U) ) {\n r_reduction_sel((x.U * 4.U) + 18.U) := \"b10\".U\n } .elsewhen (w_vn(32.U * x.U + 16.U) === w_vn(32.U * x.U + 18.U) ) {\n r_reduction_sel((x.U * 4.U) + 18.U) := \"b01\".U\n } .otherwise {\n r_reduction_sel((x.U * 4.U) + 18.U):= \"b00\".U\n }\n } .otherwise {\n r_reduction_sel((x.U * 4.U) + 18.U) := \"b0000\".U\n }\n }\n }\n\n\n r_add_lvl_0Reg := VecInit(Seq(\n r_reduction_add(0),\n r_reduction_add(1),\n r_reduction_add(2),\n r_reduction_add(3),\n r_reduction_add(4),\n r_reduction_add(5),\n r_reduction_add(6),\n r_reduction_add(7),\n r_reduction_add(8),\n r_reduction_add(9),\n r_reduction_add(10),\n r_reduction_add(11),\n r_reduction_add(12),\n r_reduction_add(13),\n r_reduction_add(14),\n r_reduction_add(15)\n ))\n\n r_add_lvl_1Reg := VecInit(Seq(\n r_reduction_add(16),\n r_reduction_add(17),\n r_reduction_add(18),\n r_reduction_add(19),\n r_reduction_add(20),\n r_reduction_add(21),\n r_reduction_add(22),\n r_reduction_add(23),\n r_reduction_add(16),\n r_reduction_add(17),\n r_reduction_add(18),\n r_reduction_add(19),\n r_reduction_add(20),\n r_reduction_add(21),\n r_reduction_add(22),\n r_reduction_add(23)\n ))\n\n\n\n r_add_lvl_2Reg := VecInit(Seq(\n r_reduction_add(24),\n r_reduction_add(25),\n r_reduction_add(26),\n r_reduction_add(27),\n r_reduction_add(24),\n r_reduction_add(25),\n r_reduction_add(26),\n r_reduction_add(27),\n r_reduction_add(24),\n r_reduction_add(25),\n r_reduction_add(26),\n r_reduction_add(27)\n ))\n\n r_add_lvl_3Reg := VecInit(Seq(\n r_reduction_add(28),\n r_reduction_add(29),\n r_reduction_add(28),\n r_reduction_add(29),\n r_reduction_add(28),\n r_reduction_add(29),\n r_reduction_add(28),\n r_reduction_add(29)\n\n ))\n\n r_add_lvl_4Reg := VecInit(Seq(\n r_reduction_add(30),\n r_reduction_add(30), \n r_reduction_add(30), \n r_reduction_add(30), \n r_reduction_add(30)\n ))\n\n\n r_cmd_lvl_0Reg := VecInit(Seq(\n r_reduction_cmd(0),\n r_reduction_cmd(1),\n r_reduction_cmd(2),\n r_reduction_cmd(3),\n r_reduction_cmd(4),\n r_reduction_cmd(5),\n r_reduction_cmd(6),\n r_reduction_cmd(7),\n r_reduction_cmd(8),\n r_reduction_cmd(9),\n r_reduction_cmd(10),\n r_reduction_cmd(11),\n r_reduction_cmd(12),\n r_reduction_cmd(13),\n r_reduction_cmd(14),\n r_reduction_cmd(15)\n \n ))\n\n \n r_cmd_lvl_1Reg := VecInit(Seq( \n r_reduction_cmd(16),\n r_reduction_cmd(17),\n r_reduction_cmd(18),\n r_reduction_cmd(19),\n r_reduction_cmd(20),\n r_reduction_cmd(21),\n r_reduction_cmd(22),\n r_reduction_cmd(23),\n r_reduction_cmd(16),\n r_reduction_cmd(17),\n r_reduction_cmd(18),\n r_reduction_cmd(19),\n r_reduction_cmd(20),\n r_reduction_cmd(21),\n r_reduction_cmd(22),\n r_reduction_cmd(23)\n ))\n\n r_cmd_lvl_2Reg := VecInit(Seq(\n r_reduction_cmd(24),\n r_reduction_cmd(25),\n r_reduction_cmd(26),\n r_reduction_cmd(27),\n r_reduction_cmd(24),\n r_reduction_cmd(25),\n r_reduction_cmd(26),\n r_reduction_cmd(27),\n r_reduction_cmd(24),\n r_reduction_cmd(25),\n r_reduction_cmd(26),\n r_reduction_cmd(27)\n ))\n\n r_cmd_lvl_3Reg := VecInit(Seq(\n r_reduction_cmd(28),\n r_reduction_cmd(29),\n r_reduction_cmd(28),\n r_reduction_cmd(29),\n r_reduction_cmd(28),\n r_reduction_cmd(29),\n r_reduction_cmd(28),\n r_reduction_cmd(29)\n ))\n\n r_cmd_lvl_4Reg := VecInit(Seq(\n r_reduction_cmd(30),\n r_reduction_cmd(30),\n r_reduction_cmd(30),\n r_reduction_cmd(30),\n r_reduction_cmd(30)\n ))\n\n r_sel_lvl_2Reg := VecInit(Seq(\n r_reduction_sel(0),\n r_reduction_sel(1),\n r_reduction_sel(2),\n r_reduction_sel(3),\n r_reduction_sel(4),\n r_reduction_sel(5),\n r_reduction_sel(6),\n r_reduction_sel(7),\n r_reduction_sel(0),\n r_reduction_sel(1),\n r_reduction_sel(2),\n r_reduction_sel(3),\n r_reduction_sel(4),\n r_reduction_sel(5),\n r_reduction_sel(6),\n r_reduction_sel(7),\n r_reduction_sel(0),\n r_reduction_sel(1),\n r_reduction_sel(2),\n r_reduction_sel(3),\n r_reduction_sel(4),\n r_reduction_sel(5),\n r_reduction_sel(6),\n r_reduction_sel(7)\n \n\n ))\n r_sel_lvl_3Reg := VecInit(Seq(\n r_reduction_sel(8),\n r_reduction_sel(9),\n r_reduction_sel(10), \n r_reduction_sel(11),\n r_reduction_sel(12),\n r_reduction_sel(13),\n r_reduction_sel(14), \n r_reduction_sel(15),\n r_reduction_sel(8),\n r_reduction_sel(9),\n r_reduction_sel(10), \n r_reduction_sel(11),\n r_reduction_sel(12),\n r_reduction_sel(13),\n r_reduction_sel(14), \n r_reduction_sel(15),\n r_reduction_sel(8),\n r_reduction_sel(9),\n r_reduction_sel(10), \n r_reduction_sel(11),\n r_reduction_sel(12),\n r_reduction_sel(13),\n r_reduction_sel(14), \n r_reduction_sel(15),\n r_reduction_sel(8),\n r_reduction_sel(9),\n r_reduction_sel(10), \n r_reduction_sel(11),\n r_reduction_sel(12),\n r_reduction_sel(13),\n r_reduction_sel(14), \n r_reduction_sel(15)\n ))\n r_sel_lvl_4Reg := VecInit(Seq(\n r_reduction_sel(16),\n r_reduction_sel(17),\n r_reduction_sel(18),\n r_reduction_sel(19),\n r_reduction_sel(16),\n r_reduction_sel(17),\n r_reduction_sel(18),\n r_reduction_sel(19),\n r_reduction_sel(16),\n r_reduction_sel(17),\n r_reduction_sel(18),\n r_reduction_sel(19),\n r_reduction_sel(16),\n r_reduction_sel(17),\n r_reduction_sel(18),\n r_reduction_sel(19),\n r_reduction_sel(16),\n r_reduction_sel(17),\n r_reduction_sel(18),\n r_reduction_sel(19)\n ))\n\n when(io.i_stationary === 0.B && io.i_data_valid === 1.B) {\n r_valid(0) := 1.U\n } .otherwise {\n r_valid(0) := 0.U\n }\n\n for (i <- 0 until 4) {\n \n \n r_valid(i + 1) := r_valid(i)\n }\n \n\n io.o_reduction_valid := r_valid(3)\n io.o_reduction_add := VecInit(Seq(\n r_add_lvl_4Reg(4), \n r_add_lvl_3Reg(6),\n r_add_lvl_3Reg(7), \n r_add_lvl_2Reg(8), \n r_add_lvl_2Reg(9), \n r_add_lvl_2Reg(10), \n r_add_lvl_2Reg(11), \n r_add_lvl_1Reg(8),\n r_add_lvl_1Reg(9),\n r_add_lvl_1Reg(10),\n r_add_lvl_1Reg(11),\n r_add_lvl_1Reg(12),\n r_add_lvl_1Reg(13),\n r_add_lvl_1Reg(14),\n r_add_lvl_1Reg(15), \n r_add_lvl_0Reg(0),\n r_add_lvl_0Reg(1),\n r_add_lvl_0Reg(2),\n r_add_lvl_0Reg(3),\n r_add_lvl_0Reg(4),\n r_add_lvl_0Reg(5),\n r_add_lvl_0Reg(6),\n r_add_lvl_0Reg(7),\n r_add_lvl_0Reg(8),\n r_add_lvl_0Reg(9),\n r_add_lvl_0Reg(10),\n r_add_lvl_0Reg(11),\n r_add_lvl_0Reg(12),\n r_add_lvl_0Reg(13),\n r_add_lvl_0Reg(14),\n r_add_lvl_0Reg(15)\n ))\n\n\n \n io.o_reduction_cmd := VecInit(Seq(\n r_cmd_lvl_4Reg(4),\n r_cmd_lvl_3Reg(6),\n r_cmd_lvl_3Reg(7),\n r_cmd_lvl_2Reg(8),\n r_cmd_lvl_2Reg(9),\n r_cmd_lvl_2Reg(10),\n r_cmd_lvl_2Reg(11),\n r_cmd_lvl_1Reg(8),\n r_cmd_lvl_1Reg(9),\n r_cmd_lvl_1Reg(10),\n r_cmd_lvl_1Reg(11),\n r_cmd_lvl_1Reg(12),\n r_cmd_lvl_1Reg(13),\n r_cmd_lvl_1Reg(14),\n r_cmd_lvl_1Reg(15),\n r_cmd_lvl_0Reg(0),\n r_cmd_lvl_0Reg(1),\n r_cmd_lvl_0Reg(2),\n r_cmd_lvl_0Reg(3),\n r_cmd_lvl_0Reg(4),\n r_cmd_lvl_0Reg(5),\n r_cmd_lvl_0Reg(6),\n r_cmd_lvl_0Reg(7),\n r_cmd_lvl_0Reg(8),\n r_cmd_lvl_0Reg(9),\n r_cmd_lvl_0Reg(10),\n r_cmd_lvl_0Reg(11),\n r_cmd_lvl_0Reg(12),\n r_cmd_lvl_0Reg(13),\n r_cmd_lvl_0Reg(14),\n r_cmd_lvl_0Reg(15)\n\n ))\n\n io.o_reduction_sel := VecInit(Seq(\n r_sel_lvl_4Reg(16),\n r_sel_lvl_4Reg(17), \n r_sel_lvl_4Reg(18), \n r_sel_lvl_4Reg(19), \n r_sel_lvl_3Reg(24),\n r_sel_lvl_3Reg(25), \n r_sel_lvl_3Reg(26), \n r_sel_lvl_3Reg(27), \n r_sel_lvl_3Reg(28), \n r_sel_lvl_3Reg(29), \n r_sel_lvl_3Reg(30),\n r_sel_lvl_3Reg(31), \n r_sel_lvl_2Reg(16),\n r_sel_lvl_2Reg(17),\n r_sel_lvl_2Reg(18),\n r_sel_lvl_2Reg(19),\n r_sel_lvl_2Reg(20),\n r_sel_lvl_2Reg(21),\n r_sel_lvl_2Reg(22),\n r_sel_lvl_2Reg(23)\n \n ))\n}", "groundtruth": " }.otherwise {\n r_reduction_add(30.U + x.U) := 0.U\n r_reduction_cmd( 30.U + x.U) := \"b000\".U\n }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.8, "category_reason": ".otherwise clause"} {"task_id": "magma-si", "path": "magma-si/src/main/scala/components/FanNetwork.scala", "left_context": "package magmasi.components\n\nimport chisel3._\nimport chisel3.util._\n\nclass FanNetworkcom(Num : Int = 32 , Data_type : 32 ) extends Module {\n val io = IO(new Bundle{\n val i_valid = Input(UInt(1.W))\n val i_data_bus = Input(Vec(Num, UInt(Data_type.W)))\n val i_add_en_bus = Input(Vec(Num - 1, UInt(1.W)))\n val i_cmd_bus = Input(Vec(Num - 1, UInt(3.W)))\n val i_sel_bus = Input(Vec(20, UInt(2.W)))\n val o_valid = Output(Vec(Num, UInt(1.W)))\n val o_data_bus = Output(Vec(Num, UInt(Data_type.W)))\n val o_adder = Output(Vec(Num, UInt(Data_type.W)))\n\n })\n val clk = clock\n val rst = reset.asBool\n\n var w_fan_lvl_0 = WireInit(VecInit(Seq.fill(30)(0.U(960.W))))\n var w_fan_lvl_1 = WireInit(VecInit(Seq.fill(14)(0.U(480.W))))\n var w_fan_lvl_2 = WireInit(VecInit(Seq.fill(6)(0.U(192.W))))\n var w_fan_lvl_3 = WireInit(VecInit(Seq.fill(2)(0.U(64.W))))\n var w_fan_lvl_4 = WireInit(VecInit(Seq.fill(1)(0.U(32.W))))\n\n var r_fan_ff_lvl_0_to_4 = RegInit(VecInit(Seq.fill(2)(0.U(32.W))))\n var r_fan_ff_lvl_0_to_3 = RegInit(VecInit(Seq.fill(6)(0.U(32.W))))\n var r_fan_ff_lvl_0_to_2 = RegInit(VecInit(Seq.fill(14)(0.U(32.W))))\n var r_fan_ff_lvl_1_to_4 = RegInit(VecInit(Seq.fill(2)(0.U(32.W))))\n var r_fan_ff_lvl_1_to_3 = RegInit(VecInit(Seq.fill(6)(0.U(32.W))))\n var r_fan_ff_lvl_2_to_4 = RegInit(VecInit(Seq.fill(2)(0.U(32.W))))\n\n val w_vn_lvl_0 = WireInit(VecInit(Seq.fill(32)(0.U(32.W))))\n val w_vn_lvl_0_valid = WireInit(VecInit(Seq.fill(32)(0.U(1.W))))\n val w_vn_lvl_1 = WireInit(VecInit(Seq.fill(16)(0.U(32.W))))\n val w_vn_lvl_1_valid = WireInit(VecInit(Seq.fill(16)(0.U(1.W))))\n val w_vn_lvl_2 = WireInit(VecInit(Seq.fill(8)(0.U(32.W))))\n val w_vn_lvl_2_valid = WireInit(VecInit(Seq.fill(8)(0.U(1.W))))\n val w_vn_lvl_3 = WireInit(VecInit(Seq.fill(4)(0.U(32.W))))\n val w_vn_lvl_3_valid = WireInit(VecInit(Seq.fill(4)(0.U(1.W))))\n val w_vn_lvl_4 = WireInit(VecInit(Seq.fill(2)(0.U(32.W))))\n val w_vn_lvl_4_valid = WireInit(VecInit(Seq.fill(2)(0.U(1.W))))\n\n val r_lvl_output_ff = RegInit(VecInit(Seq.fill(160)(0.U(32.W))))\n val r_lvl_output_ff_valid = RegInit(VecInit(Seq.fill(160)(0.U(1.W)))) \n val r_valid = RegInit(VecInit(Seq.fill(7)(0.U(1.W))))\n \n val r_final_sum = RegInit(0.U(32.W))\n val r_final_add = RegInit(false.B)\n val r_final_add2 = RegInit(false.B)\n\n r_fan_ff_lvl_0_to_2 := VecInit(Seq(w_fan_lvl_0(2), w_fan_lvl_0(3), w_fan_lvl_0(6),w_fan_lvl_0(7), w_fan_lvl_0(10), w_fan_lvl_0(11),w_fan_lvl_0(14), w_fan_lvl_0(15), w_fan_lvl_0(18),w_fan_lvl_0(19), w_fan_lvl_0(22), w_fan_lvl_0(23),w_fan_lvl_0(26), w_fan_lvl_0(27)))\n r_fan_ff_lvl_0_to_3 := VecInit(Seq(r_fan_ff_lvl_0_to_2(2), r_fan_ff_lvl_0_to_2(3),r_fan_ff_lvl_0_to_2(6), r_fan_ff_lvl_0_to_2(7), r_fan_ff_lvl_0_to_2(10), r_fan_ff_lvl_0_to_2(11)))\n r_fan_ff_lvl_0_to_4 := VecInit(Seq(r_fan_ff_lvl_0_to_3(2), r_fan_ff_lvl_0_to_3(3)))\n r_fan_ff_lvl_1_to_4 := VecInit(Seq(r_fan_ff_lvl_1_to_3(2), r_fan_ff_lvl_1_to_3(3)))\n r_fan_ff_lvl_1_to_3 := VecInit(Seq(w_fan_lvl_1(2), w_fan_lvl_1(3), w_fan_lvl_1(6), w_fan_lvl_1(7), w_fan_lvl_1(10), w_fan_lvl_1(11)))\n r_fan_ff_lvl_2_to_4 := VecInit(Seq(w_fan_lvl_2(2),w_fan_lvl_2(3)))\n\n\n\n// level 0 \n when (w_vn_lvl_0_valid(1)(0) === 1.U && w_vn_lvl_0_valid(0)(0) === 1.U) {\n r_lvl_output_ff(1) := w_vn_lvl_0(1)\n r_lvl_output_ff(0) := w_vn_lvl_0(0)\n r_lvl_output_ff_valid(1) := true.B\n r_lvl_output_ff_valid(0) := true.B\n }.elsewhen (w_vn_lvl_0_valid(1)(0) === 1.U && w_vn_lvl_0_valid(0)(0) === 0.U) {\n r_lvl_output_ff(1) := w_vn_lvl_0(1)\n r_lvl_output_ff(0) := 0.U\n r_lvl_output_ff_valid(1) := true.B\n r_lvl_output_ff_valid(0) := false.B\n }.elsewhen (w_vn_lvl_0_valid(1)(0) === 0.U && w_vn_lvl_0_valid(0)(0) === 1.U) {\n r_lvl_output_ff(1) := 0.U\n r_lvl_output_ff(0) := w_vn_lvl_0(0)\n r_lvl_output_ff_valid(1) := false.B\n r_lvl_output_ff_valid(0) := true.B\n }.otherwise {\n r_lvl_output_ff(1) := 0.U\n r_lvl_output_ff(0) := 0.U\n r_lvl_output_ff_valid(1) := false.B\n r_lvl_output_ff_valid(0) := false.B\n }\n\n when (w_vn_lvl_0_valid(3)(0) === 1.U && w_vn_lvl_0_valid(2)(0) === 1.U) {\n r_lvl_output_ff(3) := w_vn_lvl_0(3)\n r_lvl_output_ff(2) := w_vn_lvl_0(2)\n r_lvl_output_ff_valid(3) := 1.U\n r_lvl_output_ff_valid(2) := 1.U\n }.elsewhen (w_vn_lvl_0_valid(3)(0) === 1.U && w_vn_lvl_0_valid(2)(0) === 0.U) {\n r_lvl_output_ff(3) := w_vn_lvl_0(3)\n r_lvl_output_ff(2) := 0.U\n r_lvl_output_ff_valid(3) := 1.U\n r_lvl_output_ff_valid(2) := 0.U\n }.elsewhen (w_vn_lvl_0_valid(3)(0) === 0.U && w_vn_lvl_0_valid(2)(0) === 1.U) {\n r_lvl_output_ff(3) := 0.U\n r_lvl_output_ff(2) := w_vn_lvl_0(2)\n r_lvl_output_ff_valid(3) := 0.U\n r_lvl_output_ff_valid(2) := 1.U\n }.otherwise {\n r_lvl_output_ff(3) := 0.U\n r_lvl_output_ff(2) := 0.U\n r_lvl_output_ff_valid(3) := 0.U\n r_lvl_output_ff_valid(2) := 0.U\n }\n\n when (w_vn_lvl_0_valid(5)(0) === 1.U && w_vn_lvl_0_valid(4)(0) === 1.U) {\n r_lvl_output_ff(5) := w_vn_lvl_0(5)\n r_lvl_output_ff(4) := w_vn_lvl_0(4)\n r_lvl_output_ff_valid(5) := true.B\n r_lvl_output_ff_valid(4) := true.B\n }.elsewhen (w_vn_lvl_0_valid(5)(0) === 1.U && w_vn_lvl_0_valid(4)(0) === 0.U) {\n r_lvl_output_ff(5) := w_vn_lvl_0(5)\n r_lvl_output_ff(4) := 0.U\n r_lvl_output_ff_valid(5) := true.B\n r_lvl_output_ff_valid(4) := false.B\n }.elsewhen (w_vn_lvl_0_valid(5)(0) === 0.U && w_vn_lvl_0_valid(4)(0) === 1.U) {\n r_lvl_output_ff(5) := 0.U\n r_lvl_output_ff(4) := w_vn_lvl_0(4)\n r_lvl_output_ff_valid(5) := false.B\n r_lvl_output_ff_valid(4) := true.B\n }.otherwise {\n r_lvl_output_ff(5) := 0.U\n r_lvl_output_ff(4) := 0.U\n r_lvl_output_ff_valid(5) := false.B\n r_lvl_output_ff_valid(4) := false.B\n }\n\n\n when (w_vn_lvl_0_valid(7)(0) === 1.U && w_vn_lvl_0_valid(6)(0) === 1.U) {\n r_lvl_output_ff(7) := w_vn_lvl_0(7)\n r_lvl_output_ff(6) := w_vn_lvl_0(6)\n r_lvl_output_ff_valid(7) := true.B\n r_lvl_output_ff_valid(6) := true.B\n }.elsewhen (w_vn_lvl_0_valid(7)(0) === 1.U && w_vn_lvl_0_valid(6)(0) === 0.U) {\n r_lvl_output_ff(7) := w_vn_lvl_0(7)\n r_lvl_output_ff(6) := 0.U\n r_lvl_output_ff_valid(7) := true.B\n r_lvl_output_ff_valid(6) := false.B\n }.elsewhen (w_vn_lvl_0_valid(7)(0) === 0.U && w_vn_lvl_0_valid(6)(0) === 1.U) {\n r_lvl_output_ff(7) := 0.U\n r_lvl_output_ff(6) := w_vn_lvl_0(6)\n r_lvl_output_ff_valid(7) := false.B\n r_lvl_output_ff_valid(6) := true.B\n }.otherwise {\n r_lvl_output_ff(7) := 0.U\n r_lvl_output_ff(6) := 0.U\n r_lvl_output_ff_valid(7) := false.B\n r_lvl_output_ff_valid(6) := false.B\n }\n\n \n when (w_vn_lvl_0_valid(9)(0) && w_vn_lvl_0_valid(8)(0)) {\n r_lvl_output_ff(9) := w_vn_lvl_0(9)\n r_lvl_output_ff(8) := w_vn_lvl_0(8)\n r_lvl_output_ff_valid(9) := true.B\n r_lvl_output_ff_valid(8) := true.B\n }.elsewhen (w_vn_lvl_0_valid(9)(0) && !w_vn_lvl_0_valid(8)(0)) {\n r_lvl_output_ff(9) := w_vn_lvl_0(9)\n r_lvl_output_ff(8) := 0.U\n r_lvl_output_ff_valid(9) := true.B\n r_lvl_output_ff_valid(8) := false.B\n }.elsewhen (!w_vn_lvl_0_valid(9)(0) && w_vn_lvl_0_valid(8)(0)) {\n r_lvl_output_ff(9) := 0.U\n r_lvl_output_ff(8) := w_vn_lvl_0(8)\n r_lvl_output_ff_valid(9) := false.B\n r_lvl_output_ff_valid(8) := true.B\n }.otherwise {\n r_lvl_output_ff(9) := 0.U\n r_lvl_output_ff(8) := 0.U\n r_lvl_output_ff_valid(9) := false.B\n r_lvl_output_ff_valid(8) := false.B\n }\n\n\n when (w_vn_lvl_0_valid(11)(0) && w_vn_lvl_0_valid(10)(0)) {\n r_lvl_output_ff(11) := w_vn_lvl_0(11)\n r_lvl_output_ff(10) := w_vn_lvl_0(10)\n r_lvl_output_ff_valid(11) := true.B\n r_lvl_output_ff_valid(10) := true.B\n }.elsewhen (w_vn_lvl_0_valid(11)(0) && !w_vn_lvl_0_valid(10)(0)) {\n r_lvl_output_ff(11) := w_vn_lvl_0(11)\n r_lvl_output_ff(10) := 0.U\n r_lvl_output_ff_valid(11) := true.B\n r_lvl_output_ff_valid(10) := false.B\n }.elsewhen (!w_vn_lvl_0_valid(11)(0) && w_vn_lvl_0_valid(10)(0)) {\n r_lvl_output_ff(11) := 0.U\n r_lvl_output_ff(10) := w_vn_lvl_0(10)\n r_lvl_output_ff_valid(11) := false.B\n r_lvl_output_ff_valid(10) := true.B\n }.otherwise {\n r_lvl_output_ff(11) := 0.U\n r_lvl_output_ff(10) := 0.U\n r_lvl_output_ff_valid(11) := false.B\n r_lvl_output_ff_valid(10) := false.B\n }\n\n\n when (w_vn_lvl_0_valid(13)(0) && w_vn_lvl_0_valid(12)(0)) {\n r_lvl_output_ff(13) := w_vn_lvl_0(13)\n r_lvl_output_ff(12) := w_vn_lvl_0(12)\n r_lvl_output_ff_valid(13) := true.B\n r_lvl_output_ff_valid(12) := true.B\n }.elsewhen (w_vn_lvl_0_valid(13)(0) && !w_vn_lvl_0_valid(12)(0)) {\n r_lvl_output_ff(13) := w_vn_lvl_0(13)\n r_lvl_output_ff(12) := 0.U\n r_lvl_output_ff_valid(13) := true.B\n r_lvl_output_ff_valid(12) := false.B\n }.elsewhen (!w_vn_lvl_0_valid(13)(0) && w_vn_lvl_0_valid(12)(0)) {\n r_lvl_output_ff(13) := 0.U\n r_lvl_output_ff(12) := w_vn_lvl_0(12)\n r_lvl_output_ff_valid(13) := false.B\n r_lvl_output_ff_valid(12) := true.B\n }.otherwise {\n r_lvl_output_ff(13) := 0.U\n r_lvl_output_ff(12) := 0.U\n r_lvl_output_ff_valid(13) := false.B\n r_lvl_output_ff_valid(12) := false.B\n }\n\n\n when (w_vn_lvl_0_valid(15)(0) && w_vn_lvl_0_valid(14)(0)) {\n r_lvl_output_ff(15) := w_vn_lvl_0(15)\n r_lvl_output_ff(14) := w_vn_lvl_0(14)\n r_lvl_output_ff_valid(15) := true.B\n r_lvl_output_ff_valid(14) := true.B\n }.elsewhen (w_vn_lvl_0_valid(15)(0) && !w_vn_lvl_0_valid(14)(0)) {\n r_lvl_output_ff(15) := w_vn_lvl_0(15)\n r_lvl_output_ff(14) := 0.U\n r_lvl_output_ff_valid(15) := true.B\n r_lvl_output_ff_valid(14) := false.B\n }.elsewhen (!w_vn_lvl_0_valid(15)(0) && w_vn_lvl_0_valid(14)(0)) {\n r_lvl_output_ff(15) := 0.U\n r_lvl_output_ff(14) := w_vn_lvl_0(14)\n r_lvl_output_ff_valid(15) := false.B\n r_lvl_output_ff_valid(14) := true.B\n }.otherwise {\n r_lvl_output_ff(15) := 0.U\n r_lvl_output_ff(14) := 0.U\n r_lvl_output_ff_valid(15) := false.B\n r_lvl_output_ff_valid(14) := false.B\n }\n\n\n when (w_vn_lvl_0_valid(17)(0) && w_vn_lvl_0_valid(16)(0)) {\n r_lvl_output_ff(17) := w_vn_lvl_0(17)\n r_lvl_output_ff(16) := w_vn_lvl_0(16)\n r_lvl_output_ff_valid(17) := true.B\n r_lvl_output_ff_valid(16) := true.B\n }.elsewhen (w_vn_lvl_0_valid(17)(0) && !w_vn_lvl_0_valid(16)(0)) {\n r_lvl_output_ff(17) := w_vn_lvl_0(17)\n r_lvl_output_ff(16) := 0.U\n r_lvl_output_ff_valid(17) := true.B\n r_lvl_output_ff_valid(16) := false.B\n }.elsewhen (!w_vn_lvl_0_valid(17)(0) && w_vn_lvl_0_valid(16)(0)) {\n r_lvl_output_ff(17) := 0.U\n r_lvl_output_ff(16) := w_vn_lvl_0(16)\n r_lvl_output_ff_valid(17) := false.B\n r_lvl_output_ff_valid(16) := true.B\n }.otherwise {\n r_lvl_output_ff(17) := 0.U\n r_lvl_output_ff(16) := 0.U\n r_lvl_output_ff_valid(17) := false.B\n r_lvl_output_ff_valid(16) := false.B\n }\n\n\n when (w_vn_lvl_0_valid(19)(0) && w_vn_lvl_0_valid(18)(0)) {\n r_lvl_output_ff(19) := w_vn_lvl_0(19)\n r_lvl_output_ff(18) := w_vn_lvl_0(18)\n r_lvl_output_ff_valid(19) := true.B\n r_lvl_output_ff_valid(18) := true.B\n }.elsewhen (w_vn_lvl_0_valid(19)(0) && !w_vn_lvl_0_valid(18)(0)) {\n r_lvl_output_ff(19) := w_vn_lvl_0(19)\n r_lvl_output_ff(18) := 0.U\n r_lvl_output_ff_valid(19) := true.B\n r_lvl_output_ff_valid(18) := false.B\n }.elsewhen (!w_vn_lvl_0_valid(19)(0) && w_vn_lvl_0_valid(18)(0)) {\n r_lvl_output_ff(19) := 0.U\n r_lvl_output_ff(18) := w_vn_lvl_0(18)\n r_lvl_output_ff_valid(19) := false.B\n r_lvl_output_ff_valid(18) := true.B\n }.otherwise {\n r_lvl_output_ff(19) := 0.U\n r_lvl_output_ff(18) := 0.U\n r_lvl_output_ff_valid(19) := false.B\n r_lvl_output_ff_valid(18) := false.B\n }\n\n\n when (w_vn_lvl_0_valid(21)(0) && w_vn_lvl_0_valid(20)(0)) {\n r_lvl_output_ff(21) := w_vn_lvl_0(21)\n r_lvl_output_ff(20) := w_vn_lvl_0(20)\n r_lvl_output_ff_valid(21) := true.B\n r_lvl_output_ff_valid(20) := true.B\n }.elsewhen (w_vn_lvl_0_valid(21)(0) && !w_vn_lvl_0_valid(20)(0)) {\n r_lvl_output_ff(21) := w_vn_lvl_0(21)\n r_lvl_output_ff(20) := 0.U\n r_lvl_output_ff_valid(21) := true.B\n r_lvl_output_ff_valid(20) := false.B\n }.elsewhen (!w_vn_lvl_0_valid(21)(0) && w_vn_lvl_0_valid(20)(0)) {\n r_lvl_output_ff(21) := 0.U\n r_lvl_output_ff(20) := w_vn_lvl_0(20)\n r_lvl_output_ff_valid(21) := false.B\n r_lvl_output_ff_valid(20) := true.B\n }.otherwise {\n r_lvl_output_ff(21) := 0.U\n r_lvl_output_ff(20) := 0.U\n r_lvl_output_ff_valid(21) := false.B\n r_lvl_output_ff_valid(20) := false.B\n }\n\n\n when (w_vn_lvl_0_valid(23)(0) && w_vn_lvl_0_valid(22)(0)) {\n r_lvl_output_ff(23) := w_vn_lvl_0(23)\n r_lvl_output_ff(22) := w_vn_lvl_0(22)\n r_lvl_output_ff_valid(23) := true.B\n r_lvl_output_ff_valid(22) := true.B\n }.elsewhen (w_vn_lvl_0_valid(23)(0) && !w_vn_lvl_0_valid(22)(0)) {\n r_lvl_output_ff(23) := w_vn_lvl_0(23)\n r_lvl_output_ff(22) := 0.U\n r_lvl_output_ff_valid(23) := true.B\n r_lvl_output_ff_valid(22) := false.B\n }.elsewhen (!w_vn_lvl_0_valid(23)(0) && w_vn_lvl_0_valid(22)(0)) {\n r_lvl_output_ff(23) := 0.U\n r_lvl_output_ff(22) := w_vn_lvl_0(22)\n r_lvl_output_ff_valid(23) := false.B\n r_lvl_output_ff_valid(22) := true.B\n }.otherwise {\n r_lvl_output_ff(23) := 0.U\n r_lvl_output_ff(22) := 0.U\n r_lvl_output_ff_valid(23) := false.B\n r_lvl_output_ff_valid(22) := false.B\n }\n\n\n when (w_vn_lvl_0_valid(25)(0) && w_vn_lvl_0_valid(24)(0)) {\n r_lvl_output_ff(25) := w_vn_lvl_0(25)\n r_lvl_output_ff(24) := w_vn_lvl_0(24)\n r_lvl_output_ff_valid(25) := true.B\n r_lvl_output_ff_valid(24) := true.B\n }.elsewhen (w_vn_lvl_0_valid(25)(0) && !w_vn_lvl_0_valid(24)(0)) {\n r_lvl_output_ff(25) := w_vn_lvl_0(25)\n r_lvl_output_ff(24) := 0.U\n r_lvl_output_ff_valid(25) := true.B\n r_lvl_output_ff_valid(24) := false.B\n }.elsewhen (!w_vn_lvl_0_valid(25)(0) && w_vn_lvl_0_valid(24)(0)) {\n r_lvl_output_ff(25) := 0.U\n r_lvl_output_ff(24) := w_vn_lvl_0(24)\n r_lvl_output_ff_valid(25) := false.B\n r_lvl_output_ff_valid(24) := true.B\n }.otherwise {\n r_lvl_output_ff(25) := 0.U\n r_lvl_output_ff(24) := 0.U\n r_lvl_output_ff_valid(25) := false.B\n r_lvl_output_ff_valid(24) := false.B\n }\n\n\n when (w_vn_lvl_0_valid(27)(0) && w_vn_lvl_0_valid(26)(0)) {\n r_lvl_output_ff(27) := w_vn_lvl_0(27)\n r_lvl_output_ff(26) := w_vn_lvl_0(26)\n r_lvl_output_ff_valid(27) := true.B\n r_lvl_output_ff_valid(26) := true.B\n }.elsewhen (w_vn_lvl_0_valid(27)(0) && !w_vn_lvl_0_valid(26)(0)) {\n r_lvl_output_ff(27) := w_vn_lvl_0(27)\n r_lvl_output_ff(26) := 0.U\n r_lvl_output_ff_valid(27) := true.B\n r_lvl_output_ff_valid(26) := false.B\n }.elsewhen (!w_vn_lvl_0_valid(27)(0) && w_vn_lvl_0_valid(26)(0)) {\n r_lvl_output_ff(27) := 0.U\n r_lvl_output_ff(26) := w_vn_lvl_0(26)\n r_lvl_output_ff_valid(27) := false.B\n r_lvl_output_ff_valid(26) := true.B\n }.otherwise {\n r_lvl_output_ff(27) := 0.U\n r_lvl_output_ff(26) := 0.U\n r_lvl_output_ff_valid(27) := false.B\n r_lvl_output_ff_valid(26) := false.B\n }\n\n\n when (w_vn_lvl_0_valid(29)(0) && w_vn_lvl_0_valid(28)(0)) {\n r_lvl_output_ff(29) := w_vn_lvl_0(29)\n r_lvl_output_ff(28) := w_vn_lvl_0(28)\n r_lvl_output_ff_valid(29) := true.B\n r_lvl_output_ff_valid(28) := true.B\n }.elsewhen (w_vn_lvl_0_valid(29)(0) && !w_vn_lvl_0_valid(28)(0)) {\n r_lvl_output_ff(29) := w_vn_lvl_0(29)\n r_lvl_output_ff(28) := 0.U\n r_lvl_output_ff_valid(29) := true.B\n r_lvl_output_ff_valid(28) := false.B\n }.elsewhen (!w_vn_lvl_0_valid(29)(0) && w_vn_lvl_0_valid(28)(0)) {\n r_lvl_output_ff(29) := 0.U\n r_lvl_output_ff(28) := w_vn_lvl_0(28)\n r_lvl_output_ff_valid(29) := false.B\n r_lvl_output_ff_valid(28) := true.B\n }.otherwise {\n r_lvl_output_ff(29) := 0.U\n r_lvl_output_ff(28) := 0.U\n r_lvl_output_ff_valid(29) := false.B\n r_lvl_output_ff_valid(28) := false.B\n }\n\n\n when(w_vn_lvl_0_valid(31)(0) && w_vn_lvl_0_valid(30)(0)) {\n r_lvl_output_ff(31) := w_vn_lvl_0(31)\n r_lvl_output_ff(30) := w_vn_lvl_0(30)\n r_lvl_output_ff_valid(31) := true.B\n r_lvl_output_ff_valid(30) := true.B\n }.elsewhen(w_vn_lvl_0_valid(31)(0) && !w_vn_lvl_0_valid(30)(0)) {\n r_lvl_output_ff(31) := w_vn_lvl_0(31)\n r_lvl_output_ff(30) := 0.U\n r_lvl_output_ff_valid(31) := true.B\n r_lvl_output_ff_valid(30) := false.B\n }.elsewhen(!w_vn_lvl_0_valid(31)(0) && w_vn_lvl_0_valid(30)(0)) {\n r_lvl_output_ff(31) := 0.U\n r_lvl_output_ff(30) := w_vn_lvl_0(30)\n r_lvl_output_ff_valid(31) := false.B\n r_lvl_output_ff_valid(30) := true.B\n }.otherwise {\n r_lvl_output_ff(31) := 0.U\n r_lvl_output_ff(30) := 0.U\n r_lvl_output_ff_valid(31) := false.B\n r_lvl_output_ff_valid(30) := false.B\n }\n\n\n\n// level 1\n r_lvl_output_ff(32) := r_lvl_output_ff(0)\n r_lvl_output_ff_valid(32) := r_lvl_output_ff_valid(0)\n\n when(w_vn_lvl_1_valid(0)(0)) {\n r_lvl_output_ff(33) := w_vn_lvl_1(0)\n r_lvl_output_ff_valid(33) := true.B\n }.otherwise {\n r_lvl_output_ff(33) := r_lvl_output_ff(1)\n r_lvl_output_ff_valid(33) := r_lvl_output_ff_valid(1)\n }\n\n when(w_vn_lvl_1_valid(1)(0)) {\n r_lvl_output_ff(34) := w_vn_lvl_1(1)\n r_lvl_output_ff_valid(34) := true.B\n }.otherwise {\n r_lvl_output_ff(34) := r_lvl_output_ff(2)\n r_lvl_output_ff_valid(34) := r_lvl_output_ff_valid(2)\n }\n\n r_lvl_output_ff(35) := r_lvl_output_ff(3)\n r_lvl_output_ff_valid(35) := r_lvl_output_ff_valid(3)\n\n r_lvl_output_ff(36) := r_lvl_output_ff(4)\n r_lvl_output_ff_valid(36) := r_lvl_output_ff_valid(4)\n\n when(w_vn_lvl_1_valid(2)(0)) {\n r_lvl_output_ff(37) := w_vn_lvl_1(2)\n r_lvl_output_ff_valid(37) := true.B\n }.otherwise {\n r_lvl_output_ff(37) := r_lvl_output_ff(5)\n r_lvl_output_ff_valid(37) := r_lvl_output_ff_valid(5)\n }\n\n when(w_vn_lvl_1_valid(3)(0)) {\n r_lvl_output_ff(38) := w_vn_lvl_1(3)\n r_lvl_output_ff_valid(38) := true.B\n }.otherwise {\n r_lvl_output_ff(38) := r_lvl_output_ff(6)\n r_lvl_output_ff_valid(38) := r_lvl_output_ff_valid(6)\n }\n\n\n\n r_lvl_output_ff(39) := r_lvl_output_ff(7)\n r_lvl_output_ff_valid(39) := r_lvl_output_ff_valid(7)\n\n r_lvl_output_ff(40) := r_lvl_output_ff(8)\n r_lvl_output_ff_valid(40) := r_lvl_output_ff_valid(8)\n\n when(w_vn_lvl_1_valid(4)(0)) {\n r_lvl_output_ff(41) := w_vn_lvl_1(4)\n r_lvl_output_ff_valid(41) := true.B\n }.otherwise {\n r_lvl_output_ff(41) := r_lvl_output_ff(9)\n r_lvl_output_ff_valid(41) := r_lvl_output_ff_valid(9)\n }\n when(w_vn_lvl_1_valid(5)(0)) {\n r_lvl_output_ff(42) := w_vn_lvl_1(5)\n r_lvl_output_ff_valid(42) := true.B\n }.otherwise {\n r_lvl_output_ff(42) := r_lvl_output_ff(10)\n r_lvl_output_ff_valid(42) := r_lvl_output_ff_valid(10)\n }\n\n r_lvl_output_ff(43) := r_lvl_output_ff(11)\n r_lvl_output_ff_valid(43) := r_lvl_output_ff_valid(11)\n\n r_lvl_output_ff(44) := r_lvl_output_ff(12)\n r_lvl_output_ff_valid(44) := r_lvl_output_ff_valid(12)\n\n when(w_vn_lvl_1_valid(6)(0)) {\n r_lvl_output_ff(45) := w_vn_lvl_1(6)\n r_lvl_output_ff_valid(45) := true.B\n }.otherwise {\n r_lvl_output_ff(45) := r_lvl_output_ff(13)\n r_lvl_output_ff_valid(45) := r_lvl_output_ff_valid(13)\n }\n\n when(w_vn_lvl_1_valid(7)(0)) {\n r_lvl_output_ff(46) := w_vn_lvl_1(7)\n r_lvl_output_ff_valid(46) := true.B\n }.otherwise {\n r_lvl_output_ff(46) := r_lvl_output_ff(14)\n r_lvl_output_ff_valid(46) := r_lvl_output_ff_valid(14)\n }\n r_lvl_output_ff(47) := r_lvl_output_ff(15)\n r_lvl_output_ff_valid(47) := r_lvl_output_ff_valid(15)\n\n r_lvl_output_ff(48) := r_lvl_output_ff(16)\n r_lvl_output_ff_valid(48) := r_lvl_output_ff_valid(16)\n\n when(w_vn_lvl_1_valid(8)(0)) {\n r_lvl_output_ff(49) := w_vn_lvl_1(8)\n r_lvl_output_ff_valid(49) := true.B\n }.otherwise {\n r_lvl_output_ff(49) := r_lvl_output_ff(17)\n r_lvl_output_ff_valid(49) := r_lvl_output_ff_valid(17)\n }\n\n when(w_vn_lvl_1_valid(9)(0)) {\n r_lvl_output_ff(50) := w_vn_lvl_1(9)\n r_lvl_output_ff_valid(50) := true.B\n }.otherwise {\n r_lvl_output_ff(50) := r_lvl_output_ff(18)\n r_lvl_output_ff_valid(50) := r_lvl_output_ff_valid(18)\n }\n\n\n\n r_lvl_output_ff(51) := r_lvl_output_ff(19)\n r_lvl_output_ff_valid(51) := r_lvl_output_ff_valid(19)\n\n r_lvl_output_ff(52) := r_lvl_output_ff(20)\n r_lvl_output_ff_valid(52) := r_lvl_output_ff_valid(20)\n\n when(w_vn_lvl_1_valid(10)(0)) {\n r_lvl_output_ff(53) := w_vn_lvl_1(10)\n r_lvl_output_ff_valid(53) := true.B\n }.otherwise {\n r_lvl_output_ff(53) := r_lvl_output_ff(21)\n r_lvl_output_ff_valid(53) := r_lvl_output_ff_valid(21)\n }\n\n when(w_vn_lvl_1_valid(11)(0)) {\n r_lvl_output_ff(54) := w_vn_lvl_1(11)\n r_lvl_output_ff_valid(54) := true.B\n }.otherwise {\n r_lvl_output_ff(54) := r_lvl_output_ff(22)\n r_lvl_output_ff_valid(54) := r_lvl_output_ff_valid(22)\n }\n\n r_lvl_output_ff(55) := r_lvl_output_ff(23)\n r_lvl_output_ff_valid(55) := r_lvl_output_ff_valid(23)\n\n r_lvl_output_ff(56) := r_lvl_output_ff(24)\n r_lvl_output_ff_valid(56) := r_lvl_output_ff_valid(24)\n\n when(w_vn_lvl_1_valid(12)(0)) {\n r_lvl_output_ff(57) := w_vn_lvl_1(12)\n r_lvl_output_ff_valid(57) := true.B\n }.otherwise {\n r_lvl_output_ff(57) := r_lvl_output_ff(25)\n r_lvl_output_ff_valid(57) := r_lvl_output_ff_valid(25)\n }\n\n when(w_vn_lvl_1_valid(13)(0)) {\n r_lvl_output_ff(58) := w_vn_lvl_1(13)\n r_lvl_output_ff_valid(58) := true.B\n }.otherwise {\n r_lvl_output_ff(58) := r_lvl_output_ff(26)\n r_lvl_output_ff_valid(58) := r_lvl_output_ff_valid(26)\n }\n\n r_lvl_output_ff(59) := r_lvl_output_ff(27)\n r_lvl_output_ff_valid(59) := r_lvl_output_ff_valid(27)\n\n r_lvl_output_ff(60) := r_lvl_output_ff(28)\n r_lvl_output_ff_valid(60) := r_lvl_output_ff_valid(28)\n\n when(w_vn_lvl_1_valid(14) === true.B) {\n r_lvl_output_ff(61) := w_vn_lvl_1(14)\n r_lvl_output_ff_valid(61) := true.B\n }.otherwise {\n r_lvl_output_ff(61) := r_lvl_output_ff(29)\n r_lvl_output_ff_valid(61) := r_lvl_output_ff_valid(29)\n }\n\n when(w_vn_lvl_1_valid(15) === true.B) {\n r_lvl_output_ff(62) := w_vn_lvl_1(15)\n r_lvl_output_ff_valid(62) := true.B\n }.otherwise {\n r_lvl_output_ff(62) := r_lvl_output_ff(30)\n r_lvl_output_ff_valid(62) := r_lvl_output_ff_valid(30)\n }\n\n r_lvl_output_ff(63) := r_lvl_output_ff(31)\n r_lvl_output_ff_valid(63) := r_lvl_output_ff_valid(31)\n\n// level 2\n r_lvl_output_ff(64) := r_lvl_output_ff(32)\n r_lvl_output_ff_valid(64) := r_lvl_output_ff_valid(32)\n\n r_lvl_output_ff(65) := r_lvl_output_ff(33)\n r_lvl_output_ff_valid(65) := r_lvl_output_ff_valid(33)\n\n r_lvl_output_ff(66) := r_lvl_output_ff(34)\n r_lvl_output_ff_valid(66) := r_lvl_output_ff_valid(34)\n\n when (w_vn_lvl_2_valid(0) === true.B) {\n r_lvl_output_ff(67) := w_vn_lvl_2(0)\n r_lvl_output_ff_valid(67) := true.B\n", "right_context": " r_lvl_output_ff_valid(68) := true.B\n }.otherwise {\n r_lvl_output_ff(68) := r_lvl_output_ff(36)\n r_lvl_output_ff_valid(68) := r_lvl_output_ff_valid(36)\n }\n \n r_lvl_output_ff(69) := r_lvl_output_ff(37)\n r_lvl_output_ff_valid(69) := r_lvl_output_ff_valid(37)\n\n r_lvl_output_ff(70) := r_lvl_output_ff(38)\n r_lvl_output_ff_valid(70) := r_lvl_output_ff_valid(38)\n\n r_lvl_output_ff(71) := r_lvl_output_ff(39)\n r_lvl_output_ff_valid(71) := r_lvl_output_ff_valid(39)\n\n r_lvl_output_ff(72) := r_lvl_output_ff(40)\n r_lvl_output_ff_valid(72) := r_lvl_output_ff_valid(40)\n\n r_lvl_output_ff(73) := r_lvl_output_ff(41)\n r_lvl_output_ff_valid(73) := r_lvl_output_ff_valid(41)\n\n r_lvl_output_ff(74) := r_lvl_output_ff(42)\n r_lvl_output_ff_valid(74) := r_lvl_output_ff_valid(42)\n\n when (w_vn_lvl_2_valid(2) === true.B) {\n r_lvl_output_ff(75) := w_vn_lvl_2(2)\n r_lvl_output_ff_valid(75) := true.B\n }.otherwise {\n r_lvl_output_ff(75) := r_lvl_output_ff(43)\n r_lvl_output_ff_valid(75) := r_lvl_output_ff_valid(43)\n }\n\n when (w_vn_lvl_2_valid(3) === true.B) {\n r_lvl_output_ff(76) := w_vn_lvl_2(3)\n r_lvl_output_ff_valid(76) := true.B\n }.otherwise {\n r_lvl_output_ff(76) := r_lvl_output_ff(44)\n r_lvl_output_ff_valid(76) := r_lvl_output_ff_valid(44)\n }\n\n r_lvl_output_ff(77) := r_lvl_output_ff(45)\n r_lvl_output_ff_valid(77) := r_lvl_output_ff_valid(45)\n\n r_lvl_output_ff(78) := r_lvl_output_ff(46)\n r_lvl_output_ff_valid(78) := r_lvl_output_ff_valid(46)\n\n r_lvl_output_ff(79) := r_lvl_output_ff(47)\n r_lvl_output_ff_valid(79) := r_lvl_output_ff_valid(47)\n\n r_lvl_output_ff(80) := r_lvl_output_ff(48)\n r_lvl_output_ff_valid(80) := r_lvl_output_ff_valid(48)\n\n r_lvl_output_ff(81) := r_lvl_output_ff(49)\n r_lvl_output_ff_valid(81) := r_lvl_output_ff_valid(49)\n\n r_lvl_output_ff(82) := r_lvl_output_ff(50)\n r_lvl_output_ff_valid(82) := r_lvl_output_ff_valid(50)\n\n when (w_vn_lvl_2_valid(4) === true.B) {\n r_lvl_output_ff(83) := w_vn_lvl_2(4)\n r_lvl_output_ff_valid(83) := true.B\n } otherwise {\n r_lvl_output_ff(83) := r_lvl_output_ff(51)\n r_lvl_output_ff_valid(83) := r_lvl_output_ff_valid(51)\n }\n\n when (w_vn_lvl_2_valid(5) === 1.B) {\n r_lvl_output_ff(84) := w_vn_lvl_2(5)\n r_lvl_output_ff_valid(84) := true.B\n } otherwise {\n r_lvl_output_ff(84) := r_lvl_output_ff(52)\n r_lvl_output_ff_valid(84) := r_lvl_output_ff_valid(52)\n }\n\n r_lvl_output_ff(85) := r_lvl_output_ff(53)\n r_lvl_output_ff_valid(85) := r_lvl_output_ff_valid(53)\n\n r_lvl_output_ff(86) := r_lvl_output_ff(54)\n r_lvl_output_ff_valid(86) := r_lvl_output_ff_valid(54)\n\n r_lvl_output_ff(87) := r_lvl_output_ff(55)\n r_lvl_output_ff_valid(87) := r_lvl_output_ff_valid(55)\n\n r_lvl_output_ff(88) := r_lvl_output_ff(56)\n r_lvl_output_ff_valid(88) := r_lvl_output_ff_valid(56)\n\n r_lvl_output_ff(89) := r_lvl_output_ff(57)\n r_lvl_output_ff_valid(89) := r_lvl_output_ff_valid(57)\n\n r_lvl_output_ff(90) := r_lvl_output_ff(58)\n r_lvl_output_ff_valid(90) := r_lvl_output_ff_valid(58)\n\n when (w_vn_lvl_2_valid(6) === 1.B) {\n r_lvl_output_ff(91) := w_vn_lvl_2(6)\n r_lvl_output_ff_valid(91) := true.B\n } otherwise {\n r_lvl_output_ff(91) := r_lvl_output_ff(59)\n r_lvl_output_ff_valid(91) := r_lvl_output_ff_valid(59)\n }\n\n when (w_vn_lvl_2_valid(7) === 1.B) {\n r_lvl_output_ff(92) := w_vn_lvl_2(7)\n r_lvl_output_ff_valid(92) := true.B\n } otherwise {\n r_lvl_output_ff(92) := r_lvl_output_ff(60)\n r_lvl_output_ff_valid(92) := r_lvl_output_ff_valid(60)\n }\n\n r_lvl_output_ff(93) := r_lvl_output_ff(61)\n r_lvl_output_ff_valid(93) := r_lvl_output_ff_valid(61)\n\n r_lvl_output_ff(94) := r_lvl_output_ff(62)\n r_lvl_output_ff_valid(94) := r_lvl_output_ff_valid(62)\n\n r_lvl_output_ff(95) := r_lvl_output_ff(63)\n r_lvl_output_ff_valid(95) := r_lvl_output_ff_valid(63)\n\n// level3\n\n r_lvl_output_ff(96) := r_lvl_output_ff(64)\n r_lvl_output_ff_valid(96) := r_lvl_output_ff_valid(64)\n\n r_lvl_output_ff(97) := r_lvl_output_ff(65)\n r_lvl_output_ff_valid(97) := r_lvl_output_ff_valid(65)\n\n r_lvl_output_ff(98) := r_lvl_output_ff(66)\n r_lvl_output_ff_valid(98) := r_lvl_output_ff_valid(66)\n\n r_lvl_output_ff(99) := r_lvl_output_ff(67)\n r_lvl_output_ff_valid(99) := r_lvl_output_ff_valid(67)\n\n r_lvl_output_ff(100) := r_lvl_output_ff(68)\n r_lvl_output_ff_valid(100) := r_lvl_output_ff_valid(68)\n\n r_lvl_output_ff(101) := r_lvl_output_ff(69)\n r_lvl_output_ff_valid(101) := r_lvl_output_ff_valid(69)\n\n r_lvl_output_ff(102) := r_lvl_output_ff(70)\n r_lvl_output_ff_valid(102) := r_lvl_output_ff_valid(70)\n\n when (w_vn_lvl_3_valid(0) === 1.B) {\n r_lvl_output_ff(103) := w_vn_lvl_3(0)\n r_lvl_output_ff_valid(103) := true.B\n } .otherwise {\n r_lvl_output_ff(103) := r_lvl_output_ff(71)\n r_lvl_output_ff_valid(103) := r_lvl_output_ff_valid(71)\n }\n\n when (w_vn_lvl_3_valid(1) === 1.B) {\n r_lvl_output_ff(104) := w_vn_lvl_3(1)\n r_lvl_output_ff_valid(104) := true.B\n } .otherwise {\n r_lvl_output_ff(104) := r_lvl_output_ff(72)\n r_lvl_output_ff_valid(104) := r_lvl_output_ff_valid(72)\n }\n\n r_lvl_output_ff(105) := r_lvl_output_ff(73)\n r_lvl_output_ff_valid(105) := r_lvl_output_ff_valid(73)\n\n r_lvl_output_ff(106) := r_lvl_output_ff(74)\n r_lvl_output_ff_valid(106) := r_lvl_output_ff_valid(74)\n\n r_lvl_output_ff(107) := r_lvl_output_ff(75)\n r_lvl_output_ff_valid(107) := r_lvl_output_ff_valid(75)\n\n r_lvl_output_ff(108) := r_lvl_output_ff(76)\n r_lvl_output_ff_valid(108) := r_lvl_output_ff_valid(76)\n\n r_lvl_output_ff(109) := r_lvl_output_ff(77)\n r_lvl_output_ff_valid(109) := r_lvl_output_ff_valid(77)\n\n r_lvl_output_ff(110) := r_lvl_output_ff(78)\n r_lvl_output_ff_valid(110) := r_lvl_output_ff_valid(78)\n\n r_lvl_output_ff(11) := r_lvl_output_ff(79)\n r_lvl_output_ff_valid(111) := r_lvl_output_ff_valid(79)\n\n r_lvl_output_ff(112) := r_lvl_output_ff(80)\n r_lvl_output_ff_valid(112) := r_lvl_output_ff_valid(80)\n\n r_lvl_output_ff(113) := r_lvl_output_ff(81)\n r_lvl_output_ff_valid(113) := r_lvl_output_ff_valid(81)\n\n r_lvl_output_ff(114) := r_lvl_output_ff(82)\n r_lvl_output_ff_valid(114) := r_lvl_output_ff_valid(82)\n\n r_lvl_output_ff(115) := r_lvl_output_ff(83)\n r_lvl_output_ff_valid(115) := r_lvl_output_ff_valid(83)\n\n r_lvl_output_ff(116) := r_lvl_output_ff(84)\n r_lvl_output_ff_valid(116) := r_lvl_output_ff_valid(84)\n\n r_lvl_output_ff(117) := r_lvl_output_ff(85)\n r_lvl_output_ff_valid(117) := r_lvl_output_ff_valid(85)\n\n r_lvl_output_ff(118) := r_lvl_output_ff(86)\n r_lvl_output_ff_valid(118) := r_lvl_output_ff_valid(86)\n\n when (w_vn_lvl_3_valid(2) === 1.B) {\n r_lvl_output_ff(119) := w_vn_lvl_3(2)\n r_lvl_output_ff_valid(119) := true.B\n } .otherwise {\n r_lvl_output_ff(119) := r_lvl_output_ff(87)\n r_lvl_output_ff_valid(119) := r_lvl_output_ff_valid(87)\n }\n\n when (w_vn_lvl_3_valid(3) === 1.B) {\n r_lvl_output_ff(120) := w_vn_lvl_3(3)\n r_lvl_output_ff_valid(120) := true.B\n } .otherwise {\n r_lvl_output_ff(120) := r_lvl_output_ff(88)\n r_lvl_output_ff_valid(120) := r_lvl_output_ff_valid(88)\n }\n\n r_lvl_output_ff(121) := r_lvl_output_ff(89)\n r_lvl_output_ff_valid(121) := r_lvl_output_ff_valid(89)\n\n r_lvl_output_ff(122) := r_lvl_output_ff(90)\n r_lvl_output_ff_valid(122) := r_lvl_output_ff_valid(90)\n\n r_lvl_output_ff(123) := r_lvl_output_ff(91)\n r_lvl_output_ff_valid(123) := r_lvl_output_ff_valid(91)\n\n r_lvl_output_ff(124) := r_lvl_output_ff(92)\n r_lvl_output_ff_valid(124) := r_lvl_output_ff_valid(92)\n\n r_lvl_output_ff(125) := r_lvl_output_ff(93)\n r_lvl_output_ff_valid(125) := r_lvl_output_ff_valid(93)\n\n r_lvl_output_ff(126) := r_lvl_output_ff(94)\n r_lvl_output_ff_valid(126) := r_lvl_output_ff_valid(94)\n\n r_lvl_output_ff(127) := r_lvl_output_ff(95)\n r_lvl_output_ff_valid(127) := r_lvl_output_ff_valid(95)\n\n// level 4\n r_lvl_output_ff(128) := r_lvl_output_ff(96)\n r_lvl_output_ff_valid(128) := r_lvl_output_ff_valid(96)\n\n r_lvl_output_ff(129) := r_lvl_output_ff(97)\n r_lvl_output_ff_valid(129) := r_lvl_output_ff_valid(97)\n\n r_lvl_output_ff(130) := r_lvl_output_ff(98)\n r_lvl_output_ff_valid(130) := r_lvl_output_ff_valid(98)\n\n r_lvl_output_ff(131) := r_lvl_output_ff(99)\n r_lvl_output_ff_valid(131) := r_lvl_output_ff_valid(99)\n\n r_lvl_output_ff(132) := r_lvl_output_ff(100)\n r_lvl_output_ff_valid(132) := r_lvl_output_ff_valid(100)\n\n r_lvl_output_ff(133) := r_lvl_output_ff(101)\n r_lvl_output_ff_valid(133) := r_lvl_output_ff_valid(101)\n\n r_lvl_output_ff(134) := r_lvl_output_ff(102)\n r_lvl_output_ff_valid(134) := r_lvl_output_ff_valid(102)\n\n r_lvl_output_ff(135) := r_lvl_output_ff(103)\n r_lvl_output_ff_valid(135) := r_lvl_output_ff_valid(103)\n\n r_lvl_output_ff(136) := r_lvl_output_ff(104)\n r_lvl_output_ff_valid(136) := r_lvl_output_ff_valid(104)\n\n r_lvl_output_ff(137) := r_lvl_output_ff(105)\n r_lvl_output_ff_valid(137) := r_lvl_output_ff_valid(105)\n\n r_lvl_output_ff(138) := r_lvl_output_ff(106)\n r_lvl_output_ff_valid(138) := r_lvl_output_ff_valid(106)\n\n r_lvl_output_ff(139) := r_lvl_output_ff(107)\n r_lvl_output_ff_valid(139) := r_lvl_output_ff_valid(107)\n\n r_lvl_output_ff(140) := r_lvl_output_ff(108)\n r_lvl_output_ff_valid(140) := r_lvl_output_ff_valid(108)\n\n r_lvl_output_ff(141) := r_lvl_output_ff(109)\n r_lvl_output_ff_valid(141) := r_lvl_output_ff_valid(109)\n\n r_lvl_output_ff(142) := r_lvl_output_ff(110)\n r_lvl_output_ff_valid(142) := r_lvl_output_ff_valid(110)\n\n when (w_vn_lvl_4_valid(0) === 1.B) {\n r_lvl_output_ff(143) := w_vn_lvl_4(0)\n r_lvl_output_ff_valid(143) := 1.B\n } .otherwise {\n r_lvl_output_ff(143) := r_lvl_output_ff(111)\n r_lvl_output_ff_valid(143) := r_lvl_output_ff_valid(111)\n }\n\n when (w_vn_lvl_4_valid(1) === 1.B) {\n r_lvl_output_ff(144) := w_vn_lvl_4(1)\n r_lvl_output_ff_valid(144) := 1.B\n } .otherwise {\n r_lvl_output_ff(144) := r_lvl_output_ff(112)\n r_lvl_output_ff_valid(144) := r_lvl_output_ff_valid(112)\n }\n\n r_lvl_output_ff(145) := r_lvl_output_ff(113)\n r_lvl_output_ff_valid(145) := r_lvl_output_ff_valid(113)\n\n r_lvl_output_ff(146) := r_lvl_output_ff(114)\n r_lvl_output_ff_valid(146) := r_lvl_output_ff_valid(114)\n\n r_lvl_output_ff(147) := r_lvl_output_ff(115)\n r_lvl_output_ff_valid(147) := r_lvl_output_ff_valid(115)\n\n r_lvl_output_ff(148) := r_lvl_output_ff(116)\n r_lvl_output_ff_valid(148) := r_lvl_output_ff_valid(116)\n\n r_lvl_output_ff(149) := r_lvl_output_ff(117)\n r_lvl_output_ff_valid(149) := r_lvl_output_ff_valid(117)\n\n r_lvl_output_ff(150) := r_lvl_output_ff(118)\n r_lvl_output_ff_valid(150) := r_lvl_output_ff_valid(118)\n\n r_lvl_output_ff(151) := r_lvl_output_ff(119)\n r_lvl_output_ff_valid(151) := r_lvl_output_ff_valid(119)\n\n r_lvl_output_ff(152) := r_lvl_output_ff(120)\n r_lvl_output_ff_valid(152) := r_lvl_output_ff_valid(120)\n\n r_lvl_output_ff(153) := r_lvl_output_ff(121)\n r_lvl_output_ff_valid(153) := r_lvl_output_ff_valid(121)\n\n r_lvl_output_ff(154) := r_lvl_output_ff(122)\n r_lvl_output_ff_valid(154) := r_lvl_output_ff_valid(122)\n\n r_lvl_output_ff(155) := r_lvl_output_ff(123)\n r_lvl_output_ff_valid(155) := r_lvl_output_ff_valid(123)\n \n r_lvl_output_ff(156) := r_lvl_output_ff(124)\n r_lvl_output_ff_valid(156) := r_lvl_output_ff_valid(124)\n\n r_lvl_output_ff(157) := r_lvl_output_ff(125)\n r_lvl_output_ff_valid(157) := r_lvl_output_ff_valid(125)\n\n r_lvl_output_ff(158) := r_lvl_output_ff(126)\n r_lvl_output_ff_valid(158) := r_lvl_output_ff_valid(126)\n\n r_lvl_output_ff(159) := r_lvl_output_ff(127)\n r_lvl_output_ff_valid(159) := r_lvl_output_ff_valid(127) \n\n when (io.i_valid === 1.U) {\n r_valid(0) := 1.U\n } .otherwise {\n r_valid(0) := 0.U\n }\n\n for (i <- 0 until 6) {\n\n\n r_valid(i + 1) := r_valid(i)\n }\n\n\n val my_adder_0 = Module(new EdgeAdderSwitch(32,2,2,2))\n\n my_adder_0.io.i_valid := r_valid(0)\n my_adder_0.io.i_data_bus := VecInit(Seq(io.i_data_bus(1), io.i_data_bus(0)))\n my_adder_0.io.i_add_en := io.i_add_en_bus(0)\n my_adder_0.io.i_cmd := io.i_cmd_bus(0)\n my_adder_0.io.i_sel := 0.U\n w_vn_lvl_0(0) := my_adder_0.io.o_vn(31,0)\n w_vn_lvl_0(1) := my_adder_0.io.o_vn(63,32) \n w_vn_lvl_0_valid(0) := my_adder_0.io.o_vn_valid(0)\n w_vn_lvl_0_valid(1) := my_adder_0.io.o_vn_valid(1)\n w_fan_lvl_0(0) := my_adder_0.io.o_adder\n\n val my_adder_1 = Module(new EdgeAdderSwitch(32,2,2,2))\n\n my_adder_1.io.i_valid := r_valid(1)\n my_adder_1.io.i_data_bus := VecInit(Seq(w_fan_lvl_0(1), w_fan_lvl_0(0)))\n my_adder_1.io.i_add_en := io.i_add_en_bus(16)\n my_adder_1.io.i_cmd := io.i_cmd_bus(16)\n my_adder_1.io.i_sel := 0.U\n w_vn_lvl_1(0) := my_adder_1.io.o_vn(31,0)\n w_vn_lvl_1(1) := my_adder_1.io.o_vn(63,32)\n w_vn_lvl_1_valid(0) := my_adder_1.io.o_vn_valid(0)\n w_vn_lvl_1_valid(1) := my_adder_1.io.o_vn_valid(1)\n w_fan_lvl_1(0) := my_adder_1.io.o_adder\n\n val my_adder_2 = Module(new AdderSwitch(32,2,2,2))\n\n my_adder_2.io.i_valid := r_valid(0)\n my_adder_2.io.i_data_bus := VecInit(Seq(io.i_data_bus(3), io.i_data_bus(2))) \n my_adder_2.io.i_add_en := io.i_add_en_bus(1)\n my_adder_2.io.i_cmd := io.i_cmd_bus(1)\n my_adder_2.io.i_sel := 0.U\n\n w_vn_lvl_0(2) := my_adder_2.io.o_vn(31,0)\n w_vn_lvl_0(3) := my_adder_2.io.o_vn(63,32)\n\n w_vn_lvl_0_valid(2) := my_adder_2.io.o_vn_valid(0)\n w_vn_lvl_0_valid(3) := my_adder_2.io.o_vn_valid(1)\n\n w_fan_lvl_0(1) := my_adder_2.io.o_adder(0)\n w_fan_lvl_0(2) := my_adder_2.io.o_adder(1)\n\n\n val my_adder_3 = Module(new EdgeAdderSwitch(32,4,2,2))\n\n my_adder_3.io.i_valid := r_valid(2)\n my_adder_3.io.i_data_bus := VecInit(Seq(w_fan_lvl_1(1), r_fan_ff_lvl_0_to_2(1), r_fan_ff_lvl_0_to_2(0), w_fan_lvl_1(0)))\n my_adder_3.io.i_add_en := io.i_add_en_bus(24)\n my_adder_3.io.i_cmd := io.i_cmd_bus(24)\n my_adder_3.io.i_sel := Cat(io.i_sel_bus(1),io.i_sel_bus(0))\n w_vn_lvl_2(0) := my_adder_3.io.o_vn(31,0)\n w_vn_lvl_2(1) := my_adder_3.io.o_vn(63,32)\n\n w_vn_lvl_2_valid(0) := my_adder_3.io.o_vn_valid(0)\n w_vn_lvl_2_valid(1) := my_adder_3.io.o_vn_valid(1)\n\n w_fan_lvl_2(0) := my_adder_3.io.o_adder\n\n val my_adder_4 = Module(new AdderSwitch(32,2,2,2))\n\n my_adder_4.io.i_valid := r_valid(0)\n my_adder_4.io.i_data_bus := VecInit(Seq(io.i_data_bus(5),io.i_data_bus(4)))\n my_adder_4.io.i_add_en := io.i_add_en_bus(2)\n my_adder_4.io.i_cmd := io.i_cmd_bus(2)\n my_adder_4.io.i_sel := 0.U\n w_vn_lvl_0(4) := my_adder_4.io.o_vn(31,0)\n w_vn_lvl_0(5) := my_adder_4.io.o_vn(63,32)\n\n w_vn_lvl_0_valid(4) := my_adder_4.io.o_vn_valid(0)\n w_vn_lvl_0_valid(5) := my_adder_4.io.o_vn_valid(1)\n\n w_fan_lvl_0(3) := my_adder_4.io.o_adder(0)\n w_fan_lvl_0(4) := my_adder_4.io.o_adder(1)\n\n\n val my_adder_5 = Module(new AdderSwitch(32,2,2,2))\n\n my_adder_5.io.i_valid := r_valid(1)\n my_adder_5.io.i_data_bus := VecInit(Seq(w_fan_lvl_0(5), w_fan_lvl_0(4)))\n my_adder_5.io.i_add_en := io.i_add_en_bus(17)\n my_adder_5.io.i_cmd := io.i_cmd_bus(17)\n my_adder_5.io.i_sel := 0.U\n w_vn_lvl_1(2) := my_adder_5.io.o_vn(31,0)\n w_vn_lvl_1(3) := my_adder_5.io.o_vn(63,32)\n\n w_vn_lvl_1_valid(2) := my_adder_5.io.o_vn_valid(0)\n w_vn_lvl_1_valid(3) := my_adder_5.io.o_vn_valid(1)\n\n w_fan_lvl_1(1) := my_adder_5.io.o_adder(0)\n w_fan_lvl_1(2) := my_adder_5.io.o_adder(1)\n\n val my_adder_6 = Module(new AdderSwitch(32,2,2,2))\n\n my_adder_6.io.i_valid := r_valid(0)\n my_adder_6.io.i_data_bus := VecInit(Seq(io.i_data_bus(7),io.i_data_bus(6)))\n my_adder_6.io.i_add_en := io.i_add_en_bus(3)\n my_adder_6.io.i_cmd := io.i_cmd_bus(3)\n my_adder_6.io.i_sel := 0.U\n w_vn_lvl_0(6) := my_adder_6.io.o_vn(31,0)\n w_vn_lvl_0(7) := my_adder_6.io.o_vn(63,32)\n\n w_vn_lvl_0_valid(6) := my_adder_6.io.o_vn_valid(0)\n w_vn_lvl_0_valid(7) := my_adder_6.io.o_vn_valid(1)\n\n w_fan_lvl_0(5) := my_adder_6.io.o_adder(0)\n w_fan_lvl_0(6) := my_adder_6.io.o_adder(1)\n\n val my_adder_7 = Module(new EdgeAdderSwitch(32,6,4,2))\n\n my_adder_7.io.i_valid := r_valid(3)\n \n my_adder_7.io.i_data_bus := VecInit(Seq( w_fan_lvl_2(1), r_fan_ff_lvl_1_to_3(1), r_fan_ff_lvl_0_to_3(1), r_fan_ff_lvl_0_to_3(0), r_fan_ff_lvl_1_to_3(0), w_fan_lvl_2(0)))\n my_adder_7.io.i_add_en := io.i_add_en_bus(28)\n my_adder_7.io.i_cmd := io.i_cmd_bus(28)\nmy_adder_7.io.i_sel := Cat(io.i_sel_bus(11),io.i_sel_bus(10),io.i_sel_bus(9),io.i_sel_bus(8))\n\n w_vn_lvl_3(0) := my_adder_7.io.o_vn(31,0)\n w_vn_lvl_3(1) := my_adder_7.io.o_vn(63,32)\n\n w_vn_lvl_3_valid(0) := my_adder_7.io.o_vn_valid (0)\n w_vn_lvl_3_valid(1) := my_adder_7.io.o_vn_valid (1)\n\n w_fan_lvl_3(0) := my_adder_7.io.o_adder\n\n val my_adder_8 = Module(new AdderSwitch(32,2,2,2))\n\n my_adder_8.io.i_valid := r_valid(0)\n my_adder_8.io.i_data_bus := VecInit(Seq(io.i_data_bus(9),io.i_data_bus(8)))\n my_adder_8.io.i_add_en := io.i_add_en_bus(4)\n my_adder_8.io.i_cmd := io.i_cmd_bus(4)\n my_adder_8.io.i_sel := 0.U\n w_vn_lvl_0(8) := my_adder_8.io.o_vn(31,0)\n w_vn_lvl_0(9) := my_adder_8.io.o_vn(63,32)\n\n w_vn_lvl_0_valid(8) := my_adder_8.io.o_vn_valid(1)\n w_vn_lvl_0_valid(9) := my_adder_8.io.o_vn_valid(0)\n\n w_fan_lvl_0(7) := my_adder_8.io.o_adder(0)\n w_fan_lvl_0(8) := my_adder_8.io.o_adder(1)\n\n val my_adder_9 = Module(new AdderSwitch(32,2,2,2))\n\n my_adder_9.io.i_valid := r_valid(1)\n my_adder_9.io.i_data_bus := VecInit(Seq(w_fan_lvl_0(9), w_fan_lvl_0(8)))\n my_adder_9.io.i_add_en := io.i_add_en_bus(18)\n my_adder_9.io.i_cmd := io.i_cmd_bus(18)\n my_adder_9.io.i_sel := 0.U\n w_vn_lvl_1(4) := my_adder_9.io.o_vn(31,0)\n w_vn_lvl_1(5) := my_adder_9.io.o_vn(63,32)\n\n w_vn_lvl_1_valid(4) := my_adder_9.io.o_vn_valid(0)\n w_vn_lvl_1_valid(5) := my_adder_9.io.o_vn_valid(1)\n\n w_fan_lvl_1(3) := my_adder_9.io.o_adder(0)\n w_fan_lvl_1(4) := my_adder_9.io.o_adder(1)\n\n val my_adder_10 = Module(new AdderSwitch(32,2,2,2))\n\n my_adder_10.io.i_valid := r_valid(0)\n my_adder_10.io.i_data_bus := VecInit(Seq(io.i_data_bus(11),io.i_data_bus(10)))\n my_adder_10.io.i_add_en := io.i_add_en_bus(5)\n my_adder_10.io.i_cmd := io.i_cmd_bus(5)\n my_adder_10.io.i_sel := 0.U\n w_vn_lvl_0(10) := my_adder_10.io.o_vn(31,0)\n w_vn_lvl_0(11) := my_adder_10.io.o_vn(63,32)\n\n w_vn_lvl_0_valid(10) := my_adder_10.io.o_vn_valid(0)\n w_vn_lvl_0_valid(11) := my_adder_10.io.o_vn_valid(1)\n\n w_fan_lvl_0(9) := my_adder_10.io.o_adder(0)\n w_fan_lvl_0(10) := my_adder_10.io.o_adder(1)\n\n\n val my_adder_11 = Module(new AdderSwitch(32,4,2,2))\n\n my_adder_11.io.i_valid := r_valid(2)\n my_adder_11.io.i_data_bus := VecInit(Seq(w_fan_lvl_1(5), r_fan_ff_lvl_0_to_2(5), r_fan_ff_lvl_0_to_2(4), w_fan_lvl_1(4)))\n\n my_adder_11.io.i_add_en := io.i_add_en_bus(25)\n my_adder_11.io.i_cmd := io.i_cmd_bus(25)\n my_adder_11.io.i_sel := Cat(io.i_sel_bus(3),io.i_sel_bus(2))\n\n w_vn_lvl_2(2) := my_adder_11.io.o_vn(31,0)\n w_vn_lvl_2(3) := my_adder_11.io.o_vn(63,32)\n\n w_vn_lvl_2_valid(2) := my_adder_11.io.o_vn_valid(0)\n w_vn_lvl_2_valid(3) := my_adder_11.io.o_vn_valid(1)\n\n w_fan_lvl_2(1) := my_adder_11.io.o_adder(0)\n w_fan_lvl_2(2) := my_adder_11.io.o_adder(1)\n\n\n val my_adder_12 = Module(new AdderSwitch(32,2,2,2))\n\n my_adder_12.io.i_valid := r_valid(0)\n my_adder_12.io.i_data_bus := VecInit(Seq(io.i_data_bus(13),io.i_data_bus(12)))\n my_adder_12.io.i_add_en := io.i_add_en_bus(6)\n my_adder_12.io.i_cmd := io.i_cmd_bus(6)\n my_adder_12.io.i_sel := 0.U\n w_vn_lvl_0(12) := my_adder_12.io.o_vn(31,0)\n w_vn_lvl_0(13) := my_adder_12.io.o_vn(63,32)\n\n w_vn_lvl_0_valid(12) := my_adder_12.io.o_vn_valid(0)\n w_vn_lvl_0_valid(13) := my_adder_12.io.o_vn_valid(1)\n\n w_fan_lvl_0(11) := my_adder_12.io.o_adder(0)\n w_fan_lvl_0(12) := my_adder_12.io.o_adder(1)\n\n\n val my_adder_13 = Module(new AdderSwitch(32,2,2,2))\n\n my_adder_13.io.i_valid := r_valid(1)\n my_adder_13.io.i_data_bus := VecInit(Seq(w_fan_lvl_0(12), w_fan_lvl_0(11)))\n my_adder_13.io.i_add_en := io.i_add_en_bus(19)\n my_adder_13.io.i_cmd := io.i_cmd_bus(19)\n my_adder_13.io.i_sel := 0.U\n w_vn_lvl_1(6) := my_adder_13.io.o_vn(31,0)\n w_vn_lvl_1(7) := my_adder_13.io.o_vn(63,32)\n\n w_vn_lvl_1_valid(6) := my_adder_13.io.o_vn_valid(0)\n w_vn_lvl_1_valid(7) := my_adder_13.io.o_vn_valid(1)\n\n w_fan_lvl_1(5) := my_adder_13.io.o_adder(0)\n w_fan_lvl_1(6) := my_adder_13.io.o_adder(1)\n\n\n val my_adder_14 = Module(new AdderSwitch(32,2,2,2))\n\n my_adder_14.io.i_valid := r_valid(0)\n my_adder_14.io.i_data_bus := VecInit(Seq(io.i_data_bus(15),io.i_data_bus(14)))\n my_adder_14.io.i_add_en := io.i_add_en_bus(7)\n my_adder_14.io.i_cmd := io.i_cmd_bus(7)\n my_adder_14.io.i_sel := 0.U\n w_vn_lvl_0(14) := my_adder_14.io.o_vn(31,0)\n w_vn_lvl_0(15) := my_adder_14.io.o_vn(63,32)\n\n w_vn_lvl_0_valid(14) := my_adder_14.io.o_vn_valid(0)\n w_vn_lvl_0_valid(15) := my_adder_14.io.o_vn_valid(1)\n\n w_fan_lvl_0(13) := my_adder_14.io.o_adder(0) \n w_fan_lvl_0(14) := my_adder_14.io.o_adder(1) \n\n\n val my_adder_15 = Module(new EdgeAdderSwitch(32,8,4,2))\n\n my_adder_15.io.i_valid := r_valid(4)\n my_adder_15.io.i_data_bus := VecInit(Seq(w_fan_lvl_3(1), r_fan_ff_lvl_2_to_4(1), r_fan_ff_lvl_1_to_4(1), r_fan_ff_lvl_0_to_4(1), r_fan_ff_lvl_0_to_4(0), r_fan_ff_lvl_1_to_4(0), r_fan_ff_lvl_2_to_4(0), w_fan_lvl_3(0)))\n \n my_adder_15.io.i_add_en := io.i_add_en_bus(30)\n my_adder_15.io.i_cmd := io.i_cmd_bus(30)\n my_adder_15.io.i_sel := Cat(io.i_sel_bus(19),io.i_sel_bus(18),io.i_sel_bus(17),io.i_sel_bus(16))\n w_vn_lvl_4(0) := my_adder_15.io.o_vn(31,0)\n w_vn_lvl_4(1) := my_adder_15.io.o_vn(63,32)\n\n w_vn_lvl_4_valid(0) := my_adder_15.io.o_vn_valid(0)\n w_vn_lvl_4_valid(1) := my_adder_15.io.o_vn_valid(1)\n\n w_fan_lvl_4(0) := my_adder_15.io.o_adder \n\n\n val my_adder_16 = Module(new AdderSwitch(32,2,2,2))\n\n my_adder_16.io.i_valid := r_valid(0)\n my_adder_16.io.i_data_bus := VecInit(Seq(io.i_data_bus(17),io.i_data_bus(16)))\n my_adder_16.io.i_add_en := io.i_add_en_bus(8)\n my_adder_16.io.i_cmd := io.i_cmd_bus(8)\n my_adder_16.io.i_sel := 0.U\n w_vn_lvl_0(16) := my_adder_16.io.o_vn(31,0)\n w_vn_lvl_0(17) := my_adder_16.io.o_vn(63,32)\n\n w_vn_lvl_0_valid(16) := my_adder_16.io.o_vn_valid(0)\n w_vn_lvl_0_valid(17) := my_adder_16.io.o_vn_valid(1)\n\n w_fan_lvl_0(15) := my_adder_16.io.o_adder(0) \n w_fan_lvl_0(16) := my_adder_16.io.o_adder(1) \n\n\n val my_adder_17 = Module(new AdderSwitch(32,2,2,2))\n\n my_adder_17.io.i_valid := r_valid(1)\n my_adder_17.io.i_data_bus := VecInit(Seq(w_fan_lvl_0(16), w_fan_lvl_0(15)))\n my_adder_17.io.i_add_en := io.i_add_en_bus(20)\n my_adder_17.io.i_cmd := io.i_cmd_bus(20)\n my_adder_17.io.i_sel := 0.U\n w_vn_lvl_1(8) := my_adder_17.io.o_vn(31,0)\n w_vn_lvl_1(9) := my_adder_17.io.o_vn(63,32)\n\n w_vn_lvl_1_valid(8) := my_adder_17.io.o_vn_valid(0)\n w_vn_lvl_1_valid(9) := my_adder_17.io.o_vn_valid(1)\n\n w_fan_lvl_1(7) := my_adder_17.io.o_adder(0) \n w_fan_lvl_1(8) := my_adder_17.io.o_adder(1) \n\n\n val my_adder_18 = Module(new AdderSwitch(32,2,2,2))\n\n my_adder_18.io.i_valid := r_valid(0)\n my_adder_18.io.i_data_bus := VecInit(Seq(io.i_data_bus(19),io.i_data_bus(18)))\n my_adder_18.io.i_add_en := io.i_add_en_bus(9)\n my_adder_18.io.i_cmd := io.i_cmd_bus(9)\n my_adder_18.io.i_sel := 0.U\n w_vn_lvl_0(18) := my_adder_18.io.o_vn(31,0)\n w_vn_lvl_0(19) := my_adder_18.io.o_vn(63,32)\n\n w_vn_lvl_0_valid(18) := my_adder_18.io.o_vn_valid(0)\n w_vn_lvl_0_valid(19) := my_adder_18.io.o_vn_valid(1)\n\n w_fan_lvl_0(17) := my_adder_18.io.o_adder(0) \n w_fan_lvl_0(18) := my_adder_18.io.o_adder(1) \n\n\n val my_adder_19 = Module(new AdderSwitch(32,4,2,2))\n\n my_adder_19.io.i_valid := r_valid(2)\n my_adder_19.io.i_data_bus := VecInit(Seq(w_fan_lvl_1(9), r_fan_ff_lvl_0_to_2(9), r_fan_ff_lvl_0_to_2(8), w_fan_lvl_1(8)))\n my_adder_19.io.i_add_en := io.i_add_en_bus(26)\n my_adder_19.io.i_cmd := io.i_cmd_bus(26)\n my_adder_19.io.i_sel := Cat(io.i_sel_bus(5),io.i_sel_bus(4))\n w_vn_lvl_2(4) := my_adder_19.io.o_vn(31,0)\n w_vn_lvl_2(5) := my_adder_19.io.o_vn(63,32)\n\n w_vn_lvl_2_valid(4) := my_adder_19.io.o_vn_valid(0)\n w_vn_lvl_2_valid(5) := my_adder_19.io.o_vn_valid(1)\n\n w_fan_lvl_2(3) := my_adder_19.io.o_adder(0)\n w_fan_lvl_2(4) := my_adder_19.io.o_adder(1) \n\n\n\n val my_adder_20 = Module(new AdderSwitch(32,2,2,2))\n\n my_adder_20.io.i_valid := r_valid(0)\n my_adder_20.io.i_data_bus := VecInit(Seq(io.i_data_bus(21),io.i_data_bus(20)))\n my_adder_20.io.i_add_en := io.i_add_en_bus(10)\n my_adder_20.io.i_cmd := io.i_cmd_bus(10)\n my_adder_20.io.i_sel := 0.U\n w_vn_lvl_0(20) := my_adder_20.io.o_vn(31,0)\n w_vn_lvl_0(21) := my_adder_20.io.o_vn(63,32)\n\n w_vn_lvl_0_valid(20) := my_adder_20.io.o_vn_valid(0)\n w_vn_lvl_0_valid(21) := my_adder_20.io.o_vn_valid(1)\n\n w_fan_lvl_0(19) := my_adder_20.io.o_adder(0)\n w_fan_lvl_0(20) := my_adder_20.io.o_adder(1)\n\n\n\n\n val my_adder_21 = Module(new AdderSwitch(32,2,2,2))\n\n my_adder_21.io.i_valid := r_valid(1)\n my_adder_21.io.i_data_bus := VecInit(Seq(w_fan_lvl_0(20), w_fan_lvl_0(19)))\n my_adder_21.io.i_add_en := io.i_add_en_bus(21)\n my_adder_21.io.i_cmd := io.i_cmd_bus(21)\n my_adder_21.io.i_sel := 0.U\n \n w_vn_lvl_1(10) := my_adder_21.io.o_vn(31,0)\n w_vn_lvl_1(11) := my_adder_21.io.o_vn(63,32)\n\n w_vn_lvl_1_valid(10) := my_adder_21.io.o_vn_valid(0)\n w_vn_lvl_1_valid(11) := my_adder_21.io.o_vn_valid(1)\n\n w_fan_lvl_1(9) := my_adder_21.io.o_adder(0) \n w_fan_lvl_1(10) := my_adder_21.io.o_adder(1) \n\n\n val my_adder_22 = Module(new AdderSwitch(32,2,2,2))\n\n my_adder_22.io.i_valid := r_valid(0)\n my_adder_22.io.i_data_bus := VecInit(Seq(io.i_data_bus(23),io.i_data_bus(22)))\n my_adder_22.io.i_add_en := io.i_add_en_bus(11)\n my_adder_22.io.i_cmd := io.i_cmd_bus(11)\n my_adder_22.io.i_sel := 0.U\n w_vn_lvl_0(22) := my_adder_22.io.o_vn(31,0)\n w_vn_lvl_0(23) := my_adder_22.io.o_vn(63,32)\n\n w_vn_lvl_0_valid(22) := my_adder_22.io.o_vn_valid(0)\n w_vn_lvl_0_valid(23) := my_adder_22.io.o_vn_valid(1)\n\n w_fan_lvl_0(21) := my_adder_22.io.o_adder(0)\n w_fan_lvl_0(22) := my_adder_22.io.o_adder(1)\n\n\n val my_adder_23 = Module(new EdgeAdderSwitch(32,6,4,2))\n\n my_adder_23.io.i_valid := r_valid(3)\n my_adder_23.io.i_data_bus := VecInit(Seq(w_fan_lvl_2(5), r_fan_ff_lvl_1_to_3(5), r_fan_ff_lvl_0_to_3(5), r_fan_ff_lvl_0_to_3(4), r_fan_ff_lvl_1_to_3(4), w_fan_lvl_2(4)))\n my_adder_23.io.i_add_en := io.i_add_en_bus(29)\n my_adder_23.io.i_cmd := io.i_cmd_bus(29)\n my_adder_23.io.i_sel := Cat(io.i_sel_bus(15),io.i_sel_bus(14),io.i_sel_bus(13),io.i_sel_bus(12))\n w_vn_lvl_3(2) := my_adder_23.io.o_vn(31,0)\n w_vn_lvl_3(3) := my_adder_23.io.o_vn(63,32)\n\n w_vn_lvl_3_valid(2) := my_adder_23.io.o_vn_valid(0)\n w_vn_lvl_3_valid(3) := my_adder_23.io.o_vn_valid(1)\n\n w_fan_lvl_3(1) := my_adder_23.io.o_adder \n\n val my_adder_24 = Module(new AdderSwitch(32,2,2,2))\n\n my_adder_24.io.i_valid := r_valid(0)\n my_adder_24.io.i_data_bus := VecInit(Seq(io.i_data_bus(25),io.i_data_bus(24)))\n my_adder_24.io.i_add_en := io.i_add_en_bus(12)\n my_adder_24.io.i_cmd := io.i_cmd_bus(12)\n my_adder_24.io.i_sel := 0.U\n w_vn_lvl_0(24) := my_adder_24.io.o_vn(31,0)\n w_vn_lvl_0(25) := my_adder_24.io.o_vn(63,32)\n\n w_vn_lvl_0_valid(24) := my_adder_24.io.o_vn_valid(0)\n w_vn_lvl_0_valid(25) := my_adder_24.io.o_vn_valid(1)\n\n w_fan_lvl_0(23) := my_adder_24.io.o_adder(0)\n w_fan_lvl_0(24) := my_adder_24.io.o_adder(1)\n\n\n\n val my_adder_25 = Module(new AdderSwitch(32,2,2,2))\n\n my_adder_25.io.i_valid := r_valid(1)\n my_adder_25.io.i_data_bus := VecInit(Seq(w_fan_lvl_0(24), w_fan_lvl_0(23)))\n my_adder_25.io.i_add_en := io.i_add_en_bus(22)\n my_adder_25.io.i_cmd := io.i_cmd_bus(22)\n my_adder_25.io.i_sel := 0.U\n w_vn_lvl_1(12) := my_adder_25.io.o_vn(32,0)\n w_vn_lvl_1(13) := my_adder_25.io.o_vn(63,32)\n\n w_vn_lvl_1_valid(12) := my_adder_25.io.o_vn_valid(0)\n w_vn_lvl_1_valid(13) := my_adder_25.io.o_vn_valid(1)\n\n w_fan_lvl_1(11) := my_adder_25.io.o_adder(0)\n w_fan_lvl_1(12) := my_adder_25.io.o_adder(1)\n\n\n\n\n val my_adder_26 = Module(new AdderSwitch(32,2,2,2))\n\n my_adder_26.io.i_valid := r_valid(0)\n my_adder_26.io.i_data_bus := VecInit(Seq(io.i_data_bus(27),io.i_data_bus(26)))\n my_adder_26.io.i_add_en := io.i_add_en_bus(13)\n my_adder_26.io.i_cmd := io.i_cmd_bus(13)\n my_adder_26.io.i_sel := 0.U\n w_vn_lvl_0(26) := my_adder_26.io.o_vn(31,0)\n w_vn_lvl_0(27) := my_adder_26.io.o_vn(63,32)\n\n w_vn_lvl_0_valid(26) := my_adder_26.io.o_vn_valid(0)\n w_vn_lvl_0_valid(27) := my_adder_26.io.o_vn_valid(1)\n\n w_fan_lvl_0(25) := my_adder_26.io.o_adder(0)\n w_fan_lvl_0(26) := my_adder_26.io.o_adder(1) \n\n\n val my_adder_27 = Module(new EdgeAdderSwitch(32,4,2,2))\n\n my_adder_27.io.i_valid := r_valid(2)\n my_adder_27.io.i_data_bus := VecInit(Seq(w_fan_lvl_1(13), r_fan_ff_lvl_0_to_2(13), r_fan_ff_lvl_0_to_2(12), w_fan_lvl_1(12)))\n my_adder_27.io.i_add_en := io.i_add_en_bus(27)\n my_adder_27.io.i_cmd := io.i_cmd_bus(27)\n my_adder_27.io.i_sel := Cat(io.i_sel_bus(7),io.i_sel_bus(6))\n w_vn_lvl_2(6) := my_adder_27.io.o_vn(31,0)\n w_vn_lvl_2(7) := my_adder_27.io.o_vn(63,32)\n\n w_vn_lvl_2_valid(6) := my_adder_27.io.o_vn_valid(0)\n w_vn_lvl_2_valid(7) := my_adder_27.io.o_vn_valid(1)\n\n w_fan_lvl_2(5) := my_adder_27.io.o_adder\n \n\n\n\n\n val my_adder_28 = Module(new AdderSwitch(32,2,2,2))\n\n my_adder_28.io.i_valid := r_valid(0)\n my_adder_28.io.i_data_bus := VecInit(Seq(io.i_data_bus(29),io.i_data_bus(28)))\n my_adder_28.io.i_add_en := io.i_add_en_bus(14)\n my_adder_28.io.i_cmd := io.i_cmd_bus(14)\n my_adder_28.io.i_sel := 0.U\n w_vn_lvl_0(28) := my_adder_28.io.o_vn(31,0)\n w_vn_lvl_0(29) := my_adder_28.io.o_vn(63,32)\n\n w_vn_lvl_0_valid(28) := my_adder_28.io.o_vn_valid(0)\n w_vn_lvl_0_valid(29) := my_adder_28.io.o_vn_valid(1)\n\n w_fan_lvl_0(27) := my_adder_28.io.o_adder(0) \n w_fan_lvl_0(28) := my_adder_28.io.o_adder(1)\n\n\n\n val my_adder_29 = Module(new EdgeAdderSwitch(32, 2,2,2))\n\n my_adder_29.io.i_valid := r_valid(1)\n my_adder_29.io.i_data_bus := VecInit(Seq(w_fan_lvl_0(28), w_fan_lvl_0(27)))\n my_adder_29.io.i_add_en := io.i_add_en_bus(23)\n my_adder_29.io.i_cmd := io.i_cmd_bus(23)\n my_adder_29.io.i_sel := 0.U\n w_vn_lvl_1(14) := my_adder_29.io.o_vn(31,0)\n w_vn_lvl_1(15) := my_adder_29.io.o_vn(63,32)\n\n w_vn_lvl_1_valid(14) := my_adder_29.io.o_vn_valid(0)\n w_vn_lvl_1_valid(15) := my_adder_29.io.o_vn_valid(1)\n\n w_fan_lvl_1(13) := my_adder_29.io.o_adder\n\n\n\n val my_adder_30 = Module(new EdgeAdderSwitch(32,2,2,2))\n\n my_adder_30.io.i_valid := r_valid(0)\n my_adder_30.io.i_data_bus := VecInit(Seq(io.i_data_bus(31),io.i_data_bus(30)))\n my_adder_30.io.i_add_en := io.i_add_en_bus(15)\n my_adder_30.io.i_cmd := io.i_cmd_bus(15)\n my_adder_30.io.i_sel := 0.U\n w_vn_lvl_0(30) := my_adder_30.io.o_vn(31,0)\n w_vn_lvl_0(31) := my_adder_30.io.o_vn(63,32)\n \n w_vn_lvl_0_valid(30) := my_adder_30.io.o_vn_valid(0)\n w_vn_lvl_0_valid(31) := my_adder_30.io.o_vn_valid(1)\n\n w_fan_lvl_0(29) := my_adder_30.io.o_adder \n\n\n r_final_add := 0.U\n r_final_add2 := 0.U\n r_final_sum := 0.U\n\n r_final_add := io.i_add_en_bus(30)\n r_final_add2 := r_final_add\n r_final_sum := w_fan_lvl_4(0)\n\n\n\n\n\n\n io.o_data_bus(0) := 0.U\n io.o_data_bus(1) := 0.U\n io.o_data_bus(2) := 0.U\n io.o_data_bus(3) := 0.U\n io.o_data_bus(4) := 0.U\n io.o_data_bus(5) := 0.U\n io.o_data_bus(6) := 0.U\n io.o_data_bus(7) := 0.U\n\n io.o_data_bus(8) := 0.U\n io.o_data_bus(9) := 0.U\n io.o_data_bus(10) := 0.U\n io.o_data_bus(11) := 0.U\n io.o_data_bus(12) := 0.U\n io.o_data_bus(13) := 0.U\n io.o_data_bus(14) := 0.U\n io.o_data_bus(15) := 0.U\n\n io.o_data_bus(16) := 0.U\n io.o_data_bus(17) := 0.U\n io.o_data_bus(18) := 0.U\n io.o_data_bus(19) := 0.U\n io.o_data_bus(20) := 0.U\n io.o_data_bus(21) := 0.U\n io.o_data_bus(22) := 0.U\n io.o_data_bus(23) := 0.U\n\n io.o_data_bus(24) := 0.U\n io.o_data_bus(25) := 0.U\n io.o_data_bus(26) := 0.U\n io.o_data_bus(27) := 0.U\n io.o_data_bus(28) := 0.U\n io.o_data_bus(29) := 0.U\n io.o_data_bus(30) := 0.U\n io.o_data_bus(31) := 0.U\n\n \n io.o_data_bus(0) := r_lvl_output_ff(128)\n io.o_data_bus(1) := r_lvl_output_ff(129)\n io.o_data_bus(2) := r_lvl_output_ff(130)\n io.o_data_bus(3) := r_lvl_output_ff(131)\n io.o_data_bus(4) := r_lvl_output_ff(132)\n io.o_data_bus(5) := r_lvl_output_ff(133)\n io.o_data_bus(6) := r_lvl_output_ff(134)\n io.o_data_bus(7) := r_lvl_output_ff(135)\n io.o_data_bus(8) := r_lvl_output_ff(136)\n io.o_data_bus(9) := r_lvl_output_ff(137)\n io.o_data_bus(10) := r_lvl_output_ff(138)\n io.o_data_bus(11) := r_lvl_output_ff(139)\n io.o_data_bus(12) := r_lvl_output_ff(140)\n io.o_data_bus(13) := r_lvl_output_ff(141)\n io.o_data_bus(14) := r_lvl_output_ff(142)\n\n when (r_final_add2 === 1.U) {\n io.o_data_bus(15) := r_final_sum\n } .otherwise {\n io.o_data_bus(15) := r_lvl_output_ff(143)\n }\n io.o_data_bus(16) := r_lvl_output_ff(144)\n io.o_data_bus(17) := r_lvl_output_ff(145)\n io.o_data_bus(18) := r_lvl_output_ff(146)\n io.o_data_bus(19) := r_lvl_output_ff(147)\n io.o_data_bus(20) := r_lvl_output_ff(148)\n io.o_data_bus(21) := r_lvl_output_ff(149)\n io.o_data_bus(22) := r_lvl_output_ff(150)\n io.o_data_bus(23) := r_lvl_output_ff(151)\n io.o_data_bus(24) := r_lvl_output_ff(152)\n io.o_data_bus(25) := r_lvl_output_ff(153)\n io.o_data_bus(26) := r_lvl_output_ff(154)\n io.o_data_bus(27) := r_lvl_output_ff(155)\n io.o_data_bus(28) := r_lvl_output_ff(156)\n io.o_data_bus(29) := r_lvl_output_ff(157)\n io.o_data_bus(30) := r_lvl_output_ff(158)\n io.o_data_bus(31) := r_lvl_output_ff(159)\n \n\n\n\n\n\n\n io.o_valid(0) := 0.U\n io.o_valid(1) := 0.U\n io.o_valid(2) := 0.U\n io.o_valid(3) := 0.U\n io.o_valid(4) := 0.U\n io.o_valid(5) := 0.U\n io.o_valid(6) := 0.U\n io.o_valid(7) := 0.U\n\n io.o_valid(8) := 0.U\n io.o_valid(9) := 0.U\n io.o_valid(10) := 0.U\n io.o_valid(11) := 0.U\n io.o_valid(12) := 0.U\n io.o_valid(13) := 0.U\n io.o_valid(14) := 0.U\n io.o_valid(15) := 0.U\n\n io.o_valid(16) := 0.U\n io.o_valid(17) := 0.U\n io.o_valid(18) := 0.U\n io.o_valid(19) := 0.U\n io.o_valid(20) := 0.U\n io.o_valid(21) := 0.U\n io.o_valid(22) := 0.U\n io.o_valid(23) := 0.U\n\n io.o_valid(24) := 0.U\n io.o_valid(25) := 0.U\n io.o_valid(26) := 0.U\n io.o_valid(27) := 0.U\n io.o_valid(28) := 0.U\n io.o_valid(29) := 0.U\n io.o_valid(30) := 0.U\n io.o_valid(31) := 0.U\n\n \n io.o_valid(0) := r_lvl_output_ff_valid(128)\n io.o_valid(1) := r_lvl_output_ff_valid(129)\n io.o_valid(2) := r_lvl_output_ff_valid(130)\n io.o_valid(3) := r_lvl_output_ff_valid(131)\n io.o_valid(4) := r_lvl_output_ff_valid(132)\n io.o_valid(5) := r_lvl_output_ff_valid(133)\n io.o_valid(6) := r_lvl_output_ff_valid(134)\n io.o_valid(7) := r_lvl_output_ff_valid(135)\n io.o_valid(8) := r_lvl_output_ff_valid(136)\n io.o_valid(9) := r_lvl_output_ff_valid(137)\n io.o_valid(10) := r_lvl_output_ff_valid(138)\n io.o_valid(11) := r_lvl_output_ff_valid(139)\n io.o_valid(12) := r_lvl_output_ff_valid(140)\n io.o_valid(13) := r_lvl_output_ff_valid(141)\n io.o_valid(14) := r_lvl_output_ff_valid(142)\n when (r_final_add2 === 1.U) {\n io.o_valid(15) := 1.U\n } .otherwise {\n io.o_valid(15) := r_lvl_output_ff_valid(143)\n }\n io.o_valid(16) := r_lvl_output_ff_valid(144)\n io.o_valid(17) := r_lvl_output_ff_valid(145)\n io.o_valid(18) := r_lvl_output_ff_valid(146)\n io.o_valid(19) := r_lvl_output_ff_valid(147)\n io.o_valid(20) := r_lvl_output_ff_valid(148)\n io.o_valid(21) := r_lvl_output_ff_valid(149)\n io.o_valid(22) := r_lvl_output_ff_valid(150)\n io.o_valid(23) := r_lvl_output_ff_valid(151)\n io.o_valid(24) := r_lvl_output_ff_valid(152)\n io.o_valid(25) := r_lvl_output_ff_valid(153)\n io.o_valid(26) := r_lvl_output_ff_valid(154)\n io.o_valid(27) := r_lvl_output_ff_valid(155)\n io.o_valid(28) := r_lvl_output_ff_valid(156)\n io.o_valid(29) := r_lvl_output_ff_valid(157)\n io.o_valid(30) := r_lvl_output_ff_valid(158)\n io.o_valid(31) := r_lvl_output_ff_valid(159)\n\n io.o_adder(0) := 0.U\n io.o_adder(1) := 0.U\n io.o_adder(2) := 0.U\n io.o_adder(3) := 0.U\n io.o_adder(4) := 0.U\n io.o_adder(5) := 0.U\n io.o_adder(6) := 0.U\n io.o_adder(7) := 0.U\n io.o_adder(8) := 0.U\n io.o_adder(9) := 0.U\n io.o_adder(10) := 0.U\n io.o_adder(11) := 0.U\n io.o_adder(12) := 0.U\n io.o_adder(13) := 0.U\n io.o_adder(14) := 0.U\n io.o_adder(15) := 0.U\n io.o_adder(16) := 0.U\n io.o_adder(17) := 0.U\n io.o_adder(18) := 0.U\n io.o_adder(19) := 0.U\n io.o_adder(20) := 0.U\n io.o_adder(21) := 0.U\n io.o_adder(22) := 0.U\n io.o_adder(23) := 0.U\n io.o_adder(24) := 0.U\n io.o_adder(25) := 0.U\n io.o_adder(26) := 0.U\n io.o_adder(27) := 0.U\n io.o_adder(28) := 0.U\n io.o_adder(29) := 0.U\n io.o_adder(30) := 0.U\n io.o_adder(31) := 0.U\n\n\n io.o_adder(0) := w_fan_lvl_0(0)\n io.o_adder(1) := w_fan_lvl_1(0)\n io.o_adder(2) := w_fan_lvl_0(1)\n io.o_adder(3) := w_fan_lvl_2(0)\n io.o_adder(4) := w_fan_lvl_0(3)\n io.o_adder(5) := w_fan_lvl_1(1)\n io.o_adder(6) := w_fan_lvl_0(5)\n io.o_adder(7) := w_fan_lvl_3(0)\n io.o_adder(8) := w_fan_lvl_0(7)\n io.o_adder(9) := w_fan_lvl_1(3)\n io.o_adder(10) := w_fan_lvl_0(9) \n io.o_adder(11) := w_fan_lvl_2(1)\n io.o_adder(12) := w_fan_lvl_0(11)\n io.o_adder(13) := w_fan_lvl_1(5)\n io.o_adder(14) := w_fan_lvl_0(13)\n io.o_adder(15) := w_fan_lvl_4(0)\n io.o_adder(16) := w_fan_lvl_0(15)\n io.o_adder(17) := w_fan_lvl_1(7)\n io.o_adder(18) := w_fan_lvl_0(17)\n io.o_adder(19) := w_fan_lvl_0(17)\n io.o_adder(20) := w_fan_lvl_0(19)\n io.o_adder(21) := w_fan_lvl_1(9)\n io.o_adder(22) := w_fan_lvl_0(21)\n io.o_adder(23) := w_fan_lvl_3(1) \n io.o_adder(24) := w_fan_lvl_0(23)\n io.o_adder(25) := w_fan_lvl_1(11)\n io.o_adder(26) := w_fan_lvl_0(25)\n io.o_adder(27) := w_fan_lvl_2(5)\n io.o_adder(28) := w_fan_lvl_0(27)\n io.o_adder(29) := w_fan_lvl_1(13) \n io.o_adder(30) := w_fan_lvl_0(29)\n\n}\n", "groundtruth": " }.otherwise {\n r_lvl_output_ff(67) := r_lvl_output_ff(35)\n r_lvl_output_ff_valid(67) := r_lvl_output_ff_valid(35)\n }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.8, "category_reason": ".otherwise clause"} {"task_id": "magma-si", "path": "magma-si/src/main/scala/components/FlexDPE.scala", "left_context": "package magmasi.components\n\nimport chisel3._\nimport chisel3.util._\n\nclass flexdpecom2(IN_DATA_TYPE : Int = 32 ,DATA_TYPE: Int = 32, NUM_PES: Int = 32, LOG2_PES: Int = 5) extends Module {\n implicit val config = MagmasiConfig()\n val io = IO(new Bundle {\n val i_vn = Input(Vec(NUM_PES, UInt(LOG2_PES.W)))\n val i_stationary = Input(Bool())\n val i_data_valid = Input(Bool())\n", "right_context": " val i_mux_bus = Input(Vec(2 * (LEVELS - 2) * NUM_PES + NUM_PES, Bool()))\n })\n val LEVELS : Int = (2 * (math.log(NUM_PES) / math.log(2))).toInt + 1\n\n val r_mult = RegInit(VecInit(Seq.fill(NUM_PES)(0.U((DATA_TYPE-1).W))))\n\n val r_stationary_ff = Reg(Bool())\n val r_stationary_ff2 = Reg(Bool())\n\n val r_data_valid_ff = Reg(Bool())\n val r_data_valid_ff2 = Reg(Bool())\n \n r_stationary_ff := io.i_stationary\n r_stationary_ff2 := r_stationary_ff\n\n r_data_valid_ff := io.i_data_valid\n r_data_valid_ff2 := r_data_valid_ff\n \n\n \n val my_controller = Module(new fancontrol(32,32,5))\n\n my_controller.io.i_vn := io.i_vn\n my_controller.io.i_stationary := 0.B\n my_controller.io.i_data_valid := io.i_data_valid\n val w_reduction_add = my_controller.io.o_reduction_add\n val w_reduction_cmd = my_controller.io.o_reduction_cmd\n val w_reduction_sel = my_controller.io.o_reduction_sel\n val w_reduction_valid = my_controller.io.o_reduction_valid\n\n val my_Benes = Module(new Benes())\n\n my_Benes.io.i_data_bus1 := io.i_data_bus\n my_Benes.io.i_data_bus2 := io.i_data_bus2\n my_Benes.io.i_mux_bus := io.i_mux_bus\n \n val w_dist_bus1 = my_Benes.io.o_dist_bus1\n val w_dist_bus2 = my_Benes.io.o_dist_bus2\n\n\n\n val buffer_mult = Module(new buffer_multiplication())\n\n \n buffer_mult.io.buffer1 := w_dist_bus1\n buffer_mult.io.buffer2 := w_dist_bus2 \n \n r_mult := buffer_mult.io.out\n\n\n\n\n\n val my_fan_network = Module(new FanNetworkcom(32,32))\n\n my_fan_network.io.i_valid := w_reduction_valid\n my_fan_network.io.i_data_bus := r_mult \n my_fan_network.io.i_add_en_bus := w_reduction_add\n my_fan_network.io.i_cmd_bus := w_reduction_cmd\n my_fan_network.io.i_sel_bus := w_reduction_sel\n io.o_valid := my_fan_network.io.o_valid\n io.o_data_bus := my_fan_network.io.o_data_bus\n io.o_adder := my_fan_network.io.o_adder\n}\n", "groundtruth": " val i_data_bus = Input(Vec(NUM_PES, UInt(DATA_TYPE.W)))\n val i_data_bus2 = Input(Vec(NUM_PES, UInt(DATA_TYPE.W)))\n\n val o_valid = Output(Vec(NUM_PES, UInt(1.W)))\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.85, "category_reason": "Input/Output port declarations"} {"task_id": "magma-si", "path": "magma-si/src/main/scala/components/MagmasiConfig.scala", "left_context": "package magmasi.components\nimport scala.math\n\ncase class MagmasiConfig (\n val DATA_TYPE: Int = 16,\n val NUM_PES : Int = 4,\n", "right_context": " val rowsA :Int = 4,\n val colsA :Int = 4,\n val rowsB :Int = 4,\n val colsB :Int = 4\n) {\n val LEVELS : Int = (2 * (math.log(NUM_IN) / math.log(2))).toInt + 1\n}", "groundtruth": " val NUM_IN : Int = 4,\n val SEL_IN: Int = 2,\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "magma-si", "path": "magma-si/src/main/scala/components/MultSwitch.scala", "left_context": "\npackage magmasi.components\nimport chisel3._\nimport chisel3.util._\n\nclass MultSwitch() extends Module {\n val io = IO(new Bundle {\n\n val i_valid = Input(Bool())\n val i_data = Input(UInt(16.W))\n val i_stationary = Input(Bool())\n val o_valid = Output(Bool())\n val o_data = Output(UInt(32.W))\n })\n\n val r_buffer = RegInit(0.U(16.W))\n val r_buffer_valid = RegInit(false.B)\n \n // Concatenate the temporary signal with 16 zeros and assign it to io.o_data\n\n\n // Logic to store correct value into the stationary buffer\n\n\n when(io.i_stationary && io.i_valid) {\n r_buffer := io.i_data // Latch the stationary value into the switch buffer\n r_buffer_valid := true.B // Validate buffer\n }\n\n\n val w_A = Mux(r_buffer_valid && io.i_valid, io.i_data, 0.U) // Streaming\n val w_B = Mux(r_buffer_valid && io.i_valid, r_buffer, 0.U) // Stationary\n\n // Logic to generate correct output valid signal\n val o_validReg = RegInit(false.B)\n\n", "right_context": " io.o_valid := o_validReg\n val multiplier_output = Wire(UInt(32.W))\n // Instantiate multiplier\n val multiplier_module = Module(new SimpleMultiplier)\n multiplier_module.io.A := w_A\n multiplier_module.io.B := w_B\n // Create a temporary signal to hold multiplier output\n multiplier_output := multiplier_module.io.O // Assign the value from the multiplier to the temporary signal\n\n io.o_data := Cat(0.U(16.W), multiplier_output(15, 0))\n\n // Convert BF16 to FP32\n \n}\n\n\n", "groundtruth": " when (r_buffer_valid && io.i_valid) {\n o_validReg := true.B\n }.otherwise {\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "magma-si", "path": "magma-si/src/main/scala/components/ReductionMux.scala", "left_context": "package magmasi.components\n\nimport chisel3._\nimport chisel3.util._\n\nclass ReductionMux(val W: Int = 32, val NUM_IN: Int = 4, val SEL_IN: Int = 2) extends Module {\n require(NUM_IN >= 2 && NUM_IN % 2 == 0, \"NUM_IN has to be >= 2 and divisible by 2\")\n require(SEL_IN % 2 == 0, \"SEL_IN has to be divisible by 2\")\n \n val SEL_IN_LEFT_END = SEL_IN / 2 - 1 // 2/1 =2\n val SEL_IN_RIGHT_START = SEL_IN / 2\n \n val io = IO(new Bundle {\n val i_data = Input(Vec(NUM_IN, UInt(W.W)))\n val i_sel = Input(UInt(SEL_IN.W))\n val o_data = Output(Vec(2, UInt(W.W)))\n })\n val w_data_left = Wire(Vec(NUM_IN/2,UInt(W.W)))\n for (i <- 0 until NUM_IN/2){\n w_data_left(i) := io.i_data(i)\n }\n val w_data_right = Wire(Vec(NUM_IN/2,UInt(W.W)))\n for (i <- 0 until NUM_IN/2 ){\n w_data_right(i) := io.i_data(i+NUM_IN/2)\n }\n\n\n val w_sel_in_left = (io.i_sel(SEL_IN_LEFT_END, 0))//210\n val w_sel_in_right = (io.i_sel(SEL_IN - 1, SEL_IN_RIGHT_START))\n\n", "right_context": "\n\n}\n", "groundtruth": " when ((w_sel_in_left).asUInt < 2.U) {\n \n io.o_data(0) := w_data_left(w_sel_in_left)\n }.otherwise {\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "magma-si", "path": "magma-si/src/main/scala/components/Regor.scala", "left_context": "package magmasi.components\n\nimport chisel3._\nimport chisel3.util._\n\nclass Regor(rows:Int,cols:Int,DATA_TYPE:Int) extends Module{\n implicit val config = MagmasiConfig()\n\n val io = IO(new Bundle{\n val mat1 =Input(Vec(rows, Vec(cols, UInt(DATA_TYPE.W))))\n val mat2 = Input(Vec(rows, Vec(cols, UInt(DATA_TYPE.W))))\n val compressedBitmap = Output(Vec(rows, Vec(cols, UInt(DATA_TYPE.W))))\n })\n val matReg1 = RegInit(VecInit(Seq.fill(rows)(VecInit(Seq.fill(cols)(0.U(DATA_TYPE.W))))))\n io.compressedBitmap := matReg1\n\n val bitmap = Module(new Bitmap())\n bitmap.io.mat1 := io.mat1\n bitmap.io.mat2 := io.mat2\n\n val reg = RegInit(VecInit(Seq.fill(rows)(false.B)))\n for (i <- 0 until rows) {\n reg(i) := io.mat2(i).map(_ =/= 0.U).reduce(_ || _)\n }\n dontTouch(reg)\n\n\n val i = RegInit(0.U(log2Ceil(rows).W))\n val j = RegInit(0.U(log2Ceil(cols).W))\n dontTouch(i)\n dontTouch(j)\n\n\n when (i < cols.U) {\n when ((reg(j) === 0.U) && (bitmap.io.bitmap1(i)(j) === 1.U)){\n matReg1(i)(j) := 0.U//bitmap.io.bitmap1(i)(j)\n", "right_context": " when (i === (rows-1).U){\n j := j + 1.U\n }\n}", "groundtruth": " }.otherwise{\n matReg1(i)(j) := bitmap.io.bitmap1(i)(j)\n }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.8, "category_reason": ".otherwise clause"} {"task_id": "magma-si", "path": "magma-si/src/main/scala/components/SimpleAdder.scala", "left_context": "package magmasi.components\n\nimport chisel3._\nimport chisel3.util._ \n\n\nclass SimpleAdder extends Module{\n val io = IO(new Bundle{\n val A = Input(UInt(32.W))\n val B = Input(UInt(32.W))\n val O = Output(UInt(32.W))\n })\n\n", "right_context": "}", "groundtruth": " io.O := io.A + io.B\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.5, "category_reason": ":= to io port"} {"task_id": "magma-si", "path": "magma-si/src/main/scala/components/SimpleMultiplier.scala", "left_context": "package magmasi.components\n\nimport chisel3._\nimport chisel3.util._ \n\n\nclass SimpleMultiplier extends Module{\n val io = IO(new Bundle{\n val A = Input(UInt(16.W))\n val B = Input(UInt(16.W))\n val O = Output(UInt(16.W))\n })\n\n", "right_context": "}", "groundtruth": " io.O := io.A * io.B\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.5, "category_reason": ":= to io port"} {"task_id": "magma-si", "path": "magma-si/src/main/scala/components/Switches.scala", "left_context": "/* These Modules are translated into CHISEL from https://github.com/georgia-tech-synergy-lab/SIGMA/blob/master/vmod/benes.v */\npackage magmasi.components\n\nimport chisel3._\n\n// input_switch module\nclass InputSwitch(val width: Int) extends Module {\n val io = IO(new Bundle {\n val y = Output(UInt(width.W))\n val z = Output(UInt(width.W))\n val in = Input(UInt(width.W))\n })\n io.y := io.in\n io.z := io.in\n}\n\n// output_switch module\nclass OutputSwitch(val width: Int) extends Module {\n val io = IO(new Bundle {\n val y = Output(UInt(width.W))\n val in0 = Input(UInt(width.W))\n val in1 = Input(UInt(width.W))\n val sel = Input(Bool())\n })\n\n val mux0 = Module(new BenesMux(width))\n mux0.io.a := io.in0\n mux0.io.b := io.in1\n mux0.io.sel := io.sel\n io.y := mux0.io.o\n}\n\n// switch module\nclass Switch(val width: Int) extends Module {\n val io = IO(new Bundle {\n val y = Output(UInt(width.W))\n val z = Output(UInt(width.W))\n val in0 = Input(UInt(width.W))\n", "right_context": " })\n\n val mux0 = Module(new BenesMux(width))\n val mux1 = Module(new BenesMux(width))\n mux0.io.a := io.in0\n mux0.io.b := io.in1\n mux0.io.sel := io.sel0\n mux1.io.a := io.in0\n mux1.io.b := io.in1\n mux1.io.sel := io.sel1\n io.y := mux0.io.o\n io.z := mux1.io.o\n}\n\n// benes_mux module is assumed to be available in the same scope\nclass BenesMux(W: Int) extends Module {\n val io = IO(new Bundle {\n val o = Output(UInt(W.W))\n val a = Input(UInt(W.W))\n val b = Input(UInt(W.W))\n val sel = Input(Bool())\n })\n\n io.o := Mux(io.sel, io.b, io.a)\n}", "groundtruth": " val in1 = Input(UInt(width.W))\n val sel0 = Input(Bool())\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.8, "category_reason": "Input or Output in Bundle/IO context"} {"task_id": "magma-si", "path": "magma-si/src/main/scala/components/benseBuffers.scala", "left_context": "package magmasi.components\n\nimport chisel3._\nimport chisel3.util._\n\nclass benseBuffers(implicit val config: MagmasiConfig) extends Module{\n \n", "right_context": " // benes routing calling here to reach it's destination into the buffer1 and buffer2\n val benes = Module(new Benes()) \n benes.io.i_data_bus1 <> io.i_data_bus1\n benes.io.i_data_bus2 <> io.i_data_bus2\n benes.io.i_mux_bus <> io.i_mux_bus\n\n //which buffer have get reaches their destination they will both get multiplication over here\n val buffer = Module(new buffer_multiplication())\n buffer.io.buffer1 <> benes.io.o_dist_bus1\n buffer.io.buffer2 <> benes.io.o_dist_bus2\n io.out := buffer.io.out\n}\n", "groundtruth": " val io = IO(new Bundle{\n val i_data_bus2 = Input(Vec(config.NUM_PES, UInt(config.DATA_TYPE.W)))\n val i_data_bus1 = Input(Vec(config.NUM_PES, UInt(config.DATA_TYPE.W)))\n val i_mux_bus = Input(Vec(config.NUM_PES, UInt((config.LEVELS-1).W)))\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.9, "category_reason": "IO bundle definition"} {"task_id": "magma-si", "path": "magma-si/src/main/scala/components/buffer_multiplication.scala", "left_context": "package magmasi.components\n\nimport chisel3._\nimport chisel3.util._\n\nclass buffer_multiplication(implicit val config: MagmasiConfig) extends Module{\n val io = IO(new Bundle{\n val buffer1 = Input(Vec(config.NUM_PES, UInt(config.DATA_TYPE.W)))\n val buffer2 = Input(Vec(config.NUM_PES, UInt(config.DATA_TYPE.W)))\n val out = Output(Vec(config.NUM_PES, UInt(config.DATA_TYPE.W)))\n })\n\n def multiply(vec1: Vec[UInt], vec2: Vec[UInt], index: Int = 0): Vec[UInt] = {\n if (index >= config.NUM_PES) {\n VecInit(Seq.fill(config.NUM_PES)(0.U(config.DATA_TYPE.W)))\n", "right_context": "}\n", "groundtruth": " } else {\n val elementMul = vec1(index) * vec2(index)\n val result = multiply(vec1, vec2, index + 1)\n result(index) := elementMul\n result\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.6, "category_reason": "val binding"} {"task_id": "magma-si", "path": "magma-si/src/test/scala/components/AdderSwitchTester.scala.scala", "left_context": "package magmasi.components\n\nimport chisel3._\nimport chisel3.util._\nimport chiseltest._ \nimport org.scalatest.freespec.AnyFreeSpec\n\nclass AdderSwitchTester extends AnyFreeSpec with ChiselScalatestTester {\n \"Adder Switch Test\" in {\n implicit val config = MagmasiConfig()\n test(new AdderSwitch(32,2,2,2)).withAnnotations(Seq(VerilatorBackendAnnotation)) { dut =>\n dut.io.i_data_bus(0).poke(2.U)\n dut.io.i_data_bus(1).poke(5.U)\n // dut.io.i_data_bus(4).poke(2.U)\n // dut.io.i_data_bus(5).poke(5.U)\n // dut.io.i_data_bus(6).poke(4.U)\n", "right_context": "\n }\n }\n}\n\n", "groundtruth": " // dut.io.i_data_bus(7).poke(6.U)\n dut.io.i_valid.poke(1.B)\n dut.io.i_add_en.poke(1.U)\n dut.io.i_cmd.poke(5.U)\n", "crossfile_context": "", "category": "Testbench Stimulus and Environment", "subcategory": "Stimulus Generation", "confidence": 0.85, "category_reason": "Chisel test harness (poke/peek/step)"} {"task_id": "magma-si", "path": "magma-si/src/test/scala/components/BitmapTester.scala", "left_context": "package magmasi.components\n\nimport chisel3._\nimport chisel3.util._\nimport chiseltest._ \nimport org.scalatest.freespec.AnyFreeSpec\n\nclass BitmapTester extends AnyFreeSpec with ChiselScalatestTester {\n \"Bitmap Table\" in {\n implicit val config = MagmasiConfig()\n test(new Bitmap()).withAnnotations (Seq(VerilatorBackendAnnotation)) { dut =>\n val inputData = Seq(\n Seq(0, 2, 3, 0),\n Seq(5, 6, 7, 0),\n Seq(9, 10, 11, 0),\n Seq(13, 14, 15, 0)\n ) \n\n\n // Assign test values to KM_matrix\n for (i <- 0 until 4) {\n", "right_context": " } \n}\n", "groundtruth": " for (j <- 0 until 4) {\n dut.io.mat1(i)(j).poke(inputData(i)(j).U)\n dut.io.mat2(i)(j).poke(inputData(i)(j).U)\n }\n", "crossfile_context": "", "category": "Testbench Stimulus and Environment", "subcategory": "Stimulus Generation", "confidence": 0.85, "category_reason": "Chisel test harness (poke/peek/step)"} {"task_id": "magma-si", "path": "magma-si/src/test/scala/components/EdgeAdderSwitchTester.scala.scala", "left_context": "package magmasi.components\n\nimport chisel3._\nimport chisel3.util._\nimport chiseltest._ \nimport org.scalatest.freespec.AnyFreeSpec\n\n", "right_context": " dut.io.i_data_bus(1).poke(4.U)\n // dut.io.i_data_bus(2).poke(5.U)\n // dut.io.i_data_bus(3).poke(6.U)\n // dut.io.i_data_bus(4).poke(3.U)\n // dut.io.i_data_bus(5).poke(4.U)\n // dut.io.i_data_bus(6).poke(5.U)\n // dut.io.i_data_bus(7).poke(6.U)\n dut.io.i_valid.poke(1.B)\n dut.io.i_add_en.poke(1.U)\n dut.io.i_cmd.poke(5.U)\n dut.io.i_sel.poke(1.U)\n dut.clock.step(3)\n //dut.io.o_adder.expect(10.U)\n\n }\n }\n}\n\n\n", "groundtruth": "class EdgeAdderSwitchTester extends AnyFreeSpec with ChiselScalatestTester {\n \"Edge Adder Switch Test\" in {\n implicit val config = MagmasiConfig()\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.6, "category_reason": "val binding"} {"task_id": "magma-si", "path": "magma-si/src/test/scala/components/FanCtrlTester.scala", "left_context": "package magmasi.components\n\nimport chisel3._\nimport chisel3.util._\nimport chiseltest._ \nimport org.scalatest.freespec.AnyFreeSpec\n\nclass fancontroltest extends AnyFreeSpec with ChiselScalatestTester {\n \"Fancontrolcom Test\" in {\n test(new fancontrol(32,32,5)){ c =>\n c.io.i_vn(0).poke(\"b11111\".U)\n c.io.i_vn(1).poke(\"b11111\".U)\n c.io.i_vn(2).poke(\"b11111\".U)\n c.io.i_vn(3).poke(\"b11111\".U)\n c.io.i_vn(4).poke(\"b11111\".U)\n c.io.i_vn(5).poke(\"b11111\".U)\n c.io.i_vn(6).poke(\"b11111\".U)\n c.io.i_vn(7).poke(\"b11111\".U)\n c.io.i_vn(8).poke(\"b11111\".U)\n c.io.i_vn(9).poke(\"b11111\".U)\n", "right_context": " c.io.i_vn(17).poke(\"b11111\".U)\n c.io.i_vn(18).poke(\"b11111\".U)\n c.io.i_vn(19).poke(\"b11111\".U)\n c.io.i_vn(20).poke(\"b11111\".U)\n c.io.i_vn(21).poke(\"b11111\".U)\n c.io.i_vn(22).poke(\"b11111\".U)\n c.io.i_vn(23).poke(\"b11111\".U)\n c.io.i_vn(24).poke(\"b11111\".U)\n c.io.i_vn(25).poke(\"b11111\".U)\n c.io.i_vn(26).poke(\"b11111\".U)\n c.io.i_vn(27).poke(\"b11111\".U)\n c.io.i_vn(28).poke(\"b11111\".U)\n c.io.i_vn(29).poke(\"b11111\".U)\n c.io.i_vn(30).poke(\"b11111\".U)\n\n \n \n c.io.i_stationary.poke(0.B)\n c.io.i_data_valid.poke(1.B)\n\n \n c.clock.step(20)\n }\n }\n}\n\n\n", "groundtruth": " c.io.i_vn(10).poke(\"b11111\".U)\n c.io.i_vn(11).poke(\"b11111\".U)\n\n c.io.i_vn(12).poke(\"b11111\".U)\n c.io.i_vn(13).poke(\"b11111\".U)\n", "crossfile_context": "", "category": "Testbench Stimulus and Environment", "subcategory": "Stimulus Generation", "confidence": 0.85, "category_reason": "Chisel test harness (poke/peek/step)"} {"task_id": "magma-si", "path": "magma-si/src/test/scala/components/FanNetworkTester.scala", "left_context": "package magmasi.components\n\nimport chisel3._\nimport chisel3.util._\nimport chiseltest._ \nimport org.scalatest.freespec.AnyFreeSpec\n\nclass FanNetcomTester extends AnyFreeSpec with ChiselScalatestTester {\n \"FanNetcomplete Test\" in {\n test(new FanNetworkcom(32,32)){ c =>\n\n c.io.i_valid.poke(1.U)\n c.io.i_data_bus(0).poke(1.U)\n c.io.i_data_bus(1).poke(1.U)\n c.io.i_data_bus(2).poke(1.U)\n c.io.i_data_bus(3).poke(1.U)\n c.io.i_data_bus(4).poke(1.U)\n c.io.i_data_bus(5).poke(1.U)\n c.io.i_data_bus(6).poke(1.U)\n c.io.i_data_bus(7).poke(1.U)\n c.io.i_data_bus(8).poke(1.U)\n c.io.i_data_bus(9).poke(1.U)\n c.io.i_data_bus(10).poke(1.U)\n c.io.i_data_bus(11).poke(1.U)\n c.io.i_data_bus(12).poke(1.U)\n c.io.i_data_bus(13).poke(1.U)\n c.io.i_data_bus(14).poke(1.U)\n c.io.i_data_bus(15).poke(1.U)\n c.io.i_data_bus(16).poke(1.U)\n c.io.i_data_bus(17).poke(1.U)\n c.io.i_data_bus(18).poke(1.U)\n c.io.i_data_bus(19).poke(1.U)\n c.io.i_data_bus(20).poke(1.U)\n c.io.i_data_bus(21).poke(1.U)\n c.io.i_data_bus(22).poke(1.U)\n c.io.i_data_bus(23).poke(1.U)\n c.io.i_data_bus(24).poke(1.U)\n c.io.i_data_bus(25).poke(1.U)\n c.io.i_data_bus(26).poke(1.U)\n c.io.i_data_bus(27).poke(1.U)\n c.io.i_data_bus(28).poke(1.U)\n c.io.i_data_bus(29).poke(1.U)\n c.io.i_data_bus(30).poke(1.U)\n c.io.i_data_bus(31).poke(1.U)\n //c.io.i_add_en_bus.poke(2147483647.U)\n \n \n", "right_context": " c.io.i_add_en_bus(i).poke(1.U)\n c.io.i_cmd_bus(i).poke(\"b101\".U)\n }\n // c.io.i_cmd_bus.poke(\"b101101101101101101101101101101101101101101101101101101101101101101101101101101101101101101101\".U)\n //c.io.i_sel_bus.poke(1.U)\n for (i <- 0 until 20) {\n c.io.i_sel_bus(i).poke(1.U)\n }\n\n c.clock.step(20)\n }\n }\n}\n\n\n", "groundtruth": " for (i <- 0 until 31) {\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Loop-based Control", "confidence": 0.8, "category_reason": "for loop"} {"task_id": "magma-si", "path": "magma-si/src/test/scala/components/FlexDPE_Tester.scala", "left_context": "package magmasi.components\n\nimport chisel3._\nimport chisel3.util._\nimport chiseltest._ \nimport org.scalatest.freespec.AnyFreeSpec\n\nclass flexdpecom2test extends AnyFreeSpec with ChiselScalatestTester {\n \"flexdpe Test\" in {\n test(new flexdpecom2()){ c =>\n\n // for input data base 1\n c.io.i_data_bus(0).poke(1.U)\n c.io.i_data_bus(1).poke(1.U)\n c.io.i_data_bus(2).poke(1.U)\n c.io.i_data_bus(3).poke(1.U)\n // for input data bus 2\n c.io.i_data_bus2(0).poke(0.U)\n c.io.i_data_bus2(1).poke(2.U)\n c.io.i_data_bus2(2).poke(2.U)\n c.io.i_data_bus2(3).poke(0.U)\n\n\n // for i vn\n c.io.i_vn(3).poke(\"b11101\".U)\n c.io.i_vn(4).poke(\"b11101\".U)\n\n c.io.i_vn(7).poke(\"b10111\".U)\n c.io.i_vn(8).poke(\"b10111\".U)\n\n c.io.i_vn(11).poke(\"b01111\".U)\n c.io.i_vn(12).poke(\"b01111\".U)\n\n c.io.i_vn(15).poke(\"b11110\".U)\n c.io.i_vn(16).poke(\"b11110\".U)\n\n c.io.i_vn(23).poke(\"b11111\".U)\n", "right_context": " c.io.i_vn(13).poke(\"b11000\".U)\n\n // for muxes\n c.io.i_mux_bus(576).poke(1.B)\n c.io.i_mux_bus(579).poke(1.B)\n\n // stationary and valid\n c.io.i_stationary.poke(1.B)\n c.io.i_data_valid.poke(1.B)\n\n c.clock.step(20)\n // for input data base 1\n c.io.i_data_bus(0).poke(1.U)\n c.io.i_data_bus(1).poke(1.U)\n c.io.i_data_bus(2).poke(1.U)\n c.io.i_data_bus(3).poke(1.U)\n // for input data bus 2\n c.io.i_data_bus2(0).poke(0.U)\n c.io.i_data_bus2(1).poke(3.U)\n c.io.i_data_bus2(2).poke(3.U)\n c.io.i_data_bus2(3).poke(0.U)\n\n // for i vn\n c.io.i_vn(3).poke(\"b11101\".U)\n c.io.i_vn(4).poke(\"b11101\".U)\n\n c.io.i_vn(7).poke(\"b10111\".U)\n c.io.i_vn(8).poke(\"b10111\".U)\n\n c.io.i_vn(11).poke(\"b01111\".U)\n c.io.i_vn(12).poke(\"b01111\".U)\n\n c.io.i_vn(15).poke(\"b11110\".U)\n c.io.i_vn(16).poke(\"b11110\".U)\n\n c.io.i_vn(23).poke(\"b11111\".U)\n c.io.i_vn(24).poke(\"b11111\".U)\n\n c.io.i_vn(18).poke(\"b11111\".U)\n c.io.i_vn(13).poke(\"b11000\".U)\n\n // for muxes\n c.io.i_mux_bus(576).poke(1.B)\n c.io.i_mux_bus(579).poke(1.B)\n\n // stationary and valid\n c.io.i_stationary.poke(1.B)\n c.io.i_data_valid.poke(1.B)\n \n c.clock.step(40)\n }\n }\n}\n", "groundtruth": " c.io.i_vn(24).poke(\"b11111\".U)\n\n", "crossfile_context": "", "category": "Testbench Stimulus and Environment", "subcategory": "Stimulus Generation", "confidence": 0.85, "category_reason": "Chisel test harness (poke/peek/step)"} {"task_id": "magma-si", "path": "magma-si/src/test/scala/components/MultSwitchTester.scala", "left_context": "\npackage magmasi.components\n\nimport chisel3._\nimport chisel3.util._\nimport chiseltest._ \nimport org.scalatest.freespec.AnyFreeSpec\n\nclass MultSwitchTester extends AnyFreeSpec with ChiselScalatestTester {\n \"multiplier Switch Test\" in {\n test(new MultSwitch()){ dut =>\n dut.io.i_valid.poke(1.B)\n", "right_context": " dut.clock.step(2)\n }\n }\n}\n", "groundtruth": " dut.io.i_data.poke(2.U)\n dut.io.i_stationary.poke(1.U)\n dut.io.o_valid.expect(0.B)\n", "crossfile_context": "", "category": "Monitoring and Checking Logic", "subcategory": "Error Reporting and Logging", "confidence": 0.85, "category_reason": "Chisel expect (golden check)"} {"task_id": "magma-si", "path": "magma-si/src/test/scala/components/MybenesTester.scala", "left_context": "\npackage magmasi.components\n\nimport chisel3._\nimport chisel3.util._\nimport chiseltest._ \nimport org.scalatest.freespec.AnyFreeSpec\n\nclass MybenesTester extends AnyFreeSpec with ChiselScalatestTester {\n \"Benes Test\" in {\n implicit val config = MagmasiConfig()\n test(new Benes()).withAnnotations(Seq(VerilatorBackendAnnotation)) { dut =>\n val inputData = Seq(1,2,2,4)\n for (i <- 0 until 4) {\n dut.io.i_data_bus2(i).poke(inputData(i).U)\n //dut.io.i_data_bus2(i).poke(inputData(i).U)\n }\n dut.io.i_mux_bus(0).poke(0.B)\n dut.io.i_mux_bus(1).poke(0.B)\n dut.io.i_mux_bus(2).poke(0.B)\n dut.io.i_mux_bus(3).poke(0.B)\n", "right_context": " dut.clock.step(5)\n }\n } \n}\n", "groundtruth": " val LEVELS : Int = (2 * (math.log(4) / math.log(2))).toInt + 1\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "magma-si", "path": "magma-si/src/test/scala/components/ReductionMuxTester.scala", "left_context": "package magmasi.components\n\nimport chisel3._\nimport chisel3.util._\nimport chiseltest._ \nimport org.scalatest.freespec.AnyFreeSpec\n\nclass ReductionMuxTester extends AnyFreeSpec with ChiselScalatestTester {\n \"Reduction Mux Test\" in {\n implicit val config = MagmasiConfig()\n test(new ReductionMux).withAnnotations(Seq(VerilatorBackendAnnotation)) { dut =>\n dut.io.i_data(0).poke(3.U)\n", "right_context": "", "groundtruth": " dut.io.i_data(1).poke(4.U)\n dut.io.i_data(2).poke(5.U)\n dut.io.i_data(3).poke(6.U)\n dut.io.i_sel.poke(3.U)\n dut.clock.step(1)\n", "crossfile_context": "", "category": "Testbench Stimulus and Environment", "subcategory": "Stimulus Generation", "confidence": 0.85, "category_reason": "Chisel test harness (poke/peek/step)"} {"task_id": "magma-si", "path": "magma-si/src/test/scala/components/RegorTester.scala", "left_context": "package magmasi.components\n\nimport chisel3._\nimport chisel3.util._\nimport chiseltest._ \nimport org.scalatest.freespec.AnyFreeSpec\n\nclass RegorTester extends AnyFreeSpec with ChiselScalatestTester {\n \"Temporary Register step 3 Table\" in {\n implicit val config = MagmasiConfig()\n test(new Regor(4,4,32)).withAnnotations (Seq(VerilatorBackendAnnotation)) { dut =>\n val inputData = Seq(\n Seq(0, 2, 3, 1),\n Seq(5, 6, 7, 0),\n Seq(9, 10, 11, 0),\n Seq(1, 2, 3, 0)\n", "right_context": " Seq(0, 0, 0, 0)\n )\n\n\n // Assign test values to KM_matrix\n for (i <- 0 until 4) {\n for (j <- 0 until 4) {\n dut.io.mat1(i)(j).poke(inputData(i)(j).U)\n dut.io.mat2(i)(j).poke(inputData1(i)(j).U)\n }\n }\n dut.clock.step(65)\n }\n } \n}\n\n", "groundtruth": " ) \n val inputData1 = Seq(\n Seq(1, 2, 0, 0),\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.6, "category_reason": "val binding"} {"task_id": "magma-si", "path": "magma-si/src/test/scala/components/benesBuffersTester.scala", "left_context": "\npackage magmasi.components\n\nimport chisel3._\nimport chisel3.util._\nimport chiseltest._ \nimport org.scalatest.freespec.AnyFreeSpec\n\nclass benesBuffersTester extends AnyFreeSpec with ChiselScalatestTester {\n \"My Benes Top test\" in {\n implicit val config = MagmasiConfig()\n test(new benseBuffers()).withAnnotations(Seq(VerilatorBackendAnnotation)) { dut =>\n\n \n val inputData = Seq(1, 2, 3, 4, 5, 6, 7, 8)\n\n // Connect input data to the DUT\n", "right_context": " dut.io.i_mux_bus(0).poke(3.U)\n dut.io.i_mux_bus(1).poke(3.U)\n dut.io.i_mux_bus(2).poke(3.U)\n dut.io.i_mux_bus(3).poke(3.U)\n val LEVELS : Int = (2 * (math.log(4) / math.log(2))).toInt + 1\n\n\n\n\n\n dut.clock.step(3)\n\n\n\n }\n }\n}\n", "groundtruth": " for (i <- 0 until 4) {\n dut.io.i_data_bus1(i).poke(inputData(i).U)\n }\n", "crossfile_context": "", "category": "Testbench Stimulus and Environment", "subcategory": "Stimulus Generation", "confidence": 0.85, "category_reason": "Chisel test harness (poke/peek/step)"} {"task_id": "magma-si", "path": "magma-si/src/test/scala/components/bufferMultTester.scala", "left_context": "package magmasi.components\n\nimport chisel3._\nimport chisel3.util._\nimport chiseltest._ \nimport org.scalatest.freespec.AnyFreeSpec\n\nclass bufferMultTester extends AnyFreeSpec with ChiselScalatestTester {\n \"buffer multiplication Test\" in {\n val DATA_TYPE = 32\n val NUM_IN = 4\n implicit val config = MagmasiConfig()\n test(new buffer_multiplication()).withAnnotations(Seq(VerilatorBackendAnnotation)) { dut =>\n", "right_context": " }\n}\n\n\n\n", "groundtruth": " val inputData = Seq(1, 2, 3, 4, 5, 6, 7, 8)\n for (i <- 0 until NUM_IN) {\n dut.io.buffer1(i).poke(inputData(i).U)\n dut.io.buffer2(i).poke(inputData(i).U)\n", "crossfile_context": "", "category": "Testbench Stimulus and Environment", "subcategory": "Stimulus Generation", "confidence": 0.85, "category_reason": "Chisel test harness (poke/peek/step)"} {"task_id": "tiny-gpu-chisel", "path": "tiny-gpu-chisel/playground/src/Alu.scala", "left_context": "package alu\n\nimport chisel3._\nimport chisel3.util._\nimport statecode.CoreState\nimport statecode.AluOpCode\n\nclass Alu extends Module {\n val io = IO(new Bundle {\n val enable = Input(Bool())\n\n val core_state = Input(CoreState())\n\n val decoded_alu_op = new Bundle {\n val arithmetic_mux = Input(AluOpCode()) // Select arithmetic operation\n val output_mux = Input(Bool()) // Select operation in ALU\n }\n\n val reg_in = new Bundle {\n val rs = Input(UInt(8.W))\n val rt = Input(UInt(8.W))\n }\n\n val alu_out = Output(UInt(8.W))\n })\n\n val alu_out_reg = RegInit(0.U(8.W))\n\n when(io.enable) {\n when(io.core_state === CoreState.EXECUTE) {\n", "right_context": " alu_out_reg := io.reg_in.rs + io.reg_in.rt\n }\n is(AluOpCode.SUB) {\n alu_out_reg := io.reg_in.rs - io.reg_in.rt\n }\n is(AluOpCode.MUL) {\n alu_out_reg := io.reg_in.rs * io.reg_in.rt\n }\n is(AluOpCode.DIV) {\n alu_out_reg := io.reg_in.rs / io.reg_in.rt\n }\n }\n }\n }\n }\n\n when(reset.asBool) {\n io.alu_out := 0.U\n }.otherwise {\n io.alu_out := alu_out_reg\n }\n}\n", "groundtruth": " when(io.decoded_alu_op.output_mux) {\n // Set values to compare with NZP register in alu_out[2:0]\n val gt = io.reg_in.rs > io.reg_in.rt\n val eq = io.reg_in.rs === io.reg_in.rt\n val lt = io.reg_in.rs < io.reg_in.rt\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "tiny-gpu-chisel", "path": "tiny-gpu-chisel/playground/src/Controller.scala", "left_context": "package controller\n\nimport chisel3._\nimport chisel3.util._\n\nimport statecode.ControlState\n\n// MEMORY CONTROLLER\n// > Receives memory requests from all cores\n// > Throttles requests based on limited external memory bandwidth\n// > Waits for responses from external memory and distributes them back to cores\nclass Controller(\n AddrBits: Int = 8,\n DataBits: Int = 16,\n NumConsumers: Int = 4,\n NumChannels: Int = 1,\n WriteEnable: Boolean = true)\n extends Module {\n // TODO: Use decoupledIO interface for consumer and memory\n val io = IO(new Bundle {\n // Consumer Interface (Fetchers / LSUs)\n val consumer_read_addr_receiver = Vec(NumConsumers, Flipped(new DecoupledIO(UInt(AddrBits.W))))\n val consumer_read_data = Output(Vec(NumConsumers, UInt(DataBits.W)))\n\n val consumer_write_receiver =\n if (WriteEnable)\n Some(\n Vec(\n NumConsumers,\n Flipped(DecoupledIO(new Bundle {\n val address = UInt(AddrBits.W)\n val data = UInt(DataBits.W)\n }))\n )\n )\n else None\n\n // Memory Interface (Data / Program)\n val mem_read_sender = Vec(NumChannels, new DecoupledIO(UInt(AddrBits.W)))\n val mem_read_data = Input(Vec(NumChannels, UInt(DataBits.W)))\n\n val mem_write_sender =\n if (WriteEnable)\n Some(\n Vec(\n NumChannels,\n DecoupledIO(new Bundle {\n val address = UInt(AddrBits.W)\n val data = UInt(DataBits.W)\n })\n )\n )\n else None\n })\n\n val mem_read_valid = RegInit(VecInit(Seq.fill(NumChannels)(false.B)))\n val mem_read_address = RegInit(VecInit(Seq.fill(NumChannels)(0.U(AddrBits.W))))\n\n val mem_write_valid = RegInit(VecInit(Seq.fill(NumChannels)(false.B)))\n val mem_write_address = RegInit(VecInit(Seq.fill(NumChannels)(0.U(AddrBits.W))))\n val mem_write_data = RegInit(VecInit(Seq.fill(NumChannels)(0.U(DataBits.W))))\n\n val consumer_read_ready = RegInit(VecInit(Seq.fill(NumConsumers)(false.B)))\n val consumer_read_data = RegInit(VecInit(Seq.fill(NumConsumers)(0.U(DataBits.W))))\n val consumer_write_ready = RegInit(VecInit(Seq.fill(NumConsumers)(false.B)))\n\n val current_consumer = RegInit(VecInit(Seq.fill(NumChannels)(0.U(log2Ceil(NumConsumers).W))))\n val controller_state = RegInit(VecInit(Seq.fill(NumChannels)(ControlState.IDLE)))\n\n val channel_serving_consumer = RegInit(VecInit(Seq.fill(NumConsumers)(false.B)))\n\n // // Add debug printing\n // printf(\"#### Module Internal State ####\\n\")\n // printf(cf\"#controller_state: ${controller_state}\\n\")\n // printf(cf\"#mem_read_valid: ${mem_read_valid}\\n\")\n // printf(cf\"#mem_read_address: ${mem_read_address}\\n\")\n // printf(cf\"#mem_write_valid: ${mem_write_valid}\\n\")\n // printf(cf\"#mem_write_address: ${mem_write_address}\\n\")\n // printf(cf\"#mem_write_data: ${mem_write_data}\\n\")\n // printf(cf\"#consumer_read_ready: ${consumer_read_ready}\\n\")\n // printf(cf\"#consumer_read_data: ${consumer_read_data}\\n\")\n // printf(cf\"#consumer_write_ready: ${consumer_write_ready}\\n\")\n // printf(cf\"#channel_serving_consumer: ${channel_serving_consumer}\\n\")\n // printf(cf\"#current_consumer: ${current_consumer}\\n\")\n\n when(!reset.asBool) {\n // For each channel, we handle processing concurrently\n for (i <- 0 until NumChannels) {\n switch(controller_state(i)) {\n is(ControlState.IDLE) {\n // While this channel is idle, cycle through consumers looking for one with a pending request\n // Once we find a pending request, pick it up with this channel and stop looking for requests\n val read_signals = Wire(Vec(NumConsumers, Bool()))\n // val write_signals = Wire(Vec(NumConsumers, Bool()))\n val write_signals = VecInit(Seq.fill(NumConsumers)(false.B))\n for (j <- 0 until NumConsumers) {\n read_signals(j) := io.consumer_read_addr_receiver(j).valid && !channel_serving_consumer(j)\n // write_signals(j) := io.consumer_write_receiver(j).valid && !channel_serving_consumer(j)\n io.consumer_write_receiver.map(write_receiver =>\n write_signals(j) := write_receiver(j).valid && !channel_serving_consumer(j)\n )\n }\n\n val first_read_idx = PriorityEncoder(read_signals)\n val first_write_idx = PriorityEncoder(write_signals)\n // printf(\"#first_read_idx: %b, first_write_idx: %b\\n\", first_read_idx, first_write_idx)\n\n when(read_signals.asUInt > 0.U && first_read_idx <= first_write_idx) {\n val read_address = io.consumer_read_addr_receiver(first_read_idx).bits\n\n channel_serving_consumer(first_read_idx) := true.B\n current_consumer(i) := first_read_idx\n\n mem_read_valid(i) := true.B\n mem_read_address(i) := read_address\n\n controller_state(i) := ControlState.READ_WAITING\n }.elsewhen(write_signals.asUInt > 0.U) {\n // val write_address = io.consumer_write_receiver(first_write_idx).bits.address\n // val write_data = io.consumer_write_receiver(first_write_idx).bits.data\n val write_address = io.consumer_write_receiver.map(_.apply(first_write_idx).bits.address).getOrElse(0.U)\n val write_data = io.consumer_write_receiver.map(_.apply(first_write_idx).bits.data).getOrElse(0.U)\n\n channel_serving_consumer(first_write_idx) := true.B\n", "right_context": " }\n }\n is(ControlState.READ_WAITING) {\n // Wait for response from memory for pending read request\n when(io.mem_read_sender(i).ready) {\n mem_read_valid(i) := false.B\n consumer_read_ready(current_consumer(i)) := true.B\n consumer_read_data(current_consumer(i)) := io.mem_read_data(i)\n controller_state(i) := ControlState.READ_RELAYING\n }\n }\n is(ControlState.WRITE_WAITING) {\n // Wait for response from memory for pending write request\n val write_ready = io.mem_write_sender.map(_.apply(i).ready).getOrElse(false.B)\n // when(io.mem_write_sender(i).ready) {\n when(write_ready) {\n mem_write_valid(i) := false.B\n consumer_write_ready(current_consumer(i)) := true.B\n controller_state(i) := ControlState.WRITE_RELAYING\n }\n }\n is(ControlState.READ_RELAYING) {\n when(!io.consumer_read_addr_receiver(current_consumer(i)).valid) {\n channel_serving_consumer(current_consumer(i)) := false.B\n consumer_read_ready(current_consumer(i)) := false.B\n controller_state(i) := ControlState.IDLE\n }\n }\n is(ControlState.WRITE_RELAYING) {\n val write_valid = io.consumer_write_receiver.map(!_.apply(current_consumer(i)).valid).getOrElse(false.B)\n // when(!io.consumer_write_receiver(current_consumer(i)).valid) {\n when(write_valid) {\n channel_serving_consumer(current_consumer(i)) := false.B\n consumer_write_ready(current_consumer(i)) := false.B\n controller_state(i) := ControlState.IDLE\n }\n }\n }\n }\n }\n\n for (i <- 0 until NumConsumers) {\n io.consumer_read_addr_receiver(i).ready := consumer_read_ready(i)\n io.consumer_read_data(i) := consumer_read_data(i)\n // io.consumer_write_receiver(i).ready := consumer_write_ready(i)\n io.consumer_write_receiver.map(_.apply(i).ready := consumer_write_ready(i))\n }\n\n for (i <- 0 until NumChannels) {\n io.mem_read_sender(i).valid := mem_read_valid(i)\n io.mem_read_sender(i).bits := mem_read_address(i)\n // io.mem_write_sender(i).valid := mem_write_valid(i)\n // io.mem_write_sender(i).bits.address := mem_write_address(i)\n // io.mem_write_sender(i).bits.data := mem_write_data(i)\n io.mem_write_sender.map(sender => {\n sender(i).valid := mem_write_valid(i)\n sender(i).bits.address := mem_write_address(i)\n sender(i).bits.data := mem_write_data(i)\n })\n }\n}\n", "groundtruth": " current_consumer(i) := first_write_idx\n\n mem_write_valid(i) := true.B\n mem_write_address(i) := write_address\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.6, "category_reason": ":= in when/switch context"} {"task_id": "tiny-gpu-chisel", "path": "tiny-gpu-chisel/playground/src/Core.scala", "left_context": "package core\n\nimport chisel3._\nimport chisel3.util._\nimport statecode.CoreState\n\nimport fetcher.Fetcher\nimport decoder.Decoder\nimport scheduler.Scheduler\nimport registers.RegisterFiles\nimport alu.Alu\nimport lsu.MemLoadStoreUnit\nimport pc.ProgramCounter\n\n// TODO: Change each submodules' IO Bundle,\n// and then connect them in a more Chisel way\n\n// COMPUTE CORE\n// > Handles processing 1 block at a time\n// > The core also has it's own scheduler to manage control flow\n// > Each core contains 1 fetcher & decoder, and register files, ALUs, LSUs, PC for each thread\nclass Core(\n DataMemAddrBits: Int = 8,\n DataMemDataBits: Int = 8,\n ProgramMemAddrBits: Int = 8,\n ProgramMemDataBits: Int = 16,\n ThreadsPerBlock: Int = 4)\n extends Module {\n val io = IO(new Bundle {\n // Kernel Execution\n val start = Input(Bool())\n val done = Output(Bool())\n\n // Block Metadata\n val block_id = Input(UInt(8.W))\n val thread_count = Input(UInt(log2Ceil(ThreadsPerBlock).W))\n\n // Program Memory\n val program_mem_read_address_sender = new DecoupledIO(UInt(ProgramMemAddrBits.W))\n val program_mem_read_data = Input(UInt(ProgramMemDataBits.W))\n\n // Data Memory\n\n val data_mem_read_data = Input(Vec(ThreadsPerBlock, UInt(DataMemDataBits.W)))\n val data_mem_read_address_sender = Vec(ThreadsPerBlock, new DecoupledIO(UInt(DataMemAddrBits.W)))\n val data_mem_write_sender = Vec(\n ThreadsPerBlock,\n new DecoupledIO(new Bundle {\n val address = UInt(DataMemAddrBits.W)\n val data = UInt(DataMemDataBits.W)\n })\n )\n\n // debug outputs\n val core_state = Output(CoreState())\n val current_pc = Output(UInt(8.W))\n })\n\n val fetcher = Module(new Fetcher(ProgramMemAddrBits, ProgramMemDataBits))\n val decoder = Module(new Decoder())\n val scheduler = Module(new Scheduler(ThreadsPerBlock))\n\n // val core_state = RegNext(scheduler.io.core_state)\n // val current_pc = RegNext(scheduler.io.current_pc)\n val core_state = Wire(CoreState())\n val current_pc = Wire(UInt(8.W))\n core_state := scheduler.io.core_state\n current_pc := scheduler.io.current_pc\n\n // printf(cf\"--Core State: $core_state, current PC: $current_pc, Fetcher State: ${fetcher.io.fetcher_state}\\n\")\n\n // Fetcher inputs connections (3/3)\n fetcher.io.core_state := core_state\n fetcher.io.current_pc := current_pc\n fetcher.io.mem_read_data := io.program_mem_read_data\n\n // Decoder inputs connections (2/2)\n decoder.io.core_state := scheduler.io.core_state\n decoder.io.instruction := fetcher.io.instruction\n\n // Scheduler inputs connections (5/7)\n scheduler.io.start := io.start\n scheduler.io.mem_rw_enable := decoder.io.mem_rw_enable\n scheduler.io.decoded_ret := decoder.io.decoded_ret\n scheduler.io.fetcher_state := fetcher.io.fetcher_state\n\n // TODO: just use a for loop\n val compute_units = Seq\n .tabulate(ThreadsPerBlock)(i => {\n val alu = Module(new Alu())\n val lsu = Module(new MemLoadStoreUnit())\n val regfile = Module(new RegisterFiles(ThreadsPerBlock, i, DataMemDataBits))\n val pc = Module(new ProgramCounter(DataMemDataBits, DataMemAddrBits))\n\n val enable = (i.U < io.thread_count)\n\n // alu inputs connections (6/6)\n alu.io.enable := enable\n alu.io.core_state := scheduler.io.core_state\n alu.io.reg_in := regfile.io.reg_out\n alu.io.decoded_alu_op := decoder.io.decoded_alu_op\n\n // lsu inputs connections (7/7)\n", "right_context": " regfile.io.enable := enable\n regfile.io.block_id := io.block_id\n regfile.io.core_state := scheduler.io.core_state\n regfile.io.decoded_reg_address := decoder.io.decoded_reg_address\n regfile.io.decoded_reg_write_enable := decoder.io.decoded_reg_write_enable\n regfile.io.decoded_reg_input_mux := decoder.io.decoded_reg_input_mux\n regfile.io.decoded_immediate := decoder.io.decoded_immediate\n regfile.io.alu_out := alu.io.alu_out\n regfile.io.lsu_out := lsu.io.lsu_out\n\n // pc inputs connections (8/8)\n pc.io.enable := enable\n pc.io.decoded_nzp := decoder.io.decoded_nzp\n pc.io.decoded_immediate := decoder.io.decoded_immediate\n pc.io.decoded_nzp_write_enable := decoder.io.decoded_nzp_write_enable\n pc.io.decoded_pc_mux := decoder.io.decoded_pc_mux\n pc.io.alu_out := alu.io.alu_out\n pc.io.current_pc := scheduler.io.current_pc\n pc.io.core_state := scheduler.io.core_state\n\n // Connect to scheduler input (7/7)\n scheduler.io.lsu_state(i) := lsu.io.lsu_state\n scheduler.io.next_pc(i) := pc.io.next_pc\n\n // Connect to core module outputs (5/8)\n io.data_mem_read_address_sender(i) <> lsu.io.mem_read_address_sender\n io.data_mem_write_sender(i) <> lsu.io.mem_write_sender\n\n (alu, lsu, regfile, pc)\n })\n\n // Connect to module outputs (8/8)\n io.done := scheduler.io.done\n io.program_mem_read_address_sender <> fetcher.io.mem_read_address_sender\n\n // debug\n io.core_state := core_state\n io.current_pc := current_pc\n}\n", "groundtruth": " lsu.io.enable := enable\n lsu.io.core_state := scheduler.io.core_state\n lsu.io.mem_rw_enable := decoder.io.mem_rw_enable\n lsu.io.mem_read_data := io.data_mem_read_data(i)\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.5, "category_reason": ":= to io port"} {"task_id": "tiny-gpu-chisel", "path": "tiny-gpu-chisel/playground/src/Decoder.scala", "left_context": "package decoder\n\nimport chisel3._\nimport chisel3.util._\n\nimport statecode.CoreState\nimport statecode.AluOpCode\nimport statecode.RegInputOp\nimport statecode.DecoderState\n\nclass Decoder extends Module {\n val io = IO(new Bundle {\n val core_state = Input(CoreState())\n val instruction = Input(UInt(16.W))\n\n // Instruction signals\n val decoded_reg_address = new Bundle {\n val rd = Output(UInt(4.W))\n val rs = Output(UInt(4.W))\n val rt = Output(UInt(4.W))\n }\n val decoded_nzp = Output(UInt(3.W))\n val decoded_immediate = Output(UInt(8.W))\n\n // Control signals\n val mem_rw_enable = new Bundle {\n val read_enable = Output(Bool()) // Enable reading from memory\n val write_enable = Output(Bool()) // Enable writing to memory\n }\n val decoded_reg_write_enable = Output(Bool()) // Enable writing to a register\n val decoded_nzp_write_enable = Output(Bool()) // Enable writing to NZP register\n val decoded_reg_input_mux = Output(RegInputOp()) // Select input to register\n\n val decoded_alu_op = new Bundle {\n val arithmetic_mux = Output(AluOpCode()) // Select arithmetic operation\n val output_mux = Output(Bool()) // Select operation in ALU\n }\n val decoded_pc_mux = Output(Bool()) // Select source of next PC\n\n // Return (finished executing thread)\n val decoded_ret = Output(Bool())\n })\n\n val decoded_rd_address = RegInit(0.U(4.W))\n val decoded_rs_address = RegInit(0.U(4.W))\n val decoded_rt_address = RegInit(0.U(4.W))\n val decoded_nzp = RegInit(0.U(3.W))\n val decoded_immediate = RegInit(0.U(8.W))\n val decoded_reg_write_enable = RegInit(false.B)\n val decoded_mem_read_enable = RegInit(false.B)\n val decoded_mem_write_enable = RegInit(false.B)\n val decoded_nzp_write_enable = RegInit(false.B)\n val decoded_reg_input_mux = RegInit(RegInputOp.ARITHMETIC)\n val decoded_alu_arithmetic_mux = RegInit(AluOpCode.ADD)\n val decoded_alu_output_mux = RegInit(false.B)\n val decoded_pc_mux = RegInit(false.B)\n val decoded_ret = RegInit(false.B)\n\n when(!reset.asBool) {\n when(io.core_state === CoreState.DECODE) {\n // Get instruction signals from instruction every time\n decoded_rd_address := io.instruction(11, 8)\n decoded_rs_address := io.instruction(7, 4)\n decoded_rt_address := io.instruction(3, 0)\n decoded_immediate := io.instruction(7, 0)\n decoded_nzp := io.instruction(11, 9)\n\n // Control signals reset on every decode and set conditionally by instruction\n decoded_reg_write_enable := false.B\n decoded_mem_read_enable := false.B\n decoded_mem_write_enable := false.B\n decoded_nzp_write_enable := false.B\n decoded_reg_input_mux := RegInputOp.ARITHMETIC\n decoded_alu_arithmetic_mux := AluOpCode.ADD\n decoded_alu_output_mux := false.B\n decoded_pc_mux := false.B\n decoded_ret := false.B\n\n // Set the control signals for each instruction\n val (instruction_opcode, _) = DecoderState.safe(io.instruction(15, 12))\n switch(instruction_opcode) {\n is(DecoderState.NOP) {\n // no-op\n }\n is(DecoderState.BRnzp) {\n decoded_pc_mux := true.B\n }\n is(DecoderState.CMP) {\n decoded_alu_output_mux := true.B\n decoded_nzp_write_enable := true.B\n }\n is(DecoderState.ADD) {\n decoded_reg_write_enable := true.B\n decoded_reg_input_mux := RegInputOp.ARITHMETIC\n decoded_alu_arithmetic_mux := AluOpCode.ADD\n }\n is(DecoderState.SUB) {\n decoded_reg_write_enable := true.B\n decoded_reg_input_mux := RegInputOp.ARITHMETIC\n decoded_alu_arithmetic_mux := AluOpCode.SUB\n }\n is(DecoderState.MUL) {\n decoded_reg_write_enable := true.B\n decoded_reg_input_mux := RegInputOp.ARITHMETIC\n decoded_alu_arithmetic_mux := AluOpCode.MUL\n }\n is(DecoderState.DIV) {\n", "right_context": " decoded_mem_read_enable := true.B\n }\n is(DecoderState.STR) {\n decoded_mem_write_enable := true.B\n }\n is(DecoderState.CONST) {\n decoded_reg_write_enable := true.B\n decoded_reg_input_mux := RegInputOp.CONSTANT\n }\n is(DecoderState.RET) {\n decoded_ret := true.B\n }\n }\n }\n }\n\n io.decoded_reg_address.rd := decoded_rd_address\n io.decoded_reg_address.rs := decoded_rs_address\n io.decoded_reg_address.rt := decoded_rt_address\n io.decoded_nzp := decoded_nzp\n io.decoded_immediate := decoded_immediate\n io.decoded_reg_write_enable := decoded_reg_write_enable\n io.mem_rw_enable.read_enable := decoded_mem_read_enable\n io.mem_rw_enable.write_enable := decoded_mem_write_enable\n io.decoded_nzp_write_enable := decoded_nzp_write_enable\n io.decoded_reg_input_mux := decoded_reg_input_mux\n io.decoded_alu_op.arithmetic_mux := decoded_alu_arithmetic_mux\n io.decoded_alu_op.output_mux := decoded_alu_output_mux\n io.decoded_pc_mux := decoded_pc_mux\n io.decoded_ret := decoded_ret\n}\n", "groundtruth": " decoded_reg_write_enable := true.B\n decoded_reg_input_mux := RegInputOp.ARITHMETIC\n decoded_alu_arithmetic_mux := AluOpCode.DIV\n }\n", "crossfile_context": "", "category": "Interface", "subcategory": "Port Definition", "confidence": 0.5, "category_reason": ":= to io port"} {"task_id": "tiny-gpu-chisel", "path": "tiny-gpu-chisel/playground/src/DecoupledGCD.scala", "left_context": "package gcd\n\nimport chisel3._\nimport chisel3.util.Decoupled\n\nclass GcdInputBundle(val w: Int) extends Bundle {\n val value1 = UInt(w.W)\n val value2 = UInt(w.W)\n}\n\nclass GcdOutputBundle(val w: Int) extends Bundle {\n val value1 = UInt(w.W)\n val value2 = UInt(w.W)\n val gcd = UInt(w.W)\n}\n\n/** Compute Gcd using subtraction method. Subtracts the smaller from the larger until register y is zero. value input\n * register x is then the Gcd. Unless first input is zero then the Gcd is y. Can handle stalls on the producer or\n * consumer side\n */\nclass DecoupledGcd(width: Int) extends Module {\n val input = IO(Flipped(Decoupled(new GcdInputBundle(width))))\n val output = IO(Decoupled(new GcdOutputBundle(width)))\n\n val xInitial = Reg(UInt())\n val yInitial = Reg(UInt())\n val x = Reg(UInt())\n val y = Reg(UInt())\n val busy = RegInit(false.B)\n val resultValid = RegInit(false.B)\n\n input.ready := !busy\n output.valid := resultValid\n output.bits := DontCare\n\n when(busy) {\n when(x > y) {\n", "right_context": " when(x === 0.U) {\n output.bits.gcd := y\n }.otherwise {\n output.bits.gcd := x\n }\n\n output.bits.value1 := xInitial\n output.bits.value2 := yInitial\n resultValid := true.B\n\n when(output.ready && resultValid) {\n busy := false.B\n resultValid := false.B\n }\n }\n }.otherwise {\n when(input.valid) {\n val bundle = input.deq()\n x := bundle.value1\n y := bundle.value2\n xInitial := bundle.value1\n yInitial := bundle.value2\n busy := true.B\n }\n }\n}\n", "groundtruth": " x := x - y\n }.otherwise {\n y := y - x\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.8, "category_reason": ".otherwise clause"} {"task_id": "tiny-gpu-chisel", "path": "tiny-gpu-chisel/playground/src/DeviceControlRegister.scala", "left_context": "package dcr\n\nimport chisel3._\nimport chisel3.util._\n\n// > Used to configure high-level settings\n// > In this minimal example, the DCR is used to configure the number of threads to run for the kernel\nclass DeviceControlRegister extends Module {\n val io = IO(new Bundle {\n val device_control_write_enable = Input(Bool())\n val device_control_data = Input(UInt(8.W))\n val thread_count = Output(UInt(8.W))\n })\n\n // Store device control data in dedicated register\n val device_control_register = RegInit(0.U(8.W))\n\n", "right_context": "}\n", "groundtruth": " when(!reset.asBool && io.device_control_write_enable) {\n device_control_register := io.device_control_data\n }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "tiny-gpu-chisel", "path": "tiny-gpu-chisel/playground/src/Dispatch.scala", "left_context": "package dispatch\n\nimport chisel3._\nimport chisel3.util._\nimport org.apache.commons.lang3.ThreadUtils.ThreadPredicate\n\nclass Dispatch(NumCores: Int = 2, ThreadsPerCore: Int = 4) extends Module {\n val ThreadCountWidth = log2Ceil(ThreadsPerCore) + 1\n val io = IO(new Bundle {\n val start = Input(Bool())\n\n // Kernel Metadata\n val thread_count = Input(UInt(8.W))\n\n // Core States\n val core_done = Input(Vec(NumCores, Bool()))\n val core_start = Output(Vec(NumCores, Bool()))\n val core_reset = Output(Vec(NumCores, Bool()))\n val core_block_id = Output(Vec(NumCores, UInt(8.W)))\n val core_thread_count = Output(Vec(NumCores, UInt(ThreadCountWidth.W)))\n\n // Kernel Execution\n val done = Output(Bool())\n })\n\n printf(cf\"Dispatch: start = ${io.start}, thread_count = ${io.thread_count}, core_done = ${io.core_done}\\n\")\n\n // Calculate the total number of blocks based on total threads & threads per block\n val total_blocks = (io.thread_count + ThreadsPerCore.U - 1.U) / ThreadsPerCore.U\n\n val done = RegInit(false.B)\n val blocks_dispatched = RegInit(0.U(8.W))\n val blocks_done = RegInit(0.U(8.W))\n val start_execution = RegInit(false.B)\n val core_start = RegInit(VecInit(Seq.fill(NumCores)(false.B)))\n val core_reset = RegInit(VecInit(Seq.fill(NumCores)(true.B)))\n val core_block_id = RegInit(VecInit(Seq.fill(NumCores)(0.U(8.W))))\n val core_thread_count = RegInit(VecInit(Seq.fill(NumCores)(ThreadsPerCore.U(ThreadCountWidth.W))))\n\n printf(\n", "right_context": " )\n\n // printf(cf\"--total_blocks = $total_blocks, thread_count = ${io.thread_count}, blocks_done = $blocks_done\\n\")\n\n // Keep track of how many blocks have been processed\n when(!reset.asBool && io.start) {\n when(!start_execution) {\n start_execution := true.B\n core_reset.foreach(_ := true.B)\n }\n\n // If the last block has finished processing, mark this kernel as done executing\n when(blocks_done === total_blocks) {\n done := true.B\n }\n\n for (i <- 0 until NumCores) {\n when(core_reset(i)) {\n core_reset(i) := false.B\n\n // If this core was just reset, check if there are more blocks to be dispatched\n when(blocks_dispatched < total_blocks) {\n // printf(cf\"--i = $i, blocks_dispatched = $blocks_dispatched, total_blocks = $total_blocks\\n\")\n core_start(i) := true.B\n core_block_id(i) := blocks_dispatched\n core_thread_count(i) := Mux(\n blocks_dispatched === total_blocks - 1.U,\n io.thread_count - (blocks_dispatched * ThreadsPerCore.U),\n ThreadsPerCore.U\n )\n blocks_dispatched := blocks_dispatched + 1.U\n }\n }\n\n // printf(cf\"--core_start(i) = ${core_start(i)}, io.core_done(i) = ${io.core_done(i)}\\n\")\n when(core_start(i) && io.core_done(i)) {\n // If a core just finished executing it's current block, reset it\n core_reset(i) := true.B\n core_start(i) := false.B\n blocks_done := blocks_done + 1.U\n }\n }\n }\n\n io.core_start := core_start\n io.core_reset := core_reset\n io.core_block_id := core_block_id\n io.core_thread_count := core_thread_count\n io.done := done\n}\n", "groundtruth": " cf\"Dispatch outputs: core_start=${core_start}, core_reset=${core_reset}, core_block_id=${core_block_id}, core_thread_count=${core_thread_count}, done=${done}\\n\"\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.55, "category_reason": "Code near when block"} {"task_id": "tiny-gpu-chisel", "path": "tiny-gpu-chisel/playground/src/Elaborate.scala", "left_context": "object Elaborate extends App {\n val firtoolOptions = Array(\n \"--lowering-options=\" + List(\n // make yosys happy\n // see https://github.com/llvm/circt/blob/main/docs/VerilogGeneration.md\n \"disallowLocalVariables\",\n \"disallowPackedArrays\",\n \"locationInfoStyle=wrapInAtSquareBracket\"\n ).reduce(_ + \",\" + _)\n )\n circt.stage.ChiselStage.emitSystemVerilogFile(new gcd.GCD(), args, firtoolOptions)\n circt.stage.ChiselStage.emitSystemVerilogFile(new alu.Alu(), args, firtoolOptions)\n circt.stage.ChiselStage.emitSystemVerilogFile(new pc.ProgramCounter, args, firtoolOptions)\n circt.stage.ChiselStage.emitSystemVerilogFile(new lsu.MemLoadStoreUnit(), args, firtoolOptions)\n circt.stage.ChiselStage.emitSystemVerilogFile(new registers.RegisterFiles(), args, firtoolOptions)\n circt.stage.ChiselStage.emitSystemVerilogFile(new scheduler.Scheduler(), args, firtoolOptions)\n circt.stage.ChiselStage.emitSystemVerilogFile(new fetcher.Fetcher(), args, firtoolOptions)\n circt.stage.ChiselStage.emitSystemVerilogFile(new decoder.Decoder(), args, firtoolOptions)\n circt.stage.ChiselStage.emitSystemVerilogFile(new core.Core(), args, firtoolOptions)\n circt.stage.ChiselStage.emitSystemVerilogFile(new dispatch.Dispatch(), args, firtoolOptions)\n", "right_context": "", "groundtruth": " circt.stage.ChiselStage.emitSystemVerilogFile(new dcr.DeviceControlRegister(), args, firtoolOptions)\n circt.stage.ChiselStage.emitSystemVerilogFile(new controller.Controller(), args, firtoolOptions)\n circt.stage.ChiselStage.emitSystemVerilogFile(new gpu.Gpu(), args, firtoolOptions)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "tiny-gpu-chisel", "path": "tiny-gpu-chisel/playground/src/Fetcher.scala", "left_context": "package fetcher\n\nimport chisel3._\nimport chisel3.util._\n\nimport statecode.CoreState\nimport statecode.FetcherState\n\nclass Fetcher(ProgramMemAddrBits: Int = 8, ProgramMemDataBits: Int = 16) extends Module {\n val io = IO(new Bundle {\n // Execution State\n val core_state = Input(CoreState())\n val current_pc = Input(UInt(8.W))\n\n // Program Memory\n val mem_read_address_sender = new DecoupledIO(UInt(ProgramMemAddrBits.W))\n val mem_read_data = Input(UInt(ProgramMemDataBits.W))\n\n val fetcher_state = Output(FetcherState())\n val instruction = Output(UInt(ProgramMemDataBits.W))\n })\n\n val fetcher_state = RegInit(FetcherState.IDLE)\n val mem_read_valid = RegInit(false.B)\n val mem_read_address = RegInit(0.U(ProgramMemAddrBits.W))\n val instruction = RegInit(0.U(ProgramMemDataBits.W))\n\n when(!reset.asBool) {\n switch(fetcher_state) {\n is(FetcherState.IDLE) {\n when(io.core_state === CoreState.FETCH) {\n fetcher_state := FetcherState.FETCHING\n mem_read_valid := true.B\n mem_read_address := io.current_pc\n }\n }\n is(FetcherState.FETCHING) {\n when(io.mem_read_address_sender.ready) {\n fetcher_state := FetcherState.FETCHED\n instruction := io.mem_read_data\n mem_read_valid := false.B\n }\n }\n is(FetcherState.FETCHED) {\n", "right_context": " }\n\n io.fetcher_state := fetcher_state\n io.mem_read_address_sender.valid := mem_read_valid\n io.mem_read_address_sender.bits := mem_read_address\n io.instruction := instruction\n}\n", "groundtruth": " when(io.core_state === CoreState.DECODE) {\n fetcher_state := FetcherState.IDLE\n }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "tiny-gpu-chisel", "path": "tiny-gpu-chisel/playground/src/GCD.scala", "left_context": "package gcd\n\nimport chisel3._\n\n/** Compute GCD using subtraction method. Subtracts the smaller from the larger until register y is zero. value in\n * register x is then the GCD\n */\nclass GCD extends Module {\n val io = IO(new Bundle {\n val value1 = Input(UInt(16.W))\n val value2 = Input(UInt(16.W))\n val loadingValues = Input(Bool())\n val outputGCD = Output(UInt(16.W))\n val outputValid = Output(Bool())\n })\n\n val x = Reg(UInt())\n val y = Reg(UInt())\n\n", "right_context": "\n when(io.loadingValues) {\n x := io.value1\n y := io.value2\n }\n\n io.outputGCD := x\n io.outputValid := y === 0.U\n}\n", "groundtruth": " when(x > y) { x := x - y }.otherwise { y := y - x }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "tiny-gpu-chisel", "path": "tiny-gpu-chisel/playground/src/MemLoadStoreUnit.scala", "left_context": "package lsu\n\nimport chisel3._\nimport chisel3.util._\nimport statecode.CoreState\nimport statecode.LSUState\n\nclass MemLoadStoreUnit extends Module {\n val io = IO(new Bundle {\n val enable = Input(Bool())\n\n val core_state = Input(CoreState())\n\n // Decoder outputs\n val mem_rw_enable = new Bundle {\n val read_enable = Input(Bool()) // Enable reading from memory\n val write_enable = Input(Bool()) // Enable writing to memory\n }\n\n // Registers\n val reg_in = new Bundle {\n val rs = Input(UInt(8.W))\n val rt = Input(UInt(8.W))\n }\n\n val mem_read_data = Input(UInt(8.W))\n val mem_read_address_sender = new DecoupledIO(UInt(8.W))\n\n val mem_write_sender = DecoupledIO(new Bundle {\n val address = UInt(8.W)\n val data = UInt(8.W)\n })\n\n // LSU Outputs\n val lsu_state = Output(LSUState())\n val lsu_out = Output(UInt(8.W))\n })\n\n val lsu_state = RegInit(LSUState.IDLE)\n val lsu_out = RegInit(0.U(8.W))\n val mem_read_valid = RegInit(false.B)\n val mem_read_address = RegInit(0.U(8.W))\n val mem_write_valid = RegInit(false.B)\n val mem_write_address = RegInit(0.U(8.W))\n val mem_write_data = RegInit(0.U(8.W))\n\n when(io.enable) {\n // If memory read enable is triggered (LDR instruction)\n when(io.mem_rw_enable.read_enable) {\n switch(io.lsu_state) {\n is(LSUState.IDLE) {\n when(io.core_state === CoreState.REQUEST) {\n lsu_state := LSUState.REQUESTING\n }\n }\n is(LSUState.REQUESTING) {\n mem_read_valid := true.B\n mem_read_address := io.reg_in.rs\n lsu_state := LSUState.WAITING\n }\n is(LSUState.WAITING) {\n when(io.mem_read_address_sender.ready) {\n mem_read_valid := false.B\n lsu_out := io.mem_read_data\n lsu_state := LSUState.DONE\n }\n }\n is(LSUState.DONE) {\n when(io.core_state === CoreState.UPDATE) {\n lsu_state := LSUState.IDLE\n }\n }\n }\n }\n\n // If memory write enable is triggered (STR instruction)\n when(io.mem_rw_enable.write_enable) {\n switch(io.lsu_state) {\n is(LSUState.IDLE) {\n when(io.core_state === CoreState.REQUEST) {\n lsu_state := LSUState.REQUESTING\n }\n }\n is(LSUState.REQUESTING) {\n mem_write_valid := true.B\n mem_write_address := io.reg_in.rs\n mem_write_data := io.reg_in.rt\n lsu_state := LSUState.WAITING\n }\n is(LSUState.WAITING) {\n when(io.mem_write_sender.ready) {\n mem_write_valid := false.B\n lsu_state := LSUState.DONE\n }\n }\n is(LSUState.DONE) {\n", "right_context": " }\n }\n\n io.lsu_state := lsu_state\n io.lsu_out := lsu_out\n io.mem_read_address_sender.valid := mem_read_valid\n io.mem_read_address_sender.bits := mem_read_address\n io.mem_write_sender.valid := mem_write_valid\n io.mem_write_sender.bits.address := mem_write_address\n io.mem_write_sender.bits.data := mem_write_data\n}\n", "groundtruth": " when(io.core_state === CoreState.UPDATE) {\n lsu_state := LSUState.IDLE\n }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "tiny-gpu-chisel", "path": "tiny-gpu-chisel/playground/src/ProgramCounter.scala", "left_context": "package pc\n\nimport chisel3._\nimport chisel3.util._\nimport statecode.CoreState\nimport scala.reflect.internal.Reporter.INFO\n// PROGRAM COUNTER\n// > Calculates the next PC for each thread to update to (but currently we assume all threads\n// update to the same PC and don't support branch divergence)\n// > Currently, each thread in each core has it's own calculation for next PC\n// > The NZP register value is set by the CMP instruction (based on >/=/< comparison) to\n// initiate the BRnzp instruction for branching\nclass ProgramCounter(DataMemWidth: Int = 8, MemAddrWidth: Int = 8) extends Module {\n val io = IO(new Bundle {\n val enable = Input(Bool())\n\n val core_state = Input(CoreState())\n\n val decoded_nzp = Input(UInt(2.W))\n val decoded_immediate = Input(UInt(DataMemWidth.W))\n val decoded_nzp_write_enable = Input(Bool())\n val decoded_pc_mux = Input(Bool())\n\n val alu_out = Input(UInt(DataMemWidth.W))\n\n val current_pc = Input(UInt(MemAddrWidth.W))\n val next_pc = Output(UInt(MemAddrWidth.W))\n })\n\n val nzp = RegInit(0.U(2.W))\n val next_pc = RegInit(0.U(MemAddrWidth.W))\n\n when(io.enable) {\n when(io.core_state === CoreState.EXECUTE) {\n when(io.decoded_pc_mux) {\n when((nzp & io.decoded_nzp) =/= 0.U) {\n // On BRnzp instruction, branch to immediate if NZP case matches previous CMP\n next_pc := io.decoded_immediate\n }.otherwise {\n // Otherwise, just update to PC + 1 (next line)\n next_pc := io.current_pc + 1.U\n }\n }.otherwise {\n // By default update to PC + 1 (next line)\n next_pc := io.current_pc + 1.U\n }\n }\n\n // Store NZP when core_state = UPDATE\n", "right_context": " }.otherwise {\n io.next_pc := next_pc\n }\n}\n", "groundtruth": " when(io.core_state === CoreState.UPDATE) {\n when(io.decoded_nzp_write_enable) {\n nzp := io.alu_out(2, 0)\n }\n }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "tiny-gpu-chisel", "path": "tiny-gpu-chisel/playground/src/RegisterFiles.scala", "left_context": "package registers\n\nimport chisel3._\nimport chisel3.util._\nimport statecode.CoreState\nimport statecode.RegInputOp\n\nclass RegisterFiles(ThreadsPerBlk: Int = 4, ThreadId: Int = 0, DataBits: Int = 8) extends Module {\n val io = IO(new Bundle {\n val enable = Input(Bool())\n\n // Kernel Execution\n val block_id = Input(UInt(8.W))\n\n // State\n val core_state = Input(CoreState())\n\n // Instruction Signals\n val decoded_reg_address = new Bundle {\n val rd = Input(UInt(4.W))\n val rs = Input(UInt(4.W))\n val rt = Input(UInt(4.W))\n }\n\n // Control Signals\n val decoded_reg_write_enable = Input(Bool())\n val decoded_reg_input_mux = Input(RegInputOp())\n val decoded_immediate = Input(UInt(DataBits.W))\n\n // Thread Unit Outputs\n val alu_out = Input(UInt(DataBits.W))\n val lsu_out = Input(UInt(DataBits.W))\n\n // Register File Outputs\n val reg_out = new Bundle {\n val rs = Output(UInt(DataBits.W))\n val rt = Output(UInt(DataBits.W))\n }\n })\n\n def InitValByIndex(index: Int): UInt = {\n index match {\n case 14 => ThreadsPerBlk.U\n case 15 => ThreadId.U\n case _ => 0.U(8.W)\n }\n }\n\n val registers = RegInit(VecInit(Seq.tabulate(16)(i => InitValByIndex(i))))\n\n val rs = RegInit(0.U(DataBits.W))\n val rt = RegInit(0.U(DataBits.W))\n\n when(!reset.asBool && io.enable) {\n // [Bad Solution] Shouldn't need to set this every cycle\n // Update the block_id when a new block is issued from dispatcher\n registers(13) := io.block_id\n\n // Fill rs/rt when core_state = REQUEST\n when(io.core_state === CoreState.REQUEST) {\n rs := registers(io.decoded_reg_address.rs)\n rt := registers(io.decoded_reg_address.rt)\n }.elsewhen(io.core_state === CoreState.UPDATE) { // Store rd when core_state = UPDATE\n // Only allow writing to R0 - R12\n when(io.decoded_reg_write_enable && io.decoded_reg_address.rd < 13.U) {\n switch(io.decoded_reg_input_mux) {\n is(RegInputOp.ARITHMETIC) {\n registers(io.decoded_reg_address.rd) := io.alu_out\n", "right_context": " }\n }\n\n // printf(\n // \"registers: [%d%d%d%d%d%d%d%d%d%d%d%d%d]\\n\",\n // registers(0),\n // registers(1),\n // registers(2),\n // registers(3),\n // registers(4),\n // registers(5),\n // registers(6),\n // registers(7),\n // registers(8),\n // registers(9),\n // registers(10),\n // registers(11),\n // registers(12)\n // )\n\n io.reg_out.rs := rs\n io.reg_out.rt := rt\n}\n", "groundtruth": " }\n is(RegInputOp.MEMORY) {\n registers(io.decoded_reg_address.rd) := io.lsu_out\n }\n is(RegInputOp.CONSTANT) {\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.75, "category_reason": "is() in switch context"} {"task_id": "tiny-gpu-chisel", "path": "tiny-gpu-chisel/playground/src/Scheduler.scala", "left_context": "package scheduler\n\nimport chisel3._\nimport chisel3.util._\nimport statecode.CoreState\nimport statecode.LSUState\nimport statecode.FetcherState\n\n// SCHEDULER\n// > Manages the entire control flow of a single compute core processing 1 block\n// 1. FETCH - Retrieve instruction at current program counter (PC) from program memory\n// 2. DECODE - Decode the instruction into the relevant control signals\n// 3. REQUEST - If we have an instruction that accesses memory, trigger the async memory requests from LSUs\n// 4. WAIT - Wait for all async memory requests to resolve (if applicable)\n// 5. EXECUTE - Execute computations on retrieved data from registers / memory\n// 6. UPDATE - Update register values (including NZP register) and program counter\n// > Each core has it's own scheduler where multiple threads can be processed with\n// the same control flow at once.\n// > Technically, different instructions can branch to different PCs, requiring \"branch divergence.\" In\n// this minimal implementation, we assume no branch divergence (naive approach for simplicity)\nclass Scheduler(ThreadsPerBlock: Int = 4) extends Module {\n val io = IO(new Bundle {\n val start = Input(Bool())\n\n // Control signals\n val mem_rw_enable = new Bundle {\n val read_enable = Input(Bool()) // Enable reading from memory\n val write_enable = Input(Bool()) // Enable writing to memory\n }\n val decoded_ret = Input(Bool())\n\n // Memory access state\n val fetcher_state = Input(FetcherState())\n val lsu_state = Input(Vec(ThreadsPerBlock, LSUState()))\n\n // Current & Next PC\n val current_pc = Output(UInt(8.W))\n val next_pc = Input(Vec(ThreadsPerBlock, UInt(8.W)))\n\n // Execution state\n val core_state = Output(CoreState())\n val done = Output(Bool())\n })\n\n val current_pc = RegInit(0.U(8.W))\n val core_state = RegInit(CoreState.IDLE)\n val done = RegInit(false.B)\n\n when(!reset.asBool) {\n switch(core_state) {\n is(CoreState.IDLE) {\n // Here after reset (before kernel is launched, or after previous block has been processed)\n when(io.start) {\n core_state := CoreState.FETCH\n }\n }\n\n is(CoreState.FETCH) {\n // Move on once fetcher_state = FETCHED\n", "right_context": " is(CoreState.DECODE) {\n // Decode is synchronous so we move on after one cycle\n core_state := CoreState.REQUEST\n }\n\n is(CoreState.REQUEST) {\n // Request is synchronous so we move on after one cycle\n core_state := CoreState.WAIT\n }\n\n is(CoreState.WAIT) {\n // Wait for all LSUs to finish their request before continuing\n // Make sure no lsu_state = REQUESTING or WAITING\n val any_lsu_waiting =\n io.lsu_state.exists(lsu_state => lsu_state === LSUState.WAITING || lsu_state === LSUState.REQUESTING)\n\n // If no LSU is waiting for a response, move onto the next stage\n when(!any_lsu_waiting) {\n core_state := CoreState.EXECUTE\n }\n }\n\n is(CoreState.EXECUTE) {\n // Execute is synchronous so we move on after one cycle\n core_state := CoreState.UPDATE\n }\n\n is(CoreState.UPDATE) {\n when(io.decoded_ret) {\n // If we reach a RET instruction, this block is done executing\n done := true.B\n core_state := CoreState.DONE\n }.otherwise {\n // TODO: Branch divergence. For now assume all next_pc converge\n current_pc := io.next_pc((ThreadsPerBlock - 1).U)\n core_state := CoreState.FETCH\n }\n }\n\n is(CoreState.DONE) {\n // no-op\n }\n }\n }\n\n io.current_pc := current_pc\n io.core_state := core_state\n io.done := done\n}\n", "groundtruth": " when(io.fetcher_state === FetcherState.FETCHED) {\n core_state := CoreState.DECODE\n }\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.85, "category_reason": "when conditional"} {"task_id": "tiny-gpu-chisel", "path": "tiny-gpu-chisel/playground/src/StateCode.scala", "left_context": "package statecode\n\nimport chisel3._\n\nobject CoreState extends ChiselEnum {\n val IDLE = Value(\"b000\".U)\n val FETCH = Value(\"b001\".U)\n val DECODE = Value(\"b010\".U)\n val REQUEST = Value(\"b011\".U)\n val WAIT = Value(\"b100\".U)\n val EXECUTE = Value(\"b101\".U)\n val UPDATE = Value(\"b110\".U)\n val DONE = Value(\"b111\".U)\n}\n\nobject AluOpCode extends ChiselEnum {\n val ADD, SUB, MUL, DIV = Value\n}\n\n", "right_context": " val CMP = Value(\"b0010\".U)\n val ADD = Value(\"b0011\".U)\n val SUB = Value(\"b0100\".U)\n val MUL = Value(\"b0101\".U)\n val DIV = Value(\"b0110\".U)\n val LDR = Value(\"b0111\".U)\n val STR = Value(\"b1000\".U)\n val CONST = Value(\"b1001\".U)\n val RET = Value(\"b1111\".U)\n}\n\nobject ControlState extends ChiselEnum {\n val IDLE = Value(\"b000\".U)\n val READ_WAITING = Value(\"b010\".U)\n val WRITE_WAITING = Value(\"b011\".U)\n val READ_RELAYING = Value(\"b100\".U)\n val WRITE_RELAYING = Value(\"b101\".U)\n}\n\nobject FetcherState extends ChiselEnum {\n val IDLE = Value(\"b000\".U)\n val FETCHING = Value(\"b001\".U)\n val FETCHED = Value(\"b010\".U)\n}\n\nobject LSUState extends ChiselEnum {\n val IDLE, REQUESTING, WAITING, DONE = Value\n}\n", "groundtruth": "object RegInputOp extends ChiselEnum {\n val ARITHMETIC = Value(\"b00\".U)\n val MEMORY = Value(\"b01\".U)\n val CONSTANT = Value(\"b10\".U)\n}\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Type Definition", "confidence": 0.8, "category_reason": "ChiselEnum"} {"task_id": "tiny-gpu-chisel", "path": "tiny-gpu-chisel/playground/test/src/AluSpec.scala", "left_context": "package alu\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.BundleLiterals._\nimport chisel3.simulator.EphemeralSimulator._\nimport org.scalatest.freespec.AnyFreeSpec\nimport org.scalatest.matchers.must.Matchers\n\nimport statecode.AluOpCode\nimport statecode.CoreState\n\nclass AluModel {\n var alu_out = 0\n\n def update(\n enable: Boolean,\n core_state: CoreState.Type,\n rs: Int,\n rt: Int,\n arithmetic_mux: AluOpCode.Type,\n output_mux: Boolean\n ): Unit = {\n if (enable && core_state == CoreState.EXECUTE) {\n if (output_mux) {\n // Compare operation\n", "right_context": " val eq = if (rs == rt) 1 else 0\n val lt = if (rs < rt) 1 else 0\n alu_out = (gt << 2) | (eq << 1) | lt\n } else {\n // Arithmetic operation\n alu_out = arithmetic_mux match {\n case AluOpCode.ADD => (rs + rt) & 0xff\n case AluOpCode.SUB => ((rs - rt) + 256) & 0xff\n case AluOpCode.MUL => (rs * rt) & 0xff\n case AluOpCode.DIV => if (rt == 0) 0 else rs / rt\n }\n }\n }\n }\n\n def reset(): Unit = {\n alu_out = 0\n }\n}\n\nclass AluSpec extends AnyFreeSpec with Matchers {\n \"Test ALU for all supported operations\" in {\n simulate(new Alu) { dut =>\n def cmpResult(rs: Int, rt: Int): Int = {\n val gt = if (rs > rt) 1 else 0\n val eq = if (rs == rt) 1 else 0\n val lt = if (rs < rt) 1 else 0\n (gt << 2) | (eq << 1) | lt\n }\n\n // Calculate expected result based on operation\n def arithmeticResult(rs: Int, rt: Int, op: AluOpCode.Type): Int = {\n op match {\n case AluOpCode.ADD => (rs + rt) & 0xff\n case AluOpCode.SUB => ((rs - rt) + 256) & 0xff\n case AluOpCode.MUL => (rs * rt) & 0xff\n case AluOpCode.DIV => if (rt == 0) 0 else rs / rt\n }\n }\n\n val testValues = for {\n rs <- 0 to 255\n rt <- 0 to 255\n op <- List(AluOpCode.ADD, AluOpCode.SUB, AluOpCode.MUL, AluOpCode.DIV)\n core_state <- List(CoreState.IDLE, CoreState.EXECUTE)\n is_cmp <- List(true, false)\n } yield (rs, rt, op, core_state, is_cmp)\n\n dut.reset.poke(true.B)\n dut.clock.step()\n dut.reset.poke(false.B)\n dut.clock.step()\n\n var aluModel = new AluModel()\n // Test each combination\n for ((rs, rt, op, core_state, is_cmp) <- testValues) {\n // Set inputs\n dut.io.enable.poke(true.B)\n dut.io.core_state.poke(core_state)\n dut.io.decoded_alu_op.arithmetic_mux.poke(op)\n dut.io.decoded_alu_op.output_mux.poke(is_cmp)\n dut.io.reg_in.rs.poke(rs.U)\n dut.io.reg_in.rt.poke(rt.U)\n\n dut.clock.step()\n\n aluModel.update(\n enable = true,\n core_state = core_state,\n rs = rs,\n rt = rt,\n arithmetic_mux = op,\n output_mux = is_cmp\n )\n // Verify output\n dut.io.alu_out.expect(aluModel.alu_out.U)\n }\n }\n }\n}\n", "groundtruth": " val gt = if (rs > rt) 1 else 0\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.6, "category_reason": "val binding"} {"task_id": "tiny-gpu-chisel", "path": "tiny-gpu-chisel/playground/test/src/ControllerSpec.scala", "left_context": "package controller\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.BundleLiterals._\nimport chisel3.simulator.EphemeralSimulator._\nimport org.scalatest.freespec.AnyFreeSpec\nimport org.scalatest.matchers.must.Matchers\n\nimport statecode.ControlState\n\nclass ControllerModel(AddrBits: Int = 8, DataBits: Int = 16, NumConsumers: Int = 4, NumChannels: Int = 1) {\n var controller_state = Array.fill(NumChannels)(ControlState.IDLE)\n var mem_read_valid = Array.fill(NumChannels)(false)\n var mem_read_address = Array.fill(NumChannels)(0)\n var mem_write_valid = Array.fill(NumChannels)(false)\n var mem_write_address = Array.fill(NumChannels)(0)\n var mem_write_data = Array.fill(NumChannels)(0)\n var consumer_read_ready = Array.fill(NumConsumers)(false)\n var consumer_read_data = Array.fill(NumConsumers)(0)\n var consumer_write_ready = Array.fill(NumConsumers)(false)\n var channel_serving_consumer = Array.fill(NumConsumers)(false)\n var current_consumer = Array.fill(NumChannels)(0)\n\n def update(\n consumer_read_valid: Array[Boolean],\n consumer_read_addr: Array[Int],\n consumer_write_valid: Array[Boolean],\n consumer_write_addr: Array[Int],\n consumer_write_data: Array[Int],\n mem_read_ready: Array[Boolean],\n mem_read_data: Array[Int],\n mem_write_ready: Array[Boolean]\n ): Unit = {\n // Update model state for each channel\n for (i <- 0 until NumChannels) {\n controller_state(i) match {\n case ControlState.IDLE =>\n // Follow the original verilog implementation\n var break = false\n var j = 0\n while (j < NumConsumers && !break) {\n if (consumer_read_valid(j) && !channel_serving_consumer(j)) {\n channel_serving_consumer(j) = true\n current_consumer(i) = j\n mem_read_valid(i) = true\n mem_read_address(i) = consumer_read_addr(j)\n controller_state(i) = ControlState.READ_WAITING\n break = true\n } else if (consumer_write_valid(j) && !channel_serving_consumer(j)) {\n channel_serving_consumer(j) = true\n current_consumer(i) = j\n mem_write_valid(i) = true\n mem_write_address(i) = consumer_write_addr(j)\n mem_write_data(i) = consumer_write_data(j)\n controller_state(i) = ControlState.WRITE_WAITING\n break = true\n }\n j += 1\n }\n\n case ControlState.READ_WAITING =>\n if (mem_read_ready(i)) {\n mem_read_valid(i) = false\n consumer_read_ready(current_consumer(i)) = true\n consumer_read_data(current_consumer(i)) = mem_read_data(i)\n controller_state(i) = ControlState.READ_RELAYING\n }\n\n case ControlState.WRITE_WAITING =>\n", "right_context": " mem_write_valid(i) = false\n consumer_write_ready(current_consumer(i)) = true\n controller_state(i) = ControlState.WRITE_RELAYING\n }\n\n case ControlState.READ_RELAYING =>\n if (!consumer_read_valid(current_consumer(i))) {\n channel_serving_consumer(current_consumer(i)) = false\n consumer_read_ready(current_consumer(i)) = false\n controller_state(i) = ControlState.IDLE\n }\n\n case ControlState.WRITE_RELAYING =>\n if (!consumer_write_valid(current_consumer(i))) {\n channel_serving_consumer(current_consumer(i)) = false\n consumer_write_ready(current_consumer(i)) = false\n controller_state(i) = ControlState.IDLE\n }\n }\n }\n\n // // Debug printing\n // println(\"=== Model Internal State ===\")\n // println(s\"-controller_state: ${controller_state.mkString(\", \")}\")\n // println(s\"-mem_read_valid: ${mem_read_valid.mkString(\", \")}\")\n // println(s\"-mem_read_address: ${mem_read_address.mkString(\", \")}\")\n // println(s\"-mem_write_valid: ${mem_write_valid.mkString(\", \")}\")\n // println(s\"-mem_write_address: ${mem_write_address.mkString(\", \")}\")\n // println(s\"-mem_write_data: ${mem_write_data.mkString(\", \")}\")\n // println(s\"-consumer_read_ready: ${consumer_read_ready.mkString(\", \")}\")\n // println(s\"-consumer_read_data: ${consumer_read_data.mkString(\", \")}\")\n // println(s\"-consumer_write_ready: ${consumer_write_ready.mkString(\", \")}\")\n // println(s\"-channel_serving_consumer: ${channel_serving_consumer.mkString(\", \")}\")\n // println(s\"-current_consumer: ${current_consumer.mkString(\", \")}\")\n // println(\"==================\\n\")\n }\n\n // def reset(): Unit = {\n // controller_state = Array.fill(3)(ControlState.IDLE)\n // mem_read_valid = Array.fill(1)(false)\n // mem_read_address = Array.fill(1)(0)\n // mem_write_valid = Array.fill(1)(false)\n // mem_write_address = Array.fill(1)(0)\n // mem_write_data = Array.fill(1)(0)\n // consumer_read_ready = Array.fill(4)(false)\n // consumer_read_data = Array.fill(4)(0)\n // consumer_write_ready = Array.fill(4)(false)\n // channel_serving_consumer = Array.fill(4)(false)\n // current_consumer = Array.fill(1)(0)\n // }\n}\n\nclass ControllerSpec extends AnyFreeSpec with Matchers {\n \"Test controller\" - {\n \"should match model behavior with random inputs\" in {\n val AddrBits = 8\n val DataBits = 16\n val NumConsumers = 4\n val NumChannels = 1\n\n simulate(new Controller(AddrBits, DataBits, NumConsumers, NumChannels)) { dut =>\n dut.reset.poke(true.B)\n dut.clock.step()\n dut.reset.poke(false.B)\n dut.clock.step()\n\n var cnt = 0\n val rng = new scala.util.Random(42)\n val controllerModel = new ControllerModel()\n\n while (cnt < 10000) {\n // Generate random inputs\n val consumer_read_valid = Array.fill(NumConsumers)(rng.nextBoolean())\n val consumer_read_addr = Array.fill(NumConsumers)(rng.nextInt(AddrBits))\n val consumer_write_valid = Array.fill(NumConsumers)(rng.nextBoolean())\n val consumer_write_addr = Array.fill(NumConsumers)(rng.nextInt(AddrBits))\n val consumer_write_data = Array.fill(NumConsumers)(rng.nextInt(DataBits))\n val mem_read_ready = Array.fill(NumChannels)(rng.nextBoolean())\n val mem_read_data = Array.fill(NumChannels)(rng.nextInt(DataBits))\n val mem_write_ready = Array.fill(NumChannels)(rng.nextBoolean())\n\n // Apply inputs to DUT\n for (i <- 0 until NumConsumers) {\n dut.io.consumer_read_addr_receiver(i).valid.poke(consumer_read_valid(i).B)\n dut.io.consumer_read_addr_receiver(i).bits.poke(consumer_read_addr(i).U)\n // dut.io.consumer_write_receiver(i).valid.poke(consumer_write_valid(i).B)\n // dut.io.consumer_write_receiver(i).bits.address.poke(consumer_write_addr(i).U)\n // dut.io.consumer_write_receiver(i).bits.data.poke(consumer_write_data(i).U)\n dut.io.consumer_write_receiver.map(receiver => {\n receiver(i).valid.poke(consumer_write_valid(i).B)\n receiver(i).bits.address.poke(consumer_write_addr(i).U)\n receiver(i).bits.data.poke(consumer_write_data(i).U)\n })\n }\n\n for (i <- 0 until NumChannels) {\n dut.io.mem_read_sender(i).ready.poke(mem_read_ready(i).B)\n dut.io.mem_read_data(i).poke(mem_read_data(i).U)\n // dut.io.mem_write_sender(i).ready.poke(mem_write_ready(i).B)\n dut.io.mem_write_sender.map(_.apply(i).ready.poke(mem_write_ready(i).B))\n }\n\n dut.clock.step()\n\n // println(\"\\n\\n=== Input Signals ===\")\n // println(s\"consumer_read_valid: ${consumer_read_valid.mkString(\", \")}\")\n // println(s\"consumer_read_addr: ${consumer_read_addr.mkString(\", \")}\")\n // println(s\"consumer_write_valid: ${consumer_write_valid.mkString(\", \")}\")\n // println(s\"consumer_write_addr: ${consumer_write_addr.mkString(\", \")}\")\n // println(s\"consumer_write_data: ${consumer_write_data.mkString(\", \")}\")\n // println(s\"mem_read_ready: ${mem_read_ready.mkString(\", \")}\")\n // println(s\"mem_read_data: ${mem_read_data.mkString(\", \")}\")\n // println(s\"mem_write_ready: ${mem_write_ready.mkString(\", \")}\")\n\n // Update model\n controllerModel.update(\n consumer_read_valid,\n consumer_read_addr,\n consumer_write_valid,\n consumer_write_addr,\n consumer_write_data,\n mem_read_ready,\n mem_read_data,\n mem_write_ready\n )\n\n // Compare model with DUT\n for (i <- 0 until NumConsumers) {\n dut.io.consumer_read_addr_receiver(i).ready.expect(controllerModel.consumer_read_ready(i).B)\n dut.io.consumer_read_data(i).expect(controllerModel.consumer_read_data(i).U)\n // dut.io.consumer_write_receiver(i).ready.expect(controllerModel.consumer_write_ready(i).B)\n dut.io.consumer_write_receiver.map(_.apply(i).ready.expect(controllerModel.consumer_write_ready(i).B))\n }\n\n for (i <- 0 until NumChannels) {\n dut.io.mem_read_sender(i).valid.expect(controllerModel.mem_read_valid(i).B)\n dut.io.mem_read_sender(i).bits.expect(controllerModel.mem_read_address(i).U)\n // dut.io.mem_write_sender(i).valid.expect(controllerModel.mem_write_valid(i).B)\n // if (controllerModel.mem_write_valid(i)) {\n // dut.io.mem_write_sender(i).bits.address.expect(controllerModel.mem_write_address(i).U)\n // dut.io.mem_write_sender(i).bits.data.expect(controllerModel.mem_write_data(i).U)\n // }\n dut.io.mem_write_sender.map(sender => {\n sender(i).valid.expect(controllerModel.mem_write_valid(i).B)\n if (controllerModel.mem_write_valid(i)) {\n sender(i).bits.address.expect(controllerModel.mem_write_address(i).U)\n sender(i).bits.data.expect(controllerModel.mem_write_data(i).U)\n }\n })\n }\n\n cnt += 1\n }\n }\n }\n }\n}\n", "groundtruth": " if (mem_write_ready(i)) {\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "tiny-gpu-chisel", "path": "tiny-gpu-chisel/playground/test/src/CoreSpec.scala", "left_context": "package core\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.BundleLiterals._\nimport chisel3.simulator.EphemeralSimulator._\nimport org.scalatest.freespec.AnyFreeSpec\nimport org.scalatest.matchers.must.Matchers\n\nimport statecode.CoreState\nimport statecode.FetcherState\nimport statecode.LSUState\nimport statecode.RegInputOp\nimport statecode.AluOpCode\n\nclass CoreModel(\n DataMemAddrBits: Int = 8,\n DataMemDataBits: Int = 8,\n ProgramMemAddrBits: Int = 8,\n ProgramMemDataBits: Int = 16,\n ThreadsPerBlock: Int = 4) {\n // State variables matching the Core module's submodules\n var fetcherModel = new fetcher.FetcherModel()\n var decoderModel = new decoder.DecoderModel()\n var schedulerModel = new scheduler.SchedulerModel(ThreadsPerBlock)\n\n // Arrays for per-thread components\n var aluModels = Array.fill(ThreadsPerBlock)(new alu.AluModel())\n var lsuModels = Array.fill(ThreadsPerBlock)(new lsu.LsuModel())\n var regfileModels = Array.fill(ThreadsPerBlock)(new registers.RegModel())\n var pcModels = Array.fill(ThreadsPerBlock)(new pc.PCModel())\n\n class PrevCycleData {\n // Fetcher outputs\n var fetcher_state = FetcherState.IDLE\n var read_valid = false\n var read_address = 0\n var instruction = 0\n // Fetcher end\n\n // Decoder outputs\n var decoded_rd_address = 0\n var decoded_rs_address = 0\n var decoded_rt_address = 0\n var decoded_nzp = 0\n var decoded_immediate = 0\n var decoded_reg_write_enable = false\n var decoded_mem_read_enable = false\n var decoded_mem_write_enable = false\n var decoded_nzp_write_enable = false\n var decoded_reg_input_mux = RegInputOp.ARITHMETIC\n var decoded_alu_arithmetic_mux = AluOpCode.ADD\n var decoded_alu_output_mux = false\n var decoded_pc_mux = false\n var decoded_ret = false\n // Decoder end\n\n // Scheduler outputs\n var current_pc = 0\n var core_state = CoreState.IDLE\n var done = false\n // Scheduler end\n\n // ALU outputs\n var alu_out = Array.fill(ThreadsPerBlock)(0)\n // ALU end\n\n", "right_context": "\n // LSU outputs\n // var lsu_read_valid = Array.fill(ThreadsPerBlock)(false)\n // var lsu_read_address = Array.fill(ThreadsPerBlock)(0)\n // var lsu_write_valid = Array.fill(ThreadsPerBlock)(false)\n // var lsu_write_address = Array.fill(ThreadsPerBlock)(0)\n // var lsu_write_data = Array.fill(ThreadsPerBlock)(0)\n var lsu_state = Array.fill(ThreadsPerBlock)(LSUState.IDLE)\n var lsu_out = Array.fill(ThreadsPerBlock)(0)\n // LSU end\n\n // Register Files outputs\n var regout_rs = Array.fill(ThreadsPerBlock)(0)\n var regout_rt = Array.fill(ThreadsPerBlock)(0)\n // Register end\n\n def save(model: fetcher.FetcherModel) = {\n fetcher_state = model.fetcher_state\n read_valid = model.read_valid\n read_address = model.read_address\n instruction = model.instruction\n }\n\n def save(model: decoder.DecoderModel) = {\n decoded_rd_address = model.decoded_rd_address\n decoded_rs_address = model.decoded_rs_address\n decoded_rt_address = model.decoded_rt_address\n decoded_nzp = model.decoded_nzp\n decoded_immediate = model.decoded_immediate\n decoded_reg_write_enable = model.decoded_reg_write_enable\n decoded_mem_read_enable = model.decoded_mem_read_enable\n decoded_mem_write_enable = model.decoded_mem_write_enable\n decoded_nzp_write_enable = model.decoded_nzp_write_enable\n decoded_reg_input_mux = model.decoded_reg_input_mux\n decoded_alu_arithmetic_mux = model.decoded_alu_arithmetic_mux\n decoded_alu_output_mux = model.decoded_alu_output_mux\n decoded_pc_mux = model.decoded_pc_mux\n decoded_ret = model.decoded_ret\n }\n\n def save(model: scheduler.SchedulerModel) = {\n core_state = model.core_state\n current_pc = model.current_pc\n done = model.done\n }\n\n def save(model: alu.AluModel, idx: Int) = {\n alu_out(idx) = model.alu_out\n }\n\n def save(model: pc.PCModel, idx: Int) = {\n next_pc(idx) = model.next_pc\n }\n\n def save(model: lsu.LsuModel, idx: Int) = {\n // lsu_read_valid(idx) = model.read_valid\n // lsu_read_address(idx) = model.read_address\n // lsu_write_valid(idx) = model.write_valid\n // lsu_write_address(idx) = model.write_address\n // lsu_write_data(idx) = model.write_data\n lsu_state(idx) = model.lsu_state\n lsu_out(idx) = model.output_data\n }\n\n def save(model: registers.RegModel, idx: Int) = {\n regout_rs(idx) = model.rs_out()\n regout_rt(idx) = model.rt_out()\n }\n }\n\n var prevCycleData = new PrevCycleData\n\n // core's 8 outputs\n var done = false\n\n var program_mem_read_address_valid = false\n var program_mem_read_address_bits = 0\n\n var data_mem_read_address_valid = Array.fill(ThreadsPerBlock)(false)\n var data_mem_read_address_bits = Array.fill(ThreadsPerBlock)(0)\n\n var data_mem_write_address_valid = Array.fill(ThreadsPerBlock)(false)\n var data_mem_write_address_bits = Array.fill(ThreadsPerBlock)(0)\n var data_mem_write_data_bits = Array.fill(ThreadsPerBlock)(0)\n\n // debug var\n var cycle = 0\n\n def update(\n // Kernel execution inputs\n start: Boolean,\n block_id: Int,\n thread_count: Int,\n\n // Memory inputs\n program_mem_read_ready: Boolean,\n program_mem_read_data: Int,\n\n // Data Memory signals\n data_mem_read_data: Array[Int],\n data_mem_read_ready: Array[Boolean],\n data_mem_write_ready: Array[Boolean]\n ): Unit = {\n // Update fetcher\n fetcherModel.update(\n core_state = prevCycleData.core_state,\n current_pc = prevCycleData.current_pc,\n mem_read_ready = program_mem_read_ready,\n mem_read_data = program_mem_read_data\n )\n\n // Update decoder\n decoderModel.update(\n core_state = prevCycleData.core_state,\n instruction = prevCycleData.instruction\n )\n\n // Update scheduler\n schedulerModel.update(\n start = start,\n mem_read_enable = prevCycleData.decoded_mem_read_enable,\n mem_write_enable = prevCycleData.decoded_mem_write_enable,\n decoded_ret = prevCycleData.decoded_ret,\n fetcher_state = prevCycleData.fetcher_state,\n lsu_state = prevCycleData.lsu_state,\n next_pc = prevCycleData.next_pc\n )\n\n // Update per-thread components\n for (i <- 0 until ThreadsPerBlock) {\n val enable = i < thread_count\n\n val rd_in = prevCycleData.decoded_rd_address\n val rs_in = prevCycleData.decoded_rs_address\n val rt_in = prevCycleData.decoded_rt_address\n\n // Update ALU\n aluModels(i).update(\n enable = enable,\n core_state = prevCycleData.core_state,\n rs = prevCycleData.regout_rs(i),\n rt = prevCycleData.regout_rt(i),\n arithmetic_mux = prevCycleData.decoded_alu_arithmetic_mux,\n output_mux = prevCycleData.decoded_alu_output_mux\n )\n\n // Update LSU\n lsuModels(i).update(\n enable = enable,\n core_state = prevCycleData.core_state,\n read_enable = prevCycleData.decoded_mem_read_enable,\n write_enable = prevCycleData.decoded_mem_write_enable,\n rs = prevCycleData.regout_rs(i),\n rt = prevCycleData.regout_rt(i),\n mem_read_data = data_mem_read_data(i),\n mem_read_ready = data_mem_read_ready(i),\n mem_write_ready = data_mem_write_ready(i)\n )\n\n // Update Register Files\n regfileModels(i).update(\n enable = enable,\n block_id = block_id,\n core_state = prevCycleData.core_state,\n rs = rs_in,\n rd = rd_in,\n rt = rt_in,\n decoded_reg_write_enable = prevCycleData.decoded_reg_write_enable,\n decoded_reg_input_mux = prevCycleData.decoded_reg_input_mux,\n decoded_immediate = prevCycleData.decoded_immediate,\n alu_out = prevCycleData.alu_out(i),\n lsu_out = prevCycleData.lsu_out(i)\n )\n\n // Update PC\n pcModels(i).update(\n enable = enable,\n core_state = prevCycleData.core_state,\n decoded_nzp = prevCycleData.decoded_nzp,\n decoded_immediate = prevCycleData.decoded_immediate,\n decoded_nzp_write_enable = prevCycleData.decoded_nzp_write_enable,\n decoded_pc_mux = prevCycleData.decoded_pc_mux,\n alu_out = prevCycleData.alu_out(i),\n current_pc = prevCycleData.current_pc\n )\n\n prevCycleData.save(aluModels(i), i)\n prevCycleData.save(lsuModels(i), i)\n prevCycleData.save(regfileModels(i), i)\n prevCycleData.save(pcModels(i), i)\n }\n\n // update outputs\n done = schedulerModel.done\n program_mem_read_address_valid = fetcherModel.read_valid\n program_mem_read_address_bits = fetcherModel.read_address\n\n for (i <- 0 until ThreadsPerBlock) {\n data_mem_read_address_valid(i) = lsuModels(i).read_valid\n data_mem_read_address_bits(i) = lsuModels(i).read_address\n data_mem_write_address_valid(i) = lsuModels(i).write_valid\n data_mem_write_address_bits(i) = lsuModels(i).write_address\n data_mem_write_data_bits(i) = lsuModels(i).write_data\n }\n\n prevCycleData.save(fetcherModel)\n prevCycleData.save(decoderModel)\n prevCycleData.save(schedulerModel)\n\n // print and update debug info\n // println(\n // \"#Model After Cycle: \" + cycle + \", CoreState: \" + prevCycleData.core_state + \", PC: \" + prevCycleData.current_pc + \", Fetcher State: \" + fetcherModel.fetcher_state\n // )\n cycle += 1\n }\n\n // def reset(): Unit = {\n // fetcherModel.reset()\n // decoderModel.reset()\n // schedulerModel.reset()\n // aluModels.foreach(_.reset())\n // lsuModels.foreach(_.reset())\n // regfileModels.foreach(_.reset())\n // pcModels.foreach(_.reset())\n // }\n\n}\n\nclass CoreSpec extends AnyFreeSpec with Matchers {\n \"Test Core\" - {\n \"should match model behavior with random inputs\" in {\n val DataMemAddrBits: Int = 8\n val DataMemDataBits: Int = 8\n val ProgramMemAddrBits: Int = 8\n val ProgramMemDataBits: Int = 16\n val ThreadsPerBlock: Int = 4\n simulate(new Core(DataMemAddrBits, DataMemDataBits, ProgramMemAddrBits, ProgramMemDataBits, ThreadsPerBlock)) {\n dut =>\n dut.reset.poke(true.B)\n dut.clock.step()\n dut.reset.poke(false.B)\n dut.clock.step()\n\n // println(\"########## Start ##########\")\n\n var cnt = 0\n val rng = new scala.util.Random(42) // 42 is the seed for reproducibility\n val coreModel = new CoreModel()\n while (cnt < 10000) {\n val block_id = rng.nextInt(13)\n val thread_count = rng.nextInt(ThreadsPerBlock)\n val mem_read_ready = rng.nextBoolean()\n val mem_read_data = rng.nextInt(256)\n val data_mem_read_data = Array.fill(ThreadsPerBlock)(rng.nextInt(256))\n val data_mem_read_ready = Array.fill(ThreadsPerBlock)(rng.nextBoolean())\n val data_mem_write_ready = Array.fill(ThreadsPerBlock)(rng.nextBoolean())\n\n dut.io.start.poke(true.B)\n dut.io.block_id.poke(block_id.U)\n dut.io.thread_count.poke(thread_count.U)\n\n dut.io.program_mem_read_address_sender.ready.poke(mem_read_ready.B)\n dut.io.program_mem_read_data.poke(mem_read_data.U)\n\n for (i <- 0 until ThreadsPerBlock) {\n dut.io.data_mem_read_data(i).poke(data_mem_read_data(i).U)\n dut.io.data_mem_read_address_sender(i).ready.poke(data_mem_read_ready(i).B)\n dut.io.data_mem_write_sender(i).ready.poke(data_mem_write_ready(i).B)\n }\n\n dut.clock.step()\n\n // println(s\"\\n=== Random Values for Cycle $cnt ===\")\n // println(s\"Block ID: $block_id\")\n // println(s\"Thread Count: $thread_count\")\n // println(s\"Program Memory Read: [ready=$mem_read_ready, data=$mem_read_data]\")\n // println(s\"Read Data: [${data_mem_read_data.mkString(\", \")}]\")\n // println(s\"Read Ready: [${data_mem_read_ready.mkString(\", \")}]\")\n // println(s\"Write Ready: [${data_mem_write_ready.mkString(\", \")}]\")\n // println()\n // println(\"--Aft Core State: \" + dut.io.core_state.peekValue() + \", current_pc: \" + dut.io.current_pc.peek())\n\n coreModel.update(\n start = true,\n block_id = block_id,\n thread_count = thread_count,\n // Memory inputs\n program_mem_read_ready = mem_read_ready,\n program_mem_read_data = mem_read_data,\n // Data Memory signals\n data_mem_read_data = data_mem_read_data,\n data_mem_read_ready = data_mem_read_ready,\n data_mem_write_ready = data_mem_write_ready\n )\n\n // verify all 8 outputs\n dut.io.done.expect(coreModel.done.B)\n dut.io.program_mem_read_address_sender.valid.expect(coreModel.program_mem_read_address_valid.B)\n dut.io.program_mem_read_address_sender.bits.expect(coreModel.program_mem_read_address_bits.U)\n\n for (i <- 0 until ThreadsPerBlock) {\n dut.io.data_mem_read_address_sender(i).valid.expect(coreModel.data_mem_read_address_valid(i).B)\n dut.io.data_mem_read_address_sender(i).bits.expect(coreModel.data_mem_read_address_bits(i).U)\n dut.io.data_mem_write_sender(i).valid.expect(coreModel.data_mem_write_address_valid(i).B)\n dut.io.data_mem_write_sender(i).bits.address.expect(coreModel.data_mem_write_address_bits(i).U)\n dut.io.data_mem_write_sender(i).bits.data.expect(coreModel.data_mem_write_data_bits(i).U)\n }\n\n cnt += 1\n }\n }\n }\n }\n}\n", "groundtruth": " // PC output\n var next_pc = Array.fill(ThreadsPerBlock)(0)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "tiny-gpu-chisel", "path": "tiny-gpu-chisel/playground/test/src/DecoderSpec.scala", "left_context": "package decoder\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.BundleLiterals._\nimport chisel3.simulator.EphemeralSimulator._\nimport org.scalatest.freespec.AnyFreeSpec\nimport org.scalatest.matchers.must.Matchers\n\nimport statecode.CoreState\nimport statecode.AluOpCode\nimport statecode.RegInputOp\n\nclass DecoderModel {\n var decoded_rd_address = 0\n var decoded_rs_address = 0\n var decoded_rt_address = 0\n var decoded_nzp = 0\n var decoded_immediate = 0\n var decoded_reg_write_enable = false\n var decoded_mem_read_enable = false\n var decoded_mem_write_enable = false\n var decoded_nzp_write_enable = false\n var decoded_reg_input_mux = RegInputOp.ARITHMETIC\n var decoded_alu_arithmetic_mux = AluOpCode.ADD\n var decoded_alu_output_mux = false\n var decoded_pc_mux = false\n var decoded_ret = false\n\n def update(\n core_state: CoreState.Type,\n instruction: Int\n ): Unit = {\n if (core_state == CoreState.DECODE) {\n decoded_rd_address = (instruction & 0xf00) >> 8\n decoded_rs_address = (instruction & 0xf0) >> 4\n decoded_rt_address = instruction & 0x000f\n decoded_immediate = instruction & 0x00ff\n decoded_nzp = (instruction & 0xe00) >> 9\n\n // reset\n decoded_reg_write_enable = false\n decoded_mem_read_enable = false\n decoded_mem_write_enable = false\n decoded_nzp_write_enable = false\n decoded_reg_input_mux = RegInputOp.ARITHMETIC\n decoded_alu_arithmetic_mux = AluOpCode.ADD\n decoded_alu_output_mux = false\n decoded_pc_mux = false\n decoded_ret = false\n\n val instruction_opcode = (instruction & 0xf000) >> 12\n instruction_opcode match {\n case 0x0 => {\n // DecoderState.NOP\n }\n case 0x1 => {\n // DecoderState.BRnzp\n decoded_pc_mux = true\n }\n case 0x2 => {\n // DecoderState.CMP\n decoded_alu_output_mux = true\n decoded_nzp_write_enable = true\n }\n case 0x3 => {\n // DecoderState.ADD\n decoded_reg_write_enable = true\n decoded_reg_input_mux = RegInputOp.ARITHMETIC\n decoded_alu_arithmetic_mux = AluOpCode.ADD\n }\n case 0x4 => {\n // DecoderState.SUB\n decoded_reg_write_enable = true\n decoded_reg_input_mux = RegInputOp.ARITHMETIC\n decoded_alu_arithmetic_mux = AluOpCode.SUB\n }\n case 0x5 => {\n // DecoderState.MUL\n decoded_reg_write_enable = true\n decoded_reg_input_mux = RegInputOp.ARITHMETIC\n decoded_alu_arithmetic_mux = AluOpCode.MUL\n }\n case 0x6 => {\n // DecoderState.DIV\n decoded_reg_write_enable = true\n decoded_reg_input_mux = RegInputOp.ARITHMETIC\n decoded_alu_arithmetic_mux = AluOpCode.DIV\n }\n case 0x7 => {\n // DecoderState.LDR\n decoded_reg_write_enable = true\n decoded_reg_input_mux = RegInputOp.MEMORY\n decoded_mem_read_enable = true\n }\n case 0x8 => {\n // DecoderState.STR\n decoded_mem_write_enable = true\n }\n case 0x9 => {\n // DecoderState.CONST\n decoded_reg_write_enable = true\n decoded_reg_input_mux = RegInputOp.CONSTANT\n }\n case 0xf => {\n // DecoderState.RET\n decoded_ret = true\n }\n", "right_context": " }\n }\n\n }\n}\n\nclass DecoderSpec extends AnyFreeSpec with Matchers {\n \"Test decoder\" - {\n \"should match model behavior with random inputs\" in {\n val ProgramMemAddrBits: Int = 8\n val ProgramMemDataBits: Int = 16\n simulate(new Decoder) { dut =>\n dut.reset.poke(true.B)\n dut.clock.step()\n dut.reset.poke(false.B)\n dut.clock.step()\n\n var cnt = 0\n val rng = new scala.util.Random(42) // 42 is the seed for reproducibility\n val decoderModel = new DecoderModel()\n while (cnt < 10000) {\n val core_state = CoreState.DECODE\n val instruction = rng.nextInt(65536) // 2^16 for 16-bit data\n\n // println(\"instruction: \" + f\"${instruction.toBinaryString}%16s\".replace(' ', '0').grouped(4).mkString(\" \"))\n\n dut.io.core_state.poke(core_state)\n dut.io.instruction.poke(instruction.U)\n\n dut.clock.step()\n\n decoderModel.update(core_state, instruction)\n dut.io.decoded_reg_address.rd.expect(decoderModel.decoded_rd_address.U)\n dut.io.decoded_reg_address.rs.expect(decoderModel.decoded_rs_address.U)\n dut.io.decoded_reg_address.rt.expect(decoderModel.decoded_rt_address.U)\n\n dut.io.decoded_nzp.expect(decoderModel.decoded_nzp.U)\n dut.io.decoded_immediate.expect(decoderModel.decoded_immediate.U)\n\n dut.io.mem_rw_enable.read_enable.expect(decoderModel.decoded_mem_read_enable.B)\n dut.io.mem_rw_enable.write_enable.expect(decoderModel.decoded_mem_write_enable.B)\n\n dut.io.decoded_reg_write_enable.expect(decoderModel.decoded_reg_write_enable.B)\n dut.io.decoded_nzp_write_enable.expect(decoderModel.decoded_nzp_write_enable.B)\n assert(dut.io.decoded_reg_input_mux.peekValue().asBigInt == decoderModel.decoded_reg_input_mux.litValue)\n\n assert(\n dut.io.decoded_alu_op.arithmetic_mux\n .peekValue()\n .asBigInt == decoderModel.decoded_alu_arithmetic_mux.litValue\n )\n dut.io.decoded_alu_op.output_mux.expect(decoderModel.decoded_alu_output_mux.B)\n\n dut.io.decoded_pc_mux.expect(decoderModel.decoded_pc_mux.B)\n dut.io.decoded_ret.expect(decoderModel.decoded_ret.B)\n\n cnt += 1\n }\n }\n }\n }\n}\n", "groundtruth": " case _ => {}\n", "crossfile_context": "", "category": "Control Flow Block", "subcategory": "Conditional Control", "confidence": 0.7, "category_reason": "Scala case/match expression"} {"task_id": "tiny-gpu-chisel", "path": "tiny-gpu-chisel/playground/test/src/DispatchSpec.scala", "left_context": "package dispatch\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.BundleLiterals._\nimport chisel3.simulator.EphemeralSimulator._\nimport org.scalatest.freespec.AnyFreeSpec\nimport org.scalatest.matchers.must.Matchers\n\nimport statecode.CoreState\n\nclass DispatchModel(NumCores: Int = 2, ThreadsPerCore: Int = 4) {\n val ThreadCountWidth = log2Ceil(ThreadsPerCore) + 1\n\n var core_start = Array.fill(NumCores)(false)\n var core_reset = Array.fill(NumCores)(true)\n var core_block_id = Array.fill(NumCores)(0)\n var core_thread_count = Array.fill(NumCores)(ThreadsPerCore)\n var done = false\n\n // interal states\n var start_execution = false\n var blocks_done = 0\n var blocks_dispatched = 0\n\n def update(\n start: Boolean,\n thread_count: Int,\n core_done: Array[Boolean]\n ): Unit = {\n if (!start) {\n return\n }\n\n if (!start_execution) {\n start_execution = true\n core_reset.map(_ => true)\n }\n\n val total_blocks = (thread_count + ThreadsPerCore - 1) / ThreadsPerCore\n // println(s\"total_blocks in model: $total_blocks, thread_count = $thread_count, blocks_done = $blocks_done\")\n if (blocks_done == total_blocks) {\n done = true\n }\n\n var run_cnt = 0\n var prev_core_start = core_start.clone()\n for (i <- 0 until NumCores) {\n // println(\n // s\"#i = $i, blocks_dispatched = $blocks_dispatched, total_blocks = $total_blocks, core_reset(i) = ${core_reset(i)}\"\n // )\n if (core_reset(i)) {\n core_reset(i) = false\n\n if (blocks_dispatched < total_blocks) {\n core_start(i) = true\n core_block_id(i) = blocks_dispatched\n core_thread_count(i) = if (blocks_dispatched == total_blocks - 1) {\n thread_count - (blocks_dispatched * ThreadsPerCore)\n", "right_context": " // blocks_dispatched += 1\n run_cnt += 1\n }\n }\n\n // println(s\"#i = $i, core_start(i) = ${prev_core_start(i)}, core_done(i) = ${core_done(i)}\")\n if (prev_core_start(i) && core_done(i)) {\n core_reset(i) = true\n core_start(i) = false\n blocks_done += 1\n }\n }\n blocks_dispatched += run_cnt\n }\n}\n\nclass DispatchSpec extends AnyFreeSpec with Matchers {\n \"Test dispatch\" - {\n \"should match model behavior with random inputs\" in {\n val NumCores: Int = 2\n val ThreadsPerCore: Int = 4\n\n simulate(new Dispatch(NumCores, ThreadsPerCore)) { dut =>\n dut.reset.poke(true.B)\n dut.clock.step()\n dut.reset.poke(false.B)\n dut.clock.step()\n\n var cnt = 0\n val rng = new scala.util.Random(42) // 42 is the seed for reproducibility\n val dispatchModel = new DispatchModel()\n\n while (cnt < 10000) {\n val core_done = Array.fill(NumCores)(rng.nextBoolean())\n val thread_count = rng.nextInt(ThreadsPerCore)\n\n dut.io.start.poke(true.B)\n dut.io.thread_count.poke(thread_count.U)\n for (i <- 0 until NumCores) {\n dut.io.core_done(i).poke(core_done(i).B)\n }\n\n dut.clock.step()\n\n // Update model\n dispatchModel.update(\n start = true,\n thread_count = thread_count,\n core_done = core_done\n )\n\n // Compare model with DUT\n dut.io.done.expect(dispatchModel.done.B)\n for (i <- 0 until NumCores) {\n dut.io.core_start(i).expect(dispatchModel.core_start(i).B)\n dut.io.core_reset(i).expect(dispatchModel.core_reset(i).B)\n dut.io.core_block_id(i).expect(dispatchModel.core_block_id(i).U)\n dut.io.core_thread_count(i).expect(dispatchModel.core_thread_count(i).U)\n }\n\n cnt += 1\n }\n }\n }\n }\n}\n", "groundtruth": " } else { ThreadsPerCore }\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "tiny-gpu-chisel", "path": "tiny-gpu-chisel/playground/test/src/FetcherSpec.scala", "left_context": "package fetcher\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.BundleLiterals._\nimport chisel3.simulator.EphemeralSimulator._\nimport org.scalatest.freespec.AnyFreeSpec\nimport org.scalatest.matchers.must.Matchers\n\nimport statecode.CoreState\nimport statecode.FetcherState\n\nclass FetcherModel {\n var fetcher_state = FetcherState.IDLE\n var read_valid = false\n var read_address = 0\n var instruction = 0\n\n def update(\n core_state: CoreState.Type,\n current_pc: Int,\n mem_read_ready: Boolean,\n mem_read_data: Int\n ) = {\n // State machine logic matching the Fetcher module\n fetcher_state match {\n case FetcherState.IDLE =>\n", "right_context": " instruction = mem_read_data\n read_valid = false\n }\n\n case FetcherState.FETCHED =>\n if (core_state == CoreState.DECODE) {\n fetcher_state = FetcherState.IDLE\n }\n }\n }\n\n def reset(): Unit = {\n fetcher_state = FetcherState.IDLE\n read_valid = false\n read_address = 0\n instruction = 0\n }\n}\n\nclass FetcherSpec extends AnyFreeSpec with Matchers {\n \"Test fetcher\" - {\n \"should match model behavior with random inputs\" in {\n val ProgramMemAddrBits: Int = 8\n val ProgramMemDataBits: Int = 16\n simulate(new Fetcher(ProgramMemAddrBits, ProgramMemDataBits)) { dut =>\n dut.reset.poke(true.B)\n dut.clock.step()\n dut.reset.poke(false.B)\n dut.clock.step()\n\n def randomCoreState(rng: scala.util.Random): CoreState.Type = {\n val v = rng.nextInt(3)\n v match {\n case 0 => CoreState.FETCH\n case 1 => CoreState.DECODE\n case 2 => CoreState.EXECUTE\n }\n }\n\n var cnt = 0\n val rng = new scala.util.Random(42) // 42 is the seed for reproducibility\n val fetcherModel = new FetcherModel()\n\n while (cnt < 10000) {\n val core_state = randomCoreState(rng)\n val current_pc = rng.nextInt(256)\n val mem_read_ready = rng.nextInt(2) == 1\n val mem_read_data = rng.nextInt(65536) // 2^16 for 16-bit data\n\n dut.io.core_state.poke(core_state)\n dut.io.current_pc.poke(current_pc.U)\n dut.io.mem_read_address_sender.ready.poke(mem_read_ready.B)\n dut.io.mem_read_data.poke(mem_read_data.U)\n\n dut.clock.step()\n\n // Update model\n fetcherModel.update(\n core_state = core_state,\n current_pc = current_pc,\n mem_read_ready = mem_read_ready,\n mem_read_data = mem_read_data\n )\n\n // Compare model with DUT\n assert(dut.io.fetcher_state.peekValue().asBigInt == fetcherModel.fetcher_state.litValue)\n dut.io.mem_read_address_sender.valid.expect(fetcherModel.read_valid.B)\n dut.io.mem_read_address_sender.bits.expect(fetcherModel.read_address.U)\n dut.io.instruction.expect(fetcherModel.instruction.U)\n\n cnt += 1\n }\n }\n }\n }\n}\n", "groundtruth": " if (core_state == CoreState.FETCH) {\n fetcher_state = FetcherState.FETCHING\n read_valid = true\n read_address = current_pc\n }\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "tiny-gpu-chisel", "path": "tiny-gpu-chisel/playground/test/src/GCDSpec.scala", "left_context": "// See README.md for license details.\n\npackage gcd\n\nimport chisel3._\nimport chisel3.experimental.BundleLiterals._\nimport chisel3.simulator.EphemeralSimulator._\nimport org.scalatest.freespec.AnyFreeSpec\nimport org.scalatest.matchers.must.Matchers\n\n/** This is a trivial example of how to run this Specification From within sbt use:\n * {{{\n * testOnly gcd.GCDSpec\n * }}}\n * From a terminal shell use:\n * {{{\n * sbt 'testOnly gcd.GCDSpec'\n * }}}\n * Testing from mill:\n * {{{\n * mill %NAME%.test.testOnly gcd.GCDSpec\n * }}}\n */\nclass GCDSpec extends AnyFreeSpec with Matchers {\n \"Gcd should calculate proper greatest common denominator\" in {\n simulate(new DecoupledGcd(16)) { dut =>\n val testValues = for {\n x <- 0 to 10\n y <- 0 to 10\n } yield (x, y)\n val inputSeq = testValues.map { case (x, y) => (new GcdInputBundle(16)).Lit(_.value1 -> x.U, _.value2 -> y.U) }\n val resultSeq = testValues.map { case (x, y) =>\n (new GcdOutputBundle(16)).Lit(_.value1 -> x.U, _.value2 -> y.U, _.gcd -> BigInt(x).gcd(BigInt(y)).U)\n }\n\n dut.reset.poke(true.B)\n dut.clock.step()\n dut.reset.poke(false.B)\n dut.clock.step()\n\n var sent, received, cycles: Int = 0\n while (sent != 100 && received != 100) {\n assert(cycles <= 1000, \"timeout reached\")\n\n if (sent < 100) {\n dut.input.valid.poke(true.B)\n dut.input.bits.value1.poke(testValues(sent)._1.U)\n dut.input.bits.value2.poke(testValues(sent)._2.U)\n if (dut.input.ready.peek().litToBoolean) {\n sent += 1\n }\n }\n\n if (received < 100) {\n dut.output.ready.poke(true.B)\n", "right_context": " dut.clock.step()\n cycles += 1\n }\n }\n }\n}\n", "groundtruth": " if (dut.output.valid.peekValue().asBigInt == 1) {\n dut.output.bits.gcd.expect(BigInt(testValues(received)._1).gcd(testValues(received)._2))\n received += 1\n }\n", "crossfile_context": "", "category": "Monitoring and Checking Logic", "subcategory": "Error Reporting and Logging", "confidence": 0.85, "category_reason": "Chisel expect (golden check)"} {"task_id": "tiny-gpu-chisel", "path": "tiny-gpu-chisel/playground/test/src/GpuSpec.scala", "left_context": "package gpu\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.BundleLiterals._\nimport chisel3.simulator.EphemeralSimulator._\nimport org.scalatest.freespec.AnyFreeSpec\nimport org.scalatest.matchers.must.Matchers\n\nimport core.CoreModel\nimport controller.ControllerModel\nimport dispatch.DispatchModel\nimport scala.collection.mutable.ArrayBuffer\n\nclass GpuModel(\n DataMemAddrBits: Int = 8,\n DataMemDataBits: Int = 8,\n DataMemNumChannels: Int = 4,\n ProgramMemAddrBits: Int = 8,\n ProgramMemDataBits: Int = 16,\n ProgramMemNumChannels: Int = 1,\n NumCores: Int = 2,\n ThreadsPerBlock: Int = 4) {\n // Submodule models\n private var dispatchModel = new DispatchModel(NumCores, ThreadsPerBlock)\n\n // Memory controllers\n private val NumLSUs = NumCores * ThreadsPerBlock\n private var dataMemoryController = new ControllerModel(\n DataMemAddrBits,\n DataMemDataBits,\n NumCores * ThreadsPerBlock,\n DataMemNumChannels\n )\n private var programMemoryController = new ControllerModel(\n ProgramMemAddrBits,\n ProgramMemDataBits,\n NumCores,\n ProgramMemNumChannels\n )\n\n // Core models\n private var coreModels = Array.fill(NumCores)(\n new CoreModel(\n DataMemAddrBits,\n DataMemDataBits,\n ProgramMemAddrBits,\n ProgramMemDataBits,\n ThreadsPerBlock\n )\n )\n\n // Last cycle datas\n // Device Control Register\n var drc_thread_count = 0\n\n // Data memory controller outputs\n var data_consumer_read_ready = Array.fill(NumLSUs)(false)\n var data_consumer_read_data = Array.fill(NumLSUs)(0)\n var data_consumer_write_ready = Array.fill(NumLSUs)(false)\n def save_data_memory_controller(model: controller.ControllerModel) = {\n data_consumer_read_ready = model.consumer_read_ready\n data_consumer_read_data = model.consumer_read_data\n data_consumer_write_ready = model.consumer_write_ready\n }\n\n // Program memory controller without write outputs\n var program_consumer_read_ready = Array.fill(NumCores)(false)\n var program_consumer_read_data = Array.fill(NumCores)(0)\n def save_program_memory_controller(model: controller.ControllerModel) = {\n program_consumer_read_ready = model.consumer_read_ready\n program_consumer_read_data = model.consumer_read_data\n }\n\n // Dispatcher outputs\n var dispatcher_core_start = Array.fill(NumCores)(false)\n var dispatcher_core_block_id = Array.fill(NumCores)(0)\n var dispatcher_core_thread_count = Array.fill(NumCores)(ThreadsPerBlock)\n def save_dispatcher(model: dispatch.DispatchModel) = {\n dispatcher_core_start = model.core_start\n dispatcher_core_block_id = model.core_block_id\n dispatcher_core_thread_count = model.core_thread_count\n }\n\n // Cores outputs 8/8\n var cores_done = Array.fill(NumCores)(false)\n var cores_program_mem_read_address_valid = Array.fill(NumCores)(false)\n var cores_program_mem_read_address_bits = Array.fill(NumCores)(0)\n var cores_data_mem_read_address_valid = Array.fill(NumCores)(Array.fill(ThreadsPerBlock)(false))\n var cores_data_mem_read_address_bits = Array.fill(NumCores)(Array.fill(ThreadsPerBlock)(0))\n var cores_data_mem_write_address_valid = Array.fill(NumCores)(Array.fill(ThreadsPerBlock)(false))\n var cores_data_mem_write_address_bits = Array.fill(NumCores)(Array.fill(ThreadsPerBlock)(0))\n var cores_data_mem_write_data_bits = Array.fill(NumCores)(Array.fill(ThreadsPerBlock)(0))\n def save_core(idx: Int, model: core.CoreModel) = {\n cores_done(idx) = model.done\n cores_program_mem_read_address_valid(idx) = model.program_mem_read_address_valid\n cores_program_mem_read_address_bits(idx) = model.program_mem_read_address_bits\n cores_data_mem_read_address_valid(idx) = model.data_mem_read_address_valid\n cores_data_mem_read_address_bits(idx) = model.data_mem_read_address_bits\n cores_data_mem_write_address_valid(idx) = model.data_mem_write_address_valid\n cores_data_mem_write_address_bits(idx) = model.data_mem_write_address_bits\n cores_data_mem_write_data_bits(idx) = model.data_mem_write_data_bits\n }\n\n // GPU outputs 8/8\n var gpu_done = false\n var gpu_program_mem_read_valid = Array.fill(ProgramMemNumChannels)(false)\n var gpu_program_mem_read_bits = Array.fill(ProgramMemNumChannels)(0)\n var gpu_data_mem_read_valid = Array.fill(DataMemNumChannels)(false)\n var gpu_data_mem_read_bits = Array.fill(DataMemNumChannels)(0)\n var gpu_data_mem_write_valid = Array.fill(DataMemNumChannels)(false)\n var gpu_data_mem_write_address = Array.fill(DataMemNumChannels)(0)\n var gpu_data_mem_write_data = Array.fill(DataMemNumChannels)(0)\n\n def update(\n // Control inputs\n start: Boolean,\n device_control_write_enable: Boolean,\n device_control_data: Int,\n\n // Memory inputs\n program_mem_read_ready: Array[Boolean],\n program_mem_read_data: Array[Int],\n data_mem_read_ready: Array[Boolean],\n data_mem_read_data: Array[Int],\n data_mem_write_ready: Array[Boolean]\n ): Unit = {\n // Update dispatcher\n val core_done = coreModels.map(_.done)\n dispatchModel.update(\n start = start,\n thread_count = drc_thread_count,\n core_done = cores_done\n )\n\n // Update memory controllers\n dataMemoryController.update(\n consumer_read_valid = cores_data_mem_read_address_valid.flatten,\n consumer_read_addr = cores_data_mem_read_address_bits.flatten,\n consumer_write_valid = cores_data_mem_write_address_valid.flatten,\n consumer_write_addr = cores_data_mem_write_address_bits.flatten,\n consumer_write_data = cores_data_mem_write_data_bits.flatten,\n mem_read_ready = data_mem_read_ready,\n mem_read_data = data_mem_read_data,\n mem_write_ready = data_mem_write_ready\n )\n\n programMemoryController.update(\n consumer_read_valid = cores_program_mem_read_address_valid,\n consumer_read_addr = cores_program_mem_read_address_bits,\n consumer_write_valid = Array.fill(NumCores)(false),\n consumer_write_addr = Array.fill(NumCores)(0),\n consumer_write_data = Array.fill(NumCores)(0),\n mem_read_ready = program_mem_read_ready,\n mem_read_data = program_mem_read_data,\n mem_write_ready = Array.fill(DataMemNumChannels)(false)\n )\n\n // Update each core\n for (i <- 0 until NumCores) {\n // Update core model\n coreModels(i).update(\n start = dispatcher_core_start(i),\n block_id = dispatcher_core_block_id(i),\n thread_count = dispatcher_core_thread_count(i),\n program_mem_read_ready = program_consumer_read_ready(i),\n program_mem_read_data = program_consumer_read_data(i),\n data_mem_read_data = data_consumer_read_data.slice(i * ThreadsPerBlock, (i + 1) * ThreadsPerBlock),\n data_mem_read_ready = data_consumer_read_ready.slice(i * ThreadsPerBlock, (i + 1) * ThreadsPerBlock),\n data_mem_write_ready = data_consumer_write_ready.slice(i * ThreadsPerBlock, (i + 1) * ThreadsPerBlock)\n )\n save_core(i, coreModels(i))\n }\n\n // Update outputs\n gpu_done = dispatchModel.done\n gpu_program_mem_read_valid = coreModels.map(_.program_mem_read_address_valid)\n gpu_program_mem_read_bits = coreModels.map(_.program_mem_read_address_bits)\n gpu_data_mem_read_valid = dataMemoryController.mem_read_valid\n gpu_data_mem_read_bits = dataMemoryController.mem_read_address\n gpu_data_mem_write_valid = dataMemoryController.mem_write_valid\n gpu_data_mem_write_address = dataMemoryController.mem_write_address\n gpu_data_mem_write_data = dataMemoryController.mem_write_data\n\n // update internal states\n if (device_control_write_enable) {\n drc_thread_count = device_control_data\n }\n save_program_memory_controller(programMemoryController)\n save_data_memory_controller(dataMemoryController)\n save_dispatcher(dispatchModel)\n }\n}\n\nclass GpuSpec extends AnyFreeSpec with Matchers {\n \"A cycle based GPU tester\" - {\n \"should match model behavior with random inputs\" in {\n val DataMemAddrBits = 8\n val DataMemDataBits = 8\n val DataMemNumChannels = 4\n val ProgramMemAddrBits = 8\n val ProgramMemDataBits = 16\n val ProgramMemNumChannels = 1\n val NumCores = 2\n val ThreadsPerBlock = 4\n\n simulate(\n new Gpu(\n DataMemAddrBits,\n DataMemDataBits,\n DataMemNumChannels,\n ProgramMemAddrBits,\n ProgramMemDataBits,\n ProgramMemNumChannels,\n NumCores,\n ThreadsPerBlock\n )\n ) { dut =>\n // Reset the DUT\n dut.reset.poke(true.B)\n dut.clock.step()\n dut.reset.poke(false.B)\n dut.clock.step()\n\n var cnt = 0\n val rng = new scala.util.Random(42) // 42 is the seed for reproducibility\n val gpuModel = new GpuModel(\n DataMemAddrBits,\n DataMemDataBits,\n DataMemNumChannels,\n ProgramMemAddrBits,\n ProgramMemDataBits,\n ProgramMemNumChannels,\n NumCores,\n ThreadsPerBlock\n )\n\n while (cnt < 10000) {\n // Generate random inputs\n val device_control_data = rng.nextInt(256)\n\n val program_mem_read_ready = Array.fill(ProgramMemNumChannels)(rng.nextBoolean())\n val program_mem_read_data =\n Array.fill(ProgramMemNumChannels)(rng.nextInt(1 << ProgramMemDataBits))\n\n val data_mem_read_ready = Array.fill(DataMemNumChannels)(rng.nextBoolean())\n val data_mem_read_data = Array.fill(DataMemNumChannels)(rng.nextInt(1 << DataMemDataBits))\n val data_mem_write_ready = Array.fill(DataMemNumChannels)(rng.nextBoolean())\n\n // Apply inputs to DUT\n dut.io.start.poke(true.B)\n dut.io.device_control_write_enable.poke(true.B)\n dut.io.device_control_data.poke(device_control_data.U)\n\n for (i <- 0 until ProgramMemNumChannels) {\n dut.io.program_mem_read_sender(i).ready.poke(program_mem_read_ready(i).B)\n dut.io.program_mem_read_data(i).poke(program_mem_read_data(i).U)\n }\n\n for (i <- 0 until DataMemNumChannels) {\n dut.io.data_mem_read_sender(i).ready.poke(data_mem_read_ready(i).B)\n dut.io.data_mem_read_data(i).poke(data_mem_read_data(i).U)\n dut.io.data_mem_write_sender(i).ready.poke(data_mem_write_ready(i).B)\n }\n\n dut.clock.step()\n\n // Update model with same inputs\n gpuModel.update(\n start = true,\n device_control_write_enable = true,\n device_control_data = device_control_data,\n program_mem_read_ready = program_mem_read_ready,\n program_mem_read_data = program_mem_read_data,\n data_mem_read_ready = data_mem_read_ready,\n data_mem_read_data = data_mem_read_data,\n data_mem_write_ready = data_mem_write_ready\n )\n\n // Verify outputs\n dut.io.done.expect(gpuModel.gpu_done.B)\n\n // Verify program memory interface\n for (i <- 0 until ProgramMemNumChannels) {\n dut.io.program_mem_read_sender(i).valid.expect(gpuModel.gpu_program_mem_read_valid(i).B)\n dut.io.program_mem_read_sender(i).bits.expect(gpuModel.gpu_program_mem_read_bits(i).U)\n }\n\n // Verify data memory interface\n for (i <- 0 until DataMemNumChannels) {\n dut.io.data_mem_read_sender(i).valid.expect(gpuModel.gpu_data_mem_read_valid(i).B)\n dut.io.data_mem_read_sender(i).bits.expect(gpuModel.gpu_data_mem_read_bits(i).U)\n dut.io.data_mem_write_sender(i).valid.expect(gpuModel.gpu_data_mem_write_valid(i).B)\n dut.io.data_mem_write_sender(i).bits.address.expect(gpuModel.gpu_data_mem_write_address(i).U)\n dut.io.data_mem_write_sender(i).bits.data.expect(gpuModel.gpu_data_mem_write_data(i).U)\n }\n\n cnt += 1\n }\n }\n }\n }\n}\n\nclass ProgramMemoryMock(program: Seq[Int]) {\n def step(dut: Gpu) = {\n dut.io.program_mem_read_sender.zip(dut.io.program_mem_read_data).foreach { case (sender, reader) =>\n val readValid = sender.valid.peek().litToBoolean\n if (readValid) {\n val addr = sender.bits.peekValue().asBigInt.toInt\n reader.poke(program(addr).U)\n }\n sender.ready.poke(readValid.B)\n }\n }\n}\n\nclass DataMemoryMock(data: Seq[Int], ProgramMemAddrBits: Int = 8) {\n var mem = ArrayBuffer.fill(1 << ProgramMemAddrBits)(0)\n for (i <- 0 until data.length) {\n mem(i) = data(i)\n }\n\n def step(dut: Gpu) = {\n dut.io.data_mem_read_sender.zip(dut.io.data_mem_read_data).foreach { case (sender, reader) =>\n val readValid = sender.valid.peek().litToBoolean\n // Debug print for read interface\n println(\n", "right_context": " )\n if (readValid) {\n val addr = sender.bits.peekValue().asBigInt.toInt\n reader.poke(mem(addr).U)\n }\n sender.ready.poke(readValid.B)\n }\n\n dut.io.data_mem_write_sender.foreach { sender =>\n val writeValid = sender.valid.peek().litToBoolean\n // Debug print for write interface\n println(s\"Write: valid=${writeValid}, addr=${sender.bits.address.peekValue().asBigInt.toInt}\")\n if (writeValid) {\n val addr = sender.bits.address.peekValue().asBigInt.toInt\n val data = sender.bits.data.peekValue().asBigInt.toInt\n mem(addr) = data\n }\n sender.ready.poke(writeValid.B)\n }\n }\n\n def getMemory: ArrayBuffer[Int] = mem\n}\n\nclass GpuBehaviorSpec extends AnyFreeSpec with Matchers {\n \"A behavior based GPU tester\" - {\n \"The final memory state should match GpuVM's data memory\" in {\n val DataMemAddrBits = 8\n val DataMemDataBits = 8\n val DataMemNumChannels = 4\n val ProgramMemAddrBits = 8\n val ProgramMemDataBits = 16\n val ProgramMemNumChannels = 1\n val NumCores = 2\n val ThreadsPerBlock = 4\n\n // val asmFile = sys.env.get(\"GPU_ASM\")\n // if (asmFile.isEmpty) {\n // println(\"Usage: Set the environment variable GPU_ASM to the path of the asm file.\")\n // System.exit(1)\n // }\n // val asm = scala.io.Source.fromFile(asmFile.get).getLines().mkString(\"\\n\")\n val asm = MatAddAsm.src\n\n val lexer = new Lexer()\n val parser = new AsmParser()\n val vm = new GpuVM(NumCores, ThreadsPerBlock, 1 << DataMemAddrBits)\n\n parser.parse(lexer.tokenize(asm))\n\n vm.init(parser.getDataArrays)\n vm.run(parser.getInstructions)\n\n val program_mem = new ProgramMemoryMock(MachineCodeEmitter.emit(asm))\n val data_mem = new DataMemoryMock(parser.getDataArrays.flatten)\n\n simulate(\n new Gpu(\n DataMemAddrBits,\n DataMemDataBits,\n DataMemNumChannels,\n ProgramMemAddrBits,\n ProgramMemDataBits,\n ProgramMemNumChannels,\n NumCores,\n ThreadsPerBlock\n )\n // ,\n // Seq(WriteVcdAnnotation)\n ) { dut =>\n // Reset the DUT\n dut.reset.poke(true.B)\n dut.clock.step()\n dut.reset.poke(false.B)\n // dut.clock.step()\n\n val thread = 8\n dut.io.start.poke(true.B)\n dut.io.device_control_write_enable.poke(true.B)\n dut.io.device_control_data.poke(thread.U)\n println(s\"DUT io.done = ${dut.io.done.peek().litToBoolean}\")\n dut.clock.step()\n\n dut.io.device_control_write_enable.poke(false.B)\n\n println(s\"DUT io.done = ${dut.io.done.peek().litToBoolean}\")\n dut.clock.step()\n println(s\"DUT io.done = ${dut.io.done.peek().litToBoolean}\")\n\n var cnt = 0\n while (!dut.io.done.peek().litToBoolean && cnt < 10) {\n println(\"In while loop\")\n program_mem.step(dut)\n data_mem.step(dut)\n dut.clock.step()\n cnt += 1\n }\n\n data_mem.getMemory.zip(vm.getMemory).zipWithIndex.foreach { case ((a, b), i) =>\n if (a != b) {\n println(s\"Mismatch at index $i: $a != $b\")\n }\n }\n }\n }\n }\n}\n", "groundtruth": " s\"Read: valid=${sender.valid.peek().litToBoolean}, addr=${sender.bits.peekValue().asBigInt.toInt}\"\n", "crossfile_context": "", "category": "Testbench Stimulus and Environment", "subcategory": "Stimulus Generation", "confidence": 0.85, "category_reason": "Chisel test harness (poke/peek/step)"} {"task_id": "tiny-gpu-chisel", "path": "tiny-gpu-chisel/playground/test/src/GpuVM.scala", "left_context": "package gpu\n\nimport scala.collection.mutable.ArrayBuffer\n\n// First, let's define our Token types\nsealed trait Token\nobject Token {\n // Keywords\n case object Thread extends Token\n case object Data extends Token\n// case object Comment extends Token\n // case object Comma extends Token\n case object Const extends Token\n case object Nop extends Token\n case object Brn extends Token\n case object Brz extends Token\n case object Brp extends Token\n case object Cmp extends Token\n case object Add extends Token\n case object Sub extends Token\n case object Mul extends Token\n case object Div extends Token\n case object Ldr extends Token\n case object Str extends Token\n", "right_context": "\n // Special variables\n case object BlockIdx extends Token\n case object BlockDim extends Token\n case object ThreadIdx extends Token\n\n // Values\n case class Number(value: Int) extends Token\n case class Immediate(value: Int) extends Token // Added for #NUMBER format\n case class Register(number: Int) extends Token // Added for Rxx format\n\n case class LabelDef(name: String) extends Token\n case class LabelUse(name: String) extends Token\n\n // For any unrecognized tokens\n case class Invalid(value: String) extends Token\n}\n\nclass Lexer {\n def tokenize(input: String): Vector[Token] = {\n // Split the input into lines and process each line\n val tokens = input\n .replace(\",\", \" \")\n .split(\"\\n\")\n .flatMap { line =>\n // Split each line into parts, handling comments\n val parts = line.split(\";\", 2)\n val codeLine = parts(0).trim\n\n // println(\"*Debug: \" + codeLine)\n\n if (codeLine.isEmpty) Vector.empty\n else {\n // Split the line into words while preserving special characters\n val words = codeLine.split(\"\\\\s+\").filter(_.nonEmpty)\n words.map(tokenizeWord).toVector\n }\n }\n .toVector\n\n // Report any invalid tokens\n val invalidTokens = tokens.collect { case Token.Invalid(value) => value }\n if (invalidTokens.nonEmpty) {\n println(\"Error: Invalid tokens found:\")\n invalidTokens.foreach(token => println(s\" - $token\"))\n Vector.empty\n } else {\n tokens\n }\n }\n\n private def tokenizeWord(word: String): Token = {\n import Token._\n\n word.toLowerCase match {\n case \".thread\" | \".threads\" => Thread\n case \".data\" => Data\n // case \";\" => Comment\n // case \",\" => Comma\n case \"const\" => Const\n case \"nop\" => Nop\n case \"brn\" => Brn\n case \"brz\" => Brz\n case \"brp\" => Brp\n case \"cmp\" => Cmp\n case \"add\" => Add\n case \"sub\" => Sub\n case \"mul\" => Mul\n case \"div\" => Div\n case \"ldr\" => Ldr\n case \"str\" => Str\n case \"ret\" => Ret\n case \"%blockidx\" => BlockIdx\n case \"%blockdim\" => BlockDim\n case \"%threadidx\" => ThreadIdx\n // Handle register numbers (R0-R99)\n case reg if reg.toLowerCase.startsWith(\"r\") =>\n try {\n val number = reg.substring(1).toInt\n if (number >= 0 && number <= 99) Register(reg.substring(1).toInt)\n else Invalid(reg)\n } catch {\n case _: NumberFormatException => Invalid(reg)\n }\n // Handle immediate numbers (#NUMBER)\n case imm if imm.startsWith(\"#\") =>\n try {\n val number = imm.substring(1, imm.length).toInt\n Immediate(number)\n } catch {\n case _: NumberFormatException => Invalid(imm)\n }\n case num if num.matches(\"-?\\\\d+\") => Number(num.toInt)\n case label if label.endsWith(\":\") => LabelDef(label.dropRight(1))\n case use if use.matches(\"^[a-z_]*$\") => LabelUse(use)\n case other => Invalid(other)\n }\n }\n}\n\n// Test the lexer\nobject LexerTest {\n def main(args: Array[String]): Unit = {\n val lexer = new Lexer()\n val input = \"\"\"\n .threads 8\n .data 0 1 2 3 4 5 6 7 ; matrix A (1 x 8)\n .data 0 1 2 3 4 5 6 7 ; matrix B (1 x 8)\n\n MUL R0, %blockIdx, %blockDim\n ADD R0, R0, %threadIdx ; i = blockIdx * blockDim + threadIdx\n\n CONST R1, #0 ; baseA (matrix A base address)\n CONST R2, #8 ; baseB (matrix B base address)\n CONST R3, #16 ; baseC (matrix C base address)\n\n ADD R4, R1, R0 ; addr(A[i]) = baseA + i\n LDR R4, R4 ; load A[i] from global memory\n\n ADD R5, R2, R0 ; addr(B[i]) = baseB + i\n LDR R5, R5 ; load B[i] from global memory\n\n ADD R6, R4, R15 ; C[i] = A[i] + B[i]\n\n ADD R7, R3, R0 ; addr(C[i]) = baseC + i\n STR R7, R6 ; store C[i] in global memory\n\n RET ; end of kernel\n \"\"\"\n\n val tokens = lexer.tokenize(input)\n tokens.foreach(println)\n }\n}\n\nsealed trait RegType\nobject RegType {\n // Keywords\n case class Imm(value: Int) extends RegType\n case class Reg(value: Int) extends RegType\n case class LabelUse(name: String) extends RegType\n // case class BlockIdx() extends RegType\n // case class BlockDim() extends RegType\n // case class ThreadIdx() extends RegType\n}\n\nclass Instruction(op: Token, args: Vector[RegType]) {\n private var _args: Vector[RegType] = args\n def getOp: Token = op\n def getArgs: Vector[RegType] = _args\n def setArgs(args: Vector[RegType]): Unit = {\n _args = args\n }\n}\n\nclass AsmParser() {\n val BlockIdxOffset = 13\n val BlockDimOffset = 14\n val ThreadIdxOffset = 15\n\n private var debug: Boolean = false\n def setDebug(debug: Boolean): Unit = {\n this.debug = debug\n }\n\n private var tokens: Vector[Token] = Vector.empty\n private var threadCount: Int = 0\n private var dataArrays: Vector[Vector[Int]] = Vector.empty\n private var instructions: Vector[Instruction] = Vector.empty\n private var labels: Map[String, Int] = Map.empty\n private var idx: Int = 0\n def peek(): Token = tokens(idx)\n def consume(): Token = {\n val tok = peek()\n idx += 1\n tok\n }\n def lookahead(): Token = tokens(idx + 1)\n def isEof(): Boolean = idx >= tokens.length\n\n def parseReg(reg: Token): RegType = {\n reg match {\n case Token.Register(number) => RegType.Reg(number)\n case Token.BlockIdx => RegType.Reg(BlockIdxOffset)\n case Token.BlockDim => RegType.Reg(BlockDimOffset)\n case Token.ThreadIdx => RegType.Reg(ThreadIdxOffset)\n case _ => throw new IllegalArgumentException(s\"Invalid register expression in token: $reg\")\n }\n }\n\n def parseBinayOp(op: Token): Instruction = {\n try {\n val (r1, r2) = (consume(), consume())\n new Instruction(\n op,\n Vector(parseReg(r1), parseReg(r2))\n )\n } catch {\n case _: NoSuchElementException => throw new IllegalArgumentException(\"Invalid binary operation expression\")\n }\n }\n\n def parseTernaryOp(op: Token): Instruction = {\n try {\n val (r1, r2, r3) = (consume(), consume(), consume())\n new Instruction(\n op,\n Vector(parseReg(r1), parseReg(r2), parseReg(r3))\n )\n } catch {\n case _: NoSuchElementException => throw new IllegalArgumentException(\"Invalid ternary operation expression\")\n }\n }\n\n def parse(tokens: Vector[Token]): Unit = {\n this.tokens = tokens\n while (!isEof()) {\n val tok = consume()\n if (debug) {\n println(s\"*Debug current token: $tok\")\n }\n tok match {\n case Token.Thread => {\n val num = consume()\n assert(num.isInstanceOf[Token.Number], \"Invalid thread count\")\n threadCount = num.asInstanceOf[Token.Number].value\n }\n case Token.Data => {\n var array = Vector.empty[Int]\n while (peek().isInstanceOf[Token.Number]) {\n val n = consume()\n array = array :+ n.asInstanceOf[Token.Number].value\n }\n dataArrays = dataArrays :+ array\n }\n case Token.Const => {\n val reg = consume()\n assert(reg.isInstanceOf[Token.Register], \"Invalid Const expr\")\n val imm = consume()\n assert(imm.isInstanceOf[Token.Immediate], \"Invalid Const expr\")\n\n val (r, i) = (reg.asInstanceOf[Token.Register].number, imm.asInstanceOf[Token.Immediate].value)\n val instruction = new Instruction(Token.Const, Vector(RegType.Reg(r), RegType.Imm(i)))\n instructions = instructions :+ instruction\n }\n case Token.Nop => {\n val instruction = new Instruction(Token.Nop, Vector.empty)\n instructions = instructions :+ instruction\n }\n case Token.Brn => {\n val label = consume()\n assert(label.isInstanceOf[Token.LabelUse], \"Invalid Brn expr\")\n val instruction =\n new Instruction(Token.Brn, Vector(RegType.LabelUse(label.asInstanceOf[Token.LabelUse].name)))\n instructions = instructions :+ instruction\n }\n case Token.Brz => {\n val label = consume()\n assert(label.isInstanceOf[Token.LabelUse], \"Invalid Brz expr\")\n val instruction =\n new Instruction(Token.Brz, Vector(RegType.LabelUse(label.asInstanceOf[Token.LabelUse].name)))\n instructions = instructions :+ instruction\n }\n case Token.Brp => {\n val label = consume()\n assert(label.isInstanceOf[Token.LabelUse], \"Invalid Brp expr\")\n val instruction =\n new Instruction(Token.Brp, Vector(RegType.LabelUse(label.asInstanceOf[Token.LabelUse].name)))\n instructions = instructions :+ instruction\n }\n case Token.LabelDef(name) => {\n labels = labels + (name -> instructions.length)\n }\n case Token.Cmp => {\n instructions = instructions :+ parseBinayOp(Token.Cmp)\n }\n case Token.Add => {\n instructions = instructions :+ parseTernaryOp(Token.Add)\n }\n case Token.Sub => {\n instructions = instructions :+ parseTernaryOp(Token.Sub)\n }\n case Token.Mul => {\n instructions = instructions :+ parseTernaryOp(Token.Mul)\n }\n case Token.Div => {\n instructions = instructions :+ parseTernaryOp(Token.Div)\n }\n case Token.Ldr => {\n instructions = instructions :+ parseBinayOp(Token.Ldr)\n }\n case Token.Str => {\n instructions = instructions :+ parseBinayOp(Token.Str)\n }\n case Token.Ret => {\n instructions = instructions :+ new Instruction(Token.Ret, Vector.empty)\n }\n case other => {\n println(s\"Unrecognized token: $other\")\n }\n }\n }\n\n // post process:\n // Turn labels into immediate values\n instructions\n .filter(inst =>\n inst.getOp == Token.Brn || inst.getOp == Token.Brn || inst.getOp == Token.Brz || inst.getOp == Token.Brp\n )\n .foreach { inst =>\n val label = inst.getArgs.head.asInstanceOf[RegType.LabelUse].name\n val idx = labels(label)\n inst.setArgs(Vector(RegType.Imm(idx)))\n }\n\n }\n\n // Getter methods\n def getThreadCount: Int = threadCount\n def getDataArrays: Seq[Seq[Int]] = dataArrays\n def getInstructions: Seq[Instruction] = instructions\n}\n\nobject MatAddAsm {\n val src = \"\"\"\n .threads 8\n .data 0 1 2 3 4 5 6 7 ; matrix A (1 x 8)\n .data 0 1 2 3 4 5 6 7 ; matrix B (1 x 8)\n\n MUL R0, %blockIdx, %blockDim\n ADD R0, R0, %threadIdx ; i = blockIdx * blockDim + threadIdx\n\n CONST R1, #0 ; baseA (matrix A base address)\n CONST R2, #8 ; baseB (matrix B base address)\n CONST R3, #16 ; baseC (matrix C base address)\n\n ADD R4, R1, R0 ; addr(A[i]) = baseA + i\n LDR R4, R4 ; load A[i] from global memory\n\n ADD R5, R2, R0 ; addr(B[i]) = baseB + i\n LDR R5, R5 ; load B[i] from global memory\n\n ADD R6, R4, R5 ; C[i] = A[i] + B[i]\n\n ADD R7, R3, R0 ; addr(C[i]) = baseC + i\n STR R7, R6 ; store C[i] in global memory\n\n RET ; end of kernel\n \"\"\"\n}\n\nobject MatMulAsm {\n val src = \"\"\"\n .threads 4\n .data 1 2 3 4 ; matrix A (2 x 2)\n .data 1 2 3 4 ; matrix B (2 x 2)\n\n MUL R0, %blockIdx, %blockDim\n ADD R0, R0, %threadIdx ; i = blockIdx * blockDim + threadIdx\n\n CONST R1, #1 ; increment\n CONST R2, #2 ; N (matrix inner dimension)\n CONST R3, #0 ; baseA (matrix A base address)\n CONST R4, #4 ; baseB (matrix B base address)\n CONST R5, #8 ; baseC (matrix C base address)\n\n DIV R6, R0, R2 ; row = i // N\n MUL R7, R6, R2\n SUB R7, R0, R7 ; col = i % N\n\n CONST R8, #0 ; acc = 0\n CONST R9, #0 ; k = 0\n\n LOOP:\n MUL R10, R6, R2\n ADD R10, R10, R9\n ADD R10, R10, R3 ; addr(A[i]) = row * N + k + baseA\n LDR R10, R10 ; load A[i] from global memory\n\n MUL R11, R9, R2\n ADD R11, R11, R7\n ADD R11, R11, R4 ; addr(B[i]) = k * N + col + baseB\n LDR R11, R11 ; load B[i] from global memory\n\n MUL R12, R10, R11\n ADD R8, R8, R12 ; acc = acc + A[i] * B[i]\n\n ADD R9, R9, R1 ; increment k\n\n CMP R9, R2\n BRn LOOP ; loop while k < N\n\n ADD R9, R5, R0 ; addr(C[i]) = baseC + i\n STR R9, R8 ; store C[i] in global memory\n\n RET ; end of kernel\n \"\"\"\n}\n\nobject AsmParserTest1 {\n def main(args: Array[String]): Unit = {\n val lexer = new Lexer()\n val parser = new AsmParser()\n parser.parse(lexer.tokenize(MatAddAsm.src))\n\n println(\"Thread count: \" + parser.getThreadCount)\n println(\"\\nData arrays:\")\n parser.getDataArrays.zipWithIndex.foreach { case (array, i) =>\n println(s\"Array $i: ${array.mkString(\", \")}\")\n }\n }\n}\n\nobject AsmParserTest2 {\n def main(args: Array[String]): Unit = {\n val lexer = new Lexer()\n val tokens = lexer.tokenize(MatMulAsm.src)\n tokens.foreach(println)\n\n val parser = new AsmParser()\n println(\"\\n################## Parse result ##################\\n\")\n\n parser.parse(tokens)\n\n println(\"Thread count: \" + parser.getThreadCount)\n println(\"\\nData arrays:\")\n parser.getDataArrays.zipWithIndex.foreach { case (array, i) =>\n println(s\"Array $i: ${array.mkString(\", \")}\")\n }\n\n parser.getInstructions.zipWithIndex.foreach { case (inst, i) =>\n println(s\"Instruction $i: ${inst.getOp} ${inst.getArgs.mkString(\", \")}\")\n }\n }\n}\n\nclass GpuVM(NumCores: Int = 2, ThreadsPerBlock: Int = 4, MemSize: Int = 256) {\n private var debug: Boolean = false\n def setDebug(debug: Boolean): Unit = {\n this.debug = debug\n }\n\n val NumOfThread = NumCores * ThreadsPerBlock\n\n private var registers: Vector[ArrayBuffer[Int]] = Vector.fill(NumOfThread)(ArrayBuffer.fill(16)(0))\n private var memory: ArrayBuffer[Int] = ArrayBuffer.empty\n\n private var pc: Int = 0\n private var nzp: ArrayBuffer[Seq[Boolean]] = ArrayBuffer.fill(NumOfThread)(Seq.fill(3)(false))\n\n def getRegisters: Vector[ArrayBuffer[Int]] = registers\n def getMemory: ArrayBuffer[Int] = memory\n\n val BlockIdxOffset = 13\n val BlockDimOffset = 14\n val ThreadIdxOffset = 15\n\n def printRegister(threadIdx: Int): Unit = {\n print(s\"Thread $threadIdx registers: [\")\n // registers(threadIdx).map(v => f\"$v%3d\").mkString(\", \")\n print(registers(threadIdx).foldLeft(\"\")((acc, v) => acc + f\"$v%3d, \"))\n println(\"]\")\n }\n\n def printAllRegisters(): Unit = {\n println(\"################## Registers ##################\")\n for (threadIdx <- 0 until NumOfThread) {\n printRegister(threadIdx)\n }\n println()\n }\n\n def printMemory(): Unit = {\n println(\"***************** Memory *****************\")\n memory.grouped(8).foreach(group => println(group.map(n => f\"$n%4d\").mkString(\" \")))\n println()\n }\n\n def init(dataArrays: Seq[Seq[Int]]): Unit = {\n // Initialize blockIdx, blockDim, threadIdx for each thread's register file\n for (blockId <- 0 until NumCores) {\n for (threadId <- 0 until ThreadsPerBlock) {\n val threadIdx = blockId * ThreadsPerBlock + threadId\n registers(threadIdx)(BlockIdxOffset) = blockId\n registers(threadIdx)(BlockDimOffset) = ThreadsPerBlock\n registers(threadIdx)(ThreadIdxOffset) = threadId\n }\n }\n\n // copy data arrays to memory\n memory = ArrayBuffer.fill(MemSize)(0)\n var offset = 0\n for (array <- dataArrays) {\n for (v <- array) {\n memory(offset) = v\n offset += 1\n }\n }\n }\n\n def run(instructions: Seq[Instruction]): Unit = {\n while (pc < instructions.length) {\n val inst = instructions(pc)\n if (debug) {\n println(s\"*Debug current instruction: ${inst.getOp} ${inst.getArgs.mkString(\", \")}\")\n printAllRegisters()\n printMemory()\n println(\"\\n\")\n }\n for (threadIdx <- 0 until NumOfThread) {\n def nextPc(): Int = {\n inst.getOp match {\n case Token.Nop => {\n // do nothing\n }\n case Token.Brn => {\n val labelIdx = inst.getArgs.head.asInstanceOf[RegType.Imm].value\n if (nzp(threadIdx)(0)) {\n return labelIdx\n }\n }\n case Token.Brz => {\n val labelIdx = inst.getArgs.head.asInstanceOf[RegType.Imm].value\n if (nzp(threadIdx)(1)) {\n return labelIdx\n }\n }\n case Token.Brp => {\n val labelIdx = inst.getArgs.head.asInstanceOf[RegType.Imm].value\n if (nzp(threadIdx)(2)) {\n return labelIdx\n }\n }\n case Token.Cmp => {\n val s = inst.getArgs(0).asInstanceOf[RegType.Reg].value\n val t = inst.getArgs(1).asInstanceOf[RegType.Reg].value\n nzp(threadIdx) = Seq(\n registers(threadIdx)(s) < registers(threadIdx)(t), // neg : idx 0\n registers(threadIdx)(s) == registers(threadIdx)(t), // zero: idx 1\n registers(threadIdx)(s) > registers(threadIdx)(t) // pos : idx 2\n )\n }\n case Token.Add => {\n val d = inst.getArgs(0).asInstanceOf[RegType.Reg].value\n val s = inst.getArgs(1).asInstanceOf[RegType.Reg].value\n val t = inst.getArgs(2).asInstanceOf[RegType.Reg].value\n registers(threadIdx)(d) = registers(threadIdx)(s) + registers(threadIdx)(t)\n }\n case Token.Sub => {\n val d = inst.getArgs(0).asInstanceOf[RegType.Reg].value\n val s = inst.getArgs(1).asInstanceOf[RegType.Reg].value\n val t = inst.getArgs(2).asInstanceOf[RegType.Reg].value\n registers(threadIdx)(d) = registers(threadIdx)(s) - registers(threadIdx)(t)\n }\n case Token.Mul => {\n val d = inst.getArgs(0).asInstanceOf[RegType.Reg].value\n val s = inst.getArgs(1).asInstanceOf[RegType.Reg].value\n val t = inst.getArgs(2).asInstanceOf[RegType.Reg].value\n registers(threadIdx)(d) = registers(threadIdx)(s) * registers(threadIdx)(t)\n }\n case Token.Div => {\n val d = inst.getArgs(0).asInstanceOf[RegType.Reg].value\n val s = inst.getArgs(1).asInstanceOf[RegType.Reg].value\n val t = inst.getArgs(2).asInstanceOf[RegType.Reg].value\n registers(threadIdx)(d) = registers(threadIdx)(s) / registers(threadIdx)(t)\n }\n case Token.Ldr => {\n val d = inst.getArgs(0).asInstanceOf[RegType.Reg].value\n val s = inst.getArgs(1).asInstanceOf[RegType.Reg].value\n registers(threadIdx)(d) = memory(registers(threadIdx)(s))\n }\n case Token.Str => {\n val s = inst.getArgs(0).asInstanceOf[RegType.Reg].value\n val t = inst.getArgs(1).asInstanceOf[RegType.Reg].value\n // println(\n // s\"*Debug store: thread=$threadIdx, s=$s, t=$t, registers(threadIdx)(s)=${registers(threadIdx)(s)}, registers(threadIdx)(t)=${registers(threadIdx)(t)}\"\n // )\n memory(registers(threadIdx)(s)) = registers(threadIdx)(t)\n }\n case Token.Const => {\n val (reg, imm) =\n (inst.getArgs.head.asInstanceOf[RegType.Reg].value, inst.getArgs.last.asInstanceOf[RegType.Imm].value)\n registers(threadIdx)(reg) = imm\n }\n case Token.Ret => {\n return instructions.length\n }\n case _ => {\n throw new Exception(s\"Unrecognized instruction: ${inst.getOp}\")\n }\n }\n return pc + 1\n }\n val npc = nextPc()\n // for each instruction, only update pc once\n if (threadIdx == NumOfThread - 1) {\n pc = npc\n }\n if (debug) {\n println(s\"Thread $threadIdx npc: $npc\")\n printRegister(threadIdx)\n println(nzp(threadIdx))\n printMemory()\n println(\"\\n\")\n }\n }\n }\n }\n}\n\nobject GpuVMAddTest {\n def main(args: Array[String]): Unit = {\n val lexer = new Lexer()\n val tokens = lexer.tokenize(MatAddAsm.src)\n val parser = new AsmParser()\n parser.parse(tokens)\n\n println(\"################## MatAddTest ##################\")\n println(\"################## Parse result ##################\")\n parser.getDataArrays.foreach(println)\n\n println(\"################## VM init ##################\")\n val vm = new GpuVM()\n // vm.setDebug(true)\n vm.init(parser.getDataArrays)\n vm.printAllRegisters()\n vm.printMemory()\n\n println(\"################## Run result ##################\")\n vm.run(parser.getInstructions)\n\n vm.printAllRegisters()\n vm.printMemory()\n\n val ref = Seq( 0, 2, 4, 6, 8, 10, 12, 14)\n assert(vm.getMemory.slice(16, 24) == ref)\n println(\"**** GpuVMAddTest PASSED ****\")\n }\n}\n\nobject GpuVMMulTest {\n def main(args: Array[String]): Unit = {\n val lexer = new Lexer()\n val tokens = lexer.tokenize(MatMulAsm.src)\n val parser = new AsmParser()\n parser.parse(tokens)\n\n println(\"################## MatMulTest ##################\")\n println(\"################## Parse result ##################\")\n parser.getDataArrays.foreach(println)\n\n println(\"################## VM init ##################\")\n val vm = new GpuVM()\n // vm.setDebug(true)\n vm.init(parser.getDataArrays)\n vm.printAllRegisters()\n vm.printMemory()\n\n println(\"################## Run result ##################\")\n vm.run(parser.getInstructions)\n\n vm.printAllRegisters()\n vm.printMemory()\n\n \n val ref = Seq( 7, 10 , 15 ,22)\n assert(vm.getMemory.slice(8, 12) == ref)\n println(\"**** GpuVMMulTest PASSED ****\")\n }\n}\n\nclass MachineCodeEmitter() {\n def asmToMachineCode(asm: String): Seq[Int] = {\n val lexer = new Lexer()\n val parser = new AsmParser()\n parser.parse(lexer.tokenize(asm))\n val instructions = parser.getInstructions\n\n var machineCode = Seq.empty[Int]\n for (inst <- instructions) {\n inst.getOp match {\n case Token.Nop => {\n machineCode = machineCode :+ 0\n }\n case Token.Brn => {\n val labelIdx = inst.getArgs.head.asInstanceOf[RegType.Imm].value\n machineCode = machineCode :+ ((1 << 12) | (1 << 11) | labelIdx)\n }\n case Token.Brz => {\n val labelIdx = inst.getArgs.head.asInstanceOf[RegType.Imm].value\n machineCode = machineCode :+ ((1 << 12) | (1 << 10) | labelIdx)\n }\n case Token.Brp => {\n val labelIdx = inst.getArgs.head.asInstanceOf[RegType.Imm].value\n machineCode = machineCode :+ ((1 << 12) | (1 << 9) | labelIdx)\n }\n case Token.Cmp => {\n val s = inst.getArgs(0).asInstanceOf[RegType.Reg].value\n val t = inst.getArgs(1).asInstanceOf[RegType.Reg].value\n machineCode = machineCode :+ ((1 << 13) | (s << 4) | t)\n }\n case Token.Add => {\n val d = inst.getArgs(0).asInstanceOf[RegType.Reg].value\n val s = inst.getArgs(1).asInstanceOf[RegType.Reg].value\n val t = inst.getArgs(2).asInstanceOf[RegType.Reg].value\n machineCode = machineCode :+ ((3 << 12) | (d << 8) | (s << 4) | t)\n }\n case Token.Sub => {\n val d = inst.getArgs(0).asInstanceOf[RegType.Reg].value\n val s = inst.getArgs(1).asInstanceOf[RegType.Reg].value\n val t = inst.getArgs(2).asInstanceOf[RegType.Reg].value\n machineCode = machineCode :+ ((4 << 12) | (d << 8) | (s << 4) | t)\n }\n case Token.Mul => {\n val d = inst.getArgs(0).asInstanceOf[RegType.Reg].value\n val s = inst.getArgs(1).asInstanceOf[RegType.Reg].value\n val t = inst.getArgs(2).asInstanceOf[RegType.Reg].value\n machineCode = machineCode :+ ((5 << 12) | (d << 8) | (s << 4) | t)\n }\n case Token.Div => {\n val d = inst.getArgs(0).asInstanceOf[RegType.Reg].value\n val s = inst.getArgs(1).asInstanceOf[RegType.Reg].value\n val t = inst.getArgs(2).asInstanceOf[RegType.Reg].value\n machineCode = machineCode :+ ((6 << 12) | (d << 8) | (s << 4) | t)\n }\n case Token.Ldr => {\n val d = inst.getArgs(0).asInstanceOf[RegType.Reg].value\n val s = inst.getArgs(1).asInstanceOf[RegType.Reg].value\n machineCode = machineCode :+ ((7 << 12) | (d << 8) | (s << 4))\n }\n case Token.Str => {\n val s = inst.getArgs(0).asInstanceOf[RegType.Reg].value\n val t = inst.getArgs(1).asInstanceOf[RegType.Reg].value\n machineCode = machineCode :+ ((8 << 12) | (s << 4) | t)\n }\n case Token.Const => {\n val (reg, imm) =\n (inst.getArgs.head.asInstanceOf[RegType.Reg].value, inst.getArgs.last.asInstanceOf[RegType.Imm].value)\n machineCode = machineCode :+ ((9 << 12) | (reg << 8) | imm)\n }\n case Token.Ret => {\n machineCode = machineCode :+ ((0xf << 12))\n }\n case _ => {\n // throw new Exception(s\"Unrecognized instruction: ${inst.getOp}\")\n }\n }\n }\n\n machineCode\n }\n}\n\nobject MachineCodeEmitterTest {\n def main(args: Array[String]): Unit = {\n def verify(src: Seq[Int], ref: Seq[Int]): Boolean = {\n if (src.length != ref.length) {\n println(s\"src.length != ref.length: ${src.length} != ${ref.length}\")\n return false\n }\n for (i <- 0 until src.length) {\n if (src(i) != ref(i)) {\n println(s\"src($i) != ref($i): ${MachineCodeEmitter.toBinary(src(i))} != ${MachineCodeEmitter.toBinary(ref(i))}\")\n return false\n }\n }\n return true\n }\n\n println(\"Testing MatAddAsm:\")\n val machineCode = new MachineCodeEmitter()\n val addMC = machineCode.asmToMachineCode(MatAddAsm.src)\n addMC.zipWithIndex.foreach { case (ins, idx) => println(f\"$idx: ${MachineCodeEmitter.toBinary(ins)}\") }\n\n val addProgram = Seq( \n 0b0101000011011110,\n 0b0011000000001111,\n 0b1001000100000000,\n 0b1001001000001000,\n 0b1001001100010000,\n 0b0011010000010000,\n 0b0111010001000000,\n 0b0011010100100000,\n 0b0111010101010000,\n 0b0011011001000101,\n 0b0011011100110000,\n 0b1000000001110110,\n 0b1111000000000000\n )\n\n assert(verify(addMC, addProgram))\n println(\"**** MachineCodeEmitter MatAddTest PASSED ****\")\n\n println(\"\\n\\nTesting MatMulAsm:\")\n val mulMC = machineCode.asmToMachineCode(MatMulAsm.src)\n mulMC.zipWithIndex.foreach { case (ins, idx) => println(f\"$idx: ${MachineCodeEmitter.toBinary(ins)}\") }\n\n val mulProgram = Seq(\n 0b0101000011011110, \n 0b0011000000001111, \n 0b1001000100000001, \n 0b1001001000000010, \n 0b1001001100000000, \n 0b1001010000000100, \n 0b1001010100001000, \n 0b0110011000000010, \n 0b0101011101100010, \n 0b0100011100000111, \n 0b1001100000000000, \n 0b1001100100000000, \n 0b0101101001100010, \n 0b0011101010101001, \n 0b0011101010100011, \n 0b0111101010100000, \n 0b0101101110010010, \n 0b0011101110110111, \n 0b0011101110110100, \n 0b0111101110110000, \n 0b0101110010101011, \n 0b0011100010001100, \n 0b0011100110010001, \n 0b0010000010010010, \n 0b0001100000001100, \n 0b0011100101010000, \n 0b1000000010011000, \n 0b1111000000000000\n )\n assert(verify(mulMC, mulProgram))\n println(\"**** MachineCodeEmitter MatMulTest PASSED ****\") \n }\n}\n\nobject MachineCodeEmitter {\n def toBinary(ins: Int): String = {\n def toDigit4(i: Int) =\n String.format(\"%4s\", i.toBinaryString).replace(' ', '0')\n\n val (p1, p2, p3, p4) = (\n toDigit4((ins & 0xf000) >> 12),\n toDigit4((ins & 0x0f00) >> 8),\n toDigit4((ins & 0x00f0) >> 4),\n toDigit4((ins & 0x000f))\n )\n\n f\"$p1 $p2 $p3 $p4\"\n }\n\n def emit(asm: String): Seq[Int] = {\n val lexer = new Lexer()\n val parser = new AsmParser()\n parser.parse(lexer.tokenize(asm))\n \n val emitter = new MachineCodeEmitter()\n val machineCode = emitter.asmToMachineCode(asm)\n machineCode\n }\n\n def main(args: Array[String]): Unit = {\n if (args.length < 1 || args(0).isEmpty) {\n println(\"Usage: Tiny-GPU MachineCodeEmitter [--idx: Print instructions with index]\")\n return\n }\n\n val asmFile = args(0)\n val withIndex = args.length > 1 && args(1) == \"--idx\"\n\n // Read the ASM file\n val asm = scala.io.Source.fromFile(asmFile).getLines().mkString(\"\\n\")\n \n // Emit machine code\n val machineCode = emit(asm)\n\n // Print the machine code in binary format\n if (withIndex) {\n machineCode.zipWithIndex.foreach { case (ins, idx) => \n println(f\"$idx%4d: ${toBinary(ins)}\") \n }\n } else {\n machineCode.foreach(ins => println(MachineCodeEmitter.toBinary(ins)))\n }\n }\n}\n", "groundtruth": " case object Ret extends Token\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"} {"task_id": "tiny-gpu-chisel", "path": "tiny-gpu-chisel/playground/test/src/LsuSpec.scala", "left_context": "package lsu\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.BundleLiterals._\nimport chisel3.simulator.EphemeralSimulator._\nimport org.scalatest.freespec.AnyFreeSpec\nimport org.scalatest.matchers.must.Matchers\n\nimport statecode.CoreState\nimport statecode.LSUState\n\nclass LsuModel {\n var lsu_state = LSUState.IDLE\n var output_data = 0\n var read_valid = false\n var read_address = 0\n var write_valid = false\n var write_address = 0\n var write_data = 0\n\n def update(\n enable: Boolean,\n core_state: CoreState.Type,\n read_enable: Boolean,\n write_enable: Boolean,\n rs: Int,\n rt: Int,\n mem_read_data: Int,\n mem_read_ready: Boolean,\n mem_write_ready: Boolean\n ) = {\n if (enable) {\n if (read_enable) {\n lsu_state match {\n case LSUState.IDLE =>\n if (core_state == CoreState.REQUEST) {\n lsu_state = LSUState.REQUESTING\n }\n case LSUState.REQUESTING =>\n read_valid = true\n read_address = rs\n lsu_state = LSUState.WAITING\n case LSUState.WAITING =>\n if (mem_read_ready) {\n read_valid = false\n output_data = mem_read_data\n lsu_state = LSUState.DONE\n }\n case LSUState.DONE =>\n if (core_state == CoreState.UPDATE) {\n lsu_state = LSUState.IDLE\n }\n }\n }\n\n if (write_enable) {\n lsu_state match {\n case LSUState.IDLE =>\n if (core_state == CoreState.REQUEST) {\n lsu_state = LSUState.REQUESTING\n }\n case LSUState.REQUESTING =>\n write_valid = true\n write_address = rs\n write_data = rt\n lsu_state = LSUState.WAITING\n case LSUState.WAITING =>\n if (mem_write_ready) {\n write_valid = false\n lsu_state = LSUState.DONE\n }\n case LSUState.DONE =>\n if (core_state == CoreState.UPDATE) {\n lsu_state = LSUState.IDLE\n }\n }\n }\n }\n }\n}\n\nclass LsuSpec extends AnyFreeSpec with Matchers {\n \"Test Load/Store Unit\" - {\n \"should match model behavior with random inputs\" in {\n simulate(new MemLoadStoreUnit) { dut =>\n dut.reset.poke(true.B)\n dut.clock.step()\n dut.reset.poke(false.B)\n dut.clock.step()\n\n def randomCoreState(rng: scala.util.Random): CoreState.Type = {\n val v = rng.nextInt(2)\n v match {\n case 0 => CoreState.REQUEST\n case 1 => CoreState.UPDATE\n }\n }\n\n var cnt = 0\n val rng = new scala.util.Random(42) // 42 is the seed for reproducibility\n val lsuModel = new LsuModel()\n\n while (cnt < 10000) {\n val enable = rng.nextBoolean()\n val core_state = randomCoreState(rng)\n val read_enable = rng.nextBoolean()\n", "right_context": " val rs = rng.nextInt(256)\n val rt = rng.nextInt(256)\n val mem_read_data = rng.nextInt(256)\n val mem_read_ready = rng.nextBoolean()\n val mem_write_ready = rng.nextBoolean()\n\n dut.io.enable.poke(enable.B)\n dut.io.core_state.poke(core_state)\n dut.io.mem_rw_enable.read_enable.poke(read_enable.B)\n dut.io.mem_rw_enable.write_enable.poke(write_enable.B)\n dut.io.reg_in.rs.poke(rs.U)\n dut.io.reg_in.rt.poke(rt.U)\n dut.io.mem_read_data.poke(mem_read_data.U)\n dut.io.mem_read_address_sender.ready.poke(mem_read_ready.B)\n dut.io.mem_write_sender.ready.poke(mem_write_ready.B)\n\n dut.clock.step()\n\n lsuModel.update(\n enable = enable,\n core_state = core_state,\n read_enable = read_enable,\n write_enable = write_enable,\n rs = rs,\n rt = rt,\n mem_read_data = mem_read_data,\n mem_read_ready = mem_read_ready,\n mem_write_ready = mem_write_ready\n )\n\n // dut.io.lsu_state.expect(LSUState.IDLE)\n assert(dut.io.lsu_state.peekValue().asBigInt == lsuModel.lsu_state.litValue)\n dut.io.lsu_out.expect(lsuModel.output_data.U)\n dut.io.mem_read_address_sender.valid.expect(lsuModel.read_valid.B)\n if (lsuModel.read_valid) {\n dut.io.mem_read_address_sender.bits.expect(lsuModel.read_address.U)\n }\n dut.io.mem_write_sender.valid.expect(lsuModel.write_valid.B)\n if (lsuModel.write_valid) {\n dut.io.mem_write_sender.bits.address.expect(lsuModel.write_address.U)\n dut.io.mem_write_sender.bits.data.expect(lsuModel.write_data.U)\n }\n\n cnt += 1\n }\n }\n }\n }\n}\n", "groundtruth": " val write_enable = if (read_enable) false else rng.nextBoolean() // Ensure not both enabled\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.6, "category_reason": "val binding"} {"task_id": "tiny-gpu-chisel", "path": "tiny-gpu-chisel/playground/test/src/PCSpec.scala", "left_context": "package pc\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.BundleLiterals._\nimport chisel3.simulator.EphemeralSimulator._\nimport org.scalatest.freespec.AnyFreeSpec\nimport org.scalatest.matchers.must.Matchers\n\nimport statecode.CoreState\n\nclass PCModel(DataMemWidth: Int = 8, MemAddrWidth: Int = 8) {\n var nzp = 0\n var next_pc = 0\n val max_pc = 1 << MemAddrWidth\n\n def update(\n enable: Boolean,\n core_state: CoreState.Type,\n decoded_nzp: Int,\n decoded_immediate: Int,\n decoded_nzp_write_enable: Boolean,\n decoded_pc_mux: Boolean,\n alu_out: Int,\n current_pc: Int\n ) = {\n if (enable) {\n // Execute state logic\n if (core_state == CoreState.EXECUTE) {\n if (decoded_pc_mux) {\n if ((nzp & decoded_nzp) != 0) {\n // Branch taken\n next_pc = decoded_immediate\n } else {\n // Branch not taken\n next_pc = (current_pc + 1) % max_pc\n }\n } else {\n // Normal PC increment\n next_pc = (current_pc + 1) % max_pc\n }\n }\n\n // Update state logic\n if (core_state == CoreState.UPDATE) {\n if (decoded_nzp_write_enable) {\n // Update NZP register from ALU output\n nzp = alu_out & 0x7 // Take only lowest 3 bits\n }\n }\n }\n }\n\n def reset(): Unit = {\n nzp = 0\n next_pc = 0\n }\n\n // Getter for testing\n", "right_context": "}\n\nclass PCSpec extends AnyFreeSpec with Matchers {\n \"Test Program Counter\" in {\n val DataMemWidth: Int = 8\n val MemAddrWidth: Int = 8\n simulate(new ProgramCounter(DataMemWidth, MemAddrWidth)) { dut =>\n dut.reset.poke(true.B)\n dut.clock.step()\n dut.reset.poke(false.B)\n dut.clock.step()\n\n def randomCoreState(rng: scala.util.Random): CoreState.Type = {\n val v = rng.nextInt(2)\n v match {\n case 0 => CoreState.EXECUTE\n case 1 => CoreState.UPDATE\n }\n }\n\n dut.io.enable.poke(true.B)\n\n var cnt = 0\n val rng = new scala.util.Random(42) // 42 is the seed for reproducibility\n val pcModel = new PCModel()\n while (cnt < 10000) {\n val core_state = randomCoreState(rng)\n val decoded_nzp = rng.nextInt(4)\n val decoded_immediate = rng.nextInt(256)\n val decoded_nzp_write_enable = rng.nextInt(2) == 1\n val decoded_pc_mux = rng.nextInt(2) == 1\n val alu_out = rng.nextInt(256)\n val current_pc = rng.nextInt(256)\n\n dut.io.core_state.poke(core_state)\n dut.io.decoded_nzp.poke(decoded_nzp.U)\n dut.io.decoded_immediate.poke(decoded_immediate.U)\n dut.io.decoded_nzp_write_enable.poke(decoded_nzp_write_enable.B)\n dut.io.decoded_pc_mux.poke(decoded_pc_mux.B)\n dut.io.alu_out.poke(alu_out.U)\n dut.io.current_pc.poke(current_pc.U)\n\n dut.clock.step()\n\n pcModel\n .update(\n enable = true,\n core_state = core_state,\n decoded_nzp = decoded_nzp,\n decoded_immediate = decoded_immediate,\n decoded_nzp_write_enable = decoded_nzp_write_enable,\n decoded_pc_mux = decoded_pc_mux,\n alu_out = alu_out,\n current_pc = current_pc\n )\n\n dut.io.next_pc.expect(\n pcModel.next_pc.U\n )\n\n cnt += 1\n }\n }\n }\n}\n", "groundtruth": " def getNzp: Int = nzp\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "tiny-gpu-chisel", "path": "tiny-gpu-chisel/playground/test/src/RegFileSpec.scala", "left_context": "package registers\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.BundleLiterals._\nimport chisel3.simulator.EphemeralSimulator._\nimport org.scalatest.freespec.AnyFreeSpec\nimport org.scalatest.matchers.must.Matchers\n\nimport statecode.RegInputOp\nimport statecode.CoreState\n\nimport scala.collection.mutable.ArrayBuffer\n\nclass RegModel {\n var registers = ArrayBuffer.fill(16)(0)\n var rs_in = 0\n var rt_in = 0\n\n def rs_out(): Int = {\n registers(rs_in)\n }\n\n def rt_out(): Int = {\n registers(rt_in)\n }\n\n", "right_context": " decoded_reg_write_enable: Boolean,\n decoded_reg_input_mux: RegInputOp.Type,\n decoded_immediate: Int,\n alu_out: Int,\n lsu_out: Int\n ): Unit = {\n if (enable) {\n registers(13) = block_id\n if (core_state == CoreState.REQUEST) {\n rs_in = rs\n rt_in = rt\n } else if (decoded_reg_write_enable && rd < 13) {\n val data = decoded_reg_input_mux match {\n case RegInputOp.ARITHMETIC => alu_out\n case RegInputOp.MEMORY => lsu_out\n case RegInputOp.CONSTANT => decoded_immediate\n }\n registers(rd) = data\n }\n }\n }\n}\n\nclass RegFileSpec extends AnyFreeSpec with Matchers {\n \"Test load/store for RegisterFiles\" in {\n val threadsPerBlk = 4\n val threadId = 0\n val dataBits = 8\n simulate(new RegisterFiles(threadsPerBlk, threadId, dataBits)) { dut =>\n dut.reset.poke(true.B)\n dut.clock.step()\n dut.reset.poke(false.B)\n dut.clock.step()\n\n dut.io.enable.poke(true.B)\n\n // test reg14 and reg15 defualt values\n dut.io.core_state.poke(CoreState.REQUEST)\n dut.io.decoded_reg_address.rs.poke(14.U)\n dut.io.decoded_reg_address.rt.poke(15.U)\n dut.clock.step()\n dut.io.reg_out.rs.expect(threadsPerBlk.U)\n dut.io.reg_out.rt.expect(threadId.U)\n\n // helper functions\n def randomRegOp(rng: scala.util.Random): RegInputOp.Type = {\n val v = rng.nextInt(3)\n v match {\n case 0 => RegInputOp.ARITHMETIC\n case 1 => RegInputOp.MEMORY\n case 2 => RegInputOp.CONSTANT\n }\n }\n\n def randomCoreState(rng: scala.util.Random): CoreState.Type = {\n val v = rng.nextInt(2)\n v match {\n case 0 => CoreState.REQUEST\n case 1 => CoreState.UPDATE\n }\n }\n\n // Initialize register model\n val regModel = new RegModel()\n\n val times = 100\n val rng = new scala.util.Random(42) // 42 is the seed for reproducibility\n for (i <- 0 until times) {\n // Generate test sequence\n val block_id = rng.nextInt(256)\n val rd_in = rng.nextInt(12)\n val rs_in = rng.nextInt(12)\n val rt_in = rng.nextInt(12)\n val op = randomRegOp(rng)\n val core_state = randomCoreState(rng)\n val alu_out = rng.nextInt(256)\n val lsu_out = rng.nextInt(256)\n val immediate = rng.nextInt(256)\n\n dut.io.core_state.poke(core_state)\n val is_write = core_state == CoreState.UPDATE\n dut.io.decoded_reg_write_enable.poke(is_write.B)\n\n dut.io.decoded_reg_address.rd.poke(rd_in.U)\n dut.io.decoded_reg_address.rs.poke(rs_in.U)\n dut.io.decoded_reg_address.rt.poke(rt_in.U)\n\n dut.io.decoded_reg_input_mux.poke(op)\n dut.io.decoded_immediate.poke(immediate.U)\n dut.io.alu_out.poke(alu_out.U)\n dut.io.lsu_out.poke(lsu_out.U)\n\n // Update model\n regModel.update(\n enable = true,\n block_id = block_id,\n core_state = core_state,\n rd = rd_in,\n rs = rs_in,\n rt = rt_in,\n decoded_reg_write_enable = is_write,\n decoded_reg_input_mux = op,\n decoded_immediate = immediate,\n alu_out = alu_out,\n lsu_out = lsu_out\n )\n\n dut.clock.step()\n // println(\n // s\"rd_in: $rd_in, rs_in: $rs_in, rt_in: $rt_in, op: $op, core_state: $core_state, immediate: $immediate, alu_out: $alu_out, lsu_out: $lsu_out\"\n // )\n // println(s\"regModel after 1 cycle: ${regModel.registers}\")\n\n if (core_state == CoreState.REQUEST) {\n dut.io.reg_out.rs.expect(regModel.rs_out().U)\n dut.io.reg_out.rt.expect(regModel.rt_out().U)\n }\n }\n }\n }\n}\n", "groundtruth": " def update(\n enable: Boolean,\n block_id: Int,\n core_state: CoreState.Type,\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Function and Procedure Signature", "confidence": 0.8, "category_reason": "Method definition"} {"task_id": "tiny-gpu-chisel", "path": "tiny-gpu-chisel/playground/test/src/SchdulerSpec.scala", "left_context": "package scheduler\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.BundleLiterals._\nimport chisel3.simulator.EphemeralSimulator._\nimport org.scalatest.freespec.AnyFreeSpec\nimport org.scalatest.matchers.must.Matchers\n\nimport statecode.CoreState\nimport statecode.LSUState\nimport statecode.FetcherState\n\nclass SchedulerModel(ThreadsPerBlock: Int = 4) {\n var current_pc = 0\n var core_state = CoreState.IDLE\n var done = false\n\n def update(\n start: Boolean,\n mem_read_enable: Boolean,\n mem_write_enable: Boolean,\n decoded_ret: Boolean,\n fetcher_state: FetcherState.Type,\n lsu_state: Array[LSUState.Type],\n next_pc: Array[Int]\n ): Unit = {\n // State machine logic matching the Scheduler module\n core_state match {\n case CoreState.IDLE =>\n if (start) {\n core_state = CoreState.FETCH\n }\n\n case CoreState.FETCH =>\n if (fetcher_state == FetcherState.FETCHED) {\n core_state = CoreState.DECODE\n }\n\n case CoreState.DECODE =>\n core_state = CoreState.REQUEST\n\n case CoreState.REQUEST =>\n core_state = CoreState.WAIT\n\n case CoreState.WAIT =>\n // Check if any LSU is waiting or requesting\n val any_lsu_waiting = lsu_state.exists(state => state == LSUState.WAITING || state == LSUState.REQUESTING)\n if (!any_lsu_waiting) {\n core_state = CoreState.EXECUTE\n }\n\n case CoreState.EXECUTE =>\n core_state = CoreState.UPDATE\n\n case CoreState.UPDATE =>\n if (decoded_ret) {\n done = true\n", "right_context": " case CoreState.DONE =>\n // Stay in DONE state\n }\n }\n}\n\nclass SchedulerSpec extends AnyFreeSpec with Matchers {\n \"Test scheduler\" - {\n \"should match model behavior with random inputs\" in {\n val ThreadsPerBlock: Int = 4\n simulate(new Scheduler(ThreadsPerBlock)) { dut =>\n dut.reset.poke(true.B)\n dut.clock.step()\n dut.reset.poke(false.B)\n dut.clock.step()\n\n var cnt = 0\n val rng = new scala.util.Random(42) // 42 is the seed for reproducibility\n val schedulerModel = new SchedulerModel(ThreadsPerBlock)\n\n def randomLsuState(rng: scala.util.Random): LSUState.Type = {\n val v = rng.nextInt(4)\n v match {\n case 0 => LSUState.IDLE\n case 1 => LSUState.REQUESTING\n case 2 => LSUState.WAITING\n case 3 => LSUState.DONE\n }\n }\n\n while (cnt < 10000) {\n // Generate random inputs\n val start = rng.nextBoolean()\n val mem_read_enable = rng.nextBoolean()\n val mem_write_enable = rng.nextBoolean()\n val decoded_ret = rng.nextBoolean()\n val (fetcher_state, _) = FetcherState.safe(rng.nextInt(3).U) // Assuming 3 states: IDLE, FETCHING, FETCHED\n val lsu_state = Array.fill(ThreadsPerBlock)(randomLsuState(rng)) // Assuming 4 states in LSUState\n val next_pc = Array.fill(ThreadsPerBlock)(rng.nextInt(256)) // 8-bit PC values\n\n // Poke inputs\n dut.io.start.poke(start.B)\n dut.io.mem_rw_enable.read_enable.poke(mem_read_enable.B)\n dut.io.mem_rw_enable.write_enable.poke(mem_write_enable.B)\n dut.io.decoded_ret.poke(decoded_ret.B)\n dut.io.fetcher_state.poke(fetcher_state)\n for (i <- 0 until ThreadsPerBlock) {\n dut.io.lsu_state(i).poke(lsu_state(i))\n dut.io.next_pc(i).poke(next_pc(i).U)\n }\n\n dut.clock.step()\n\n // Update model\n schedulerModel.update(\n start = start,\n mem_read_enable = mem_read_enable,\n mem_write_enable = mem_write_enable,\n decoded_ret = decoded_ret,\n fetcher_state = fetcher_state,\n lsu_state = lsu_state,\n next_pc = next_pc\n )\n\n // Compare model with DUT\n dut.io.current_pc.expect(schedulerModel.current_pc.U)\n assert(dut.io.core_state.peekValue().asBigInt == schedulerModel.core_state.litValue)\n dut.io.done.expect(schedulerModel.done.B)\n\n cnt += 1\n }\n }\n }\n }\n}\n", "groundtruth": " core_state = CoreState.DONE\n } else {\n // Use the last thread's next_pc (same as in module)\n current_pc = next_pc(ThreadsPerBlock - 1)\n", "crossfile_context": "", "category": "Declaration and Definition", "subcategory": "Signal and Wire Declaration", "confidence": 0.5, "category_reason": "General declaration"}